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-rw-r--r--packages/linux/linux-omap2-git/beagleboard/TWL4030-05.patch208
1 files changed, 118 insertions, 90 deletions
diff --git a/packages/linux/linux-omap2-git/beagleboard/TWL4030-05.patch b/packages/linux/linux-omap2-git/beagleboard/TWL4030-05.patch
index b41c836711..02a72ed9df 100644
--- a/packages/linux/linux-omap2-git/beagleboard/TWL4030-05.patch
+++ b/packages/linux/linux-omap2-git/beagleboard/TWL4030-05.patch
@@ -1,68 +1,54 @@
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-MBOX-Line: From nobody Thu Jul 17 19:34:52 2008
-From: Paul Walmsley <paul@pwsan.com>
-Subject: [PATCH 5/9] TWL4030: read and write module ISRs to clear them at init
-To: linux-omap@vger.kernel.org
-Date: Thu, 17 Jul 2008 19:34:52 -0600
-Message-ID: <20080718013451.18943.18579.stgit@localhost.localdomain>
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+TWL4030: use *_SIH_CTRL.COR bit to determine whether to read or write ISR to clear
+
+From: Paul Walmsley <paul@pwsan.com>
TWL4030 interrupt status register bits can be cleared in one of two ways:
either by reading from the register, or by writing a 1 to the
appropriate bit(s) in the register. This behavior can be altered at any
time by the <twlmodule>_SIH_CTRL.COR register bit ("clear-on-read").
-twl4030-core.c does not touch these *_SIH_CTRL registers during boot,
-and the TWL4030 TRM is deeply confused as to whether COR=1 means that
-the registers are cleared on reads, or cleared on writes.
+The TWL4030 TRM is deeply confused as to whether COR=1 means that the
+registers are cleared on reads, or cleared on writes. Peter De
+Schrijver <peter.de-schrijver> confirms that COR=1 means that the registers
+are cleared on read.
+
+So, for each TWL4030 SIH, check the value of the *_SIH_CTRL.COR bit, and if
+it is 1, use reads to clear the ISRs; if it is 0, use writes.
+
+Also, use WARN_ON() to warn if the read/write failed, and don't skip
+the rest of the initialization on failure either.
+
+Thanks to Peter for his help with this patch.
-So, take the cautious way out and both read from and write to the TWL4030
-module ISRs to clear them at startup. Also, use WARN_ON() to warn if the
-read/write failed, and don't skip the rest of the initialization on failure
-either.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
- drivers/i2c/chips/twl4030-core.c | 128 +++++++++++++++-----------------------
- 1 files changed, 51 insertions(+), 77 deletions(-)
+ drivers/i2c/chips/twl4030-core.c | 183 ++++++++++++++++++++++----------------
+ 1 files changed, 106 insertions(+), 77 deletions(-)
diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
-index 9d93524..615fb84 100644
+index 9d93524..eae0634 100644
--- a/drivers/i2c/chips/twl4030-core.c
+++ b/drivers/i2c/chips/twl4030-core.c
-@@ -712,6 +712,28 @@ static int power_companion_init(void)
+@@ -133,6 +133,16 @@
+ /* on I2C-1 for 2430SDP */
+ #define CONFIG_I2C_TWL4030_ID 1
+
++/* SIH_CTRL registers */
++#define TWL4030_INT_PWR_SIH_CTRL 0x07
++#define TWL4030_INTERRUPTS_BCISIHCTRL 0x0d
++#define TWL4030_MADC_MADC_SIH_CTRL 0x67
++#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
++#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2d
++
++#define TWL4030_SIH_CTRL_COR_MASK (1 << 2)
++
++
+ /* Helper functions */
+ static int
+ twl4030_detect_client(struct i2c_adapter *adapter, unsigned char sid);
+@@ -712,13 +722,61 @@ static int power_companion_init(void)
return e;
}
@@ -70,28 +56,46 @@ index 9d93524..615fb84 100644
+ * twl4030_i2c_clear_isr - clear TWL4030 SIH ISR regs via read + write
+ * @mod_no: TWL4030 module number
+ * @reg: register index to clear
++ * @cor: value of the <module>_SIH_CTRL.COR bit (1 or 0)
+ *
-+ * Reads, then writes 0xff to a TWL4030 interrupt status register to ensure
-+ * that interrupts are cleared. The read + write is necessary since we
-+ * don't know whether the COR bit is set in <module>_SIH_CTRL. Returns
-+ * the status from the I2C read operation.
++ * Either reads (cor == 1) or writes (cor == 0) to a TWL4030 interrupt
++ * status register to ensure that any prior interrupts are cleared.
++ * Returns the status from the I2C read operation.
+ */
-+static int twl4030_i2c_clear_isr(u8 mod_no, u8 reg)
++static int twl4030_i2c_clear_isr(u8 mod_no, u8 reg, u8 cor)
+{
-+ int res;
+ u8 tmp;
+
-+ res = twl4030_i2c_read_u8(mod_no, &tmp, reg);
-+ if (res < 0)
-+ return res;
++ return (cor) ? twl4030_i2c_read_u8(mod_no, &tmp, reg) :
++ twl4030_i2c_write_u8(mod_no, 0xff, reg);
++}
++
++/**
++ * twl4030_read_cor_bit - are TWL module ISRs cleared by reads or writes?
++ * @mod_no: TWL4030 module number
++ * @reg: register index to clear
++ *
++ * Returns 1 if the TWL4030 SIH interrupt status registers (ISRs) for
++ * the specified TWL module are cleared by reads, or 0 if cleared by
++ * writes.
++ */
++static int twl4030_read_cor_bit(u8 mod_no, u8 reg)
++{
++ u8 tmp = 0;
++
++ WARN_ON(twl4030_i2c_read_u8(mod_no, &tmp, reg) < 0);
++
++ tmp &= TWL4030_SIH_CTRL_COR_MASK;
++ tmp >>= __ffs(TWL4030_SIH_CTRL_COR_MASK);
+
-+ return twl4030_i2c_write_u8(mod_no, 0xff, reg);
++ return tmp;
+}
+
static void twl_init_irq(void)
{
int i = 0;
-@@ -719,6 +741,13 @@ static void twl_init_irq(void)
+ int res = 0;
++ int cor;
char *msg = "Unable to register interrupt subsystem";
unsigned int irq_num;
@@ -102,19 +106,27 @@ index 9d93524..615fb84 100644
+ * handlers present.
+ */
+
++
/* PWR_IMR1 */
res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x1);
if (res < 0) {
-@@ -735,19 +764,11 @@ static void twl_init_irq(void)
+@@ -734,20 +792,18 @@ static void twl_init_irq(void)
+ }
/* Clear off any other pending interrupts on power */
++
++ /* Are PWR interrupt status bits cleared by reads or writes? */
++ cor = twl4030_read_cor_bit(TWL4030_MODULE_INT,
++ TWL4030_INT_PWR_SIH_CTRL);
++ WARN_ON(cor < 0);
++
/* PWR_ISR1 */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x00);
- if (res < 0) {
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x00) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x00, cor) < 0);
/* PWR_ISR2 */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x02);
@@ -123,21 +135,27 @@ index 9d93524..615fb84 100644
- return;
- }
- /* POWER HACK (END) */
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x02) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x02, cor) < 0);
+
/* Slave address 0x4A */
/* BCIIMR1A */
-@@ -779,32 +800,16 @@ static void twl_init_irq(void)
+@@ -778,33 +834,22 @@ static void twl_init_irq(void)
+ return;
}
++ /* Are BCI interrupt status bits cleared by reads or writes? */
++ cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS,
++ TWL4030_INTERRUPTS_BCISIHCTRL);
++ WARN_ON(cor < 0);
++
/* BCIISR1A */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x0);
- if (res < 0) {
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x0) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x0, cor) < 0);
/* BCIISR2A */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x1);
@@ -145,7 +163,7 @@ index 9d93524..615fb84 100644
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x1) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x1, cor) < 0);
/* BCIISR1B */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x4);
@@ -153,7 +171,7 @@ index 9d93524..615fb84 100644
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x4) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x4, cor) < 0);
/* BCIISR2B */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x5);
@@ -161,20 +179,26 @@ index 9d93524..615fb84 100644
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x5) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x5, cor) < 0);
/* MAD C */
/* MADC_IMR1 */
-@@ -822,18 +827,10 @@ static void twl_init_irq(void)
+@@ -821,19 +866,16 @@ static void twl_init_irq(void)
+ return;
}
++ /* Are MADC interrupt status bits cleared by reads or writes? */
++ cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC,
++ TWL4030_MADC_MADC_SIH_CTRL);
++ WARN_ON(cor < 0);
++
/* MADC_ISR1 */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x61);
- if (res < 0) {
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x61) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x61, cor) < 0);
/* MADC_ISR2 */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x63);
@@ -182,11 +206,11 @@ index 9d93524..615fb84 100644
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x63) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x63, cor) < 0);
/* key Pad */
/* KEYPAD - IMR1 */
-@@ -842,12 +839,10 @@ static void twl_init_irq(void)
+@@ -842,12 +884,15 @@ static void twl_init_irq(void)
pr_err("%s[%d][%d]\n", msg, res, __LINE__);
return;
}
@@ -197,32 +221,43 @@ index 9d93524..615fb84 100644
- twl4030_i2c_read_u8(TWL4030_MODULE_KEYPAD, &clear, 0x11);
- }
+
++ /* Are keypad interrupt status bits cleared by reads or writes? */
++ cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD,
++ TWL4030_KEYPAD_KEYP_SIH_CTRL);
++ WARN_ON(cor < 0);
++
+ /* KEYPAD - ISR1 */
+ /* XXX does this still need to be done twice for some reason? */
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x11) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x11, cor) < 0);
/* KEYPAD - IMR2 */
res = twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xFF, (0x14));
-@@ -856,6 +851,9 @@ static void twl_init_irq(void)
+@@ -856,6 +901,9 @@ static void twl_init_irq(void)
return;
}
+ /* KEYPAD - ISR2 */
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x13) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x13, cor) < 0);
+
/* Slave address 0x49 */
/* GPIO_IMR1A */
res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x1C));
-@@ -900,46 +898,22 @@ static void twl_init_irq(void)
+@@ -899,47 +947,28 @@ static void twl_init_irq(void)
+ return;
}
++ /* Are GPIO interrupt status bits cleared by reads or writes? */
++ cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO,
++ TWL4030_GPIO_GPIO_SIH_CTRL);
++ WARN_ON(cor < 0);
++
/* GPIO_ISR1A */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x19);
- if (res < 0) {
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x19) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x19, cor) < 0);
/* GPIO_ISR2A */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1a);
@@ -230,7 +265,7 @@ index 9d93524..615fb84 100644
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1a) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1a, cor) < 0);
/* GPIO_ISR3A */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1b);
@@ -238,7 +273,7 @@ index 9d93524..615fb84 100644
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1b) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1b, cor) < 0);
/* GPIO_ISR1B */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1f);
@@ -246,7 +281,7 @@ index 9d93524..615fb84 100644
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1f) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1f, cor) < 0);
/* GPIO_ISR2B */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x20);
@@ -254,7 +289,7 @@ index 9d93524..615fb84 100644
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x20) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x20, cor) < 0);
/* GPIO_ISR3B */
- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x21);
@@ -262,14 +297,7 @@ index 9d93524..615fb84 100644
- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
- return;
- }
-+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x21) < 0);
++ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x21, cor) < 0);
/* install an irq handler for each of the PIH modules */
for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) {
-
-
---
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generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 07:09:46 +0000