1 files changed, 0 insertions, 245 deletions
diff --git a/packages/linux/linux-omap2-git/beagleboard/02-omappm-mpu-latency-modeling.eml b/packages/linux/linux-omap2-git/beagleboard/02-omappm-mpu-latency-modeling.eml
deleted file mode 100644
index 35ef87bdf0..0000000000
--- a/packages/linux/linux-omap2-git/beagleboard/02-omappm-mpu-latency-modeling.eml
+++ /dev/null
@@ -1,245 +0,0 @@
-Adds resource def's for mpu/core/powerdomain latencies for OMAP3
-
-Signed-off-by: Rajendra Nayak <rnayak@ti.com>
----
- arch/arm/mach-omap2/resource34xx.h |  226 +++++++++++++++++++++++++++++++++++++
- 1 files changed, 226 insertions(+)
-
-Index: linux-omap-2.6/arch/arm/mach-omap2/resource34xx.h
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-omap-2.6/arch/arm/mach-omap2/resource34xx.h	2008-08-07
-15:07:02.000000000 +0530
-@@ -0,0 +1,226 @@
-+/*
-+ * linux/arch/arm/mach-omap2/resource34xx.h
-+ *
-+ * OMAP3 resource definitions
-+ *
-+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
-+ * Written by Rajendra Nayak <rnayak@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
-+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-+ *
-+ * History:
-+ *
-+ */
-+
-+#ifndef __ARCH_ARM_MACH_OMAP2_RESOURCE_H
-+#define __ARCH_ARM_MACH_OMAP2_RESOURCE_H
-+
-+#include <asm/arch/resource.h>
-+#include <asm/arch/powerdomain.h>
-+
-+/**
-+ * mpu_latency/core_latency are used to control the cpuidle C state.
-+ */
-+void init_latency(struct shared_resource *resp);
-+int set_latency(struct shared_resource *resp, u32 target_level);
-+
-+static u8 mpu_qos_req_added;
-+static u8 core_qos_req_added;
-+
-+static struct shared_resource_ops lat_res_ops = {
-+	.init 		= init_latency,
-+	.change_level   = set_latency,
-+};
-+
-+static struct shared_resource mpu_latency = {
-+	.name 		= "mpu_latency",
-+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-+	.resource_data  = &mpu_qos_req_added,
-+	.ops 		= &lat_res_ops,
-+};
-+
-+static struct shared_resource core_latency = {
-+	.name 		= "core_latency",
-+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-+	.resource_data	= &core_qos_req_added,
-+	.ops 		= &lat_res_ops,
-+};
-+
-+/**
-+ * Power domain Latencies are used to control the target Power
-+ * domain state once all clocks for the power domain
-+ * are released.
-+ */
-+void init_pd_latency(struct shared_resource *resp);
-+int set_pd_latency(struct shared_resource *resp, u32 target_level);
-+
-+/* Power Domain Latency levels */
-+#define PD_LATENCY_OFF		0x0
-+#define PD_LATENCY_RET		0x1
-+#define PD_LATENCY_INACT	0x2
-+#define PD_LATENCY_ON		0x3
-+
-+#define PD_LATENCY_MAXLEVEL 	0x4
-+
-+struct pd_latency_db {
-+	char *pwrdm_name;
-+	struct powerdomain *pd;
-+	/* Latencies for each state transition, stored in us */
-+	unsigned long latency[PD_LATENCY_MAXLEVEL];
-+};
-+
-+static struct shared_resource_ops pd_lat_res_ops = {
-+	.init		= init_pd_latency,
-+	.change_level 	= set_pd_latency,
-+};
-+
-+static struct pd_latency_db iva2_pwrdm_lat_db = {
-+	.pwrdm_name = "iva2_pwrdm",
-+	.latency[PD_LATENCY_OFF] = 1000,
-+	.latency[PD_LATENCY_RET] = 100,
-+	.latency[PD_LATENCY_INACT] = 0,
-+	.latency[PD_LATENCY_ON] = 0
-+};
-+
-+static struct shared_resource iva2_pwrdm_latency = {
-+	.name		= "iva2_pwrdm_latency",
-+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-+	.resource_data	= &iva2_pwrdm_lat_db,
-+	.ops		= &pd_lat_res_ops,
-+};
-+
-+static struct pd_latency_db gfx_pwrdm_lat_db = {
-+	.pwrdm_name = "gfx_pwrdm",
-+	.latency[PD_LATENCY_OFF] = 1000,
-+	.latency[PD_LATENCY_RET] = 100,
-+	.latency[PD_LATENCY_INACT] = 0,
-+	.latency[PD_LATENCY_ON]	 = 0
-+};
-+
-+static struct shared_resource gfx_pwrdm_latency = {
-+	.name		= "gfx_pwrdm_latency",
-+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
-+	.resource_data	= &gfx_pwrdm_lat_db,
-+	.ops		= &pd_lat_res_ops,
-+};
-+
-+static struct shared_resource sgx_pwrdm_latency = {
-+	.name 		= "sgx_pwrdm_latency",
-+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
-+	.resource_data  = &gfx_pwrdm_lat_db,
-+	.ops		= &pd_lat_res_ops,
-+};
-+
-+static struct pd_latency_db dss_pwrdm_lat_db = {
-+	.pwrdm_name = "dss_pwrdm",
-+	.latency[PD_LATENCY_OFF] = 70,
-+	.latency[PD_LATENCY_RET] = 20,
-+	.latency[PD_LATENCY_INACT] = 0,
-+	.latency[PD_LATENCY_ON]	 = 0
-+};
-+
-+static struct shared_resource dss_pwrdm_latency = {
-+	.name		= "dss_pwrdm_latency",
-+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-+	.resource_data	= &dss_pwrdm_lat_db,
-+	.ops		= &pd_lat_res_ops,
-+};
-+
-+static struct pd_latency_db cam_pwrdm_lat_db = {
-+	.pwrdm_name = "cam_pwrdm",
-+	.latency[PD_LATENCY_OFF] = 850,
-+	.latency[PD_LATENCY_RET] = 35,
-+	.latency[PD_LATENCY_INACT] = 0,
-+	.latency[PD_LATENCY_ON]	 = 0
-+};
-+
-+static struct shared_resource cam_pwrdm_latency = {
-+	.name		= "cam_pwrdm_latency",
-+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-+	.resource_data	= &cam_pwrdm_lat_db,
-+	.ops		= &pd_lat_res_ops,
-+};
-+
-+static struct pd_latency_db per_pwrdm_lat_db = {
-+	.pwrdm_name = "per_pwrdm",
-+	.latency[PD_LATENCY_OFF] = 200,
-+	.latency[PD_LATENCY_RET] = 110,
-+	.latency[PD_LATENCY_INACT] = 0,
-+	.latency[PD_LATENCY_ON]	 = 0
-+};
-+
-+static struct shared_resource per_pwrdm_latency = {
-+	.name		= "per_pwrdm_latency",
-+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-+	.resource_data	= &per_pwrdm_lat_db,
-+	.ops		= &pd_lat_res_ops,
-+};
-+
-+static struct pd_latency_db neon_pwrdm_lat_db = {
-+	.pwrdm_name = "neon_pwrdm",
-+	.latency[PD_LATENCY_OFF] = 1000,
-+	.latency[PD_LATENCY_RET] = 100,
-+	.latency[PD_LATENCY_INACT] = 0,
-+	.latency[PD_LATENCY_ON]	 = 0
-+};
-+
-+static struct shared_resource neon_pwrdm_latency = {
-+	.name		= "neon_pwrdm_latency",
-+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-+	.resource_data	= &neon_pwrdm_lat_db,
-+	.ops		= &pd_lat_res_ops,
-+};
-+
-+static struct pd_latency_db usbhost_pwrdm_lat_db = {
-+	.pwrdm_name = "usbhost_pwrdm",
-+	.latency[PD_LATENCY_OFF] = 1000,
-+	.latency[PD_LATENCY_RET] = 100,
-+	.latency[PD_LATENCY_INACT] = 0,
-+	.latency[PD_LATENCY_ON]	 = 0
-+};
-+
-+static struct shared_resource usbhost_pwrdm_latency = {
-+	.name		= "usbhost_pwrdm_latency",
-+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
-+	.resource_data  = &usbhost_pwrdm_lat_db,
-+	.ops		= &pd_lat_res_ops,
-+};
-+
-+static struct pd_latency_db emu_pwrdm_lat_db = {
-+	.pwrdm_name = "emu_pwrdm",
-+	.latency[PD_LATENCY_OFF] = 1000,
-+	.latency[PD_LATENCY_RET] = 100,
-+	.latency[PD_LATENCY_INACT] = 0,
-+	.latency[PD_LATENCY_ON]  = 0
-+};
-+
-+static struct shared_resource emu_pwrdm_latency = {
-+	.name           = "emu_pwrdm",
-+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-+	.resource_data  = &emu_pwrdm_lat_db,
-+	.ops		= &pd_lat_res_ops,
-+};
-+
-+struct shared_resource *resources_omap[] __initdata = {
-+	&mpu_latency,
-+	&core_latency,
-+	/* Power Domain Latency resources */
-+	&iva2_pwrdm_latency,
-+	&gfx_pwrdm_latency,
-+	&sgx_pwrdm_latency,
-+	&dss_pwrdm_latency,
-+	&cam_pwrdm_latency,
-+	&per_pwrdm_latency,
-+	&neon_pwrdm_latency,
-+	&usbhost_pwrdm_latency,
-+	&emu_pwrdm_latency,
-+	NULL
-+};
-+
-+#endif /* __ARCH_ARM_MACH_OMAP2_RESOURCE_H */
-
-
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