diff options
Diffstat (limited to 'packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch')
| -rw-r--r-- | packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch b/packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch new file mode 100644 index 0000000000..35417344e0 --- /dev/null +++ b/packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch @@ -0,0 +1,98 @@ +Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c +=================================================================== +--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-06-28 22:44:12.000000000 -0300 ++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-06-28 22:45:00.000000000 -0300 +@@ -20,6 +20,7 @@ + #include <asm/arch/pxa-regs.h> + #include <asm/arch/pxafb.h> + #include <asm/arch/ezx.h> ++#include <asm/arch/ezx-pcap.h> + + #include "generic.h" + +@@ -49,7 +50,85 @@ + .pxafb_lcd_power = &ezx_lcd_power, + }; + ++/* PCAP */ ++static int __init a780_pcap_init(void) ++{ ++ /* initialize PCAP registers */ ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1CTRL, 1); ++// ezx_pcap_vibrator_level(PCAP_VIBRATOR_VOLTAGE_LEVEL3); ++ ++ /* set SW1 sleep to keep SW1 1.3v in sync mode */ ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE10, 0); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE11, 0); ++ ++ /* SW1 active in sync mode */ ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE00, 1); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE01, 0); ++ ++ /* at SW1 -core voltage to 1.30V */ ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW10_DVS, 1); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW11_DVS, 1); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW12_DVS, 1); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW13_DVS, 0); ++ ++ /* when STANDY2 PIN ACTIVE (high) set V3-- sram V8 -- pll off */ ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_STBY, 1); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_LOWPWR, 0); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_STBY, 1); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_LOWPWR, 0); ++ ++ /* ++ * when STANDY2 PIN ACTIVE (high) set V4-- lcd only for e680 V6 --- ++ * camera for e680 ++ */ ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_STBY, 1); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_LOWPWR, 1); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_STBY, 1); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_LOWPWR, 0); ++ ++ /* set Vc to low power mode when AP sleep */ ++// SSP_PCAP_bit_set( SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VC_STBY); ++ ++ /* set VAUX2 to voltage 2.775V and low power mode when AP sleep */ ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_1, 1); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_0, 0); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_STBY, 1); ++ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_LOWPWR, 1); ++// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN, 1); ++ ++// PGSR(GPIO34_TXENB) |= GPIO_bit(GPIO34_TXENB); ++ ++ return 0; ++} ++ ++static struct pcap_platform_data a780_pcap_platform_data = { ++ .port = 1, ++ .cs = GPIO_SPI_CE, ++ .flags = PCAP_MCI_TF, ++ .clk = 1, ++ .init = a780_pcap_init, ++}; ++ ++static struct resource a780_pcap_resources[] = { ++ [0] = { ++ .start = IRQ_GPIO1, ++ .end = IRQ_GPIO1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device a780_pcap_device = { ++ .name = "ezx-pcap", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(a780_pcap_resources), ++ .resource = a780_pcap_resources, ++ .dev = { ++ .platform_data = &a780_pcap_platform_data, ++ }, ++}; ++ + static struct platform_device *devices[] __initdata = { ++ &a780_pcap_device, + }; + + static void __init a780_init(void) |