diff options
Diffstat (limited to 'packages/gcc/gcc-4.1.2')
| -rw-r--r-- | packages/gcc/gcc-4.1.2/gcc-4.0.2-e300c2c3.patch | 311 |
1 files changed, 311 insertions, 0 deletions
diff --git a/packages/gcc/gcc-4.1.2/gcc-4.0.2-e300c2c3.patch b/packages/gcc/gcc-4.1.2/gcc-4.0.2-e300c2c3.patch new file mode 100644 index 0000000000..736ac4b6b6 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/gcc-4.0.2-e300c2c3.patch @@ -0,0 +1,311 @@ +Adds support for Freescale Power architecture e300c2 and e300c3 cores. +http://www.bitshrine.org/gpp/tc-fsl-x86lnx-e300c3-nptl-4.0.2-2.src.rpm + +Leon Woestenberg <leonw@mailcan.com> + +Index: gcc-4.1.2/gcc/config/rs6000/e300c2c3.md +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ gcc-4.1.2/gcc/config/rs6000/e300c2c3.md 2007-10-18 15:32:51.000000000 +0200 +@@ -0,0 +1,189 @@ ++;; Pipeline description for Motorola PowerPC e300c3 core. ++;; Copyright (C) 2003 Free Software Foundation, Inc. ++;; ++;; This file is part of GCC. ++ ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published ++;; by the Free Software Foundation; either version 2, or (at your ++;; option) any later version. ++ ++;; GCC is distributed in the hope that it will be useful, but WITHOUT ++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++;; License for more details. ++ ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING. If not, write to the ++;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, ++;; MA 02111-1307, USA. ++ ++(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire") ++(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most") ++ ++;; We don't simulate general issue queue (GIC). If we have SU insn ++;; and then SU1 insn, they can not be issued on the same cycle ++;; (although SU1 insn and then SU insn can be issued) because the SU ++;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle ++;; multipass insn scheduling will find the situation and issue the SU1 ++;; insn and then the SU insn. ++(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most") ++ ++;; We could describe completion buffers slots in combination with the ++;; retirement units and the order of completion but the result ++;; automaton would behave in the same way because we can not describe ++;; real latency time with taking in order completion into account. ++;; Actually we could define the real latency time by querying reserved ++;; automaton units but the current scheduler uses latency time before ++;; issuing insns and making any reservations. ++;; ++;; So our description is aimed to achieve a insn schedule in which the ++;; insns would not wait in the completion buffer. ++(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire") ++ ++;; Branch unit: ++(define_cpu_unit "ppce300c3_bu" "ppce300c3_most") ++ ++;; IU: ++(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most") ++ ++;; IU: This used to describe non-pipelined division. ++(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long") ++ ++;; SRU: ++(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most") ++ ++;; Here we simplified LSU unit description not describing the stages. ++(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most") ++ ++;; FPU: ++(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most") ++ ++;; The following units are used to make automata deterministic ++(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most") ++(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most") ++(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire") ++(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most") ++ ++;; The following sets to make automata deterministic when option ndfa is used. ++(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0") ++(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0") ++(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0") ++(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0") ++ ++;; Some useful abbreviations. ++(define_reservation "ppce300c3_decode" ++ "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0") ++(define_reservation "ppce300c3_issue" ++ "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0") ++(define_reservation "ppce300c3_retire" ++ "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0") ++(define_reservation "ppce300c3_iu_stage0" ++ "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0") ++ ++;; Compares can be executed either one of the IU or SRU ++(define_insn_reservation "ppce300c3_cmp" 1 ++ (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \ ++ +ppce300c3_retire") ++ ++;; Other one cycle IU insns ++(define_insn_reservation "ppce300c3_iu" 1 ++ (and (eq_attr "type" "integer,insert_word") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire") ++ ++;; Branch. Actually this latency time is not used by the scheduler. ++(define_insn_reservation "ppce300c3_branch" 1 ++ (and (eq_attr "type" "jmpreg,branch") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire") ++ ++;; Multiply is non-pipelined but can be executed in any IU ++(define_insn_reservation "ppce300c3_multiply" 2 ++ (and (eq_attr "type" "imul,imul2,imul3,imul_compare") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \ ++ ppce300c3_iu_stage0+ppce300c3_retire") ++ ++;; Divide. We use the average latency time here. We omit reserving a ++;; retire unit because of the result automata will be huge. ++(define_insn_reservation "ppce300c3_divide" 20 ++ (and (eq_attr "type" "idiv") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\ ++ ppce300c3_mu_div*19") ++ ++;; CR logical ++(define_insn_reservation "ppce300c3_cr_logical" 1 ++ (and (eq_attr "type" "cr_logical,delayed_cr") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") ++ ++;; Mfcr ++(define_insn_reservation "ppce300c3_mfcr" 1 ++ (and (eq_attr "type" "mfcr") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") ++ ++;; Mtcrf ++(define_insn_reservation "ppce300c3_mtcrf" 1 ++ (and (eq_attr "type" "mtcr") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") ++ ++;; Mtjmpr ++(define_insn_reservation "ppce300c3_mtjmpr" 1 ++ (and (eq_attr "type" "mtjmpr,mfjmpr") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") ++ ++;; Float point instructions ++(define_insn_reservation "ppce300c3_fpcompare" 3 ++ (and (eq_attr "type" "fpcompare") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") ++ ++(define_insn_reservation "ppce300c3_fp" 3 ++ (and (eq_attr "type" "fp") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") ++ ++(define_insn_reservation "ppce300c3_dmul" 4 ++ (and (eq_attr "type" "dmul") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire") ++ ++; Divides are not pipelined ++(define_insn_reservation "ppce300c3_sdiv" 18 ++ (and (eq_attr "type" "sdiv") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17") ++ ++(define_insn_reservation "ppce300c3_ddiv" 33 ++ (and (eq_attr "type" "ddiv") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32") ++ ++;; Loads ++(define_insn_reservation "ppce300c3_load" 2 ++ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") ++ ++(define_insn_reservation "ppce300c3_fpload" 2 ++ (and (eq_attr "type" "fpload,fpload_ux,fpload_u") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") ++ ++;; Stores. ++(define_insn_reservation "ppce300c3_store" 2 ++ (and (eq_attr "type" "store,store_ux,store_u") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") ++ ++(define_insn_reservation "ppce300c3_fpstore" 2 ++ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") +Index: gcc-4.1.2/gcc/config/rs6000/rs6000.c +=================================================================== +--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.c 2006-12-16 20:24:56.000000000 +0100 ++++ gcc-4.1.2/gcc/config/rs6000/rs6000.c 2007-10-18 15:34:26.000000000 +0200 +@@ -557,6 +557,21 @@ + COSTS_N_INSNS (29), /* ddiv */ + }; + ++/* Instruction costs on E300C2 and E300C3 cores. */ ++static const ++struct processor_costs ppce300c2c3_cost = { ++ COSTS_N_INSNS (4), /* mulsi */ ++ COSTS_N_INSNS (4), /* mulsi_const */ ++ COSTS_N_INSNS (4), /* mulsi_const9 */ ++ COSTS_N_INSNS (4), /* muldi */ ++ COSTS_N_INSNS (19), /* divsi */ ++ COSTS_N_INSNS (19), /* divdi */ ++ COSTS_N_INSNS (3), /* fp */ ++ COSTS_N_INSNS (4), /* dmul */ ++ COSTS_N_INSNS (18), /* sdiv */ ++ COSTS_N_INSNS (33), /* ddiv */ ++}; ++ + /* Instruction costs on POWER4 and POWER5 processors. */ + static const + struct processor_costs power4_cost = { +@@ -1140,6 +1155,8 @@ + /* 8548 has a dummy entry for now. */ + {"8548", PROCESSOR_PPC8540, + POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN}, ++ {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, ++ {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK}, + {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, + {"970", PROCESSOR_POWER4, + POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, +@@ -1529,6 +1546,11 @@ + rs6000_cost = &ppc8540_cost; + break; + ++ case PROCESSOR_PPCE300C2: ++ case PROCESSOR_PPCE300C3: ++ rs6000_cost = &ppce300c2c3_cost; ++ break; ++ + case PROCESSOR_POWER4: + case PROCESSOR_POWER5: + rs6000_cost = &power4_cost; +@@ -16647,6 +16669,8 @@ + case CPU_PPC750: + case CPU_PPC7400: + case CPU_PPC8540: ++ case CPU_PPCE300C2: ++ case CPU_PPCE300C3: + return 2; + case CPU_RIOS2: + case CPU_PPC604: +Index: gcc-4.1.2/gcc/config/rs6000/rs6000.h +=================================================================== +--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.h 2006-11-18 01:25:49.000000000 +0100 ++++ gcc-4.1.2/gcc/config/rs6000/rs6000.h 2007-10-18 15:32:51.000000000 +0200 +@@ -111,6 +111,8 @@ + %{mcpu=970: -mpower4 -maltivec} \ + %{mcpu=G5: -mpower4 -maltivec} \ + %{mcpu=8540: -me500} \ ++%{mcpu=e300c2: -mppc} \ ++%{mcpu=e300c3: -mppc -mpmr} \ + %{maltivec: -maltivec} \ + -many" + +@@ -211,6 +213,8 @@ + PROCESSOR_PPC7400, + PROCESSOR_PPC7450, + PROCESSOR_PPC8540, ++ PROCESSOR_PPCE300C2, ++ PROCESSOR_PPCE300C3, + PROCESSOR_POWER4, + PROCESSOR_POWER5 + }; +Index: gcc-4.1.2/gcc/config/rs6000/rs6000.md +=================================================================== +--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.md 2006-12-16 20:24:56.000000000 +0100 ++++ gcc-4.1.2/gcc/config/rs6000/rs6000.md 2007-10-18 15:32:51.000000000 +0200 +@@ -103,7 +103,7 @@ + ;; Processor type -- this attribute must exactly match the processor_type + ;; enumeration in rs6000.h. + +-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" ++(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,power4,power5" + (const (symbol_ref "rs6000_cpu_attr"))) + + (automata_option "ndfa") +@@ -119,6 +119,7 @@ + (include "7xx.md") + (include "7450.md") + (include "8540.md") ++(include "e300c2c3.md") + (include "power4.md") + (include "power5.md") + +Index: gcc-4.1.2/gcc/config.gcc +=================================================================== +--- gcc-4.1.2.orig/gcc/config.gcc 2007-10-18 15:26:23.000000000 +0200 ++++ gcc-4.1.2/gcc/config.gcc 2007-10-18 15:32:51.000000000 +0200 +@@ -2710,7 +2710,7 @@ + | rios | rios1 | rios2 | rsc | rsc1 | rs64a \ + | 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \ + | 601 | 602 | 603 | 603e | ec603e | 604 \ +- | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \ ++ | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \ + | 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5) + # OK + ;; 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