diff options
17 files changed, 3749 insertions, 15 deletions
diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/.mtn2git_empty b/packages/u-boot/u-boot-1.1.4/at32stk1000/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/.mtn2git_empty diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch new file mode 100644 index 0000000000..fa8c8f701f --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch @@ -0,0 +1,112 @@ +diff -uprN u-boot-orig/cpu/at32ap7xxx/ap7000/devices.c u-boot/cpu/at32ap7xxx/ap7000/devices.c +--- u-boot-orig/cpu/at32ap7xxx/ap7000/devices.c 2007-01-01 19:26:46.000000000 +0100 ++++ u-boot/cpu/at32ap7xxx/ap7000/devices.c 2006-12-22 14:51:26.000000000 +0100 +@@ -223,6 +223,46 @@ static const struct resource macb1_resou + }, + }; + #endif ++#if defined(CFG_SPI0) ++static const struct resource spi0_resource[] = { ++ { ++ .type = RESOURCE_CLOCK, ++ .u = { ++ .clock = { CLOCK_APBA, 0 }, ++ }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 0 }, ++ }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 1, DEVICE_PIOA, GPIO_FUNC_B, 20 }, ++ }, ++ }, ++}; ++#endif ++#if defined(CFG_SPI1) ++static const struct resource spi1_resource[] = { ++ { ++ .type = RESOURCE_CLOCK, ++ .u = { ++ .clock = { CLOCK_APBA, 1 }, ++ }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 6, DEVICE_PIOB, GPIO_FUNC_B, 0 }, ++ }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 1, DEVICE_PIOA, GPIO_FUNC_A, 27 }, ++ }, ++ }, ++}; ++#endif + #if defined(CFG_LCDC) + static const struct resource lcdc_resource[] = { + { +@@ -230,6 +270,16 @@ static const struct resource lcdc_resour + .u = { + .clock = { CLOCK_AHB, 7 }, + }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 13, DEVICE_PIOC, GPIO_FUNC_A, 19 }, ++ }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 18, DEVICE_PIOD, GPIO_FUNC_A, 0 }, ++ }, + }, + }; + #endif +@@ -390,6 +440,20 @@ const struct device chip_device[] = { + .resource = macb0_resource, + }, + #endif ++#if defined(CFG_SPI0) ++ [DEVICE_SPI0] = { ++ .regs = (void *)SPI0_BASE, ++ .nr_resources = ARRAY_SIZE(spi0_resource), ++ .resource = spi0_resource, ++ }, ++#endif ++#if defined(CFG_SPI1) ++ [DEVICE_SPI1] = { ++ .regs = (void *)SPI1_BASE, ++ .nr_resources = ARRAY_SIZE(spi1_resource), ++ .resource = spi1_resource, ++ }, ++#endif + #if defined(CFG_MACB1) + [DEVICE_MACB1] = { + .regs = (void *)MACB1_BASE, +@@ -399,6 +463,7 @@ const struct device chip_device[] = { + #endif + #if defined(CFG_LCDC) + [DEVICE_LCDC] = { ++ .regs = (void *)LCDC_BASE, + .nr_resources = ARRAY_SIZE(lcdc_resource), + .resource = lcdc_resource, + }, +diff -uprN u-boot-orig/include/asm-avr32/arch-ap7000/platform.h u-boot/include/asm-avr32/arch-ap7000/platform.h +--- u-boot-orig/include/asm-avr32/arch-ap7000/platform.h 2007-01-01 19:26:46.000000000 +0100 ++++ u-boot/include/asm-avr32/arch-ap7000/platform.h 2006-12-22 14:20:39.000000000 +0100 +@@ -66,6 +66,12 @@ enum device_id { + #if defined(CFG_MACB1) + DEVICE_MACB1, + #endif ++#if defined(CFG_SPI0) ++ DEVICE_SPI0, ++#endif ++#if defined(CFG_SPI1) ++ DEVICE_SPI1, ++#endif + #if defined(CFG_LCDC) + DEVICE_LCDC, + #endif diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch new file mode 100644 index 0000000000..33c5eb9b7c --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch @@ -0,0 +1,117 @@ +Index: u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c +=================================================================== +--- u-boot-1.1.4.orig/cpu/at32ap7xxx/hsdramc.c 2007-01-11 15:28:40.000000000 +0100 ++++ u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c 2007-01-11 15:29:36.000000000 +0100 +@@ -133,6 +133,7 @@ + printf("SDRAM: %u MB at address 0x%08lx\n", + sdram_size >> 20, info->phys_addr); + ++#ifdef CONFIG_SDRAM_TEST + printf("Testing SDRAM..."); + for (i = 0; i < sdram_size / 4; i++) + sdram[i] = i; +@@ -148,6 +149,7 @@ + } + + puts("OK\n"); ++#endif + + return sdram_size; + } +Index: u-boot-1.1.4/include/configs/atngw.h +=================================================================== +--- u-boot-1.1.4.orig/include/configs/atngw.h 2007-01-11 15:28:40.000000000 +0100 ++++ u-boot-1.1.4/include/configs/atngw.h 2007-01-30 16:41:23.000000000 +0100 +@@ -31,6 +31,10 @@ + + #define CONFIG_NGW_EXT_FLASH 1 + ++/* Handy macros for making strings */ ++#define xstringify(x) #x ++#define stringify(x) xstringify(x) ++ + /* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency +@@ -80,9 +84,9 @@ + + #define CONFIG_BAUDRATE 115200 + #define CONFIG_BOOTARGS \ +- "console=ttyS0 root=/dev/mmcblk0p1" ++ "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2" + #define CONFIG_BOOTCOMMAND \ +- "mmcinit; ext2load mmc 0:1 0x90400000 /uImage; bootm 0x90400000" ++ "fsload 0x90250000 /uImage; bootm 0x90250000" + + #define CONFIG_BOOTDELAY 2 + #define CONFIG_AUTOBOOT 1 +@@ -105,8 +109,8 @@ + * generated and assigned to the environment variables "ethaddr" and + * "eth1addr". + */ +-#define CONFIG_ETHADDR "6a:87:71:14:cd:cb" +-#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6" ++#define CONFIG_ETHADDR "42:b2:13:36:50:94" ++#define CONFIG_ETH1ADDR "4e:29:49:7e:5c:b9" + #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 + #define CONFIG_NET_MULTI 1 + +@@ -183,6 +187,7 @@ + + #define CFG_SDRAM_BASE 0x10000000 + #define CFG_SDRAM_16BIT 1 ++#define CONFIG_SDRAM_TEST 1 + + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_SIZE 65536 +@@ -202,7 +207,7 @@ + #define CFG_DMA_ALLOC_END (CFG_MALLOC_START) + #define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) + /* Allow 2MB for the kernel run-time image */ +-#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) ++#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00250000) + #define CFG_BOOTPARAMS_LEN (16 * 1024) + + /* Other configuration settings that shouldn't have to change all that often */ +Index: u-boot-1.1.4/include/configs/atstk1002.h +=================================================================== +--- u-boot-1.1.4.orig/include/configs/atstk1002.h 2007-01-11 15:29:36.000000000 +0100 ++++ u-boot-1.1.4/include/configs/atstk1002.h 2007-01-30 16:41:25.000000000 +0100 +@@ -98,7 +98,7 @@ + #define CFG_CONSOLE_UART_DEV DEVICE_USART1 + + /* Define to force consol on serial */ +-/* #define CFG_CONSOLE_ALLWAYS_UART 1 */ ++#define CFG_CONSOLE_ALLWAYS_UART 1 + #ifdef CFG_CONSOLE_ALLWAYS_UART + #define CFG_CONSOLE_IS_IN_ENV 1 + #define CFG_CONSOLE_OVERWRITE_ROUTINE 1 +@@ -123,7 +123,7 @@ + #endif + + #define CONFIG_BOOTCOMMAND \ +- "mmcinit; ext2load mmc 0:1 /uImage; bootm" ++ "mmcinit; ext2load mmc 0:1 0x90250000 /uImage; bootm 0x90250000" + #define CONFIG_BOOTDELAY 2 + #define CONFIG_AUTOBOOT 1 + +@@ -145,8 +145,8 @@ + * generated and assigned to the environment variables "ethaddr" and + * "eth1addr". + */ +-#define CONFIG_ETHADDR "6a:87:71:14:cd:cb" +-#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6" ++#define CONFIG_ETHADDR "42:b2:13:36:50:94" ++#define CONFIG_ETH1ADDR "4e:29:49:7e:5c:b9" + #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 + #define CONFIG_NET_MULTI 1 + +@@ -233,6 +233,8 @@ + #define CFG_INTRAM_SIZE 0x8000 + + #define CFG_SDRAM_BASE 0x10000000 ++/* Will do SDRAM test if defined */ ++#define CONFIG_SDRAM_TEST 1 + + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_SIZE 65536 diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch new file mode 100644 index 0000000000..cac9be5d55 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch @@ -0,0 +1,11 @@ +diff -uprN u-boot-orig/include/asm-avr32/global_data.h u-boot/include/asm-avr32/global_data.h +--- u-boot-orig/include/asm-avr32/global_data.h 2007-01-01 19:26:46.000000000 +0100 ++++ u-boot/include/asm-avr32/global_data.h 2006-12-19 11:08:14.000000000 +0100 +@@ -44,6 +44,7 @@ typedef struct global_data { + unsigned long env_addr; /* Address of env struct */ + unsigned long env_valid; /* Checksum of env valid? */ + unsigned long cpu_hz; /* TODO: remove */ ++ unsigned long fb_base; /* Address to framebuffer */ + void **jt; + } gd_t; + diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch new file mode 100644 index 0000000000..397d6b00aa --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch @@ -0,0 +1,16 @@ +diff -uprN u-boot-orig/include/asm-avr32/initcalls.h u-boot/include/asm-avr32/initcalls.h +--- u-boot-orig/include/asm-avr32/initcalls.h 2007-01-01 19:26:46.000000000 +0100 ++++ u-boot/include/asm-avr32/initcalls.h 2007-01-05 13:29:16.000000000 +0100 +@@ -30,6 +30,12 @@ extern void board_init_memories(void); + extern void board_init_pio(void); + extern void board_init_info(void); + ++#if CONFIG_SPI ++extern void board_init_spi(void); ++#else ++static inline void board_init_spi(void) { } ++#endif ++ + #if (CONFIG_COMMANDS & CFG_CMD_NET) + extern void net_init(void); + #else diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch new file mode 100644 index 0000000000..221333c4bc --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch @@ -0,0 +1,252 @@ +diff -uprN u-boot-orig/include/asm-avr32/arch-ap7000/sm.h u-boot/include/asm-avr32/arch-ap7000/sm.h +--- u-boot-orig/include/asm-avr32/arch-ap7000/sm.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/asm-avr32/arch-ap7000/sm.h 2006-12-21 16:28:04.000000000 +0100 +@@ -0,0 +1,248 @@ ++/* ++ * Register definitions for SM ++ * ++ * System Manager ++ */ ++#ifndef __ASM_AVR32_SM_H__ ++#define __ASM_AVR32_SM_H__ ++ ++/* SM register offsets */ ++#define SM_PM_MCCTRL 0x0000 ++#define SM_PM_CKSEL 0x0004 ++#define SM_PM_CPU_MASK 0x0008 ++#define SM_PM_AHB_MASK 0x000c ++#define SM_PM_APBA_MASK 0x0010 ++#define SM_PM_APBB_MASK 0x0014 ++#define SM_PM_PLL0 0x0020 ++#define SM_PM_PLL1 0x0024 ++#define SM_PM_VCTRL 0x0030 ++#define SM_PM_VMREF 0x0034 ++#define SM_PM_VMV 0x0038 ++#define SM_PM_IER 0x0040 ++#define SM_PM_IDR 0x0044 ++#define SM_PM_IMR 0x0048 ++#define SM_PM_ISR 0x004c ++#define SM_PM_ICR 0x0050 ++#define SM_PM_GCCTRL 0x0060 ++#define SM_PM_GCCTRL0 0x0060 ++#define SM_PM_GCCTRL1 0x0064 ++#define SM_PM_GCCTRL2 0x0068 ++#define SM_PM_GCCTRL3 0x006c ++#define SM_PM_GCCTRL4 0x0070 ++#define SM_PM_GCCTRL5 0x0074 ++#define SM_PM_GCCTRL6 0x0078 ++#define SM_PM_GCCTRL7 0x007c ++#define SM_RTC_CTRL 0x0080 ++#define SM_RTC_VAL 0x0084 ++#define SM_RTC_TOP 0x0088 ++#define SM_RTC_IER 0x0090 ++#define SM_RTC_IDR 0x0094 ++#define SM_RTC_IMR 0x0098 ++#define SM_RTC_ISR 0x009c ++#define SM_RTC_ICR 0x00a0 ++#define SM_WDT_CTRL 0x00b0 ++#define SM_WDT_CLR 0x00b4 ++#define SM_WDT_EXT 0x00b8 ++#define SM_RC_RCAUSE 0x00c0 ++#define SM_EIM_IER 0x0100 ++#define SM_EIM_IDR 0x0104 ++#define SM_EIM_IMR 0x0108 ++#define SM_EIM_ISR 0x010c ++#define SM_EIM_ICR 0x0110 ++#define SM_EIM_MODE 0x0114 ++#define SM_EIM_EDGE 0x0118 ++#define SM_EIM_LEVEL 0x011c ++#define SM_EIM_TEST 0x0120 ++#define SM_EIM_NMIC 0x0124 ++ ++/* Bitfields in PM_MCCTRL */ ++ ++/* Bitfields in PM_CKSEL */ ++#define SM_CPUSEL_OFFSET 0 ++#define SM_CPUSEL_SIZE 3 ++#define SM_CPUDIV_OFFSET 7 ++#define SM_CPUDIV_SIZE 1 ++#define SM_AHBSEL_OFFSET 8 ++#define SM_AHBSEL_SIZE 3 ++#define SM_AHBDIV_OFFSET 15 ++#define SM_AHBDIV_SIZE 1 ++#define SM_APBASEL_OFFSET 16 ++#define SM_APBASEL_SIZE 3 ++#define SM_APBADIV_OFFSET 23 ++#define SM_APBADIV_SIZE 1 ++#define SM_APBBSEL_OFFSET 24 ++#define SM_APBBSEL_SIZE 3 ++#define SM_APBBDIV_OFFSET 31 ++#define SM_APBBDIV_SIZE 1 ++ ++/* Bitfields in PM_CPU_MASK */ ++ ++/* Bitfields in PM_AHB_MASK */ ++ ++/* Bitfields in PM_APBA_MASK */ ++ ++/* Bitfields in PM_APBB_MASK */ ++ ++/* Bitfields in PM_PLL0 */ ++#define SM_PLLEN_OFFSET 0 ++#define SM_PLLEN_SIZE 1 ++#define SM_PLLOSC_OFFSET 1 ++#define SM_PLLOSC_SIZE 1 ++#define SM_PLLOPT_OFFSET 2 ++#define SM_PLLOPT_SIZE 3 ++#define SM_PLLDIV_OFFSET 8 ++#define SM_PLLDIV_SIZE 8 ++#define SM_PLLMUL_OFFSET 16 ++#define SM_PLLMUL_SIZE 8 ++#define SM_PLLCOUNT_OFFSET 24 ++#define SM_PLLCOUNT_SIZE 6 ++#define SM_PLLTEST_OFFSET 31 ++#define SM_PLLTEST_SIZE 1 ++ ++/* Bitfields in PM_PLL1 */ ++ ++/* Bitfields in PM_VCTRL */ ++#define SM_VAUTO_OFFSET 0 ++#define SM_VAUTO_SIZE 1 ++#define SM_PM_VCTRL_VAL_OFFSET 8 ++#define SM_PM_VCTRL_VAL_SIZE 7 ++ ++/* Bitfields in PM_VMREF */ ++#define SM_REFSEL_OFFSET 0 ++#define SM_REFSEL_SIZE 4 ++ ++/* Bitfields in PM_VMV */ ++#define SM_PM_VMV_VAL_OFFSET 0 ++#define SM_PM_VMV_VAL_SIZE 8 ++ ++/* Bitfields in PM_IER */ ++ ++/* Bitfields in PM_IDR */ ++ ++/* Bitfields in PM_IMR */ ++ ++/* Bitfields in PM_ISR */ ++ ++/* Bitfields in PM_ICR */ ++#define SM_LOCK0_OFFSET 0 ++#define SM_LOCK0_SIZE 1 ++#define SM_LOCK1_OFFSET 1 ++#define SM_LOCK1_SIZE 1 ++#define SM_WAKE_OFFSET 2 ++#define SM_WAKE_SIZE 1 ++#define SM_VOK_OFFSET 3 ++#define SM_VOK_SIZE 1 ++#define SM_VMRDY_OFFSET 4 ++#define SM_VMRDY_SIZE 1 ++#define SM_CKRDY_OFFSET 5 ++#define SM_CKRDY_SIZE 1 ++ ++/* Bitfields in PM_GCCTRL */ ++#define SM_OSCSEL_OFFSET 0 ++#define SM_OSCSEL_SIZE 1 ++#define SM_PLLSEL_OFFSET 1 ++#define SM_PLLSEL_SIZE 1 ++#define SM_CEN_OFFSET 2 ++#define SM_CEN_SIZE 1 ++#define SM_CPC_OFFSET 3 ++#define SM_CPC_SIZE 1 ++#define SM_DIVEN_OFFSET 4 ++#define SM_DIVEN_SIZE 1 ++#define SM_DIV_OFFSET 8 ++#define SM_DIV_SIZE 8 ++ ++/* Bitfields in RTC_CTRL */ ++#define SM_PCLR_OFFSET 1 ++#define SM_PCLR_SIZE 1 ++#define SM_TOPEN_OFFSET 2 ++#define SM_TOPEN_SIZE 1 ++#define SM_CLKEN_OFFSET 3 ++#define SM_CLKEN_SIZE 1 ++#define SM_PSEL_OFFSET 8 ++#define SM_PSEL_SIZE 16 ++ ++/* Bitfields in RTC_VAL */ ++#define SM_RTC_VAL_VAL_OFFSET 0 ++#define SM_RTC_VAL_VAL_SIZE 31 ++ ++/* Bitfields in RTC_TOP */ ++#define SM_RTC_TOP_VAL_OFFSET 0 ++#define SM_RTC_TOP_VAL_SIZE 32 ++ ++/* Bitfields in RTC_IER */ ++ ++/* Bitfields in RTC_IDR */ ++ ++/* Bitfields in RTC_IMR */ ++ ++/* Bitfields in RTC_ISR */ ++ ++/* Bitfields in RTC_ICR */ ++#define SM_TOPI_OFFSET 0 ++#define SM_TOPI_SIZE 1 ++ ++/* Bitfields in WDT_CTRL */ ++#define SM_KEY_OFFSET 24 ++#define SM_KEY_SIZE 8 ++ ++/* Bitfields in WDT_CLR */ ++ ++/* Bitfields in WDT_EXT */ ++ ++/* Bitfields in RC_RCAUSE */ ++#define SM_POR_OFFSET 0 ++#define SM_POR_SIZE 1 ++#define SM_BOD_OFFSET 1 ++#define SM_BOD_SIZE 1 ++#define SM_EXT_OFFSET 2 ++#define SM_EXT_SIZE 1 ++#define SM_WDT_OFFSET 3 ++#define SM_WDT_SIZE 1 ++#define SM_NTAE_OFFSET 4 ++#define SM_NTAE_SIZE 1 ++#define SM_SERP_OFFSET 5 ++#define SM_SERP_SIZE 1 ++ ++/* Bitfields in EIM_IER */ ++ ++/* Bitfields in EIM_IDR */ ++ ++/* Bitfields in EIM_IMR */ ++ ++/* Bitfields in EIM_ISR */ ++ ++/* Bitfields in EIM_ICR */ ++ ++/* Bitfields in EIM_MODE */ ++ ++/* Bitfields in EIM_EDGE */ ++#define SM_INT0_OFFSET 0 ++#define SM_INT0_SIZE 1 ++#define SM_INT1_OFFSET 1 ++#define SM_INT1_SIZE 1 ++#define SM_INT2_OFFSET 2 ++#define SM_INT2_SIZE 1 ++#define SM_INT3_OFFSET 3 ++#define SM_INT3_SIZE 1 ++ ++/* Bitfields in EIM_LEVEL */ ++ ++/* Bitfields in EIM_TEST */ ++#define SM_TESTEN_OFFSET 31 ++#define SM_TESTEN_SIZE 1 ++ ++/* Bitfields in EIM_NMIC */ ++#define SM_EN_OFFSET 0 ++#define SM_EN_SIZE 1 ++ ++/* Bit manipulation macros */ ++#define SM_BIT(name) (1 << SM_##name##_OFFSET) ++#define SM_BF(name,value) (((value) & ((1 << SM_##name##_SIZE) - 1)) << SM_##name##_OFFSET) ++#define SM_BFEXT(name,value) (((value) >> SM_##name##_OFFSET) & ((1 << SM_##name##_SIZE) - 1)) ++#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value)) ++ ++/* Register access macros */ ++#define sm_readl(port,reg) readl((port)->regs + SM_##reg) ++#define sm_writel(port,reg,value) writel((value), (port)->regs + SM_##reg) ++ ++#endif /* __ASM_AVR32_SM_H__ */ diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch new file mode 100644 index 0000000000..4deb284564 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch @@ -0,0 +1,124 @@ +Index: u-boot-orig/include/configs/atstk1002.h +=================================================================== +--- u-boot-orig.orig/include/configs/atstk1002.h 2007-01-05 15:58:53.000000000 +0100 ++++ u-boot-orig/include/configs/atstk1002.h 2007-01-05 16:04:50.000000000 +0100 +@@ -32,6 +32,10 @@ + + #define CONFIG_ATSTK1000_EXT_FLASH 1 + ++/* Handy macros for making strings */ ++#define xstringify(x) #x ++#define stringify(x) xstringify(x) ++ + /* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency +@@ -68,10 +72,39 @@ + #define CFG_USART1 1 + #define CFG_MMCI 1 + #define CFG_MACB0 1 +-#define CFG_MACB1 1 ++/* #define CFG_MACB1 1 */ ++ ++/* Enable SPI support */ ++#define CONFIG_SPI 1 ++#define CONFIG_ATMEL_SPI 1 ++#define CFG_SPI0 1 ++ ++/* Enable LCD support */ ++#define CFG_DMAC 1 ++#define CFG_LCDC 1 ++#define CONFIG_LCD 1 ++#define CONFIG_ATMEL_LCDC 1 ++#define CONFIG_DISPLAY_LTV350QV 1 ++ ++/* Setup LCD */ ++#define LCD_BPP LCD_COLOR24 ++/* CFG_SDRAM_BASE + 0x00500000 */ ++#define CFG_LCD_BASE 0x10500000 ++#define CFG_WHITE_ON_BLACK 1 ++#define CONFIG_VIDEO_BMP_GZIP 1 ++#define CFG_VIDEO_LOGO_MAX_SIZE 262144 /* > 320 * 240 * 3 */ ++/* #define CONFIG_SPLASH_SCREEN 1 */ + + #define CFG_CONSOLE_UART_DEV DEVICE_USART1 + ++/* Define to force consol on serial */ ++/* #define CFG_CONSOLE_ALLWAYS_UART 1 */ ++#ifdef CFG_CONSOLE_ALLWAYS_UART ++#define CFG_CONSOLE_IS_IN_ENV 1 ++#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 ++#define CFG_CONSOLE_ENV_OVERWRITE 1 ++#endif ++ + /* User serviceable stuff */ + #define CONFIG_CMDLINE_TAG 1 + #define CONFIG_SETUP_MEMORY_TAGS 1 +@@ -80,11 +113,17 @@ + #define CONFIG_STACKSIZE (2048) + + #define CONFIG_BAUDRATE 115200 ++ ++#ifdef CFG_LCD_BASE + #define CONFIG_BOOTARGS \ +- "console=ttyUS0 root=/dev/mmcblk0p1 fbmem=600k" +-#define CONFIG_BOOTCOMMAND \ +- "mmcinit; ext2load mmc 0:1 0x90400000 /uImage; bootm 0x90400000" ++ "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k@" stringify(CFG_LCD_BASE) ++#else ++#define CONFIG_BOOTARGS \ ++ "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k" ++#endif + ++#define CONFIG_BOOTCOMMAND \ ++ "mmcinit; ext2load mmc 0:1 /uImage; bootm" + #define CONFIG_BOOTDELAY 2 + #define CONFIG_AUTOBOOT 1 + +@@ -144,7 +183,7 @@ + /* | CFG_CMD_DIAG */ \ + /* | CFG_CMD_HWFLOW */ \ + /* | CFG_CMD_SAVES */ \ +- /* | CFG_CMD_SPI */ \ ++ | CFG_CMD_SPI \ + /* | CFG_CMD_PING */ \ + | CFG_CMD_MMC \ + /* | CFG_CMD_FAT */ \ +@@ -152,6 +191,7 @@ + /* | CFG_CMD_ITEST */ \ + | CFG_CMD_EXT2 \ + | CFG_CMD_JFFS2 \ ++ | CFG_CMD_BMP \ + ) + + #include <cmd_confdefs.h> +@@ -201,7 +241,7 @@ + #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + + #ifdef CONFIG_ATSTK1000 +-# define CFG_MALLOC_LEN (256*1024) ++# define CFG_MALLOC_LEN (512*1024) + # define CFG_MALLOC_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ +@@ -213,7 +253,7 @@ + # define CFG_DMA_ALLOC_END (CFG_MALLOC_START) + # define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) + /* Allow 2MB for the kernel run-time image */ +-# define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) ++# define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00250000) + # define CFG_BOOTPARAMS_LEN (16 * 1024) + #else + # define CFG_MALLOC_LEN (8*1024) +Index: u-boot-orig/board/atstk1000/atstk1000.c +=================================================================== +--- u-boot-orig.orig/board/atstk1000/atstk1000.c 2007-01-05 16:02:33.000000000 +0100 ++++ u-boot-orig/board/atstk1000/atstk1000.c 2007-01-05 16:04:00.000000000 +0100 +@@ -52,3 +52,7 @@ + gd->bd->bi_phy_id[0] = 0x10; + gd->bd->bi_phy_id[1] = 0x11; + } ++ ++#ifdef CFG_CONSOLE_ALLWAYS_UART ++int overwrite_console(void) { return 1; } ++#endif diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch new file mode 100644 index 0000000000..57c0fae127 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch @@ -0,0 +1,163 @@ +diff -uprN u-boot-orig/board/atstk1000/ltv350qv.c u-boot/board/atstk1000/ltv350qv.c +--- u-boot-orig/board/atstk1000/ltv350qv.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/atstk1000/ltv350qv.c 2007-01-02 15:17:32.000000000 +0100 +@@ -0,0 +1,147 @@ ++/* ++ * Copyright (C) 2005-2006 Atmel Corporation ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include <common.h> ++ ++#ifdef CONFIG_LCD ++#ifndef CONFIG_SPI ++#error No SPI controller for LCD setup, enable CFG_SPI ++#endif ++ ++#include <spi.h> ++ ++#ifdef CONFIG_ATMEL_SPI ++#include <atmel_spi.h> ++#endif ++ ++static int ltv350qv_write_reg(u8 reg, u16 val) ++{ ++ int ret; ++ u8 buffer[3]; ++ ++ buffer[0] = 0x74; ++ buffer[1] = 0x00; ++ buffer[2] = reg & 0x7f; ++ ++ ret = spi_write(&buffer[0], 1, &buffer[1], 2); ++ if (ret != 3) { ++ printf("spi_write returned %d\n", ret); ++ return -1; ++ } ++ ++ buffer[0] = 0x76; ++ buffer[1] = val >> 8; ++ buffer[2] = val; ++ ++ ret = spi_write(&buffer[0], 1, &buffer[1], 2); ++ if (ret != 3) { ++ printf("spi_write returned %d\n", ret); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++#define write_reg(reg, val) \ ++ do { \ ++ ret = ltv350qv_write_reg(reg, val); \ ++ if (ret) \ ++ goto out; \ ++ } while (0) ++ ++void ltv350qv_power_on(void) ++{ ++ int ret; ++ ++#ifdef CONFIG_ATMEL_SPI ++ spi_select_chip(1); ++#endif ++ ++ debug ("ltv350qv: do power on sequence\n"); ++ ++ /* write startup procedure */ ++ write_reg(9, 0x0000); ++ udelay(15000); ++ write_reg(9, 0x4000); ++ write_reg(10, 0x2000); ++ write_reg(9, 0x4055); ++ udelay(55000); ++ write_reg(1, 0x409d); ++ write_reg(2, 0x0204); ++ write_reg(3, 0x0100); ++ write_reg(4, 0x3000); ++ write_reg(5, 0x4003); ++ write_reg(6, 0x000a); ++ write_reg(7, 0x0021); ++ write_reg(8, 0x0c00); ++ write_reg(10, 0x0103); ++ write_reg(11, 0x0301); ++ write_reg(12, 0x1f0f); ++ write_reg(13, 0x1f0f); ++ write_reg(14, 0x0707); ++ write_reg(15, 0x0307); ++ write_reg(16, 0x0707); ++ write_reg(17, 0x0000); ++ write_reg(18, 0x0004); ++ write_reg(19, 0x0000); ++ ++ udelay(20000); ++ write_reg(9, 0x4a55); ++ write_reg(5, 0x5003); ++ ++ debug ("ltv350qv: power on sequence done\n"); ++out: ++ return; ++} ++ ++void ltv350qv_power_off(void) ++{ ++ int ret; ++ ++#ifdef CONFIG_ATMEL_SPI ++ spi_select_chip(1); ++#endif ++ ++ debug ("ltv350qv: do power off sequence\n"); ++ /* GON -> 0, POC -> 0 */ ++ write_reg(9, 0x4055); ++ /* DSC -> 0 */ ++ write_reg(5, 0x4003); ++ /* VCOMG -> 0 */ ++ write_reg(10, 0x2103); ++ ++ udelay(1000000); ++ ++ /* AP[2:0] -> 000 */ ++ write_reg(9, 0x4050); ++ ++ debug ("ltv350qv: power off sequence done\n"); ++out: ++ return; ++} ++ ++void ltv350qv_init(void) ++{ ++ debug ("ltv350qv: initializing LTV350QV panel\n"); ++ ltv350qv_power_on(); ++} ++ ++#endif +diff -uprN u-boot-orig/board/atstk1000/Makefile u-boot/board/atstk1000/Makefile +--- u-boot-orig/board/atstk1000/Makefile 2007-01-01 19:26:46.000000000 +0100 ++++ u-boot/board/atstk1000/Makefile 2007-01-01 16:23:12.000000000 +0100 +@@ -30,7 +30,7 @@ endif + + LIB := lib$(BOARD).a + +-SRC := $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c ++SRC := $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c ltv350qv.c + SRC += spi.c + OBJS := $(addsuffix .o,$(basename $(SRC))) + diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch new file mode 100644 index 0000000000..b9cdba16ff --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch @@ -0,0 +1,98 @@ +diff -uprN u-boot-orig/board/atstk1000/spi.c u-boot/board/atstk1000/spi.c +--- u-boot-orig/board/atstk1000/spi.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/atstk1000/spi.c 2007-01-03 08:46:36.000000000 +0100 +@@ -0,0 +1,83 @@ ++/* ++ * Copyright (C) 2006 Atmel Corporation ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include <common.h> ++ ++#include <spi.h> ++#include <asm/io.h> ++#include <atmel_spi.h> ++ ++extern void ltv350qv_init(void); ++ ++static struct spi_options_t cs0 = { ++ .reg = 0, ++ .baudrate = 200000, ++ .bits = 8, ++ .spck_delay = 0, ++ .trans_delay = 0, ++ .stay_act = 1, ++ .spi_mode = 3, ++}; ++static struct spi_options_t cs1 = { ++ .reg = 1, ++ .baudrate = 1500000, ++ .bits = 8, ++ .spck_delay = 0, ++ .trans_delay = 0, ++ .stay_act = 1, ++ .spi_mode = 3, |