diff options
| -rw-r--r-- | packages/ixp4xx/ixp4xx-csr-2.1/mii-debug.patch | 26 | ||||
| -rw-r--r-- | packages/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch | 30 | ||||
| -rw-r--r-- | packages/ixp4xx/ixp4xx-csr_2.1.bb | 4 |
3 files changed, 59 insertions, 1 deletions
diff --git a/packages/ixp4xx/ixp4xx-csr-2.1/mii-debug.patch b/packages/ixp4xx/ixp4xx-csr-2.1/mii-debug.patch new file mode 100644 index 0000000000..b6e017a64c --- /dev/null +++ b/packages/ixp4xx/ixp4xx-csr-2.1/mii-debug.patch @@ -0,0 +1,26 @@ +debug only patch to add information about MII id problems + +--- ixp_osal/src/ethMii/IxEthMii.c 1970-01-01 00:00:00.000000000 +0000 ++++ ixp_osal/src/ethMii/IxEthMii.c 1970-01-01 00:00:00.000000000 +0000 +@@ -122,6 +122,10 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT3 + ) + { + /* supported phy */ ++ ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, ++ IX_OSAL_LOG_DEV_STDOUT, ++ "ixEthMiiPhyScan, Mii %d: Mii PHY ID %8.8x\n", ++ i, ixEthMiiPhyId[i], 3, 4, 5, 6); + phyPresent[i] = TRUE; + } /* end of if(ixEthMiiPhyId) */ + else +@@ -131,8 +135,8 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT3 + /* unsupported phy */ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, + IX_OSAL_LOG_DEV_STDOUT, +- "ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n", +- ixEthMiiPhyId[i], 2, 3, 4, 5, 6); ++ "ixEthMiiPhyScan, Mii %d: unexpected Mii PHY ID %8.8x\n", ++ i, ixEthMiiPhyId[i], 3, 4, 5, 6); + ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID; + phyPresent[i] = TRUE; + } diff --git a/packages/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch b/packages/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch new file mode 100644 index 0000000000..150dc27016 --- /dev/null +++ b/packages/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch @@ -0,0 +1,30 @@ +this patch adds support for the RTL8201CP PHY + +--- ixp400_xscale_sw/src/ethMii/IxEthMii.c 1970-01-01 00:00:00.000000000 +0000 ++++ ixp400_xscale_sw/src/ethMii/IxEthMii.c 1970-01-01 00:00:00.000000000 +0000 +@@ -119,6 +119,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT3 + || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973_PHY_ID) + || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973A3_PHY_ID) + || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT9785_PHY_ID) ++ || (ixEthMiiPhyId[i] == IX_ETH_MII_RTL8201_PHY_ID) + ) + { + /* supported phy */ +@@ -287,6 +288,7 @@ ixEthMiiPhyReset(UINT32 phyAddr) + (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID) || + (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973_PHY_ID) || + (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973A3_PHY_ID) || ++ (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_RTL8201_PHY_ID) || + (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID) + ) + { +--- ixp400_xscale_sw/src/ethMii/IxEthMii_p.h 1970-01-01 00:00:00.000000000 +0000 ++++ ixp400_xscale_sw/src/ethMii/IxEthMii_p.h 1970-01-01 00:00:00.000000000 +0000 +@@ -179,6 +179,7 @@ + #define IX_ETH_MII_LXT973A3_PHY_ID 0x00137A11 + #define IX_ETH_MII_KS8995_PHY_ID 0x00221450 + #define IX_ETH_MII_LXT9785_PHY_ID 0x001378FF ++#define IX_ETH_MII_RTL8201_PHY_ID 0x00008201 + #define IX_ETH_MII_RTL8305_FAKE_PHY_ID 0x83058305 + + #define IX_ETH_MII_INVALID_PHY_ID 0x00000000 diff --git a/packages/ixp4xx/ixp4xx-csr_2.1.bb b/packages/ixp4xx/ixp4xx-csr_2.1.bb index a0798df722..a37f8c6944 100644 --- a/packages/ixp4xx/ixp4xx-csr_2.1.bb +++ b/packages/ixp4xx/ixp4xx-csr_2.1.bb @@ -31,10 +31,12 @@ SRC_URI += "file://ixethdb-header.patch;patch=1" SRC_URI += "file://bit-macro.patch;patch=1" SRC_URI += "file://ixnpemhconfigisr-is-private.patch;patch=1" SRC_URI += "file://le.patch;patch=1" +SRC_URI += "file://mii-debug.patch;patch=1" +SRC_URI += "file://rtl8201-support.patch;patch=1" DEPENDS = "ixp-osal" S = "${WORKDIR}/ixp400_xscale_sw" -PR = "r4" +PR = "r5" COMPATIBLE_HOST = "^arm.*-linux.*" |