diff options
| -rw-r--r-- | packages/linux/linux-2.6.24/gesbc-9302/0005-ep93xx-reboot.patch | 1256 | ||||
| -rw-r--r-- | packages/linux/linux_2.6.24.bb | 3 |
2 files changed, 1258 insertions, 1 deletions
diff --git a/packages/linux/linux-2.6.24/gesbc-9302/0005-ep93xx-reboot.patch b/packages/linux/linux-2.6.24/gesbc-9302/0005-ep93xx-reboot.patch new file mode 100644 index 0000000000..fa84a0bbcf --- /dev/null +++ b/packages/linux/linux-2.6.24/gesbc-9302/0005-ep93xx-reboot.patch @@ -0,0 +1,1256 @@ +From 1b16045d453045e93b4f94cc57d3205ae9b9d118 Mon Sep 17 00:00:00 2001 +From: Cliff Brake <cbrake@bec-systems.com> +Date: Thu, 7 Feb 2008 08:47:28 -0500 +Subject: [PATCH] ep93xx-reboot + +--- + include/asm-arm/arch-ep93xx/ep93xx-regs.h | 1047 ++++++++++++++++++++++++++++- + include/asm-arm/arch-ep93xx/system.h | 114 +++- + 2 files changed, 1148 insertions(+), 13 deletions(-) + +diff --git a/include/asm-arm/arch-ep93xx/ep93xx-regs.h b/include/asm-arm/arch-ep93xx/ep93xx-regs.h +index 625c6f0..6e799d9 100644 +--- a/include/asm-arm/arch-ep93xx/ep93xx-regs.h ++++ b/include/asm-arm/arch-ep93xx/ep93xx-regs.h +@@ -15,17 +15,898 @@ + */ + + #define EP93XX_AHB_PHYS_BASE 0x80000000 +-#define EP93XX_AHB_VIRT_BASE 0xfef00000 ++#define EP93XX_AHB_VIRT_BASE 0xff000000//0xfef00000 + #define EP93XX_AHB_SIZE 0x00100000 + ++ + #define EP93XX_APB_PHYS_BASE 0x80800000 +-#define EP93XX_APB_VIRT_BASE 0xfed00000 ++#define EP93XX_APB_VIRT_BASE 0xff800000//0xfed00000 + #define EP93XX_APB_SIZE 0x00200000 + + +-/* AHB peripherals */ ++#define IO_BASE_PHYS EP93XX_AHB_PHYS_BASE ++#define IO_BASE_VIRT EP93XX_AHB_VIRT_BASE ++/* ++ * We don't map the PCMCIA initially. The PCMCIA driver will use ioremap ++ * to be able to see it. But besides that PCMCIA will not exist in the ++ * memory map. ++ */ ++#define PCMCIA_BASE_VIRT 0xD0000000 // Virtual address of PCMCIA ++#define PCMCIA_BASE_PHYS 0x40000000 // Physical address of PCMCIA ++#define PCMCIA_SIZE 0x10000000 // How much? ++ ++ ++ ++/* ++ * We don't map the PCMCIA initially. The PCMCIA driver will use ioremap ++ * to be able to see it. But besides that PCMCIA will not exist in the */ ++/* SMC register map */ ++/* Address Read Location Write Location */ ++/* 0x8000.2000 SMCBCR0(Bank config register 0) SMCBCR0(Bank config register 0) */ ++/* 0x8000.2004 SMCBCR1(Bank config register 1) SMCBCR1(Bank config register 1) */ ++/* 0x8000.2008 SMCBCR2(Bank config register 2) SMCBCR2(Bank config register 2) */ ++/* 0x8000.200C SMCBCR3(Bank config register 3) SMCBCR3(Bank config register 3) */ ++/* 0x8000.2010 Reserved, RAZ Reserved, RAZ */ ++/* 0x8000.2014 Reserved, RAZ Reserved, RAZ */ ++/* 0x8000.2018 SMCBCR6(Bank config register 6) SMCBCR6(Bank config register 6) */ ++/* 0x8000.201C SMCBCR7(Bank config register 7) SMCBCR7(Bank config register 7) */ ++/* 0x8000.2020 PCAttribute Register PCAttribute Register */ ++/* 0x8000.2024 PCCommon Register PCCommon Register */ ++/* 0x8000.2028 PCIO Register PCIO Register */ ++/* 0x8000.202C Reserved, RAZ Reserved, RAZ */ ++/* 0x8000.2030 Reserved, RAZ Reserved, RAZ */ ++/* 0x8000.2034 Reserved, RAZ Reserved, RAZ */ ++/* 0x8000.2038 Reserved, RAZ Reserved, RAZ */ ++/* 0x8000.203C Reserved, RAZ Reserved, RAZ */ ++/* 0x8000.2040 PCMCIACtrl Register PCMCIACtrl Register */ ++ ++#define SRAM_OFFSET 0x080000 ++#define SRAM_BASE (EP93XX_AHB_VIRT_BASE|SRAM_OFFSET) ++#define SMCBCR0 (SRAM_BASE+0x00) /* 0x8000.2000 Bank config register 0 */ ++#define SMCBCR1 (SRAM_BASE+0x04) /* 0x8000.2004 Bank config register 1 */ ++#define SMCBCR2 (SRAM_BASE+0x08) /* 0x8000.2008 Bank config register 2 */ ++#define SMCBCR3 (SRAM_BASE+0x0C) /* 0x8000.200C Bank config register 3 */ ++ /* 0x8000.2010 Reserved, RAZ */ ++ /* 0x8000.2014 Reserved, RAZ */ ++#define SMCBCR6 (SRAM_BASE+0x18) /* 0x8000.2018 Bank config register 6 */ ++#define SMCBCR7 (SRAM_BASE+0x1C) /* 0x8000.201C Bank config register 7 */ ++ ++#define SMC_PCAttribute (SRAM_BASE+0x20) /* 0x8000.2020 PCMCIA Attribute Register */ ++#define SMC_PCCommon (SRAM_BASE+0x24) /* 0x8000.2024 PCMCIA Common Register */ ++#define SMC_PCIO (SRAM_BASE+0x28) /* 0x8000.2028 PCMCIA IO Register */ ++ /* 0x8000.202C Reserved, RAZ */ ++ /* 0x8000.2030 Reserved, RAZ */ ++ /* 0x8000.2034 Reserved, RAZ */ ++ /* 0x8000.2038 Reserved, RAZ */ ++ /* 0x8000.203C Reserved, RAZ */ ++#define SMC_PCMCIACtrl (SRAM_BASE+0x40) /* 0x8000.2040 PCMCIA control register */ ++ ++ ++ ++ + #define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000) ++// ++/* 8000_0000 - 8000_ffff: DMA */ ++#define DMA_OFFSET 0x000000 ++#define DMA_BASE (EP93XX_DMA_BASE) ++#define DMAMP_TX_0_CONTROL (DMA_BASE+0x0000) ++#define DMAMP_TX_0_INTERRUPT (DMA_BASE+0x0004) ++#define DMAMP_TX_0_PPALLOC (DMA_BASE+0x0008) ++#define DMAMP_TX_0_STATUS (DMA_BASE+0x000C) ++#define DMAMP_TX_0_REMAIN (DMA_BASE+0x0014) ++#define DMAMP_TX_0_MAXCNT0 (DMA_BASE+0x0020) ++#define DMAMP_TX_0_BASE0 (DMA_BASE+0x0024) ++#define DMAMP_TX_0_CURRENT0 (DMA_BASE+0x0028) ++#define DMAMP_TX_0_MAXCNT1 (DMA_BASE+0x0030) ++#define DMAMP_TX_0_BASE1 (DMA_BASE+0x0034) ++#define DMAMP_TX_0_CURRENT1 (DMA_BASE+0x0038) ++ ++#define DMAMP_RX_1_CONTROL (DMA_BASE+0x0040) ++#define DMAMP_RX_1_INTERRUPT (DMA_BASE+0x0044) ++#define DMAMP_RX_1_PPALLOC (DMA_BASE+0x0048) ++#define DMAMP_RX_1_STATUS (DMA_BASE+0x004C) ++#define DMAMP_RX_1_REMAIN (DMA_BASE+0x0054) ++#define DMAMP_RX_1_MAXCNT0 (DMA_BASE+0x0060) ++#define DMAMP_RX_1_BASE0 (DMA_BASE+0x0064) ++#define DMAMP_RX_1_CURRENT0 (DMA_BASE+0x0068) ++#define DMAMP_RX_1_MAXCNT1 (DMA_BASE+0x0070) ++#define DMAMP_RX_1_BASE1 (DMA_BASE+0x0074) ++#define DMAMP_RX_1_CURRENT1 (DMA_BASE+0x0078) ++ ++#define DMAMP_TX_2_CONTROL (DMA_BASE+0x0080) ++#define DMAMP_TX_2_INTERRUPT (DMA_BASE+0x0084) ++#define DMAMP_TX_2_PPALLOC (DMA_BASE+0x0088) ++#define DMAMP_TX_2_STATUS (DMA_BASE+0x008C) ++#define DMAMP_TX_2_REMAIN (DMA_BASE+0x0094) ++#define DMAMP_TX_2_MAXCNT0 (DMA_BASE+0x00A0) ++#define DMAMP_TX_2_BASE0 (DMA_BASE+0x00A4) ++#define DMAMP_TX_2_CURRENT0 (DMA_BASE+0x00A8) ++#define DMAMP_TX_2_MAXCNT1 (DMA_BASE+0x00B0) ++#define DMAMP_TX_2_BASE1 (DMA_BASE+0x00B4) ++#define DMAMP_TX_2_CURRENT1 (DMA_BASE+0x00B8) ++ ++#define DMAMP_RX_3_CONTROL (DMA_BASE+0x00C0) ++#define DMAMP_RX_3_INTERRUPT (DMA_BASE+0x00C4) ++#define DMAMP_RX_3_PPALLOC (DMA_BASE+0x00C8) ++#define DMAMP_RX_3_STATUS (DMA_BASE+0x00CC) ++#define DMAMP_RX_3_REMAIN (DMA_BASE+0x00D4) ++#define DMAMP_RX_3_MAXCNT0 (DMA_BASE+0x00E0) ++#define DMAMP_RX_3_BASE0 (DMA_BASE+0x00E4) ++#define DMAMP_RX_3_CURRENT0 (DMA_BASE+0x00E8) ++#define DMAMP_RX_3_MAXCNT1 (DMA_BASE+0x00F0) ++#define DMAMP_RX_3_BASE1 (DMA_BASE+0x00F4) ++#define DMAMP_RX_3_CURRENT1 (DMA_BASE+0x00F8) ++ ++#define DMAMM_0_CONTROL (DMA_BASE+0x0100) ++#define DMAMM_0_INTERRUPT (DMA_BASE+0x0104) ++#define DMAMM_0_STATUS (DMA_BASE+0x010C) ++#define DMAMM_0_BCR0 (DMA_BASE+0x0110) ++#define DMAMM_0_BCR1 (DMA_BASE+0x0114) ++#define DMAMM_0_SAR_BASE0 (DMA_BASE+0x0118) ++#define DMAMM_0_SAR_BASE1 (DMA_BASE+0x011C) ++#define DMAMM_0_SAR_CURRENT0 (DMA_BASE+0x0124) ++#define DMAMM_0_SAR_CURRENT1 (DMA_BASE+0x0128) ++#define DMAMM_0_DAR_BASE0 (DMA_BASE+0x012C) ++#define DMAMM_0_DAR_BASE1 (DMA_BASE+0x0130) ++#define DMAMM_0_DAR_CURRENT0 (DMA_BASE+0x0134) ++#define DMAMM_0_DAR_CURRENT1 (DMA_BASE+0x013C) ++ ++#define DMAMM_1_CONTROL (DMA_BASE+0x0140) ++#define DMAMM_1_INTERRUPT (DMA_BASE+0x0144) ++#define DMAMM_1_STATUS (DMA_BASE+0x014C) ++#define DMAMM_1_BCR0 (DMA_BASE+0x0150) ++#define DMAMM_1_BCR1 (DMA_BASE+0x0154) ++#define DMAMM_1_SAR_BASE0 (DMA_BASE+0x0158) ++#define DMAMM_1_SAR_BASE1 (DMA_BASE+0x015C) ++#define DMAMM_1_SAR_CURRENT0 (DMA_BASE+0x0164) ++#define DMAMM_1_SAR_CURRENT1 (DMA_BASE+0x0168) ++#define DMAMM_1_DAR_BASE0 (DMA_BASE+0x016C) ++#define DMAMM_1_DAR_BASE1 (DMA_BASE+0x0170) ++#define DMAMM_1_DAR_CURRENT0 (DMA_BASE+0x0174) ++#define DMAMM_1_DAR_CURRENT1 (DMA_BASE+0x017C) ++ ++#define DMAMP_RX_5_CONTROL (DMA_BASE+0x0200) ++#define DMAMP_RX_5_INTERRUPT (DMA_BASE+0x0204) ++#define DMAMP_RX_5_PPALLOC (DMA_BASE+0x0208) ++#define DMAMP_RX_5_STATUS (DMA_BASE+0x020C) ++#define DMAMP_RX_5_REMAIN (DMA_BASE+0x0214) ++#define DMAMP_RX_5_MAXCNT0 (DMA_BASE+0x0220) ++#define DMAMP_RX_5_BASE0 (DMA_BASE+0x0224) ++#define DMAMP_RX_5_CURRENT0 (DMA_BASE+0x0228) ++#define DMAMP_RX_5_MAXCNT1 (DMA_BASE+0x0230) ++#define DMAMP_RX_5_BASE1 (DMA_BASE+0x0234) ++#define DMAMP_RX_5_CURRENT1 (DMA_BASE+0x0238) ++ ++#define DMAMP_TX_4_CONTROL (DMA_BASE+0x0240) ++#define DMAMP_TX_4_INTERRUPT (DMA_BASE+0x0244) ++#define DMAMP_TX_4_PPALLOC (DMA_BASE+0x0248) ++#define DMAMP_TX_4_STATUS (DMA_BASE+0x024C) ++#define DMAMP_TX_4_REMAIN (DMA_BASE+0x0254) ++#define DMAMP_TX_4_MAXCNT0 (DMA_BASE+0x0260) ++#define DMAMP_TX_4_BASE0 (DMA_BASE+0x0264) ++#define DMAMP_TX_4_CURRENT0 (DMA_BASE+0x0268) ++#define DMAMP_TX_4_MAXCNT1 (DMA_BASE+0x0270) ++#define DMAMP_TX_4_BASE1 (DMA_BASE+0x0274) ++#define DMAMP_TX_4_CURRENT1 (DMA_BASE+0x0278) ++ ++#define DMAMP_RX_7_CONTROL (DMA_BASE+0x0280) ++#define DMAMP_RX_7_INTERRUPT (DMA_BASE+0x0284) ++#define DMAMP_RX_7_PPALLOC (DMA_BASE+0x0288) ++#define DMAMP_RX_7_STATUS (DMA_BASE+0x028C) ++#define DMAMP_RX_7_REMAIN (DMA_BASE+0x0294) ++#define DMAMP_RX_7_MAXCNT0 (DMA_BASE+0x02A0) ++#define DMAMP_RX_7_BASE0 (DMA_BASE+0x02A4) ++#define DMAMP_RX_7_CURRENT0 (DMA_BASE+0x02A8) ++#define DMAMP_RX_7_MAXCNT1 (DMA_BASE+0x02B0) ++#define DMAMP_RX_7_BASE1 (DMA_BASE+0x02B4) ++#define DMAMP_RX_7_CURRENT1 (DMA_BASE+0x02B8) ++ ++#define DMAMP_TX_6_CONTROL (DMA_BASE+0x02C0) ++#define DMAMP_TX_6_INTERRUPT (DMA_BASE+0x02C4) ++#define DMAMP_TX_6_PPALLOC (DMA_BASE+0x02C8) ++#define DMAMP_TX_6_STATUS (DMA_BASE+0x02CC) ++#define DMAMP_TX_6_REMAIN (DMA_BASE+0x02D4) ++#define DMAMP_TX_6_MAXCNT0 (DMA_BASE+0x02E0) ++#define DMAMP_TX_6_BASE0 (DMA_BASE+0x02E4) ++#define DMAMP_TX_6_CURRENT0 (DMA_BASE+0x02E8) ++#define DMAMP_TX_6_MAXCNT1 (DMA_BASE+0x02F0) ++#define DMAMP_TX_6_BASE1 (DMA_BASE+0x02F4) ++#define DMAMP_TX_6_CURRENT1 (DMA_BASE+0x02F8) ++ ++#define DMAMP_RX_9_CONTROL (DMA_BASE+0x0300) ++#define DMAMP_RX_9_INTERRUPT (DMA_BASE+0x0304) ++#define DMAMP_RX_9_PPALLOC (DMA_BASE+0x0308) ++#define DMAMP_RX_9_STATUS (DMA_BASE+0x030C) ++#define DMAMP_RX_9_REMAIN (DMA_BASE+0x0314) ++#define DMAMP_RX_9_MAXCNT0 (DMA_BASE+0x0320) ++#define DMAMP_RX_9_BASE0 (DMA_BASE+0x0324) ++#define DMAMP_RX_9_CURRENT0 (DMA_BASE+0x0328) ++#define DMAMP_RX_9_MAXCNT1 (DMA_BASE+0x0330) ++#define DMAMP_RX_9_BASE1 (DMA_BASE+0x0334) ++#define DMAMP_RX_9_CURRENT1 (DMA_BASE+0x0338) ++ ++#define DMAMP_TX_8_CONTROL (DMA_BASE+0x0340) ++#define DMAMP_TX_8_INTERRUPT (DMA_BASE+0x0344) ++#define DMAMP_TX_8_PPALLOC (DMA_BASE+0x0348) ++#define DMAMP_TX_8_STATUS (DMA_BASE+0x034C) ++#define DMAMP_TX_8_REMAIN (DMA_BASE+0x0354) ++#define DMAMP_TX_8_MAXCNT0 (DMA_BASE+0x0360) ++#define DMAMP_TX_8_BASE0 (DMA_BASE+0x0364) ++#define DMAMP_TX_8_CURRENT0 (DMA_BASE+0x0368) ++#define DMAMP_TX_8_MAXCNT1 (DMA_BASE+0x0370) ++#define DMAMP_TX_8_BASE1 (DMA_BASE+0x0374) ++#define DMAMP_TX_8_CURRENT1 (DMA_BASE+0x0378) ++ ++#define DMA_ARBITRATION (DMA_BASE+0x0380) ++#define DMA_INTERRUPT (DMA_BASE+0x03C0) ++ ++ ++/* ++ * DMA Register Base addresses and Offsets ++ */ ++#define DMA_M2P_TX_0_BASE DMAMP_TX_0_CONTROL ++#define DMA_M2P_RX_1_BASE DMAMP_RX_1_CONTROL ++#define DMA_M2P_TX_2_BASE DMAMP_TX_2_CONTROL ++#define DMA_M2P_RX_3_BASE DMAMP_RX_3_CONTROL ++#define DMA_M2M_0_BASE DMAMM_0_CONTROL ++#define DMA_M2M_1_BASE DMAMM_1_CONTROL ++#define DMA_M2P_RX_5_BASE DMAMP_RX_5_CONTROL ++#define DMA_M2P_TX_4_BASE DMAMP_TX_4_CONTROL ++#define DMA_M2P_RX_7_BASE DMAMP_RX_7_CONTROL ++#define DMA_M2P_TX_6_BASE DMAMP_TX_6_CONTROL ++#define DMA_M2P_RX_9_BASE DMAMP_RX_9_CONTROL ++#define DMA_M2P_TX_8_BASE DMAMP_TX_8_CONTROL ++ ++#define M2P_OFFSET_CONTROL 0x0000 ++#define M2P_OFFSET_INTERRUPT 0x0004 ++#define M2P_OFFSET_PPALLOC 0x0008 ++#define M2P_OFFSET_STATUS 0x000C ++#define M2P_OFFSET_REMAIN 0x0014 ++#define M2P_OFFSET_MAXCNT0 0x0020 ++#define M2P_OFFSET_BASE0 0x0024 ++#define M2P_OFFSET_CURRENT0 0x0028 ++#define M2P_OFFSET_MAXCNT1 0x0030 ++#define M2P_OFFSET_BASE1 0x0034 ++#define M2P_OFFSET_CURRENT1 0x0038 ++ ++#define M2M_OFFSET_CONTROL 0x0000 ++#define M2M_OFFSET_INTERRUPT 0x0004 ++#define M2M_OFFSET_STATUS 0x000C ++#define M2M_OFFSET_BCR0 0x0010 ++#define M2M_OFFSET_BCR1 0x0014 ++#define M2M_OFFSET_SAR_BASE0 0x0018 ++#define M2M_OFFSET_SAR_BASE1 0x001C ++#define M2M_OFFSET_SAR_CURRENT0 0x0024 ++#define M2M_OFFSET_SAR_CURRENT1 0x0028 ++#define M2M_OFFSET_DAR_BASE0 0x002C ++#define M2M_OFFSET_DAR_BASE1 0x0030 ++#define M2M_OFFSET_DAR_CURRENT0 0x0034 ++#define M2M_OFFSET_DAR_CURRENT1 0x003C ++ ++ ++ ++/* 8003_0000 - 8003_ffff: Raster */ ++#define RASTER_OFFSET 0x030000 ++#define RASTER_BASE (EP93XX_AHB_VIRT_BASE|RASTER_OFFSET) ++#define VLINESTOTAL (RASTER_BASE+0x00) ++#define VSYNCSTRTSTOP (RASTER_BASE+0x04) ++#define VACTIVESTRTSTOP (RASTER_BASE+0x08) ++#define VCLKSTRTSTOP (RASTER_BASE+0x0C) ++#define HCLKSTOTAL (RASTER_BASE+0x10) ++#define HSYNCSTRTSTOP (RASTER_BASE+0x14) ++#define HACTIVESTRTSTOP (RASTER_BASE+0x18) ++#define HCLKSTRTSTOP (RASTER_BASE+0x1C) ++#define BRIGHTNESS (RASTER_BASE+0x20) ++#define VIDEOATTRIBS (RASTER_BASE+0x24) ++#define VIDSCRNPAGE (RASTER_BASE+0x28) ++#define VIDSCRNHPG (RASTER_BASE+0x2C) ++#define SCRNLINES (RASTER_BASE+0x30) ++#define LINELENGTH (RASTER_BASE+0x34) ++#define VLINESTEP (RASTER_BASE+0x38) ++#define LINECARRY (RASTER_BASE+0x3C) ++#define BLINKRATE (RASTER_BASE+0x40) ++#define BLINKMASK (RASTER_BASE+0x44) ++#define BLINKPATTRN (RASTER_BASE+0x48) ++#define PATTRNMASK (RASTER_BASE+0x4C) ++#define BG_OFFSET (RASTER_BASE+0x50) ++#define PIXELMODE (RASTER_BASE+0x54) ++#define PARLLIFOUT (RASTER_BASE+0x58) ++#define PARLLIFIN (RASTER_BASE+0x5C) ++#define CURSOR_ADR_START (RASTER_BASE+0x60) ++#define CURSOR_ADR_RESET (RASTER_BASE+0x64) ++#define CURSORSIZE (RASTER_BASE+0x68) ++#define CURSORCOLOR1 (RASTER_BASE+0x6C) ++#define CURSORCOLOR2 (RASTER_BASE+0x70) ++#define CURSORXYLOC (RASTER_BASE+0x74) ++#define CURSOR_DHSCAN_LH_YLOC (RASTER_BASE+0x78) ++#define RASTER_SWLOCK (RASTER_BASE+0x7C) ++#define GS_LUT (RASTER_BASE+0x80) ++#define RASTER_TCR (RASTER_BASE+0x100) ++#define RASTER_TISRA (RASTER_BASE+0x104) ++#define RASTER_TISRB (RASTER_BASE+0x108) ++#define CURSOR_TISR (RASTER_BASE+0x10C) ++#define RASTER_TOCRA (RASTER_BASE+0x110) ++#define RASTER_TOCRB (RASTER_BASE+0x114) ++#define FIFO_TOCRA (RASTER_BASE+0x118) ++#define FIFO_TOCRB (RASTER_BASE+0x11C) ++#define BLINK_TISR (RASTER_BASE+0x120) ++#define DAC_TISRA (RASTER_BASE+0x124) ++#define DAC_TISRB (RASTER_BASE+0x128) ++#define SHIFT_TISR (RASTER_BASE+0x12C) ++#define DACMUX_TOCRA (RASTER_BASE+0x130) ++#define DACMUX_TOCRB (RASTER_BASE+0x134) ++#define PELMUX_TOCR (RASTER_BASE+0x138) ++#define VIDEO_TOCRA (RASTER_BASE+0x13C) ++#define VIDEO_TOCRB (RASTER_BASE+0x140) ++#define YCRCB_TOCR (RASTER_BASE+0x144) ++#define CURSOR_TOCR (RASTER_BASE+0x148) ++#define VIDEO_TOCRC (RASTER_BASE+0x14C) ++#define SHIFT_TOCR (RASTER_BASE+0x150) ++#define BLINK_TOCR (RASTER_BASE+0x154) ++#define RASTER_TCER (RASTER_BASE+0x180) ++#define SIGVAL (RASTER_BASE+0x200) ++#define SIGCTL (RASTER_BASE+0x204) ++#define VSIGSTRTSTOP (RASTER_BASE+0x208) ++#define HSIGSTRTSTOP (RASTER_BASE+0x20C) ++#define SIGCLR (RASTER_BASE+0x210) ++#define ACRATE (RASTER_BASE+0x214) ++#define LUTCONT (RASTER_BASE+0x218) ++#define VBLANKSTRTSTOP (RASTER_BASE+0x228) ++#define HBLANKSTRTSTOP (RASTER_BASE+0x22C) ++#define LUT (RASTER_BASE+0x400) ++#define CURSORBLINK1 (RASTER_BASE+0x21C) ++#define CURSORBLINK2 (RASTER_BASE+0x220) ++#define CURSORBLINK (RASTER_BASE+0x224) ++#define EOLOFFSET (RASTER_BASE+0x230) ++#define FIFOLEVEL (RASTER_BASE+0x234) ++#define GS_LUT2 (RASTER_BASE+0x280) ++#define GS_LUT3 (RASTER_BASE+0x300) ++#define COLOR_LUT (RASTER_BASE+0x400) ++ ++/* 8004_0000 - 8004_ffff: Graphics */ ++#define GRAPHICS_OFFSET 0x040000 ++#define GRAPHICS_BASE (EP93XX_AHB_VIRT_BASE|GRAPHICS_OFFSET) ++#define SRCPIXELSTRT (GRAPHICS_BASE+0x00) ++#define DESTPIXELSTRT (GRAPHICS_BASE+0x04) ++#define BLKSRCSTRT (GRAPHICS_BASE+0x08) ++#define BLKDSTSTRT (GRAPHICS_BASE+0x0C) ++#define BLKSRCWIDTH (GRAPHICS_BASE+0x10) ++#define SRCLINELENGTH (GRAPHICS_BASE+0x14) ++#define BLKDESTWIDTH (GRAPHICS_BASE+0x18) ++#define BLKDESTHEIGHT (GRAPHICS_BASE+0x1C) ++#define DESTLINELENGTH (GRAPHICS_BASE+0x20) ++#define BLOCKCTRL (GRAPHICS_BASE+0x24) ++#define TRANSPATTRN (GRAPHICS_BASE+0x28) ++#define BLOCKMASK (GRAPHICS_BASE+0x2C) ++#define BACKGROUND (GRAPHICS_BASE+0x30) ++#define LINEINC (GRAPHICS_BASE+0x34) ++#define LINEINIT (GRAPHICS_BASE+0x38) ++#define LINEPATTRN (GRAPHICS_BASE+0x3C) ++ ++ ++/* 800B_0000 - 800B_FFFF: VIC 0 */ ++#define VIC0_OFFSET 0x0B0000 ++#define VIC0_BASE (EP93XX_AHB_VIRT_BASE|VIC0_OFFSET) ++#define VIC0 (VIC0_BASE+0x000) ++#define VIC0IRQSTATUS (VIC0_BASE+0x000) /* R IRQ status register */ ++#define VIC0FIQSTATUS (VIC0_BASE+0x004) /* R FIQ status register */ ++#define VIC0RAWINTR (VIC0_BASE+0x008) /* R Raw interrupt status register */ ++#define VIC0INTSELECT (VIC0_BASE+0x00C) /* R/W Interrupt select register */ ++#define VIC0INTENABLE (VIC0_BASE+0x010) /* R/W Interrupt enable register */ ++#define VIC0INTENCLEAR (VIC0_BASE+0x014) /* W Interrupt enable clear register */ ++#define VIC0SOFTINT (VIC0_BASE+0x018) /* R/W Software interrupt register */ ++#define VIC0SOFTINTCLEAR (VIC0_BASE+0x01C) /* R/W Software interrupt clear register */ ++#define VIC0PROTECTION (VIC0_BASE+0x020) /* R/W Protection enable register */ ++#define VIC0VECTADDR (VIC0_BASE+0x030) /* R/W Vector address register */ ++#define VIC0DEFVECTADDR (VIC0_BASE+0x034) /* R/W Default vector address register */ ++#define VIC0VECTADDR00 (VIC0_BASE+0x100) /* R/W Vector address 00 register */ ++#define VIC0VECTADDR01 (VIC0_BASE+0x104) /* R/W Vector address 01 register */ ++#define VIC0VECTADDR02 (VIC0_BASE+0x108) /* R/W Vector address 02 register */ ++#define VIC0VECTADDR03 (VIC0_BASE+0x10C) /* R/W Vector address 03 register */ ++#define VIC0VECTADDR04 (VIC0_BASE+0x110) /* R/W Vector address 04 register */ ++#define VIC0VECTADDR05 (VIC0_BASE+0x114) /* R/W Vector address 05 register */ ++#define VIC0VECTADDR06 (VIC0_BASE+0x118) /* R/W Vector address 06 register */ ++#define VIC0VECTADDR07 (VIC0_BASE+0x11C) /* R/W Vector address 07 register */ ++#define VIC0VECTADDR08 (VIC0_BASE+0x120) /* R/W Vector address 08 register */ ++#define VIC0VECTADDR09 (VIC0_BASE+0x124) /* R/W Vector address 09 register */ ++#define VIC0VECTADDR10 (VIC0_BASE+0x128) /* R/W Vector address 10 register */ ++#define VIC0VECTADDR11 (VIC0_BASE+0x12C) /* R/W Vector address 11 register */ ++#define VIC0VECTADDR12 (VIC0_BASE+0x130) /* R/W Vector address 12 register */ ++#define VIC0VECTADDR13 (VIC0_BASE+0x134) /* R/W Vector address 13 register */ ++#define VIC0VECTADDR14 (VIC0_BASE+0x138) /* R/W Vector address 14 register */ ++#define VIC0VECTADDR15 (VIC0_BASE+0x13C) /* R/W Vector address 15 register */ ++#define VIC0VECTCNTL00 (VIC0_BASE+0x200) /* R/W Vector control 00 register */ ++#define VIC0VECTCNTL01 (VIC0_BASE+0x204) /* R/W Vector control 01 register */ ++#define VIC0VECTCNTL02 (VIC0_BASE+0x208) /* R/W Vector control 02 register */ ++#define VIC0VECTCNTL03 (VIC0_BASE+0x20C) /* R/W Vector control 03 register */ ++#define VIC0VECTCNTL04 (VIC0_BASE+0x210) /* R/W Vector control 04 register */ ++#define VIC0VECTCNTL05 (VIC0_BASE+0x214) /* R/W Vector control 05 register */ ++#define VIC0VECTCNTL06 (VIC0_BASE+0x218) /* R/W Vector control 06 register */ ++#define VIC0VECTCNTL07 (VIC0_BASE+0x21C) /* R/W Vector control 07 register */ ++#define VIC0VECTCNTL08 (VIC0_BASE+0x220) /* R/W Vector control 08 register */ ++#define VIC0VECTCNTL09 (VIC0_BASE+0x224) /* R/W Vector control 09 register */ ++#define VIC0VECTCNTL10 (VIC0_BASE+0x228) /* R/W Vector control 10 register */ ++#define VIC0VECTCNTL11 (VIC0_BASE+0x22C) /* R/W Vector control 11 register */ ++#define VIC0VECTCNTL12 (VIC0_BASE+0x230) /* R/W Vector control 12 register */ ++#define VIC0VECTCNTL13 (VIC0_BASE+0x234) /* R/W Vector control 13 register */ ++#define VIC0VECTCNTL14 (VIC0_BASE+0x238) /* R/W Vector control 14 register */ ++#define VIC0VECTCNTL15 (VIC0_BASE+0x23C) /* R/W Vector control 15 register */ ++#define VIC0ITCR (VIC0_BASE+0x300) /* R/W Test control register */ ++#define VIC0ITIP1 (VIC0_BASE+0x304) /* R Test input register (nVICIRQIN/nVICFIQIN)*/ ++#define VIC0ITIP2 (VIC0_BASE+0x308) /* R Test input register (VICVECTADDRIN) */ ++#define VIC0ITOP1 (VIC0_BASE+0x30C) /* R Test output register (nVICIRQ/nVICFIQ) */ ++#define VIC0ITOP2 (VIC0_BASE+0x310) /* R Test output register (VICVECTADDROUT) */ ++#define VIC0PERIPHID0 (VIC0_BASE+0xFE0) /* R Peripheral ID register bits 7:0 */ ++#define VIC0PERIPHID1 (VIC0_BASE+0xFE4) /* R Peripheral ID register bits 15:8 */ ++#define VIC0PERIPHID2 (VIC0_BASE+0xFE8) /* R Peripheral ID register bits 23:16 */ ++#define VIC0PERIPHID3 (VIC0_BASE+0xFEC) /* R Peripheral ID register bits 31:24 */ ++ ++ ++/* 800C_0000 - 800C_FFFF: VIC 0 */ ++#define VIC1_OFFSET 0x0C0000 ++#define VIC1_BASE (EP93XX_AHB_VIRT_BASE|VIC1_OFFSET) ++#define VIC1 (VIC1_BASE+0x000) ++#define VIC1IRQSTATUS (VIC1_BASE+0x000) /* R IRQ status register */ ++#define VIC1FIQSTATUS (VIC1_BASE+0x004) /* R FIQ status register */ ++#define VIC1RAWINTR (VIC1_BASE+0x008) /* R Raw interrupt status register */ ++#define VIC1INTSELECT (VIC1_BASE+0x00C) /* R/W Interrupt select register */ ++#define VIC1INTENABLE (VIC1_BASE+0x010) /* R/W Interrupt enable register */ ++#define VIC1INTENCLEAR (VIC1_BASE+0x014) /* W Interrupt enable clear register */ ++#define VIC1SOFTINT (VIC1_BASE+0x018) /* R/W Software interrupt register */ ++#define VIC1SOFTINTCLEAR (VIC1_BASE+0x01C) /* R/W Software interrupt clear register */ ++#define VIC1PROTECTION (VIC1_BASE+0x020) /* R/W Protection enable register */ ++#define VIC1VECTADDR (VIC1_BASE+0x030) /* R/W Vector address register */ ++#define VIC1DEFVECTADDR (VIC1_BASE+0x034) /* R/W Default vector address register */ ++#define VIC1VECTADDR00 (VIC1_BASE+0x100) /* R/W Vector address 00 register */ ++#define VIC1VECTADDR01 (VIC1_BASE+0x104) /* R/W Vector address 01 register */ ++#define VIC1VECTADDR02 (VIC1_BASE+0x108) /* R/W Vector address 02 register */ ++#define VIC1VECTADDR03 (VIC1_BASE+0x10C) /* R/W Vector address 03 register */ ++#define VIC1VECTADDR04 (VIC1_BASE+0x110) /* R/W Vector address 04 register */ ++#define VIC1VECTADDR05 (VIC1_BASE+0x114) /* R/W Vector address 05 register */ ++#define VIC1VECTADDR06 (VIC1_BASE+0x118) /* R/W Vector address 06 register */ ++#define VIC1VECTADDR07 (VIC1_BASE+0x11C) /* R/W Vector address 07 register */ ++#define VIC1VECTADDR08 (VIC1_BASE+0x120) /* R/W Vector address 08 register */ ++#define VIC1VECTADDR09 (VIC1_BASE+0x124) /* R/W Vector address 09 register */ ++#define VIC1VECTADDR10 (VIC1_BASE+0x128) /* R/W Vector address 10 register */ ++#define VIC1VECTADDR11 (VIC1_BASE+0x12C) /* R/W Vector address 11 register */ ++#define VIC1VECTADDR12 (VIC1_BASE+0x130) /* R/W Vector address 12 register */ ++#define VIC1VECTADDR13 (VIC1_BASE+0x134) /* R/W Vector address 13 register */ ++#define VIC1VECTADDR14 (VIC1_BASE+0x138) /* R/W Vector address 14 register */ ++#define VIC1VECTADDR15 (VIC1_BASE+0x13C) /* R/W Vector address 15 register */ ++#define VIC1VECTCNTL00 (VIC1_BASE+0x200) /* R/W Vector control 00 register */ ++#define VIC1VECTCNTL01 (VIC1_BASE+0x204) /* R/W Vector control 01 register */ ++#define VIC1VECTCNTL02 (VIC1_BASE+0x208) /* R/W Vector control 02 register */ ++#define VIC1VECTCNTL03 (VIC1_BASE+0x20C) /* R/W Vector control 03 register */ ++#define VIC1VECTCNTL04 (VIC1_BASE+0x210) /* R/W Vector control 04 register */ ++#define VIC1VECTCNTL05 (VIC1_BASE+0x214) /* R/W Vector control 05 register */ ++#define VIC1VECTCNTL06 (VIC1_BASE+0x218) /* R/W Vector control 06 register */ ++#define VIC1VECTCNTL07 (VIC1_BASE+0x21C) /* R/W Vector control 07 register */ ++#define VIC1VECTCNTL08 (VIC1_BASE+0x220) /* R/W Vector control 08 register */ ++#define VIC1VECTCNTL09 (VIC1_BASE+0x224) /* R/W Vector control 09 register */ ++#define VIC1VECTCNTL10 (VIC1_BASE+0x228) /* R/W Vector control 10 register */ ++#define VIC1VECTCNTL11 (VIC1_BASE+0x22C) /* R/W Vector control 11 register */ ++#define VIC1VECTCNTL12 (VIC1_BASE+0x230) /* R/W Vector control 12 register */ ++#define VIC1VECTCNTL13 (VIC1_BASE+0x234) /* R/W Vector control 13 register */ ++#define VIC1VECTCNTL14 (VIC1_BASE+0x238) /* R/W Vector control 14 register */ ++#define VIC1VECTCNTL15 (VIC1_BASE+0x23C) /* R/W Vector control 15 register */ ++#define VIC1ITCR (VIC1_BASE+0x300) /* R/W Test control register */ ++#define VIC1ITIP1 (VIC1_BASE+0x304) /* R Test input register (nVICIRQIN/nVICFIQIN)*/ ++#define VIC1ITIP2 (VIC1_BASE+0x308) /* R Test input register (VICVECTADDRIN) */ ++#define VIC1ITOP1 (VIC1_BASE+0x30C) /* R Test output register (nVICIRQ/nVICFIQ) */ ++#define VIC1ITOP2 (VIC1_BASE+0x310) /* R Test output register (VICVECTADDROUT) */ ++#define VIC1PERIPHID0 (VIC1_BASE+0xFE0) /* R Peripheral ID register bits 7:0 */ ++#define VIC1PERIPHID1 (VIC1_BASE+0xFE4) /* R Peripheral ID register bits 15:8 */ ++#define VIC1PERIPHID2 (VIC1_BASE+0xFE8) /* R Peripheral ID register bits 23:16 */ ++#define VIC1PERIPHID3 (VIC1_BASE+0xFEC) /* R Peripheral ID register bits 31:24 */ ++ ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////////////// ++///////////////////////////////////APB///////////////////////////////////////////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////////////////////////////////// ++/* 8081_0000 - 8081_ffff: Timers */ ++#define TIMERS_OFFSET 0x010000 ++#define TIMERS_BASE (EP93XX_APB_VIRT_BASE|TIMERS_OFFSET) ++ ++#define TIMER1LOAD (TIMERS_BASE+0x00) ++#define TIMER1VALUE (TIMERS_BASE+0x04) ++#define TIMER1CONTROL (TIMERS_BASE+0x08) ++#define TIMER1CLEAR (TIMERS_BASE+0x0C) ++#define TIMER1TEST (TIMERS_BASE+0x10) ++ ++#define TIMER2LOAD (TIMERS_BASE+0x20) ++#define TIMER2VALUE (TIMERS_BASE+0x24) ++#define TIMER2CONTROL (TIMERS_BASE+0x28) ++#define TIMER2CLEAR (TIMERS_BASE+0x2C) ++#define TIMER2TEST (TIMERS_BASE+0x30) ++ ++#define TIMER3LOAD (TIMERS_BASE+0x80) ++#define TIMER3VALUE (TIMERS_BASE+0x84) ++#define TIMER3CONTROL (TIMERS_BASE+0x88) ++#define TIMER3CLEAR (TIMERS_BASE+0x8C) ++#define TIMER3TEST (TIMERS_BASE+0x90) ++ ++#define TTIMERBZCONT (TIMERS_BASE+0x40) ++ ++#define TIMER4VALUELOW (TIMERS_BASE+0x60) ++#define TIMER4VALUEHIGH (TIMERS_BASE+0x64) ++ ++ ++/* 8082_0000 - 8082_ffff: I2S */ ++#define I2S_OFFSET 0x020000 ++#define I2S_BASE (EP93XX_APB_VIRT_BASE|I2S_OFFSET) ++#define I2S_PHYS_BASE (EP93XX_APB_PHYS_BASE + I2S_OFFSET) ++ ++ ++ ++#define I2STxClkCfg (I2S_BASE+0x00) /* 8082.0000 R/W Transmitter clock config register */ ++#define I2SRxClkCfg (I2S_BASE+0x04) /* 8082.0004 R/W Receiver clock config register */ ++#define I2SGlSts (I2S_BASE+0x08) /* 8082.0008 R/W SAI Global Status register. */ ++#define I2SGlCtrl (I2S_BASE+0x0C) /* 8082.000C R/W SAI Global Control register */ ++ ++#define I2STX0Lft (I2S_BASE+0x10) /* 8082.0010 R/W Left TX data reg for channel 0 */ ++#define I2STX0Rt (I2S_BASE+0x14) /* 8082.0014 R/W Right TX data reg for channel 0 */ ++#define I2STX1Lft (I2S_BASE+0x18) /* 8082.0018 R/W Left TX data reg for channel 1 */ ++#define I2STX1Rt (I2S_BASE+0x1C) /* 8082.001C R/W Right TX data reg for channel 1 */ ++#define I2STX2Lft (I2S_BASE+0x20) /* 8082.0020 R/W Left TX data reg for channel 2 */ ++#define I2STX2Rt (I2S_BASE+0x24) /* 8082.0024 R/W Right TX data reg for channel 2 */ ++ ++#define I2STXLinCtrlData (I2S_BASE+0x28) /* 8082.0028 R/W TX Line Control data register */ ++#define I2STXCtrl (I2S_BASE+0x2C) /* 8082.002C R/W TX Control register */ ++#define I2STXWrdLen (I2S_BASE+0x30) /* 8082.0030 R/W TX Word Length */ ++#define I2STX0En (I2S_BASE+0x34) /* 8082.0034 R/W TX0 Channel Enable */ ++#define I2STX1En (I2S_BASE+0x38) /* 8082.0038 R/W TX1 Channel Enable */ ++#define I2STX2En (I2S_BASE+0x3C) /* 8082.003C R/W TX2 Channel Enable */ ++ ++#define I2SRX0Lft (I2S_BASE+0x40) /* 8082.0040 R Left RX data reg for channel 0 */ ++#define I2SRX0Rt (I2S_BASE+0x44) /* 8082.0044 R Right RX data reg for channel 0 */ ++#define I2SRX1Lft (I2S_BASE+0x48) /* 8082.0048 R Left RX data reg for channel 1 */ ++#define I2SRX1Rt (I2S_BASE+0x4C) /* 8082.004c R Right RX data reg for channel 1 */ ++#define I2SRX2Lft (I2S_BASE+0x50) /* 8082.0050 R Left RX data reg for channel 2 */ ++#define I2SRX2Rt (I2S_BASE+0x54) /* 8082.0054 R Right RX data reg for channel 2 */ ++ ++#define I2SRXLinCtrlData (I2S_BASE+0x58) /* 8082.0058 R/W RX Line Control data register */ ++#define I2SRXCtrl (I2S_BASE+0x5C) /* 8082.005C R/W RX Control register */ ++#define I2SRXWrdLen (I2S_BASE+0x60) /* 8082.0060 R/W RX Word Length */ ++#define I2SRX0En (I2S_BASE+0x64) /* 8082.0064 R/W RX0 Channel Enable */ ++#define I2SRX1En (I2S_BASE+0x68) /* 8082.0068 R/W RX1 Channel Enable */ ++#define I2SRX2En (I2S_BASE+0x6C) /* 8082.006C R/W RX2 Channel Enable */ ++ ++ ++ ++ ++/* 8084_0000 - 8084_ffff: GPIO */ ++#define GPIO_OFFSET 0x040000 ++#define GPIO_BASE (EP93XX_APB_VIRT_BASE|GPIO_OFFSET) ++#define GPIO_PADR (GPIO_BASE+0x00) ++#define GPIO_PBDR (GPIO_BASE+0x04) ++#define GPIO_PCDR (GPIO_BASE+0x08) ++#define GPIO_PDDR (GPIO_BASE+0x0C) ++#define GPIO_PADDR (GPIO_BASE+0x10) ++#define GPIO_PBDDR (GPIO_BASE+0x14) ++#define GPIO_PCDDR (GPIO_BASE+0x18) ++#define GPIO_PDDDR (GPIO_BASE+0x1C) ++#define GPIO_PEDR (GPIO_BASE+0x20) ++#define GPIO_PEDDR (GPIO_BASE+0x24) ++// #define 0x8084.0028 Reserved ++// #define 0x8084.002C Reserved ++#define GPIO_PFDR (GPIO_BASE+0x30) ++#define GPIO_PFDDR (GPIO_BASE+0x34) ++#define GPIO_PGDR (GPIO_BASE+0x38) ++#define GPIO_PGDDR (GPIO_BASE+0x3C) ++#define GPIO_PHDR (GPIO_BASE+0x40) ++#define GPIO_PHDDR (GPIO_BASE+0x44) ++// #define 0x8084.0048 RAZ RAZ ++#define GPIO_FINTTYPE1 (GPIO_BASE+0x4C) ++#define GPIO_FINTTYPE2 (GPIO_BASE+0x50) ++#define GPIO_FEOI (GPIO_BASE+0x54) /* WRITE ONLY - READ UNDEFINED */ ++#define GPIO_FINTEN (GPIO_BASE+0x58) ++#define GPIO_INTSTATUSF (GPIO_BASE+0x5C) ++#define GPIO_RAWINTSTASUSF (GPIO_BASE+0x60) ++#define GPIO_FDB (GPIO_BASE+0x64) ++#define GPIO_PAPINDR (GPIO_BASE+0x68) ++#define GPIO_PBPINDR (GPIO_BASE+0x6C) ++#define GPIO_PCPINDR (GPIO_BASE+0x70) ++#define GPIO_PDPINDR (GPIO_BASE+0x74) ++#define GPIO_PEPINDR (GPIO_BASE+0x78) ++#define GPIO_PFPINDR (GPIO_BASE+0x7C) ++#define GPIO_PGPINDR (GPIO_BASE+0x80) ++#define GPIO_PHPINDR (GPIO_BASE+0x84) ++#define GPIO_AINTTYPE1 (GPIO_BASE+0x90) ++#define GPIO_AINTTYPE2 (GPIO_BASE+0x94) ++#define GPIO_AEOI (GPIO_BASE+0x98) /* WRITE ONLY - READ UNDEFINED */ ++#define GPIO_AINTEN (GPIO_BASE+0x9C) ++#define GPIO_INTSTATUSA (GPIO_BASE+0xA0) ++#define GPIO_RAWINTSTSTISA (GPIO_BASE+0xA4) ++#define GPIO_ADB (GPIO_BASE+0xA8) ++#define GPIO_BINTTYPE1 (GPIO_BASE+0xAC) ++#define GPIO_BINTTYPE2 (GPIO_BASE+0xB0) ++#define GPIO_BEOI (GPIO_BASE+0xB4) /* WRITE ONLY - READ UNDEFINED */ ++#define GPIO_BINTEN (GPIO_BASE+0xB8) ++#define GPIO_INTSTATUSB (GPIO_BASE+0xBC) ++#define GPIO_RAWINTSTSTISB (GPIO_BASE+0xC0) ++#define GPIO_BDB (GPIO_BASE+0xC4) ++#define GPIO_EEDRIVE (GPIO_BASE+0xC8) ++//#define Reserved (GPIO_BASE+0xCC) ++#define GPIO_TCR (GPIO_BASE+0xD0) /* Test Registers */ ++#define GPIO_TISRA (GPIO_BASE+0xD4) /* Test Registers */ ++#define GPIO_TISRB (GPIO_BASE+0xD8) /* Test Registers */ ++#define GPIO_TISRC (GPIO_BASE+0xDC) /* Test Registers */ ++#define GPIO_TISRD (GPIO_BASE+0xE0) /* Test Registers */ ++#define GPIO_TISRE (GPIO_BASE+0xE4) /* Test Registers */ ++#define GPIO_TISRF (GPIO_BASE+0xE8) /* Test Registers */ ++#define GPIO_TISRG (GPIO_BASE+0xEC) /* Test Registers */ ++#define GPIO_TISRH (GPIO_BASE+0xF0) /* Test Registers */ ++#define GPIO_TCER (GPIO_BASE+0xF4) /* Test Registers */ ++ ++ ++/* 8088_0000 - 8088_ffff: Ac97 Controller (AAC) */ ++#define AC97_OFFSET 0x080000 ++#define AC97_BASE (EP93XX_APB_VIRT_BASE|AC97_OFFSET) ++#define EP93XX_AC97_PHY_BASE (EP93XX_APB_PHYS_BASE|AC97_OFFSET) ++#define AC97DR1 (AC97_BASE+0x00) /* 8088.0000 R/W Data read or written from/to FIFO1 */ ++#define AC97RXCR1 (AC97_BASE+0x04) /* 8088.0004 R/W Control register for receive */ ++#define AC97TXCR1 (AC97_BASE+0x08) /* 8088.0008 R/W Control register for transmit */ ++#define AC97SR1 (AC97_BASE+0x0C) /* 8088.000C R Status register */ ++#define AC97RISR1 (AC97_BASE+0x10) /* 8088.0010 R Raw interrupt status register */ ++#define AC97ISR1 (AC97_BASE+0x14) /* 8088.0014 R Interrupt Status */ ++#define AC97IE1 (AC97_BASE+0x18) /* 8088.0018 R/W Interrupt Enable */ ++ /* 8088.001C Reserved - RAZ */ ++#define AC97DR2 (AC97_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */ ++#define AC97RXCR2 (AC97_BASE+0x24) /* 8088.0024 R/W Control register for receive */ ++#define AC97TXCR2 (AC97_BASE+0x28) /* 8088.0028 R/W Control register for transmit */ ++#define AC97SR2 (AC97_BASE+0x2C) /* 8088.002C R Status register */ ++#define AC97RISR2 (AC97_BASE+0x30) /* 8088.0030 R Raw interrupt status register */ ++#define AC97ISR2 (AC97_BASE+0x34) /* 8088.0034 R Interrupt Status */ ++#define AC97IE2 (AC97_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */ ++ /* 8088.003C Reserved - RAZ */ ++#define AC97DR3 (AC97_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */ ++#define AC97RXCR3 (AC97_BASE+0x44) /* 8088.0044 R/W Control register for receive */ ++#define AC97TXCR3 (AC97_BASE+0x48) /* 8088.0048 R/W Control register for transmit */ ++#define AC97SR3 (AC97_BASE+0x4C) /* 8088.004C R Status register */ ++#define AC97RISR3 (AC97_BASE+0x50) /* 8088.0050 R Raw interrupt status register */ ++#define AC97ISR3 (AC97_BASE+0x54) /* 8088.0054 R Interrupt Status */ ++#define AC97IE3 (AC97_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */ ++ /* 8088.005C Reserved - RAZ */ ++#define AC97DR2 (AC97_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */ ++#define AC97RXCR2 (AC97_BASE+0x24) /* 8088.0024 R/W Control register for receive */ ++#define AC97TXCR2 (AC97_BASE+0x28) /* 8088.0028 R/W Control register for transmit */ ++#define AC97SR2 (AC97_BASE+0x2C) /* 8088.002C R Status register */ ++#define AC97RISR2 (AC97_BASE+0x30) /* 8088.0030 R Raw interrupt status register */ ++#define AC97ISR2 (AC97_BASE+0x34) /* 8088.0034 R Interrupt Status */ ++#define AC97IE2 (AC97_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */ ++ /* 8088.003C Reserved - RAZ */ ++#define AC97DR3 (AC97_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */ ++#define AC97RXCR3 (AC97_BASE+0x44) /* 8088.0044 R/W Control register for receive */ ++#define AC97TXCR3 (AC97_BASE+0x48) /* 8088.0048 R/W Control register for transmit */ ++#define AC97SR3 (AC97_BASE+0x4C) /* 8088.004C R Status register */ ++#define AC97RISR3 (AC97_BASE+0x50) /* 8088.0050 R Raw interrupt status register */ ++#define AC97ISR3 (AC97_BASE+0x54) /* 8088.0054 R Interrupt Status */ ++#define AC97IE3 (AC97_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */ ++ /* 8088.005C Reserved - RAZ */ ++#define AC97DR4 (AC97_BASE+0x60) /* 8088.0060 R/W Data read or written from/to FIFO4. */ ++#define AC97RXCR4 (AC97_BASE+0x64) /* 8088.0064 R/W Control register for receive */ ++#define AC97TXCR4 (AC97_BASE+0x68) /* 8088.0068 R/W Control register for transmit */ ++#define AC97SR4 (AC97_BASE+0x6C) /* 8088.006C R Status register */ ++#define AC97RISR4 (AC97_BASE+0x70) /* 8088.0070 R Raw interrupt status register */ ++#define AC97ISR4 (AC97_BASE+0x74) /* 8088.0074 R Interrupt Status */ ++#define AC97IE4 (AC97_BASE+0x78) /* 8088.0078 R/W Interrupt Enable */ ++ /* 8088.007C Reserved - RAZ */ ++#define AC97S1DATA (AC97_BASE+0x80) /* 8088.0080 R/W Data received/transmitted on SLOT1 */ ++#define AC97S2DATA (AC97_BASE+0x84) /* 8088.0084 R/W Data received/transmitted on SLOT2 */ ++#define AC97S12DATA (AC97_BASE+0x88) /* 8088.0088 R/W Dat |