diff options
39 files changed, 2489 insertions, 112 deletions
diff --git a/conf/bitbake.conf b/conf/bitbake.conf index 95ee9c6136..5d4ec2b39b 100644 --- a/conf/bitbake.conf +++ b/conf/bitbake.conf @@ -508,7 +508,7 @@ E_URI = "http://enlightenment.freedesktop.org/files" FREEBSD_MIRROR = "ftp://ftp.freebsd.org/pub/FreeBSD/" FREEDESKTOP_CVS = "cvs://anoncvs:anoncvs@anoncvs.freedesktop.org/cvs" FREESMARTPHONE_GIT = "git://git.freesmartphone.org" -GENTOO_MIRROR = "http://distro.ibiblio.org/pub/linux/distributions/gentoo/distfiles" +GENTOO_MIRROR = "http://distfiles.gentoo.org/distfiles" GNOME_GIT = "git://git.gnome.org" GNOME_MIRROR = "http://ftp.gnome.org/pub/GNOME/sources" GNU_MIRROR = "ftp://ftp.gnu.org/gnu" diff --git a/conf/checksums.ini b/conf/checksums.ini index d8392d1507..2d7e77c515 100644 --- a/conf/checksums.ini +++ b/conf/checksums.ini @@ -1870,6 +1870,10 @@ sha256=9d1fff10d391cb64890bb8e0050d3f023520a8dd5aee43c4d3f9c6f8611da668 md5=a3bcd50138d29c1d23a0d378edb52dfe sha256=019b98442d4debcd74d759043884b4b0ed48a2bef425649bfe3061d00e854fc5 +[ftp://www.at91.com/pub/buildroot/at91bootstrap-2.11.tar.bz2] +md5=8962bd639d189e1d3328b6c056d96099 +sha256=09ef85da45a086c27b6a43a457f81bf44913e7fa2e854e72281aa3c25c00874b + [ftp://www.at91.com/pub/buildroot/at91bootstrap-2.3.tar.bz2] md5=a29b3f07e623d20894ab23335daf5da5 sha256=d598d078c24a24b13eac8a219a4ab05499909404cbd4efcb8641fdcde28464c0 @@ -3910,6 +3914,10 @@ sha256=73f3b92c0f85ab2bf0f9bb18f928a8b84cacdbb459f3a530df540d4ddf134405 md5=7bc5c89870d47c88f407fcfd666c739d sha256=102bb7a5d329dd6831bc8a923fa0b5d7634efa215e3d15377630d9b738df49da +[http://www.kernel.org/pub/linux/network/connman/connman-0.19.tar.gz] +md5=3d61c5db55d225c3efbf4c950dc0842f +sha256=cc4a4b73d8d7b0e19dd2dd274ba91acb67b14c84fc448a921d1359e25e4d2df0 + [ftp://ftp.moblin.org/connman/releases/connman-0.2.tar.gz] md5=bf48aa07d3c1e5fe272c7f139bc01fc9 sha256=eacc3c57cffb411b09d834d2225323cde5676165b5d2fc2a27b16cde98e3ba97 @@ -10174,6 +10182,10 @@ sha256=cae6ed86296d01be98ee3be0c224c4323eee508941a7f162a0366d56655afe06 md5=62749c6cdf28ce31aae335092fa107df sha256=cae6ed86296d01be98ee3be0c224c4323eee508941a7f162a0366d56655afe06 +[http://downloads.sourceforge.net/hdparm/hdparm-9.15.tar.gz] +md5=0524dd10ad986285ff4eeb3507f7471c +sha256=689a413119c4d670ed95b9ac24511655c4805db678ad93866ab1036a0ba4d6bf + [http://handhelds.org/~zecke/oe_packages/hexatrolic-103beta3-zecke1.tar.bz2] md5=1d9420e8b5a6d5fa491c458ffafd4adb sha256=b60a5358e56e676529e7d3d655d5107a76b9a2434e38952711fea794f65721ce @@ -14446,6 +14458,10 @@ sha256=d112f79489d5deabc0cbb48c6192353d488d9e62c28752eda091f585f2e41176 md5=df2447c23750ef2b4a314200feacc2ee sha256=c9bdc5820bc283dcfefba4d4f632c9083adffe5a06c21e089ee123209d229ecf +[http://downloads.sourceforge.net/libusb/libusb-1.0.1.tar.bz2] +md5=8fb0e066678a0d294894b5b2969cb4b3 +sha256=510b9c7339e878324066ec1cb74c0f67d5df858065155a3239999ff911257d45 + [http://downloads.sourceforge.net/libusb/libusb-compat-0.1.0-beta1.tar.bz2] md5=3d9f7c3966d24c6e2d58becac96e4e27 sha256=9365108d71cecb78055de4df6eeb2fadf0fe9143ef105bcb6934dcf391983a49 @@ -22834,6 +22850,10 @@ sha256=404df2c479517020290be9847191523c1fcbd3e929e8bb1191a7832209d04af8 md5=490d13c141ba7b4a96582541ea83a461 sha256=944ab9cfcfc9a4bd7efeecf32ea609fa6517970a9708c44eee6d5750c4ff8e0c +[http://mirrors.m0k.org/transmission/files/transmission-1.61.tar.bz2] +md5=0b0428f4a6237a64dc8b7d378ace3f06 +sha256=3bc5bf49ed02a3d93b4b9b71c7814960e972c1bde4e9fb83b2cd500c83ae4a9a + [http://xorg.freedesktop.org/releases/individual/proto/trapproto-3.4.3.tar.bz2] md5=3b713239e5e6b269b31cb665563358df sha256=ff32a0d3bc696cadc3457be9c85e9818af2b6daa2f159188bb01aad7e932a0e1 @@ -23190,6 +23210,10 @@ sha256=c750c8180057385eaa0844f1148d6f0223b986da322773195eab44b33b97c19f md5=b2c104938c1c3eb47e7605432bbd3157 sha256=c750c8180057385eaa0844f1148d6f0223b986da322773195eab44b33b97c19f +[http://uim.freedesktop.org/releases/uim/stable/uim-1.3.1.tar.bz2] +md5=2832e23d4778bbacbfa4b49bf642d667 +sha256=ed2cfa15018a4fd2557e875f66fcb3f0b9dabe12fa0700aa2f11cca69c2cb256 + [http://uim.googlecode.com/files/uim-1.3.1.tar.bz2] md5=2832e23d4778bbacbfa4b49bf642d667 sha256=ed2cfa15018a4fd2557e875f66fcb3f0b9dabe12fa0700aa2f11cca69c2cb256 diff --git a/conf/distro/include/sane-srcrevs.inc b/conf/distro/include/sane-srcrevs.inc index bd78008dd0..add9586c7e 100644 --- a/conf/distro/include/sane-srcrevs.inc +++ b/conf/distro/include/sane-srcrevs.inc @@ -111,7 +111,7 @@ SRCREV_pn-libowl ?= "277" SRCREV_pn-libxcalibrate ?= "209d83af61ed38a002c8096377deac292b3e396c" SRCREV_pn-libxosd ?= "627" SRCREV_pn-linux-bfin ?= "3758" -SRCREV_pn-linux-bug ?= "8996" +SRCREV_pn-linux-bug ?= "9110" SRCREV_pn-linux-hackndev-2.6 ?= "1308" SRCREV_pn-linux-ixp4xx ?= "1089" SRCREV_pn-linux-openmoko-2.6.24 ?= "fb42ce6724576fc173faf8abfb04aa2c36d213b7" @@ -131,7 +131,7 @@ SRCREV_pn-matchbox-panel-2 ?= "1626" SRCREV_pn-matchbox-stroke ?= "1820" SRCREV_pn-mickeydbus ?= "f894801916cc4d0e912e4553490dc215276c52a9" SRCREV_pn-mickeyterm ?= "f894801916cc4d0e912e4553490dc215276c52a9" -SRCREV_pn-midori ?= "f30dff433056e239ca775d16f343bdb249f1a338" +SRCREV_pn-midori ?= "eaaed697bf962862b6f393c6b1aceeb04df7414b" SRCREV_pn-moblin-proto ?= "8f2cb524fe06555182c25b4ba3202d7b368ac0ce" SRCREV_pn-moko-gtk-engine ?= "4734" SRCREV_pn-mokoko ?= "127" @@ -249,7 +249,7 @@ SRCREV_pn-usbpath-native ?= "3172" SRCREV-pn-vala-dbus-binding-tool-native ?= "55a6bc5dd032731d89c238d274b2898ef02d12f8" SRCREV_pn-vala-terminal ?= "94117f453ce884e9c30b611fae6fc19f85f98f2b" SRCREV_pn-vala-native ?= "6cf030120cd7f6a76a5d766d7420aea847e02cfd" -SRCREV_pn-webkit-gtk ?= "43434" +SRCREV_pn-webkit-gtk ?= "43635" SRCREV_pn-wlan-ng-modules ?= "1859" SRCREV_pn-wlan-ng-utils ?= "1859" SRCREV_pn-wmiconfig ?= "4522" diff --git a/conf/machine/include/kirkwood.inc b/conf/machine/include/kirkwood.inc index f58feb686c..9e6f130c35 100644 --- a/conf/machine/include/kirkwood.inc +++ b/conf/machine/include/kirkwood.inc @@ -11,7 +11,7 @@ USE_DEVFS = "0" PREFERRED_PROVIDER_virtual/bootloader = "" PREFERRED_PROVIDER_virtual/kernel = "linux-kirkwood" -MACHINE_KERNEL_PR = "r1" +MACHINE_KERNEL_PR = "r5" IMAGE_FSTYPES += "tar.gz ubi" SERIAL_CONSOLE = "ttyS0 115200" diff --git a/recipes/at91bootstrap/at91bootstrap-2.11/0001-AFEB9260-support-thumb-support.patch b/recipes/at91bootstrap/at91bootstrap-2.11/0001-AFEB9260-support-thumb-support.patch new file mode 100644 index 0000000000..ddeedc2d22 --- /dev/null +++ b/recipes/at91bootstrap/at91bootstrap-2.11/0001-AFEB9260-support-thumb-support.patch @@ -0,0 +1,1554 @@ +From c628ebaf33fb1054b391c96225565a43df0b375b Mon Sep 17 00:00:00 2001 +From: slapin <slapin@builder.iar.darktech.org> +Date: Sun, 10 May 2009 02:16:44 +0400 +Subject: [PATCH] AFEB9260 support / thumb support + +--- + Config.in | 5 +- + Makefile | 2 +- + board/Config.in | 47 +++++- + board/afeb9260/afeb9260.c | 251 +++++++++++++++++++++++++++++ + board/afeb9260/afeb9260.h | 126 +++++++++++++++ + board/afeb9260/afeb9260_defconfig | 94 +++++++++++ + board/afeb9260/old/afeb9260.c | 240 +++++++++++++++++++++++++++ + board/afeb9260/old/afeb9260.mk | 8 + + board/afeb9260/old/dataflash/afeb9260.h | 127 +++++++++++++++ + board/afeb9260/old/nandflash/afeb9260ek.h | 151 +++++++++++++++++ + board/afeb9260/old/pll.h | 35 ++++ + board/at91cap9adk/at91cap9adk.c | 6 +- + board/at91sam9260ek/at91sam9260ek.c | 5 + + board/at91sam9261ek/at91sam9261ek.c | 5 + + board/at91sam9263ek/at91sam9263ek.c | 5 + + board/at91sam9g20ek/at91sam9g20ek.c | 6 +- + board/at91sam9rlek/at91sam9rlek.c | 5 + + board/at91sam9xeek/at91sam9xeek.c | 5 + + board/board_cpp.mk | 25 +++ + crt0_gnu.S | 12 ++ + driver/Config.in.dataflash | 2 +- + driver/dataflash.c | 2 +- + include/part.h | 6 + + 23 files changed, 1157 insertions(+), 13 deletions(-) + create mode 100644 board/afeb9260/afeb9260.c + create mode 100644 board/afeb9260/afeb9260.h + create mode 100644 board/afeb9260/afeb9260_defconfig + create mode 100644 board/afeb9260/old/afeb9260.c + create mode 100644 board/afeb9260/old/afeb9260.mk + create mode 100644 board/afeb9260/old/dataflash/afeb9260.h + create mode 100644 board/afeb9260/old/nandflash/afeb9260ek.h + create mode 100644 board/afeb9260/old/pll.h + +diff --git a/Config.in b/Config.in +index e187a27..d7f7a3b 100644 +--- a/Config.in ++++ b/Config.in +@@ -109,4 +109,7 @@ config CONFIG_USER_HW_INIT + help + Initialize Hardware + +- ++config CONFIG_THUMB ++ bool "Build in thumb mode" ++ help ++ Build code in thumb mode +diff --git a/Makefile b/Makefile +index 32bd556..8a53e94 100644 +--- a/Makefile ++++ b/Makefile +@@ -189,7 +189,7 @@ include driver/driver_cpp.mk + # -lgcc : tells the linker to tie in newlib + LDFLAGS+=-nostartfiles -Map=result/$(BOOT_NAME).map --cref + #LDFLAGS+=-lc -lgcc +-LDFLAGS+=-T elf32-littlearm.lds -Ttext $(LINK_ADDR) ++LDFLAGS+=-T elf32-littlearm.lds --gc-sections -Ttext $(LINK_ADDR) + + all: $(obj) $(AT91BOOTSTRAP) .config filesize + +diff --git a/board/Config.in b/board/Config.in +index 074018a..1c2168b 100644 +--- a/board/Config.in ++++ b/board/Config.in +@@ -92,6 +92,17 @@ config CONFIG_AT91CAP9ADK + help + Use the AT91CAP9ADK Development board + ++config CONFIG_AFEB9260 ++ bool "afeb9260" ++ select CONFIG_SDRAM ++ select ALLOW_DATAFLASH ++ select ALLOW_NANDFLASH ++ select ALLOW_CPU_CLK_166MHZ ++ select ALLOW_CPU_CLK_180MHZ ++ select ALLOW_CRYSTAL_18_432MHZ ++ help ++ Use the AFEB9260 Development board ++ + endchoice + + config CONFIG_CHIP +@@ -103,6 +114,7 @@ config CONFIG_CHIP + default "AT91SAM9XE" if CONFIG_AT91SAM9XEEK + default "AT91SAM9G20" if CONFIG_AT91SAM9G20EK + default "AT91CAP9" if CONFIG_AT91CAP9ADK ++ default "AT91SAM9260" if CONFIG_AFEB9260 + help + Name of the board, A Board Support package + (BSP) must be available. +@@ -116,6 +128,7 @@ config CONFIG_BOARD + default "at91sam9xeek" if CONFIG_AT91SAM9XEEK + default "at91sam9g20ek" if CONFIG_AT91SAM9G20EK + default "at91cap9adk" if CONFIG_AT91CAP9ADK ++ default "afeb9260" if CONFIG_AFEB9260 + help + Name of the board, A Board Support package + (BSP) must be available. +@@ -129,6 +142,7 @@ config CONFIG_MACH_TYPE + default "0x44B" if CONFIG_AT91SAM9XEEK + default "0x658" if CONFIG_AT91SAM9G20EK + default "1442" if CONFIG_AT91CAP9ADK ++ default "1859" if CONFIG_AFEB9260 + help + + config CONFIG_LINK_ADDR +@@ -141,6 +155,7 @@ config CONFIG_LINK_ADDR + default "0x200000" if CONFIG_AT91SAM9G20EK + default "0x000000" if CONFIG_AT91CAP9ADK && CONFIG_DATAFLASH + default "0x100000" if CONFIG_AT91CAP9ADK && CONFIG_FLASH ++ default "0x200000" if CONFIG_AFEB9260 + default "0x200000" + help + +@@ -153,11 +168,13 @@ config CONFIG_TOP_OF_MEMORY + default "0x301000" if CONFIG_AT91SAM9XEEK + default "0x301000" if CONFIG_AT91SAM9G20EK + default "0x108000" if CONFIG_AT91CAP9ADK ++ default "0x301000" if CONFIG_AFEB9260 + help + + config CONFIG_BOOTSTRAP_MAXSIZE + string + default "4096" if CONFIG_AT91SAM9260EK ++ default "4096" if CONFIG_AFEB9260 + default "16384" + + choice +@@ -212,6 +229,14 @@ choice + prompt "CPU clock" + default CONFIG_CPU_CLK_200MHZ + ++config CONFIG_CPU_CLK_166MHZ ++ bool "166 MHz" ++ depends on ALLOW_CPU_CLK_166MHZ ++ ++config CONFIG_CPU_CLK_180MHZ ++ bool "180 MHz" ++ depends on ALLOW_CPU_CLK_180MHZ ++ + config CONFIG_CPU_CLK_200MHZ + bool "200 MHz" + depends on ALLOW_CPU_CLK_200MHZ +@@ -231,6 +256,12 @@ config CONFIG_CPU_CLK_400MHZ + + endchoice + ++config ALLOW_CPU_CLK_166MHZ ++ bool ++ ++config ALLOW_CPU_CLK_180MHZ ++ bool ++ + config ALLOW_CPU_CLK_200MHZ + bool + +@@ -251,10 +282,18 @@ config DISABLE_CPU_CLK_240MHZ + choice + prompt "Bus Speed" + default CONFIG_BUS_SPEED_133MHZ +- depends on CONFIG_AT91SAM9G20EK ++ depends on CONFIG_AT91SAM9G20EK || CONFIG_AFEB9260 + help + Select the speed of the bus + ++config CONFIG_BUS_SPEED_83MHZ ++ bool "83 MHz" ++ depends on CONFIG_AFEB9260 ++ ++config CONFIG_BUS_SPEED_90MHZ ++ bool "90 MHz" ++ depends on CONFIG_AFEB9260 ++ + config CONFIG_BUS_SPEED_100MHZ + bool "100 MHz" + depends on CONFIG_AT91SAM9G20EK +@@ -264,9 +303,3 @@ config CONFIG_BUS_SPEED_133MHZ + depends on CONFIG_AT91SAM9G20EK + + endchoice +- +- +- +- +- +- +diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c +new file mode 100644 +index 0000000..249a372 +--- /dev/null ++++ b/board/afeb9260/afeb9260.c +@@ -0,0 +1,251 @@ ++/* ---------------------------------------------------------------------------- ++ * ATMEL Microcontroller Software Support - ROUSSET - ++ * ---------------------------------------------------------------------------- ++ * Copyright (c) 2006, Atmel Corporation ++ ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the disclaiimer below. ++ * ++ * Atmel's name may not be used to endorse or promote products derived from ++ * this software without specific prior written permission. ++ * ++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE ++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, ++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ---------------------------------------------------------------------------- ++ * File Name : at91sam9260ek.c ++ * Object : ++ * Creation : NLe Jul 13th 2006 ++ * ODi Nov 9th : dstp #3507 "Bad PIO descriptors in at91samxxxek.c" ++ *----------------------------------------------------------------------------- ++ */ ++#include "part.h" ++#include "main.h" ++#include "gpio.h" ++#include "pmc.h" ++#include "debug.h" ++#include "memory.h" ++ ++#ifndef CONFIG_THUMB ++static inline unsigned int get_cp15(void) ++{ ++ unsigned int value; ++ __asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (value)); ++ return value; ++} ++ ++static inline void set_cp15(unsigned int value) ++{ ++ __asm__("mcr p15, 0, %0, c1, c0, 0" : : "r" (value)); ++} ++#else ++int get_cp15(void); ++void set_cp15(unsigned int value); ++#endif ++ ++#ifdef CONFIG_HW_INIT ++/*----------------------------------------------------------------------------*/ ++/* \fn hw_init */ ++/* \brief This function performs very low level HW initialization */ ++/* This function is invoked as soon as possible during the c_startup */ ++/* The bss segment must be initialized */ ++/*----------------------------------------------------------------------------*/ ++void hw_init(void) ++{ ++ unsigned int cp15; ++ ++ /* Disable watchdog */ ++ writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR); ++ ++ /* At this stage the main oscillator is supposed to be enabled ++ * PCK = MCK = MOSC */ ++ ++ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ ++ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); ++ ++ /* PCK = PLLA = 2 * MCK */ ++ pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT); ++ /* Switch MCK on PLLA output */ ++ pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT); ++ ++ /* Configure PLLB */ ++ pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT); ++ ++ /* Configure CP15 */ ++ cp15 = get_cp15(); ++ cp15 |= I_CACHE; ++ set_cp15(cp15); ++ ++ /* Configure the PIO controller */ ++ writel(3 << 14, AT91C_BASE_PIOB + PIO_ASR(0)); ++ writel(3 << 14, AT91C_BASE_PIOB + PIO_PDR(0)); ++ ++ /* Configure the EBI Slave Slot Cycle to 64 */ ++ writel( (readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40, (AT91C_BASE_MATRIX + MATRIX_SCFG3)); ++ ++#ifdef CONFIG_DEBUG ++ /* Enable Debug messages on the DBGU */ ++ dbg_init(BAUDRATE(MASTER_CLOCK, 115200)); ++ header(); ++#endif /* CONFIG_DEBUG */ ++ ++#ifdef CONFIG_SDRAM ++ /* Initialize the matrix */ ++ writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_BASE_CCFG + CCFG_EBICSA); ++ ++#if defined(CONFIG_BUS_SPEED_83MHZ) || defined(CONFIG_BUS_SPEED_90MHZ) ++/* CLK= 11ns */ ++/* TWR = tDPL = 2 2CLK always */ ++/* TRC = tRC = 65ns = 6 clk */ ++/* TRP = tRP = 20ns = 2 clk */ ++/* TRCD = tRCD = 20ns = 2 clk */ ++/* TRAS = tRAS = 45ns = 5 clk */ ++/* TXSR = tRRC = 65ns = 6 clk */ ++ ++ sdram_init( AT91C_SDRAMC_NC_9 | ++ AT91C_SDRAMC_NR_13 | ++ AT91C_SDRAMC_CAS_2 | ++ AT91C_SDRAMC_NB_4_BANKS | ++ AT91C_SDRAMC_DBW_32_BITS | ++ AT91C_SDRAMC_TWR_2 | ++ AT91C_SDRAMC_TRC_6 | /* *7 */ ++ AT91C_SDRAMC_TRP_2 | ++ AT91C_SDRAMC_TRCD_2 | ++ AT91C_SDRAMC_TRAS_5 | /* *5 */ ++ AT91C_SDRAMC_TXSR_6, /* *8 */ /* Control Register */ ++ 710, AT91C_SDRAMC_MD_SDRAM); /* Refresh Timer Register */ ++#else ++ /* Configure SDRAM Controller */ ++ sdram_init( AT91C_SDRAMC_NC_9 | ++ AT91C_SDRAMC_NR_13 | ++ AT91C_SDRAMC_CAS_2 | ++ AT91C_SDRAMC_NB_4_BANKS | ++ AT91C_SDRAMC_DBW_32_BITS | ++ AT91C_SDRAMC_TWR_2 | ++ AT91C_SDRAMC_TRC_7 | ++ AT91C_SDRAMC_TRP_2 | ++ AT91C_SDRAMC_TRCD_2 | ++ AT91C_SDRAMC_TRAS_5 | ++ AT91C_SDRAMC_TXSR_8, /* Control Register */ ++ (MASTER_CLOCK * 7)/1000000, /* Refresh Timer Register */ ++ AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */ ++#endif ++ ++#endif /* CONFIG_SDRAM */ ++} ++#endif /* CONFIG_HW_INIT */ ++ ++#ifdef CONFIG_SDRAM ++/*------------------------------------------------------------------------------*/ ++/* \fn sdramc_hw_init */ ++/* \brief This function performs SDRAMC HW initialization */ ++/*------------------------------------------------------------------------------*/ ++void sdramc_hw_init(void) ++{ ++ /* Configure PIOs */ ++/* const struct pio_desc sdramc_pio[] = { ++ {"D16", AT91C_PIN_PC(16), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D17", AT91C_PIN_PC(17), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D18", AT91C_PIN_PC(18), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D19", AT91C_PIN_PC(19), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D20", AT91C_PIN_PC(20), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D21", AT91C_PIN_PC(21), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D22", AT91C_PIN_PC(22), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D23", AT91C_PIN_PC(23), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D24", AT91C_PIN_PC(24), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D25", AT91C_PIN_PC(25), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D26", AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D27", AT91C_PIN_PC(27), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D28", AT91C_PIN_PC(28), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D29", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D30", AT91C_PIN_PC(30), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D31", AT91C_PIN_PC(31), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ }; ++*/ ++ /* Configure the SDRAMC PIO controller to output PCK0 */ ++/* pio_setup(sdramc_pio); */ ++ ++ writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0)); ++ writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0)); ++ ++} ++#endif /* CONFIG_SDRAM */ ++ ++#ifdef CONFIG_DATAFLASH ++/*------------------------------------------------------------------------------*/ ++/* \fn df_hw_init */ ++/* \brief This function performs DataFlash HW initialization */ ++/*------------------------------------------------------------------------------*/ ++void df_hw_init(void) ++{ ++ writel(0xf, 0xfffff444); ++ writel(0xf, 0xfffff460); ++ writel(0xf, 0xfffff470); ++ writel(0xf, 0xfffff404); ++ writel(1 << 11, AT91C_BASE_PIOC + PIO_BSR(0)); ++ writel(1 << 11, AT91C_BASE_PIOC + PIO_PDR(0)); ++} ++#endif /* CONFIG_DATAFLASH */ ++ ++/* We init NAND regardless of whatever */ ++/*------------------------------------------------------------------------------*/ ++/* \fn nandflash_hw_init */ ++/* \brief NandFlash HW init */ ++/*------------------------------------------------------------------------------*/ ++void nandflash_hw_init(void) ++{ ++ /* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */ ++ writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM, AT91C_BASE_CCFG + CCFG_EBICSA); ++ ++ /* Configure SMC CS3 */ ++ writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3); ++ writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3); ++ writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE) , AT91C_BASE_SMC + SMC_CYCLE3); ++ writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | ++ AT91C_SMC_DBW_WIDTH_EIGTH_BITS | AT91C_SM_TDF) , AT91C_BASE_SMC + SMC_CTRL3); ++ ++ /* Configure the PIO controller */ ++ writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC); ++ ++ writel(1 << 13, AT91C_BASE_PIOC + PIO_IFDR(0)); ++ writel(1 << 13, AT91C_BASE_PIOC + PIO_PPUER(0)); ++ writel(1 << 13, AT91C_BASE_PIOC + PIO_ODR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_CODR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_MDDR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_PPUDR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_OER(0)); ++ writel(3 << 13, AT91C_BASE_PIOC + PIO_IDR(0)); ++ writel(3 << 13, AT91C_BASE_PIOC + PIO_PER(0)); ++} ++ ++ ++/*------------------------------------------------------------------------------*/ ++/* \fn nandflash_cfg_16bits_dbw_init */ ++/* \brief Configure SMC in 16 bits mode */ ++/*------------------------------------------------------------------------------*/ ++void nandflash_cfg_16bits_dbw_init(void) ++{ ++ writel(readl(AT91C_BASE_SMC + SMC_CTRL3) | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS, AT91C_BASE_SMC + SMC_CTRL3); ++} ++ ++/*------------------------------------------------------------------------------*/ ++/* \fn nandflash_cfg_8bits_dbw_init */ ++/* \brief Configure SMC in 8 bits mode */ ++/*------------------------------------------------------------------------------*/ ++void nandflash_cfg_8bits_dbw_init(void) ++{ ++ writel((readl(AT91C_BASE_SMC + SMC_CTRL3) & ~(AT91C_SMC_DBW)) | AT91C_SMC_DBW_WIDTH_EIGTH_BITS, AT91C_BASE_SMC + SMC_CTRL3); ++} +diff --git a/board/afeb9260/afeb9260.h b/board/afeb9260/afeb9260.h +new file mode 100644 +index 0000000..7310c0f +--- /dev/null ++++ b/board/afeb9260/afeb9260.h +@@ -0,0 +1,126 @@ ++/* ---------------------------------------------------------------------------- ++ * ATMEL Microcontroller Software Support - ROUSSET - ++ * ---------------------------------------------------------------------------- ++ * Copyright (c) 2006, Atmel Corporation ++ ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the disclaiimer below. ++ * ++ * Atmel's name may not be used to endorse or promote products derived from ++ * this software without specific prior written permission. ++ * ++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE ++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, ++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ---------------------------------------------------------------------------- ++ * File Name : afeb9260.h ++ * Object : ++ * Creation : NLe Jul 13th 2006 ++ *----------------------------------------------------------------------------- ++ */ ++#ifndef _AFEB9260_H ++#define _AFEB9260_H ++ ++/* ******************************************************************* */ ++/* PMC Settings */ ++/* */ ++/* The main oscillator is enabled as soon as possible in the c_startup */ ++/* and MCK is switched on the main oscillator. */ ++/* PLL initialization is done later in the hw_init() function */ ++/* ******************************************************************* */ ++#if defined(CONFIG_CPU_CLK_200MHZ) ++#define MASTER_CLOCK (198656000/2) ++#define PLLA_SETTINGS 0x2060BF09 ++#endif ++ ++#if defined(CONFIG_CPU_CLK_166MHZ) ++#define PLLA_SETTINGS 0x25ceBFa5 /* 166MHz */ ++#define MASTER_CLOCK (165999709/2) /* 166MHz MCK=83MHz*/ ++#endif ++ ++#if defined(CONFIG_CPU_CLK_180MHZ) ++#define PLLA_SETTINGS 0x2125BF1E /* 180MHz */ ++#define MASTER_CLOCK (179999198/2) /* 180MHz MCK=90MHz */ ++#endif ++ ++#define TOP_OF_MEMORY 0x301000 ++#define PLL_LOCK_TIMEOUT 1000000 ++ ++#define PLLB_SETTINGS 0x10483F0E ++ ++/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */ ++#define MCKR_SETTINGS (AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2) ++#define MCKR_CSS_SETTINGS (AT91C_PMC_CSS_PLLA_CLK | MCKR_SETTINGS) ++ ++/* ******************************************************************* */ ++/* DataFlash Settings |