diff options
44 files changed, 27731 insertions, 461 deletions
diff --git a/conf/checksums.ini b/conf/checksums.ini index 93e3738bca..948a4bfbd7 100644 --- a/conf/checksums.ini +++ b/conf/checksums.ini @@ -178,6 +178,10 @@ sha256=fe044ec9817a31f2b76f701b2cfd980809676943a901ba3d49200162807fa1f9 md5=82c698151f934eb28c65d1838cee7d9e sha256=d392567cb39b4ea606c0e0acafd8ed72320311b995336ece5fcefcf9b150e9d7 +[http://hal.freedesktop.org/releases/DeviceKit-003.tar.gz] +md5=8b311547f4a2c8c6b6598e3318d66cd7 +sha256=d2d21f995d1a152ca2d8beea6d37f31e48cca034b82ceb7322f39422e849e9cf + [http://search.cpan.org/CPAN/authors/id/G/GA/GAAS/Digest-SHA1-2.11.tar.gz] md5=2449bfe21d6589c96eebf94dae24df6b sha256=3cebe0a6894daee3bfa5d9619fc90e7619cb6a77ac1b04d027341cd6033ae989 @@ -7130,6 +7134,10 @@ sha256=719f2bbd79d55cdd6f5e31b49cec49df71ddb32a4439dba678de0e09330096da md5=18be4e7a1ac713bda93d00fee20bbef8 sha256=c119ce82f0e42d3412420c42c1ead75e0b9de67131a5c9dd3cdab509f65ddfdd +[http://avr32linux.org/twiki/pub/Main/GDBPatches/gdb-6.7.1.atmel.1.0.3.tar.bz2] +md5=8a5cf43042a84ec0da0aca301bd1dae4 +sha256=2c8bbd8cc3323899e698fad071cc0e4e8880c178deaa849073ca4a2c9bc176f2 + [ftp://ftp.gnu.org/gnu/gdb/gdb-6.7.1.tar.gz] md5=7a74dcafdd39d18678e5b5cc2c50bb0c sha256=66e6ff871a7ed71ea433b8341ffebbe48590119e43a42953d392f5ce517c95e4 @@ -7878,6 +7886,10 @@ sha256=9605f7aee1b8d58cac10dd514c2bdfa340089d85b149db828816d18ac3ebaff8 md5=4a7c977086af47fe43ea08b29ab93503 sha256=939c8a8f819b8c39e4e355a764b2a47c6959d57029c5134a51a282d7cccd60c5 +[http://ftp.gnome.org/pub/GNOME/sources/gnome-bluetooth/2.27/gnome-bluetooth-2.27.4.tar.bz2] +md5=e34180aa90d5d718b819572b21b76d08 +sha256=250fede462d5ec0576c0ab9c7f965fb56dc5de6e1180405da8cf0e867a2eca3a + [http://ftp.gnome.org/pub/GNOME/sources/gnome-common/2.18/gnome-common-2.18.0.tar.bz2] md5=567172e685fc0783b1d6ab9843a85d6a sha256=ba28c1017e7e4212db16ada3f44cb446b6637c9c4fe16c0e2c2a51c94c46bc5b @@ -9998,6 +10010,10 @@ sha256=bbe44edc3d519028761a22b282b912ab8f43db2003c6791c295c4a52f5db48bf md5=31d1f505afe3ba1b351e18612aa57a70 sha256=bbe44edc3d519028761a22b282b912ab8f43db2003c6791c295c4a52f5db48bf +[http://downloads.sourceforge.net/haserl/haserl-0.9.25.tar.gz] +md5=906c634a2af4ac3a4b656ef4e244c4cd +sha256=d33ba27082c8bc4427ccebd8a56cf9aef190391f0361398197efb03210910f0e + [http://www.server-side.de/download/havp-0.82.tar.gz] md5=9e6a16b7d074782d1c62f1f7316e56ab sha256=e2db8d3383cd8eca6a18ebee85875de895f3ac7414eab091a87f052d79a87b09 @@ -22806,6 +22822,10 @@ sha256=5cd64b5ac52720a7f60015e01696422277ecc459e89dce8b16d457f30a9409ab md5=cb11d3d74eee4d31124523d90d8c31fa sha256=0c0afa2816482e087987f71958b656ff0c122032f5e3897a8d17daca5bc14115 +[ftp://ftp.denx.de/pub/u-boot/u-boot-2009.03.tar.bz2] +md5=285e2184d2efef50e0fe43b71d2a7b11 +sha256=a2889bee9c45575b284564dbc27cf3dc6cb9833d4ff643976a1b3dba2d763f86 + [http://linux.omap.com/pub/bootloader/2430sdp/source/u-boot-SEP1106.tar.gz] md5=49c07dec9e1be69fd01d46f47ec03731 sha256=a090786113b02647413ebc15888af269f2e6d50f73cbb94b0619cc1702911dae @@ -22910,6 +22930,10 @@ sha256=cc9f58ff58fbd3f5868e1f1e368e3c93e1f441afd0ac1dcbd5d01a9ce5b5b0d7 md5=a3fcdcd21b2f33d598f45a68fff892bd sha256=ee3922bd46dbdc406be5d498be5bc062a0b39f05f1c0a1b22c3657eb0e805975 +[http://kernel.org/pub/linux/utils/kernel/hotplug/udev-141.tar.gz] +md5=86382b7bbc64459e714c65a2a4e10916 +sha256=001be4a8963c48e7debc82c6078562d087a2979da63e558a5e3613c03725c377 + [http://udhcp.busybox.net/source/udhcp-0.9.8.tar.gz] md5=2d7e548820d2ded5e183933cb701defb sha256=da0ca1e821e3fa7cfbe73ddb1480b921002ee992f5e5fbc611422c103b907443 diff --git a/conf/distro/include/sane-srcrevs.inc b/conf/distro/include/sane-srcrevs.inc index 333abf423c..2734271267 100644 --- a/conf/distro/include/sane-srcrevs.inc +++ b/conf/distro/include/sane-srcrevs.inc @@ -257,7 +257,7 @@ SRCREV_pn-zhone ?= "f38cc52fbf11f7fe945797a6b8ade29ed479d924" # Enlightenment Foundation Libraries # Caution: This is not alphabetically, but (roughly) dependency-sorted. # Please leave it like that. -EFL_SRCREV ?= "39916" +EFL_SRCREV ?= "40087" SRCREV_pn-edb-native ?= "${EFL_SRCREV}" SRCREV_pn-edb ?= "${EFL_SRCREV}" SRCREV_pn-eina-native ?= "${EFL_SRCREV}" diff --git a/conf/machine/hipox.conf b/conf/machine/hipox.conf index 728ad2bb0d..f3a31cf63b 100644 --- a/conf/machine/hipox.conf +++ b/conf/machine/hipox.conf @@ -12,7 +12,7 @@ PREFERRED_PROVIDER_virtual/kernel = "linux" KERNEL_IMAGETYPE = "uImage" -PREFERRED_VERSION_u-boot = "1.1.2" +PREFERRED_VERSION_u-boot = "2009.03" UBOOT_LOADADDRESS = "0x48008000" UBOOT_ENTRYPOINT = "0x48008000" UBOOT_ARCH = "arm" diff --git a/conf/machine/micro2440.conf b/conf/machine/micro2440.conf new file mode 100644 index 0000000000..17aa0d310a --- /dev/null +++ b/conf/machine/micro2440.conf @@ -0,0 +1,19 @@ +#@TYPE: Machine +#@Name: FriendlyARM micro2440 +#@DESCRIPTION: Machine configuration for FriendlyARM micro2440 Samsung 2440 based board + +TARGET_ARCH = "arm" + +PREFERRED_PROVIDER_virtual/kernel = "linux" + +# used by sysvinit_2 +SERIAL_CONSOLE = "115200 ttySAC0" + +IMAGE_FSTYPES = "jffs2 tar.gz" + +MACHINE_FEATURES = "kernel26 touchscreen screen usbhost usbgadget sound alsa ethernet" + +require conf/machine/include/tune-arm920t.inc + +KERNEL_IMAGETYPE = "uImage" +EXTRA_IMAGECMD_jffs2 = "--pad --little-endian -e16KiB -s 0x200 -n" diff --git a/recipes/efl1/evas-native_svn.bb b/recipes/efl1/evas-native_svn.bb index 56723ca9ab..4a17942c78 100644 --- a/recipes/efl1/evas-native_svn.bb +++ b/recipes/efl1/evas-native_svn.bb @@ -1,6 +1,6 @@ require evas.inc inherit native -DEPENDS = "freetype-native libpng-native jpeg-native eet-native eina-native" +DEPENDS = "freetype-native libpng-native jpeg-native eet-native eina-native libfribidi-native" PR = "r1" EXTRA_OECONF = "\ diff --git a/recipes/efl1/evas.inc b/recipes/efl1/evas.inc index 0fb01f31a7..d2a773805d 100644 --- a/recipes/efl1/evas.inc +++ b/recipes/efl1/evas.inc @@ -1,7 +1,7 @@ DESCRIPTION = "Evas is the Enlightenment canvas API" LICENSE = "MIT BSD" # can also depend on valgrind, libsdl-x11, directfb -DEPENDS = "eina eet freetype jpeg libpng virtual/libx11 libxext libxrender fontconfig" +DEPENDS = "eina eet freetype jpeg libpng virtual/libx11 libxext libxrender fontconfig libfribidi" PV = "0.9.9.050+svnr${SRCREV}" PR = "r1" diff --git a/recipes/gnome/gnome-bluetooth_2.27.4.bb b/recipes/gnome/gnome-bluetooth_2.27.4.bb new file mode 100644 index 0000000000..70377a6a3c --- /dev/null +++ b/recipes/gnome/gnome-bluetooth_2.27.4.bb @@ -0,0 +1,15 @@ +LICENSE = "GPL" +SECTION = "x11/gnome" + +inherit autotools gnome pkgconfig + +DEPENDS = "obexd obex-data-server gconf-dbus gtk+ dbus-glib libunique libnotify hal bluez4 gnome-keyring" +RRECOMMENDS_${PN} += "obexd obex-data-server" +RCONFLICTS_${PN} = "bluez-gnome" + +do_configure_prepend() { + sed -i -e s:docs::g ${S}/Makefile.am + echo "EXTRA_DIST = version.xml" > gnome-doc-utils.make + echo "EXTRA_DIST = version.xml" > gtk-doc.make +} + diff --git a/recipes/haserl/haserl_0.9.25.bb b/recipes/haserl/haserl_0.9.25.bb new file mode 100644 index 0000000000..d1a06007c0 --- /dev/null +++ b/recipes/haserl/haserl_0.9.25.bb @@ -0,0 +1,9 @@ +# Copyright (C) 2007-2008, Stelios Koroneos - Digital OPSiS, All Rights Reserved +# Released under the MIT license (see packages/COPYING) +DESCRIPTION = "A cgi wrapper for embedding shell scripts into html documents" +SECTION = "console/network" +LICENSE = "GPL" + +SRC_URI = "${SOURCEFORGE_MIRROR}/${PN}/${PN}-${PV}.tar.gz" + +inherit autotools gettext diff --git a/recipes/images/initramfs-image.bb b/recipes/images/initramfs-image.bb index d3d1d751cf..e5189849ba 100644 --- a/recipes/images/initramfs-image.bb +++ b/recipes/images/initramfs-image.bb @@ -2,7 +2,7 @@ # command line, from teh choices of block device, loop back images (including # recursive) and NFS. -IMAGE_INSTALL = "initramfs-module-block initramfs-module-loop initramfs-module-nfs" +IMAGE_INSTALL = "busybox-static initramfs-module-block initramfs-module-loop initramfs-module-nfs" IMAGE_LINGUAS = "" # Remove any kernel-image that the kernel-module-* packages may have pulled in. diff --git a/recipes/libfribidi/libfribidi-native_0.10.4.bb b/recipes/libfribidi/libfribidi-native_0.10.4.bb new file mode 100644 index 0000000000..62d706dfc5 --- /dev/null +++ b/recipes/libfribidi/libfribidi-native_0.10.4.bb @@ -0,0 +1,29 @@ +DESCRIPTION = "Fribidi library for bidirectional text" +SECTION = "libs" +PRIORITY = "optional" + +inherit autotools pkgconfig native + +PR = "r0" + +S = "${WORKDIR}/fribidi-${PV}" + +SRC_URI = "${SOURCEFORGE_MIRROR}/fribidi/fribidi-${PV}.tar.bz2 \ + file://libtool-update.patch;patch=1" + +#PACKAGES += " ${PN}-bin" +FILES_${PN} = "${libdir}/lib*.so.*" +#FILES_${PN}-bin = "${libdir}/uu*" + +do_configure_prepend () { +# this version of libtool is old - we have to nobble this file to get it to litoolize + rm ltconfig + rm aclocal.m4 + rm acinclude.m4 +} + +do_stage () { + oe_libinstall -a -so -C .libs libfribidi ${STAGING_LIBDIR} + autotools_stage_includes +} + diff --git a/recipes/linux/linux-2.6.24/hipox/hipox.patch b/recipes/linux/linux-2.6.24/hipox/hipox.patch index 686876fb1e..e2d857570a 100644 --- a/recipes/linux/linux-2.6.24/hipox/hipox.patch +++ b/recipes/linux/linux-2.6.24/hipox/hipox.patch @@ -23398,7 +23398,7 @@ diff -Nurd linux-2.6.24/arch/arm/mach-hipox/hipox.c linux-2.6.24-oxe810/arch/arm +#endif // CONFIG_HIPOX_SATA_POWER_2 +} + -+MACHINE_START(OXNAS, "Oxsemi NAS") ++MACHINE_START(HIPOX, "OXE810 based HydraIP") + /* Maintainer: Oxford Semiconductor Ltd */ +#ifdef CONFIG_ARCH_HIPOX_UART1 + .phys_io = UART_1_BASE_PA, diff --git a/recipes/linux/linux-2.6.29/ep93xx/add-edb9301.patch b/recipes/linux/linux-2.6.29/ep93xx/add-edb9301.patch new file mode 100644 index 0000000000..48e7c18f42 --- /dev/null +++ b/recipes/linux/linux-2.6.29/ep93xx/add-edb9301.patch @@ -0,0 +1,112 @@ +Add Cirrus Logic EDB9301 Dev Board to arch/arm/mach-ep93xx + +Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> + +--- + +diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig +index 56bddce..9ca8974 100644 +--- a/arch/arm/mach-ep93xx/Kconfig ++++ b/arch/arm/mach-ep93xx/Kconfig +@@ -15,6 +15,12 @@ config MACH_ADSSPHERE + Say 'Y' here if you want your kernel to support the ADS + Sphere board. + ++config MACH_EDB9301 ++ bool "Support Cirrus Logic EDB9301" ++ help ++ Say 'Y' here if you want your kernel to support the Cirrus ++ Logic EDB9301 Evaluation Board. ++ + config MACH_EDB9302 + bool "Support Cirrus Logic EDB9302" + help +diff --git a/arch/arm/mach-ep93xx/Makefile +b/arch/arm/mach-ep93xx/Makefile +index 944e42d..7e7536f 100644 +--- a/arch/arm/mach-ep93xx/Makefile ++++ b/arch/arm/mach-ep93xx/Makefile +@@ -7,6 +7,7 @@ obj-n := + obj- := + + obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o ++obj-$(CONFIG_MACH_EDB9301) += edb9301.o + obj-$(CONFIG_MACH_EDB9302) += edb9302.o + obj-$(CONFIG_MACH_EDB9302A) += edb9302a.o + obj-$(CONFIG_MACH_EDB9307) += edb9307.o +diff --git a/arch/arm/mach-ep93xx/edb9301.c +b/arch/arm/mach-ep93xx/edb9301.c +new file mode 100644 +index 0000000..4108c7c +--- /dev/null ++++ b/arch/arm/mach-ep93xx/edb9301.c +@@ -0,0 +1,68 @@ ++/* ++ * arch/arm/mach-ep93xx/edb9301.c ++ * Cirrus Logic EDB9301 support. ++ * ++ * Copyright (C) 2009 H Hartley Sweeten <hsweeten@visionengravers.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or (at ++ * your option) any later version. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/mm.h> ++#include <linux/sched.h> ++#include <linux/interrupt.h> ++#include <linux/ioport.h> ++#include <linux/mtd/physmap.h> ++#include <linux/platform_device.h> ++#include <linux/io.h> ++#include <linux/i2c.h> ++#include <mach/hardware.h> ++#include <asm/mach-types.h> ++#include <asm/mach/arch.h> ++ ++static struct physmap_flash_data edb9301_flash_data = { ++ .width = 2, ++}; ++ ++static struct resource edb9301_flash_resource = { ++ .start = EP93XX_CS6_PHYS_BASE, ++ .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device edb9301_flash = { ++ .name = "physmap-flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &edb9301_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &edb9301_flash_resource, ++}; ++ ++static struct ep93xx_eth_data edb9301_eth_data = { ++ .phy_id = 1, ++}; ++ ++static void __init edb9301_init_machine(void) ++{ ++ ep93xx_init_devices(); ++ platform_device_register(&edb9301_flash); ++ ++ ep93xx_register_eth(&edb9301_eth_data, 1); ++} ++ ++MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board") ++ /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */ ++ .phys_io = EP93XX_APB_PHYS_BASE, ++ .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, ++ .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, ++ .map_io = ep93xx_map_io, ++ .init_irq = ep93xx_init_irq, ++ .timer = &ep93xx_timer, ++ .init_machine = edb9301_init_machine, ++MACHINE_END + diff --git a/recipes/linux/linux-2.6.29/ep93xx/edb9301-fix-machine-id.patch b/recipes/linux/linux-2.6.29/ep93xx/edb9301-fix-machine-id.patch new file mode 100644 index 0000000000..65bfc9bc5e --- /dev/null +++ b/recipes/linux/linux-2.6.29/ep93xx/edb9301-fix-machine-id.patch @@ -0,0 +1,19 @@ +--- + arch/arm/tools/mach-types | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- linux-2.6.29.orig/arch/arm/tools/mach-types ++++ linux-2.6.29/arch/arm/tools/mach-types +@@ -473,11 +473,11 @@ hawk MACH_HAWK HAWK 456 + ccat91sbc001 MACH_CCAT91SBC001 CCAT91SBC001 457 + expresso MACH_EXPRESSO EXPRESSO 458 + h4000 MACH_H4000 H4000 459 + dino MACH_DINO DINO 460 + ml675k MACH_ML675K ML675K 461 +-edb9301 MACH_EDB9301 EDB9301 462 ++edb9301 MACH_EDB9301 EDB9301 454 + edb9315 MACH_EDB9315 EDB9315 463 + reciva_tt MACH_RECIVA_TT RECIVA_TT 464 + cstcb01 MACH_CSTCB01 CSTCB01 465 + cstcb1 MACH_CSTCB1 CSTCB1 466 + shadwell MACH_SHADWELL SHADWELL 467 diff --git a/recipes/linux/linux-2.6.29/micro2440/0001-S3C-Backported-the-s3c2410-touchscreen-from-openmok.patch b/recipes/linux/linux-2.6.29/micro2440/0001-S3C-Backported-the-s3c2410-touchscreen-from-openmok.patch new file mode 100644 index 0000000000..4e3b3001f8 --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0001-S3C-Backported-the-s3c2410-touchscreen-from-openmok.patch @@ -0,0 +1,792 @@ +From d13aef4d7aff3b01ea349a07b899debe094bf33e Mon Sep 17 00:00:00 2001 +From: Michel Pollet <buserror@gmail.com> +Date: Fri, 13 Mar 2009 18:43:43 +0000 +Subject: [PATCH] S3C: Backported the s3c2410 touchscreen from openmoko + +This peripheral is pretty essential for the s3c and is missing +from mainstream linux. This is a straight port of the moko +kernel. +--- + arch/arm/mach-s3c2410/include/mach/ts.h | 35 ++ + arch/arm/plat-s3c/include/plat/devs.h | 3 +- + arch/arm/plat-s3c24xx/devs.c | 19 + + arch/arm/plat-s3c24xx/s3c244x.c | 3 + + drivers/input/touchscreen/Kconfig | 18 + + drivers/input/touchscreen/Makefile | 1 + + drivers/input/touchscreen/s3c2410_ts.c | 609 +++++++++++++++++++++++++++++++ + 7 files changed, 687 insertions(+), 1 deletions(-) + create mode 100644 arch/arm/mach-s3c2410/include/mach/ts.h + create mode 100644 drivers/input/touchscreen/s3c2410_ts.c + +diff --git a/arch/arm/mach-s3c2410/include/mach/ts.h b/arch/arm/mach-s3c2410/include/mach/ts.h +new file mode 100644 +index 0000000..1b451ea +--- /dev/null ++++ b/arch/arm/mach-s3c2410/include/mach/ts.h +@@ -0,0 +1,35 @@ ++/* arch/arm/mach-s3c2410/include/mach/ts.h ++ * ++ * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org> ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * ++ * Changelog: ++ * 24-Mar-2005 RTP Created file ++ * 03-Aug-2005 RTP Renamed to ts.h ++ */ ++ ++#ifndef __ASM_ARM_TS_H ++#define __ASM_ARM_TS_H ++ ++#include <../drivers/input/touchscreen/ts_filter.h> ++ ++struct s3c2410_ts_mach_info { ++ int delay; ++ int presc; ++ /* array of pointers to filter APIs we want to use, in order ++ * ends on first NULL, all NULL is OK ++ */ ++ struct ts_filter_api *filter_sequence[MAX_TS_FILTER_CHAIN]; ++ /* array of configuration ints, one for each filter above */ ++ void *filter_config[MAX_TS_FILTER_CHAIN]; ++}; ++ ++void set_s3c2410ts_info(struct s3c2410_ts_mach_info *hard_s3c2410ts_info); ++ ++#endif /* __ASM_ARM_TS_H */ ++ +diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h +index 6b1b523..cf160ab 100644 +--- a/arch/arm/plat-s3c/include/plat/devs.h ++++ b/arch/arm/plat-s3c/include/plat/devs.h +@@ -45,10 +45,11 @@ extern struct platform_device s3c_device_nand; + + extern struct platform_device s3c_device_usbgadget; + ++extern struct platform_device s3c_device_ts; ++ + /* s3c2440 specific devices */ + + #ifdef CONFIG_CPU_S3C2440 + + extern struct platform_device s3c_device_camif; +- + #endif +diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c +index 16ac01d..a3f8102 100644 +--- a/arch/arm/plat-s3c24xx/devs.c ++++ b/arch/arm/plat-s3c24xx/devs.c +@@ -26,6 +26,8 @@ + #include <asm/mach/irq.h> + #include <mach/fb.h> + #include <mach/hardware.h> ++#include <mach/ts.h> ++#include <asm/io.h> + #include <asm/irq.h> + + #include <plat/regs-serial.h> +@@ -229,6 +231,23 @@ struct platform_device s3c_device_nand = { + + EXPORT_SYMBOL(s3c_device_nand); + ++/* Touchscreen */ ++struct platform_device s3c_device_ts = { ++ .name = "s3c2410-ts", ++ .id = -1, ++}; ++ ++EXPORT_SYMBOL(s3c_device_ts); ++ ++static struct s3c2410_ts_mach_info s3c2410ts_info; ++ ++void set_s3c2410ts_info(struct s3c2410_ts_mach_info *hard_s3c2410ts_info) ++{ ++ memcpy(&s3c2410ts_info,hard_s3c2410ts_info,sizeof(struct s3c2410_ts_mach_info)); ++ s3c_device_ts.dev.platform_data = &s3c2410ts_info; ++} ++EXPORT_SYMBOL(set_s3c2410ts_info); ++ + /* USB Device (Gadget)*/ + + static struct resource s3c_usbgadget_resource[] = { +diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c +index c1de6bb..df78a15 100644 +--- a/arch/arm/plat-s3c24xx/s3c244x.c ++++ b/arch/arm/plat-s3c24xx/s3c244x.c +@@ -59,6 +59,8 @@ void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no) + s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); + } + ++extern struct platform_device s3c_device_ts; ++ + void __init s3c244x_map_io(void) + { + /* register our io-tables */ +@@ -70,6 +72,7 @@ void __init s3c244x_map_io(void) + s3c_device_sdi.name = "s3c2440-sdi"; + s3c_device_i2c0.name = "s3c2440-i2c"; + s3c_device_nand.name = "s3c2440-nand"; ++ s3c_device_ts.name = "s3c2440-ts"; + s3c_device_usbgadget.name = "s3c2440-usbgadget"; + } + +diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig +index bb6486a..9076492 100644 +--- a/drivers/input/touchscreen/Kconfig ++++ b/drivers/input/touchscreen/Kconfig +@@ -79,6 +79,24 @@ config TOUCHSCREEN_FUJITSU + To compile this driver as a module, choose M here: the + module will be called fujitsu-ts. + ++config TOUCHSCREEN_S3C2410 ++ tristate "Samsung S3C2410 touchscreen input driver" ++ depends on ARCH_S3C2410 && INPUT && INPUT_TOUCHSCREEN ++ select SERIO ++ help ++ Say Y here if you have the s3c2410 touchscreen. ++ ++ If unsure, say N. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called s3c2410_ts. ++ ++config TOUCHSCREEN_S3C2410_DEBUG ++ boolean "Samsung S3C2410 touchscreen debug messages" ++ depends on TOUCHSCREEN_S3C2410 ++ help ++ Select this if you want debug messages ++ + config TOUCHSCREEN_GUNZE + tristate "Gunze AHL-51S touchscreen" + select SERIO +diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile +index d3375af..fbcde99 100644 +--- a/drivers/input/touchscreen/Makefile ++++ b/drivers/input/touchscreen/Makefile +@@ -34,3 +34,4 @@ wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9705) += wm9705.o + wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9712) += wm9712.o + wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9713) += wm9713.o + obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o ++obj-$(CONFIG_TOUCHSCREEN_S3C2410) += s3c2410_ts.o +diff --git a/drivers/input/touchscreen/s3c2410_ts.c b/drivers/input/touchscreen/s3c2410_ts.c +new file mode 100644 +index 0000000..ea0777c +--- /dev/null ++++ b/drivers/input/touchscreen/s3c2410_ts.c +@@ -0,0 +1,609 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org> ++ * iPAQ H1940 touchscreen support ++ * ++ * ChangeLog ++ * ++ * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at> ++ * - added clock (de-)allocation code ++ * ++ * 2005-03-06: Arnaud Patard <arnaud.patard@rtp-net.org> ++ * - h1940_ -> s3c2410 (this driver is now also used on the n30 ++ * machines :P) ++ * - Debug messages are now enabled with the config option ++ * TOUCHSCREEN_S3C2410_DEBUG ++ * - Changed the way the value are read ++ * - Input subsystem should now work ++ * - Use ioremap and readl/writel ++ * ++ * 2005-03-23: Arnaud Patard <arnaud.patard@rtp-net.org> ++ * - Make use of some undocumented features of the touchscreen ++ * controller ++ * ++ * 2007-05-23: Harald Welte <laforge@openmoko.org> ++ * - Add proper support for S32440 ++ * ++ * 2008-06-23: Andy Green <andy@openmoko.com> ++ * - removed averaging system ++ * - added generic Touchscreen filter stuff ++ * ++ * 2008-11-27: Nelson Castillo <arhuaco@freaks-unidos.net> ++ * - improve interrupt handling ++ */ ++ ++#include <linux/errno.h> ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/slab.h> ++#include <linux/input.h> ++#include <linux/init.h> ++#include <linux/serio.h> ++#include <linux/timer.h> ++#include <linux/kfifo.h> ++#include <linux/delay.h> ++#include <linux/platform_device.h> ++#include <linux/clk.h> ++#include <asm/io.h> ++#include <asm/irq.h> ++ ++#include <mach/regs-gpio.h> ++#include <mach/ts.h> ++ ++#include <plat/regs-adc.h> ++ ++#include "ts_filter.h" ++ ++/* For ts.dev.id.version */ ++#define S3C2410TSVERSION 0x0101 ++ ++#define TSC_SLEEP (S3C2410_ADCTSC_PULL_UP_DISABLE | S3C2410_ADCTSC_XY_PST(0)) ++ ++#define WAIT4INT(x) (((x)<<8) | \ ++ S3C2410_ADCTSC_YM_SEN | \ ++ S3C2410_ADCTSC_YP_SEN | \ ++ S3C2410_ADCTSC_XP_SEN | \ ++ S3C2410_ADCTSC_XY_PST(3)) ++ ++#define AUTOPST (S3C2410_ADCTSC_YM_SEN | \ ++ S3C2410_ADCTSC_YP_SEN | \ ++ S3C2410_ADCTSC_XP_SEN | \ ++ S3C2410_ADCTSC_AUTO_PST | \ ++ S3C2410_ADCTSC_XY_PST(0)) ++ ++#define DEBUG_LVL KERN_DEBUG ++ ++MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>"); ++MODULE_DESCRIPTION("s3c2410 touchscreen driver"); ++MODULE_LICENSE("GPL"); ++ ++/* ++ * Definitions & global arrays. ++ */ ++ ++static char *s3c2410ts_name = "s3c2410 TouchScreen"; ++ ++#define TS_RELEASE_TIMEOUT (HZ >> 7 ? HZ >> 7 : 1) /* 8ms (5ms if HZ is 200) */ ++#define TS_EVENT_FIFO_SIZE (2 << 6) /* must be a power of 2 */ ++ ++#define TS_STATE_STANDBY 0 /* initial state */ ++#define TS_STATE_PRESSED 1 ++#define TS_STATE_RELEASE_PENDING 2 ++#define TS_STATE_RELEASE 3 ++ ++/* ++ * Per-touchscreen data. ++ */ ++ ++struct s3c2410ts { ++ struct input_dev *dev; ++ struct ts_filter *tsf[MAX_TS_FILTER_CHAIN]; ++ int coords[2]; /* just X and Y for us */ ++ int is_down; ++ int state; ++ struct kfifo *event_fifo; ++}; ++ ++static struct s3c2410ts ts; ++ ++static void __iomem *base_addr; ++ ++/* ++ * A few low level functions. ++ */ ++ ++static inline void s3c2410_ts_connect(void) ++{ ++ s3c2410_gpio_cfgpin(S3C2410_GPG12, S3C2410_GPG12_XMON); ++ s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPG13_nXPON); ++ s3c2410_gpio_cfgpin(S3C2410_GPG14, S3C2410_GPG14_YMON); ++ s3c2410_gpio_cfgpin(S3C2410_GPG15, S3C2410_GPG15_nYPON); ++} ++ ++static void s3c2410_ts_start_adc_conversion(void) ++{ ++ writel(S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST, ++ base_addr + S3C2410_ADCTSC); ++ writel(readl(base_addr + S3C2410_ADCCON) | S3C2410_ADCCON_ENABLE_START, ++ base_addr + S3C2410_ADCCON); ++} ++ ++/* ++ * Just send the input events. ++ */ ++ ++enum ts_input_event {IE_DOWN = 0, IE_UP}; ++ ++static void ts_input_report(int event, int coords[]) ++{ ++#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG ++ static char *s[] = {"down", "up"}; ++ struct timeval tv; ++ ++ do_gettimeofday(&tv); ++#endif ++ ++ if (event == IE_DOWN) { ++ input_report_abs(ts.dev, ABS_X, coords[0]); ++ input_report_abs(ts.dev, ABS_Y, coords[1]); ++ input_report_key(ts.dev, BTN_TOUCH, 1); ++ input_report_abs(ts.dev, ABS_PRESSURE, 1); ++ ++#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG ++ printk(DEBUG_LVL "T:%06d %6s (X:%03d, Y:%03d)\n", ++ (int)tv.tv_usec, s[event], coords[0], coords[1]); ++#endif ++ } else { ++ input_report_key(ts.dev, BTN_TOUCH, 0); ++ input_report_abs(ts.dev, ABS_PRESSURE, 0); ++ ++#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG ++ printk(DEBUG_LVL "T:%06d %6s\n", ++ (int)tv.tv_usec, s[event]); ++#endif ++ } ++ ++ input_sync(ts.dev); ++} ++ ++/* ++ * Manage the state of the touchscreen. ++ */ ++ ++static void event_send_timer_f(unsigned long data); ++ ++static struct timer_list event_send_timer = ++ TIMER_INITIALIZER(event_send_timer_f, 0, 0); ++ ++static void event_send_timer_f(unsigned long data) ++{ ++ static int noop_counter; ++ int event_type; ++ ++ while (__kfifo_get(ts.event_fifo, (unsigned char *)&event_type, ++ sizeof(int))) { ++ int buf[2]; ++ ++ switch (event_type) { ++ case 'D': ++ if (ts.state == TS_STATE_RELEASE_PENDING) ++ /* Ignore short UP event */ ++ ts.state = TS_STATE_PRESSED; ++ break; ++ ++ case 'U': ++ ts.state = TS_STATE_RELEASE_PENDING; ++ break; ++ ++ case 'P': ++ if (ts.is_down) /* stylus_action needs a conversion */ ++ s3c2410_ts_start_adc_conversion(); ++ ++ if (unlikely(__kfifo_get(ts.event_fifo, ++ (unsigned char *)buf, ++ sizeof(int) * 2) ++ != sizeof(int) * 2)) ++ goto ts_exit_error; ++ ++ ts_input_report(IE_DOWN, buf); ++ ts.state = TS_STATE_PRESSED; ++ break; ++ ++ default: ++ goto ts_exit_error; ++ } ++ ++ noop_counter = 0; ++ } ++ ++ if (noop_counter++ >= 1) { ++ noop_counter = 0; ++ if (ts.state == TS_STATE_RELEASE_PENDING) { ++ /* We delay the UP event for a ++ * while to avoid jitter. If we get a DOWN ++ * event we do not send it. */ ++ ++ ts_input_report(IE_UP, NULL); ++ ts.state = TS_STATE_STANDBY; ++ ++ if (ts.tsf[0]) ++ (ts.tsf[0]->api->clear)(ts.tsf[0]); ++ } ++ } else { ++ mod_timer(&event_send_timer, jiffies + TS_RELEASE_TIMEOUT); ++ } ++ ++ return; ++ ++ts_exit_error: /* should not happen unless we have a bug */ ++ printk(KERN_ERR __FILE__ ": event_send_timer_f failed\n"); ++} ++ ++/* ++ * Manage interrupts. ++ */ ++ ++static irqreturn_t stylus_updown(int irq, void *dev_id) ++{ ++ unsigned long data0; ++ unsigned long data1; ++ int event_type; ++ ++ data0 = readl(base_addr+S3C2410_ADCDAT0); ++ data1 = readl(base_addr+S3C2410_ADCDAT1); ++ ++ ts.is_down = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && ++ (!(data1 & S3C2410_ADCDAT0_UPDOWN)); ++ ++ event_type = ts.is_down ? 'D' : 'U'; ++ ++ if (unlikely(__kfifo_put(ts.event_fifo, (unsigned char *)&event_type, ++ sizeof(int)) != sizeof(int))) /* should not happen */ ++ printk(KERN_ERR __FILE__": stylus_updown lost event!\n"); ++ ++ if (ts.is_down) ++ s3c2410_ts_start_adc_conversion(); ++ else ++ writel(WAIT4INT(0), base_addr+S3C2410_ADCTSC); ++ ++ mod_timer(&event_send_timer, jiffies + 1); ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t stylus_action(int irq, void *dev_id) ++{ ++ int buf[3]; ++ ++ /* grab the ADC results */ ++ ts.coords[0] = readl(base_addr + S3C2410_ADCDAT0) & ++ S3C2410_ADCDAT0_XPDATA_MASK; ++ ts.coords[1] = readl(base_addr + S3C2410_ADCDAT1) & ++ S3C2410_ADCDAT1_YPDATA_MASK; ++ ++ if (ts.tsf[0]) { /* filtering is enabled, don't use raw directly */ ++ switch ((ts.tsf[0]->api->process)(ts.tsf[0], &ts.coords[0])) { ++ case 0: /* ++ * no real sample came out of processing yet, ++ * get another raw result to feed it ++ */ ++ s3c2410_ts_start_adc_conversion(); ++ return IRQ_HANDLED; ++ case 1: /* filters are ready to deliver a sample */ ++ (ts.tsf[0]->api->scale)(ts.tsf[0], &ts.coords[0]); ++ break; ++ case -1: ++ /* error in filters, ignore the event */ ++ (ts.tsf[0]->api->clear)(ts.tsf[0]); ++ writel(WAIT4INT(1), base_addr + S3C2410_ADCTSC); ++ return IRQ_HANDLED; ++ default: ++ printk(KERN_ERR":stylus_action error\n"); ++ } ++ } ++ ++ /* We use a buffer because want an atomic operation */ ++ buf[0] = 'P'; ++ buf[1] = ts.coords[0]; ++ buf[2] = ts.coords[1]; ++ ++ if (unlikely(__kfifo_put(ts.event_fifo, (unsigned char *)buf, ++ sizeof(int) * 3) != sizeof(int) * 3)) ++ /* should not happen */ ++ printk(KERN_ERR":stylus_action error\n"); ++ ++ writel(WAIT4INT(1), base_addr + S3C2410_ADCTSC); ++ mod_timer(&event_send_timer, jiffies + 1); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct clk *adc_clock; ++ ++/* ++ * The functions for inserting/removing us as a module. ++ */ ++ ++static int __init s3c2410ts_probe(struct platform_device *pdev) ++{ ++ int rc; ++ struct s3c2410_ts_mach_info *info; ++ struct input_dev *input_dev; ++ int ret = 0; ++ ++ dev_info(&pdev->dev, "Starting\n"); ++ ++ info = (struct s3c2410_ts_mach_info *)pdev->dev.platform_data; ++ ++ if (!info) ++ { ++ dev_err(&pdev->dev, "Hm... too bad: no platform data for ts\n"); ++ return -EINVAL; ++ } ++ ++#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG ++ printk(DEBUG_LVL "Entering s3c2410ts_init\n"); ++#endif ++ ++ adc_clock = clk_get(NULL, "adc"); ++ if (!adc_clock) { ++ dev_err(&pdev->dev, "failed to get adc clock source\n"); ++ return -ENOENT; ++ } ++ clk_enable(adc_clock); ++ ++#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG ++ printk(DEBUG_LVL "got and enabled clock\n"); ++#endif ++ ++ base_addr = ioremap(S3C2410_PA_ADC,0x20); ++ if (base_addr == NULL) { ++ dev_err(&pdev->dev, "Failed to remap register block\n"); ++ ret = -ENOMEM; ++ goto bail0; ++ } ++ ++ ++ /* If we acutally are a S3C2410: Configure GPIOs */ ++ if (!strcmp(pdev->name, "s3c2410-ts")) ++ s3c2410_ts_connect(); ++ ++ if ((info->presc & 0xff) > 0) ++ writel(S3C2410_ADCCON_PRSCEN | ++ S3C2410_ADCCON_PRSCVL(info->presc&0xFF), ++ base_addr + S3C2410_ADCCON); ++ else ++ writel(0, base_addr+S3C2410_ADCCON); ++ ++ /* Initialise registers */ ++ if ((info->delay & 0xffff) > 0) ++ writel(info->delay & 0xffff, base_addr + S3C2410_ADCDLY); ++ ++ writel(WAIT4INT(0), base_addr + S3C2410_ADCTSC); ++ ++ /* Initialise input stuff */ ++ memset(&ts, 0, sizeof(struct s3c2410ts)); ++ input_dev = input_allocate_device(); ++ ++ if (!input_dev) { ++ dev_err(&pdev->dev, "Unable to allocate the input device\n"); ++ ret = -ENOMEM; ++ goto bail1; ++ } ++ ++ ts.dev = input_dev; ++ ts.dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) | ++ BIT_MASK(EV_ABS); ++ ts.dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); ++ input_set_abs_params(ts.dev, ABS_X, 0, 0x3FF, 0, 0); ++ input_set_abs_params(ts.dev, ABS_Y, 0, 0x3FF, 0, 0); ++ input_set_abs_params(ts.dev, ABS_PRESSURE, 0, 1, 0, 0); ++ ++ ts.dev->name = s3c2410ts_name; ++ ts.dev->id.bustype = BUS_RS232; ++ ts.dev->id.vendor = 0xDEAD; ++ ts.dev->id.product = 0xBEEF; ++ ts.dev->id.version = S3C2410TSVERSION; ++ ts.state = TS_STATE_STANDBY; ++ ts.event_fifo = kfifo_alloc(TS_EVENT_FIFO_SIZE, GFP_KERNEL, NULL); ++ if (IS_ERR(ts.event_fifo)) { ++ ret = -EIO; ++ goto bail2; ++ } ++ ++ /* create the filter chain set up for the 2 coordinates we produce */ ++ ret = ts_filter_create_chain( ++ pdev, (struct ts_filter_api **)&info->filter_sequence, ++ (void *)&info->filter_config, ts.tsf, ARRAY_SIZE(ts.coords)); ++ if (ret) ++ dev_info(&pdev->dev, "%d filter(s) initialized\n", ret); ++ else /* this is OK, just means there won't be any filtering */ ++ dev_info(&pdev->dev, "Unfiltered output selected\n"); ++ ++ if (ts.tsf[0]) ++ (ts.tsf[0]->api->clear)(ts.tsf[0]); ++ else ++ dev_info(&pdev->dev, "No filtering\n"); ++ ++ /* Get irqs */ ++ if (request_irq(IRQ_ADC, stylus_action, IRQF_SAMPLE_RANDOM, ++ "s3c2410_action", ts.dev)) { ++ dev_err(&pdev->dev, "Could not allocate ts IRQ_ADC !\n"); ++ iounmap(base_addr); ++ ret = -EIO; ++ goto bail3; ++ } ++ if (request_irq(IRQ_TC, stylus_updown, IRQF_SAMPLE_RANDOM, ++ "s3c2410_action", ts.dev)) { ++ dev_err(&pdev->dev, "Could not allocate ts IRQ_TC !\n"); ++ free_irq(IRQ_ADC, ts.dev); ++ iounmap(base_addr); ++ ret = -EIO; ++ goto bail4; ++ } ++ ++ dev_info(&pdev->dev, "successfully loaded\n"); ++ ++ /* All went ok, so register to the input system */ ++ rc = input_register_device(ts.dev); ++ if (rc) { ++ ret = -EIO; ++ goto bail5; ++ } ++ ++ return 0; ++ ++bail5: ++ free_irq(IRQ_TC, ts.dev); ++ free_irq(IRQ_ADC, ts.dev); ++ clk_disable(adc_clock); ++ iounmap(base_addr); ++ disable_irq(IRQ_TC); ++bail4: ++ disable_irq(IRQ_ADC); ++bail3: ++ ts_filter_destroy_chain(pdev, ts.tsf); ++ kfifo_free(ts.event_fifo); ++bail2: ++ input_unregister_device(ts.dev); ++bail1: ++ iounmap(base_addr); ++bail0: ++ ++ return ret; ++} ++ ++static int s3c2410ts_remove(struct platform_device *pdev) ++{ ++ disable_irq(IRQ_ADC); ++ disable_irq(IRQ_TC); ++ free_irq(IRQ_TC,ts.dev); ++ free_irq(IRQ_ADC,ts.dev); ++ ++ if (adc_clock) { ++ clk_disable(adc_clock); ++ clk_put(adc_clock); ++ adc_clock = NULL; ++ } ++ ++ input_unregister_device(ts.dev); ++ iounmap(base_addr); ++ ++ ts_filter_destroy_chain(pdev, ts.tsf); ++ ++ kfifo_free(ts.event_fifo); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int s3c2410ts_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ writel(TSC_SLEEP, base_addr+S3C2410_ADCTSC); ++ writel(readl(base_addr+S3C2410_ADCCON) | S3C2410_ADCCON_STDBM, ++ base_addr+S3C2410_ADCCON); ++ ++ disable_irq(IRQ_ADC); ++ disable_irq(IRQ_TC); ++ ++ clk_disable(adc_clock); ++ ++ return 0; ++} ++ ++static int s3c2410ts_resume(struct platform_device *pdev) ++{ ++ struct s3c2410_ts_mach_info *info = ++ ( struct s3c2410_ts_mach_info *)pdev->dev.platform_data; ++ ++ clk_enable(adc_clock); ++ mdelay(1); ++ ++ if (ts.tsf[0]) ++ (ts.tsf[0]->api->clear)(ts.tsf[0]); ++ ++ enable_irq(IRQ_ADC); ++ enable_irq(IRQ_TC); ++ ++ if ((info->presc&0xff) > 0) ++ writel(S3C2410_ADCCON_PRSCEN | ++ S3C2410_ADCCON_PRSCVL(info->presc&0xFF), ++ base_addr+S3C2410_ADCCON); ++ else ++ writel(0,base_addr+S3C2410_ADCCON); ++ ++ /* Initialise registers */ ++ if ((info->delay & 0xffff) > 0) ++ writel(info->delay & 0xffff, base_addr+S3C2410_ADCDLY); ++ ++ writel(WAIT4INT(0), base_addr+S3C2410_ADCTSC); ++ ++ return 0; ++} ++ ++#else ++#define s3c2410ts_suspend NULL ++#define s3c2410ts_resume NULL ++#endif ++ ++static struct platform_driver s3c2410ts_driver = { ++ .driver = { ++ .name = "s3c2410-ts", ++ .owner = THIS_MODULE, ++ }, ++ .probe = s3c2410ts_probe, ++ .remove = s3c2410ts_remove, ++ .suspend = s3c2410ts_suspend, ++ .resume = s3c2410ts_resume, ++ ++}; ++ ++static struct platform_driver s3c2440ts_driver = { ++ .driver = { ++ .name = "s3c2440-ts", ++ .owner = THIS_MODULE, ++ }, ++ .probe = s3c2410ts_probe, ++ .remove = s3c2410ts_remove, ++ .suspend = s3c2410ts_suspend, ++ .resume = s3c2410ts_resume, ++ ++}; ++ ++static int __init s3c2410ts_init(void) ++{ ++ int rc; ++ ++ rc = platform_driver_register(&s3c2410ts_driver); ++ if (rc < 0) ++ return rc; ++ ++ rc = platform_driver_register(&s3c2440ts_driver); ++ if (rc < 0) ++ platform_driver_unregister(&s3c2410ts_driver); ++ ++ return rc; ++} ++ ++static void __exit s3c2410ts_exit(void) ++{ ++ platform_driver_unregister(&s3c2440ts_driver); ++ platform_driver_unregister(&s3c2410ts_driver); ++} ++ ++module_init(s3c2410ts_init); ++module_exit(s3c2410ts_exit); ++ +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/0002-S3C-Backported-openmoko-s-touchscreen-filters.patch b/recipes/linux/linux-2.6.29/micro2440/0002-S3C-Backported-openmoko-s-touchscreen-filters.patch new file mode 100644 index 0000000000..c171db81ec --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0002-S3C-Backported-openmoko-s-touchscreen-filters.patch @@ -0,0 +1,1260 @@ +From fe4e1650cff50bff8e8ad62dc036609f53307442 Mon Sep 17 00:00:00 2001 +From: Michel Pollet <buserror@gmail.com> +Date: Sat, 14 Mar 2009 10:24:07 +0000 +Subject: [PATCH] S3C: Backported openmoko's touchscreen filters + +Openmoko's touchscreen layer supports various filtering policy +for the ADC and touchscreen corrdinates. This is a staight port. +--- + drivers/input/touchscreen/Kconfig | 48 ++++++ + drivers/input/touchscreen/Makefile | 5 + + drivers/input/touchscreen/ts_filter.c | 73 +++++++++ + drivers/input/touchscreen/ts_filter.h | 62 +++++++ + drivers/input/touchscreen/ts_filter_group.c | 221 ++++++++++++++++++++++++++ + drivers/input/touchscreen/ts_filter_group.h | 39 +++++ + drivers/input/touchscreen/ts_filter_linear.c | 173 ++++++++++++++++++++ + drivers/input/touchscreen/ts_filter_linear.h | 64 ++++++++ + drivers/input/touchscreen/ts_filter_mean.c | 174 ++++++++++++++++++++ + drivers/input/touchscreen/ts_filter_mean.h | 34 ++++ + drivers/input/touchscreen/ts_filter_median.c | 217 +++++++++++++++++++++++++ + drivers/input/touchscreen/ts_filter_median.h | 36 ++++ + 12 files changed, 1146 insertions(+), 0 deletions(-) + create mode 100644 drivers/input/touchscreen/ts_filter.c + create mode 100644 drivers/input/touchscreen/ts_filter.h + create mode 100644 drivers/input/touchscreen/ts_filter_group.c + create mode 100644 drivers/input/touchscreen/ts_filter_group.h + create mode 100644 drivers/input/touchscreen/ts_filter_linear.c + create mode 100644 drivers/input/touchscreen/ts_filter_linear.h + create mode 100644 drivers/input/touchscreen/ts_filter_mean.c + create mode 100644 drivers/input/touchscreen/ts_filter_mean.h + create mode 100644 drivers/input/touchscreen/ts_filter_median.c + create mode 100644 drivers/input/touchscreen/ts_filter_median.h + +diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig +index 9076492..75ff0a8 100644 +--- a/drivers/input/touchscreen/Kconfig ++++ b/drivers/input/touchscreen/Kconfig +@@ -11,6 +11,54 @@ menuconfig INPUT_TOUCHSCREEN + + if INPUT_TOUCHSCREEN + ++menuconfig TOUCHSCREEN_FILTER ++ boolean "Touchscreen Filtering" ++ depends on INPUT_TOUCHSCREEN ++ select TOUCHSCREEN_FILTER_GROUP ++ select TOUCHSCREEN_FILTER_MEDIAN ++ select TOUCHSCREEN_FILTER_MEAN ++ select TOUCHSCREEN_FILTER_LINEAR ++ help ++ Select this to include kernel touchscreen filter support. The filters ++ can be combined in any order in your machine init and the parameters ++ for them can also be set there. ++ ++if TOUCHSCREEN_FILTER ++ ++config TOUCHSCREEN_FILTER_GROUP ++ bool "Group Touchscreen Filter" ++ depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER ++ default Y ++ help ++ Say Y here if you want to use the Group touchscreen filter, it ++ avoids using atypical samples. ++ ++config TOUCHSCREEN_FILTER_MEDIAN ++ bool "Median Average Touchscreen Filter" ++ depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER ++ default Y ++ help ++ Say Y here if you want to use the Median touchscreen filter, it's ++ highly effective if you data is noisy with occasional excursions. ++ ++config TOUCHSCREEN_FILTER_MEAN ++ bool "Mean Average Touchscreen Filter" ++ depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER ++ default Y ++ help ++ Say Y here if you want to use the Mean touchscreen filter, it ++ can further improve decent quality data by removing jitter ++ ++config TOUCHSCREEN_FILTER_LINEAR ++ bool "Linear Touchscreen Filter" ++ depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER ++ default Y ++ help ++ Say Y here if you want to use the Linear touchscreen filter, it ++ enables the use of calibration data for the touchscreen. ++ ++endif ++ + config TOUCHSCREEN_ADS7846 + tristate "ADS7846/TSC2046 and ADS7843 based touchscreens" + depends on SPI_MASTER +diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile +index fbcde99..4b0a03e 100644 +--- a/drivers/input/touchscreen/Makefile ++++ b/drivers/input/touchscreen/Makefile +@@ -35,3 +35,8 @@ wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9712) += wm9712.o + wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9713) += wm9713.o + obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o + obj-$(CONFIG_TOUCHSCREEN_S3C2410) += s3c2410_ts.o ++obj-$(CONFIG_TOUCHSCREEN_FILTER) += ts_filter.o ++obj-$(CONFIG_TOUCHSCREEN_FILTER_GROUP) += ts_filter_group.o ++obj-$(CONFIG_TOUCHSCREEN_FILTER_LINEAR) += ts_filter_linear.o ++obj-$(CONFIG_TOUCHSCREEN_FILTER_MEDIAN) += ts_filter_median.o ++obj-$(CONFIG_TOUCHSCREEN_FILTER_MEAN) += ts_filter_mean.o +diff --git a/drivers/input/touchscreen/ts_filter.c b/drivers/input/touchscreen/ts_filter.c +new file mode 100644 +index 0000000..832844d +--- /dev/null ++++ b/drivers/input/touchscreen/ts_filter.c +@@ -0,0 +1,73 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (c) 2008 Andy Green <andy@openmoko.com> ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/device.h> ++#include "ts_filter.h" ++ ++static DEFINE_MUTEX(chain_mutex); ++ ++int ts_filter_create_chain(struct platform_device *pdev, ++ struct ts_filter_api **api, void **config, ++ struct ts_filter **arr, int count_coords) ++{ ++ int count = 0; ++ struct ts_filter *last = NULL; ++ ++ if (!api) ++ return 0; ++ ++ mutex_lock(&chain_mutex); ++ ++ while (*api) { ++ *arr = ((*api)->create)(pdev, *config++, count_coords); ++ if (!*arr) { ++ printk(KERN_ERR "Filter %d failed init\n", count); ++ return count; ++ } ++ (*arr)->api = *api++; ++ if (last) ++ last->next = *arr; ++ last = *arr; ++ arr++; ++ count++; ++ } ++ ++ mutex_unlock(&chain_mutex); ++ ++ return count; ++} ++EXPORT_SYMBOL_GPL(ts_filter_create_chain); ++ ++void ts_filter_destroy_chain(struct platform_device *pdev, ++ struct ts_filter **arr) ++{ ++ struct ts_filter **first = arr; ++ ++ mutex_lock(&chain_mutex); ++ ++ while (*arr) { ++ ((*arr)->api->destroy)(pdev, *arr); ++ arr++; ++ } ++ *first = NULL; ++ ++ mutex_unlock(&chain_mutex); ++} ++EXPORT_SYMBOL_GPL(ts_filter_destroy_chain); ++ +diff --git a/drivers/input/touchscreen/ts_filter.h b/drivers/input/touchscreen/ts_filter.h +new file mode 100644 +index 0000000..3746e45 +--- /dev/null ++++ b/drivers/input/touchscreen/ts_filter.h +@@ -0,0 +1,62 @@ ++#ifndef __TS_FILTER_H__ ++#define __TS_FILTER_H__ ++ ++/* ++ * Touchscreen filter. ++ * ++ * (c) 2008 Andy Green <andy@openmoko.com> ++ */ ++ ++#include <linux/platform_device.h> ++ ++#define MAX_TS_FILTER_CHAIN 8 /* Max. filters we can chain up. */ ++#define MAX_TS_FILTER_COORDS 3 /* X, Y and Z (pressure). */ ++ ++struct ts_filter; ++ ++/* Operations that a filter can perform. */ ++ ++struct ts_filter_api { ++ struct ts_filter * (*create)(struct platform_device *pdev, void *config, ++ int count_coords); ++ void (*destroy)(struct platform_device *pdev, struct ts_filter *filter); ++ void (*clear)(struct ts_filter *filter); ++ int (*process)(struct ts_filter *filter, int *coords); ++ void (*scale)(struct ts_filter *filter, int *coords); ++}; ++ ++/* ++ * This is the common part of all filters. ++ * We use this type as an otherwise opaque handle on to ++ * the actual filter. Therefore you need one of these ++ * at the start of your actual filter struct. ++ */ ++ ++struct ts_filter { ++ struct ts_filter *next; /* Next in chain. */ ++ struct ts_filter_api *api; /* Operations to use for this object. */ ++ int count_coords; ++ int coords[MAX_TS_FILTER_COORDS]; ++}; ++ ++/* ++ * Helper to create a filter chain from an array of API pointers and ++ * array of config ints. Leaves pointers to created filters in arr ++ * array and fills in ->next pointers to create the chain. ++ */ ++ ++#ifdef CONFIG_TOUCHSCREEN_FILTER ++extern int ts_filter_create_chain(struct platform_device *pdev, ++ struct ts_filter_api **api, void **config, ++ struct ts_filter **arr, int count_coords); ++ ++/* Helper to destroy a whole chain from the list of filter pointers. */ ++ ++extern void ts_filter_destroy_chain(struct platform_device *pdev, ++ struct ts_filter **arr); ++#else ++#define ts_filter_create_chain(pdev, api, config, arr, count_coords) (0) ++#define ts_filter_destroy_chain(pdev, arr) do { } while (0) ++#endif ++ ++#endif +diff --git a/drivers/input/touchscreen/ts_filter_group.c b/drivers/input/touchscreen/ts_filter_group.c +new file mode 100644 +index 0000000..f2ecd92 +--- /dev/null ++++ b/drivers/input/touchscreen/ts_filter_group.c +@@ -0,0 +1,221 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (C) 2008 by Openmoko, Inc. ++ * Author: Nelson Castillo <arhuaco@freaks-unidos.net> ++ * All rights reserved. ++ * ++ * This filter is useful to reject samples that are not reliable. We consider ++ * that a sample is not reliable if it deviates form the Majority. ++ * ++ * 1) We collect S samples. ++ * ++ * 2) For each dimension: ++ * ++ * - We sort the points. ++ * - Points that are "close enough" are considered to be in the same set. ++ * - We choose the set with more elements. If more than "threshold" ++ * points are in this set we use the first and the last point of the set ++ * to define the valid range for this dimension [min, max], otherwise we ++ * discard all the points and go to step 1. ++ * ++ * 3) We consider the unsorted S samples and try to feed them to the next ++ * filter in the chain. If one of the points of each sample ++ * is not in the allowed range for its dimension, we discard the sample. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/slab.h> ++#include <linux/sort.h> ++#include "ts_filter_group.h" ++ ++static void ts_filter_group_clear_internal(struct ts_filter_group *tsfg, ++ int attempts) ++{ ++ tsfg->N = 0; ++ tsfg->tries_left = attempts; ++} ++ ++static void ts_filter_group_clear(struct ts_filter *tsf) ++{ ++ struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf; ++ ++ ts_filter_group_clear_internal(tsfg, tsfg->config->attempts); ++ ++ if (tsf->next) /* chain */ ++ (tsf->next->api->clear)(tsf->next); ++} ++ ++static struct ts_filter *ts_filter_group_create(struct platform_device *pdev, ++ void *conf, int count_coords) ++{ ++ struct ts_filter_group *tsfg; ++ int i; ++ ++ BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS)); ++ ++ tsfg = kzalloc(sizeof(struct ts_filter_group), GFP_KERNEL); ++ if (!tsfg) ++ return NULL; ++ ++ tsfg->config = (struct ts_filter_group_configuration *)conf; ++ tsfg->tsf.count_coords = count_coords; ++ ++ BUG_ON(tsfg->config->attempts <= 0); ++ ++ tsfg->samples[0] = kmalloc((2 + count_coords) * sizeof(int) * ++ tsfg->config->extent, GFP_KERNEL); ++ if (!tsfg->samples[0]) { ++ kfree(tsfg); ++ return NULL; ++ } ++ for (i = 1; i < count_coords; ++i) ++ tsfg->samples[i] = tsfg->samples[0] + i * tsfg->config->extent; ++ tsfg->sorted_samples = tsfg->samples[0] + count_coords * ++ tsfg->config->extent; ++ tsfg->group_size = tsfg->samples[0] + (1 + count_coords) * ++ tsfg->config->extent; ++ ++ ts_filter_group_clear_internal(tsfg, tsfg->config->attempts); ++ ++ printk(KERN_INFO" Created group ts filter len %d depth %d close %d " ++ "thresh %d\n", tsfg->config->extent, count_coords, ++ tsfg->config->close_enough, tsfg->config->threshold); ++ ++ return &tsfg->tsf; ++} ++ ++static void ts_filter_group_destroy(struct platform_device *pdev, ++ struct ts_filter *tsf) ++{ ++ struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf; ++ ++ kfree(tsfg->samples[0]); /* first guy has pointer from kmalloc */ ++ kfree(tsf); ++} ++ ++static void ts_filter_group_scale(struct ts_filter *tsf, int *coords) ++{ ++ if (tsf->next) ++ (tsf->next->api->scale)(tsf->next, coords); ++} ++ ++static int int_cmp(const void *_a, const void *_b) ++{ ++ const int *a = _a; ++ const int *b = _b; ++ ++ if (*a > *b) ++ return 1; ++ if (*a < *b) ++ return -1; ++ return 0; ++} ++ ++static int ts_filter_group_process(struct ts_filter *tsf, int *coords) ++{ ++ struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf; ++ int n; ++ int i; ++ int ret = 0; /* ask for more samples by default */ ++ ++ BUG_ON(tsfg->N >= tsfg->config->extent); ++ ++ for (n = 0; n < tsf->count_coords; n++) ++ tsfg->samples[n][tsfg->N] = coords[n]; ++ ++ if (++tsfg->N < tsfg->config->extent) ++ return 0; /* we meed more samples */ ++ ++ for (n = 0; n < tsfg->tsf.count_coords; n++) { ++ int *v = tsfg->sorted_samples; ++ int ngroups = 0; ++ int best_size; ++ int best_idx = 0; ++ int idx = 0; ++ ++ memcpy(v, tsfg->samples[n], tsfg->N * sizeof(int)); ++ sort(v, tsfg->N, sizeof(int), int_cmp, NULL); ++ ++ tsfg->group_size[0] = 1; ++ for (i = 1; i < tsfg->N; ++i) { ++ if (v[i] - v[i - 1] <= tsfg->config->close_enough) ++ tsfg->group_size[ngroups]++; ++ else ++ tsfg->group_size[++ngroups] = 1; ++ } ++ ngroups++; ++ ++ best_size = tsfg->group_size[0]; ++ for (i = 1; i < ngroups; i++) { ++ idx += tsfg->group_size[i - 1]; ++ if (best_size < tsfg->group_size[i]) { ++ best_size = tsfg->group_size[i]; ++ best_idx = idx; ++ } ++ } ++ ++ if (best_size < tsfg->config->threshold) { ++ /* this set is not good enough for us */ ++ if (--tsfg->tries_left) { ++ ts_filter_group_clear_internal ++ (tsfg, tsfg->tries_left); ++ return 0; /* ask for more samples */ ++ } ++ return -1; /* we give up */ ++ } ++ ++ tsfg->range_min[n] = v[best_idx]; ++ tsfg->range_max[n] = v[best_idx + best_size - 1]; ++ } ++ ++ for (i = 0; i < tsfg->N; ++i) { ++ int r; ++ ++ for (n = 0; n < tsfg->tsf.count_coords; ++n) { ++ coords[n] = tsfg->samples[n][i]; ++ if (coords[n] < tsfg->range_min[n] || ++ coords[n] > tsfg->range_max[n]) ++ break; ++ } ++ ++ if (n != tsfg->tsf.count_coords) /* sample not OK */ ++ continue; ++ ++ if (tsf->next) { ++ r = (tsf->next->api->process)(tsf->next, coords); ++ if (r) { ++ ret = r; ++ break; ++ } ++ } else if (i == tsfg->N - 1) { ++ ret = 1; ++ } ++ } ++ ++ ts_filter_group_clear_internal(tsfg, tsfg->config->attempts); ++ ++ return ret; ++} ++ ++struct ts_filter_api ts_filter_group_api = { ++ .create = ts_filter_group_create, ++ .destroy = ts_filter_group_destroy, ++ .clear = ts_filter_group_clear, ++ .process = ts_filter_group_process, ++ .scale = ts_filter_group_scale, ++}; ++ +diff --git a/drivers/input/touchscreen/ts_filter_group.h b/drivers/input/touchscreen/ts_filter_group.h +new file mode 100644 +index 0000000..c411080 +--- /dev/null ++++ b/drivers/input/touchscreen/ts_filter_group.h +@@ -0,0 +1,39 @@ ++#ifndef __TS_FILTER_GROUP_H__ ++#define __TS_FILTER_GROUP_H__ ++ ++#include "ts_filter.h" ++ ++/* ++ * Touchscreen group filter. ++ * ++ * Copyright (C) 2008 by Openmoko, Inc. ++ * Author: Nelson Castillo <arhuaco@freaks-unidos.net> ++ * ++ */ ++ ++struct ts_filter_group_configuration { ++ int extent; ++ int close_enough; ++ int threshold; ++ int attempts; ++}; ++ ++struct ts_filter_group { ++ struct ts_filter tsf; ++ struct ts_filter_group_configuration *config; ++ ++ int N; /* How many samples we have */ ++ int *samples[MAX_TS_FILTER_COORDS]; /* the samples, our input */ ++ ++ int *group_size; /* used for temporal computations */ ++ int *sorted_samples; /* used for temporal computations */ ++ ++ int range_max[MAX_TS_FILTER_COORDS]; /* max computed ranges */ ++ int range_min[MAX_TS_FILTER_COORDS]; /* min computed ranges */ ++ ++ int tries_left; /* We finish if we don't get enough samples */ ++}; ++ ++extern struct ts_filter_api ts_filter_group_api; ++ ++#endif +diff --git a/drivers/input/touchscreen/ts_filter_linear.c b/drivers/input/touchscreen/ts_filter_linear.c +new file mode 100644 +index 0000000..c336252 +--- /dev/null ++++ b/drivers/input/touchscreen/ts_filter_linear.c +@@ -0,0 +1,173 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (C) 2008 by Openmoko, Inc. ++ * Author: Nelson Castillo <arhuaco@freaks-unidos.net> ++ * All rights reserved. ++ * ++ * Linearly scale touchscreen values. ++ * ++ * Expose the TS_FILTER_LINEAR_NCONSTANTS for the linear transformation ++ * using sysfs. ++ * ++ */ ++ ++#include "ts_filter_linear.h" ++#include <linux/kernel.h> ++#include <linux/slab.h> ++#include <linux/string.h> ++ ++ ++/* sysfs functions */ ++ ++ ++static ssize_t const_attr_show(struct kobject *kobj, ++ struct attribute *attr, ++ char *buf) ++{ ++ struct const_attribute *a = to_const_attr(attr); ++ ++ return a->show(to_const_obj(kobj), a, buf); ++} ++ ++static ssize_t const_attr_store(struct kobject *kobj, ++ struct attribute *attr, ++ const char *buf, size_t len) ++{ ++ struct const_attribute *a = to_const_attr(attr); ++ ++ return a->store(to_const_obj(kobj), a, buf, len); ++} ++ ++static struct sysfs_ops const_sysfs_ops = { ++ .show = const_attr_show, ++ .store = const_attr_store, ++}; ++ ++static void const_release(struct kobject *kobj) ++{ ++ kfree(to_const_obj(kobj)->tsfl); ++} ++ ++static ssize_t const_show(struct const_obj *obj, struct const_attribute *attr, ++ char *buf) ++{ ++ int who; ++ ++ sscanf(attr->attr.name, "%d", &who); ++ return sprintf(buf, "%d\n", obj->tsfl->constants[who]); ++} ++ ++static ssize_t const_store(struct const_obj *obj, struct const_attribute *attr, ++ const char *buf, size_t count) ++{ ++ int who; ++ ++ sscanf(attr->attr.name, "%d", &who); ++ sscanf(buf, "%d", &obj->tsfl->constants[who]); ++ return count; ++} ++ ++/* filter functions */ ++ ++static struct ts_filter *ts_filter_linear_create(struct platform_device *pdev, ++ void *conf, int count_coords) ++{ ++ struct ts_filter_linear *tsfl; ++ int i; ++ int ret; ++ ++ tsfl = kzalloc(sizeof(struct ts_filter_linear), GFP_KERNEL); ++ if (!tsfl) ++ return NULL; ++ ++ tsfl->config = (struct ts_filter_linear_configuration *)conf; ++ tsfl->tsf.count_coords = count_coords; ++ ++ for (i = 0; i < TS_FILTER_LINEAR_NCONSTANTS; ++i) { ++ tsfl->constants[i] = tsfl->config->constants[i]; ++ ++ /* sysfs */ ++ sprintf(tsfl->attr_names[i], "%d", i); ++ tsfl->kattrs[i].attr.name = tsfl->attr_names[i]; ++ tsfl->kattrs[i].attr.mode = 0666; ++ tsfl->kattrs[i].show = const_show; ++ tsfl->kattrs[i].store = const_store; ++ tsfl->attrs[i] = &tsfl->kattrs[i].attr; ++ } ++ tsfl->attrs[i] = NULL; ++ ++ tsfl->const_ktype.sysfs_ops = &const_sysfs_ops; ++ tsfl->const_ktype.release = const_release; ++ tsfl->const_ktype.default_attrs = tsfl->attrs; ++ tsfl->c_obj.tsfl = tsfl; /* kernel frees tsfl in const_release */ ++ ++ ret = kobject_init_and_add(&tsfl->c_obj.kobj, &tsfl->const_ktype, ++ &pdev->dev.kobj, "calibration"); ++ if (ret) { ++ kobject_put(&tsfl->c_obj.kobj); ++ return NULL; ++ } ++ ++ printk(KERN_INFO" Created Linear ts filter depth %d\n", count_coords); ++ ++ return &tsfl->tsf; ++} ++ ++static void ts_filter_linear_destroy(struct platform_device *pdev, ++ struct ts_filter *tsf) ++{ ++ struct ts_filter_linear *tsfl = (struct ts_filter_linear *)tsf; ++ ++ /* kernel frees tsfl in const_release */ ++ kobject_put(&tsfl->c_obj.kobj); ++} ++ ++static void ts_filter_linear_clear(struct ts_filter *tsf) ++{ ++ if (tsf->next) /* chain */ ++ (tsf->next->api->clear)(tsf->next); ++} ++ ++ ++static void ts_filter_linear_scale(struct ts_filter *tsf, int *coords) ++{ ++ struct ts_filter_linear *tsfl = (struct ts_filter_linear *)tsf; ++ int *k = tsfl->constants; ++ int c0 = coords[tsfl->config->coord0]; ++ int c1 = coords[tsfl->config->coord1]; ++ ++ coords[tsfl->config->coord0] = (k[2] + k[0] * c0 + k[1] * c1) / k[6]; ++ coords[tsfl->config->coord1] = (k[5] + k[3] * c0 + k[4] * c1) / k[6]; ++ ++ if (tsf->next) ++ (tsf->next->api->scale)(tsf->next, coords); ++} ++ ++static int ts_filter_linear_process(struct ts_filter *tsf, int *coords) ++{ ++ if (tsf->next) ++ return (tsf->next->api->process)(tsf->next, coords); ++ ++ return 1; ++} ++ ++struct ts_filter_api ts_filter_linear_api = { ++ .create = ts_filter_linear_create, ++ .destroy = ts_filter_linear_destroy, ++ .clear = ts_filter_linear_clear, ++ .process = ts_filter_linear_process, ++ .scale = ts_filter_linear_scale, ++}; +diff --git a/drivers/input/touchscreen/ts_filter_linear.h b/drivers/input/touchscreen/ts_filter_linear.h +new file mode 100644 +index 0000000..fc27cf7 +--- /dev/null ++++ b/drivers/input/touchscreen/ts_filter_linear.h +@@ -0,0 +1,64 @@ ++#ifndef __TS_FILTER_LINEAR_H__ ++#define __TS_FILTER_LINEAR_H__ ++ ++#include "ts_filter.h" ++#include <linux/kobject.h> ++ ++/* ++ * Touchscreen linear filter. ++ * ++ * Copyright (C) 2008 by Openmoko, Inc. ++ * Author: Nelson Castillo <arhuaco@freaks-unidos.net> ++ * ++ */ ++ ++#define TS_FILTER_LINEAR_NCONSTANTS 7 ++ ++/* sysfs */ ++ ++struct ts_filter_linear; ++ ++struct const_obj { ++ struct ts_filter_linear *tsfl; ++ struct kobject kobj; ++}; ++ ++#define to_const_obj(x) container_of(x, struct const_obj, kobj) ++ ++struct const_attribute { ++ struct attribute attr; ++ ssize_t (*show)(struct const_obj *const, struct const_attribute *attr, ++ char *buf); ++ ssize_t (*store)(struct const_obj *const, struct const_attribute *attr, ++ const char *buf, size_t count); ++}; ++ ++#define to_const_attr(x) container_of(x, struct const_attribute, attr) ++ ++/* filter configuration */ ++ ++struct ts_filter_linear_configuration { ++ int constants[TS_FILTER_LINEAR_NCONSTANTS]; ++ int coord0; ++ int coord1; ++}; ++ ++/* the filter */ ++ ++struct ts_filter_linear { ++ struct ts_filter tsf; ++ struct ts_filter_linear_configuration *config; ++ ++ int constants[TS_FILTER_LINEAR_NCONSTANTS]; ++ ++ /* sysfs */ ++ struct const_obj c_obj; ++ struct kobj_type const_ktype; ++ struct const_attribute kattrs[TS_FILTER_LINEAR_NCONSTANTS]; ++ struct attribute *attrs[TS_FILTER_LINEAR_NCONSTANTS + 1]; ++ char attr_names[TS_FILTER_LINEAR_NCONSTANTS][2]; ++}; ++ ++extern struct ts_filter_api ts_filter_linear_api; ++ ++#endif +diff --git a/drivers/input/touchscreen/ts_filter_mean.c b/drivers/input/touchscreen/ts_filter_mean.c +new file mode 100644 +index 0000000..e4e0f2a +--- /dev/null ++++ b/drivers/input/touchscreen/ts_filter_mean.c +@@ -0,0 +1,174 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (c) 2008 Andy Green <andy@openmoko.com> ++ * ++ * ++ * Mean has no effect if the samples are changing by more that the ++ * threshold set by averaging_threshold in the configuration. ++ * ++ * However while samples come in that don't go outside this threshold from ++ * the last reported sample, Mean replaces the samples with a simple mean ++ * of a configurable number of samples (set by bits_filter_length in config, ++ * which is 2^n, so 5 there makes 32 sample averaging). ++ * ++ * Mean works well if the input data is already good quality, reducing + / - 1 ++ * sample jitter when the stylus is still, or moving very slowly, without ++ * introducing abrupt transitions or reducing ability to follow larger ++ * movements. If you set the threshold higher than the dynamic range of the ++ * coordinates, you can just use it as a simple mean average. ++ */ ++ ++#include <linux/errno.h> ++#include <linux/kernel.h> ++#include <linux/slab.h> ++#include "ts_filter_mean.h" ++ ++static void ts_filter_mean_clear_internal(struct ts_filter *tsf) ++{ ++ struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf; ++ int n; ++ ++ for (n = 0; n < tsfs->tsf.count_coords; n++) { ++ tsfs->fhead[n] = 0; ++ tsfs->ftail[n] = 0; ++ tsfs->lowpass[n] = 0; ++ } ++} ++ ++static void ts_filter_mean_clear(struct ts_filter *tsf) ++{ ++ ts_filter_mean_clear_internal(tsf); ++ ++ if (tsf->next) /* chain */ ++ (tsf->next->api->clear)(tsf->next); ++} ++ ++static struct ts_filter *ts_filter_mean_create(struct platform_device *pdev, ++ void *config, int count_coords) ++{ ++ int *p; ++ int n; ++ struct ts_filter_mean *tsfs = kzalloc( ++ sizeof(struct ts_filter_mean), GFP_KERNEL); ++ ++ if (!tsfs) ++ return NULL; ++ ++ BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS)); ++ tsfs->tsf.count_coords = count_coords; ++ ++ tsfs->config = (struct ts_filter_mean_configuration *)config; ++ ++ tsfs->config->extent = 1 << tsfs->config->bits_filter_length; ++ BUG_ON((tsfs->config->extent > 256) || (!tsfs->config->extent)); ++ ++ p = kmalloc(tsfs->config->extent * sizeof(int) * count_coords, ++ GFP_KERNEL); ++ if (!p) ++ return NULL; ++ ++ for (n = 0; n < count_coords; n++) { ++ tsfs->fifo[n] = p; ++ p += tsfs->config->extent; ++ } ++ ++ if (!tsfs->config->averaging_threshold) ++ tsfs->config->averaging_threshold = 0xffff; /* always active */ ++ ++ ts_filter_mean_clear_internal(&tsfs->tsf); ++ ++ printk(KERN_INFO" Created Mean ts filter len %d depth %d thresh %d\n", ++ tsfs->config->extent, count_coords, ++ tsfs->config->averaging_threshold); ++ ++ return &tsfs->tsf; ++} ++ ++static void ts_filter_mean_destroy(struct platform_device *pdev, ++ struct ts_filter *tsf) ++{ ++ struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf; ++ ++ kfree(tsfs->fifo[0]); /* first guy has pointer from kmalloc */ ++ kfree(tsf); ++} ++ ++static void ts_filter_mean_scale(struct ts_filter *tsf, int *coords) ++{ ++ if (tsf->next) /* chain */ ++ (tsf->next->api->scale)(tsf->next, coords); ++} ++ ++/* ++ * Give us the raw sample data in x and y, and if we return 1 then you can ++ * get a filtered coordinate from tsm->x and tsm->y. If we return 0 you didn't ++ * fill the filter with samples yet. ++ */ ++ ++static int ts_filter_mean_process(struct ts_filter *tsf, int *coords) ++{ ++ struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf; ++ int n; ++ int len; ++ ++ for (n = 0; n < tsf->count_coords; n++) { ++ ++ /* ++ * Has he moved far enough away that we should abandon current ++ * low pass filtering state? ++ */ ++ if ((coords[n] < (tsfs->reported[n] - ++ tsfs->config->averaging_threshold)) || ++ (coords[n] > (tsfs->reported[n] + ++ tsfs->config->averaging_threshold))) { ++ tsfs->fhead[n] = 0; ++ tsfs->ftail[n] = 0; ++ tsfs->lowpass[n] = 0; ++ } ++ ++ /* capture this sample into fifo and sum */ ++ tsfs->fifo[n][tsfs->fhead[n]++] = coords[n]; ++ if (tsfs->fhead[n] == tsfs->config->extent) ++ tsfs->fhead[n] = 0; ++ tsfs->lowpass[n] += coords[n]; ++ ++ /* adjust the sum into an average and use that*/ ++ len = (tsfs->fhead[n] - tsfs->ftail[n]) & ++ (tsfs->config->extent - 1); ++ coords[n] = (tsfs->lowpass[n] + (len >> 1)) / len; ++ tsfs->reported[n] = coords[n]; ++ ++ /* remove oldest sample if we are full */ ++ if (len == (tsfs->config->extent - 1)) { ++ tsfs->lowpass[n] -= tsfs->fifo[n][tsfs->ftail[n]++]; ++ if (tsfs->ftail[n] == tsfs->config->extent) ++ tsfs->ftail[n] = 0; ++ } ++ } ++ ++ if (tsf->next) /* chain */ ++ return (tsf->next->api->process)(tsf->next, coords); ++ ++ return 1; ++} ++ ++struct ts_filter_api ts_filter_mean_api = { ++ .create = ts_filter_mean_create, ++ .destroy = ts_filter_mean_destroy, ++ .clear = ts_filter_mean_clear, ++ .process = ts_filter_mean_process, ++ .scale = ts_filter_mean_scale, ++}; +diff --git a/drivers/input/touchscreen/ts_filter_mean.h b/drivers/input/touchscreen/ts_filter_mean.h +new file mode 100644 +index 0000000..44c506c +--- /dev/null ++++ b/drivers/input/touchscreen/ts_filter_mean.h +@@ -0,0 +1,34 @@ ++#ifndef __TS_FILTER_MEAN_H__ ++#define __TS_FILTER_MEAN_H__ ++ ++#include "ts_filter.h" ++ ++/* ++ * Touchscreen filter. ++ * ++ * mean ++ * ++ * (c) 2008 Andy Green <andy@openmoko.com> ++ */ ++ ++struct ts_filter_mean_configuration { ++ int bits_filter_length; ++ int averaging_threshold; ++ ++ int extent; ++}; ++ ++struct ts_filter_mean { ++ struct ts_filter tsf; ++ struct ts_filter_mean_configuration *config; ++ ++ int reported[MAX_TS_FILTER_COORDS]; ++ int lowpass[MAX_TS_FILTER_COORDS]; ++ int *fifo[MAX_TS_FILTER_COORDS]; ++ int fhead[MAX_TS_FILTER_COORDS]; ++ int ftail[MAX_TS_FILTER_COORDS]; ++}; ++ ++extern struct ts_filter_api ts_filter_mean_api; ++ ++#endif +diff --git a/drivers/input/touchscreen/ts_filter_median.c b/drivers/input/touchscreen/ts_filter_median.c +new file mode 100644 +index 0000000..b3b6a9c +--- /dev/null ++++ b/drivers/input/touchscreen/ts_filter_median.c +@@ -0,0 +1,217 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (c) 2008 Andy Green <andy@openmoko.com> ++ * ++ * ++ * Median averaging stuff. We sort incoming raw samples into an array of ++ * MEDIAN_SIZE length, discarding the oldest sample each time once we are full. ++ * We then return the sum of the middle three samples for X and Y. It means ++ * the final result must be divided by (3 * scaling factor) to correct for ++ * avoiding the repeated /3. ++ * ++ * This strongly rejects brief excursions away from a central point that is ++ * sticky in time compared to the excursion duration. ++ * ++ * Thanks to Dale Schumacher (who wrote some example code) and Carl-Daniel ++ * Halifinger who pointed out this would be a good method. ++ */ ++ ++#include <linux/errno.h> ++#include <linux/kernel.h> ++#include <linux/slab.h> ++#include "ts_filter_median.h" ++ ++static void ts_filter_median_insert(int *p, int sample, int count) ++{ ++ int n; ++ ++ /* search through what we got so far to find where to put sample */ ++ for (n = 0; n < count; n++) ++ /* we met somebody bigger than us? */ ++ if (sample < p[n]) { ++ /* starting from the end, push bigger guys down one */ ++ for (count--; count >= n; count--) ++ p[count + 1] = p[count]; ++ p[n] = sample; /* and put us in place of first bigger */ ++ return; ++ } ++ ++ p[count] = sample; /* nobody was bigger than us, add us on the end */ ++} ++ ++static void ts_filter_median_del(int *p, int value, int count) ++{ ++ int index; ++ ++ for (index = 0; index < count; index++) ++ if (p[index] == value) { ++ for (; index < count; index++) ++ p[index] = p[index + 1]; ++ return; ++ } ++} ++ ++ ++static void ts_filter_median_clear_internal(struct ts_filter *tsf) ++{ ++ struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf; ++ ++ tsfm->pos = 0; ++ tsfm->valid = 0; ++ ++} ++static void ts_filter_median_clear(struct ts_filter *tsf) ++{ ++ ts_filter_median_clear_internal(tsf); ++ ++ if (tsf->next) /* chain */ ++ (tsf->next->api->clear)(tsf->next); ++} ++ ++static struct ts_filter *ts_filter_median_create(struct platform_device *pdev, ++ void *conf, int count_coords) ++{ ++ int *p; ++ int n; ++ struct ts_filter_median *tsfm = kzalloc(sizeof(struct ts_filter_median), ++ GFP_KERNEL); ++ ++ if (!tsfm) ++ return NULL; ++ ++ tsfm->config = (struct ts_filter_median_configuration *)conf; ++ BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS)); ++ tsfm->tsf.count_coords = count_coords; ++ ++ tsfm->config->midpoint = (tsfm->config->extent >> 1) + 1; ++ ++ p = kmalloc(2 * count_coords * sizeof(int) * (tsfm->config->extent + 1), ++ GFP_KERNEL); ++ if (!p) { ++ kfree(tsfm); ++ return NULL; ++ } ++ ++ for (n = 0; n < count_coords; n++) { ++ tsfm->sort[n] = p; ++ p += tsfm->config->extent + 1; ++ tsfm->fifo[n] = p; ++ p += tsfm->config->extent + 1; ++ } ++ ++ ts_filter_median_clear_internal(&tsfm->tsf); ++ ++ printk(KERN_INFO" Created Median ts filter len %d depth %d dec %d\n", ++ tsfm->config->extent, count_coords, ++ tsfm->config->decimation_threshold); ++ ++ return &tsfm->tsf; ++} ++ ++static void ts_filter_median_destroy(struct platform_device *pdev, ++ struct ts_filter *tsf) ++{ ++ struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf; ++ ++ kfree(tsfm->sort[0]); /* first guy has pointer from kmalloc */ ++ kfree(tsf); ++} ++ ++static void ts_filter_median_scale(struct ts_filter *tsf, int *coords) ++{ ++ int n; ++ ++ for (n = 0; n < tsf->count_coords; n++) ++ coords[n] = (coords[n] + 2) / 3; ++ ++ if (tsf->next) /* chain */ ++ (tsf->next->api->scale)(tsf->next, coords); ++} ++ ++/* ++ * Give us the raw sample data coords, and if we return 1 then you can ++ * get a filtered coordinate from coords. If we return 0 you didn't ++ * fill all the filters with samples yet. ++ */ ++ ++static int ts_filter_median_process(struct ts_filter *tsf, int *coords) ++{ ++ struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf; ++ int n; ++ int movement = 1; ++ ++ for (n = 0; n < tsf->count_coords; n++) { ++ /* grab copy in insertion order to remove when oldest */ ++ tsfm->fifo[n][tsfm->pos] = coords[n]; ++ /* insert these samples in sorted order in the median arrays */ ++ ts_filter_median_insert(tsfm->sort[n], coords[n], tsfm->valid); ++ } ++ /* move us on in the fifo */ ++ if (++tsfm->pos == (tsfm->config->extent + 1)) ++ tsfm->pos = 0; ++ ++ /* we have finished a median sampling? */ ++ if (++tsfm->valid != tsfm->config->extent) ++ return 0; /* no valid sample to use */ ++ ++ /* discard the oldest sample in median sorted array */ ++ tsfm->valid--; ++ ++ /* ++ * Sum the middle 3 in the median sorted arrays. We don't divide back ++ * down which increases the sum resolution by a factor of 3 until the ++ * scale API is called. ++ */ ++ for (n = 0; n < tsfm->tsf.count_coords; n++) ++ /* perform the deletion of the oldest sample */ ++ ts_filter_median_del(tsfm->sort[n], tsfm->fifo[n][tsfm->pos], ++ tsfm->valid); ++ ++ tsfm->decimation_count--; ++ if (tsfm->decimation_count >= 0) ++ return 0; ++ ++ for (n = 0; n < tsfm->tsf.count_coords; n++) { ++ /* give the coordinate result from summing median 3 */ ++ coords[n] = tsfm->sort[n][tsfm->config->midpoint - 1] + ++ tsfm->sort[n][tsfm->config->midpoint] + ++ tsfm->sort[n][tsfm->config->midpoint + 1] ++ ; ++ ++ movement += abs(tsfm->last_issued[n] - coords[n]); ++ } ++ ++ if (movement > tsfm->config->decimation_threshold) /* fast */ ++ tsfm->decimation_count = tsfm->config->decimation_above; ++ else ++ tsfm->decimation_count = tsfm->config->decimation_below; ++ ++ memcpy(&tsfm->last_issued[0], coords, ++ tsfm->tsf.count_coords * sizeof(int)); ++ ++ if (tsf->next) /* chain */ ++ return (tsf->next->api->process)(tsf->next, coords); ++ ++ return 1; ++} ++ ++struct ts_filter_api ts_filter_median_api = { ++ .create = ts_filter_median_create, ++ .destroy = ts_filter_median_destroy, ++ .clear = ts_filter_median_clear, ++ .process = ts_filter_median_process, ++ .scale = ts_filter_median_scale, ++}; +diff --git a/drivers/input/touchscreen/ts_filter_median.h b/drivers/input/touchscreen/ts_filter_median.h +new file mode 100644 +index 0000000..8f25e27 +--- /dev/null ++++ b/drivers/input/touchscreen/ts_filter_median.h +@@ -0,0 +1,36 @@ ++#ifndef __TS_FILTER_MEDIAN_H__ ++#define __TS_FILTER_MEDIAN_H__ ++ ++#include "ts_filter.h" ++ ++/* ++ * Touchscreen filter. ++ * ++ * median ++ * ++ * (c) 2008 Andy Green <andy@openmoko.com> ++ */ ++ ++struct ts_filter_median_configuration { ++ int extent; ++ int midpoint; ++ int decimation_threshold; ++ int decimation_above; ++ int decimation_below; ++}; ++ ++struct ts_filter_median { ++ struct ts_filter tsf; ++ struct ts_filter_median_configuration *config; ++ ++ int decimation_count; ++ int last_issued[MAX_TS_FILTER_COORDS]; ++ int valid; /* how many samples in the sort buffer are valid */ ++ int *sort[MAX_TS_FILTER_COORDS]; /* samples taken for median */ ++ int *fifo[MAX_TS_FILTER_COORDS]; /* samples taken for median */ ++ int pos; /* where we are in the fifo sample memory */ ++}; ++ ++extern struct ts_filter_api ts_filter_median_api; ++ ++#endif +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/0003-VENDOR-armworks-logo.patch b/recipes/linux/linux-2.6.29/micro2440/0003-VENDOR-armworks-logo.patch new file mode 100644 index 0000000000..47909aa684 --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0003-VENDOR-armworks-logo.patch @@ -0,0 +1,12079 @@ +From 42c2c795ebc07043ee046dc95d1da5320a02e2ae Mon Sep 17 00:00:00 2001 +From: Michel Pollet <buserror@gmail.com> +Date: Wed, 25 Mar 2009 17:38:41 +0000 +Subject: [PATCH] VENDOR: armworks logo + +Sponsor's kernel logo + +Signed-off-by: Michel Pollet <buserror@gmail.com> +--- + drivers/video/logo/Kconfig | 5 + + drivers/video/logo/Makefile | 1 + + drivers/video/logo/logo.c | 6 + + drivers/video/logo/logo_armworks_clut224.ppm |12004 ++++++++++++++++++++++++++ + 4 files changed, 12016 insertions(+), 0 deletions(-) + create mode 100644 drivers/video/logo/logo_armworks_clut224.ppm + +diff --git a/drivers/video/logo/Kconfig b/drivers/video/logo/Kconfig +index 39ac49e..34834ed 100644 +--- a/drivers/video/logo/Kconfig ++++ b/drivers/video/logo/Kconfig +@@ -82,4 +82,9 @@ config LOGO_M32R_CLUT224 + depends on M32R + default y + ++config LOGO_ARMWORKS_CLUT224 ++ bool "Armworks 224-color logo" ++ depends on MACH_MINI2440 ++ default y ++ + endif # LOGO +diff --git a/drivers/video/logo/Makefile b/drivers/video/logo/Makefile +index b91251d..4d0423f 100644 +--- a/drivers/video/logo/Makefile ++++ b/drivers/video/logo/Makefile +@@ -15,6 +15,7 @@ obj-$(CONFIG_LOGO_SUPERH_MONO) += logo_superh_mono.o + obj-$(CONFIG_LOGO_SUPERH_VGA16) += logo_superh_vga16.o + obj-$(CONFIG_LOGO_SUPERH_CLUT224) += logo_superh_clut224.o + obj-$(CONFIG_LOGO_M32R_CLUT224) += logo_m32r_clut224.o ++obj-$(CONFIG_LOGO_ARMWORKS_CLUT224) += logo_armworks_clut224.o + + obj-$(CONFIG_SPU_BASE) += logo_spe_clut224.o + +diff --git a/drivers/video/logo/logo.c b/drivers/video/logo/logo.c +index 2e85a2b..451817e 100644 +--- a/drivers/video/logo/logo.c ++++ b/drivers/video/logo/logo.c +@@ -35,6 +35,7 @@ extern const struct linux_logo logo_superh_mono; + extern const struct linux_logo logo_superh_vga16; + extern const struct linux_logo logo_superh_clut224; + extern const struct linux_logo logo_m32r_clut224; ++extern const struct linux_logo logo_armworks_clut224; + + static int nologo; + module_param(nologo, bool, 0); +@@ -115,6 +116,11 @@ const struct linux_logo * __init_refok fb_find_logo(int depth) + /* M32R Linux logo */ + logo = &logo_m32r_clut224; + #endif ++#ifdef CONFIG_LOGO_ARMWORKS_CLUT224 ++ /* ARMWorks Linux logo -- lower priority */ ++ if (!logo) ++ logo = &logo_armworks_clut224; ++#endif + } + return logo; + } +diff --git a/drivers/video/logo/logo_armworks_clut224.ppm b/drivers/video/logo/logo_armworks_clut224.ppm +new file mode 100644 +index 0000000..a632167 +--- /dev/null ++++ b/drivers/video/logo/logo_armworks_clut224.ppm +@@ -0,0 +1,12004 @@ ++P3 ++# CREATOR: GIMP PNM Filter Version 1.1 ++160 25 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++237 ++229 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++222 ++222 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++239 ++236 ++254 ++249 ++242 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++219 ++190 ++253 ++70 ++115 ++253 ++70 ++115 ++253 ++248 ++253 ++255 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++107 ++98 ++252 ++0 ++46 ++254 ++105 ++154 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++245 ++233 ++253 ++26 ++69 ++251 ++51 ++102 ++253 ++252 ++250 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++194 ++181 ++253 ++0 ++46 ++254 ++31 ++58 ++250 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++250 ++254 ++74 ++79 ++250 ++96 ++142 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++255 ++246 ++253 ++107 ++108 ++252 ++51 ++102 ++253 ++54 ++95 ++252 ++39 ++86 ++253 ++54 ++95 ++252 ++94 ++132 ++253 ++196 ++207 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++248 ++253 ++255 ++252 ++250 ++254 ++146 ++155 ++253 ++113 ++137 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++255 ++246 ++253 ++51 ++102 ++253 ++206 ++211 ++254 ++252 ++250 ++254 ++93 ++105 ++254 ++92 ++119 ++252 ++146 ++172 ++254 ++252 ++250 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++250 ++254 ++120 ++126 ++252 ++168 ++190 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++105 ++113 ++251 ++92 ++119 ++252 ++121 ++164 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++255 ++240 ++254 ++1 ++52 ++251 ++5 ++39 ++251 ++214 ++226 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++201 ++165 ++255 ++31 ++58 ++250 ++0 ++58 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++74 ++79 ++250 ++0 ++63 ++251 ++121 ++164 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++234 ++219 ++253 ++120 ++126 ++252 ++51 ++102 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++172 ++152 ++253 ++31 ++58 ++250 ++0 ++46 ++254 ++213 ++233 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++181 ++166 ++251 ++31 ++58 ++250 ++0 ++74 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++250 ++226 ++255 ++33 ++46 ++250 ++1 ++52 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++33 ++46 ++250 ++0 ++63 ++251 ++0 ++63 ++251 ++0 ++63 ++251 ++31 ++58 ++250 ++12 ++65 ++254 ++1 ++52 ++251 ++94 ++132 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++31 ++58 ++250 ++0 ++46 ++254 ++241 ++254 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++194 ++166 ++255 ++0 ++58 ++254 ++117 ++152 ++253 ++254 ++255 ++252 ++107 ++108 ++252 ++0 ++63 ++251 ++25 ++80 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++231 ++254 ++33 ++46 ++250 ++39 ++86 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++241 ++214 ++253 ++1 ++52 ++251 ++31 ++58 ++250 ++176 ++178 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++231 ++254 ++1 ++52 ++251 ++1 ++52 ++251 ++223 ++230 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++201 ++170 ++252 ++0 ++63 ++251 ++0 ++63 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++74 ++79 ++250 ++0 ++63 ++251 ++129 ++161 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++120 ++126 ++252 ++31 ++58 ++250 ++70 ++115 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++240 ++254 ++39 ++86 ++253 ++70 ++115 ++253 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++178 ++163 ++255 ++0 ++63 ++251 ++0 ++74 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++132 ++122 ++252 ++26 ++69 ++251 ++0 ++63 ++251 ++155 ++174 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++246 ++253 ++31 ++58 ++250 ++31 ++58 ++250 ++113 ++137 ++251 ++197 ++177 ++253 ++146 ++155 ++253 ++52 ++67 ++251 ++26 ++69 ++251 ++33 ++46 ++250 ++214 ++226 ++253 ++254 ++255 ++252 ++255 ++246 ++253 ++1 ++52 ++251 ++0 ++63 ++251 ++155 ++174 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++84 ++94 ++254 ++0 ++63 ++251 ++51 ++102 ++253 ++254 ++255 ++252 ++215 ++182 ++254 ++31 ++58 ++250 ++1 ++52 ++251 ++227 ++239 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++186 ++158 ++253 ++0 ++63 ++251 ++1 ++52 ++251 ++227 ++239 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++172 ++152 ++253 ++0 ++63 ++251 ++1 ++52 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++231 ++254 ++0 ++58 ++254 ++0 ++58 ++254 ++222 ++222 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++201 ++170 ++252 ++31 ++58 ++250 ++0 ++63 ++251 ++254 ++255 ++252 ++249 ++242 ++255 ++212 ++203 ++255 ++249 ++242 ++255 ++252 ++250 ++254 ++171 ++171 ++253 ++159 ++159 ++253 ++188 ++197 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++246 ++253 ++168 ++164 ++253 ++159 ++159 ++253 ++206 ++211 ++254 ++65 ++74 ++252 ++0 ++63 ++251 ++129 ++161 ++253 ++254 ++255 ++252 ++211 ++207 ++253 ++211 ++207 ++253 ++255 ++246 ++253 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++250 ++254 ++220 ++206 ++252 ++211 ++207 ++253 ++248 ++253 ++255 ++254 ++255 ++252 ++245 ++233 ++253 ++168 ++164 ++253 ++159 ++159 ++253 ++191 ++191 ++253 ++255 ++252 ++251 ++222 ++222 ++254 ++105 ++113 ++251 ++31 ++58 ++250 ++54 ++95 ++252 ++237 ++229 ++255 ++220 ++206 ++252 ++248 ++253 ++255 ++239 ++236 ++254 ++211 ++207 ++253 ++222 ++222 ++254 ++254 ++255 ++252 ++168 ++164 ++253 ++159 ++159 ++253 ++191 ++191 ++253 ++222 ++222 ++254 ++237 ++229 ++255 ++234 ++219 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++246 ++253 ++194 ++181 ++253 ++159 ++159 ++253 ++168 ++164 ++253 ++206 ++211 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++178 ++163 ++255 ++31 ++58 ++250 ++0 ++74 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++248 ++253 ++255 ++255 ++252 ++251 ++0 ++46 ++254 ++0 ++63 ++251 ++19 ++66 ++255 ++26 ++90 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++31 ++58 ++250 ++31 ++58 ++250 ++168 ++190 ++254 ++255 ++252 ++251 ++248 ++253 ++255 ++255 ++235 ++252 ++0 ++58 ++254 ++0 ++63 ++251 ++176 ++178 ++253 ++254 ++255 ++252 ++219 ++190 ++253 ++31 ++58 ++250 ++12 ++65 ++254 ++51 ++102 ++253 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++1 ++52 ++251 ++26 ++69 ++251 ++0 ++58 ++254 ++248 ++253 ++255 ++252 ++255 ++251 ++1 ++52 ++251 ++31 ++58 ++250 ++121 ++164 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++65 ++74 ++252 ++26 ++69 ++251 ++31 ++58 ++250 ++146 ++172 ++254 ++248 ++253 ++255 ++255 ++252 ++251 ++74 ++79 ++250 ++31 ++58 ++250 ++55 ++116 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++203 ++186 ++253 ++159 ++159 ++253 ++171 ++171 ++253 ++239 ++236 ++254 ++252 ++250 ++254 ++248 ++253 ++255 ++255 ++252 ++251 ++211 ++207 ++253 ++211 ++207 ++253 ++254 ++255 ++252 ++206 ++193 ++253 ++159 ++159 ++253 ++171 ++171 ++253 ++245 ++233 ++253 ++31 ++58 ++250 ++0 ++58 ++254 ++223 ++230 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++220 ++206 ++252 ++223 ++212 ++252 ++188 ++197 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++171 ++171 ++253 ++159 ++159 ++253 ++176 ++178 ++253 ++249 ++242 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++201 ++165 ++255 ++0 ++63 ++251 ++31 ++58 ++250 ++248 ++253 ++255 ++197 ++177 ++253 ++1 ++52 ++251 ++25 ++80 ++252 ++1 ++52 ++251 ++1 ++52 ++251 ++0 ++58 ++254 ++1 ++52 ++251 ++39 ++86 ++253 ++254 ++255 ++252 ++252 ++250 ++254 ++248 ++253 ++255 ++197 ++177 ++253 ++0 ++46 ++254 ++0 ++63 ++251 ++1 ++52 ++251 ++0 ++58 ++254 ++52 ++67 ++251 ++31 ++58 ++250 ++121 ++164 ++254 ++252 ++231 ++254 ++0 ++46 ++254 ++0 ++46 ++254 ++214 ++226 ++253 ++255 ++252 ++251 ++254 ++255 ++252 ++240 ++208 ++253 ++0 ++46 ++254 ++5 ++39 ++251 ++230 ++244 ++251 ++172 ++152 ++253 ++1 ++52 ++251 ++31 ++58 ++250 ++31 ++58 ++250 ++0 ++58 ++254 ++0 ++74 ++252 ++105 ++113 ++251 ++0 ++63 ++251 ++26 ++69 ++251 ++0 ++63 ++251 ++1 ++52 ++251 ++0 ++46 ++254 ++214 ++226 ++253 ++178 ++163 ++255 ++1 ++52 ++251 ++0 ++63 ++251 ++0 ++63 ++251 ++0 ++58 ++254 ++31 ++58 ++250 ++1 ++52 ++251 ++1 ++52 ++251 ++31 ++58 ++250 ++0 ++46 ++254 ++232 ++249 ++255 ++254 ++255 ++252 ++33 ++46 ++250 ++0 ++58 ++254 ++31 ++58 ++250 ++0 ++63 ++251 ++31 ++58 ++250 ++0 ++74 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++181 ++166 ++251 ++0 ++63 ++251 ++0 ++74 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++201 ++170 ++252 ++0 ++63 ++251 ++26 ++69 ++251 ++52 ++67 ++251 ++1 ++52 ++251 ++222 ++222 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++246 ++253 ++1 ++52 ++251 ++0 ++58 ++254 ++170 ++195 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++255 ++240 ++254 ++1 ++52 ++251 ++31 ++58 ++250 ++176 ++178 ++253 ++254 ++255 ++252 ++186 ++158 ++253 ++0 ++63 ++251 ++26 ++69 ++251 ++1 ++52 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++215 ++182 ++254 ++31 ++58 ++250 ++52 ++67 ++251 ++1 ++52 ++251 ++223 ++230 ++252 ++252 ++250 ++254 ++107 ++98 ++252 ++0 ++63 ++251 ++84 ++94 ++254 ++254 ++255 ++252 ++242 ++226 ++254 ++1 ++52 ++251 ++0 ++63 ++251 ++26 ++69 ++251 ++26 ++90 ++253 ++255 ++252 ++251 ++255 ++240 ++254 ++1 ++52 ++251 ++0 ++63 ++251 ++151 ++183 ++252 ++255 ++252 ++251 ++220 ++206 ++252 ++1 ++52 ++251 ++0 ++58 ++254 ++31 ++58 ++250 ++0 ++63 ++251 ++0 ++46 ++254 ++94 ++132 ++253 ++254 ++255 ++252 ++249 ++242 ++255 ++5 ++39 ++251 ++1 ++52 ++251 ++26 ++69 ++251 ++1 ++52 ++251 ++0 ++63 ++251 ++33 ++46 ++250 ++222 ++222 ++254 ++0 ++58 ++254 ++0 ++58 ++254 ++214 ++226 ++253 ++254 ++255 ++252 ++139 ++132 ++253 ++1 ++52 ++251 ++5 ++39 ++251 ++168 ++190 ++254 ++220 ++206 ++252 ++33 ++46 ++250 ++31 ++58 ++250 ++31 ++58 ++250 ++31 ++58 ++250 ++5 ++39 ++251 ++232 ++237 ++253 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++201 ++170 ++252 ++0 ++63 ++251 ++31 ++58 ++250 ++252 ++250 ++254 ++197 ++177 ++253 ++0 ++63 ++251 ++12 ++65 ++254 ++52 ++67 ++251 ++159 ++159 ++253 ++105 ++113 ++251 ++0 ++58 ++254 ++31 ++58 ++250 ++82 ++136 ++253 ++254 ++255 ++252 ++210 ++185 ++254 ++1 ++52 ++251 ++0 ++63 ++251 ++26 ++69 ++251 ++159 ++159 ++253 ++67 ++107 ++251 ++0 ++63 ++251 ++0 ++63 ++251 ++121 ++164 ++254 ++255 ++235 ++252 ++1 ++52 ++251 ++1 ++52 ++251 ++223 ++230 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++234 ++219 ++253 ++31 ++58 ++250 ++1 ++52 ++251 ++248 ++253 ++255 ++0 ++46 ++254 ++26 ++69 ++251 ++51 ++102 ++253 ++181 ++166 ++251 ++105 ++113 ++251 ++96 ++142 ++252 ++176 ++178 ++253 ++64 ++85 ++253 ++26 ++69 ++251 ++26 ++69 ++251 ++137 ++146 ++254 ++92 ++119 ++252 ++230 ++244 ++251 ++181 ++166 ++251 ++0 ++63 ++251 ++52 ++67 ++251 ++1 ++52 ++251 ++146 ++155 ++253 ++78 ++97 ++251 ++145 ++140 ++253 ++54 ++95 ++252 ++0 ++63 ++251 ++0 ++58 ++254 ++241 ++254 ++255 ++254 ++255 ++252 ++145 ++140 ++253 ++92 ++119 ++252 ++159 ++159 ++253 ++120 ++126 ++252 ++0 ++58 ++254 ++31 ++58 ++250 ++82 ++136 ++253 ++254 ++255 ++252 ++181 ++166 ++251 ++31 ++58 ++250 ++0 ++74 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++83 ++87 ++252 ++0 ++63 ++251 ++113 ++167 ++252 ++105 ++113 ++251 ++0 ++63 ++251 ++96 ++142 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++246 ++253 ++31 ++58 ++250 ++31 ++58 ++250 ++146 ++172 ++254 ++252 ++231 ++254 ++220 ++206 ++252 ++84 ++94 ++254 ++26 ++69 ++251 ++0 ++46 ++254 ++230 ++244 ++251 ++254 ++255 ++252 ++93 ++105 ++254 ++0 ++63 ++251 ++26 ++69 ++251 ++0 ++58 ++254 ++173 ++186 ++252 ++255 ++252 ++251 ++105 ++113 ++251 ++0 ++63 ++251 ++0 ++63 ++251 ++31 ++58 ++250 ++191 ++191 ++253 ++254 ++255 ++252 ++197 ++177 ++253 ++0 ++63 ++251 ++1 ++52 ++251 ++248 ++253 ++249 ++186 ++158 ++253 ++0 ++63 ++251 ++31 ++58 ++250 ++26 ++69 ++251 ++1 ++52 ++251 ++230 ++244 ++251 ++181 ++166 ++251 ++31 ++58 ++250 ++0 ++46 ++254 ++241 ++254 ++255 ++252 ++231 ++254 ++5 ++39 ++251 ++26 ++69 ++251 ++26 ++69 ++251 ++171 ++171 ++253 ++105 ++113 ++251 ++0 ++58 ++254 ++0 ++58 ++254 ++146 ++172 ++254 ++255 ++252 ++251 ++1 ++52 ++251 ++26 ++69 ++251 ++31 ++58 ++250 ++51 ++102 ++253 ++145 ++140 ++253 ++77 ++122 ++252 ++255 ++240 ++254 ++1 ++52 ++251 ++1 ++52 ++251 ++232 ++237 ++253 ++186 ++158 ++253 ++0 ++58 ++254 ++1 ++52 ++251 ++146 ++172 ++254 ++252 ++250 ++254 ++64 ++85 ++253 ++52 ++67 ++251 ++25 ++80 ++252 ++171 ++171 ++253 ++145 ++140 ++253 ++26 ++69 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++201 ++165 ++255 ++0 ++63 ++251 ++0 ++63 ++251 ++254 ++255 ++252 ++197 ++177 ++253 ++31 ++58 ++250 ++31 ++58 ++250 ++252 ++255 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++132 ++122 ++252 ++0 ++63 ++251 ++0 ++74 ++252 ++254 ++255 ++252 ++52 ++67 ++251 ++26 ++69 ++251 ++39 ++86 ++253 ++252 ++255 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++74 ++79 ++250 ++31 ++58 ++250 ++129 ++161 ++253 ++255 ++235 ++252 ++0 ++58 ++254 ++0 ++58 ++254 ++222 ++222 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++241 ++214 ++253 ++0 ++58 ++254 ++1 ++52 ++251 ++252 ++250 ++254 ++1 ++52 ++251 ++0 ++63 ++251 ++155 ++174 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++113 ++137 ++251 ++31 ++58 ++250 ++55 ++116 ++253 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++250 ++254 ++186 ++158 ++253 ++0 ++63 ++251 ++0 ++58 ++254 ++206 ++211 ++254 ++254 ++255 ++252 ++252 ++255 ++251 ++255 ++252 ++251 ++229 ++192 ++251 ++0 ++63 ++251 ++1 ++52 ++251 ++241 ++254 ++255 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++250 ++254 ++252 ++250 ++254 ++186 ++158 ++253 ++0 ++63 ++251 ++25 ++80 ++252 ++252 ++250 ++254 ++181 ++166 ++251 ++0 ++63 ++251 ++26 ++69 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++250 ++226 ++255 ++0 ++58 ++254 ++1 ++52 ++251 ++214 ++226 ++253 ++194 ++166 ++255 ++0 ++63 ++251 ++0 ++58 ++254 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++33 ++46 ++250 ++26 ++69 ++251 ++31 ++58 ++250 ++0 ++58 ++254 ++31 ++58 ++250 ++26 ++69 ++251 ++1 ++52 ++251 ++144 ++180 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++52 ++67 ++251 ++52 ++67 ++251 ++31 ++58 ++250 ++26 ++69 ++251 ++55 ++116 ++253 ++252 ++250 ++254 ++1 ++52 ++251 ++26 ++69 ++251 ++0 ++63 ++251 ++26 ++69 ++251 ++96 ++142 ++252 ++248 ++253 ++255 ++252 ++250 ++254 ++0 ++46 ++254 ++0 ++63 ++251 ++170 ++195 ++252 ++83 ++87 ++252 ++0 ++63 ++251 ++144 ++180 ++254 ++65 ++74 ++252 ++31 ++58 ++250 ++144 ++180 ++254 ++107 ++98 ++252 ++0 ++63 ++251 ++51 ++102 ++253 ++254 ++255 ++252 ++132 ++122 ++252 ++0 ++63 ++251 ++0 ++63 ++251 ++254 ++255 ++252 ++248 ++253 ++255 ++255 ++252 ++251 ++105 ++113 ++251 ++52 ++67 ++251 ++0 ++63 ++251 ++254 ++255 ++252 ++1 ++52 ++251 ++52 ++67 ++251 ++55 ++116 ++253 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++231 ++254 ++0 ++58 ++254 ++31 ++58 ++250 ++206 ++193 ++253 ++1 ++52 ++251 ++0 ++63 ++251 ++114 ++145 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++52 ++67 ++251 ++0 ++63 ++251 ++77 ++122 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++194 ++166 ++255 ++31 ++58 ++250 ++0 ++63 ++251 ++252 ++255 ++251 ++197 ++177 ++253 ++0 ++63 ++251 ++0 ++63 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++201 ++170 ++252 ++31 ++58 ++250 ++0 ++74 ++252 ++254 ++255 ++252 ++1 ++52 ++251 ++31 ++58 ++250 ++188 ++197 ++251 ++248 ++253 ++255 ++255 ++252 ++251 ++255 ++252 ++251 ++74 ++79 ++250 ++0 ++63 ++251 ++121 ++164 ++254 ++255 ++240 ++254 ++0 ++58 ++254 ++0 ++58 ++254 ++223 ++230 ++252 ++248 ++253 ++255 ++255 ++252 ++251 ++241 ++214 ++253 ++0 ++58 ++254 ++1 ++52 ++251 ++248 ++253 ++249 ++83 ++87 ++252 ++0 ++63 ++251 ++0 ++58 ++254 ++54 ++95 ++252 ++191 ++191 ++253 ++254 ++255 ++252 ++255 ++252 ++251 ++120 ++126 ++252 ++0 ++63 ++251 ++67 ++107 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++181 ++166 ++251 ++0 ++63 ++251 ++0 ++58 ++254 ++248 ++253 ++255 ++255 ++252 ++251 ++252 ++255 ++251 ++252 ++250 ++254 ++215 ++182 ++254 ++0 ++63 ++251 ++1 ++52 ++251 ++241 ++254 ++255 ++255 ++252 ++251 ++203 ++186 ++253 ++50 ++77 ++252 ++0 ++46 ++254 ++33 ++46 ++250 ++0 ++58 ++254 ++52 ++67 ++251 ++26 ++69 ++251 ++252 ++250 ++254 ++181 ++166 ++251 ++0 ++63 ++251 ++0 ++74 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++145 ++140 ++253 ++0 ++63 ++251 ++0 ++63 ++251 ++255 ++252 ++251 ++255 ++246 ++253 ++1 ++52 ++251 ++31 ++58 ++250 ++151 ++183 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++1 ++52 ++251 ++0 ++63 ++251 ++26 ++69 ++251 ++0 ++63 ++251 ++0 ++63 ++251 ++0 ++58 ++254 ++176 ++178 ++253 ++254 ++255 ++252 ++252 ++250 ++254 ++255 ++235 ++252 ++0 ++58 ++254 ++31 ++58 ++250 ++206 ++193 ++253 ++1 ++52 ++251 ++0 ++58 ++254 ++240 ++208 ++253 ++0 ++58 ++254 ++26 ++69 ++251 ++186 ++158 ++253 ++0 ++63 ++251 ++70 ++115 ++253 ++255 ++252 ++251 ++254 ++255 ++252 ++84 ++94 ++254 ++26 ++69 ++251 ++25 ++80 ++252 ++0 ++63 ++251 ++1 ++52 ++251 ++227 ++239 ++254 ++173 ++144 ++251 ++0 ++63 ++251 ++64 ++85 ++253 ++26 ++69 ++251 ++0 ++63 ++251 ++155 ++174 ++251 ++254 ++255 ++252 ++50 ++77 ++252 ++0 ++63 ++251 ++82 ++136 ++253 ++255 ++252 ++251 ++252 ++250 ++254 ++255 ++252 ++251 ++229 ++192 ++251 ++0 ++58 ++254 ++1 ++52 ++251 ++252 ++255 ++251 ++1 ++52 ++251 ++31 ++58 ++250 ++206 ++193 ++253 ++248 ++253 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++231 ++254 ++1 ++52 ++251 ++0 ++63 ++251 ++0 ++58 ++254 ++26 ++69 ++251 ++1 ++52 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++163 ++139 ++252 ++0 ++63 ++251 ++0 ++63 ++251 ++0 ++74 ++252 ++146 ++172 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++248 ++253 ++255 ++201 ++165 ++255 ++0 ++63 ++251 ++31 ++58 ++250 ++255 ++252 ++251 ++197 ++177 ++253 ++0 ++58 ++254 ++0 ++63 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++252 ++250 ++254 ++201 ++170 ++252 ++0 ++63 ++251 ++50 ++77 ++252 ++255 ++246 ++253 ++1 ++52 ++251 ++0 ++58 ++254 ++196 ++207 ++254 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++74 ++79 ++250 ++0 ++63 ++251 ++121 ++164 ++254 ++252 ++231 ++254 ++1 ++52 ++251 ++0 ++58 ++254 ++214 ++226 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++241 ++214 ++253 ++31 ++58 ++250 ++0 ++58 ++254 ++219 ++245 ++255 ++252 ++255 ++251 ++107 ++108 ++252 ++1 ++52 ++251 ++0 ++63 ++251 ++0 ++58 ++254 ++54 ++95 ++252 ++254 ++255 ++252 ++120 ++126 ++252 ++31 ++58 ++250 ++67 ++107 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++255 ++251 ++178 ++163 ++255 ++0 ++63 ++251 ++25 ++80 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++252 ++250 ++254 ++254 ++255 ++252 ++223 ++186 ++252 ++0 ++58 ++254 ++0 ++58 ++254 ++248 ++253 ++249 ++197 ++177 ++253 ++33 ++46 ++250 ++52 ++67 ++251 ++0 ++63 ++251 ++94 ++132 ++253 ++78 ++97 ++251 ++0 ++63 ++251 ++0 ++74 ++252 ++254 ++255 ++252 ++181 ++166 ++251 ++0 ++63 ++251 ++26 ++69 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++31 ++58 ++250 ++52 ++67 ++251 ++77 ++122 ++252 ++220 ++206 ++252 ++223 ++212 ++252 ++65 ++74 ++252 ++0 ++63 ++251 ++26 ++90 ++253 ++248 ++253 ++255 ++255 ++246 ++253 ++1 ++52 ++251 ++31 ++58 ++250 ++176 ++205 ++255 ++254 ++255 ++252 ++0 ++63 ++251 ++26 ++69 ++251 ++0 ++74 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++230 ++202 ++255 ++0 ++58 ++254 ++0 ++58 ++254 ++254 ++255 ++252 ++52 ++67 ++251 ++52 ++67 ++251 ++50 ++77 ++252 ++0 ++63 ++251 ++96 ++142 ++252 ++219 ++190 ++253 ++0 ++58 ++254 ++1 ++52 ++251 ++252 ++250 ++254 ++248 ++253 ++249 ++181 ++166 ++251 ++0 ++63 ++251 ++26 ++69 ++251 ++52 ++67 ++251 ++39 ++86 ++253 ++252 ++255 ++251 ++242 ++226 ++254 ++31 ++58 ++250 ++0 ++63 ++251 ++26 ++69 ++251 ++1 ++52 ++251 ++238 ++247 ++255 ++248 ++253 ++255 ++65 ++74 ++252 ++31 ++58 ++250 ++121 ++164 ++254 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++240 ++208 ++253 ++0 ++58 ++254 ++1 ++52 ++251 ++239 ++236 ++254 ++1 ++52 ++251 ++0 ++63 ++251 ++222 ++222 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++252 ++231 ++254 ++0 ++58 ++254 ++52 ++67 ++251 ++0 ++63 ++251 ++0 ++63 ++251 ++26 ++69 ++251 ++94 ++132 ++253 ++248 ++253 ++255 ++248 ++253 ++255 ++254 ++255 ++252 ++155 ++151 ++252 ++0 ++46 ++254 ++31 ++58 ++250 ++31 ++58 ++250 ++19 ++66 ++255 ++252 ++250 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++194 ++166 ++255 ++0 ++63 ++251 ++31 ++58 ++250 ++254 ++255 ++252 ++197 ++177 ++253 ++31 ++58 ++250 ++0 ++63 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++201 ++170 ++252 ++0 ++63 ++251 ++0 ++74 ++252 ++255 ++252 ++251 ++1 ++52 ++251 ++31 ++58 ++250 ++188 ++197 ++251 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++74 ++79 ++250 ++31 ++58 ++250 ++121 ++164 ++254 ++245 ++233 ++253 ++1 ++52 ++251 ++1 ++52 ++251 ++223 ++230 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++250 ++226 ++255 ++1 ++52 ++251 ++1 ++52 ++251 ++227 ++239 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++240 ++254 ++93 ++105 ++254 ++0 ++63 ++251 ++0 ++58 ++254 ++168 ++190 ++254 ++145 ++140 ++253 ++0 ++63 ++251 ++67 ++107 ++251 ++248 ++253 ++255 ++252 ++250 ++254 ++254 ++255 ++252 ++181 ++166 ++251 ++31 ++58 ++250 ++0 ++74 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++248 ++253 ++255 ++248 ++253 ++255 ++223 ++186 ++252 ++31 ++58 ++250 ++1 ++52 ++251 ++248 ++253 ++249 ++64 ++85 ++253 ++0 ++63 ++251 ++55 ++116 ++253 ++255 ++252 ++251 ++248 ++253 ++255 ++220 ++206 ++252 ++1 ++52 ++251 ++0 ++74 ++252 ++252 ++250 ++254 ++181 ++166 ++251 ++0 ++63 ++251 ++0 ++74 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++215 ++182 ++254 ++0 ++58 ++254 ++52 ++67 ++251 ++0 ++63 ++251 ++0 ++58 ++254 ++0 ++58 ++254 ++0 ++63 ++251 ++26 ++69 ++251 ++1 ++52 ++251 ++213 ++233 ++255 ++255 ++252 ++251 ++31 ++58 ++250 ++31 ++58 ++250 ++168 ++190 ++254 ++255 ++252 ++251 ++230 ++202 ++255 ++1 ++52 ++251 ++31 ++58 ++250 ++114 ++145 ++251 ++254 ++255 ++252 ++173 ++144 ++251 ++0 ++63 ++251 ++50 ++77 ++252 ++248 ++253 ++249 ++172 ++152 ++253 ++0 ++63 ++251 ++26 ++69 ++251 ++0 ++58 ++254 ++195 ++216 ++245 ++252 ++231 ++254 ++0 ++58 ++254 ++1 ++52 ++251 ++227 ++239 ++254 ++255 ++252 ++251 ++255 ++240 ++254 ++1 ++52 ++251 ++26 ++69 ++251 ++31 ++58 ++250 ++121 ++164 ++254 ++243 ++245 ++242 ++254 ++255 ++252 ++50 ++77 ++252 ++52 ++67 ++251 ++52 ++67 ++251 ++26 ++90 ++253 ++255 ++252 ++251 ++255 ++252 ++251 ++64 ++85 ++253 ++0 ++63 ++251 ++94 ++132 ++253 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++210 ++185 ++254 ++0 ++63 ++251 ++1 ++52 ++251 ++248 ++253 ++249 ++0 ++46 ++254 ++0 ++58 ++254 ++196 ++207 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++231 ++254 ++0 ++58 ++254 ++52 ++67 ++251 ++77 ++122 ++252 ++132 ++122 ++252 ++0 ++63 ++251 ++33 ++46 ++250 ++222 ++222 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++255 ++251 ++254 ++255 ++252 ++145 ++140 ++253 ++0 ++63 ++251 ++0 ++58 ++254 ++77 ++122 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++255 ++251 ++201 ++170 ++252 ++0 ++63 ++251 ++0 ++63 ++251 ++254 ++255 ++252 ++197 ++177 ++253 ++0 ++63 ++251 ++0 ++63 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++201 ++165 ++255 ++31 ++58 ++250 ++50 ++77 ++252 ++252 ++250 ++254 ++52 ++67 ++251 ++0 ++63 ++251 ++25 ++80 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++243 ++245 ++242 ++74 ++79 ++250 ++0 ++63 ++251 ++129 ++161 ++253 ++255 ++246 ++253 ++1 ++52 ++251 ++31 ++58 ++250 ++168 ++190 ++254 ++254 ++255 ++252 ++252 ++255 ++251 ++163 ++139 ++252 ++0 ++63 ++251 ++1 ++52 ++251 ++230 ++244 ++251 ++237 ++229 ++255 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++31 ++58 ++250 ++0 ++63 ++251 ++121 ++164 ++254 ++113 ++137 ++251 ++0 ++63 ++251 ++26 ++90 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++249 ++178 ++163 ++255 ++0 ++63 ++251 ++26 ++69 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++210 ++185 ++254 ++0 ++63 ++251 ++0 ++58 ++254 ++254 ++255 ++252 ++26 ++69 ++251 ++31 ++58 ++250 ++144 ++180 ++254 ++254 ++255 ++252 ++252 ++250 ++254 ++163 ++139 ++252 ++0 ++63 ++251 ++0 ++58 ++254 ++254 ++255 ++252 ++186 ++158 ++253 ++31 ++58 ++250 ++50 ++77 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++83 ++87 ++252 ++0 ++63 ++251 ++26 ++69 ++251 ++146 ++155 ++253 ++137 ++146 ++254 ++137 ++146 ++254 ++155 ++151 ++252 ++0 ++58 ++254 ++0 ++63 ++251 ++113 ++137 ++251 ++255 ++252 ++251 ++33 ++46 ++250 ++0 ++63 ++251 ++170 ++195 ++252 ++252 ++255 ++251 ++255 ++252 ++251 ++120 ++113 ++253 ++26 ++69 ++251 ++33 ++46 ++250 ++227 ++239 ++254 ++105 ++113 ++251 ++31 ++58 ++250 ++77 ++122 ++252 ++252 ++250 ++254 ++250 ++226 ++255 ++31 ++58 ++250 ++0 ++63 ++251 ++26 ++69 ++251 ++255 ++252 ++251 ++252 ++255 ++251 ++1 ++52 ++251 ++31 ++58 ++250 ++176 ++178 ++253 ++255 ++252 ++251 ++248 ++253 ++249 ++64 ++85 ++253 ++0 ++63 ++251 ++1 ++52 ++251 ++223 ++230 ++252 ++255 ++252 ++251 ++252 ++250 ++254 ++186 ++158 ++253 ++0 ++63 ++251 ++0 ++58 ++254 ++129 ++161 ++253 ++255 ++252 ++251 ++252 ++250 ++254 ++139 ++132 ++253 ++0 ++63 ++251 ++0 ++63 ++251 ++252 ++250 ++254 ++255 ++252 ++251 ++248 ++253 ++255 ++74 ++79 ++250 ++0 ++63 ++251 ++0 ++74 ++252 ++255 ++252 ++251 ++0 ++58 ++254 ++0 ++58 ++254 ++206 ++211 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++243 ++245 ++242 ++252 ++231 ++254 ++0 ++58 ++254 ++1 ++52 ++251 ++232 ++233 ++243 ++248 ++253 ++249 ++31 ++58 ++250 ++26 ++69 ++251 ++0 ++74 ++252 ++248 ++253 ++255 ++249 ++242 ++255 ++232 ++237 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++132 ++122 ++252 ++0 ++63 ++251 ++51 ++102 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++252 ++250 ++254 ++252 ++250 ++254 ++201 ++165 ++255 ++0 ++63 ++251 ++31 ++58 ++250 ++255 ++252 ++251 ++197 ++177 ++253 ++31 ++58 ++250 ++0 ++63 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++194 ++166 ++255 ++31 ++58 ++250 ++0 ++74 ++252 ++252 ++250 ++254 ++172 ++152 ++253 ++0 ++58 ++254 ++0 ++63 ++251 ++0 ++58 ++254 ++105 ++113 ++251 ++50 ++77 ++252 ++0 ++63 ++251 ++52 ++67 ++251 ++129 ++161 ++253 ++252 ++255 ++251 ++52 ++67 ++251 ++0 ++63 ++251 ++0 ++58 ++254 ++67 ++107 ++251 ++65 ++74 ++252 ++31 ++58 ++250 ++52 ++67 ++251 ++1 ++52 ++251 ++248 ++253 ++249 ++107 ++98 ++252 ++0 ++63 ++251 ++113 ++137 ++251 ++107 ++108 ++252 ++0 ++63 ++251 ++0 ++58 ++254 ++191 ++191 ++253 ++186 ++158 ++253 ++31 ++58 ++250 ++0 ++63 ++251 ++26 ++90 ++253 ++64 ++85 ++253 ++117 ++152 ++253 ++197 ++177 ++253 ++0 ++63 ++251 ++0 ++74 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++215 ++182 ++254 ++0 ++58 ++254 ++0 ++58 ++254 ++252 ++255 ++251 ++78 ++97 ++251 ++52 ++67 ++251 ++1 ++52 ++251 ++113 ++137 ++251 ++93 ++105 ++254 ++0 ++58 ++254 ++52 ++67 ++251 ++1 ++52 ++251 ++248 ++253 ++249 ++181 ++166 ++251 ++0 ++63 ++251 ++1 ++52 ++251 ++223 ++230 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++252 ++231 ++254 ++31 ++58 ++250 ++0 ++63 ++251 ++117 ++152 ++253 ++255 ++252 ++251 ++255 ++252 ++251 ++243 ++245 ++242 ++252 ++255 ++251 ++105 ++113 ++251 ++0 ++63 ++251 ++0 ++63 ++251 ++254 ++255 ++252 ++1 ++52 ++251 ++0 ++58 ++254 ++168 ++190 ++254 ++248 ++253 ++255 ++255 ++252 ++251 ++248 ++253 ++255 ++0 ++58 ++254 ++0 ++63 ++251 ++51 ++102 ++253 ++50 ++77 ++252 ++0 ++63 ++251 ++146 ++172 ++254 ++252 ++255 ++251 ++255 ++252 ++251 ++83 ++87 ++252 ++0 ++63 ++251 ++129 ++161 ++253 ++252 ++250 ++254 ++254 ++255 ++252 ++83 ++87 ++252 ++0 ++63 ++251 ++105 ++154 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++186 ++158 ++253 ++0 ++63 ++251 ++39 ++86 ++253 ++254 ++255 ++252 ++252 ++255 ++251 ++252 ++255 ++251 ++255 ++235 ++252 ++0 ++58 ++254 ++1 ++52 ++251 ++227 ++239 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++246 ++253 ++0 ++46 ++254 ++0 ++63 ++251 ++0 ++63 ++251 ++113 ++137 ++251 ++50 ++77 ++252 ++52 ++67 ++251 ++1 ++52 ++251 ++170 ++195 ++252 ++255 ++252 ++251 ++1 ++52 ++251 ++31 ++58 ++250 ++206 ++211 ++254 ++254 ++255 ++252 ++248 ++253 ++255 ++252 ++255 ++251 ++252 ++231 ++254 ++0 ++58 ++254 ++1 ++52 ++251 ++237 ++229 ++255 ++252 ++255 ++251 ++230 ++202 ++255 ++1 ++52 ++251 ++31 ++58 ++250 ++105 ++154 ++254 ++194 ++166 ++255 ++1 ++52 ++251 ++77 ++122 ++252 ++113 ++137 ++251 ++31 ++58 ++250 ++0 ++63 ++251 ++82 ++136 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++186 ++158 ++253 ++33 ++46 ++250 ++0 ++46 ++254 ++254 ++255 ++252 ++201 ++170 ++252 ++33 ++46 ++250 ++0 ++46 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++201 ++165 ++255 ++1 ++52 ++251 ++31 ++58 ++250 ++254 ++255 ++252 ++252 ++255 ++251 ++139 ++132 ++253 ++1 ++52 ++251 ++0 ++63 ++251 ++1 ++52 ++251 ++0 ++58 ++254 ++31 ++58 ++250 ++0 ++46 ++254 ++105 ++154 ++254 ++255 ++252 ++251 ++223 ++212 ++252 ++1 ++52 ++251 ++0 ++58 ++254 ++0 ++58 ++254 ++1 ++52 ++251 ++78 ++97 ++251 ++1 ++52 ++251 ++5 ++39 ++251 ++241 ++254 ++255 ++26 ++69 ++251 ++1 ++52 ++251 ++1 ++52 ++251 ++0 ++58 ++254 ++1 ++52 ++251 ++94 ++132 ++253 ++252 ++255 ++251 ++254 ++255 ++252 ++50 ++77 ++252 ++1 ++52 ++251 ++31 ++58 ++250 ++1 ++52 ++251 ++129 ++161 ++253 ++168 ++164 ++253 ++33 ++46 ++250 ++31 ++58 ++250 ++252 ++250 ++254 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++201 ++170 ++252 ++1 ++52 ++251 ++5 ++39 ++251 ++241 ++254 ++255 ++255 ++240 ++254 ++0 ++63 ++251 ++0 ++58 ++254 ++0 ++58 ++254 ++0 ++46 ++254 ++77 ++122 ++252 ++26 ++69 ++251 ++0 ++58 ++254 ++77 ++122 ++252 ++241 ++214 ++253 ++0 ++46 ++254 ++0 ++58 ++254 ++39 ++86 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++249 ++139 ++132 ++253 ++33 ++46 ++250 ++33 ++46 ++250 ++227 ++239 ++254 ++255 ++252 ++251 ++255 ++252 ++251 ++248 ++253 ++255 ++255 ++252 ++251 ++229 ++192 ++251 ++33 ++46 ++250 ++5 ++39 ++251 ++151 ++183 ++252 ++33 ++46 ++250 ++33 ++46 ++250 ++151 ++183 ++252 ++255 ++252 ++251 ++252 ++250 ++254 ++255 ++252 ++251 ++210 ++185 ++254 ++33 ++46 ++250 ++1 ++52 ++251 ++1 ++52 ++251 ++5 ++39 ++251 ++196 ++207 ++254 ++252 ++250 ++254 ++248 ++253 ++255 ++201 ++170 ++252 ++32 ++30 ++249 ++227 ++239 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++120 ++126 ++252 ++0 ++46 ++254 ++26 ++69 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++255 ++235 ++252 ++5 ++39 ++251 ++105 ++154 ++254 ++254 ++255 ++252 ++252 ++250 ++254 ++248 ++253 ++255 ++248 ++253 ++255 ++74 ++79 ++250 ++26 ++69 ++251 ++252 ++250 ++254 ++252 ++250 ++254 ++248 ++253 ++255 ++255 ++252 ++251 ++250 ++226 ++255 ++52 ++67 ++251 ++1 ++52 ++251 ++0 ++58 ++254 ++1 ++52 ++251 ++0 ++58 ++254 ++155 ++174 ++251 ++252 ++250 ++254 ++255 ++240 ++254 ++5 ++39 ++251 ++0 ++46 ++254 ++196 ++207 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++252 ++231 ++254 ++5 ++39 ++251 ++0 ++46 ++254 ++214 ++226 ++253 ++248 ++253 ++255 ++254 ++255 ++252 ++120 ++113 ++253 ++1 ++52 ++251 ++33 ++46 ++250 ++25 ++80 ++252 ++1 ++52 ++251 ++33 ++46 ++250 ++1 ++52 ++251 ++1 ++52 ++251 ++54 ++95 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++245 ++233 ++253 ++245 ++233 ++253 ++248 ++253 ++255 ++248 ++253 ++255 ++245 ++233 ++253 ++245 ++233 ++253 ++254 ++255 ++252 ++252 ++250 ++254 ++248 ++253 ++255 ++252 ++250 ++254 ++237 ++229 ++255 ++245 ++233 ++253 ++255 ++252 ++251 ++252 ++255 ++251 ++254 ++255 ++252 ++249 ++242 ++255 ++211 ++207 ++253 ++211 ++207 ++253 ++243 ++245 ++242 ++255 ++246 ++253 ++245 ++233 ++253 ++249 ++242 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++220 ++206 ++252 ++211 ++207 ++253 ++232 ++233 ++243 ++252 ++255 ++251 ++237 ++229 ++255 ++245 ++233 ++253 ++248 ++253 ++255 ++255 ++252 ++251 ++237 ++229 ++255 ++220 ++206 ++252 ++211 ++207 ++253 ++234 ++239 ++242 ++252 ++250 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++220 ++206 ++252 ++220 ++206 ++252 ++223 ++212 ++252 ++249 ++242 ++255 ++252 ++250 ++254 ++237 ++229 ++255 ++239 ++236 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++242 ++226 ++254 ++237 ++229 ++255 ++252 ++255 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++223 ++212 ++252 ++211 ++207 ++253 ++245 ++233 ++253 ++248 ++253 ++255 ++255 ++246 ++253 ++211 ++207 ++253 ++240 ++235 ++233 ++254 ++255 ++252 ++242 ++226 ++254 ++211 ++207 ++253 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++252 ++250 ++254 ++239 ++236 ++254 ++242 ++226 ++254 ++237 ++229 ++255 ++252 ++255 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++250 ++254 ++248 ++253 ++255 ++252 ++255 ++251 ++245 ++233 ++253 ++242 ++226 ++254 ++249 ++242 ++255 ++245 ++233 ++253 ++242 ++226 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++255 ++251 ++248 ++253 ++249 ++252 ++231 ++254 ++245 ++233 ++253 ++245 ++233 ++253 ++237 ++229 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++248 ++253 ++249 ++211 ++207 ++253 ++252 ++250 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++249 ++242 ++255 ++237 ++229 ++255 ++239 ++236 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++255 ++251 ++220 ++206 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++255 ++251 ++237 ++229 ++255 ++237 ++229 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++250 ++254 ++248 ++253 ++255 ++252 ++255 ++251 ++252 ++255 ++251 ++234 ++219 ++253 ++211 ++207 ++253 ++223 ++212 ++252 ++243 ++245 ++242 ++254 ++255 ++252 ++252 ++255 ++251 ++252 ++255 ++251 ++245 ++233 ++253 ++237 ++229 ++255 ++248 ++253 ++255 ++252 ++250 ++254 ++255 ++252 ++251 ++248 ++253 ++255 ++248 ++253 ++249 ++242 ++226 ++254 ++237 ++229 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++237 ++229 ++255 ++245 ++233 ++253 ++255 ++252 ++251 ++249 ++242 ++255 ++220 ++206 ++252 ++211 ++207 ++253 ++239 ++236 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++252 ++250 ++254 ++252 ++255 ++251 ++252 ++255 ++251 ++252 ++250 ++254 ++252 ++250 ++254 ++248 ++253 ++255 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++255 ++252 ++251 ++248 ++253 ++255 ++252 ++250 ++254 ++252 ++250 ++254 ++255 ++252 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++255 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++255 ++252 ++251 ++248 ++253 ++255 ++255 ++252 ++251 ++248 ++253 ++255 ++255 ++252 ++251 ++252 ++255 ++251 ++255 ++252 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++248 ++253 ++255 ++252 ++255 ++251 ++248 ++253 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++252 ++255 ++251 ++248 ++253 ++249 ++255 ++252 ++251 ++255 ++252 ++251 ++248 ++253 ++255 ++255 ++252 ++251 ++252 ++250 ++254 ++248 ++253 ++255 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++255 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++255 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++248 ++253 ++255 ++248 ++253 ++255 ++248 ++253 ++255 ++252 ++250 ++254 ++252 ++250 ++254 ++248 ++253 ++255 ++248 ++253 ++255 ++248 ++253 ++255 ++255 ++252 ++251 ++248 ++253 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++248 ++253 ++255 ++248 ++253 ++255 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++248 ++253 ++255 ++252 ++255 ++251 ++252 ++255 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++250 ++254 ++255 ++252 ++251 ++248 ++253 ++249 ++252 ++255 ++251 ++248 ++253 ++255 ++255 ++252 ++251 ++252 ++250 ++254 ++252 ++250 ++254 ++248 ++253 ++249 ++248 ++253 ++255 ++255 ++252 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++255 ++252 ++251 ++252 ++255 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++255 ++251 ++252 ++255 ++251 ++255 ++252 ++251 ++252 ++250 ++254 ++252 ++255 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++248 ++253 ++255 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++255 ++252 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++252 ++250 ++254 ++252 ++250 ++254 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++252 ++250 ++254 ++248 ++253 ++255 ++230 ++227 ++225 ++248 ++253 ++255 ++234 ++239 ++242 ++201 ++189 ++179 ++238 ++247 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++207 ++202 ++200 ++252 ++250 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++230 ++227 ++225 ++219 ++225 ++231 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++252 ++250 ++254 ++250 ++242 ++234 ++182 ++177 ++176 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++252 ++250 ++254 ++255 ++252 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++243 ++245 ++242 ++234 ++239 ++242 ++255 ++252 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++248 ++253 ++255 ++255 ++252 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++234 ++226 ++218 ++211 ++217 ++219 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++243 ++245 ++242 ++254 ++255 ++252 ++254 ++255 ++252 ++240 ++235 ++233 ++230 ++227 ++225 ++234 ++239 ++242 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++250 ++242 ++234 ++205 ++213 ++222 ++255 ++252 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++223 ++214 ++206 ++234 ++239 ++242 ++252 ++250 ++254 ++197 ++193 ++191 ++254 ++255 ++252 ++252 ++250 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++210 ++205 ++197 ++248 ++253 ++255 ++255 ++252 ++251 ++232 ++233 ++243 ++243 ++245 ++242 ++252 ++250 ++254 ++252 ++255 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++250 ++254 ++255 ++252 ++251 ++250 ++242 ++234 ++205 ++213 ++222 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++248 ++253 ++255 ++252 ++250 ++254 ++252 ++250 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++255 ++252 ++251 ++252 ++250 ++254 ++252 ++250 ++254 ++252 ++250 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++248 ++253 ++255 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++101 ++81 ++79 ++254 ++255 ++252 ++93 ++90 ++106 ++223 ++214 ++206 ++248 ++253 ++255 ++182 ++177 ++176 ++234 ++239 ++242 ++133 ++131 ++123 ++191 ++195 ++199 ++248 ++253 ++255 ++248 ++253 ++255 ++114 ++98 ++88 ++133 ++131 ++123 ++133 ++153 ++169 ++223 ++214 ++206 ++205 ++213 ++222 ++250 ++242 ++234 ++211 ++217 ++219 ++127 ++119 ++113 ++168 ++191 ++209 ++223 ++214 ++206 ++191 ++206 ++219 ++250 ++242 ++234 ++217 ++211 ++210 ++219 ++225 ++231 ++191 ++195 ++199 ++234 ++226 ++218 ++205 ++213 ++222 ++234 ++226 ++218 ++191 ++195 ++199 ++254 ++255 ++252 ++217 ++211 ++210 ++191 ++195 ++199 ++254 ++255 ++252 ++197 ++193 ++191 ++205 ++213 ++222 ++223 ++214 ++206 ++197 ++217 ++223 ++254 ++255 ++252 ++218 ++199 ++188 ++133 ++153 ++169 ++254 ++255 ++252 ++223 ++214 ++206 ++191 ++206 ++219 ++234 ++226 ++218 ++248 ++253 ++255 ++219 ++225 ++231 ++230 ++227 ++225 ++248 ++253 ++255 ++233 ++220 ++201 ++71 ++78 ++85 ++135 ++121 ++116 ++230 ++244 ++251 ++182 ++177 ++176 ++238 ++247 ++255 ++234 ++226 ++218 ++200 ++207 ++211 ++99 ++93 ++91 ++191 ++206 ++219 ++254 ++255 ++252 ++131 ++111 ++91 ++110 ++114 ++118 ++211 ++217 ++219 ++217 ++211 ++210 ++200 ++207 ++211 ++207 ++202 ++200 ++253 ++243 ++227 ++109 ++128 ++145 ++191 ++195 ++199 ++254 ++255 ++252 ++197 ++193 ++191 ++238 ++247 ++255 ++233 ++220 ++201 ++127 ++119 ++113 ++214 ++226 ++253 ++210 ++205 ++197 ++83 ++94 ++106 ++254 ++255 ++252 ++191 ++195 ++199 ++248 ++253 ++255 ++223 ++214 ++206 ++116 ++95 ++90 ++219 ++245 ++255 ++241 ++216 ++191 ++103 ++132 ++168 ++233 ++200 ++174 ++127 ++173 ++205 ++218 ++199 ++188 ++205 ++213 ++222 ++250 ++242 ++234 ++211 ++217 ++219 ++243 ++245 ++242 ++165 ++156 ++151 ++144 ++145 ++154 ++219 ++225 ++231 ++234 ++226 ++218 ++255 ++252 ++251 ++211 ++217 ++219 ++201 ++189 ++179 ++219 ++225 ++231 ++250 ++242 ++234 ++211 ++217 ++219 ++243 ++245 ++242 ++191 ++195 ++199 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++128 ++106 ++98 ++136 ++138 ++135 ++116 ++128 ++152 ++175 ++164 ++146 ++140 ++125 ++114 ++191 ++206 ++219 ++114 ++126 ++132 ++152 ++151 ++143 ++190 ++169 ++150 ++144 ++172 ++189 ++252 ++250 ++254 ++143 ++119 ++115 ++136 ++138 ++135 ++163 ++169 ++165 ++99 ++101 ++107 ++110 ++114 ++118 ++175 ++164 ++146 ++149 ++165 ++177 ++135 ++121 ++116 ++201 ++189 ++179 ++123 ++140 ++148 ++159 ++140 ++125 ++158 ++152 ++139 ++133 ++153 ++169 ++168 ++130 ++120 ++182 ++180 ++166 ++116 ++128 ++152 ++122 ++122 ++119 ++210 ++205 ++197 ++114 ++111 ++108 ++166 ++173 ++180 ++136 ++125 ++125 ++117 ++106 ++105 ++174 ++167 ++156 ++149 ++165 ++177 ++201 ++189 ++179 ++99 ++101 ++107 ++99 ++101 ++107 ++241 ++254 ++255 ++218 ++199 ++188 ++144 ++172 ++189 ++253 ++243 ++227 ++104 ++107 ++127 ++165 ++156 ++151 ++152 ++151 ++143 ++144 ++145 ++154 ++83 ++94 ++106 ++114 ++111 ++108 ++252 ++250 ++254 ++189 ++172 ++142 ++171 ++197 ++224 ++248 ++253 ++255 ++157 ++123 ++106 ++197 ++217 ++223 ++114 ++111 ++108 ++117 ++106 ++105 ++166 ++173 ++180 ++114 ++111 ++108 ++219 ++225 ++231 ++248 ++253 ++255 ++140 ++125 ++114 ++142 ++155 ++162 ++240 ++235 ++233 ++119 ++121 ++124 ++114 ++111 ++108 ++175 ++164 ++146 ++149 ++165 ++177 ++142 ++155 ++162 ++158 ++152 ++139 ++135 ++121 ++116 ++123 ++140 ++148 ++133 ++131 ++123 ++96 ++109 ++136 ++152 ++151 ++143 ++174 ++167 ++156 ++135 ++154 ++178 ++122 ++124 ++136 ++146 ++125 ++108 ++152 ++151 ++143 ++122 ++124 ++136 ++130 ++146 ++146 ++146 ++125 ++108 ++232 ++249 ++255 ++253 ++243 ++227 ++86 ++88 ++91 ++117 ++106 ++105 ++171 ++197 ++224 ++174 ++167 ++156 ++86 ++88 ++91 ++182 ++180 ++166 ++135 ++154 ++178 ++117 ++106 ++105 ++210 ++205 ++197 ++152 ++156 ++171 ++122 ++122 ++119 ++116 ++95 ++90 ++149 ++143 ++139 ++167 ++182 ++195 ++149 ++143 ++139 ++96 ++107 ++119 ++165 ++156 ++151 ++167 ++182 ++195 ++101 ++81 ++79 ++133 ++131 ++123 ++176 ++200 ++211 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++114 ++98 ++88 ++254 ++255 ++252 ++104 ++107 ++127 ++175 ++164 ++146 ++210 ++205 ++197 ++119 ++121 ++124 ++114 ++126 ++132 ++136 ++138 ++135 ++233 ++220 ++201 ++128 ++158 ++189 ++248 ++253 ++255 ++99 ++93 ++91 ++248 ++253 ++255 ++248 ++253 ++255 ++117 ++106 ++105 ++142 ++155 ++162 ++174 ++157 ++146 ++204 ++224 ++243 ++146 ++125 ++108 ++227 ++239 ++254 ++110 ++114 ++118 ++110 ++114 ++118 ++190 ++169 ++150 ++204 ++224 ++243 ++168 ++130 ++120 ++230 ++228 ++206 ++128 ++158 ++189 ++158 ++152 ++139 ++140 ++125 ++114 ++133 ++131 ++123 ++167 ++182 ++195 ++144 ++145 ++154 ++162 ++139 ++130 ++217 ++211 ++210 ++122 ++124 ++136 ++142 ++155 ++162 ++135 ++121 ++116 ++143 ++146 ++145 ++248 ++253 ++255 ++223 ++214 ++206 ++86 ++88 ++91 ++123 ++140 ++148 ++136 ++125 ++125 ++99 ++101 ++107 ++248 ++253 ++249 ++83 ++74 ++80 ++216 ++201 ++179 ++103 ++132 ++168 ++254 ++255 ++252 ++250 ++242 ++234 ++99 ++93 ++91 ++119 ++121 ++124 ++201 ++189 ++179 ++110 ++114 ++118 ++142 ++155 ++162 ++165 ++156 ++151 ++96 ++107 ++119 ++158 ++152 ++139 ++135 ++154 ++178 ++254 ++255 ++252 ++146 ++125 ++108 ++119 ++121 ++124 ++211 ++217 ++219 ++142 ++155 ++162 ++136 ++125 ++125 ++230 ++228 ++206 ++144 ++172 ++189 ++110 ++114 ++118 ++96 ++107 ++119 ++216 ++201 ++179 ++122 ++124 ++136 ++182 ++177 ++176 ++122 ++122 ++119 ++99 ++93 ++91 ++217 ++211 ++210 ++99 ++101 ++107 ++96 ++107 ++119 ++201 ++189 ++179 ++130 ++146 ++146 ++166 ++173 ++180 ++127 ++119 ++113 ++99 ++93 ++91 ++219 ++245 ++255 ++250 ++233 ++208 ++103 ++132 ++168 ++233 ++200 ++174 ++144 ++172 ++189 ++99 ++101 ++107 ++110 ++114 ++118 ++190 ++169 ++150 ++195 ++216 ++245 ++175 ++152 ++137 ++114 ++111 ++108 ++144 ++172 ++189 ++174 ++139 ++122 ++176 ++200 ++211 ++83 ++74 ++80 ++230 ++228 ++206 ++96 ++107 ++119 ++110 ++114 ++118 ++165 ++156 ++151 ++230 ++244 ++251 ++159 ++140 ++125 ++144 ++145 ++154 ++200 ++207 ++211 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++234 ++226 ++218 ++136 ++125 ++125 ++176 ++200 ++211 ++252 ++250 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++250 ++254 ++255 ++252 ++251 ++255 ++252 ++251 ++248 ++253 ++255 ++255 ++252 ++251 ++248 ++253 ++255 ++248 ++253 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++248 ++253 ++255 ++254 ++255 ++252 ++248 ++253 ++255 ++248 ++253 ++255 ++252 ++250 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++252 ++250 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++248 ++253 ++255 ++248 ++253 ++255 ++248 ++253 ++255 ++252 ++255 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++252 ++250 ++254 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++250 ++254 ++248 ++253 ++255 ++248 ++253 ++255 ++255 ++252 ++251 ++248 ++253 ++255 ++248 ++253 ++255 ++255 ++252 ++251 ++252 ++250 ++254 ++255 ++252 ++251 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++248 ++253 ++255 ++255 ++252 ++251 ++255 ++252 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++248 ++253 ++255 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++255 ++252 ++251 ++252 ++250 ++254 ++252 ++250 ++254 ++248 ++253 ++255 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++255 ++252 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++252 ++255 ++251 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++255 ++252 ++251 ++255 ++252 ++251 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++250 ++254 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++255 ++251 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++255 ++252 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++248 ++253 ++255 ++254 ++255 ++252 ++255 ++252 ++251 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++252 ++250 ++254 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++248 ++253 ++255 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++255 ++252 ++251 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++255 ++252 ++251 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++252 ++250 ++254 ++248 ++253 ++255 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++252 ++250 ++254 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 ++254 ++255 ++252 +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/0004-920T-Use-specific-920t-mtune.patch b/recipes/linux/linux-2.6.29/micro2440/0004-920T-Use-specific-920t-mtune.patch new file mode 100644 index 0000000000..d6e2b4ddd5 --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0004-920T-Use-specific-920t-mtune.patch @@ -0,0 +1,28 @@ +From 95c835a4a2d6ff9c8073136d7673ddc3eba45dfa Mon Sep 17 00:00:00 2001 +From: Michel Pollet <buserror@gmail.com> +Date: Sat, 14 Mar 2009 10:35:26 +0000 +Subject: [PATCH] 920T: Use specific 920t mtune= + +Modern toolchains have an option for it, lets use it ? + +Signed-off-by: Michel Pollet <buserror@gmail.com> +--- + arch/arm/Makefile | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/Makefile b/arch/arm/Makefile +index 24e0f01..f47f9c9 100644 +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -68,7 +68,7 @@ tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi + tune-$(CONFIG_CPU_ARM9TDMI) :=-mtune=arm9tdmi + tune-$(CONFIG_CPU_ARM940T) :=-mtune=arm9tdmi + tune-$(CONFIG_CPU_ARM946E) :=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi) +-tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi ++tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm920t + tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi + tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi + tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/0005-920T-Temp-fix-for-the-40-relocation-binutils-pro.patch b/recipes/linux/linux-2.6.29/micro2440/0005-920T-Temp-fix-for-the-40-relocation-binutils-pro.patch new file mode 100644 index 0000000000..6b8aaf4445 --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0005-920T-Temp-fix-for-the-40-relocation-binutils-pro.patch @@ -0,0 +1,49 @@ +From a4cba996cb77da4afc26c35402a70c3f008afe96 Mon Sep 17 00:00:00 2001 +From: Michel Pollet <buserror@gmail.com> +Date: Sat, 14 Mar 2009 10:34:32 +0000 +Subject: [PATCH] 920T: Temp(?) fix for the 40 relocation binutils problem + +This prevents the modules failing to load when made +with modern toolchains. There is no way to prevent binutils +to generate these relocations, and on the 920t they are +in fact not needed. So this patch just skip them. + +Signed-off-by: Michel Pollet <buserror@gmail.com> +--- + arch/arm/include/asm/elf.h | 1 + + arch/arm/kernel/module.c | 7 +++++++ + 2 files changed, 8 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h +index a58378c..ce3b36e 100644 +--- a/arch/arm/include/asm/elf.h ++++ b/arch/arm/include/asm/elf.h +@@ -50,6 +50,7 @@ typedef struct user_fp elf_fpregset_t; + #define R_ARM_ABS32 2 + #define R_ARM_CALL 28 + #define R_ARM_JUMP24 29 ++#define R_ARM_V4BX 40 + + /* + * These are used to set parameters in the core dumps. +diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c +index dab48f2..fa03392 100644 +--- a/arch/arm/kernel/module.c ++++ b/arch/arm/kernel/module.c +@@ -132,6 +132,13 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, + *(u32 *)loc |= offset & 0x00ffffff; + break; + ++#ifdef CONFIG_CPU_ARM920T ++ /* modern toolchain generate V4BX for the modules, and there is no ++ * way to skip them being generated in the .ko, so in our case, we just ++ * can ignore them */ ++ case R_ARM_V4BX: /* Ignore these sections */ ++ break; ++#endif + default: + printk(KERN_ERR "%s: unknown relocation: %u\n", + module->name, ELF32_R_TYPE(rel->r_info)); +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/0006-S3C-Allow-the-machine-code-to-get-the-BBT-table-fro.patch b/recipes/linux/linux-2.6.29/micro2440/0006-S3C-Allow-the-machine-code-to-get-the-BBT-table-fro.patch new file mode 100644 index 0000000000..f5064622a5 --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0006-S3C-Allow-the-machine-code-to-get-the-BBT-table-fro.patch @@ -0,0 +1,49 @@ +From be7844e174757ecc8aae7eb0411a7a8801da3aa8 Mon Sep 17 00:00:00 2001 +From: Michel Pollet <buserror@gmail.com> +Date: Fri, 13 Mar 2009 18:16:48 +0000 +Subject: [PATCH] S3C: Allow the machine code to get the BBT table from NAND + +Added a flag to allow the machine code to tell the NAND +subsystem that it should try to pickup a BBT from the flash, +and also skip the NAND full scan at startup. +--- + arch/arm/plat-s3c/include/plat/nand.h | 4 +++- + drivers/mtd/nand/s3c2410.c | 7 +++++++ + 2 files changed, 10 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h +index f4dcd14..0bcd5d0 100644 +--- a/arch/arm/plat-s3c/include/plat/nand.h ++++ b/arch/arm/plat-s3c/include/plat/nand.h +@@ -22,7 +22,9 @@ + */ + + struct s3c2410_nand_set { +- unsigned int disable_ecc : 1; ++ unsigned int disable_ecc : 1, ++ /* openmoko u-boot can create BBT */ ++ flash_bbt : 1; + + int nr_chips; + int nr_partitions; +diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c +index 8e375d5..f813ca9 100644 +--- a/drivers/mtd/nand/s3c2410.c ++++ b/drivers/mtd/nand/s3c2410.c +@@ -757,6 +757,13 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, + + if (set->disable_ecc) + chip->ecc.mode = NAND_ECC_NONE; ++ ++ /* If you use u-boot BBT creation code, specifying this flag will ++ * let the kernel fish out the BBT from the NAND, and also skip the ++ * full NAND scan that can take 1/2s or so. Little things... */ ++ if (set->flash_bbt) ++ chip->options |= NAND_USE_FLASH_BBT|NAND_SKIP_BBTSCAN; ++ + } + + /* s3c2410_nand_update_chip +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/0007-MINI2440-Add-machine-support.patch b/recipes/linux/linux-2.6.29/micro2440/0007-MINI2440-Add-machine-support.patch new file mode 100644 index 0000000000..fd803dd405 --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0007-MINI2440-Add-machine-support.patch @@ -0,0 +1,793 @@ +From df4ff90ba57c3a4d2c52e9cb6fb808f682b0a87c Mon Sep 17 00:00:00 2001 +From: Michel Pollet <buserror@gmail.com> +Date: Wed, 25 Mar 2009 17:19:14 +0000 +Subject: [PATCH] MINI2440: Add machine support + +The MINI2440 is a chinese made s3c2440 develpment board with +a large set of peripherals. +This patch provides machine support for almost all the features +of the board. + +Since it can come with various "options" fitted, a kernel parameter +is used to specify the lcd size, backlight control and touchscreen. + +Signed-off-by: Michel Pollet <buserror@gmail.com> +--- + arch/arm/mach-s3c2440/Kconfig | 10 + + arch/arm/mach-s3c2440/Makefile | 1 + + arch/arm/mach-s3c2440/mach-mini2440.c | 734 +++++++++++++++++++++++++++++++++ + 3 files changed, 745 insertions(+), 0 deletions(-) + create mode 100644 arch/arm/mach-s3c2440/mach-mini2440.c + +diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig +index cde5ae9..7953c22 100644 +--- a/arch/arm/mach-s3c2440/Kconfig ++++ b/arch/arm/mach-s3c2440/Kconfig +@@ -79,5 +79,15 @@ config MACH_AT2440EVB + help + Say Y here if you are using the AT2440EVB development board + ++config MACH_MINI2440 ++ bool "MINI2440 development board" ++ select CPU_S3C2440 ++ select EEPROM_AT24 ++ select BACKLIGHT_PWM ++ select SND_S3C24XX_SOC_S3C24XX_UDA134X ++ help ++ Say Y here to select support for the MINI2440. Is a 10cm x 10cm board ++ available via various sources. It can come with a 3.5" or 7" touch LCD. ++ + endmenu + +diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile +index 0b4440e..bfadcf6 100644 +--- a/arch/arm/mach-s3c2440/Makefile ++++ b/arch/arm/mach-s3c2440/Makefile +@@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o + obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o + obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o + obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o ++obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o +diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c +new file mode 100644 +index 0000000..0cddb11 +--- /dev/null ++++ b/arch/arm/mach-s3c2440/mach-mini2440.c +@@ -0,0 +1,734 @@ ++/* linux/arch/arm/mach-s3c2440/mach-mini2440.c ++ * ++ * Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com> ++ * Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk> ++ * and modifications by SBZ <sbz@spgui.org> and ++ * Weibing <http://weibing.blogbus.com> ++ * Michel Pollet <buserror@gmail.com> ++ * ++ * For product information, visit http://code.google.com/p/mini2440/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/interrupt.h> ++#include <linux/list.h> ++#include <linux/timer.h> ++#include <linux/init.h> ++#include <linux/input.h> ++#include <linux/io.h> ++#include <linux/serial_core.h> ++#include <linux/dm9000.h> ++#include <linux/i2c/at24.h> ++#include <linux/platform_device.h> ++#include <linux/gpio_keys.h> ++#include <linux/i2c.h> ++#include <linux/mmc/host.h> ++#include <linux/pwm_backlight.h> ++ ++#include <asm/mach/arch.h> ++#include <asm/mach/map.h> ++ ++#include <mach/hardware.h> ++#include <mach/fb.h> ++#include <asm/mach-types.h> ++ ++#include <plat/regs-serial.h> ++#include <mach/regs-gpio.h> ++#include <mach/leds-gpio.h> ++#include <mach/regs-mem.h> ++#include <mach/regs-lcd.h> ++#include <mach/irqs.h> ++#include <plat/nand.h> ++#include <plat/iic.h> ++#include <plat/mci.h> ++#include <plat/udc.h> ++ ++#include <plat/regs-serial.h> ++#include <mach/regs-gpio.h> ++#include <mach/regs-mem.h> ++#include <mach/regs-lcd.h> ++ ++#include <linux/mtd/mtd.h> ++#include <linux/mtd/nand.h> ++#include <linux/mtd/nand_ecc.h> ++#include <linux/mtd/partitions.h> ++ ++#include <plat/clock.h> ++#include <plat/devs.h> ++#include <plat/cpu.h> ++ ++#include <sound/s3c24xx_uda134x.h> ++ ++#define MACH_MINI2440_DM9K_BASE (S3C2410_CS4 + 0x300) ++ ++static struct map_desc mini2440_iodesc[] __initdata = { ++ /* nothing to declare, move along */ ++}; ++ ++#define UCON S3C2410_UCON_DEFAULT ++#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB ++#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE ++ ++ ++static struct s3c2410_uartcfg mini2440_uartcfgs[] __initdata = { ++ [0] = { ++ .hwport = 0, ++ .flags = 0, ++ .ucon = UCON, ++ .ulcon = ULCON, ++ .ufcon = UFCON, ++ }, ++ [1] = { ++ .hwport = 1, ++ .flags = 0, ++ .ucon = UCON, ++ .ulcon = ULCON, ++ .ufcon = UFCON, ++ }, ++ [2] = { ++ .hwport = 2, ++ .flags = 0, ++ .ucon = UCON, ++ .ulcon = ULCON, ++ .ufcon = UFCON, ++ }, ++}; ++ ++/* USB device UDC support */ ++ ++static void mini2440_udc_pullup(enum s3c2410_udc_cmd_e cmd) ++{ ++ printk(KERN_DEBUG "udc: pullup(%d)\n",cmd); ++ ++ switch (cmd) { ++ case S3C2410_UDC_P_ENABLE : ++ s3c2410_gpio_setpin(S3C2410_GPC5, 1); ++ break; ++ case S3C2410_UDC_P_DISABLE : ++ s3c2410_gpio_setpin(S3C2410_GPC5, 0); ++ break; ++ case S3C2410_UDC_P_RESET : ++ break; ++ default: ++ break; ++ } ++} ++ ++static struct s3c2410_udc_mach_info mini2440_udc_cfg __initdata = { ++ .udc_command = mini2440_udc_pullup, ++}; ++ ++ ++/* LCD timing and setup */ ++ ++/* ++ * This macro simplifies the table bellow ++ */ ++#define _LCD_DECLARE(_xres,margin_left,margin_right,hsync, \ ++ _yres,margin_top,margin_bottom,vsync, refresh) \ ++ .width = _xres, \ ++ .xres = _xres, \ ++ .height = _yres, \ ++ .yres = _yres, \ ++ .left_margin = margin_left, \ ++ .right_margin = margin_right, \ ++ .upper_margin = margin_top, \ ++ .lower_margin = margin_bottom, \ ++ .hsync_len = hsync, \ ++ .vsync_len = vsync, \ ++ .pixclock = (1000000000000LL / \ ++ ((refresh) * \ ++ (hsync + margin_left + _xres + margin_right) * \ ++ (vsync + margin_top + _yres + margin_bottom))), \ ++ .bpp = 16,\ ++ .type = (S3C2410_LCDCON1_TFT16BPP |\ ++ S3C2410_LCDCON1_TFT), ++ ++struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = { ++ [0] = { // mini2440 + 3.5" TFT + touchscreen ++ _LCD_DECLARE( ++ 240, 21, 38, 6, /* x timing */ ++ 320, 2, 6, 2, /* y timing */ ++ 60) /* refresh rate */ ++ .lcdcon5 = (S3C2410_LCDCON5_FRM565 |\ ++ S3C2410_LCDCON5_INVVLINE |\ ++ S3C2410_LCDCON5_INVVFRAME |\ ++ S3C2410_LCDCON5_INVVDEN |\ ++ S3C2410_LCDCON5_PWREN), ++ }, ++ [1] = { // mini2440 + 7" TFT + touchscreen ++ _LCD_DECLARE( ++ 800, 40, 40, 48, /* x timing */ ++ 480, 29, 3, 3, /* y timing */ ++ 50) /* refresh rate */ ++ .lcdcon5 = (S3C2410_LCDCON5_FRM565 |\ ++ S3C2410_LCDCON5_INVVLINE |\ ++ S3C2410_LCDCON5_INVVFRAME |\ ++ S3C2410_LCDCON5_PWREN), ++ }, ++ /* VGA all share the timings ++ * NOTE: The VGA board seems to always output at 1024x768 ++ * unless you add the dip-switch block. The smaller resolution ++ * WILL work, but be displayed in the top/left corner on the VGA screen ++ */ ++ [2] = { ++ _LCD_DECLARE( ++ 1024, 1, 2, 2, /* y timing */ ++ 768, 200, 16, 16, /* x timing */ ++ 24) /* refresh rate, maximum stable, ++ tested with the FPGA shield */ ++ .lcdcon5 = (S3C2410_LCDCON5_FRM565 |\ ++ S3C2410_LCDCON5_HWSWP), ++ }, ++}; ++ ++/* todo - put into gpio header */ ++ ++#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2)) ++#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2)) ++ ++struct s3c2410fb_mach_info mini2440_fb_info __initdata = { ++ .displays = &mini2440_lcd_cfg[0], /* not constant! see init */ ++ .num_displays = 1, ++ .default_display = 0, ++ ++ /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN ++ * and disable the pull down resistors on pins we are using for LCD ++ * data. */ ++ ++ .gpcup = (0xf << 1) | (0x3f << 10), ++ ++ .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE | ++ S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM | ++ S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 | ++ S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 | ++ S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7), ++ ++ .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) | ++ S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) | ++ S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) | ++ S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) | ++ S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)), ++ ++ .gpdup = (0x3f << 2) | (0x3f << 10), ++ ++ .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 | ++ S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 | ++ S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 | ++ S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 | ++ S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 | ++ S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23), ++ ++ .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) | ++ S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) | ++ S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) | ++ S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)| ++ S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)| ++ S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)), ++}; ++ ++/* MMC/SD */ ++ ++static struct s3c24xx_mci_pdata mini2440_mmc_cfg __initdata = { ++ .gpio_detect = S3C2410_GPG8, ++ .gpio_wprotect = S3C2410_GPH8, ++ .set_power = NULL, ++ .ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34, ++}; ++ ++/* NAND Flash on MINI2440 board */ ++ ++static struct mtd_partition mini2440_default_nand_part[] __initdata = { ++ [0] = { ++ .name = "u-boot", ++ .size = SZ_256K, ++ .offset = 0, ++ }, ++ [1] = { ++ .name = "u-boot-env", ++ .size = SZ_128K, ++ .offset = SZ_256K, ++ }, ++ [2] = { ++ .name = "kernel", ++ /* 5 megabytes, for a kernel with no modules ++ * or a uImage with a ramdisk attached */ ++ .size = 0x00500000, ++ .offset = SZ_256K + SZ_128K, ++ }, ++ [3] = { ++ .name = "root", ++ .offset = SZ_256K + SZ_128K + 0x00500000, ++ .size = MTDPART_SIZ_FULL, ++ }, ++}; ++ ++static struct s3c2410_nand_set mini2440_nand_sets[] __initdata = { ++ [0] = { ++ .name = "nand", ++ .nr_chips = 1, ++ .nr_partitions = ARRAY_SIZE(mini2440_default_nand_part), ++ .partitions = mini2440_default_nand_part, ++ .flash_bbt = 1, /* we use u-boot to create a BBT */ ++ }, ++}; ++ ++static struct s3c2410_platform_nand mini2440_nand_info __initdata = { ++ .tacls = 0, ++ .twrph0 = 25, ++ .twrph1 = 15, ++ .nr_sets = ARRAY_SIZE(mini2440_nand_sets), ++ .sets = mini2440_nand_sets, ++ .ignore_unset_ecc = 1, ++}; ++ ++/* DM9000AEP 10/100 ethernet controller */ ++ ++static struct resource mini2440_dm9k_resource[] __initdata = { ++ [0] = { ++ .start = MACH_MINI2440_DM9K_BASE, ++ .end = MACH_MINI2440_DM9K_BASE + 3, ++ .flags = IORESOURCE_MEM ++ }, ++ [1] = { ++ .start = MACH_MINI2440_DM9K_BASE + 4, ++ .end = MACH_MINI2440_DM9K_BASE + 7, ++ .flags = IORESOURCE_MEM ++ }, ++ [2] = { ++ .start = IRQ_EINT7, ++ .end = IRQ_EINT7, ++ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, ++ } ++}; ++ ++static struct dm9000_plat_data mini2440_dm9k_pdata __initdata = { ++ .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), ++}; ++ ++static struct platform_device mini2440_device_eth __initdata = { ++ .name = "dm9000", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(mini2440_dm9k_resource), ++ .resource = mini2440_dm9k_resource, ++ .dev = { ++ .platform_data = &mini2440_dm9k_pdata, ++ }, ++}; ++ ++/* backlight */ ++ ++static int mini2440_backlight_init(struct device *dev) ++{ ++ return 0; ++} ++/* ++ * Cut the power to the LCD if brightness reaches 0 ++ */ ++static int mini2440_backlight_notify(int brightness) ++{ ++ if (brightness) { ++ s3c2410_gpio_setpin(S3C2410_GPB1, 1); ++ s3c2410_gpio_cfgpin(S3C2410_GPB1, S3C2410_GPB1_TOUT1); ++ s3c2410_gpio_setpin(S3C2410_GPG4, 1); ++ s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_LCDPWREN); ++ } else { ++ s3c2410_gpio_setpin(S3C2410_GPB1, 0); ++ s3c2410_gpio_cfgpin(S3C2410_GPB1, S3C2410_GPB1_OUTP); ++ s3c2410_gpio_setpin(S3C2410_GPG4, 0); ++ s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_OUTP); ++ } ++ return brightness; ++} ++ ++static struct platform_pwm_backlight_data mini2440_backlight_data __initdata = { ++ .pwm_id = 1, ++ .max_brightness = 1023, ++ .dft_brightness = 900, ++ .pwm_period_ns = 4000000, /* Fl = 250Hz PWM */ ++ .init = mini2440_backlight_init, ++ .notify = mini2440_backlight_notify, ++}; ++ ++static struct platform_device mini2440_backlight_device __initdata = { ++ .name = "pwm-backlight", ++ .dev = { ++ .platform_data = &mini2440_backlight_data, ++ }, ++}; ++ ++/* CON5 ++ * +--+ /-----\ ++ * | | | | ++ * | | | BAT | ++ * | | \_____/ ++ * | | ++ * | | +----+ +----+ ++ * | | | K5 | | K1 | ++ * | | +----+ +----+ ++ * | | +----+ +----+ ++ * | | | K4 | | K2 | ++ * | | +----+ +----+ ++ * | | +----+ +----+ ++ * | | | K6 | | K3 | ++ * | | +----+ +----+ ++ * ..... ++ */ ++static struct gpio_keys_button mini2440_buttons[] __initdata = { ++ { ++ .gpio = S3C2410_GPG0, /* K1 */ ++ .code = KEY_F1, ++ .desc = "Button 1", ++ .active_low = 1, ++ }, ++ { ++ .gpio = S3C2410_GPG3, /* K2 */ ++ .code = KEY_F2, ++ .desc = "Button 2", ++ .active_low = 1, ++ }, ++ { ++ .gpio = S3C2410_GPG5, /* K3 */ ++ .code = KEY_F3, ++ .desc = "Button 3", ++ .active_low = 1, ++ }, ++ { ++ .gpio = S3C2410_GPG6, /* K4 */ ++ .code = KEY_POWER, ++ .desc = "Power", ++ .active_low = 1, ++ }, ++ { ++ .gpio = S3C2410_GPG7, /* K5 */ ++ .code = KEY_F5, ++ .desc = "Button 5", ++ .active_low = 1, ++ }, ++#if 0 ++ /* this pin is also known as TCLK1 and seems to already ++ * marked as "in use" somehow in the kernel -- possibly wrongly */ ++ { ++ .gpio = S3C2410_GPG11, /* K6 */ ++ .code = KEY_F6, ++ .desc = "Button 6", ++ .active_low = 1, ++ }, ++#endif ++}; ++ ++static struct gpio_keys_platform_data mini2440_button_data __initdata = { ++ .buttons = mini2440_buttons, ++ .nbuttons = ARRAY_SIZE(mini2440_buttons), ++}; ++ ++static struct platform_device mini2440_button_device __initdata = { ++ .name = "gpio-keys", ++ .id = -1, ++ .dev = { ++ .platform_data = &mini2440_button_data, ++ } ++}; ++ ++/* LEDS */ ++ ++static struct s3c24xx_led_platdata mini2440_led1_pdata __initdata = { ++ .name = "led1", ++ .gpio = S3C2410_GPB5, ++ .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, ++ .def_trigger = "heartbeat", ++}; ++ ++static struct s3c24xx_led_platdata mini2440_led2_pdata __initdata = { ++ .name = "led2", ++ .gpio = S3C2410_GPB6, ++ .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, ++ .def_trigger = "nand-disk", ++}; ++ ++static struct s3c24xx_led_platdata mini2440_led3_pdata __initdata = { ++ .name = "led3", ++ .gpio = S3C2410_GPB7, ++ .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, ++ .def_trigger = "mmc0", ++}; ++ ++static struct s3c24xx_led_platdata mini2440_led4_pdata __initdata = { ++ .name = "led4", ++ .gpio = S3C2410_GPB8, ++ .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, ++ .def_trigger = "", ++}; ++ ++static struct platform_device mini2440_led1 __initdata = { ++ .name = "s3c24xx_led", ++ .id = 1, ++ .dev = { ++ .platform_data = &mini2440_led1_pdata, ++ }, ++}; ++ ++static struct platform_device mini2440_led2 __initdata = { ++ .name = "s3c24xx_led", ++ .id = 2, ++ .dev = { ++ .platform_data = &mini2440_led2_pdata, ++ }, ++}; ++ ++static struct platform_device mini2440_led3 __initdata = { ++ .name = "s3c24xx_led", ++ .id = 3, ++ .dev = { ++ .platform_data = &mini2440_led3_pdata, ++ }, ++}; ++ ++static struct platform_device mini2440_led4 __initdata = { ++ .name = "s3c24xx_led", ++ .id = 4, ++ .dev = { ++ .platform_data = &mini2440_led4_pdata, ++ }, ++}; ++ ++/* AUDIO */ ++ ++static struct s3c24xx_uda134x_platform_data mini2440_audio_pins __initdata = { ++ .l3_clk = S3C2410_GPB4, ++ .l3_mode = S3C2410_GPB2, ++ .l3_data = S3C2410_GPB3, ++ .model = UDA134X_UDA1341 ++}; ++ ++static struct platform_device mini2440_audio __initdata = { ++ .name = "s3c24xx_uda134x", ++ .id = 0, ++ .dev = { ++ .platform_data = &mini2440_audio_pins, ++ }, ++}; ++ ++/* ++ * I2C devices ++ */ ++static struct at24_platform_data at24c08 = { ++ .byte_len = SZ_8K / 8, ++ .page_size = 16, ++}; ++ ++static struct i2c_board_info mini2440_i2c_devs[] __initdata = { ++ { ++ I2C_BOARD_INFO("24c08", 0x50), ++ .platform_data = &at24c08, ++ }, ++}; ++ ++/* We can run that eeprom at 400khz */ ++static struct s3c2410_platform_i2c mini2440_i2c_info __initdata = { ++ .flags = 0, ++ .slave_addr = 0x10, ++ .bus_freq = 400*1000, ++ .max_freq = 400*1000, ++}; ++ ++ ++static struct platform_device *mini2440_devices[] __initdata = { ++ &s3c_device_usb, ++ &s3c_device_wdt, ++/* &s3c_device_adc,*/ /* ADC doesn't like living with touchscreen ! */ ++ &s3c_device_i2c0, ++ &s3c_device_rtc, ++ &s3c_device_usbgadget, ++ &mini2440_device_eth, ++ &mini2440_led1, ++ &mini2440_led2, ++ &mini2440_led3, ++ &mini2440_led4, ++ &mini2440_button_device, ++ &s3c_device_nand, ++ &s3c_device_sdi, ++ &s3c_device_iis, ++ &mini2440_audio, ++/* &s3c_device_timer[0],*/ /* buzzer pwm, no API for it */ ++ /* remaining devices are optional */ ++}; ++ ++static void __init mini2440_map_io(void) ++{ ++ s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); ++ s3c24xx_init_clocks(12000000); ++ s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); ++ ++ s3c_device_nand.dev.platform_data = &mini2440_nand_info; ++ s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg; ++} ++ ++/* ++ * mini2440_features string ++ * ++ * t = Touchscreen present ++ * b = PWM backlight control ++ * c = camera [TODO] ++ * 0-9 LCD configuration ++ * ++ */ ++static char mini2440_features_str[12] __initdata = "0tb"; ++ ++static int __init mini2440_features_setup(char *str) ++{ ++ if (str) ++ strlcpy(mini2440_features_str, str, sizeof(mini2440_features_str)); ++ return 1; ++} ++ ++__setup("mini2440=", mini2440_features_setup); ++ ++#define FEATURE_SCREEN (1 << 0) ++#define FEATURE_BACKLIGHT (1 << 1) ++#define FEATURE_TOUCH (1 << 2) ++#define FEATURE_CAMERA (1 << 3) ++ ++struct mini2440_features_t { ++ int count; ++ int done; ++ int lcd_index; ++ struct platform_device *optional[8]; ++}; ++ ++static void mini2440_parse_features( ++ struct mini2440_features_t * features, ++ const char * features_str ) ++{ ++ const char * fp = features_str; ++ ++ features->count = 0; ++ features->done = 0; ++ features->lcd_index = -1; ++ ++ while (*fp) { ++ char f = *fp++; ++ ++ switch (f) { ++ case '0'...'9': /* tft screen */ ++ if (features->done & FEATURE_SCREEN) { ++ printk(KERN_INFO "MINI2440: '%c' ignored, " ++ "screen type already set\n", f); ++ } else { ++ int li = f - '0'; ++ if (li >= ARRAY_SIZE(mini2440_lcd_cfg)) ++ printk(KERN_INFO "MINI2440: " ++ "'%c' out of range LCD mode\n", f); ++ else { ++ features->optional[features->count++] = ++ &s3c_device_lcd; ++ features->lcd_index = li; ++ } ++ } ++ features->done |= FEATURE_SCREEN; ++ break; ++ case 'b': ++ if (features->done & FEATURE_BACKLIGHT) ++ printk(KERN_INFO "MINI2440: '%c' ignored, " ++ "backlight already set\n", f); ++ else { ++ /* need this timer for the backlight */ ++ features->optional[features->count++] = ++ &s3c_device_timer[1]; ++ features->optional[features->count++] = ++ &mini2440_backlight_device; ++ } ++ features->done |= FEATURE_BACKLIGHT; ++ break; ++ case 't': ++ printk(KERN_INFO "MINI2440: '%c' ignored, " ++ "touchscreen not compiled in\n", f); ++ break; ++ case 'c': ++ if (features->done & FEATURE_CAMERA) ++ printk(KERN_INFO "MINI2440: '%c' ignored, " ++ "camera already registered\n", f); ++ else ++ features->optional[features->count++] = ++ &s3c_device_camif; ++ features->done |= FEATURE_CAMERA; ++ break; ++ } ++ } ++} ++ ++static void __init mini2440_init(void) ++{ ++ struct mini2440_features_t features = { 0 }; ++ int i; ++ ++ printk(KERN_INFO "MINI2440: Option string mini2440=%s\n", ++ mini2440_features_str); ++ ++ /* Parse the feature string */ ++ mini2440_parse_features(&features, mini2440_features_str); ++ ++ /* turn LCD on */ ++ s3c2410_gpio_cfgpin(S3C2410_GPC0, S3C2410_GPC0_LEND); ++ ++ /* remove pullup on PWM backlight */ ++ s3c2410_gpio_pullup(S3C2410_GPB1, 0); ++ s3c2410_gpio_setpin(S3C2410_GPB1, 0); ++ s3c2410_gpio_cfgpin(S3C2410_GPB1, S3C2410_GPB1_TOUT1); ++ ++ /* Make sure the D+ pullup pin is output */ ++ s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT); ++ ++ /* mark the key as inout, without pullups (there is one on the board) */ ++ for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) { ++ s3c2410_gpio_pullup(mini2440_buttons[i].gpio, 0); ++ s3c2410_gpio_cfgpin(mini2440_buttons[i].gpio, ++ S3C2410_GPIO_INPUT); ++ } ++ if (features.lcd_index != -1) { ++ int li; ++ ++ mini2440_fb_info.displays = ++ &mini2440_lcd_cfg[features.lcd_index]; ++ ++ printk(KERN_INFO "MINI2440: LCD"); ++ for (li = 0; li < ARRAY_SIZE(mini2440_lcd_cfg); li++) ++ if (li == features.lcd_index) ++ printk(" [%d:%dx%d]", li, ++ mini2440_lcd_cfg[li].width, ++ mini2440_lcd_cfg[li].height); ++ else ++ printk(" %d:%dx%d", li, ++ mini2440_lcd_cfg[li].width, ++ mini2440_lcd_cfg[li].height); ++ printk("\n"); ++ s3c24xx_fb_set_platdata(&mini2440_fb_info); ++ } ++ s3c24xx_udc_set_platdata(&mini2440_udc_cfg); ++ s3c_i2c0_set_platdata(&mini2440_i2c_info); ++ i2c_register_board_info(0, mini2440_i2c_devs, ++ ARRAY_SIZE(mini2440_i2c_devs)); ++ ++ platform_add_devices(mini2440_devices, ARRAY_SIZE(mini2440_devices)); ++ ++ if (features.count) /* the optional features */ ++ platform_add_devices(features.optional, features.count); ++ ++} ++ ++ ++MACHINE_START(MINI2440, "MINI2440") ++ /* Maintainer: Michel Pollet <buserror@gmail.com> */ ++ .phys_io = S3C2410_PA_UART, ++ .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, ++ .boot_params = S3C2410_SDRAM_PA + 0x100, ++ .map_io = mini2440_map_io, ++ .init_machine = mini2440_init, ++ .init_irq = s3c24xx_init_irq, ++ .timer = &s3c24xx_timer, ++MACHINE_END +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/0008-MINI2440-Delays-command-check-response-on-SD.patch b/recipes/linux/linux-2.6.29/micro2440/0008-MINI2440-Delays-command-check-response-on-SD.patch new file mode 100644 index 0000000000..94b192568d --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0008-MINI2440-Delays-command-check-response-on-SD.patch @@ -0,0 +1,30 @@ +From 94e4986b61d385491a89b5c287cebd54428df399 Mon Sep 17 00:00:00 2001 +From: Michel Pollet <buserror@gmail.com> +Date: Sat, 14 Mar 2009 10:37:57 +0000 +Subject: [PATCH] MINI2440: Delays command check response on SD + +The mini2440 faidl to initializes the SD cards reliably +without this small delay. +--- + drivers/mmc/core/sd.c | 5 +++++ + 1 files changed, 5 insertions(+), 0 deletions(-) + +diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c +index 26fc098..2449230 100644 +--- a/drivers/mmc/core/sd.c ++++ b/drivers/mmc/core/sd.c +@@ -449,6 +449,11 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr, + if (err < 0) + goto free_card; + ++#ifdef CONFIG_MACH_MINI2440 ++ /* Prevents the -110 error at startup/insertion */ ++ mdelay(10); ++#endif ++ + /* + * Fetch switch information from card. + */ +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/0009-MINI2440-Rename-the-SoC-tty-names.patch b/recipes/linux/linux-2.6.29/micro2440/0009-MINI2440-Rename-the-SoC-tty-names.patch new file mode 100644 index 0000000000..9e9f6067cd --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0009-MINI2440-Rename-the-SoC-tty-names.patch @@ -0,0 +1,35 @@ +From 356642f304af65f33a3ae756eff93bc91974ccce Mon Sep 17 00:00:00 2001 +From: Michel Pollet <buserror@gmail.com> +Date: Sat, 14 Mar 2009 10:39:49 +0000 +Subject: [PATCH] MINI2440: Rename the SoC tty names. + +The 24c2410 default serial ports are created with non- +standard names, that confuses most embedded distros and +is also inconsistent with the internal name used for the +console= parameter. This patch makes the driver use +the standardized names. +--- + drivers/serial/samsung.c | 6 ++++++ + 1 files changed, 6 insertions(+), 0 deletions(-) + +diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c +index 41ac948..e85a6db 100644 +--- a/drivers/serial/samsung.c ++++ b/drivers/serial/samsung.c +@@ -823,7 +823,13 @@ static struct uart_ops s3c24xx_serial_ops = { + + static struct uart_driver s3c24xx_uart_drv = { + .owner = THIS_MODULE, ++#ifdef CONFIG_MACH_MINI2440 ++ /* this was probably meant to be there in the first place, since the #define exists ++ * having non-standard names like "s3c2410_serial" is a royal pain for every distro */ ++ .dev_name = S3C24XX_SERIAL_NAME, ++#else + .dev_name = "s3c2410_serial", ++#endif + .nr = CONFIG_SERIAL_SAMSUNG_UARTS, + .cons = S3C24XX_SERIAL_CONSOLE, + .driver_name = S3C24XX_SERIAL_NAME, +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/0010-MINI2440-creates-a-mini2440_defconfig-file.patch b/recipes/linux/linux-2.6.29/micro2440/0010-MINI2440-creates-a-mini2440_defconfig-file.patch new file mode 100644 index 0000000000..1470baabda --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0010-MINI2440-creates-a-mini2440_defconfig-file.patch @@ -0,0 +1,2067 @@ +From eaff38986d77d4e5447a88dc2899eacb029472d2 Mon Sep 17 00:00:00 2001 +From: Michel Pollet <buserror@gmail.com> +Date: Wed, 25 Mar 2009 17:24:08 +0000 +Subject: [PATCH] MINI2440: creates a mini2440_defconfig file + +Just a working, starting point config file for the board. + +Signed-off-by: Michel Pollet <buserror@gmail.com> +--- + arch/arm/configs/mini2440_defconfig | 2045 +++++++++++++++++++++++++++++++++++ + 1 files changed, 2045 insertions(+), 0 deletions(-) + create mode 100644 arch/arm/configs/mini2440_defconfig + +diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig +new file mode 100644 +index 0000000..1602aca +--- /dev/null ++++ b/arch/arm/configs/mini2440_defconfig +@@ -0,0 +1,2045 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Wed Mar 25 17:21:37 2009 ++# ++CONFIG_ARM=y ++CONFIG_HAVE_PWM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_GROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++# CONFIG_SYSFS_DEPRECATED_V2 is not set ++CONFIG_RELAY=y ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++# CONFIG_NET_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_ALL is not set ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_COMPAT_BRK is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++CONFIG_BLK_DEV_INTEGRITY=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++CONFIG_DEFAULT_AS=y ++# CONFIG_DEFAULT_DEADLINE is not set ++# CONFIG_DEFAULT_CFQ is not set ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="anticipatory" ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++CONFIG_ARCH_S3C2410=y ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_W90X900 is not set ++CONFIG_PLAT_S3C24XX=y ++CONFIG_S3C2410_CLOCK=y ++CONFIG_CPU_S3C244X=y ++CONFIG_S3C24XX_PWM=y ++CONFIG_S3C24XX_GPIO_EXTRA=0 ++CONFIG_S3C2410_DMA=y ++# CONFIG_S3C2410_DMA_DEBUG is not set ++CONFIG_S3C24XX_ADC=y ++CONFIG_PLAT_S3C=y ++CONFIG_CPU_LLSERIAL_S3C2440_ONLY=y ++CONFIG_CPU_LLSERIAL_S3C2440=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++# CONFIG_S3C_BOOT_ERROR_RESET is not set ++CONFIG_S3C_BOOT_UART_FORCE_FIFO=y ++ ++# ++# Power management ++# ++# CONFIG_S3C2410_PM_DEBUG is not set ++# CONFIG_S3C2410_PM_CHECK is not set ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_S3C_GPIO_SPACE=0 ++ ++# ++# S3C2400 Machines ++# ++CONFIG_S3C2410_PM=y ++CONFIG_S3C2410_GPIO=y ++ ++# ++# S3C2410 Machines ++# ++# CONFIG_ARCH_SMDK2410 is not set ++# CONFIG_ARCH_H1940 is not set ++# CONFIG_MACH_N30 is not set ++# CONFIG_ARCH_BAST is not set ++# CONFIG_MACH_OTOM is not set ++# CONFIG_MACH_AML_M5900 is not set ++# CONFIG_MACH_TCT_HAMMER is not set ++# CONFIG_MACH_VR1000 is not set ++# CONFIG_MACH_QT2410 is not set ++ ++# ++# S3C2412 Machines ++# ++# CONFIG_MACH_JIVE is not set ++# CONFIG_MACH_SMDK2413 is not set ++# CONFIG_MACH_SMDK2412 is not set ++# CONFIG_MACH_VSTMS is not set ++CONFIG_CPU_S3C2440=y ++CONFIG_S3C2440_DMA=y ++ ++# ++# S3C2440 Machines ++# ++# CONFIG_MACH_ANUBIS is not set ++# CONFIG_MACH_OSIRIS is not set ++# CONFIG_MACH_RX3715 is not set ++# CONFIG_ARCH_S3C2440 is not set ++# CONFIG_MACH_NEXCODER_2440 is not set ++# CONFIG_MACH_AT2440EVB is not set ++CONFIG_MACH_MINI2440=y ++ ++# ++# S3C2442 Machines ++# ++ ++# ++# S3C2443 Machines ++# ++# CONFIG_MACH_SMDK2443 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_ARM920T=y ++CONFIG_CPU_32v4T=y ++CONFIG_CPU_ABRT_EV4T=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V4WT=y ++CONFIG_CPU_CACHE_VIVT=y ++CONFIG_CPU_COPY_V4WB=y ++CONFIG_CPU_TLB_V4WBI=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_WRITETHROUGH is not set ++# CONFIG_OUTER_CACHE is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4096 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++CONFIG_KEXEC=y ++CONFIG_ATAGS_PROC=y ++ ++# ++# CPU Power Management ++# ++CONFIG_CPU_IDLE=y ++CONFIG_CPU_IDLE_GOV_LADDER=y ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++CONFIG_BINFMT_AOUT=m ++CONFIG_BINFMT_MISC=m ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++CONFIG_APM_EMULATION=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++CONFIG_XFRM_USER=m ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=m ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++CONFIG_IP_MROUTE=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++# CONFIG_ARPD is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=m ++CONFIG_INET_TCP_DIAG=m ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++CONFIG_NETFILTER=y ++# CONFIG_NETFILTER_DEBUG is not set ++CONFIG_NETFILTER_ADVANCED=y ++CONFIG_BRIDGE_NETFILTER=y ++ ++# ++# Core Netfilter Configuration ++# ++# CONFIG_NETFILTER_NETLINK_QUEUE is not set ++# CONFIG_NETFILTER_NETLINK_LOG is not set ++# CONFIG_NF_CONNTRACK is not set ++# CONFIG_NETFILTER_XTABLES is not set ++# CONFIG_IP_VS is not set ++ ++# ++# IP: Netfilter Configuration ++# ++# CONFIG_NF_DEFRAG_IPV4 is not set ++# CONFIG_IP_NF_QUEUE is not set ++# CONFIG_IP_NF_IPTABLES is not set ++# CONFIG_IP_NF_ARPTABLES is not set ++# CONFIG_BRIDGE_NF_EBTABLES is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++CONFIG_STP=m ++CONFIG_GARP=m ++CONFIG_BRIDGE=m ++# CONFIG_NET_DSA is not set ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++# CONFIG_DECNET is not set ++CONFIG_LLC=m ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++CONFIG_NET_PKTGEN=m ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++CONFIG_BT=m ++CONFIG_BT_L2CAP=m ++CONFIG_BT_SCO=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++ ++# ++# Bluetooth device drivers ++# ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIBTSDIO=m ++CONFIG_BT_HCIUART=m ++CONFIG_BT_HCIUART_H4=y ++CONFIG_BT_HCIUART_BCSP=y ++CONFIG_BT_HCIUART_LL=y ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_FIB_RULES=y ++CONFIG_WIRELESS=y ++CONFIG_CFG80211=m ++CONFIG_CFG80211_REG_DEBUG=y ++CONFIG_NL80211=y ++CONFIG_WIRELESS_OLD_REGULATORY=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WIRELESS_EXT_SYSFS=y ++CONFIG_LIB80211=m ++CONFIG_LIB80211_CRYPT_WEP=m ++CONFIG_LIB80211_CRYPT_CCMP=m ++CONFIG_LIB80211_CRYPT_TKIP=m ++# CONFIG_LIB80211_DEBUG is not set ++CONFIG_MAC80211=m ++ ++# ++# Rate control algorithm selection ++# ++CONFIG_MAC80211_RC_MINSTREL=y ++# CONFIG_MAC80211_RC_DEFAULT_PID is not set ++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y ++CONFIG_MAC80211_RC_DEFAULT="minstrel" ++CONFIG_MAC80211_MESH=y ++CONFIG_MAC80211_LEDS=y ++# CONFIG_MAC80211_DEBUGFS is not set ++# CONFIG_MAC80211_DEBUG_MENU is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++# CONFIG_FIRMWARE_IN_KERNEL is not set ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++CONFIG_CONNECTOR=m ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++CONFIG_FTL=y ++CONFIG_NFTL=y ++CONFIG_NFTL_RW=y ++CONFIG_INFTL=y ++CONFIG_RFD_FTL=y ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++CONFIG_MTD_JEDECPROBE=y ++CONFIG_MTD_GEN_PROBE=y ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_CFI_INTELEXT is not set ++CONFIG_MTD_CFI_AMDSTD=y ++CONFIG_MTD_CFI_STAA=y ++CONFIG_MTD_CFI_UTIL=y ++CONFIG_MTD_RAM=y ++CONFIG_MTD_ROM=y ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PHYSMAP is not set ++# CONFIG_MTD_ARM_INTEGRATOR is not set ++# CONFIG_MTD_IMPA7 is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++CONFIG_MTD_NAND_VERIFY_WRITE=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C2410=y ++# CONFIG_MTD_NAND_S3C2410_DEBUG is not set ++# CONFIG_MTD_NAND_S3C2410_HWECC is not set ++# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++CONFIG_MTD_NAND_PLATFORM=y ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++CONFIG_MTD_LPDDR=y ++CONFIG_MTD_QINFO_PROBE=y ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=m ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++CONFIG_BLK_DEV_NBD=m ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=65536 ++# CONFIG_BLK_DEV_XIP is not set ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_CDROM_PKTCDVD_BUFFERS=8 ++# CONFIG_CDROM_PKTCDVD_WCACHE is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=y ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_PROC_FS is not set ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=m ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++CONFIG_TUN=m ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++CONFIG_DM9000=y ++CONFIG_DM9000_DEBUGLEVEL=4 ++# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set ++# CONFIG_ENC28J60 is not set ++# CONFIG_SMC911X is not set ++# CONFIG_SMSC911X is not set ++# CONFIG_DNET is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++CONFIG_WLAN_80211=y ++CONFIG_LIBERTAS=m ++# CONFIG_LIBERTAS_USB is not set ++CONFIG_LIBERTAS_SDIO=m ++# CONFIG_LIBERTAS_DEBUG is not set ++# CONFIG_LIBERTAS_THINFIRM is not set ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_RTL8187 is not set ++# CONFIG_MAC80211_HWSIM is not set ++# CONFIG_P54_COMMON is not set ++# CONFIG_IWLWIFI_LEDS is not set ++CONFIG_HOSTAP=m ++CONFIG_HOSTAP_FIRMWARE=y ++CONFIG_HOSTAP_FIRMWARE_NVRAM=y ++# CONFIG_B43 is not set ++# CONFIG_B43LEGACY is not set ++CONFIG_ZD1211RW=m ++CONFIG_ZD1211RW_DEBUG=y ++# CONFIG_RT2X00 is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++CONFIG_INPUT_EVBUG=y ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++CONFIG_KEYBOARD_GPIO=y ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++CONFIG_SERIO_RAW=y ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++CONFIG_VT_HW_CONSOLE_BINDING=y ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=3 ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C2440=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=128 ++CONFIG_IPMI_HANDLER=m ++# CONFIG_IPMI_PANIC_EVENT is not set ++CONFIG_IPMI_DEVICE_INTERFACE=m ++CONFIG_IPMI_SI=m ++CONFIG_IPMI_WATCHDOG=m ++CONFIG_IPMI_POWEROFF=m ++CONFIG_HW_RANDOM=y ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++CONFIG_I2C_ALGOBIT=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++CONFIG_I2C_SIMTEC=y ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++CONFIG_SENSORS_TSL2550=y ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++CONFIG_SPI_BITBANG=y ++# CONFIG_SPI_GPIO is not set ++CONFIG_SPI_S3C24XX=y ++# CONFIG_SPI_S3C24XX_GPIO is not set ++ ++# ++# SPI Protocol Masters ++# ++CONFIG_SPI_SPIDEV=y ++# CONFIG_SPI_TLE62X0 is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++CONFIG_THERMAL=m ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2_COMMON=m ++CONFIG_VIDEO_ALLOW_V4L1=y ++CONFIG_VIDEO_V4L1_COMPAT=y ++CONFIG_DVB_CORE=m ++CONFIG_VIDEO_MEDIA=m ++ ++# ++# Multimedia drivers ++# ++# CONFIG_MEDIA_ATTACH is not set ++CONFIG_MEDIA_TUNER=m ++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=m ++CONFIG_MEDIA_TUNER_TDA8290=m ++CONFIG_MEDIA_TUNER_TDA9887=m ++CONFIG_MEDIA_TUNER_TEA5761=m ++CONFIG_MEDIA_TUNER_TEA5767=m ++CONFIG_MEDIA_TUNER_MT20XX=m ++CONFIG_MEDIA_TUNER_XC2028=m ++CONFIG_MEDIA_TUNER_XC5000=m ++CONFIG_VIDEO_V4L2=m ++CONFIG_VIDEO_V4L1=m ++CONFIG_VIDEOBUF_GEN=m ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEO_HELPER_CHIPS_AUTO=y ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_CPIA is not set ++# CONFIG_VIDEO_CPIA2 is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_VIDEO_AU0828 is not set ++CONFIG_SOC_CAMERA=m ++# CONFIG_SOC_CAMERA_MT9M001 is not set ++# CONFIG_SOC_CAMERA_MT9M111 is not set ++# CONFIG_SOC_CAMERA_MT9T031 is not set ++# CONFIG_SOC_CAMERA_MT9V022 is not set ++# CONFIG_SOC_CAMERA_TW9910 is not set ++CONFIG_SOC_CAMERA_PLATFORM=m ++# CONFIG_SOC_CAMERA_OV772X is not set ++# CONFIG_VIDEO_SH_MOBILE_CEU is not set ++CONFIG_V4L_USB_DRIVERS=y ++# CONFIG_USB_VIDEO_CLASS is not set ++CONFIG_USB_GSPCA=m ++# CONFIG_USB_M5602 is not set ++# CONFIG_USB_STV06XX is not set ++# CONFIG_USB_GSPCA_CONEX is not set ++# CONFIG_USB_GSPCA_ETOMS is not set ++# CONFIG_USB_GSPCA_FINEPIX is not set ++# CONFIG_USB_GSPCA_MARS is not set ++# CONFIG_USB_GSPCA_OV519 is not set ++# CONFIG_USB_GSPCA_OV534 is not set ++# CONFIG_USB_GSPCA_PAC207 is not set ++# CONFIG_USB_GSPCA_PAC7311 is not set ++# CONFIG_USB_GSPCA_SONIXB is not set ++# CONFIG_USB_GSPCA_SONIXJ is not set ++# CONFIG_USB_GSPCA_SPCA500 is not set ++# CONFIG_USB_GSPCA_SPCA501 is not set ++# CONFIG_USB_GSPCA_SPCA505 is not set ++# CONFIG_USB_GSPCA_SPCA506 is not set ++# CONFIG_USB_GSPCA_SPCA508 is not set ++# CONFIG_USB_GSPCA_SPCA561 is not set ++# CONFIG_USB_GSPCA_STK014 is not set ++# CONFIG_USB_GSPCA_SUNPLUS is not set ++# CONFIG_USB_GSPCA_T613 is not set ++# CONFIG_USB_GSPCA_TV8532 is not set ++# CONFIG_USB_GSPCA_VC032X is not set ++CONFIG_USB_GSPCA_ZC3XX=m ++# CONFIG_VIDEO_PVRUSB2 is not set ++# CONFIG_VIDEO_EM28XX is not set ++# CONFIG_VIDEO_USBVISION is not set ++# CONFIG_USB_VICAM is not set ++# CONFIG_USB_IBMCAM is not set ++# CONFIG_USB_KONICAWC is not set ++# CONFIG_USB_QUICKCAM_MESSENGER is not set ++# CONFIG_USB_ET61X251 is not set ++# CONFIG_VIDEO_OVCAMCHIP is not set ++# CONFIG_USB_OV511 is not set ++# CONFIG_USB_SE401 is not set ++# CONFIG_USB_SN9C102 is not set ++# CONFIG_USB_STV680 is not set ++# CONFIG_USB_ZC0301 is not set ++# CONFIG_USB_PWC is not set ++# CONFIG_USB_ZR364XX is not set ++# CONFIG_USB_STKWEBCAM is not set ++# CONFIG_USB_S2255 is not set ++CONFIG_RADIO_ADAPTERS=y ++# CONFIG_USB_DSBR is not set ++# CONFIG_USB_SI470X is not set ++# CONFIG_USB_MR800 is not set ++# CONFIG_RADIO_TEA5764 is not set ++# CONFIG_DVB_DYNAMIC_MINORS is not set ++CONFIG_DVB_CAPTURE_DRIVERS=y ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Supported USB Adapters ++# ++# CONFIG_DVB_USB is not set ++# CONFIG_DVB_SIANO_SMS1XXX is not set ++ ++# ++# Supported FlexCopII (B2C2) Adapters ++# ++# CONFIG_DVB_B2C2_FLEXCOP is not set ++ ++# ++# Supported DVB Frontends ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_FE_CUSTOMISE is not set ++ ++# ++# Multistandard (satellite) frontends ++# ++# CONFIG_DVB_STB0899 is not set ++# CONFIG_DVB_STB6100 is not set ++ ++# ++# DVB-S (satellite) frontends ++# ++# CONFIG_DVB_CX24110 is not set ++# CONFIG_DVB_CX24123 is not set ++# CONFIG_DVB_MT312 is not set ++# CONFIG_DVB_S5H1420 is not set ++# CONFIG_DVB_STV0288 is not set ++# CONFIG_DVB_STB6000 is not set ++# CONFIG_DVB_STV0299 is not set ++# CONFIG_DVB_TDA8083 is not set ++# CONFIG_DVB_TDA10086 is not set ++# CONFIG_DVB_TDA8261 is not set ++# CONFIG_DVB_VES1X93 is not set ++# CONFIG_DVB_TUNER_ITD1000 is not set ++# CONFIG_DVB_TUNER_CX24113 is not set ++# CONFIG_DVB_TDA826X is not set ++# CONFIG_DVB_TUA6100 is not set ++# CONFIG_DVB_CX24116 is not set ++# CONFIG_DVB_SI21XX is not set ++ ++# ++# DVB-T (terrestrial) frontends ++# ++# CONFIG_DVB_SP8870 is not set ++# CONFIG_DVB_SP887X is not set ++# CONFIG_DVB_CX22700 is not set ++# CONFIG_DVB_CX22702 is not set ++# CONFIG_DVB_DRX397XD is not set ++# CONFIG_DVB_L64781 is not set ++# CONFIG_DVB_TDA1004X is not set ++# CONFIG_DVB_NXT6000 is not set ++# CONFIG_DVB_MT352 is not set ++# CONFIG_DVB_ZL10353 is not set ++# CONFIG_DVB_DIB3000MB is not set ++# CONFIG_DVB_DIB3000MC is not set ++# CONFIG_DVB_DIB7000M is not set ++# CONFIG_DVB_DIB7000P is not set ++# CONFIG_DVB_TDA10048 is not set ++ ++# ++# DVB-C (cable) frontends ++# ++# CONFIG_DVB_VES1820 is not set ++# CONFIG_DVB_TDA10021 is not set ++# CONFIG_DVB_TDA10023 is not set ++# CONFIG_DVB_STV0297 is not set ++ ++# ++# ATSC (North American/Korean Terrestrial/Cable DTV) frontends ++# ++# CONFIG_DVB_NXT200X is not set ++# CONFIG_DVB_OR51211 is not set ++# CONFIG_DVB_OR51132 is not set ++# CONFIG_DVB_BCM3510 is not set ++# CONFIG_DVB_LGDT330X is not set ++# CONFIG_DVB_LGDT3304 is not set ++# CONFIG_DVB_S5H1409 is not set ++# CONFIG_DVB_AU8522 is not set ++# CONFIG_DVB_S5H1411 is not set ++ ++# ++# ISDB-T (terrestrial) frontends ++# ++# CONFIG_DVB_S921 is not set ++ ++# ++# Digital terrestrial only tuners/PLL ++# ++# CONFIG_DVB_PLL is not set ++# CONFIG_DVB_TUNER_DIB0070 is not set ++ ++# ++# SEC control devices for DVB-S ++# ++# CONFIG_DVB_LNBP21 is not set ++# CONFIG_DVB_ISL6405 is not set ++# CONFIG_DVB_ISL6421 is not set ++# CONFIG_DVB_LGS8GL5 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++# CONFIG_DVB_AF9013 is not set ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=y ++CONFIG_FB=y ++CONFIG_FIRMWARE_EDID=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++CONFIG_FB_MODE_HELPERS=y ++CONFIG_FB_TILEBLITTING=y ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_UVESA is not set ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_FB_S3C2410=y ++# CONFIG_FB_S3C2410_DEBUG is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++CONFIG_BACKLIGHT_LCD_SUPPORT=y ++CONFIG_LCD_CLASS_DEVICE=y ++# CONFIG_LCD_LTV350QV is not set ++# CONFIG_LCD_ILI9320 is not set ++# CONFIG_LCD_TDO24M is not set ++# CONFIG_LCD_VGG2432A4 is not set ++CONFIG_LCD_PLATFORM=y ++CONFIG_BACKLIGHT_CLASS_DEVICE=y ++# CONFIG_BACKLIGHT_GENERIC is not set ++CONFIG_BACKLIGHT_PWM=y ++ ++# ++# Display device support ++# ++CONFIG_DISPLAY_SUPPORT=y ++ ++# ++# Display hardware drivers ++# ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y ++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y ++CONFIG_FONTS=y ++CONFIG_FONT_8x8=y ++# CONFIG_FONT_8x16 is not set ++# CONFIG_FONT_6x11 is not set ++# CONFIG_FONT_7x14 is not set ++# CONFIG_FONT_PEARL_8x8 is not set ++# CONFIG_FONT_ACORN_8x8 is not set ++CONFIG_FONT_MINI_4x6=y ++# CONFIG_FONT_SUN8x16 is not set ++# CONFIG_FONT_SUN12x22 is not set ++# CONFIG_FONT_10x18 is not set ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++# CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_HWDEP=m ++CONFIG_SND_RAWMIDI=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_PCM_OSS_PLUGINS=y ++CONFIG_SND_SEQUENCER_OSS=y ++CONFIG_SND_DYNAMIC_MINORS=y ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_DRIVERS is not set ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++CONFIG_SND_USB=y ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_CAIAQ_INPUT=y ++CONFIG_SND_SOC=y ++CONFIG_SND_S3C24XX_SOC=y ++CONFIG_SND_S3C24XX_SOC_I2S=y ++# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set ++CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=y ++CONFIG_SND_SOC_I2C_AND_SPI=y ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_L3=y ++CONFIG_SND_SOC_UDA134X=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++# CONFIG_HID_DEBUG is not set ++CONFIG_HIDRAW=y ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_NTRIG=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_GREENASIA_FF is not set ++CONFIG_HID_TOPSEED=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_SUSPEND is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++CONFIG_USB_ACM=m ++# CONFIG_USB_PRINTER is not set ++CONFIG_USB_WDM=m ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++CONFIG_USB_STORAGE_DATAFAB=y ++# CONFIG_USB_STORAGE_FREECOM is not set ++CONFIG_USB_STORAGE_ISD200=y ++CONFIG_USB_STORAGE_USBAT=y ++CONFIG_USB_STORAGE_SDDR09=y ++CONFIG_USB_STORAGE_SDDR55=y ++CONFIG_USB_STORAGE_JUMPSHOT=y ++CONFIG_USB_STORAGE_ALAUDA=y ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++CONFIG_USB_LIBUSUAL=y ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=m ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++CONFIG_USB_SERIAL_CP2101=m ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++CONFIG_USB_SERIAL_FTDI_SIO=m ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++# CONFIG_USB_SERIAL_PL2303 is not set ++# CONFIG_USB_SERIAL_OTI6858 is not set ++CONFIG_USB_SERIAL_SPCP8X5=m ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIEMENS_MPI is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_OPTICON is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++CONFIG_USB_GADGET_S3C2410=y ++CONFIG_USB_S3C2410=y ++# CONFIG_USB_S3C2410_DEBUG is not set ++# CONFIG_USB_GADGET_IMX is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_CI13XXX is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++# CONFIG_USB_GADGET_DUALSPEED is not set ++CONFIG_USB_ZERO=m ++CONFIG_USB_ETH=m ++CONFIG_USB_ETH_RNDIS=y ++CONFIG_USB_GADGETFS=m ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++CONFIG_USB_G_SERIAL=m ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++CONFIG_USB_CDC_COMPOSITE=m ++ ++# ++# OTG and related infrastructure ++# ++# CONFIG_USB_GPIO_VBUS is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SPI=y ++CONFIG_MMC_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_NEW_LEDS=y ++CONFIG_LEDS_CLASS=y ++ ++# ++# LED drivers ++# ++CONFIG_LEDS_S3C24XX=y ++# CONFIG_LEDS_PCA9532 is not set ++CONFIG_LEDS_GPIO=y ++# CONFIG_LEDS_PCA955X is not set ++ ++# ++# LED Triggers ++# ++CONFIG_LEDS_TRIGGERS=y ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_BACKLIGHT=y ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++CONFIG_RTC_INTF_DEV_UIE_EMUL=y ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++CONFIG_DMADEVICES=y ++ ++# ++# DMA Devices ++# ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=m ++CONFIG_EXT2_FS_XATTR=y ++CONFIG_EXT2_FS_POSIX_ACL=y ++CONFIG_EXT2_FS_SECURITY=y ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++# CONFIG_JBD_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++CONFIG_AUTOFS_FS=y ++CONFIG_AUTOFS4_FS=y ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=m ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_ECRYPT_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_CRAMFS=y ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++CONFIG_SUNRPC_GSS=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++CONFIG_RPCSEC_GSS_KRB5=y ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_BSD_DISKLABEL=y ++CONFIG_MINIX_SUBPARTITION=y ++CONFIG_SOLARIS_X86_PARTITION=y ++CONFIG_UNIXWARE_DISKLABEL=y ++CONFIG_LDM_PARTITION=y ++# CONFIG_LDM_DEBUG is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++CONFIG_EFI_PARTITION=y ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="cp437" ++CONFIG_NLS_CODEPAGE_437=m ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=m ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_RT_MUTEX_TESTER is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_TRACE_BRANCH_PROFILING is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++# CONFIG_DEBUG_ERRORS is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_SECURITY_FILE_CAPABILITIES=y ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_FIPS=y ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=m ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=m ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++CONFIG_CRYPTO_GF128MUL=m ++CONFIG_CRYPTO_NULL=m ++CONFIG_CRYPTO_CRYPTD=m ++CONFIG_CRYPTO_AUTHENC=m ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++CONFIG_CRYPTO_CCM=m ++CONFIG_CRYPTO_GCM=m ++CONFIG_CRYPTO_SEQIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=m ++CONFIG_CRYPTO_CTS=m ++CONFIG_CRYPTO_ECB=y ++CONFIG_CRYPTO_LRW=m ++CONFIG_CRYPTO_PCBC=m ++CONFIG_CRYPTO_XTS=m ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++CONFIG_CRYPTO_XCBC=m ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=m ++CONFIG_CRYPTO_MD4=m ++CONFIG_CRYPTO_MD5=y ++CONFIG_CRYPTO_MICHAEL_MIC=y ++CONFIG_CRYPTO_RMD128=m ++CONFIG_CRYPTO_RMD160=m ++CONFIG_CRYPTO_RMD256=m ++CONFIG_CRYPTO_RMD320=m ++CONFIG_CRYPTO_SHA1=m ++CONFIG_CRYPTO_SHA256=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++CONFIG_CRYPTO_ANUBIS=m ++CONFIG_CRYPTO_ARC4=y ++CONFIG_CRYPTO_BLOWFISH=m ++CONFIG_CRYPTO_CAMELLIA=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_CAST6=m ++CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_FCRYPT=m ++CONFIG_CRYPTO_KHAZAD=m ++CONFIG_CRYPTO_SALSA20=m ++CONFIG_CRYPTO_SEED=m ++CONFIG_CRYPTO_SERPENT=m ++CONFIG_CRYPTO_TEA=m ++CONFIG_CRYPTO_TWOFISH=m ++CONFIG_CRYPTO_TWOFISH_COMMON=m ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=m ++CONFIG_CRYPTO_LZO=m ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=m ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=m ++CONFIG_CRC16=m ++CONFIG_CRC_T10DIF=y ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++CONFIG_CRC7=y ++CONFIG_LIBCRC32C=m ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=m ++CONFIG_LZO_DECOMPRESS=m ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/0011-MINI2440-Add-touchscreen-support.patch b/recipes/linux/linux-2.6.29/micro2440/0011-MINI2440-Add-touchscreen-support.patch new file mode 100644 index 0000000000..2b9c8c044d --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0011-MINI2440-Add-touchscreen-support.patch @@ -0,0 +1,192 @@ +From 8f148bda065698d45ab955b2c700ff1a58e28003 Mon Sep 17 00:00:00 2001 +From: Michel Pollet <buserror@gmail.com> +Date: Wed, 25 Mar 2009 17:45:09 +0000 +Subject: [PATCH] MINI2440: Add touchscreen support + +Uses the newly merged moko's touchscreen, optional. +Updated defconfig too. + +Signed-off-by: Michel Pollet <buserror@gmail.com> +--- + arch/arm/configs/mini2440_defconfig | 10 +++- + arch/arm/mach-s3c2440/mach-mini2440.c | 99 ++++++++++++++++++++++++++++++++- + 2 files changed, 106 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig +index 1602aca..4e79b4e 100644 +--- a/arch/arm/configs/mini2440_defconfig ++++ b/arch/arm/configs/mini2440_defconfig +@@ -1,7 +1,7 @@ + # + # Automatically generated make config: don't edit + # Linux kernel version: 2.6.29 +-# Wed Mar 25 17:21:37 2009 ++# Wed Mar 25 17:47:16 2009 + # + CONFIG_ARM=y + CONFIG_HAVE_PWM=y +@@ -814,8 +814,15 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y + # CONFIG_INPUT_JOYSTICK is not set + # CONFIG_INPUT_TABLET is not set + CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_FILTER=y ++CONFIG_TOUCHSCREEN_FILTER_GROUP=y ++CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y ++CONFIG_TOUCHSCREEN_FILTER_MEAN=y ++CONFIG_TOUCHSCREEN_FILTER_LINEAR=y + # CONFIG_TOUCHSCREEN_ADS7846 is not set + # CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_S3C2410=y ++# CONFIG_TOUCHSCREEN_S3C2410_DEBUG is not set + # CONFIG_TOUCHSCREEN_GUNZE is not set + # CONFIG_TOUCHSCREEN_ELO is not set + # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +@@ -1302,6 +1309,7 @@ CONFIG_LOGO=y + # CONFIG_LOGO_LINUX_MONO is not set + # CONFIG_LOGO_LINUX_VGA16 is not set + # CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_LOGO_ARMWORKS_CLUT224=y + CONFIG_SOUND=y + CONFIG_SOUND_OSS_CORE=y + CONFIG_SND=y +diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c +index 0cddb11..9f7d0ff 100644 +--- a/arch/arm/mach-s3c2440/mach-mini2440.c ++++ b/arch/arm/mach-s3c2440/mach-mini2440.c +@@ -48,6 +48,16 @@ + #include <plat/mci.h> + #include <plat/udc.h> + ++/* ++ * This is compiled conditionaly, as: ++ * 1) not everyone needs the touchscreen ++ * 2) that s3c_ts code might not have been added ++ * to the kernel with this file ++ */ ++#ifdef CONFIG_TOUCHSCREEN_S3C2410 ++#include <mach/ts.h> ++#endif ++ + #include <plat/regs-serial.h> + #include <mach/regs-gpio.h> + #include <mach/regs-mem.h> +@@ -64,6 +74,13 @@ + + #include <sound/s3c24xx_uda134x.h> + ++#ifdef CONFIG_TOUCHSCREEN_FILTER ++#include <../drivers/input/touchscreen/ts_filter_linear.h> ++#include <../drivers/input/touchscreen/ts_filter_mean.h> ++#include <../drivers/input/touchscreen/ts_filter_median.h> ++#include <../drivers/input/touchscreen/ts_filter_group.h> ++#endif ++ + #define MACH_MINI2440_DM9K_BASE (S3C2410_CS4 + 0x300) + + static struct map_desc mini2440_iodesc[] __initdata = { +@@ -123,6 +140,69 @@ static struct s3c2410_udc_mach_info mini2440_udc_cfg __initdata = { + .udc_command = mini2440_udc_pullup, + }; + ++/* touchscreen configuration */ ++ ++#ifdef CONFIG_TOUCHSCREEN_FILTER ++static struct ts_filter_linear_configuration mini2440_ts_linear_config __initdata = { ++ .constants = { ++ 0, /* x factor */ ++ 1, /* y proportion */ ++ 0, /* x offset */ ++ ++ 1, /* x factor */ ++ 0, /* y factor */ ++ 0, /* y offset */ ++ ++ 1 /* common divisor */ ++ }, ++ .coord0 = 0, ++ .coord1 = 1, ++}; ++ ++static struct ts_filter_group_configuration mini2440_ts_group_config __initdata = { ++ .extent = 12, ++ .close_enough = 10, ++ .threshold = 6, /* at least half of the points in a group */ ++ .attempts = 10, ++}; ++ ++static struct ts_filter_median_configuration mini2440_ts_median_config __initdata = { ++ .extent = 20, ++ .decimation_below = 3, ++ .decimation_threshold = 8 * 3, ++ .decimation_above = 4, ++}; ++ ++static struct ts_filter_mean_configuration mini2440_ts_mean_config __initdata = { ++ .bits_filter_length = 2, /* 4 points */ ++}; ++ ++static struct s3c2410_ts_mach_info mini2440_ts_cfg __initdata = { ++ .delay = 10000, ++ .presc = 0xff, /* slow as we can go */ ++ .filter_sequence = { ++ [0] = &ts_filter_group_api, ++ [1] = &ts_filter_median_api, ++ [2] = &ts_filter_mean_api, ++ [3] = &ts_filter_linear_api, ++ }, ++ .filter_config = { ++ [0] = &mini2440_ts_group_config, ++ [1] = &mini2440_ts_median_config, ++ [2] = &mini2440_ts_mean_config, ++ [3] = &mini2440_ts_linear_config, ++ }, ++}; ++#else /* !CONFIG_TOUCHSCREEN_FILTER */ ++#ifdef CONFIG_TOUCHSCREEN_S3C2410 ++static struct s3c2410_ts_mach_info mini2440_ts_cfg = { ++ .delay = 10000, ++ .presc = 0xff, /* slow as we can go */ ++}; ++#endif /* CONFIG_TOUCHSCREEN_S3C2410 */ ++#endif ++ ++/* LCD driver info */ + + /* LCD timing and setup */ + +@@ -646,8 +726,18 @@ static void mini2440_parse_features( + features->done |= FEATURE_BACKLIGHT; + break; + case 't': +- printk(KERN_INFO "MINI2440: '%c' ignored, " +- "touchscreen not compiled in\n", f); ++#ifdef CONFIG_TOUCHSCREEN_S3C2410 ++ if (features->done & FEATURE_TOUCH) ++ printk(KERN_INFO "MINI2440: '%c' ignored, " ++ "touchscreen already set\n", f); ++ else ++ features->optional[features->count++] = ++ &s3c_device_ts; ++ features->done |= FEATURE_TOUCH; ++#else ++ printk(KERN_INFO "MINI2440: '%c' ignored, " ++ "touchscreen not compiled in\n", f); ++#endif + break; + case 'c': + if (features->done & FEATURE_CAMERA) +@@ -714,6 +804,11 @@ static void __init mini2440_init(void) + i2c_register_board_info(0, mini2440_i2c_devs, + ARRAY_SIZE(mini2440_i2c_devs)); + ++#ifdef CONFIG_TOUCHSCREEN_S3C2410 ++ if (features.done & FEATURE_TOUCH) ++ set_s3c2410ts_info(&mini2440_ts_cfg); ++#endif ++ + platform_add_devices(mini2440_devices, ARRAY_SIZE(mini2440_devices)); + + if (features.count) /* the optional features */ +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/0012-GRO-Disable-GRO-on-legacy-netif_rx-path.patch b/recipes/linux/linux-2.6.29/micro2440/0012-GRO-Disable-GRO-on-legacy-netif_rx-path.patch new file mode 100644 index 0000000000..bfad6d80eb --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/0012-GRO-Disable-GRO-on-legacy-netif_rx-path.patch @@ -0,0 +1,54 @@ +From 11c0b33d2a046a37bcd96528faa0e93359ef4a4b Mon Sep 17 00:00:00 2001 +From: Herbert Xu <herbert@gondor.apana.org.au> +Date: Thu, 26 Mar 2009 00:59:10 -0700 +Subject: [PATCH] GRO: Disable GRO on legacy netif_rx path + +When I fixed the GRO crash in the legacy receive path I used +napi_complete to replace __napi_complete. Unfortunately they're +not the same when NETPOLL is enabled, which may result in us +not calling __napi_complete at all. + +What's more, we really do need to keep the __napi_complete call +within the IRQ-off section since in theory an IRQ can occur in +between and fill up the backlog to the maximum, causing us to +lock up. + +Since we can't seem to find a fix that works properly right now, +this patch reverts all the GRO support from the netif_rx path. + +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Michel Pollet <buserror@gmail.com> +--- + net/core/dev.c | 9 +++------ + 1 files changed, 3 insertions(+), 6 deletions(-) + +diff --git a/net/core/dev.c b/net/core/dev.c +index e3fe5c7..e438f54 100644 +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -2588,18 +2588,15 @@ static int process_backlog(struct napi_struct *napi, int quota) + local_irq_disable(); + skb = __skb_dequeue(&queue->input_pkt_queue); + if (!skb) { ++ __napi_complete(napi); + local_irq_enable(); +- napi_complete(napi); +- goto out; ++ break; + } + local_irq_enable(); + +- napi_gro_receive(napi, skb); ++ netif_receive_skb(skb); + } while (++work < quota && jiffies == start_time); + +- napi_gro_flush(napi); +- +-out: + return work; + } + +-- +1.5.6.3 + diff --git a/recipes/linux/linux-2.6.29/micro2440/defconfig b/recipes/linux/linux-2.6.29/micro2440/defconfig new file mode 100644 index 0000000000..e11a85a8f7 --- /dev/null +++ b/recipes/linux/linux-2.6.29/micro2440/defconfig @@ -0,0 +1,2053 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29 +# Sat Apr 4 16:57:10 2009 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +CONFIG_NO_IOPORT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +CONFIG_BLK_DEV_INTEGRITY=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_FREEZER=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +CONFIG_ARCH_S3C2410=y +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set +CONFIG_PLAT_S3C24XX=y +CONFIG_S3C2410_CLOCK=y +CONFIG_CPU_S3C244X=y +CONFIG_S3C24XX_PWM=y +CONFIG_S3C24XX_GPIO_EXTRA=0 +CONFIG_S3C2410_DMA=y +# CONFIG_S3C2410_DMA_DEBUG is not set +CONFIG_S3C24XX_ADC=y +CONFIG_PLAT_S3C=y +CONFIG_CPU_LLSERIAL_S3C2440_ONLY=y +CONFIG_CPU_LLSERIAL_S3C2440=y + +# +# Boot options +# +# CONFIG_S3C_BOOT_WATCHDOG is not set +# CONFIG_S3C_BOOT_ERROR_RESET is not set +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y + +# +# Power management +# +# CONFIG_S3C2410_PM_DEBUG is not set +# CONFIG_S3C2410_PM_CHECK is not set +CONFIG_S3C_LOWLEVEL_UART_PORT=0 +CONFIG_S3C_GPIO_SPACE=0 + +# +# S3C2400 Machines +# +CONFIG_S3C2410_PM=y +CONFIG_S3C2410_GPIO=y + +# +# S3C2410 Machines +# +# CONFIG_ARCH_SMDK2410 is not set +# CONFIG_ARCH_H1940 is not set +# CONFIG_MACH_N30 is not set +# CONFIG_ARCH_BAST is not set +# CONFIG_MACH_OTOM is not set +# CONFIG_MACH_AML_M5900 is not set +# CONFIG_MACH_TCT_HAMMER is not set +# CONFIG_MACH_VR1000 is not set +# CONFIG_MACH_QT2410 is not set + +# +# S3C2412 Machines +# +# CONFIG_MACH_JIVE is not set +# CONFIG_MACH_SMDK2413 is not set +# CONFIG_MACH_SMDK2412 is not set +# CONFIG_MACH_VSTMS is not set +CONFIG_CPU_S3C2440=y +CONFIG_S3C2440_DMA=y + +# +# S3C2440 Machines +# +# CONFIG_MACH_ANUBIS is not set +# CONFIG_MACH_OSIRIS is not set +# CONFIG_MACH_RX3715 is not set +# CONFIG_ARCH_S3C2440 is not set +# CONFIG_MACH_NEXCODER_2440 is not set +# CONFIG_MACH_AT2440EVB is not set +CONFIG_MACH_MINI2440=y + +# +# S3C2442 Machines +# + +# +# S3C2443 Machines +# +# CONFIG_MACH_SMDK2443 is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM920T=y +CONFIG_CPU_32v4T=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=200 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_COMPAT_NET_DEV_OPS=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=m +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_NL80211=y +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m + +# +# Rate control algorithm selection +# +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=m +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_FTL=y +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +CONFIG_INFTL=y +CONFIG_RFD_FTL=y +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_S3C2410=y +# CONFIG_MTD_NAND_S3C2410_DEBUG is not set +# CONFIG_MTD_NAND_S3C2410_HWECC is not set +# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +CONFIG_MTD_LPDDR=y +CONFIG_MTD_QINFO_PROBE=y + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +CONFIG_DM9000=y +CONFIG_DM9000_DEBUGLEVEL=4 +# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set +# CONFIG_ENC28J60 is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +CONFIG_LIBERTAS=m +# CONFIG_LIBERTAS_USB is not set +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_DEBUG is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8187 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_P54_COMMON is not set +# CONFIG_IWLWIFI_LEDS is not set +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +CONFIG_ZD1211RW=m +CONFIG_ZD1211RW_DEBUG=y +# CONFIG_RT2X00 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_FILTER=y +CONFIG_TOUCHSCREEN_FILTER_GROUP=y +CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y +CONFIG_TOUCHSCREEN_FILTER_MEAN=y +CONFIG_TOUCHSCREEN_FILTER_LINEAR=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +CONFIG_TOUCHSCREEN_S3C2410=y +# CONFIG_TOUCHSCREEN_S3C2410_DEBUG is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS=3 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_S3C2440=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=128 +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_S3C2410=y +CONFIG_I2C_SIMTEC=y + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +CONFIG_SENSORS_TSL2550=y +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_S3C24XX=y +# CONFIG_SPI_S3C24XX_GPIO is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=m +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_S3C2410_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_DVB_CORE=m +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=m +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_VIDEO_AU0828 is not set +CONFIG_SOC_CAMERA=m +# CONFIG_SOC_CAMERA_MT9M001 is not set +# CONFIG_SOC_CAMERA_MT9M111 is not set +# CONFIG_SOC_CAMERA_MT9T031 is not set +# CONFIG_SOC_CAMERA_MT9V022 is not set +# CONFIG_SOC_CAMERA_TW9910 is not set +CONFIG_SOC_CAMERA_PLATFORM=m +# CONFIG_SOC_CAMERA_OV772X is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +CONFIG_V4L_USB_DRIVERS=y +# CONFIG_USB_VIDEO_CLASS is not set +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +CONFIG_USB_GSPCA_ZC3XX=m +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_USB_VICAM is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_QUICKCAM_MESSENGER is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_VIDEO_OVCAMCHIP is not set +# CONFIG_USB_OV511 is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_STV680 is not set +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_PWC is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_USB_DSBR is not set +# CONFIG_USB_SI470X is not set +# CONFIG_USB_MR800 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_DVB_DYNAMIC_MINORS is not set +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set + +# +# Supported USB Adapters +# +# CONFIG_DVB_USB is not set +# CONFIG_DVB_SIANO_SMS1XXX is not set + +# +# Supported FlexCopII (B2C2) Adapters +# +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# Multistandard (satellite) frontends +# +# CONFIG_DVB_STB0899 is not set +# CONFIG_DVB_STB6100 is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_TDA8261 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TUNER_CX24113 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_SI21XX is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_DRX397XD is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_TDA10048 is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_LGDT3304 is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522 is not set +# CONFIG_DVB_S5H1411 is not set + +# +# ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_S921 is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_LGS8GL5 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_AF9013 is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_S3C2410=y +# CONFIG_FB_S3C2410_DEBUG is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +CONFIG_FONT_MINI_4x6=y +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_ARMWORKS_CLUT224=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_SOC=y +CONFIG_SND_S3C24XX_SOC=y +CONFIG_SND_S3C24XX_SOC_I2S=y +# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set +CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_L3=y +CONFIG_SND_SOC_UDA134X=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_GREENASIA_FF is not set +CONFIG_HID_TOPSEED=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=m +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +# CONFIG_USB_STORAGE_FREECOM is not set +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +# CONFIG_USB_EZUSB is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +CONFIG_USB_SERIAL_CP2101=m +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +CONFIG_USB_SERIAL_FTDI_SIO=m +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +CONFIG_USB_SERIAL_SPCP8X5=m +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +CONFIG_USB_GADGET_S3C2410=y +CONFIG_USB_S3C2410=y +# CONFIG_USB_S3C2410_DEBUG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_DUALSPEED is not set +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_CDC_COMPOSITE=m + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=y +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SPI=y +CONFIG_MMC_S3C=y +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_S3C24XX=y +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_PCA955X is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +CONFIG_DEBUG_S3C_UART=0 + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_FILE_CAPABILITIES=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_FIPS=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y diff --git a/recipes/linux/linux/ep93xx/defconfig b/recipes/linux/linux/ep93xx/defconfig index e42a804b5a..78f1927f06 100644 --- a/recipes/linux/linux/ep93xx/defconfig +++ b/recipes/linux/linux/ep93xx/defconfig @@ -1,46 +1,71 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1-git9 -# Sat Jul 15 20:13:41 2006 +# Linux kernel version: 2.6.29 +# Wed Apr 15 16:39:12 2009 # CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_RUNTIME_PHYS_OFFSET=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -CONFIG_SYSCTL=y # CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_UID16=y +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -49,43 +74,53 @@ CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y CONFIG_FUTEX=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_SLAB=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set # CONFIG_SLOB is not set - -# -# Loadable module support -# +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Block layer -# +CONFIG_BLOCK=y +# CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y # CONFIG_IOSCHED_AS is not set -CONFIG_IOSCHED_DEADLINE=y +# CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set # CONFIG_DEFAULT_AS is not set -CONFIG_DEFAULT_DEADLINE=y +# CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_FREEZER=y # # System Type @@ -95,28 +130,39 @@ CONFIG_DEFAULT_IOSCHED="deadline" # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set CONFIG_ARCH_EP93XX=y # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set # CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_IOP3XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set # # Cirrus EP93xx Implementation Options @@ -126,24 +172,39 @@ CONFIG_CRUNCH=y # # EP93xx Platforms # +CONFIG_MACH_ADSSPHERE=y +CONFIG_MACH_EDB9301=y CONFIG_MACH_EDB9302=y +CONFIG_MACH_EDB9302A=y +CONFIG_MACH_EDB9307=y +CONFIG_MACH_EDB9307A=y +CONFIG_MACH_EDB9312=y CONFIG_MACH_EDB9315=y CONFIG_MACH_EDB9315A=y CONFIG_MACH_GESBC9312=y -# CONFIG_MACH_MICRO9 is not set +CONFIG_MACH_MICRO9=y +CONFIG_MACH_MICRO9H=y +CONFIG_MACH_MICRO9M=y +CONFIG_MACH_MICRO9L=y CONFIG_MACH_TS72XX=y +CONFIG_EP93XX_EARLY_UART1=y +# CONFIG_EP93XX_EARLY_UART2 is not set +# CONFIG_EP93XX_EARLY_UART3 is not set # # Processor Type # CONFIG_CPU_32=y CONFIG_CPU_ARM920T=y -CONFIG_CPU_32v4=y +CONFIG_CPU_32v4T=y CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_PABRT_NOIFAR=y CONFIG_CPU_CACHE_V4WT=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_COPY_V4WB=y CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y # # Processor Features @@ -152,36 +213,44 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_OUTER_CACHE is not set CONFIG_ARM_VIC=y +CONFIG_COMMON_CLKDEV=y # # Bus support # CONFIG_ARM_AMBA=y - -# -# PCCARD (PCMCIA/CardBus) support -# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_PCCARD is not set # # Kernel Features # -# CONFIG_PREEMPT is not set -# CONFIG_NO_IDLE_HZ is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y CONFIG_HZ=100 CONFIG_AEABI=y -CONFIG_OABI_COMPAT=y -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_ALIGNMENT_TRAP=y # @@ -189,8 +258,15 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyAM0,57600 root=/dev/nfs ip=bootp" +CONFIG_CMDLINE="console=ttyAM0,115200 root=/dev/nfs ip=bootp" # CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y # # Floating point emulation @@ -199,38 +275,42 @@ CONFIG_CMDLINE="console=ttyAM0,57600 root=/dev/nfs ip=bootp" # # At least one emulation must be selected # -CONFIG_FPE_NWFPE=y -CONFIG_FPE_NWFPE_XP=y -# CONFIG_FPE_FASTFPE is not set # # Userspace binary formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y # CONFIG_BINFMT_AOUT is not set # CONFIG_BINFMT_MISC is not set # # Power management options # -# CONFIG_PM is not set -# CONFIG_APM is not set - -# -# Networking -# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set +CONFIG_COMPAT_NET_DEV_OPS=y CONFIG_PACKET=y CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set @@ -248,42 +328,24 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set # CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -CONFIG_IPV6=y -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=y -CONFIG_INET6_XFRM_MODE_TUNNEL=y -# CONFIG_IPV6_TUNNEL is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# # CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -291,23 +353,25 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=y # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -# CONFIG_IEEE80211 is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -316,40 +380,39 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set CONFIG_MTD_CONCAT=y CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 # CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set # CONFIG_MTD_REDBOOT_PARTS_READONLY is not set -# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers # CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -380,16 +443,13 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set CONFIG_MTD_ROM=y # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0x0 -CONFIG_MTD_PHYSMAP_LEN=0x0 -CONFIG_MTD_PHYSMAP_BANKWIDTH=1 +# CONFIG_MTD_PHYSMAP_COMPAT is not set # CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_PLATRAM is not set @@ -407,49 +467,57 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1 # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# CONFIG_MTD_NAND=y CONFIG_MTD_NAND_VERIFY_WRITE=y # CONFIG_MTD_NAND_ECC_SMC is not set -CONFIG_MTD_NAND_TS7250=y +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_TS7250 is not set CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set - -# -# OneNAND Flash Device Drivers -# +# CONFIG_MTD_NAND_PLATFORM is not set # CONFIG_MTD_ONENAND is not set # -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support +# LPDDR flash memory drivers # +# CONFIG_MTD_LPDDR is not set # -# Block devices +# UBI - Unsorted block images # +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_NBD=y # CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_LEGACY=y +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set # CONFIG_SCSI_PROC_FS is not set # @@ -468,94 +536,68 @@ CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m # -# SCSI Transport Attributes +# SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set - -# -# SCSI low-level drivers -# +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set -# CONFIG_SCSI_SATA is not set +# CONFIG_LIBFC is not set # CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set # CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# PHY device support -# +# CONFIG_VETH is not set # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y CONFIG_MII=y CONFIG_EP93XX_ETH=y +# CONFIG_AX88796 is not set # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set # -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) +# Wireless LAN # +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces +# Enable WiMAX (Networking options) to see the WiMAX drivers # # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set # @@ -573,6 +615,7 @@ CONFIG_EP93XX_ETH=y # Character devices # # CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # @@ -589,109 +632,100 @@ CONFIG_SERIAL_AMBA_PL010_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_EP93XX_WATCHDOG=y - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set # CONFIG_HW_RANDOM is not set -# CONFIG_NVRAM is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# # CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y # -# TPM devices +# I2C Hardware Bus support # -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set # -# I2C support +# I2C system bus drivers (mostly embedded / system-on-chip) # -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set # -# I2C Algorithms +# External I2C/SMBus adapter drivers # -CONFIG_I2C_ALGOBIT=y -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set # -# I2C Hardware Bus support +# Other I2C/SMBus bus drivers # -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set -# CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_EP93XX is not set # # Miscellaneous I2C Chip support # -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set -# CONFIG_SENSORS_EEPROM is not set +# CONFIG_DS1682 is not set # CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set -CONFIG_I2C_DEBUG_CORE=y -CONFIG_I2C_DEBUG_ALGO=y -CONFIG_I2C_DEBUG_BUS=y -CONFIG_I2C_DEBUG_CHIP=y +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set # -# SPI support +# Memory mapped GPIO expanders: # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set # -# Dallas's 1-wire bus +# I2C GPIO expanders: # +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set # -# Hardware Monitoring support +# PCI GPIO expanders: # + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set @@ -705,218 +739,119 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set # -# Misc devices +# Watchdog Device Drivers # +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_EP93XX_WATCHDOG=y +CONFIG_SSB_POSSIBLE=y # -# LED devices +# Sonics Silicon Backplane # -# CONFIG_NEW_LEDS is not set +# CONFIG_SSB is not set # -# LED drivers +# Multifunction device drivers # +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set # -# LED Triggers +# Multimedia devices # # -# Multimedia devices +# Multimedia core support # # CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set # -# Digital Video Broadcasting Devices +# Multimedia drivers # -# CONFIG_DVB is not set -# CONFIG_USB_DABUSB is not set +# CONFIG_DAB is not set # # Graphics support # -# CONFIG_FIRMWARE_EDID is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # -# Sound +# Display device support # +# CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y # -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=y -CONFIG_USB_DEBUG=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_BANDWIDTH is not set -CONFIG_USB_DYNAMIC_MINORS=y -# CONFIG_USB_OTG is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# may also be needed; see USB_STORAGE Help for more information -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y - -# -# Input core support is needed for USB HID input layer or HIDBP support -# -# CONFIG_USB_HIDDEV is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -CONFIG_USB_PEGASUS=y -CONFIG_USB_RTL8150=y -# CONFIG_USB_USBNET is not set -# CONFIG_USB_MON is not set - -# -# USB port drivers -# - -# -# USB Serial Converter support -# -CONFIG_USB_SERIAL=y -CONFIG_USB_SERIAL_CONSOLE=y -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_AIRPRIME is not set -# CONFIG_USB_SERIAL_ANYDATA is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP2101 is not set -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -CONFIG_USB_SERIAL_PL2303=y -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGETKIT is not set -# CONFIG_USB_PHIDGETSERVO is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TEST is not set - -# -# USB DSL modem support -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support +# LED drivers # -# CONFIG_MMC is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_PCA955X is not set # -# Real Time Clock +# LED Triggers # +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set # # RTC interfaces @@ -925,24 +860,54 @@ CONFIG_RTC_INTF_SYSFS=y CONFIG_RTC_INTF_PROC=y CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set # -# RTC drivers +# I2C RTC drivers # -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_ISL1208 is not set +CONFIG_RTC_DRV_DS1307=y +# CONFIG_RTC_DRV_DS1374 is not set # CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -CONFIG_RTC_DRV_M48T86=y +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# CONFIG_RTC_DRV_EP93XX=y +# CONFIG_RTC_DRV_PL030 is not set # CONFIG_RTC_DRV_PL031 is not set -# CONFIG_RTC_DRV_TEST is not set -# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -952,19 +917,19 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set @@ -989,15 +954,14 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # Pseudo filesystems # CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# +CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -1005,37 +969,39 @@ CONFIG_RAMFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set # CONFIG_JFFS2_SUMMARY is not set # CONFIG_JFFS2_FS_XATTR is not set # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set # CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1043,7 +1009,6 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types @@ -1065,10 +1030,7 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_SUN_PARTITION is not set # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set - -# -# Native Language Support -# +# CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y @@ -1109,43 +1071,76 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set +# CONFIG_DLM is not set # # Kernel hacking # -# CONFIG_PRINTK_TIME is not set +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y -CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set CONFIG_DEBUG_SLAB=y # CONFIG_DEBUG_SLAB_LEAK is not set +CONFIG_DEBUG_PREEMPT=y # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_FS is not set # CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set CONFIG_FRAME_POINTER=y -# CONFIG_UNWIND_INFO is not set -CONFIG_FORCED_INLINING=y +# CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_WAITQ=y CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y # CONFIG_DEBUG_ICEDCC is not set @@ -1154,23 +1149,113 @@ CONFIG_DEBUG_LL=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set # -# Cryptographic options +# Compression # -# CONFIG_CRYPTO is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set # -# Hardware crypto devices +# Random Number Generation # +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y # # Library routines # +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set CONFIG_LIBCRC32C=y CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/recipes/linux/linux_2.6.29.bb b/recipes/linux/linux_2.6.29.bb index 1ba739b325..b6d6e45b78 100644 --- a/recipes/linux/linux_2.6.29.bb +++ b/recipes/linux/linux_2.6.29.bb @@ -1,6 +1,6 @@ require linux.inc -PR = "r2" +PR = "r3" S = "${WORKDIR}/linux-2.6.29" @@ -11,6 +11,8 @@ DEFAULT_PREFERENCE_canyonlands = "1" DEFAULT_PREFERENCE_tosa = "1" DEFAULT_PREFERENCE_vortex86sx = "1" DEFAULT_PREFERENCE_atngw100 = "1" +DEFAULT_PREFERENCE_micro2440 = "1" +DEFAULT_PREFERENCE_ep93xx = "1" SRC_URI = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-2.6.29.tar.bz2 \ file://defconfig" @@ -31,7 +33,27 @@ SRC_URI_append_canyonlands = " \ file://0001-powerpc-4xx-Add-PPC4xx-PCIe-MSI-support.patch;patch=1 \ " +SRC_URI_append_micro2440 = " \ + file://0001-S3C-Backported-the-s3c2410-touchscreen-from-openmok.patch;patch=1 \ + file://0002-S3C-Backported-openmoko-s-touchscreen-filters.patch;patch=1 \ + file://0003-VENDOR-armworks-logo.patch;patch=1 \ + file://0004-920T-Use-specific-920t-mtune.patch;patch=1 \ + file://0005-920T-Temp-fix-for-the-40-relocation-binutils-pro.patch;patch=1 \ + file://0006-S3C-Allow-the-machine-code-to-get-the-BBT-table-fro.patch;patch=1 \ + file://0007-MINI2440-Add-machine-support.patch;patch=1 \ + file://0008-MINI2440-Delays-command-check-response-on-SD.patch;patch=1 \ + file://0009-MINI2440-Rename-the-SoC-tty-names.patch;patch=1 \ + file://0010-MINI2440-creates-a-mini2440_defconfig-file.patch;patch=1 \ + file://0011-MINI2440-Add-touchscreen-support.patch;patch=1 \ + file://0012-GRO-Disable-GRO-on-legacy-netif_rx-path.patch;patch=1 \ + " + SRC_URI_append_tosa = " \ file://0001-pxa-make-second-argument-of-clk_add_alias-a-name-in.patch;patch=1 \ file://0002-spi-pxa2xx-spi-set-default-cs_control-to-null_cs_co.patch;patch=1 \ " + +SRC_URI_append_ep93xx = " \ + file://add-edb9301.patch;patch=1 \ + file://edb9301-fix-machine-id.patch;patch=1 \ + " diff --git a/recipes/packagekit/packagekit_0.4.6.bb b/recipes/packagekit/packagekit_0.4.6.bb index b5ad645c90..51b2870537 100644 --- a/recipes/packagekit/packagekit_0.4.6.bb +++ b/recipes/packagekit/packagekit_0.4.6.bb @@ -3,7 +3,7 @@ SECTION = "libs" PRIORITY = "optional" LICENSE = "GPL" DEPENDS = "gtk+ python cppunit policykit dbus (>= 1.1.1) dbus-glib glib-2.0 sqlite3 opkg intltool intltool-native (>= 0.37.1)" -RDEPENDS_${PN} = "opkg" +RDEPENDS_${PN} = "${IPKG_VARIANT}" inherit gnome autotools_stage @@ -12,6 +12,7 @@ SRC_URI = "http://www.packagekit.org/releases/PackageKit-${PV}.tar.gz \ file://opkg-fix-includes.diff;patch=1 \ file://opkg-fix-declarations.diff;patch=1 " +PR = "r1" PE = "1" S = "${WORKDIR}/PackageKit-${PV}" diff --git a/recipes/python/python-2.6.1/05-enable-ctypes-cross-build.patch b/recipes/python/python-2.6.1/05-enable-ctypes-cross-build.patch index 874b8be01d..58b8078068 100644 --- a/recipes/python/python-2.6.1/05-enable-ctypes-cross-build.patch +++ b/recipes/python/python-2.6.1/05-enable-ctypes-cross-build.patch @@ -22,7 +22,7 @@ Index: Python-2.6.1/setup.py res = os.system(cmd) if res or not os.path.exists(ffi_configfile): - print "Failed to configure _ctypes module" -+ print "Failed to configure _ctypes module (ret=%d) or missing conffile=%s" % ( ret, ffi_configfile ) ++ print "Failed to configure _ctypes module (res=%d) or missing conffile=%s" % ( res, ffi_configfile ) return False fficonfig = {} diff --git a/recipes/python/python_2.6.1.bb b/recipes/python/python_2.6.1.bb index 57c64dfa55..e50ca43aab 100644 --- a/recipes/python/python_2.6.1.bb +++ b/recipes/python/python_2.6.1.bb @@ -1,7 +1,7 @@ require python.inc DEPENDS = "python-native db gdbm openssl readline sqlite3 tcl tk zlib" DEPENDS_sharprom = "python-native db readline zlib gdbm openssl" -PR = "ml4" +PR = "ml5" SRC_URI = "\ http://www.python.org/ftp/python/${PV}/Python-${PV}.tar.bz2 \ diff --git a/recipes/sysstat/sysstat_8.1.6.bb b/recipes/sysstat/sysstat_8.1.6.bb index 0f394ed259..a734d14f57 100644 --- a/recipes/sysstat/sysstat_8.1.6.bb +++ b/recipes/sysstat/sysstat_8.1.6.bb @@ -2,6 +2,7 @@ DESCRIPTION = "The sysstat utilities are a collection of performance monitoring HOMEPAGE = "http://pagesperso-orange.fr/sebastien.godard/" LICENSE = "GPL" SECTION = "console/utils" +PR = "r1" SRC_URI = "http://pagesperso-orange.fr/sebastien.godard/sysstat-${PV}.tar.gz" @@ -13,3 +14,4 @@ do_configure_prepend() { FILES_${PN} += "${libdir}/sa" +TARGET_CC_ARCH += "${LDFLAGS}" diff --git a/recipes/u-boot/u-boot-2009.03/hipox/00-hipox.patch b/recipes/u-boot/u-boot-2009.03/hipox/00-hipox.patch new file mode 100644 index 0000000000..1433e90193 --- /dev/null +++ b/recipes/u-boot/u-boot-2009.03/hipox/00-hipox.patch @@ -0,0 +1,7034 @@ +diff -Nurd u-boot-2009.03.orig/Makefile u-boot-2009.03/Makefile +--- u-boot-2009.03.orig/Makefile 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/Makefile 2009-04-15 11:08:18.000000000 +0200 +@@ -2842,6 +2842,10 @@ + fi; + @$(MKCONFIG) SX1 arm arm925t sx1 + ++hipox_config : unconfig ++ @ln -s -f ./u-boot-arm926ejs.lds ./board/hipox/u-boot.lds ++ @$(MKCONFIG) hipox arm arm926ejs hipox; ++ + # TRAB default configuration: 8 MB Flash, 32 MB RAM + xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1)))) + +@@ -3486,7 +3490,7 @@ + @rm -f $(obj)api_examples/demo $(TIMESTAMP_FILE) $(VERSION_FILE) + @find $(OBJTREE) -type f \ + \( -name 'core' -o -name '*.bak' -o -name '*~' \ +- -o -name '*.o' -o -name '*.a' \) -print \ ++ -o -name '*.o' -o -name '*.a' -o -name .depend \) -print \ + | xargs rm -f + + clobber: clean +diff -Nurd u-boot-2009.03.orig/board/hipox/Makefile u-boot-2009.03/board/hipox/Makefile +--- u-boot-2009.03.orig/board/hipox/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/Makefile 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,51 @@ ++# ++# (C) Copyright 2000-2004 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# (C) Copyright 2004 ++# ARM Ltd. ++# Philippe Robin, <philippe.robin@arm.com> ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS := hipox.o eth.o ide-$(NAS_VERSION).o ++SOBJS := platform-$(NAS_VERSION).o ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $^ ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++-include .depend ++ ++######################################################################### +diff -Nurd u-boot-2009.03.orig/board/hipox/config.mk u-boot-2009.03/board/hipox/config.mk +--- u-boot-2009.03.orig/board/hipox/config.mk 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/config.mk 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,29 @@ ++TEXT_BASE = 0x48d00000 ++CROSS_COMPILE = arm-linux- ++ ++PLL400 ?= 733333333 ++RPSCLK ?= 25000000 ++ ++NAS_VERSION ?= 810 ++FPGA ?= 0 ++FPGA_ARM_CLK ?= 25000000 ++ ++PROBE_MEM_SIZE ?= 1 ++MEM_SIZE ?= 128 # Memory size in megabytes if probing is not enabled ++MEM_ODT ?= 150 ++ ++USE_SATA ?= 1 ++USE_SATA_ENV ?= 0 ++USE_FLASH ?= 1 ++USE_NAND ?= 1 ++ ++LINUX_ROOT_RAIDED ?= 0 ++ ++USE_EXTERNAL_UART ?= 0 ++INTERNAL_UART ?= 2 ++ ++USE_LEON_TIME_COUNT ?= 1 # uses leon counted time to update system time on power-up ++ ++TEST_BRD ?= 0 # Only significant for OX800 ++ ++PLATFORM_CPPFLAGS += -DLINUX_ROOT_RAIDED=$(LINUX_ROOT_RAIDED) -DMEM_ODT=$(MEM_ODT) -DPROBE_MEM_SIZE=$(PROBE_MEM_SIZE) -DNAS_VERSION=$(NAS_VERSION) -DFPGA=$(FPGA) -DFPGA_ARM_CLK=$(FPGA_ARM_CLK) -DINTERNAL_UART=$(INTERNAL_UART) -DUSE_EXTERNAL_UART=$(USE_EXTERNAL_UART) -DMEM_SIZE=$(MEM_SIZE) -DPLL400=$(PLL400) -DRPSCLK=$(RPSCLK) -DTEST_BRD=$(TEST_BRD) -DUSE_SATA=$(USE_SATA) -DUSE_SATA_ENV=$(USE_SATA_ENV) -DUSE_FLASH=$(USE_FLASH) -DUSE_LEON_TIME_COUNT=$(USE_LEON_TIME_COUNT) -DCONFIG_HIPOX_USE_NAND=$(USE_NAND) +diff -Nurd u-boot-2009.03.orig/board/hipox/eth.c u-boot-2009.03/board/hipox/eth.c +--- u-boot-2009.03.orig/board/hipox/eth.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/eth.c 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,1668 @@ ++/* ++ * (C) Copyright 2005 ++ * Oxford Semiconductor Ltd ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <malloc.h> ++#include <net.h> ++//#include <asm/barrier.h> ++ ++#define wmb() asm volatile ("" : : :"memory") ++ ++//#define DEBUG_GMAC_INIT ++ ++// The number of bytes wasted at the start of a received packet buffer in order ++// to ensure the IP header will be aligned to a 32-bit boundary ++static const int ETHER_FRAME_ALIGN_WASTAGE = 2; ++static const int EXTRA_RX_SKB_SPACE = 32; // Otherwise GMAC spans over >1 skb ++static const int ETHER_MTU = 1500; ++ ++static const u32 MAC_BASE_OFFSET = 0x0000; ++static const u32 DMA_BASE_OFFSET = 0x1000; ++ ++static const int NUM_TX_DMA_DESCRIPTORS = 1; ++static const int NUM_RX_DMA_DESCRIPTORS = 32; ++ ++/* Generic MII registers. */ ++#define MII_BMCR 0x00 /* Basic mode control register */ ++#define MII_BMSR 0x01 /* Basic mode status register */ ++#define MII_PHYSID1 0x02 /* PHYS ID 1 */ ++#define MII_PHYSID2 0x03 /* PHYS ID 2 */ ++#define MII_ADVERTISE 0x04 /* Advertisement control reg */ ++#define MII_LPA 0x05 /* Link partner ability reg */ ++#define MII_EXPANSION 0x06 /* Expansion register */ ++#define MII_CTRL1000 0x09 /* 1000BASE-T control */ ++#define MII_STAT1000 0x0a /* 1000BASE-T status */ ++#define MII_ESTATUS 0x0f /* Extended Status */ ++ ++/* Basic mode control register. */ ++#define BMCR_RESV 0x003f /* Unused... */ ++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ ++#define BMCR_CTST 0x0080 /* Collision test */ ++#define BMCR_FULLDPLX 0x0100 /* Full duplex */ ++#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ ++#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ ++#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ ++#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ ++#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ ++#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ ++#define BMCR_RESET 0x8000 /* Reset the DP83840 */ ++ ++/* Basic mode status register. */ ++#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ ++#define BMSR_JCD 0x0002 /* Jabber detected */ ++#define BMSR_LSTATUS 0x0004 /* Link status */ ++#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ ++#define BMSR_RFAULT 0x0010 /* Remote fault detected */ ++#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ ++#define BMSR_RESV 0x00c0 /* Unused... */ ++#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ ++#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */ ++#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */ ++#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ ++#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ ++#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ ++#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ ++#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ ++ ++/* 1000BASE-T Status register */ ++#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ ++#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ ++#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ ++#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ ++#define PHY_TYPE_NONE 0 ++#define PHY_TYPE_MICREL_KS8721BL 0x00221619 ++#define PHY_TYPE_VITESSE_VSC8201XVZ 0x000fc413 ++#define PHY_TYPE_REALTEK_RTL8211BGR 0x001cc912 ++#define PHY_TYPE_LSI_ET1011C 0x0282f013 ++ ++/* Specific PHY values */ ++#define VSC8201_MII_ACSR 0x1c // Vitesse VCS8201 gigabit PHY Auxillary Control and Status register ++#define VSC8201_MII_ACSR_MDPPS_BIT 2 // Mode/Duplex Pin Priority Select ++ ++#define ET1011C_MII_CONFIG 0x16 ++#define ET1011C_MII_CONFIG_IFMODESEL 0 ++#define ET1011C_MII_CONFIG_IFMODESEL_NUM_BITS 3 ++#define ET1011C_MII_CONFIG_SYSCLKEN 4 ++#define ET1011C_MII_CONFIG_TXCLKEN 5 ++#define ET1011C_MII_CONFIG_TBI_RATESEL 8 ++#define ET1011C_MII_CONFIG_CRS_TX_EN 15 ++ ++#define ET1011C_MII_CONFIG_IFMODESEL_GMII_MII 0 ++#define ET1011C_MII_CONFIG_IFMODESEL_TBI 1 ++#define ET1011C_MII_CONFIG_IFMODESEL_GMII_MII_GTX 2 ++ ++#define ET1011C_MII_LED2 0x1c ++#define ET1011C_MII_LED2_LED_TXRX 12 ++#define ET1011C_MII_LED2_LED_NUM_BITS 4 ++ ++#define ET1011C_MII_LED2_LED_TXRX_ON 0xe ++#define ET1011C_MII_LED2_LED_TXRX_ACTIVITY 0x7 ++ ++// Some typedefs to cope with std Linux types ++typedef void sk_buff_t; ++ ++// The in-memory descriptor structures ++typedef struct gmac_dma_desc ++{ ++ /** The encoded status field of the GMAC descriptor */ ++ u32 status; ++ /** The encoded length field of GMAC descriptor */ ++ u32 length; ++ /** Buffer 1 pointer field of GMAC descriptor */ ++ u32 buffer1; ++ /** Buffer 2 pointer or next descriptor pointer field of GMAC descriptor */ ++ u32 buffer2; ++ /** Not used for U-Boot */ ++ u32 skb; ++} __attribute ((packed)) gmac_dma_desc_t; ++ ++typedef struct gmac_desc_list_info ++{ ++ gmac_dma_desc_t* base_ptr; ++ int num_descriptors; ++ int empty_count; ++ int full_count; ++ int r_index; ++ int w_index; ++} gmac_desc_list_info_t; ++ ++// Private data structure for the GMAC driver ++typedef struct gmac_priv ++{ ++ /** Base address of GMAC MAC registers */ ++ u32 macBase; ++ /** Base address of GMAC DMA registers */ ++ u32 dmaBase; ++ ++ /** The number of descriptors in the gmac_dma_desc_t array holding both the ++ * TX and RX descriptors. The TX descriptors reside at the start of the ++ * array */ ++ unsigned total_num_descriptors; ++ ++ /** The address of the start of the descriptor array */ ++ gmac_dma_desc_t *desc_base_addr; ++ ++ /** Descriptor list management */ ++ gmac_desc_list_info_t tx_gmac_desc_list_info; ++ gmac_desc_list_info_t rx_gmac_desc_list_info; ++ ++ /** PHY info */ ++ u32 phy_type; ++ u32 phy_addr; ++ int phy_id; ++ int link_is_1000M; ++} gmac_priv_t; ++ ++/** ++ * MAC register indices ++ */ ++typedef enum gmac_mac_regs { ++ MAC_CONFIG_REG = 0, ++ MAC_FRAME_FILTER_REG = 1, ++ MAC_HASH_HIGH_REG = 2, ++ MAC_HASH_LOW_REG = 3, ++ MAC_GMII_ADR_REG = 4, ++ MAC_GMII_DATA_REG = 5, ++ MAC_FLOW_CNTL_REG = 6, ++ MAC_VLAN_TAG_REG = 7, ++ MAC_VERSION_REG = 8, ++ MAC_ADR0_HIGH_REG = 16, ++ MAC_ADR0_LOW_REG = 17, ++ MAC_ADR1_HIGH_REG = 18, ++ MAC_ADR1_LOW_REG = 19, ++ MAC_ADR2_HIGH_REG = 20, ++ MAC_ADR2_LOW_REG = 21, ++ MAC_ADR3_HIGH_REG = 22, ++ MAC_ADR3_LOW_REG = 23, ++ MAC_ADR4_HIGH_REG = 24, ++ MAC_ADR4_LOW_REG = 25, ++ MAC_ADR5_HIGH_REG = 26, ++ MAC_ADR5_LOW_REG = 27, ++ MAC_ADR6_HIGH_REG = 28, ++ MAC_ADR6_LOW_REG = 29, ++ MAC_ADR7_HIGH_REG = 30, ++ MAC_ADR7_LOW_REG = 31, ++ MAC_ADR8_HIGH_REG = 32, ++ MAC_ADR8_LOW_REG = 33, ++ MAC_ADR9_HIGH_REG = 34, ++ MAC_ADR9_LOW_REG = 35, ++ MAC_ADR10_HIGH_REG = 36, ++ MAC_ADR10_LOW_REG = 37, ++ MAC_ADR11_HIGH_REG = 38, ++ MAC_ADR11_LOW_REG = 39, ++ MAC_ADR12_HIGH_REG = 40, ++ MAC_ADR12_LOW_REG = 41, ++ MAC_ADR13_HIGH_REG = 42, ++ MAC_ADR13_LOW_REG = 43, ++ MAC_ADR14_HIGH_REG = 44, ++ MAC_ADR14_LOW_REG = 45, ++ MAC_ADR15_HIGH_REG = 46, ++ MAC_ADR15_LOW_REG = 47 ++} gmac_mac_regs_t; ++ ++ ++/** ++ * MAC register field definitions ++ */ ++typedef enum gmac_config_reg { ++ MAC_CONFIG_WD_BIT = 23, ++ MAC_CONFIG_JD_BIT = 22, ++ MAC_CONFIG_BE_BIT = 21, ++ MAC_CONFIG_JE_BIT = 20, ++ MAC_CONFIG_IFG_BIT = 17, ++ MAC_CONFIG_PS_BIT = 15, ++ MAC_CONFIG_DO_BIT = 13, ++ MAC_CONFIG_LM_BIT = 12, ++ MAC_CONFIG_DM_BIT = 11, ++ MAC_CONFIG_IPC_BIT = 10, ++ MAC_CONFIG_DR_BIT = 9, ++ MAC_CONFIG_ACS_BIT = 7, ++ MAC_CONFIG_BL_BIT = 5, ++ MAC_CONFIG_DC_BIT = 4, ++ MAC_CONFIG_TE_BIT = 3, ++ MAC_CONFIG_RE_BIT = 2 ++} gmac_config_reg_t; ++ ++#define MAC_CONFIG_IFG_NUM_BITS 3 ++#define MAC_CONFIG_BL_NUM_BITS 2 ++ ++typedef enum gmac_frame_filter_reg { ++ MAC_FRAME_FILTER_RA_BIT = 31, ++ MAC_FRAME_FILTER_SAF_BIT = 9, ++ MAC_FRAME_FILTER_SAIF_BIT = 8, ++ MAC_FRAME_FILTER_PCF_BIT = 6, ++ MAC_FRAME_FILTER_DBF_BIT = 5, ++ MAC_FRAME_FILTER_PM_BIT = 4, ++ MAC_FRAME_FILTER_DAIF_BIT = 3, ++ MAC_FRAME_FILTER_HMC_BIT = 2, ++ MAC_FRAME_FILTER_HUC_BIT = 1, ++ MAC_FRAME_FILTER_PR_BIT = 0 ++} gmac_frame_filter_reg_t; ++ ++#define MAC_FRAME_FILTER_PCF_NUM_BITS 2 ++ ++typedef enum gmac_hash_table_high_reg { ++ MAC_HASH_HIGH_HTH_BIT = 0 ++} gmac_hash_table_high_reg_t; ++ ++typedef enum gmac_hash_table_low_reg { ++ MAC_HASH_LOW_HTL_BIT = 0 ++} gmac_hash_table_low_reg_t; ++ ++typedef enum gmac_gmii_address_reg { ++ MAC_GMII_ADR_PA_BIT = 11, ++ MAC_GMII_ADR_GR_BIT = 6, ++ MAC_GMII_ADR_CR_BIT = 2, ++ MAC_GMII_ADR_GW_BIT = 1, ++ MAC_GMII_ADR_GB_BIT = 0 ++} gmac_gmii_address_reg_t; ++ ++#define MAC_GMII_ADR_PA_NUM_BITS 5 ++#define MAC_GMII_ADR_GR_NUM_BITS 5 ++#define MAC_GMII_ADR_CR_NUM_BITS 3 ++ ++typedef enum gmac_gmii_data_reg { ++ MAC_GMII_DATA_GD_BIT = 0 ++} gmac_gmii_data_reg_t; ++ ++#define MAC_GMII_DATA_GD_NUM_BITS 16 ++ ++typedef enum gmac_flow_control_reg { ++ MAC_FLOW_CNTL_PT_BIT = 16, ++ MAC_FLOW_CNTL_PLT_BIT = 4, ++ MAC_FLOW_CNTL_UP_BIT = 3, ++ MAC_FLOW_CNTL_RFE_BIT = 2, ++ MAC_FLOW_CNTL_TFE_BIT = 1, ++ MAC_FLOW_CNTL_FCB_BPA_BIT = 0 ++} gmac_flow_control_reg_t; ++ ++#define MAC_FLOW_CNTL_PT_NUM_BITS 16 ++#define MAC_FLOW_CNTL_PLT_NUM_BITS 2 ++ ++typedef enum gmac_vlan_tag_reg { ++ MAC_VLAN_TAG_LV_BIT = 0 ++} gmac_vlan_tag_reg_t; ++ ++#define MAC_VLAN_TAG_LV_NUM_BITS 16 ++ ++typedef enum gmac_version_reg { ++ MAC_VERSION_UD_BIT = 8, ++ MAC_VERSION_SD_BIT = 0 ++} gmac_version_reg_t; ++ ++#define MAC_VERSION_UD_NUM_BITS 8 ++#define MAC_VERSION_SD_NUM_BITS 8 ++ ++typedef enum gmac_mac_adr_0_high_reg { ++ MAC_ADR0_HIGH_MO_BIT = 31, ++ MAC_ADR0_HIGH_A_BIT = 0 ++} gmac_mac_adr_0_high_reg_t; ++ ++#define MAC_ADR0_HIGH_A_NUM_BITS 16 ++ ++typedef enum gmac_mac_adr_0_low_reg { ++ MAC_ADR0_LOW_A_BIT = 0 ++} gmac_mac_adr_0_low_reg_t; ++ ++typedef enum gmac_mac_adr_1_high_reg { ++ MAC_ADR1_HIGH_AE_BIT = 31, ++ MAC_ADR1_HIGH_SA_BIT = 30, ++ MAC_ADR1_HIGH_MBC_BIT = 24, ++ MAC_ADR1_HIGH_A_BIT = 0 ++} gmac_mac_adr_1_high_reg_t; ++ ++#define MAC_ADR1_HIGH_MBC_NUM_BITS 6 ++#define MAC_ADR1_HIGH_A_NUM_BITS 16 ++ ++typedef enum gmac_mac_adr_1_low_reg { ++ MAC_ADR1_LOW_A_BIT = 0 ++} gmac_mac_adr_1_low_reg_t; ++ ++ ++/** ++ * MMC register indices - registers accessed via the MAC accessor functions ++ */ ++typedef enum gmac_mmc_regs { ++ MMC_CONTROL_REG = 64, ++ MMC_RX_INT_REG = 65, ++ MMC_TX_INT_REG = 66, ++ MMC_RX_MASK_REG = 67, ++ MMC_TX_MASK_REG = 68 ++} gmac_mmc_regs_t; ++ ++/** ++ * DMA register indices ++ */ ++typedef enum gmac_dma_regs { ++ DMA_BUS_MODE_REG = 0, ++ DMA_TX_POLL_REG = 1, ++ DMA_RX_POLL_REG = 2, ++ DMA_RX_DESC_ADR_REG = 3, ++ DMA_TX_DESC_ADR_REG = 4, ++ DMA_STATUS_REG = 5, ++ DMA_OP_MODE_REG = 6, ++ DMA_INT_ENABLE_REG = 7, ++ DMA_MISSED_OVERFLOW_REG = 8, ++ DMA_CUR_TX_DESC_REG = 18, ++ DMA_CUR_RX_DESC_REG = 19, ++ DMA_CUR_TX_ADR_REG = 20, ++ DMA_CUR_RX_ADR_REG = 21 ++} gmac_dma_regs_t; ++ ++/** ++ * DMA register field definitions ++ */ ++ ++typedef enum gmac_dma_bus_mode_reg { ++ DMA_BUS_MODE_FB_BIT = 16, ++ DMA_BUS_MODE_PR_BIT = 14, ++ DMA_BUS_MODE_PBL_BIT = 8, ++ DMA_BUS_MODE_DSL_BIT = 2, ++ DMA_BUS_MODE_DA_BIT = 1, ++ DMA_BUS_MODE_SWR_BIT = 0 ++} gmac_dma_bus_mode_reg_t; ++ ++#define DMA_BUS_MODE_PR_NUM_BITS 2 ++#define DMA_BUS_MODE_PBL_NUM_BITS 6 ++#define DMA_BUS_MODE_DSL_NUM_BITS 5 ++ ++typedef enum gmac_dma_tx_poll_demand_reg { ++ DMA_TX_POLL_TPD_BIT = 0 ++} gmac_dma_tx_poll_demand_reg_t; ++ ++typedef enum gmac_dma_rx_poll_demand_reg { ++ DMA_RX_POLL_RPD_BIT = 0 ++} gmac_dma_rx_poll_demand_reg_t; ++ ++typedef enum gmac_dma_rx_desc_list_adr_reg { ++ DMA_RX_DESC_ADR_SRL_BIT = 0 ++} gmac_dma_rx_desc_list_adr_reg_t; ++ ++typedef enum gmac_dma_tx_desc_list_adr_reg { ++ DMA_TX_DESC_ADR_STL_BIT = 0 ++} gmac_dma_tx_desc_list_adr_reg_t; ++ ++typedef enum gmac_dma_status_reg { ++ DMA_STATUS_GPI_BIT = 28, ++ DMA_STATUS_GMI_BIT = 27, ++ DMA_STATUS_GLI_BIT = 26, ++ DMA_STATUS_EB_BIT = 23, ++ DMA_STATUS_TS_BIT = 20, ++ DMA_STATUS_RS_BIT = 17, ++ DMA_STATUS_NIS_BIT = 16, ++ DMA_STATUS_AIS_BIT = 15, ++ DMA_STATUS_ERI_BIT = 14, ++ DMA_STATUS_FBE_BIT = 13, ++ DMA_STATUS_ETI_BIT = 10, ++ DMA_STATUS_RWT_BIT = 9, ++ DMA_STATUS_RPS_BIT = 8, ++ DMA_STATUS_RU_BIT = 7, ++ DMA_STATUS_RI_BIT = 6, ++ DMA_STATUS_UNF_BIT = 5, ++ DMA_STATUS_OVF_BIT = 4, ++ DMA_STATUS_TJT_BIT = 3, ++ DMA_STATUS_TU_BIT = 2, ++ DMA_STATUS_TPS_BIT = 1, ++ DMA_STATUS_TI_BIT = 0 ++} gmac_dma_status_reg_t; ++ ++#define DMA_STATUS_EB_NUM_BITS 3 ++#define DMA_STATUS_TS_NUM_BITS 3 ++#define DMA_STATUS_RS_NUM_BITS 3 ++ ++typedef enum gmac_dma_op_mode_reg { ++ DMA_OP_MODE_SF_BIT = 21, ++ DMA_OP_MODE_FTF_BIT = 20, ++ DMA_OP_MODE_TTC_BIT = 14, ++ DMA_OP_MODE_ST_BIT = 13, ++ DMA_OP_MODE_RFD_BIT = 11, ++ DMA_OP_MODE_RFA_BIT = 9, ++ DMA_OP_MODE_EFC_BIT = 8, ++ DMA_OP_MODE_FEF_BIT = 7, ++ DMA_OP_MODE_FUF_BIT = 6, ++ DMA_OP_MODE_RTC_BIT = 3, ++ DMA_OP_MODE_OSF_BIT = 2, ++ DMA_OP_MODE_SR_BIT = 1 ++} gmac_dma_op_mode_reg_t; ++ ++#define DMA_OP_MODE_TTC_NUM_BITS 3 ++#define DMA_OP_MODE_RFD_NUM_BITS 2 ++#define DMA_OP_MODE_RFA_NUM_BITS 2 ++#define DMA_OP_MODE_RTC_NUM_BITS 2 ++ ++typedef enum gmac_dma_intr_enable_reg { ++ DMA_INT_ENABLE_NI_BIT = 16, ++ DMA_INT_ENABLE_AI_BIT = 15, ++ DMA_INT_ENABLE_ERE_BIT = 14, ++ DMA_INT_ENABLE_FBE_BIT = 13, ++ DMA_INT_ENABLE_ETE_BIT = 10, ++ DMA_INT_ENABLE_RW_BIT = 9, ++ DMA_INT_ENABLE_RS_BIT = 8, ++ DMA_INT_ENABLE_RU_BIT = 7, ++ DMA_INT_ENABLE_RI_BIT = 6, ++ DMA_INT_ENABLE_UN_BIT = 5, ++ DMA_INT_ENABLE_OV_BIT = 4, ++ DMA_INT_ENABLE_TJ_BIT = 3, ++ DMA_INT_ENABLE_TU_BIT = 2, ++ DMA_INT_ENABLE_TS_BIT = 1, ++ DMA_INT_ENABLE_TI_BIT = 0 ++} gmac_dma_intr_enable_reg_t; ++ ++typedef enum gmac_dma_missed_overflow_reg { ++ DMA_MISSED_OVERFLOW_OFOC_BIT = 28, // Overflow bit for FIFO Overflow Counter ++ DMA_MISSED_OVERFLOW_AMFC_BIT = 17, // Application Missed Frames Count ++ DMA_MISSED_OVERFLOW_OAMFO_BIT = 16, // Overflow bit for Application Missed Frames Count ++ DMA_MISSED_OVERFLOW_CMFC_BIT = 0 // Controller Missed Frames Count ++} gmac_dma_missed_overflow_reg_t; ++ ++#define DMA_MISSED_OVERFLOW_OAMFO_NUM_BITS 11 ++#define DMA_MISSED_OVERFLOW_CMFC_NUM_BITS 16 ++ ++typedef enum gmac_dma_current_tx_desc_reg { ++ DMA_CUR_TX_DESC_A_BIT = 0 ++} gmac_dma_current_tx_desc_reg_t; ++ ++typedef enum gmac_dma_current_rx_desc_reg { ++ DMA_CUR_RX_DESC_A_BIT = 0 ++} gmac_dma_current_rx_desc_reg_t; ++ ++typedef enum gmac_dma_current_tx_adr_reg { ++ DMA_CUR_TX_ADR_A_BIT = 0 ++} gmac_dma_current_tx_adr_reg_t; ++ ++typedef enum gmac_dma_current_rx_adr_reg { ++ DMA_CUR_RX_ADR_A_BIT = 0 ++} gmac_dma_current_rx_adr_reg_t; ++ ++/** ++ * Descriptor support ++ */ ++/** Descriptor status word field definitions */ ++typedef enum desc_status { ++ descOwnByDma = 0x80000000, /* descriptor is owned by DMA engine */ ++ ++ descFrameLengthMask = 0x3FFF0000, /* Receive descriptor frame length */ ++ descFrameLengthShift = 16, ++ ++ descError = 0x00008000, /* Error summary bit - OR of the following bits: v */ ++ ++ descRxTruncated = 0x00004000, /* Rx - no more descriptors for receive frame E */ ++ ++ descRxLengthError = 0x00001000, /* Rx - frame size not matching with length field */ ++ descRxDamaged = 0x00000800, /* Rx - frame was damaged due to buffer overflow E */ ++ descRxFirst = 0x00000200, /* Rx - first descriptor of the frame */ ++ descRxLast = 0x00000100, /* Rx - last descriptor of the frame */ ++ descRxLongFrame = 0x00000080, /* Rx - frame is longer than 1518 bytes E */ ++ descRxCollision = 0x00000040, /* Rx - late collision occurred during reception E */ ++ descRxFrameEther = 0x00000020, /* Rx - Frame type - Ethernet, otherwise 802.3 */ ++ descRxWatchdog = 0x00000010, /* Rx - watchdog timer expired during reception E */ ++ descRxMiiError = 0x00000008, /* Rx - error reported by MII interface E */ ++ descRxDribbling = 0x00000004, /* Rx - frame contains noninteger multiple of 8 bits */ ++ descRxCrc = 0x00000002, /* Rx - CRC error E */ ++ ++ descTxTimeout = 0x00004000, /* Tx - Transmit jabber timeout E */ ++ descTxLostCarrier = 0x00000800, /* Tx - carrier lost during tramsmission E */ ++ descTxNoCarrier = 0x00000400, /* Tx - no carrier signal from the tranceiver E */ ++ descTxLateCollision = 0x00000200, /* Tx - transmission aborted due to collision E */ ++ descTxExcCollisions = 0x00000100, /* Tx - transmission aborted after 16 collisions E */ ++ descTxVLANFrame = 0x00000080, /* Tx - VLAN-type frame */ ++ descTxCollMask = 0x00000078, /* Tx - Collision count */ ++ descTxCollShift = 3, ++ descTxExcDeferral = 0x00000004, /* Tx - excessive deferral E */ ++ descTxUnderflow = 0x00000002, /* Tx - late data arrival from the memory E */ ++ descTxDeferred = 0x00000001, /* Tx - frame transmision deferred */ ++} desc_status_t; ++ ++/** Descriptor length word field definitions */ ++typedef enum desc_length { ++ descTxIntEnable = 0x80000000, /* Tx - interrupt on completion */ ++ descTxLast = 0x40000000, /* Tx - Last segment of the frame */ ++ descTxFirst = 0x20000000, /* Tx - First segment of the frame */ ++ descTxDisableCrc = 0x04000000, /* Tx - Add CRC disabled (first segment only) */ ++ ++ descEndOfRing = 0x02000000, /* End of descriptors ring */ ++ descChain = 0x01000000, /* Second buffer address is chain address */ ++ descTxDisablePadd = 0x00800000, /* disable padding, added by - reyaz */ ++ ++ descSize2Mask = 0x003FF800, /* Buffer 2 size */ ++ descSize2Shift = 11, ++ descSize1Mask = 0x000007FF, /* Buffer 1 size */ ++ descSize1Shift = 0, ++} desc_length_t; ++ ++typedef enum rx_desc_status { ++ RX_DESC_STATUS_OWN_BIT = 31, ++ RX_DESC_STATUS_AFM_BIT = 30, ++ RX_DESC_STATUS_FL_BIT = 16, ++ RX_DESC_STATUS_ES_BIT = 15, ++ RX_DESC_STATUS_DE_BIT = 14, ++ RX_DESC_STATUS_SAF_BIT = 13, ++ RX_DESC_STATUS_LE_BIT = 12, ++ RX_DESC_STATUS_OE_BIT = 11, ++ RX_DESC_STATUS_IPC_BIT = 10, ++ RX_DESC_STATUS_FS_BIT = 9, ++ RX_DESC_STATUS_LS_BIT = 8, ++ RX_DESC_STATUS_VLAN_BIT = 7, ++ RX_DESC_STATUS_LC_BIT = 6, ++ RX_DESC_STATUS_FT_BIT = 5, ++ RX_DESC_STATUS_RWT_BIT = 4, ++ RX_DESC_STATUS_RE_BIT = 3, ++ RX_DESC_STATUS_DRE_BIT = 2, ++ RX_DESC_STATUS_CE_BIT = 1, ++ RX_DESC_STATUS_MAC_BIT = 0 ++} rx_desc_status_t; ++ ++#define RX_DESC_STATUS_FL_NUM_BITS 14 ++ ++typedef enum rx_desc_length { ++ RX_DESC_LENGTH_DIC_BIT = 31, ++ RX_DESC_LENGTH_RER_BIT = 25, ++ RX_DESC_LENGTH_RCH_BIT = 24, ++ RX_DESC_LENGTH_RBS2_BIT = 11, ++ RX_DESC_LENGTH_RBS1_BIT = 0, ++} rx_desc_length_t; ++ ++#define RX_DESC_LENGTH_RBS2_NUM_BITS 11 ++#define RX_DESC_LENGTH_RBS1_NUM_BITS 11 ++ ++typedef enum tx_desc_status { ++ TX_DESC_STATUS_OWN_BIT = 31, ++ TX_DESC_STATUS_ES_BIT = 15, ++ TX_DESC_STATUS_JT_BIT = 14, ++ TX_DESC_STATUS_FF_BIT = 13, ++ TX_DESC_STATUS_LOC_BIT = 11, ++ TX_DESC_STATUS_NC_BIT = 10, ++ TX_DESC_STATUS_LC_BIT = 9, ++ TX_DESC_STATUS_EC_BIT = 8, ++ TX_DESC_STATUS_VF_BIT = 7, ++ TX_DESC_STATUS_CC_BIT = 3, ++ TX_DESC_STATUS_ED_BIT = 2, ++ TX_DESC_STATUS_UF_BIT = 1, ++ TX_DESC_STATUS_DB_BIT = 0 ++} tx_desc_status_t; ++ ++#define TX_DESC_STATUS_CC_NUM_BITS 4 ++ ++typedef enum tx_desc_length { ++ TX_DESC_LENGTH_IC_BIT = 31, ++ TX_DESC_LENGTH_LS_BIT = 30, ++ TX_DESC_LENGTH_FS_BIT = 29, ++ TX_DESC_LENGTH_DC_BIT = 26, ++ TX_DESC_LENGTH_TER_BIT = 25, ++ TX_DESC_LENGTH_TCH_BIT = 24, ++ TX_DESC_LENGTH_DP_BIT = 23, ++ TX_DESC_LENGTH_TBS2_BIT = 11, ++ TX_DESC_LENGTH_TBS1_BIT = 0 ++} tx_desc_length_t; ++ ++#define TX_DESC_LENGTH_TBS2_NUM_BITS 11 ++#define TX_DESC_LENGTH_TBS1_NUM_BITS 11 ++ ++/** Return the number of descriptors available for the CPU to fill with new ++ * packet info */ ++static inline int available_for_write(gmac_desc_list_info_t* desc_list) ++{ ++ return desc_list->empty_count; ++} ++ ++/** Return non-zero if there is a descriptor available with a packet with which ++ * the GMAC DMA has finished */ ++static inline int tx_available_for_read(gmac_desc_list_info_t* desc_list) ++{ ++ return desc_list->full_count && ++ !((desc_list->base_ptr + desc_list->r_index)->status & (1UL << TX_DESC_STATUS_OWN_BIT)); ++} ++ ++/** Return non-zero if there is a descriptor available with a packet with which ++ * the GMAC DMA has finished */ ++static inline int rx_available_for_read(gmac_desc_list_info_t* desc_list) ++{ ++ return desc_list->full_count && ++ !((desc_list->base_ptr + desc_list->r_index)->status & (1UL << RX_DESC_STATUS_OWN_BIT)); ++} ++ ++/** ++ * @param A u32 containing the status from a received frame's DMA descriptor ++ * @return An int which is non-zero if a valid received frame is fully contained ++ * within the descriptor from whence the status came ++ */ ++static inline int is_rx_valid(u32 status) ++{ ++ return !(status & descError) && ++ (status & descRxFirst) && ++ (status & descRxLast); ++} ++ ++static inline int is_rx_dribbling(u32 status) ++{ ++ return status & descRxDribbling; ++} ++ ++static inline u32 get_rx_length(u32 status) ++{ ++ return (status & descFrameLengthMask) >> descFrameLengthShift; ++} ++ ++static inline int is_rx_collision_error(u32 status) ++{ ++ return status & (descRxDamaged | descRxCollision); ++} ++ ++static inline int is_rx_crc_error(u32 status) ++{ ++ return status & descRxCrc; ++} ++ ++static inline int is_rx_frame_error(u32 status) ++{ ++ return status & descRxDribbling; ++} ++ ++static inline int is_rx_length_error(u32 status) ++{ ++ return status & descRxLengthError; ++} ++ ++static inline int is_rx_long_frame(u32 status) ++{ ++ return status & descRxLongFrame; ++} ++ ++static inline int is_tx_valid(u32 status) ++{ ++ return !(status & descError); ++} ++ ++static inline int is_tx_collision_error(u32 status) ++{ ++ return (status & descTxCollMask) >> descTxCollShift; ++} ++ ++static inline int is_tx_aborted(u32 status) ++{ ++ return status & (descTxLateCollision | descTxExcCollisions); ++} ++ ++static inline int is_tx_carrier_error(u32 status) ++{ ++ return status & (descTxLostCarrier | descTxNoCarrier); ++} ++ ++/** ++ * GMAC private metadata ++ */ ++static gmac_priv_t priv_data; ++static gmac_priv_t* priv = &priv_data; ++ ++/** ++ * Descriptor list management ++ */ ++ ++static void init_rx_descriptor( ++ gmac_dma_desc_t* desc, ++ int end_of_ring, ++ int disable_ioc) ++{ ++ desc->status = 0; ++ desc->length = 0; ++ if (disable_ioc) { ++ desc->length |= (1UL << RX_DESC_LENGTH_DIC_BIT); ++ } ++ if (end_of_ring) { ++ desc->length |= (1UL << RX_DESC_LENGTH_RER_BIT); ++ } ++ desc->buffer1 = 0; ++ desc->buffer2 = 0; ++ desc->skb = 0; ++} ++ ++static void init_tx_descriptor( ++ gmac_dma_desc_t* desc, ++ int end_of_ring, ++ int enable_ioc, ++ int disable_crc, ++ int disable_padding) ++{ ++ desc->status = 0; ++ desc->length = 0; ++ if (enable_ioc) { ++ desc->length |= (1UL << TX_DESC_LENGTH_IC_BIT); ++ } ++ if (disable_crc) { ++ desc->length |= (1UL << TX_DESC_LENGTH_DC_BIT); ++ } ++ if (disable_padding) { ++ desc->length |= (1UL << TX_DESC_LENGTH_DP_BIT); ++ } ++ if (end_of_ring) { ++ desc->length |= (1UL << TX_DESC_LENGTH_TER_BIT); ++ } ++ desc->buffer1 = 0; ++ desc->buffer2 = 0; ++ desc->skb = 0; ++} ++ ++static void init_rx_desc_list( ++ gmac_desc_list_info_t* desc_list, ++ gmac_dma_desc_t* base_ptr, ++ int num_descriptors) ++{ ++ int i; ++ ++ desc_list->base_ptr = base_ptr; ++ desc_list->num_descriptors = num_descriptors; ++ desc_list->empty_count = num_descriptors; ++ desc_list->full_count = 0; ++ desc_list->r_index = 0; ++ desc_list->w_index = 0; ++ ++ for (i=0; i < (num_descriptors - 1); i++) { ++ init_rx_descriptor(base_ptr + i, 0, 0); ++ } ++ init_rx_descriptor(base_ptr + i, 1, 0); ++} ++ ++static void init_tx_desc_list( ++ gmac_desc_list_info_t* desc_list, ++ gmac_dma_desc_t* base_ptr, ++ int num_descriptors) ++{ ++ int i; ++ ++ desc_list->base_ptr = base_ptr; ++ desc_list->num_descriptors = num_descriptors; ++ desc_list->empty_count = num_descriptors; ++ desc_list->full_count = 0; ++ desc_list->r_index = 0; ++ desc_list->w_index = 0; ++ ++ for (i=0; i < (num_descriptors - 1); i++) { ++ init_tx_descriptor(base_ptr + i, 0, 1, 0, 0); ++ } ++ init_tx_descriptor(base_ptr + i, 1, 1, 0, 0); ++} ++ ++static void rx_take_ownership(gmac_desc_list_info_t* desc_list) ++{ ++ int i; ++ for (i=0; i < desc_list->num_descriptors; i++) { ++ (desc_list->base_ptr + i)->status &= ~(1UL << RX_DESC_STATUS_OWN_BIT); ++ } ++} ++ ++static void tx_take_ownership(gmac_desc_list_info_t* desc_list) ++{ ++ int i; ++ for (i=0; i < desc_list->num_descriptors; i++) { ++ (desc_list->base_ptr + i)->status &= ~(1UL << TX_DESC_STATUS_OWN_BIT); ++ } ++} ++ ++static int set_tx_descriptor( ++ gmac_priv_t* priv, ++ dma_addr_t dma_address, ++ u32 length, ++ sk_buff_t* skb) ++{ ++ int index; ++ gmac_dma_desc_t* tx; ++ ++ // Are sufficicent descriptors available for writing by the CPU? ++ if (!available_for_write(&priv->tx_gmac_desc_list_info)) { ++ return -1; ++ } ++ ++ // Get the index of the next TX descriptor available for writing by the CPU ++ index = priv->tx_gmac_desc_list_info.w_index; ++ ++ // Get a pointer to the next TX descriptor available for writing by the CPU ++ tx = priv->tx_gmac_desc_list_info.base_ptr + index; ++ ++ // Initialise the TX descriptor length field for the passed single buffer, ++ // without destroying any fields we wish to be persistent ++ ++ // No chained second buffer ++ tx->length &= ~(1UL << TX_DESC_LENGTH_TCH_BIT); ++ // Single descriptor holds entire packet ++ tx->length |= ((1UL << TX_DESC_LENGTH_LS_BIT) | (1UL << TX_DESC_LENGTH_FS_BIT)); ++ // Zero the second buffer length field ++ tx->length &= ~(((1UL << TX_DESC_LENGTH_TBS2_NUM_BITS) - 1) << TX_DESC_LENGTH_TBS2_BIT); ++ // Zero the first buffer length field ++ tx->length &= ~(((1UL << TX_DESC_LENGTH_TBS1_NUM_BITS) - 1) << TX_DESC_LENGTH_TBS1_BIT); ++ // Fill in the first buffer length ++ tx->length |= (length << TX_DESC_LENGTH_TBS1_BIT); ++ ++ // Initialise the first buffer pointer to the single passed buffer ++ tx->buffer1 = dma_address; ++ ++ // Remember the socket buffer associated with the single passed buffer ++ tx->skb = (u32)skb; ++ ++ // Update the index of the next descriptor available for writing by the CPU ++ priv->tx_gmac_desc_list_info.w_index = (tx->length & (1UL << TX_DESC_LENGTH_TER_BIT)) ? 0 : index + 1; ++ ++ // make sure all memory updates are complete before releasing the GMAC on the data. ++ wmb(); ++ ++ // Hand TX descriptor to the GMAC DMA by setting the status bit. ++ tx->status = (1UL << TX_DESC_STATUS_OWN_BIT); ++ ++ // Account for the number of descriptors used to hold the new packet ++ --priv->tx_gmac_desc_list_info.empty_count; ++ ++priv->tx_gmac_desc_list_info.full_count; ++ ++ return index; ++} ++ ++static int get_tx_descriptor( ++ gmac_priv_t* priv, ++ u32* status, ++ dma_addr_t* dma_address, ++ u32* length, ++ sk_buff_t** skb) ++{ ++ int index; ++ gmac_dma_desc_t *tx; ++ ++ // Is there at least one descriptor with which the GMAC DMA has finished? ++ if (!tx_available_for_read(&priv->tx_gmac_desc_list_info)) { ++ return -1; ++ } ++ ++ // Get the index of the descriptor released the longest time ago by the ++ // GMAC DMA ++ index = priv->tx_gmac_desc_list_info.r_index; ++ ++ // Get a pointer to the descriptor released the longest time ago by the ++ // GMAC DMA ++ tx = priv->tx_gmac_desc_list_info.base_ptr + index; ++ ++ // Extract the status field ++ if (status) { ++ *status = tx->status; ++ } ++ ++ // Extract the length field - only cope with the first buffer associated ++ // with the descriptor ++ if (length) { ++ *length = (tx->length >> TX_DESC_LENGTH_TBS1_BIT) & ++ ((1UL << TX_DESC_LENGTH_TBS1_NUM_BITS) - 1); ++ } ++ ++ // Extract the pointer to the buffer containing the packet - only cope with ++ // the first buffer associated with the descriptor ++ if (dma_address) { ++ *dma_address = tx->buffer1; ++ } ++ ++ // Extract the pointer to the socket buffer associated with the packet ++ if (skb) { ++ *skb = (sk_buff_t*)(tx->skb); ++ } ++ ++ // Update the index of the next descriptor with which the GMAC DMA may have ++ // finished ++ priv->tx_gmac_desc_list_info.r_index = (tx->length & (1UL << TX_DESC_LENGTH_TER_BIT)) ? 0 : index + 1; ++ ++ // Account for the number of descriptors freed to hold new packets ++ ++priv->tx_gmac_desc_list_info.empty_count; ++ --priv->tx_gmac_desc_list_info.full_count; ++ ++ return index; ++} ++ ++int set_rx_descriptor( ++ gmac_priv_t* priv, ++ dma_addr_t dma_address, ++ u32 length, ++ sk_buff_t* skb) ++{ ++ int index; ++ gmac_dma_desc_t* rx; ++ int num_descriptors_required; ++ ++ // Currently only support using a single descriptor to describe each packet ++ // queued with the GMAc DMA ++ num_descriptors_required = 1; ++ ++ // Are sufficicent descriptors available for writing by the CPU? ++ if (available_for_write(&priv->rx_gmac_desc_list_info) < num_descriptors_required) { ++ index = -1; ++ } else { ++ // Get the index of the next RX descriptor available for writing by the CPU ++ index = priv->rx_gmac_desc_list_info.w_index; ++ ++ // Get a pointer to the next RX descriptor available for writing by the CPU ++ rx = priv->rx_gmac_desc_list_info.base_ptr + index; ++ ++ // Initialise the RX descriptor length field for the passed single buffer, ++ // without destroying any fields we wish to be persistent ++ ++ // No chained second buffer ++ rx->length &= ~(1UL << RX_DESC_LENGTH_RCH_BIT); ++ // Zero the second buffer length field ++ rx->length &= ~(((1UL << RX_DESC_LENGTH_RBS2_NUM_BITS) - 1) << RX_DESC_LENGTH_RBS2_BIT); ++ // Zero the first buffer length field ++ rx->length &= ~(((1UL << RX_DESC_LENGTH_RBS1_NUM_BITS) - 1) << RX_DESC_LENGTH_RBS1_BIT); ++ // Fill in the first buffer length ++ rx->length |= (length << RX_DESC_LENGTH_RBS1_BIT); ++ ++ // Initialise the first buffer pointer to the single passed buffer ++ rx->buffer1 = dma_address; ++ ++ // Remember the socket buffer associated with the single passed buffer ++ rx->skb = (u32)skb; ++ ++ wmb(); ++ ++ // Initialise RX descriptor status to be owned by the GMAC DMA ++ rx->status = (1UL << RX_DESC_STATUS_OWN_BIT); ++ ++ // Update the index of the next descriptor available for writing by the CPU ++ priv->rx_gmac_desc_list_info.w_index = (rx->length & (1UL << RX_DESC_LENGTH_RER_BIT)) ? 0 : index + 1; ++ ++ // Account for the number of descriptors used to hold the new packet ++ priv->rx_gmac_desc_list_info.empty_count -= num_descriptors_required; ++ priv->rx_gmac_desc_list_info.full_count += num_descriptors_required; ++ } ++ ++ return index; ++} ++ ++int get_rx_descriptor( ++ gmac_priv_t* priv, ++ u32* status, ++ dma_addr_t* dma_address, ++ u32* length, ++ sk_buff_t** skb) ++{ ++ int index; ++ gmac_dma_desc_t *rx; ++ int num_descriptors_required; ++ ++ // Is there at least one descriptor with which the GMAC DMA has finished? ++ if (!rx_available_for_read(&priv->rx_gmac_desc_list_info)) { ++ return -1; ++ } ++ ++ // Currently can only cope with packets entirely contained within a single ++ // descriptor ++ num_descriptors_required = 1; ++ ++ // Get the index of the descriptor released the longest time ago by the ++ // GMAC DMA ++ index = priv->rx_gmac_desc_list_info.r_index; ++ ++ // Get a pointer to the descriptor released the longest time ago by the ++ // GMAC DMA ++ rx = priv->rx_gmac_desc_list_info.base_ptr + index; ++ ++ // Extract the status field ++ if (status) { ++ *status = rx->status; ++ } ++ ++ // Extract the length field - only cope with the first buffer associated ++ // with the descriptor ++ if (length) { ++ *length = (rx->length >> RX_DESC_LENGTH_RBS1_BIT) & ++ ((1UL << RX_DESC_LENGTH_RBS1_NUM_BITS) - 1); ++ } ++ ++ // Extract the pointer to the buffer containing the packet - only cope with ++ // the first buffer associated with the descriptor ++ if (dma_address) { ++ *dma_address = rx->buffer1; ++ } ++ ++ // Extract the pointer to the socket buffer associated with the packet ++ if (skb) { ++ *skb = (sk_buff_t*)(rx->skb); ++ } ++ ++ wmb(); ++ // Update the index of the next descriptor with which the GMAC DMA may have ++ // finished ++ priv->rx_gmac_desc_list_info.r_index = (rx->length & (1UL << RX_DESC_LENGTH_RER_BIT)) ? 0 : index + 1; ++ ++ // Account for the number of descriptors freed to hold new packets ++ priv->rx_gmac_desc_list_info.empty_count += num_descriptors_required; ++ priv->rx_gmac_desc_list_info.full_count -= num_descriptors_required; ++ ++ return index; ++} ++ ++/** ++ * GMAC register access functions ++ */ ++ ++/** ++ * MAC register access functions ++ */ ++ ++/** ++ * @param priv A gmac_priv_t* pointing to private device data ++ * @param reg_num An int specifying the index of the MAC register to access ++ */ ++static inline u32 mac_reg_read(gmac_priv_t* priv, int reg_num) ++{ ++ return *(volatile u32*)(priv->macBase + (reg_num << 2)); ++} ++ ++/** ++ * @param priv A gmac_priv_t* pointing to private device data ++ * @param reg_num An int specifying the index of the MAC register to access ++ */ ++static inline void mac_reg_write(gmac_priv_t* priv, int reg_num, u32 value) ++{ ++ *(volatile u32*)(priv->macBase + (reg_num << 2)) = value; ++ ++} ++ ++/** ++ * @param priv A gmac_priv_t* pointing to private device data ++ * @param reg_num An int specifying the index of the MAC register to access ++ * @param bits_to_clear A u32 specifying which bits of the specified register to ++ * clear. A set bit in this parameter will cause the matching bit in the ++ * register to be cleared ++ */ ++static inline void mac_reg_clear_mask(gmac_priv_t* priv, int reg_num, u32 bits_to_clear) ++{ ++ mac_reg_write(priv, reg_num, mac_reg_read(priv, reg_num) & ~bits_to_clear); ++} ++ ++/** ++ * @param priv A gmac_priv_t* pointing to private device data ++ * @param reg_num An int specifying the index of the MAC register to access ++ * @param bits_to_set A u32 specifying which bits of the specified register to ++ * set. A set bit in this parameter will cause the matching bit in the register ++ * to be set ++ */ ++static inline void mac_reg_set_mask(gmac_priv_t* priv, int reg_num, u32 bits_to_set) ++{ ++ mac_reg_write(priv, reg_num, mac_reg_read(priv, reg_num) | bits_to_set); ++} ++ ++ ++/** ++ * DMA register access functions ++ */ ++ ++/** ++ * @param priv A gmac_priv_t* pointing to private device data ++ * @param reg_num An int specifying the index of the DMA register to access ++ */ ++static inline u32 dma_reg_read(gmac_priv_t* priv, int reg_num) ++{ ++ return *(volatile u32*)(priv->dmaBase + (reg_num << 2)); ++} ++ ++/** ++ * @param priv A gmac_priv_t* pointing to private device data ++ * @param reg_num An int specifying the index of the DMA register to access ++ */ ++static inline void dma_reg_write(gmac_priv_t* priv, int reg_num, u32 value) ++{ ++ *(volatile u32*)(priv->dmaBase + (reg_num << 2)) = value; ++ wmb(); ++} ++ ++/** ++ * @param priv A gmac_priv_t* pointing to private device data ++ * @param reg_num An int specifying the index of the DMA register to access ++ * @param bits_to_clear A u32 specifying which bits of the specified register to ++ * clear. A set bit in this parameter will cause the matching bit in the ++ * register to be cleared ++ * @return An u32 containing the new value written to the register ++ */ ++static inline u32 dma_reg_clear_mask(gmac_priv_t* priv, int reg_num, u32 bits_to_clear) ++{ ++ u32 new_value = dma_reg_read(priv, reg_num) & ~bits_to_clear; ++ dma_reg_write(priv, reg_num, new_value); ++ return new_value; ++} ++ ++/** ++ * @param priv A gmac_priv_t* pointing to private device data ++ * @param reg_num An int specifying the index of the DMA register to access ++ * @param bits_to_set A u32 specifying which bits of the specified register to ++ * set. A set bit in this parameter will cause the matching bit in the register ++ * to be set ++ * @return An u32 containing the new value written to the register ++ */ ++static inline u32 dma_reg_set_mask(gmac_priv_t* priv, int reg_num, u32 bits_to_set) ++{ ++ u32 new_value = dma_reg_read(priv, reg_num) | bits_to_set; ++ dma_reg_write(priv, reg_num, new_value); ++ return new_value; ++} ++ ++static void eth_down(void) ++{ ++ // Stop transmitter, take ownership of all tx descriptors ++ dma_reg_clear_mask(priv, DMA_OP_MODE_REG, DMA_OP_MODE_ST_BIT); ++ if (priv->desc_base_addr) { ++ tx_take_ownership(&priv->tx_gmac_desc_list_info); ++ } ++ ++ // Stop receiver, take ownership of all rx descriptors ++ dma_reg_clear_mask(priv, DMA_OP_MODE_REG, DMA_OP_MODE_SR_BIT); ++ if (priv->desc_base_addr) { ++ rx_take_ownership(&priv->rx_gmac_desc_list_info); ++ } ++ ++ // Free descriptor resources. The TX descriptor will not have a packet ++ // buffer attached, as this is provided by the stack when transmission is ++ // required and ownership is not retained by the descriptor, as the stack ++ // waits for transmission to complete via polling ++ if (priv->desc_base_addr) { ++ // Free receive descriptors, accounting for buffer offset used to ++ // ensure IP header alignment ++ while (1) { ++ dma_addr_t dma_address; ++ if (get_rx_descriptor(priv, 0, &dma_address, 0, 0) < 0) { ++ break; ++ } ++ free((void*)(dma_address - ETHER_FRAME_ALIGN_WASTAGE)); ++ } ++ ++ // Free DMA descriptors' storage ++ free(priv->desc_base_addr); ++ ++ // Remember that we've freed the descriptors memory ++ priv->desc_base_addr = 0; ++ } ++} ++ ++/* ++ * Reads a register from the MII Management serial interface ++ */ ++int phy_read(int phyaddr, int phyreg) ++{ ++ int data = 0; ++ u32 addr = (phyaddr << MAC_GMII_ADR_PA_BIT) | ++ (phyreg << MAC_GMII_ADR_GR_BIT) | ++ (5 << MAC_GMII_ADR_CR_BIT) | ++ (1UL << MAC_GMII_ADR_GB_BIT); ++ ++ mac_reg_write(priv, MAC_GMII_ADR_REG, addr); ++ ++ for (;;) { ++ if (!(mac_reg_read(priv, MAC_GMII_ADR_REG) & (1UL << MAC_GMII_ADR_GB_BIT))) { ++ // Successfully read from PHY ++ data = mac_reg_read(priv, MAC_GMII_DATA_REG) & 0xFFFF; ++ break; ++ } ++ } ++ ++#ifdef DEBUG_GMAC_INIT ++ printf("phy_read() phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", phyaddr, phyreg, data); ++#endif // DEBUG_GMAC_INIT ++ ++ return data; ++} ++ ++/* ++ * Writes a register to the MII Management serial interface ++ */ ++void phy_write(int phyaddr, int phyreg, int phydata) ++{ ++ u32 addr = (phyaddr << MAC_GMII_ADR_PA_BIT) | ++ (phyreg << MAC_GMII_ADR_GR_BIT) | ++ (5 << MAC_GMII_ADR_CR_BIT) | ++ (1UL << MAC_GMII_ADR_GW_BIT) | ++ (1UL << MAC_GMII_ADR_GB_BIT); ++ ++ mac_reg_write(priv, MAC_GMII_DATA_REG, phydata); ++ mac_reg_write(priv, MAC_GMII_ADR_REG, addr); ++ ++ for (;;) { ++ if (!(mac_reg_read(priv, MAC_GMII_ADR_REG) & (1UL << MAC_GMII_ADR_GB_BIT))) { ++ break; ++ } ++ } ++ ++#ifdef DEBUG_GMAC_INIT ++ printf("phy_write() phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", phyaddr, phyreg, phydata); ++#endif // DEBUG_GMAC_INIT ++} ++ ++/* ++ * Finds and reports the PHY address ++ */ ++int phy_detect(void) ++{ ++ int found = 0; ++ int phyaddr; ++ ++ // Scan all 32 PHY addresses if necessary ++ priv->phy_type = 0; ++ for (phyaddr = 1; phyaddr < 33; ++phyaddr) { ++ unsigned int id1, id2; ++ ++ // Read the PHY identifiers ++ id1 = phy_read(phyaddr & 31, MII_PHYSID1); ++ id2 = phy_read(phyaddr & 31, MII_PHYSID2); ++ ++#ifdef DEBUG_GMAC_INIT ++ printf("phy_detect() PHY adr = %u -> phy_id1=0x%x, phy_id2=0x%x\n", phyaddr, id1, id2); ++#endif // DEBUG_GMAC_INIT ++ ++ // Make sure it is a valid identifier ++ if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && ++ id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { ++#ifdef DEBUG_GMAC_INIT ++ printf("phy_detect() Found PHY at address = %u\n", phyaddr); ++#endif // DEBUG_GMAC_INIT ++ ++ priv->phy_id = phyaddr & 31; ++ priv->phy_type = id1 << 16 | id2; ++ priv->phy_addr = phyaddr; ++ ++ found = 1; ++ break; ++ } ++ } ++ ++ return found; ++} ++ ++void start_phy_reset(void) ++{ ++ // Ask the PHY to reset ++ phy_write(priv->phy_addr, MII_BMCR, BMCR_RESET); ++} ++ ++int is_phy_reset_complete(void) ++{ ++ int complete = 0; ++ int bmcr; ++ ++ // Read back the status until it indicates reset, or we timeout ++ bmcr = phy_read(priv->phy_addr, MII_BMCR); ++ if (!(bmcr & BMCR_RESET)) { ++ complete = 1; ++ } ++ ++ return complete; ++} ++ ++void set_phy_type_rgmii(void) ++{ ++ // Use sysctrl to switch MAC link lines into either (G)MII or RGMII mode ++ *(volatile u32*)SYS_CTRL_GMAC_CTRL |= (1UL << SYS_CTRL_GMAC_RGMII); ++} ++ ++void phy_initialise(void) ++{ ++ switch (priv->phy_type) { ++ case PHY_TYPE_VITESSE_VSC8201XVZ: ++ { ++ // Allow s/w to override mode/duplex pin settings ++ u32 acsr = phy_read(priv->phy_id, VSC8201_MII_ACSR); ++ ++ printf("PHY is Vitesse VSC8201XVZ\n"); ++ acsr |= (1UL << VSC8201_MII_ACSR_MDPPS_BIT); ++ phy_write(priv->phy_id, VSC8201_MII_ACSR, acsr); ++ } ++ break; ++ case PHY_TYPE_REALTEK_RTL8211BGR: ++ printf("PHY is Realtek RTL8211BGR\n"); ++ set_phy_type_rgmii(); ++ break; ++ case PHY_TYPE_LSI_ET1011C: ++ { ++ u32 phy_reg; ++ ++ printf("PHY is LSI ET1011C\n"); ++ ++ // Configure clocks ++ phy_reg = phy_read(priv->phy_id, ET1011C_MII_CONFIG); ++ phy_reg &= ~(((1UL << ET1011C_MII_CONFIG_IFMODESEL_NUM_BITS) - 1) << ET1011C_MII_CONFIG_IFMODESEL); ++ phy_reg |= (ET1011C_MII_CONFIG_IFMODESEL_GMII_MII << ET1011C_MII_CONFIG_IFMODESEL); ++ phy_reg |= ((1UL << ET1011C_MII_CONFIG_SYSCLKEN) | ++ (1UL << ET1011C_MII_CONFIG_TXCLKEN) | ++ (1UL << ET1011C_MII_CONFIG_TBI_RATESEL) | ++ (1UL << ET1011C_MII_CONFIG_CRS_TX_EN)); ++ phy_write(priv->phy_id, ET1011C_MII_CONFIG, phy_reg); ++ ++ // Enable Tx/Rx LED ++ phy_reg = phy_read(priv->phy_id, ET1011C_MII_LED2); ++ phy_reg &= ~(((1UL << ET1011C_MII_LED2_LED_NUM_BITS) - 1) << ET1011C_MII_LED2_LED_TXRX); ++ phy_reg |= (ET1011C_MII_LED2_LED_TXRX_ACTIVITY << ET1011C_MII_LED2_LED_TXRX); ++ phy_write(priv->phy_id, ET1011C_MII_LED2, phy_reg); ++ } ++ break; ++ } ++} ++ ++int detect_link_speed(void) ++{ ++ u32 lpa2 = phy_read(priv->phy_id, MII_STAT1000); ++ ++ if (((lpa2 & LPA_1000FULL)) || ++ ((lpa2 & LPA_1000HALF))) { ++ priv->link_is_1000M = 1; ++ } else { ++ priv->link_is_1000M = 0; ++ } ++ ++ return 0; ++} ++ ++int is_autoneg_complete(void) ++{ ++ return phy_read(priv->phy_addr, MII_BMSR) & BMSR_ANEGCOMPLETE; ++} ++ ++int is_link_ok(void) ++{ ++ return phy_read(priv->phy_id, MII_BMSR) & BMSR_LSTATUS; ++} ++ ++int eth_init(bd_t *bd) ++{ ++ u32 version; ++ u32 reg_contents; ++ u8 *mac_addr; ++ int desc; ++ ++ // Set hardware device base addresses ++ priv->macBase = (MAC_BASE_PA + MAC_BASE_OFFSET); ++ priv->dmaBase = (MAC_BASE_PA + DMA_BASE_OFFSET); ++ ++#ifdef DEBUG_GMAC_INIT ++ printf("eth_init(): About to reset MAC core\n"); ++#endif // DEBUG_GMAC_INIT ++ // Ensure the MAC block is properly reset ++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_MAC_BIT); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_MAC_BIT); ++ ++ // Enable the clock to the MAC block ++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_MAC_BIT); ++ ++ version = mac_reg_read(priv, MAC_VERSION_REG); ++#ifdef DEBUG_GMAC_INIT ++ printf("eth_init(): GMAC Synopsis version = 0x%x, vendor version = 0x%x\n", version & 0xff, (version >> 8) & 0xff); ++#endif // DEBUG_GMAC_INIT ++ ++ // Use simple mux for 25/125 Mhz clock switching ++ *(volatile u32*)SYS_CTRL_GMAC_CTRL |= (1UL << SYS_CTRL_GMAC_SIMPLE_MAX); ++ ++ // Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY ++ *(volatile u32*)SYS_CTRL_GMAC_CTRL |= (1UL << SYS_CTRL_GMAC_CKEN_GTX); ++ ++ // Disable all GMAC interrupts ++ dma_reg_write(priv, DMA_INT_ENABLE_REG, 0); ++ ++ // Reset the entire GMAC ++ dma_reg_write(priv, DMA_BUS_MODE_REG, 1UL << DMA_BUS_MODE_SWR_BIT); ++ ++ // Wait for the reset operation to complete ++ printf("Wait GMAC to reset"); ++ while (dma_reg_read(priv, DMA_BUS_MODE_REG) & (1UL << DMA_BUS_MODE_SWR_BIT)) { ++ udelay(250000); ++ printf("."); ++ } ++ printf("\n"); ++ ++ // Attempt to discover link speed from the PHY ++ if (!phy_detect()) { ++ printf("No PHY found\n"); ++ } else { ++ // Ensure the PHY is in a sensible state by resetting it ++ start_phy_reset(); ++ ++ // Read back the status until it indicates reset, or we timeout ++ printf("Wait for PHY reset"); ++ while (!is_phy_reset_complete()) { ++ udelay(250000); ++ printf("."); ++ } ++ printf("\n"); ++ ++ // Setup the PHY based on its type ++ phy_initialise(); ++ ++ printf("Wait for link to come up"); ++ while (!is_link_ok()) { ++ udelay(250000); ++ printf("."); ++ } ++ printf("Link up\n"); ++ ++ // Wait for PHY to have completed autonegotiation ++ printf("Wait for auto-negotiation to complete"); ++ while (!is_autoneg_complete()) { ++ udelay(250000); ++ printf("."); ++ } ++ printf("\n"); ++ ++ // Interrogate the PHY for the link speed ++ if (detect_link_speed()) { ++ printf("Failed to detect link speed\n"); ++ } else { ++ printf("Link is %s\n", priv->link_is_1000M ? "1000M" : "10M/100M"); ++ } ++ } ++ ++ // Form the MAC config register contents ++ reg_contents = 0; ++ if (!priv->link_is_1000M) { ++ reg_contents |= (1UL << MAC_CONFIG_PS_BIT); // Gigabit ++ } ++ reg_contents |= (1UL << MAC_CONFIG_DM_BIT); // Full duplex ++ reg_contents |= ((1UL << MAC_CONFIG_TE_BIT) | ++ (1UL << MAC_CONFIG_RE_BIT)); ++ mac_reg_write(priv, MAC_CONFIG_REG, reg_contents); ++ ++ // Form the MAC frame filter register contents ++ reg_contents = 0; ++ mac_reg_write(priv, MAC_FRAME_FILTER_REG, reg_contents); ++ ++ // Form the hash table registers contents ++ mac_reg_write(priv, MAC_HASH_HIGH_REG, 0); ++ mac_reg_write(priv, MAC_HASH_LOW_REG, 0); ++ ++ // Form the MAC flow control register contents ++ reg_contents = 0; ++ reg_contents |= ((1UL << MAC_FLOW_CNTL_RFE_BIT) | ++ (1UL << MAC_FLOW_CNTL_TFE_BIT)); ++ mac_reg_write(priv, MAC_FLOW_CNTL_REG, reg_contents); ++ ++ // Form the MAC VLAN tag register contents ++ reg_contents = 0; ++ mac_reg_write(priv, MAC_VLAN_TAG_REG, reg_contents); ++ ++ // Form the MAC addr0 high and low registers contents from the character ++ // string representation from the environment ++ mac_addr = getenv("ethaddr"); ++#ifdef DEBUG_GMAC_INIT ++ printf("eth_init(): Mac addr = %s\n", mac_addr); ++#endif // DEBUG_GMAC_INIT ++ reg_contents = simple_strtoul(mac_addr+0, 0, 16); ++ reg_contents |= (simple_strtoul(mac_addr+3, 0, 16) << 8); ++ reg_contents |= (simple_strtoul(mac_addr+6, 0, 16) << 16); ++ reg_contents |= (simple_strtoul(mac_addr+9, 0, 16) << 24); ++ mac_reg_write(priv, MAC_ADR0_LOW_REG, reg_contents); ++ reg_contents = simple_strtoul(mac_addr+12, 0, 16); ++ reg_contents |= (simple_strtoul(mac_addr+15, 0, 16) << 8); ++ mac_reg_write(priv, MAC_ADR0_HIGH_REG, reg_contents); ++ ++ // Disable all MMC interrupt sources ++ mac_reg_write(priv, MMC_RX_MASK_REG, ~0UL); ++ mac_reg_write(priv, MMC_TX_MASK_REG, ~0UL); ++ ++ // Remember how large the unified descriptor array is to be ++ priv->total_num_descriptors = NUM_RX_DMA_DESCRIPTORS + NUM_TX_DMA_DESCRIPTORS; ++ ++ // Need a consistent DMA mapping covering all the memory occupied by DMA ++ // unified descriptor array, as both CPU and DMA engine will be reading and ++ // writing descriptor fields. ++ priv->desc_base_addr = (gmac_dma_desc_t*)malloc(sizeof(gmac_dma_desc_t) * priv->total_num_descriptors); ++ if (!priv->desc_base_addr) { ++ printf("eth_init(): Failed to allocate memory for DMA descriptors\n"); ++ goto err_out; ++ } ++ ++ // Initialise the structures managing the TX descriptor list ++ init_tx_desc_list(&priv->tx_gmac_desc_list_info, ++ priv->desc_base_addr, ++ NUM_TX_DMA_DESCRIPTORS); ++ ++ // Initialise the structures managing the RX descriptor list ++ init_rx_desc_list(&priv->rx_gmac_desc_list_info, ++ priv->desc_base_addr + NUM_TX_DMA_DESCRIPTORS, ++ priv->total_num_descriptors - NUM_TX_DMA_DESCRIPTORS); ++ ++ // Prepare receive descriptors ++ desc = 0; ++ while (available_for_write(&priv->rx_gmac_desc_list_info)) { ++ // Allocate a new buffer for the descriptor which is large enough for ++ // any packet received from the link ++ dma_addr_t dma_address = (dma_addr_t)malloc(ETHER_MTU + ETHER_FRAME_ALIGN_WASTAGE + EXTRA_RX_SKB_SPACE); ++ if (!dma_address) { ++ printf("eth_init(): No memory for socket buffer\n"); ++ break; ++ } ++ ++ desc = set_rx_descriptor(priv, ++ dma_address + ETHER_FRAME_ALIGN_WASTAGE, ++ ETHER_MTU + EXTRA_RX_SKB_SPACE, ++ 0); ++ ++ if (desc < 0) { ++ // Release the buffer ++ free((void*)dma_address); ++ ++ printf("eth_init(): Error, no RX descriptor available\n"); ++ goto err_out; ++ } ++ } ++ ++ // Initialise the GMAC DMA bus mode register ++ dma_reg_write(priv, DMA_BUS_MODE_REG, ((0UL << DMA_BUS_MODE_FB_BIT) | ++ (0UL << DMA_BUS_MODE_PR_BIT) | ++ (32UL << DMA_BUS_MODE_PBL_BIT) | // AHB burst size ++ (1UL << DMA_BUS_MODE_DSL_BIT) | ++ (0UL << DMA_BUS_MODE_DA_BIT))); ++ ++ // Write the address of the start of the tx descriptor array ++ dma_reg_write(priv, DMA_TX_DESC_ADR_REG, (u32)priv->desc_base_addr); ++ ++ // Write the address of the start of the rx descriptor array ++ dma_reg_write(priv, DMA_RX_DESC_ADR_REG, ++ (u32)(priv->desc_base_addr + priv->tx_gmac_desc_list_info.num_descriptors)); ++ ++ // Clear any pending interrupt requests ++ dma_reg_write(priv, DMA_STATUS_REG, dma_reg_read(priv, DMA_STATUS_REG)); ++ ++ // Initialise the GMAC DMA operation mode register, starting both the ++ // transmitter and receiver ++ dma_reg_write(priv, DMA_OP_MODE_REG, ((1UL << DMA_OP_MODE_SF_BIT) | // Store and forward ++ (0UL << DMA_OP_MODE_TTC_BIT) | // Tx threshold ++ (1UL << DMA_OP_MODE_ST_BIT) | // Enable transmitter ++ (0UL << DMA_OP_MODE_RTC_BIT) | // Rx threshold ++ (1UL << DMA_OP_MODE_SR_BIT))); // Enable receiver ++ ++ // Success ++ return 1; ++ ++err_out: ++ eth_down(); ++ ++ return 0; ++} ++ ++void eth_halt(void) ++{ ++ eth_down(); ++ ++ // Disable the clock to the MAC block ++ *(volatile u32*)(SYS_CTRL_CKEN_CLR_CTRL) = (1UL << SYS_CTRL_CKEN_MAC_BIT); ++} ++ ++int eth_rx(void) ++{ ++ static const int MAX_LOOPS = 2000; // 2 seconds ++ ++ int length = 0; ++ dma_addr_t dma_address; ++ u32 desc_status; ++ int loops = 0; ++ ++ // Look for the first available received packet ++ while (loops++ < MAX_LOOPS) { ++ if (get_rx_descriptor(priv, &desc_status, &dma_address, 0, 0) >= 0) { ++ if (is_rx_valid(desc_status)) { ++ // Get the length of the packet within the buffer ++ length = get_rx_length(desc_status); ++ ++ // Pass packet up the network stack - will block until processing is ++ // completed ++ NetReceive((uchar*)dma_address, length); ++ } else { ++ printf("eth_rx() Received packet has bad desc_status = 0x%08x\n", desc_status); ++ } ++ ++ // Re-initialise the RX descriptor with its buffer - relies on always ++ // setting an RX descriptor directly after getting it ++ if (set_rx_descriptor(priv, dma_address, ETHER_MTU + EXTRA_RX_SKB_SPACE, 0) < 0) { ++ printf("eth_rx(): Failed to set RX descriptor\n"); ++ } ++ ++ break; ++ } ++ ++ // Wait a bit before trying again to get a descriptor ++ udelay(1000); // 1mS ++ } ++ ++ return length; ++} ++ ++int eth_send(volatile void *packet, int length) ++{ ++ // Transmit the new packet ++ while (1) { ++ // Get the TX descriptor ++ if (set_tx_descriptor(priv, (dma_addr_t)packet, length, 0) >= 0) { ++ // Tell the GMAC to poll for the updated descriptor ++ dma_reg_write(priv, DMA_TX_POLL_REG, 0); ++ break; ++ } ++ ++ // Wait a bit before trying again to get a descriptor ++ udelay(1000); // 1mS ++ } ++ ++ // Wait for the packet buffer to be finished with ++ while (get_tx_descriptor(priv, 0, 0, 0, 0) < 0) { ++ // Wait a bit before examining the descriptor again ++ udelay(1000); // 1mS ++ } ++ ++ return length; ++} ++ +diff -Nurd u-boot-2009.03.orig/board/hipox/hipox.c u-boot-2009.03/board/hipox/hipox.c +--- u-boot-2009.03.orig/board/hipox/hipox.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/hipox.c 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,385 @@ ++/* ++ * (C) Copyright 2005 ++ * Oxford Semiconductor Ltd ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <asm/io.h> ++ ++#if defined(CONFIG_SHOW_BOOT_PROGRESS) ++void show_boot_progress(int progress) ++{ ++ printf("Boot reached stage %d\n", progress); ++} ++#endif ++ ++static inline void delay(unsigned long loops) ++{ ++ __asm__ volatile ("1:\n" ++ "subs %0, %1, #1\n" ++ "bne 1b":"=r" (loops):"0" (loops)); ++} ++ ++/* ++ * Miscellaneous platform dependent initialisations ++ */ ++ ++/** Expected Intel 28F320B3T CFI info */ ++// mfr_id: MANUFACTURER_INTEL, -> 0x0089 ++// dev_id: I28F320B3T, -> 0x8896 ++// name: "Intel 28F320B3T", ++// DevSize: SIZE_4MiB, -> 22 ++// CmdSet: P_ID_INTEL_STD, -> 0x0003 ++// NumEraseRegions: 2, ++// regions: { -> #define ERASEINFO(size,blocks) (size<<8)|(blocks-1) ++// ERASEINFO(0x10000, 63), ++// ERASEINFO(0x02000, 8), ++// } ++ ++#define FLASH_WORD_SIZE unsigned short ++ ++int board_init(void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ gd->bd->bi_arch_number = MACH_TYPE_HIPOX; ++ gd->bd->bi_boot_params = PHYS_SDRAM_1_PA + 0x100; ++ gd->flags = 0; ++ ++ icache_enable(); ++ ++ /* Block reset Static core */ ++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_STATIC_BIT); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_STATIC_BIT); ++ ++ /* Enable clock to Static core */ ++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_STATIC_BIT); ++ ++#ifdef CONFIG_HIPOX_ENABLE_PCI ++ /* Block reset PCI core */ ++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_PCI_BIT); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_PCI_BIT); ++ ++ /* Enable clock to PCI core */ ++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_PCI_BIT); ++#endif // CONFIG_HIPOX_ENABLE_PCI ++ ++#ifdef CONFIG_HIPOX_MANUAL_STATIC_ARBITRATION ++ /* Assert manual static bus PCI arbitration request */ ++ *(volatile u32*)SYS_CTRL_PCI_CTRL1 |= (1UL << SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT); ++#endif // CONFIG_HIPOX_MANUAL_STATIC_ARBITRATION ++ ++#ifdef CONFIG_HIPOX_FEEDBACK_PCI_CLKS ++ /* Set PCI feedback clk GPIO pin as an output */ ++ *(volatile u32*)GPIO_1_SET_OE |= 0x800; ++ ++ /* Enable PCI feedback clk onto GPIO pin */ ++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 |= 0x00000800; ++#endif // CONFIG_HIPOX_FEEDBACK_PCI_CLKS ++ ++#ifndef CONFIG_SYS_NO_FLASH ++ /* Enable static bus onto GPIOs, only CS0 as CS1 conflicts with UART2 */ ++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 |= 0x002FF000; ++ ++ /* Setup the static bus CS0 to access FLASH */ ++ *(volatile u32*)STATIC_CONTROL_BANK0 = STATIC_BUS_FLASH_CONFIG; ++#endif // !CONFIG_SYS_NO_FLASH ++ ++ /* Set 33MHz PCI clock */ ++ *(volatile u32*)SYS_CTRL_CKCTRL_CTRL_ADDR = 5; ++ /* Enable full speed RPS clock */ ++ *(volatile u32*)SYS_CTRL_CKCTRL_CTRL_ADDR &= ~(1UL << SYS_CTRL_CKCTRL_SLOW_BIT); ++ ++#if (USE_EXTERNAL_UART == 0) ++#ifdef CONFIG_HIPOX_UART1 ++ /* Block reset UART1 */ ++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_UART1_BIT); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_UART1_BIT); ++ ++ /* Setup pin mux'ing for first internal UART */ ++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 &= ~0x80000000; ++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_0 &= ~0x80000000; ++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_0 |= 0x80000000; // Route UART1 SOUT onto external pins ++ ++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_1 &= ~0x00000001; ++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_1 &= ~0x00000001; ++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_1 |= 0x00000001; // Route UART1 SIN onto external pins ++ ++ *(volatile u32*)GPIO_1_SET_OE |= 0x80000000; // Make UART1 SOUT an o/p ++ *(volatile u32*)GPIO_2_CLR_OE |= 0x00000001; // Make UART1 SIN an i/p ++#endif // CONFIG_HIPOX_UART1 ++ ++#ifdef CONFIG_HIPOX_UART2 ++ // Block reset UART2 ++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_UART2_BIT); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_UART2_BIT); ++ ++ /* Setup pin mux'ing for second internal UART */ ++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 &= ~0x00500000; ++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_0 &= ~0x00500000; ++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_0 |= 0x00500000; // Route UART2 SOUT and SIN onto external pins ++ ++ *(volatile u32*)GPIO_1_SET_OE |= 0x00100000; // Make UART2 SOUT an o/p ++ *(volatile u32*)GPIO_1_CLR_OE |= 0x00400000; // Make UART2 SIN an i/p ++#endif // CONFIG_HIPOX_UART2 ++ ++#ifdef CONFIG_HIPOX_UART3 ++ // Block reset UART3 ++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_UART3_BIT); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_UART3_BIT); ++ ++ // Route UART3 SIN/SOUT onto external pin ++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 &= ~0x000000C0; ++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_0 &= ~0x000000C0; ++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_0 |= 0x000000C0; ++ ++ // Setup GPIO line directions for UART3 SIN/SOUT ++ *(volatile u32*)GPIO_1_SET_OE |= 0x00000080; ++ *(volatile u32*)GPIO_1_CLR_OE |= 0x00000040; ++#endif // CONFIG_ARCH_HIPOX_UART3 ++ ++#ifdef CONFIG_HIPOX_UART4 ++ // Block reset UART4 ++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_UART4_BIT); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_UART4_BIT); ++ ++ // Enable UART4 to override PCI functions onto GPIOs ++ *(volatile u32*)SYS_CTRL_UART_CTRL |= (1UL << SYS_CTRL_UART4_NOT_PCI_MODE); ++#endif // CONFIG_HIPOX_UART4 ++#endif // !USE_EXTERNAL_UART ++ ++ return 0; ++} ++ ++int board_late_init() ++{ ++ return 0; ++} ++ ++int misc_init_r(void) ++{ ++ return 0; ++} ++ ++int dram_init(void) ++{ ++#ifdef PROBE_MEM_SIZE ++ /* Determine the amount of SDRAM the DDR controller is configured for */ ++ volatile unsigned long * const ddr_config_reg_adr = (volatile unsigned long *)(0x45800000); ++ static const int DDR_SIZE_BIT = 17; ++ static const int DDR_SIZE_NUM_BITS = 4; ++ static const unsigned long DDR_SIZE_MASK = (((1UL << DDR_SIZE_NUM_BITS) - 1) << DDR_SIZE_BIT); ++ ++ unsigned long ddr_config_reg = *ddr_config_reg_adr; ++ int ddr_size_pow2 = (ddr_config_reg & DDR_SIZE_MASK) >> DDR_SIZE_BIT; ++ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ gd->bd->bi_dram[0].size = (1 << ddr_size_pow2) * 1024 * 1024; ++ ++ if ((gd->bd->bi_dram[0].size >> 20) == 256) { ++ /* Do we really have 256M, or are we working around the DDR controller's ++ * problem with 128M size? */ ++ volatile unsigned long * const PROBE_ADR_1 = (volatile unsigned long * const)PHYS_SDRAM_1_PA; ++ volatile unsigned long * const PROBE_ADR_2 = (volatile unsigned long * const)(PHYS_SDRAM_1_PA + (128*1024*1024)); ++ static const unsigned long PROBE_VAL_1 = 0xdeadbeef; ++ static const unsigned long PROBE_VAL_2 = 0x12345678; ++ ++ *PROBE_ADR_1 = PROBE_VAL_1; ++ *PROBE_ADR_2 = PROBE_VAL_2; ++ if (*PROBE_ADR_1 != PROBE_VAL_1) { ++ gd->bd->bi_dram[0].size = 128*1024*1024; ++ } ++ } ++#else // PROBE_MEM_SIZE ++ gd->bd->bi_dram[0].size = MEM_SIZE; ++#endif // PROBE_MEM_SIZE ++ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1_PA; ++ ++ gd->bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; ++ gd->bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; ++ ++ return 0; ++} ++ ++void reset_cpu (ulong addr) ++{ ++ printf("Resetting OXE810 HydraIP..."); ++ ++ // Assert reset to cores as per power on defaults ++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = ++ (1UL << SYS_CTRL_RSTEN_COPRO_BIT) | ++ (1UL << SYS_CTRL_RSTEN_USBHS_BIT) | ++ (1UL << SYS_CTRL_RSTEN_USBHSPHY_BIT) | ++ (1UL << SYS_CTRL_RSTEN_MAC_BIT) | ++ (1UL << SYS_CTRL_RSTEN_PCI_BIT) | ++ (1UL << SYS_CTRL_RSTEN_DMA_BIT) | ++ (1UL << SYS_CTRL_RSTEN_DPE_BIT) | ++ (1UL << SYS_CTRL_RSTEN_SATA_BIT) | ++ (1UL << SYS_CTRL_RSTEN_SATA_LINK_BIT) | ++ (1UL << SYS_CTRL_RSTEN_SATA_PHY_BIT) | ++ (1UL << SYS_CTRL_RSTEN_STATIC_BIT) | ++ (1UL << SYS_CTRL_RSTEN_UART1_BIT) | ++ (1UL << SYS_CTRL_RSTEN_UART2_BIT) | ++ (1UL << SYS_CTRL_RSTEN_MISC_BIT) | ++ (1UL << SYS_CTRL_RSTEN_I2S_BIT) | ++ (1UL << SYS_CTRL_RSTEN_AHB_MON_BIT) | ++ (1UL << SYS_CTRL_RSTEN_UART3_BIT) | ++ (1UL << SYS_CTRL_RSTEN_UART4_BIT) | ++ (1UL << SYS_CTRL_RSTEN_SGDMA_BIT); ++ ++ // Release reset to cores as per power on defaults ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_GPIO_BIT); ++ ++ // Disable clocks to cores as per power-on defaults ++ *(volatile u32*)SYS_CTRL_CKEN_CLR_CTRL = ++ (1UL << SYS_CTRL_CKEN_COPRO_BIT) | ++ (1UL << SYS_CTRL_CKEN_DMA_BIT) | ++ (1UL << SYS_CTRL_CKEN_DPE_BIT) | ++ (1UL << SYS_CTRL_CKEN_SATA_BIT) | ++ (1UL << SYS_CTRL_CKEN_I2S_BIT) | ++ (1UL << SYS_CTRL_CKEN_USBHS_BIT) | ++ (1UL << SYS_CTRL_CKEN_MAC_BIT) | ++ (1UL << SYS_CTRL_CKEN_STATIC_BIT); ++ ++ // Enable clocks to cores as per power-on defaults ++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_PCI_BIT); ++ ++ // Set sys-control pin mux'ing as per power-on defaults ++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 = 0x800UL; ++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_1 = 0x0UL; ++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_0 = 0x0UL; ++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_1 = 0x0UL; ++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_0 = 0x0UL; ++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_1 = 0x0UL; ++ ++ // No need to save any state, as the ROM loader can determine whether reset ++ // is due to power cycling or programatic action, just hit the (self- ++ // clearing) CPU reset bit of the block reset register ++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_ARM_BIT); ++} ++ ++#ifdef CONFIG_CMD_NAND ++#include <linux/mtd/nand.h> ++ ++static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) ++{ ++ struct nand_chip *this = mtdinfo->priv; ++ ++ if (ctrl & NAND_CTRL_CHANGE) { ++ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; ++ ++ IO_ADDR_W = CONFIG_SYS_NAND_BASE; ++ ++#ifdef CONFIG_HIPOX_NAND_GPIO33 ++ if (ctrl & NAND_NCE) ++ *((volatile u32 *)GPIO_2_SET) = 0x00000002; // assert CS-NAND ++ else ++ *((volatile u32 *)GPIO_2_CLR) = 0x00000002; // deassert CS-NAND ++#else ++ if (ctrl & NAND_NCE) ++ *((volatile u32 *)GPIO_1_CLR) = 0x20000000; // assert CS-NAND ++ else ++ *((volatile u32 *)GPIO_1_SET) = 0x20000000; // deassert CS-NAND ++#endif ++ ++ if (ctrl & NAND_CLE) ++ IO_ADDR_W = CONFIG_SYS_NAND_COMMAND_LATCH; ++ if (ctrl & NAND_ALE) ++ IO_ADDR_W = CONFIG_SYS_NAND_ADDRESS_LATCH; ++ ++ this->IO_ADDR_W = (void *)IO_ADDR_W; ++ ++ } ++ ++ if (cmd != NAND_CMD_NONE) ++ writeb(cmd, this->IO_ADDR_W); ++} ++ ++static void oxe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) ++{ ++ uint32_t save_bank0_timing; ++ ++ struct nand_chip *chip = mtd->priv; ++ volatile uint8_t *io = chip->IO_ADDR_R; ++ ++ // change read access timing ++ save_bank0_timing = *(volatile u32*)STATIC_CONTROL_BANK0; ++ *(volatile u32*)STATIC_CONTROL_BANK0 = 0x4f1f3f04; // 27 ns ++ ++ while(len-- > 0) ++ *buf++ = *io; ++ ++ // restore timing ++ *(volatile u32*)STATIC_CONTROL_BANK0 = save_bank0_timing; ++} ++ ++int board_nand_init(struct nand_chip *nand) ++{ ++#ifdef CONFIG_HIPOX_NAND_GPIO33 ++ // use GPIO 33, active high ++ ++ *((volatile u32 *)GPIO_2_CLR) = 0x00000002; ++ *((volatile u32 *)GPIO_2_SET_OE) = 0x00000002; ++ ++ // unselect alternate functions ++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_1 &= ~0x00000002; ++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_1 &= ~0x00000002; ++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_1 &= ~0x00000002; ++ ++ // assert CS-NAND ++ *((volatile u32 *)GPIO_2_SET) = 0x00000002; ++#else ++ // use GPIO 29, active low ++ ++ *((volatile u32 *)GPIO_1_SET) = 0x20000000; ++ *((volatile u32 *)GPIO_1_SET_OE) = 0x20000000; ++ ++ // unselect alternate functions ++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 &= ~0x20000000; ++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_0 &= ~0x20000000; ++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_0 &= ~0x20000000; ++ ++ // assert CS-NAND ++ *((volatile u32 *)GPIO_1_CLR) = 0x20000000; ++#endif ++ ++ // reset NAND unit ++ *((volatile u8 *)(CONFIG_SYS_NAND_COMMAND_LATCH)) = 0xff; // reset command ++ udelay(500); ++ ++#ifdef CONFIG_HIPOX_NAND_GPIO33 ++ // deassert CS-NAND ++ *((volatile u32 *)GPIO_2_CLR) = 0x00000002; ++#else ++ // deassert CS-NAND ++ *((volatile u32 *)GPIO_1_SET) = 0x20000000; ++#endif ++ ++ nand->chip_delay = 50; ++ nand->ecc.mode = NAND_ECC_SOFT; ++ nand->cmd_ctrl = nand_hwcontrol; ++ nand->read_buf = oxe_read_buf; ++ ++ return 0; ++} ++#endif +diff -Nurd u-boot-2009.03.orig/board/hipox/ide-810.c u-boot-2009.03/board/hipox/ide-810.c +--- u-boot-2009.03.orig/board/hipox/ide-810.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/ide-810.c 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,892 @@ ++/* ++ * (C) Copyright 2005 ++ * Oxford Semiconductor Ltd ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,` ++ * MA 02111-1307 USA ++ */ ++#include <common.h> ++ ++#define SATA_DMA_CHANNEL 0 ++ ++#define DMA_CTRL_STATUS (0x0) ++#define DMA_BASE_SRC_ADR (0x4) ++#define DMA_BASE_DST_ADR (0x8) ++#define DMA_BYTE_CNT (0xC) ++#define DMA_CURRENT_SRC_ADR (0x10) ++#define DMA_CURRENT_DST_ADR (0x14) ++#define DMA_CURRENT_BYTE_CNT (0x18) ++#define DMA_INTR_ID (0x1C) ++#define DMA_INTR_CLEAR_REG (DMA_CURRENT_SRC_ADR) ++ ++#define DMA_CALC_REG_ADR(channel, register) ((volatile u32*)(DMA_BASE_PA + ((channel) << 5) + (register))) ++ ++#define DMA_CTRL_STATUS_FAIR_SHARE_ARB (1 << 0) ++#define DMA_CTRL_STATUS_IN_PROGRESS (1 << 1) ++#define DMA_CTRL_STATUS_SRC_DREQ_MASK (0x0000003C) ++#define DMA_CTRL_STATUS_SRC_DREQ_SHIFT (2) ++#define DMA_CTRL_STATUS_DEST_DREQ_MASK (0x000003C0) ++#define DMA_CTRL_STATUS_DEST_DREQ_SHIFT (6) ++#define DMA_CTRL_STATUS_INTR (1 << 10) ++#define DMA_CTRL_STATUS_NXT_FREE (1 << 11) ++#define DMA_CTRL_STATUS_RESET (1 << 12) ++#define DMA_CTRL_STATUS_DIR_MASK (0x00006000) ++#define DMA_CTRL_STATUS_DIR_SHIFT (13) ++#define DMA_CTRL_STATUS_SRC_ADR_MODE (1 << 15) ++#define DMA_CTRL_STATUS_DEST_ADR_MODE (1 << 16) ++#define DMA_CTRL_STATUS_TRANSFER_MODE_A (1 << 17) ++#define DMA_CTRL_STATUS_TRANSFER_MODE_B (1 << 18) ++#define DMA_CTRL_STATUS_SRC_WIDTH_MASK (0x00380000) ++#define DMA_CTRL_STATUS_SRC_WIDTH_SHIFT (19) ++#define DMA_CTRL_STATUS_DEST_WIDTH_MASK (0x01C00000) ++#define DMA_CTRL_STATUS_DEST_WIDTH_SHIFT (22) ++#define DMA_CTRL_STATUS_PAUSE (1 << 25) ++#define DMA_CTRL_STATUS_INTERRUPT_ENABLE (1 << 26) ++#define DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED (1 << 27) ++#define DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED (1 << 28) ++#define DMA_CTRL_STATUS_STARVE_LOW_PRIORITY (1 << 29) ++#define DMA_CTRL_STATUS_INTR_CLEAR_ENABLE (1 << 30) ++ ++#define DMA_BYTE_CNT_MASK ((1 << 21) - 1) ++#define DMA_BYTE_CNT_WR_EOT_MASK (1 << 30) ++#define DMA_BYTE_CNT_RD_EOT_MASK (1 << 31) ++ ++#define MAKE_FIELD(value, num_bits, bit_num) (((value) & ((1 << (num_bits)) - 1)) << (bit_num)) ++ ++typedef enum hipox_dma_mode { ++ HIPOX_DMA_MODE_FIXED, ++ HIPOX_DMA_MODE_INC ++} hipox_dma_mode_t; ++ ++typedef enum hipox_dma_direction { ++ HIPOX_DMA_TO_DEVICE, ++ HIPOX_DMA_FROM_DEVICE ++} hipox_dma_direction_t; ++ ++/* The available buses to which the DMA controller is attached */ ++typedef enum hipox_dma_transfer_bus ++{ ++ HIPOX_DMA_SIDE_A, ++ HIPOX_DMA_SIDE_B ++} hipox_dma_transfer_bus_t; ++ ++/* Direction of data flow between the DMA controller's pair of interfaces */ ++typedef enum hipox_dma_transfer_direction ++{ ++ HIPOX_DMA_A_TO_A, ++ HIPOX_DMA_B_TO_A, ++ HIPOX_DMA_A_TO_B, ++ HIPOX_DMA_B_TO_B ++} hipox_dma_transfer_direction_t; ++ ++/* The available data widths */ ++typedef enum hipox_dma_transfer_width ++{ ++ HIPOX_DMA_TRANSFER_WIDTH_8BITS, ++ HIPOX_DMA_TRANSFER_WIDTH_16BITS, ++ HIPOX_DMA_TRANSFER_WIDTH_32BITS ++} hipox_dma_transfer_width_t; ++ ++/* The mode of the DMA transfer */ ++typedef enum hipox_dma_transfer_mode ++{ ++ HIPOX_DMA_TRANSFER_MODE_SINGLE, ++ HIPOX_DMA_TRANSFER_MODE_BURST ++} hipox_dma_transfer_mode_t; ++ ++/* The available transfer targets */ ++typedef enum hipox_dma_dreq ++{ ++ HIPOX_DMA_DREQ_SATA = 0, ++ HIPOX_DMA_DREQ_MEMORY = 15 ++} hipox_dma_dreq_t; ++ ++typedef struct hipox_dma_device_settings { ++ unsigned long address_; ++ unsigned fifo_size_; // Chained transfers must take account of FIFO offset at end of previous transfer ++ unsigned char dreq_; ++ unsigned read_eot_:1; ++ unsigned read_final_eot_:1; ++ unsigned write_eot_:1; ++ unsigned write_final_eot_:1; ++ unsigned bus_:1; ++ unsigned width_:2; ++ unsigned transfer_mode_:1; ++ unsigned address_mode_:1; ++ unsigned address_really_fixed_:1; ++} hipox_dma_device_settings_t; ++ ++static const int MAX_NO_ERROR_LOOPS = 100000; /* 1 second in units of 10uS */ ++static const int MAX_DMA_XFER_LOOPS = 300000; /* 30 seconds in units of 100uS */ ++static const int MAX_DMA_ABORT_LOOPS = 10000; /* 0.1 second in units of 10uS */ ++static const int MAX_SRC_READ_LOOPS = 10000; /* 0.1 second in units of 10uS */ ++static const int MAX_SRC_WRITE_LOOPS = 10000; /* 0.1 second in units of 10uS */ ++static const int MAX_NOT_BUSY_LOOPS = 10000; /* 1 second in units of 100uS */ ++ ++/* The internal SATA drive on which we should attempt to find partitions */ ++static volatile u32* sata_regs_base[2] = ++{ ++ (volatile u32*)SATA_0_REGS_BASE, ++ (volatile u32*)SATA_1_REGS_BASE, ++ ++}; ++static u32 wr_sata_orb1[2] = { 0, 0 }; ++static u32 wr_sata_orb2[2] = { 0, 0 }; ++static u32 wr_sata_orb3[2] = { 0, 0 }; ++static u32 wr_sata_orb4[2] = { 0, 0 }; ++ ++static hipox_dma_device_settings_t hipox_sata_dma_settings = { ++ .address_ = SATA_DATA_BASE_PA, ++ .fifo_size_ = 16, ++ .dreq_ = HIPOX_DMA_DREQ_SATA, ++ .read_eot_ = 0, ++ .read_final_eot_ = 1, ++ .write_eot_ = 0, ++ .write_final_eot_ = 1, ++ .bus_ = HIPOX_DMA_SIDE_A, ++ .width_ = HIPOX_DMA_TRANSFER_WIDTH_32BITS, ++ .transfer_mode_ = HIPOX_DMA_TRANSFER_MODE_BURST, ++ .address_mode_ = HIPOX_DMA_MODE_FIXED, ++ .address_really_fixed_ = 0 ++}; ++ ++hipox_dma_device_settings_t hipox_ram_dma_settings = { ++ .address_ = 0, ++ .fifo_size_ = 0, ++ .dreq_ = HIPOX_DMA_DREQ_MEMORY, ++ .read_eot_ = 1, ++ .read_final_eot_ = 1, ++ .write_eot_ = 1, ++ .write_final_eot_ = 1, ++ .bus_ = HIPOX_DMA_SIDE_B, ++ .width_ = HIPOX_DMA_TRANSFER_WIDTH_32BITS, ++ .transfer_mode_ = HIPOX_DMA_TRANSFER_MODE_BURST, ++ .address_mode_ = HIPOX_DMA_MODE_FIXED, ++ .address_really_fixed_ = 1 ++}; ++ ++static void xfer_wr_shadow_to_orbs(int device) ++{ ++ *(sata_regs_base[device] + SATA_ORB1_OFF) = wr_sata_orb1[device]; ++ *(sata_regs_base[device] + SATA_ORB2_OFF) = wr_sata_orb2[device]; ++ *(sata_regs_base[device] + SATA_ORB3_OFF) = wr_sata_orb3[device]; ++ *(sata_regs_base[device] + SATA_ORB4_OFF) = wr_sata_orb4[device]; ++} ++ ++static inline void device_select(int device) ++{ ++ /* master/slave has no meaning to SATA core */ ++} ++ ++static int disk_present[CONFIG_SYS_IDE_MAXDEVICE]; ++ ++#include <ata.h> ++ ++unsigned char inline ide_inb(int device, int port) ++{ ++ unsigned char val = 0; ++ ++ /* Only permit accesses to disks found to be present during ide_preinit() */ ++ if (!disk_present[device]) { ++ return ATA_STAT_FAULT; ++ } ++ ++ device_select(device); ++ ++ switch (port) { ++ case ATA_PORT_CTL: ++ val = (*(sata_regs_base[device] + SATA_ORB4_OFF) & (0xFFUL << SATA_CTL_BIT)) >> SATA_CTL_BIT; ++ break; ++ case ATA_PORT_FEATURE: ++ val = (*(sata_regs_base[device] + SATA_ORB2_OFF) & (0xFFUL << SATA_FEATURE_BIT)) >> SATA_FEATURE_BIT; ++ break; ++ case ATA_PORT_NSECT: ++ val = (*(sata_regs_base[device] + SATA_ORB2_OFF) & (0xFFUL << SATA_NSECT_BIT)) >> SATA_NSECT_BIT; ++ break; ++ case ATA_PORT_LBAL: ++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_LBAL_BIT)) >> SATA_LBAL_BIT; ++ break; ++ case ATA_PORT_LBAM: ++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_LBAM_BIT)) >> SATA_LBAM_BIT; ++ break; ++ case ATA_PORT_LBAH: ++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_LBAH_BIT)) >> SATA_LBAH_BIT; ++ break; ++ case ATA_PORT_DEVICE: ++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_HOB_LBAH_BIT)) >> SATA_HOB_LBAH_BIT; ++ val |= (*(sata_regs_base[device] + SATA_ORB1_OFF) & (0xFFUL << SATA_DEVICE_BIT)) >> SATA_DEVICE_BIT; ++ break; ++ case ATA_PORT_COMMAND: ++ val = (*(sata_regs_base[device] + SATA_ORB2_OFF) & (0xFFUL << SATA_COMMAND_BIT)) >> SATA_COMMAND_BIT; ++ val |= ATA_STAT_DRQ ; ++ break; ++ default: ++ printf("ide_inb() Unknown port = %d\n", port); ++ break; ++ } ++ ++// printf("inb: %d:%01x => %02x\n", device, port, val); ++ ++ return val; ++} ++ ++/** ++ * Possible that ATA status will not become no-error, so must have timeout ++ * @returns An int which is zero on error ++ */ ++static inline int wait_no_error(int device) ++{ ++ int status = 0; ++ ++ /* Check for ATA core error */ ++ if (*(sata_regs_base[device] + SATA_INT_STATUS_OFF) & (1 << SATA_INT_STATUS_ERROR_BIT)) { ++ printf("wait_no_error() SATA core flagged error\n"); ++ } else { ++ int loops = MAX_NO_ERROR_LOOPS; ++ do { ++ /* Check for ATA device error */ ++ if (!(ide_inb(device, ATA_PORT_COMMAND) & (1 << ATA_STATUS_ERR_BIT))) { ++ status = 1; ++ break; ++ } ++ udelay(10); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("wait_no_error() Timed out of wait for SATA no-error condition\n"); ++ } ++ } ++ ++ return status; ++} ++ ++/** ++ * Expect SATA command to always finish, perhaps with error ++ * @returns An int which is zero on error ++ */ ++static inline int wait_sata_command_not_busy(int device) ++{ ++ /* Wait for data to be available */ ++ int status = 0; ++ int loops = MAX_NOT_BUSY_LOOPS; ++ do { ++ if (!(*(sata_regs_base[device] + SATA_COMMAND_OFF) & (1 << SATA_CMD_BUSY_BIT) )) { ++ status = 1; ++ break; ++ } ++ udelay(100); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("wait_sata_command_not_busy() Timed out of wait for SATA command to finish\n"); ++ } ++ ++ return status; ++} ++ ++void inline ide_outb(int device, int port, unsigned char val) ++{ ++ typedef enum send_method { ++ SEND_NONE, ++ SEND_SIMPLE, ++ SEND_CMD, ++ SEND_CTL, ++ } send_method_t; ++ ++ /* Only permit accesses to disks found to be present during ide_preinit() */ ++ if (!disk_present[device]) { ++ return; ++ } ++ ++// printf("outb: %d:%01x <= %02x\n", device, port, val); ++ ++ device_select(device); ++ ++ send_method_t send_regs = SEND_NONE; ++ switch (port) { ++ case ATA_PORT_CTL: ++ wr_sata_orb4[device] &= ~(0xFFUL << SATA_CTL_BIT); ++ wr_sata_orb4[device] |= (val << SATA_CTL_BIT); ++ send_regs = SEND_CTL; ++ break; ++ case ATA_PORT_FEATURE: ++ wr_sata_orb2[device] &= ~(0xFFUL << SATA_FEATURE_BIT); ++ wr_sata_orb2[device] |= (val << SATA_FEATURE_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_NSECT: ++ wr_sata_orb2[device] &= ~(0xFFUL << SATA_NSECT_BIT); ++ wr_sata_orb2[device] |= (val << SATA_NSECT_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_LBAL: ++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAL_BIT); ++ wr_sata_orb3[device] |= (val << SATA_LBAL_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_LBAM: ++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAM_BIT); ++ wr_sata_orb3[device] |= (val << SATA_LBAM_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_LBAH: ++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAH_BIT); ++ wr_sata_orb3[device] |= (val << SATA_LBAH_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_DEVICE: ++ wr_sata_orb1[device] &= ~(0xFFUL << SATA_DEVICE_BIT); ++ wr_sata_orb1[device] |= ((val & 0xf0) << SATA_DEVICE_BIT); ++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_HOB_LBAH_BIT); ++ wr_sata_orb3[device] |= ((val & 0x0f) << SATA_HOB_LBAH_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_COMMAND: ++ wr_sata_orb2[device] &= ~(0xFFUL << SATA_COMMAND_BIT); ++ wr_sata_orb2[device] |= (val << SATA_COMMAND_BIT); ++ send_regs = SEND_CMD; ++ break; ++ default: ++ printf("ide_outb() Unknown port = %d\n", port); ++ } ++ ++ u32 command; ++ switch (send_regs) { ++ case SEND_CMD: ++ wait_sata_command_not_busy(device); ++ command = *(sata_regs_base[device] + SATA_COMMAND_OFF); ++ command &= ~SATA_OPCODE_MASK; ++ command |= SATA_CMD_WRITE_TO_ORB_REGS; ++ xfer_wr_shadow_to_orbs(device); ++ wait_sata_command_not_busy(device); ++ *(sata_regs_base[device] + SATA_COMMAND_OFF) = command; ++ if (!wait_no_error(device)) { ++ printf("hipox_sata_outb() Wait for ATA no-error timed-out\n"); ++ } ++ break; ++ case SEND_CTL: ++ wait_sata_command_not_busy(device); ++ command = *(sata_regs_base[device] + SATA_COMMAND_OFF); ++ command &= ~SATA_OPCODE_MASK; ++ command |= SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND; ++ xfer_wr_shadow_to_orbs(device); ++ wait_sata_command_not_busy(device); ++ *(sata_regs_base[device] + SATA_COMMAND_OFF) = command; ++ if (!wait_no_error(device)) { ++ printf("hipox_sata_outb() Wait for ATA no-error timed-out\n"); ++ } ++ break; ++ default: ++ break; ++ } ++} ++ ++static u32 encode_start(u32 ctrl_status) ++{ ++ return ctrl_status & ~DMA_CTRL_STATUS_PAUSE; ++} ++ ++static void dma_start(void) ++{ ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = ++ encode_start(*(DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS))); ++} ++ ++static unsigned long encode_control_status( ++ hipox_dma_device_settings_t* src_settings, ++ hipox_dma_device_settings_t* dst_settings) ++{ ++ unsigned long ctrl_status; ++ hipox_dma_transfer_direction_t direction; ++ ++ ctrl_status = DMA_CTRL_STATUS_PAUSE; // Paused ++ ctrl_status |= DMA_CTRL_STATUS_FAIR_SHARE_ARB; // High priority ++ ctrl_status |= (src_settings->dreq_ << DMA_CTRL_STATUS_SRC_DREQ_SHIFT); // Dreq ++ ctrl_status |= (dst_settings->dreq_ << DMA_CTRL_STATUS_DEST_DREQ_SHIFT); // Dreq ++ ctrl_status &= ~DMA_CTRL_STATUS_RESET; // !RESET ++ ++ // Use new interrupt clearing register ++ ctrl_status |= DMA_CTRL_STATUS_INTR_CLEAR_ENABLE; ++ ++ // Setup the transfer direction and burst/single mode for the two DMA busses ++ if (src_settings->bus_ == HIPOX_DMA_SIDE_A) { ++ // Set the burst/single mode for bus A based on src device's settings ++ if (src_settings->transfer_mode_ == HIPOX_DMA_TRANSFER_MODE_BURST) { ++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A; ++ } ++ ++ if (dst_settings->bus_ == HIPOX_DMA_SIDE_A) { ++ direction = HIPOX_DMA_A_TO_A; ++ } else { ++ direction = HIPOX_DMA_A_TO_B; ++ ++ // Set the burst/single mode for bus B based on dst device's settings ++ if (dst_settings->transfer_mode_ == HIPOX_DMA_TRANSFER_MODE_BURST) { ++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B; ++ } ++ } ++ } else { ++ // Set the burst/single mode for bus B based on src device's settings ++ if (src_settings->transfer_mode_ == HIPOX_DMA_TRANSFER_MODE_BURST) { ++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B; ++ } ++ ++ if (dst_settings->bus_ == HIPOX_DMA_SIDE_A) { ++ direction = HIPOX_DMA_B_TO_A; ++ ++ // Set the burst/single mode for bus A based on dst device's settings ++ if (dst_settings->transfer_mode_ == HIPOX_DMA_TRANSFER_MODE_BURST) { ++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A; ++ } ++ } else { ++ direction = HIPOX_DMA_B_TO_B; ++ } ++ } ++ ctrl_status |= (direction << DMA_CTRL_STATUS_DIR_SHIFT); ++ ++ // Setup source address mode fixed or increment ++ if (src_settings->address_mode_ == HIPOX_DMA_MODE_FIXED) { ++ // Fixed address ++ ctrl_status &= ~(DMA_CTRL_STATUS_SRC_ADR_MODE); ++ ++ // Set up whether fixed address is _really_ fixed ++ if (src_settings->address_really_fixed_) { ++ ctrl_status |= DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED; ++ } ++ } else { ++ // Incrementing address ++ ctrl_status |= DMA_CTRL_STATUS_SRC_ADR_MODE; ++ ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED; ++ } ++ ++ // Setup destination address mode fixed or increment ++ if (dst_settings->address_mode_ == HIPOX_DMA_MODE_FIXED) { ++ // Fixed address ++ ctrl_status &= ~(DMA_CTRL_STATUS_DEST_ADR_MODE); ++ ++ // Set up whether fixed address is _really_ fixed ++ if (dst_settings->address_really_fixed_) { ++ ctrl_status |= DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED; ++ } ++ } else { ++ // Incrementing address ++ ctrl_status |= DMA_CTRL_STATUS_DEST_ADR_MODE; ++ ctrl_status &= ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED; ++ } ++ ++ // Set up the width of the transfers on the DMA buses ++ ctrl_status |= (src_settings->width_ << DMA_CTRL_STATUS_SRC_WIDTH_SHIFT); ++ ctrl_status |= (dst_settings->width_ << DMA_CTRL_STATUS_DEST_WIDTH_SHIFT); ++ ++ // Setup the priority arbitration scheme ++ ctrl_status &= ~DMA_CTRL_STATUS_STARVE_LOW_PRIORITY; // !Starve low priority ++ ++ return ctrl_status; ++} ++ ++static u32 encode_final_eot( ++ hipox_dma_device_settings_t* src_settings, ++ hipox_dma_device_settings_t* dst_settings, ++ unsigned long length) ++{ ++ // Write the length, with EOT configuration for a final transfer ++ unsigned long encoded = length; ++ if (dst_settings->write_final_eot_) { ++ encoded |= DMA_BYTE_CNT_WR_EOT_MASK; ++ } else { ++ encoded &= ~DMA_BYTE_CNT_WR_EOT_MASK; ++ } ++ if (src_settings->read_final_eot_) { ++ encoded |= DMA_BYTE_CNT_RD_EOT_MASK; ++ } else { ++ encoded &= ~DMA_BYTE_CNT_RD_EOT_MASK; ++ } ++ return encoded; ++} ++ ++static void dma_start_write(ulong* buffer, int num_bytes) ++{ ++ // Assemble complete memory settings ++ hipox_dma_device_settings_t mem_settings = hipox_ram_dma_settings; ++ mem_settings.address_ = (unsigned long)buffer; ++ mem_settings.address_mode_ = HIPOX_DMA_MODE_INC; ++ ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = encode_control_status(&mem_settings, &hipox_sata_dma_settings); ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_SRC_ADR) = mem_settings.address_; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_DST_ADR) = hipox_sata_dma_settings.address_; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BYTE_CNT) = encode_final_eot(&mem_settings, &hipox_sata_dma_settings, num_bytes); ++ ++ dma_start(); ++} ++ ++static void dma_start_read(ulong* buffer, int num_bytes) ++{ ++ // Assemble complete memory settings ++ hipox_dma_device_settings_t mem_settings = hipox_ram_dma_settings; ++ mem_settings.address_ = (unsigned long)buffer; ++ mem_settings.address_mode_ = HIPOX_DMA_MODE_INC; ++ ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = encode_control_status(&hipox_sata_dma_settings, &mem_settings); ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_SRC_ADR) = hipox_sata_dma_settings.address_; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_DST_ADR) = mem_settings.address_; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BYTE_CNT) = encode_final_eot(&hipox_sata_dma_settings, &mem_settings, num_bytes); ++ ++ dma_start(); ++} ++ ++static inline int dma_busy(void) ++{ ++ return (*DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS)) & DMA_CTRL_STATUS_IN_PROGRESS; ++} ++ ++static int wait_dma_not_busy(int device) ++{ ++ unsigned int cleanup_required = 0; ++ ++ /* Poll for DMA completion */ ++ int loops = MAX_DMA_XFER_LOOPS; ++ do { ++ if (!dma_busy()) { ++ break; ++ } ++ udelay(100); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("wait_dma_not_busy() Timed out of wait for DMA not busy\n"); ++ cleanup_required = 1; ++ } ++ ++ if (cleanup_required) { ++ /* Abort DMA to make sure it has finished. */ ++ unsigned long ctrl_status = *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS); ++ ctrl_status |= DMA_CTRL_STATUS_RESET; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = ctrl_status; ++ ++ // Wait for the channel to become idle - should be quick as should ++ // finish after the next AHB single or burst transfer ++ loops = MAX_DMA_ABORT_LOOPS; ++ do { ++ if (!(*DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) & DMA_CTRL_STATUS_IN_PROGRESS)) { ++ break; ++ } ++ udelay(10); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("wait_dma_not_busy() Timed out of wait for DMA channel abort\n"); ++ } else { ++ /* Successfully cleanup the DMA channel */ ++ cleanup_required = 0; ++ } ++ ++ // Deassert reset for the channel ++ ctrl_status = *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS); ++ ctrl_status &= ~DMA_CTRL_STATUS_RESET; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = ctrl_status; ++ } ++ ++ return !cleanup_required; ++} ++ ++/** ++ * Possible that ATA status will not become not-busy, so must have timeout ++ */ ++static unsigned int wait_not_busy(int device, unsigned long timeout_secs) ++{ ++ int busy = 1; ++ unsigned long loops = (timeout_secs * 1000) / 50; ++ do { ++ // Test the ATA status register BUSY flag ++ if (!((*(sata_regs_base[device] + SATA_ORB2_OFF) >> SATA_COMMAND_BIT) & (1UL << ATA_STATUS_BSY_BIT))) { ++ /* Not busy, so stop polling */ ++ busy = 0; ++ break; ++ } ++ ++ // Wait for 50mS before sampling ATA status register again ++ udelay(50000); ++ } while (--loops); ++ ++ return busy; ++} ++ ++void hipox_sata_output_data(int device, ulong *sect_buf, int words) ++{ ++ /* Only permit accesses to disks found to be present during ide_preinit() */ ++ if (!disk_present[device]) { ++ return; ++ } ++ ++ /* Select the required internal SATA drive */ ++ device_select(device); ++ ++ /* Start the DMA channel sending data from the passed buffer to the SATA core */ ++ dma_start_write(sect_buf, words << 2); ++ ++ /* Don't know why we need this delay, but without it the wait for DMA not ++ busy times soemtimes out, e.g. when saving environment to second disk */ ++ udelay(1000); ++ ++ /* Wait for DMA to finish */ ++ if (!wait_dma_not_busy(device)) { ++ printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n", device); ++ } ++ ++ /* Sata core should finish after DMA */ ++ if (wait_not_busy(device, 30)) { ++ printf("Timed out of wait for SATA device %d to have BUSY clear\n", device); ++ } ++ if (!wait_no_error(device)) { ++ printf("hipox_sata_output_data() Wait for ATA no-error timed-out\n"); ++ } ++} ++ ++void hipox_sata_input_data(int device, ulong *sect_buf, int words) ++{ ++ /* Only permit accesses to disks found to be present during ide_preinit() */ ++ if (!disk_present[device]) { ++ return; ++ } ++ ++ /* Select the required internal SATA drive */ ++ device_select(device); ++ ++ /* Start the DMA channel receiving data from the SATA core into the passed buffer */ ++ dma_start_read(sect_buf, words << 2); ++ ++ /* Sata core should finish before DMA */ ++ if (wait_not_busy(device, 30)) { ++ printf("Timed out of wait for SATA device %d to have BUSY clear\n", device); ++ } ++ if (!wait_no_error(device)) { ++ printf("hipox_sata_output_data() Wait for ATA no-error timed-out\n"); ++ } ++ ++ /* Wait for DMA to finish */ ++ if (!wait_dma_not_busy(device)) { ++ printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n", device); ++ } ++} ++ ++static u32 scr_read(int device, unsigned int sc_reg) ++{ ++ /* Setup adr of required register. std regs start eight into async region */ ++ *(sata_regs_base[device] + SATA_LINK_RD_ADDR) = sc_reg*4 + SATA_STD_ASYNC_REGS_OFF; ++ ++ /* Wait for data to be available */ ++ int loops = MAX_SRC_READ_LOOPS; ++ do { ++ if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) { ++ break; ++ } ++ udelay(10); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("scr_read() Timed out of wait for read completion\n"); ++ } ++ ++ /* Read the data from the async register */ ++ return *(sata_regs_base[device] + SATA_LINK_DATA); ++} ++ ++static void scr_write(int device, unsigned int sc_reg, u32 val) ++{ ++ /* Setup the data for the write */ ++ *(sata_regs_base[device] + SATA_LINK_DATA) = val; ++ ++ /* Setup adr of required register. std regs start eight into async region */ ++ *(sata_regs_base[device] + SATA_LINK_WR_ADDR) = sc_reg*4 + SATA_STD_ASYNC_REGS_OFF; ++ ++ /* Wait for data to be written */ ++ int loops = MAX_SRC_WRITE_LOOPS; ++ do { ++ if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) { ++ break; ++ } ++ udelay(10); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("scr_write() Timed out of wait for write completion\n"); ++ } ++} ++ ++#define PHY_LOOP_COUNT 25 /* Wait for upto 5 seconds for PHY to be found */ ++static int phy_reset(int device) ++{ ++#ifdef FPGA ++ /* The FPGA thinks it can do 3G when infact only 1.5G is possible, so limit ++ it to Gen-1 SATA (1.5G) */ ++ scr_write(device, SATA_SCR_CONTROL, 0x311); /* Issue phy wake & core reset */ ++ scr_read(device, SATA_SCR_STATUS); /* Dummy read; flush */ ++ udelay(1000); ++ scr_write(device, SATA_SCR_CONTROL, 0x310); /* Issue phy wake & clear core reset */ ++#else ++ scr_write(device, SATA_SCR_CONTROL, 0x301); /* Issue phy wake & core reset */ ++ scr_read(device, SATA_SCR_STATUS); /* Dummy read; flush */ ++ udelay(1000); ++ scr_write(device, SATA_SCR_CONTROL, 0x300); /* Issue phy wake & clear core reset */ ++#endif ++ /* Wait for upto 5 seconds for PHY to become ready */ ++ int phy_status = 0; ++ int loops = 0; ++ do { ++ udelay(200000); ++ if ((scr_read(device, SATA_SCR_STATUS) & 0xf) != 1) { ++ phy_status = 1; ++ break; ++ } ++ printf("No SATA PHY found\n"); ++ } while (++loops < PHY_LOOP_COUNT); ++ ++ if (phy_status) { ++ udelay(500000); /* wait half a second */ ++ } ++ return phy_status; ++} ++ ++#define FIS_LOOP_COUNT 25 /* Wait for upto 5 seconds for FIS to be received */ ++static int wait_FIS(int device) ++{ ++ int status = 0; ++ int loops = 0; ++ ++ do { ++ udelay(200000); ++ if (ide_inb(device, ATA_PORT_NSECT) > 0) { ++ status = 1; ++ break; ++ } ++ } while (++loops < FIS_LOOP_COUNT); ++ ++ return status; ++} ++ ++int ide_preinit(void) ++{ ++ int num_disks_found = 0; ++ ++ /* Initialise records of which disks are present to all present */ ++ int i; ++ for (i=0; i < CONFIG_SYS_IDE_MAXDEVICE; i++) { ++ disk_present[i] = 1; ++ } ++ ++//udelay(1000000); ++ /* Enable clocks to SATA and DMA cores */ ++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_SATA_BIT); ++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_DMA_BIT); ++ ++ /* Block reset SATA and DMA cores */ ++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_SATA_BIT) | ++ (1UL << SYS_CTRL_RSTEN_SATA_LINK_BIT) | ++ (1UL << SYS_CTRL_RSTEN_SATA_PHY_BIT) | ++ (1UL << SYS_CTRL_RSTEN_DMA_BIT); ++ udelay(50); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_SATA_PHY_BIT); ++ udelay(50); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_SATA_LINK_BIT) | ++ (1UL << SYS_CTRL_RSTEN_SATA_BIT); ++ udelay(50); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_DMA_BIT); ++ udelay(50); ++//udelay(1000000); ++ ++ /* disable and clear core interrupts */ ++ *((unsigned long*)SATA_HOST_REGS_BASE + SATA_INT_ENABLE_CLR_OFF) = ~0UL; ++ *((unsigned long*)SATA_HOST_REGS_BASE + SATA_INT_CLR_OFF) = ~0UL; ++ ++ int device; ++ for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) { ++ int found = 0; ++ int retries = 1; ++ ++ /* Disable SATA interrupts */ ++ *(sata_regs_base[device] + SATA_INT_ENABLE_CLR_OFF) = ~0UL; ++ ++ /* Clear any pending SATA interrupts */ ++ *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL; ++ ++ do { ++ /* clear sector count register for FIS detection */ ++ ide_outb(device, ATA_PORT_NSECT, 0); ++ ++ /* Get the PHY working */ ++ if (!phy_reset(device)) { ++ printf("SATA PHY not ready for device %d\n", device); ++ break; ++ } ++ ++ if (!wait_FIS(device)) { ++ printf("No FIS received from device %d\n", device); ++ } else { ++ if ((scr_read(device, SATA_SCR_STATUS) & 0xf) == 0x3) { ++ if (wait_not_busy(device, 30)) { ++ printf("Timed out of wait for SATA device %d to have BUSY clear\n", device); ++ } else { ++ ++num_disks_found; ++ found = 1; ++ } ++ } else { ++ printf("No SATA device %d found, PHY status = 0x%08x\n", ++ device, scr_read(device, SATA_SCR_STATUS)); ++ } ++ break; ++ } ++ } while (retries--) ; ++ ++ /* Record whether disk is present, so won't attempt to access it later */ ++ disk_present[device] = found; ++ } ++ ++ /* post disk detection clean-up */ ++ for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) { ++ if ( disk_present[device] ) { ++ /* set as ata-5 (28-bit) */ ++ *(sata_regs_base[device] + SATA_DRIVE_CONTROL_OFF) = 0UL; ++ ++ /* clear phy/link errors */ ++ scr_write(device, SATA_SCR_ERROR, ~0); ++ ++ /* clear host errors */ ++ *(sata_regs_base[device] + SATA_CONTROL_OFF) |= SATA_SCTL_CLR_ERR; ++ ++ /* clear interrupt register as this clears the error bit in the IDE ++ status register */ ++ *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL; ++ } ++ } ++ ++ ++ return !num_disks_found; ++} ++ +diff -Nurd u-boot-2009.03.orig/board/hipox/ide-820.c u-boot-2009.03/board/hipox/ide-820.c +--- u-boot-2009.03.orig/board/hipox/ide-820.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/ide-820.c 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,892 @@ ++/* ++ * (C) Copyright 2005 ++ * Oxford Semiconductor Ltd ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,` ++ * MA 02111-1307 USA ++ */ ++#include <common.h> ++ ++#define SATA_DMA_CHANNEL 0 ++ ++#define DMA_CTRL_STATUS (0x0) ++#define DMA_BASE_SRC_ADR (0x4) ++#define DMA_BASE_DST_ADR (0x8) ++#define DMA_BYTE_CNT (0xC) ++#define DMA_CURRENT_SRC_ADR (0x10) ++#define DMA_CURRENT_DST_ADR (0x14) ++#define DMA_CURRENT_BYTE_CNT (0x18) ++#define DMA_INTR_ID (0x1C) ++#define DMA_INTR_CLEAR_REG (DMA_CURRENT_SRC_ADR) ++ ++#define DMA_CALC_REG_ADR(channel, register) ((volatile u32*)(DMA_BASE_PA + ((channel) << 5) + (register))) ++ ++#define DMA_CTRL_STATUS_FAIR_SHARE_ARB (1 << 0) ++#define DMA_CTRL_STATUS_IN_PROGRESS (1 << 1) ++#define DMA_CTRL_STATUS_SRC_DREQ_MASK (0x0000003C) ++#define DMA_CTRL_STATUS_SRC_DREQ_SHIFT (2) ++#define DMA_CTRL_STATUS_DEST_DREQ_MASK (0x000003C0) ++#define DMA_CTRL_STATUS_DEST_DREQ_SHIFT (6) ++#define DMA_CTRL_STATUS_INTR (1 << 10) ++#define DMA_CTRL_STATUS_NXT_FREE (1 << 11) ++#define DMA_CTRL_STATUS_RESET (1 << 12) ++#define DMA_CTRL_STATUS_DIR_MASK (0x00006000) ++#define DMA_CTRL_STATUS_DIR_SHIFT (13) ++#define DMA_CTRL_STATUS_SRC_ADR_MODE (1 << 15) ++#define DMA_CTRL_STATUS_DEST_ADR_MODE (1 << 16) ++#define DMA_CTRL_STATUS_TRANSFER_MODE_A (1 << 17) ++#define DMA_CTRL_STATUS_TRANSFER_MODE_B (1 << 18) ++#define DMA_CTRL_STATUS_SRC_WIDTH_MASK (0x00380000) ++#define DMA_CTRL_STATUS_SRC_WIDTH_SHIFT (19) ++#define DMA_CTRL_STATUS_DEST_WIDTH_MASK (0x01C00000) ++#define DMA_CTRL_STATUS_DEST_WIDTH_SHIFT (22) ++#define DMA_CTRL_STATUS_PAUSE (1 << 25) ++#define DMA_CTRL_STATUS_INTERRUPT_ENABLE (1 << 26) ++#define DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED (1 << 27) ++#define DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED (1 << 28) ++#define DMA_CTRL_STATUS_STARVE_LOW_PRIORITY (1 << 29) ++#define DMA_CTRL_STATUS_INTR_CLEAR_ENABLE (1 << 30) ++ ++#define DMA_BYTE_CNT_MASK ((1 << 21) - 1) ++#define DMA_BYTE_CNT_WR_EOT_MASK (1 << 30) ++#define DMA_BYTE_CNT_RD_EOT_MASK (1 << 31) ++ ++#define MAKE_FIELD(value, num_bits, bit_num) (((value) & ((1 << (num_bits)) - 1)) << (bit_num)) ++ ++typedef enum hipox_dma_mode { ++ HIPOX_DMA_MODE_FIXED, ++ HIPOX_DMA_MODE_INC ++} hipox_dma_mode_t; ++ ++typedef enum hipox_dma_direction { ++ HIPOX_DMA_TO_DEVICE, ++ HIPOX_DMA_FROM_DEVICE ++} hipox_dma_direction_t; ++ ++/* The available buses to which the DMA controller is attached */ ++typedef enum hipox_dma_transfer_bus ++{ ++ HIPOX_DMA_SIDE_A, ++ HIPOX_DMA_SIDE_B ++} hipox_dma_transfer_bus_t; ++ ++/* Direction of data flow between the DMA controller's pair of interfaces */ ++typedef enum hipox_dma_transfer_direction ++{ ++ HIPOX_DMA_A_TO_A, ++ HIPOX_DMA_B_TO_A, ++ HIPOX_DMA_A_TO_B, ++ HIPOX_DMA_B_TO_B ++} hipox_dma_transfer_direction_t; ++ ++/* The available data widths */ ++typedef enum hipox_dma_transfer_width ++{ ++ HIPOX_DMA_TRANSFER_WIDTH_8BITS, ++ HIPOX_DMA_TRANSFER_WIDTH_16BITS, ++ HIPOX_DMA_TRANSFER_WIDTH_32BITS ++} hipox_dma_transfer_width_t; ++ ++/* The mode of the DMA transfer */ ++typedef enum hipox_dma_transfer_mode ++{ ++ HIPOX_DMA_TRANSFER_MODE_SINGLE, ++ HIPOX_DMA_TRANSFER_MODE_BURST ++} hipox_dma_transfer_mode_t; ++ ++/* The available transfer targets */ ++typedef enum hipox_dma_dreq ++{ ++ HIPOX_DMA_DREQ_SATA = 0, ++ HIPOX_DMA_DREQ_MEMORY = 15 ++} hipox_dma_dreq_t; ++ ++typedef struct hipox_dma_device_settings { ++ unsigned long address_; ++ unsigned fifo_size_; // Chained transfers must take account of FIFO offset at end of previous transfer ++ unsigned char dreq_; ++ unsigned read_eot_:1; ++ unsigned read_final_eot_:1; ++ unsigned write_eot_:1; ++ unsigned write_final_eot_:1; ++ unsigned bus_:1; ++ unsigned width_:2; ++ unsigned transfer_mode_:1; ++ unsigned address_mode_:1; ++ unsigned address_really_fixed_:1; ++} hipox_dma_device_settings_t; ++ ++static const int MAX_NO_ERROR_LOOPS = 100000; /* 1 second in units of 10uS */ ++static const int MAX_DMA_XFER_LOOPS = 300000; /* 30 seconds in units of 100uS */ ++static const int MAX_DMA_ABORT_LOOPS = 10000; /* 0.1 second in units of 10uS */ ++static const int MAX_SRC_READ_LOOPS = 10000; /* 0.1 second in units of 10uS */ ++static const int MAX_SRC_WRITE_LOOPS = 10000; /* 0.1 second in units of 10uS */ ++static const int MAX_NOT_BUSY_LOOPS = 10000; /* 1 second in units of 100uS */ ++ ++/* The internal SATA drive on which we should attempt to find partitions */ ++static volatile u32* sata_regs_base[2] = ++{ ++ (volatile u32*)SATA_0_REGS_BASE, ++ (volatile u32*)SATA_1_REGS_BASE, ++ ++}; ++static u32 wr_sata_orb1[2] = { 0, 0 }; ++static u32 wr_sata_orb2[2] = { 0, 0 }; ++static u32 wr_sata_orb3[2] = { 0, 0 }; ++static u32 wr_sata_orb4[2] = { 0, 0 }; ++ ++static hipox_dma_device_settings_t hipox_sata_dma_settings = { ++ .address_ = SATA_DATA_BASE_PA, ++ .fifo_size_ = 16, ++ .dreq_ = HIPOX_DMA_DREQ_SATA, ++ .read_eot_ = 0, ++ .read_final_eot_ = 1, ++ .write_eot_ = 0, ++ .write_final_eot_ = 1, ++ .bus_ = HIPOX_DMA_SIDE_A, ++ .width_ = HIPOX_DMA_TRANSFER_WIDTH_32BITS, ++ .transfer_mode_ = HIPOX_DMA_TRANSFER_MODE_BURST, ++ .address_mode_ = HIPOX_DMA_MODE_FIXED, ++ .address_really_fixed_ = 0 ++}; ++ ++hipox_dma_device_settings_t hipox_ram_dma_settings = { ++ .address_ = 0, ++ .fifo_size_ = 0, ++ .dreq_ = HIPOX_DMA_DREQ_MEMORY, ++ .read_eot_ = 1, ++ .read_final_eot_ = 1, ++ .write_eot_ = 1, ++ .write_final_eot_ = 1, ++ .bus_ = HIPOX_DMA_SIDE_B, ++ .width_ = HIPOX_DMA_TRANSFER_WIDTH_32BITS, ++ .transfer_mode_ = HIPOX_DMA_TRANSFER_MODE_BURST, ++ .address_mode_ = HIPOX_DMA_MODE_FIXED, ++ .address_really_fixed_ = 1 ++}; ++ ++static void xfer_wr_shadow_to_orbs(int device) ++{ ++ *(sata_regs_base[device] + SATA_ORB1_OFF) = wr_sata_orb1[device]; ++ *(sata_regs_base[device] + SATA_ORB2_OFF) = wr_sata_orb2[device]; ++ *(sata_regs_base[device] + SATA_ORB3_OFF) = wr_sata_orb3[device]; ++ *(sata_regs_base[device] + SATA_ORB4_OFF) = wr_sata_orb4[device]; ++} ++ ++static inline void device_select(int device) ++{ ++ /* master/slave has no meaning to SATA core */ ++} ++ ++static int disk_present[CONFIG_SYS_IDE_MAXDEVICE]; ++ ++#include <ata.h> ++ ++unsigned char hipox_sata_inb(int device, int port) ++{ ++ unsigned char val = 0; ++ ++ /* Only permit accesses to disks found to be present during ide_preinit() */ ++ if (!disk_present[device]) { ++ return ATA_STAT_FAULT; ++ } ++ ++ device_select(device); ++ ++ switch (port) { ++ case ATA_PORT_CTL: ++ val = (*(sata_regs_base[device] + SATA_ORB4_OFF) & (0xFFUL << SATA_CTL_BIT)) >> SATA_CTL_BIT; ++ break; ++ case ATA_PORT_FEATURE: ++ val = (*(sata_regs_base[device] + SATA_ORB2_OFF) & (0xFFUL << SATA_FEATURE_BIT)) >> SATA_FEATURE_BIT; ++ break; ++ case ATA_PORT_NSECT: ++ val = (*(sata_regs_base[device] + SATA_ORB2_OFF) & (0xFFUL << SATA_NSECT_BIT)) >> SATA_NSECT_BIT; ++ break; ++ case ATA_PORT_LBAL: ++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_LBAL_BIT)) >> SATA_LBAL_BIT; ++ break; ++ case ATA_PORT_LBAM: ++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_LBAM_BIT)) >> SATA_LBAM_BIT; ++ break; ++ case ATA_PORT_LBAH: ++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_LBAH_BIT)) >> SATA_LBAH_BIT; ++ break; ++ case ATA_PORT_DEVICE: ++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_HOB_LBAH_BIT)) >> SATA_HOB_LBAH_BIT; ++ val |= (*(sata_regs_base[device] + SATA_ORB1_OFF) & (0xFFUL << SATA_DEVICE_BIT)) >> SATA_DEVICE_BIT; ++ break; ++ case ATA_PORT_COMMAND: ++ val = (*(sata_regs_base[device] + SATA_ORB2_OFF) & (0xFFUL << SATA_COMMAND_BIT)) >> SATA_COMMAND_BIT; ++ val |= ATA_STAT_DRQ ; ++ break; ++ default: ++ printf("ide_inb() Unknown port = %d\n", port); ++ break; ++ } ++ ++// printf("inb: %d:%01x => %02x\n", device, port, val); ++ ++ return val; ++} ++ ++/** ++ * Possible that ATA status will not become no-error, so must have timeout ++ * @returns An int which is zero on error ++ */ ++static inline int wait_no_error(int device) ++{ ++ int status = 0; ++ ++ /* Check for ATA core error */ ++ if (*(sata_regs_base[device] + SATA_INT_STATUS_OFF) & (1 << SATA_INT_STATUS_ERROR_BIT)) { ++ printf("wait_no_error() SATA core flagged error\n"); ++ } else { ++ int loops = MAX_NO_ERROR_LOOPS; ++ do { ++ /* Check for ATA device error */ ++ if (!(hipox_sata_inb(device, ATA_PORT_COMMAND) & (1 << ATA_STATUS_ERR_BIT))) { ++ status = 1; ++ break; ++ } ++ udelay(10); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("wait_no_error() Timed out of wait for SATA no-error condition\n"); ++ } ++ } ++ ++ return status; ++} ++ ++/** ++ * Expect SATA command to always finish, perhaps with error ++ * @returns An int which is zero on error ++ */ ++static inline int wait_sata_command_not_busy(int device) ++{ ++ /* Wait for data to be available */ ++ int status = 0; ++ int loops = MAX_NOT_BUSY_LOOPS; ++ do { ++ if (!(*(sata_regs_base[device] + SATA_COMMAND_OFF) & (1 << SATA_CMD_BUSY_BIT) )) { ++ status = 1; ++ break; ++ } ++ udelay(100); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("wait_sata_command_not_busy() Timed out of wait for SATA command to finish\n"); ++ } ++ ++ return status; ++} ++ ++void hipox_sata_outb(int device, int port, unsigned char val) ++{ ++ typedef enum send_method { ++ SEND_NONE, ++ SEND_SIMPLE, ++ SEND_CMD, ++ SEND_CTL, ++ } send_method_t; ++ ++ /* Only permit accesses to disks found to be present during ide_preinit() */ ++ if (!disk_present[device]) { ++ return; ++ } ++ ++// printf("outb: %d:%01x <= %02x\n", device, port, val); ++ ++ device_select(device); ++ ++ send_method_t send_regs = SEND_NONE; ++ switch (port) { ++ case ATA_PORT_CTL: ++ wr_sata_orb4[device] &= ~(0xFFUL << SATA_CTL_BIT); ++ wr_sata_orb4[device] |= (val << SATA_CTL_BIT); ++ send_regs = SEND_CTL; ++ break; ++ case ATA_PORT_FEATURE: ++ wr_sata_orb2[device] &= ~(0xFFUL << SATA_FEATURE_BIT); ++ wr_sata_orb2[device] |= (val << SATA_FEATURE_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_NSECT: ++ wr_sata_orb2[device] &= ~(0xFFUL << SATA_NSECT_BIT); ++ wr_sata_orb2[device] |= (val << SATA_NSECT_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_LBAL: ++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAL_BIT); ++ wr_sata_orb3[device] |= (val << SATA_LBAL_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_LBAM: ++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAM_BIT); ++ wr_sata_orb3[device] |= (val << SATA_LBAM_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_LBAH: ++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAH_BIT); ++ wr_sata_orb3[device] |= (val << SATA_LBAH_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_DEVICE: ++ wr_sata_orb1[device] &= ~(0xFFUL << SATA_DEVICE_BIT); ++ wr_sata_orb1[device] |= ((val & 0xf0) << SATA_DEVICE_BIT); ++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_HOB_LBAH_BIT); ++ wr_sata_orb3[device] |= ((val & 0x0f) << SATA_HOB_LBAH_BIT); ++ send_regs = SEND_SIMPLE; ++ break; ++ case ATA_PORT_COMMAND: ++ wr_sata_orb2[device] &= ~(0xFFUL << SATA_COMMAND_BIT); ++ wr_sata_orb2[device] |= (val << SATA_COMMAND_BIT); ++ send_regs = SEND_CMD; ++ break; ++ default: ++ printf("ide_outb() Unknown port = %d\n", port); ++ } ++ ++ u32 command; ++ switch (send_regs) { ++ case SEND_CMD: ++ wait_sata_command_not_busy(device); ++ command = *(sata_regs_base[device] + SATA_COMMAND_OFF); ++ command &= ~SATA_OPCODE_MASK; ++ command |= SATA_CMD_WRITE_TO_ORB_REGS; ++ xfer_wr_shadow_to_orbs(device); ++ wait_sata_command_not_busy(device); ++ *(sata_regs_base[device] + SATA_COMMAND_OFF) = command; ++ if (!wait_no_error(device)) { ++ printf("hipox_sata_outb() Wait for ATA no-error timed-out\n"); ++ } ++ break; ++ case SEND_CTL: ++ wait_sata_command_not_busy(device); ++ command = *(sata_regs_base[device] + SATA_COMMAND_OFF); ++ command &= ~SATA_OPCODE_MASK; ++ command |= SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND; ++ xfer_wr_shadow_to_orbs(device); ++ wait_sata_command_not_busy(device); ++ *(sata_regs_base[device] + SATA_COMMAND_OFF) = command; ++ if (!wait_no_error(device)) { ++ printf("hipox_sata_outb() Wait for ATA no-error timed-out\n"); ++ } ++ break; ++ default: ++ break; ++ } ++} ++ ++static u32 encode_start(u32 ctrl_status) ++{ ++ return ctrl_status & ~DMA_CTRL_STATUS_PAUSE; ++} ++ ++static void dma_start(void) ++{ ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = ++ encode_start(*(DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS))); ++} ++ ++static unsigned long encode_control_status( ++ hipox_dma_device_settings_t* src_settings, ++ hipox_dma_device_settings_t* dst_settings) ++{ ++ unsigned long ctrl_status; ++ hipox_dma_transfer_direction_t direction; ++ ++ ctrl_status = DMA_CTRL_STATUS_PAUSE; // Paused ++ ctrl_status |= DMA_CTRL_STATUS_FAIR_SHARE_ARB; // High priority ++ ctrl_status |= (src_settings->dreq_ << DMA_CTRL_STATUS_SRC_DREQ_SHIFT); // Dreq ++ ctrl_status |= (dst_settings->dreq_ << DMA_CTRL_STATUS_DEST_DREQ_SHIFT); // Dreq ++ ctrl_status &= ~DMA_CTRL_STATUS_RESET; // !RESET ++ ++ // Use new interrupt clearing register ++ ctrl_status |= DMA_CTRL_STATUS_INTR_CLEAR_ENABLE; ++ ++ // Setup the transfer direction and burst/single mode for the two DMA busses ++ if (src_settings->bus_ == HIPOX_DMA_SIDE_A) { ++ // Set the burst/single mode for bus A based on src device's settings ++ if (src_settings->transfer_mode_ == HIPOX_DMA_TRANSFER_MODE_BURST) { ++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A; ++ } ++ ++ if (dst_settings->bus_ == HIPOX_DMA_SIDE_A) { ++ direction = HIPOX_DMA_A_TO_A; ++ } else { ++ direction = HIPOX_DMA_A_TO_B; ++ ++ // Set the burst/single mode for bus B based on dst device's settings ++ if (dst_settings->transfer_mode_ == HIPOX_DMA_TRANSFER_MODE_BURST) { ++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B; ++ } ++ } ++ } else { ++ // Set the burst/single mode for bus B based on src device's settings ++ if (src_settings->transfer_mode_ == HIPOX_DMA_TRANSFER_MODE_BURST) { ++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B; ++ } ++ ++ if (dst_settings->bus_ == HIPOX_DMA_SIDE_A) { ++ direction = HIPOX_DMA_B_TO_A; ++ ++ // Set the burst/single mode for bus A based on dst device's settings ++ if (dst_settings->transfer_mode_ == HIPOX_DMA_TRANSFER_MODE_BURST) { ++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A; ++ } ++ } else { ++ direction = HIPOX_DMA_B_TO_B; ++ } ++ } ++ ctrl_status |= (direction << DMA_CTRL_STATUS_DIR_SHIFT); ++ ++ // Setup source address mode fixed or increment ++ if (src_settings->address_mode_ == HIPOX_DMA_MODE_FIXED) { ++ // Fixed address ++ ctrl_status &= ~(DMA_CTRL_STATUS_SRC_ADR_MODE); ++ ++ // Set up whether fixed address is _really_ fixed ++ if (src_settings->address_really_fixed_) { ++ ctrl_status |= DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED; ++ } ++ } else { ++ // Incrementing address ++ ctrl_status |= DMA_CTRL_STATUS_SRC_ADR_MODE; ++ ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED; ++ } ++ ++ // Setup destination address mode fixed or increment ++ if (dst_settings->address_mode_ == HIPOX_DMA_MODE_FIXED) { ++ // Fixed address ++ ctrl_status &= ~(DMA_CTRL_STATUS_DEST_ADR_MODE); ++ ++ // Set up whether fixed address is _really_ fixed ++ if (dst_settings->address_really_fixed_) { ++ ctrl_status |= DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED; ++ } else { ++ ctrl_status &= ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED; ++ } ++ } else { ++ // Incrementing address ++ ctrl_status |= DMA_CTRL_STATUS_DEST_ADR_MODE; ++ ctrl_status &= ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED; ++ } ++ ++ // Set up the width of the transfers on the DMA buses ++ ctrl_status |= (src_settings->width_ << DMA_CTRL_STATUS_SRC_WIDTH_SHIFT); ++ ctrl_status |= (dst_settings->width_ << DMA_CTRL_STATUS_DEST_WIDTH_SHIFT); ++ ++ // Setup the priority arbitration scheme ++ ctrl_status &= ~DMA_CTRL_STATUS_STARVE_LOW_PRIORITY; // !Starve low priority ++ ++ return ctrl_status; ++} ++ ++static u32 encode_final_eot( ++ hipox_dma_device_settings_t* src_settings, ++ hipox_dma_device_settings_t* dst_settings, ++ unsigned long length) ++{ ++ // Write the length, with EOT configuration for a final transfer ++ unsigned long encoded = length; ++ if (dst_settings->write_final_eot_) { ++ encoded |= DMA_BYTE_CNT_WR_EOT_MASK; ++ } else { ++ encoded &= ~DMA_BYTE_CNT_WR_EOT_MASK; ++ } ++ if (src_settings->read_final_eot_) { ++ encoded |= DMA_BYTE_CNT_RD_EOT_MASK; ++ } else { ++ encoded &= ~DMA_BYTE_CNT_RD_EOT_MASK; ++ } ++ return encoded; ++} ++ ++static void dma_start_write(ulong* buffer, int num_bytes) ++{ ++ // Assemble complete memory settings ++ hipox_dma_device_settings_t mem_settings = hipox_ram_dma_settings; ++ mem_settings.address_ = (unsigned long)buffer; ++ mem_settings.address_mode_ = HIPOX_DMA_MODE_INC; ++ ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = encode_control_status(&mem_settings, &hipox_sata_dma_settings); ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_SRC_ADR) = mem_settings.address_; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_DST_ADR) = hipox_sata_dma_settings.address_; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BYTE_CNT) = encode_final_eot(&mem_settings, &hipox_sata_dma_settings, num_bytes); ++ ++ dma_start(); ++} ++ ++static void dma_start_read(ulong* buffer, int num_bytes) ++{ ++ // Assemble complete memory settings ++ hipox_dma_device_settings_t mem_settings = hipox_ram_dma_settings; ++ mem_settings.address_ = (unsigned long)buffer; ++ mem_settings.address_mode_ = HIPOX_DMA_MODE_INC; ++ ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = encode_control_status(&hipox_sata_dma_settings, &mem_settings); ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_SRC_ADR) = hipox_sata_dma_settings.address_; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_DST_ADR) = mem_settings.address_; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BYTE_CNT) = encode_final_eot(&hipox_sata_dma_settings, &mem_settings, num_bytes); ++ ++ dma_start(); ++} ++ ++static inline int dma_busy(void) ++{ ++ return (*DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS)) & DMA_CTRL_STATUS_IN_PROGRESS; ++} ++ ++static int wait_dma_not_busy(int device) ++{ ++ unsigned int cleanup_required = 0; ++ ++ /* Poll for DMA completion */ ++ int loops = MAX_DMA_XFER_LOOPS; ++ do { ++ if (!dma_busy()) { ++ break; ++ } ++ udelay(100); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("wait_dma_not_busy() Timed out of wait for DMA not busy\n"); ++ cleanup_required = 1; ++ } ++ ++ if (cleanup_required) { ++ /* Abort DMA to make sure it has finished. */ ++ unsigned long ctrl_status = *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS); ++ ctrl_status |= DMA_CTRL_STATUS_RESET; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = ctrl_status; ++ ++ // Wait for the channel to become idle - should be quick as should ++ // finish after the next AHB single or burst transfer ++ loops = MAX_DMA_ABORT_LOOPS; ++ do { ++ if (!(*DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) & DMA_CTRL_STATUS_IN_PROGRESS)) { ++ break; ++ } ++ udelay(10); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("wait_dma_not_busy() Timed out of wait for DMA channel abort\n"); ++ } else { ++ /* Successfully cleanup the DMA channel */ ++ cleanup_required = 0; ++ } ++ ++ // Deassert reset for the channel ++ ctrl_status = *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS); ++ ctrl_status &= ~DMA_CTRL_STATUS_RESET; ++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = ctrl_status; ++ } ++ ++ return !cleanup_required; ++} ++ ++/** ++ * Possible that ATA status will not become not-busy, so must have timeout ++ */ ++static unsigned int wait_not_busy(int device, unsigned long timeout_secs) ++{ ++ int busy = 1; ++ unsigned long loops = (timeout_secs * 1000) / 50; ++ do { ++ // Test the ATA status register BUSY flag ++ if (!((*(sata_regs_base[device] + SATA_ORB2_OFF) >> SATA_COMMAND_BIT) & (1UL << ATA_STATUS_BSY_BIT))) { ++ /* Not busy, so stop polling */ ++ busy = 0; ++ break; ++ } ++ ++ // Wait for 50mS before sampling ATA status register again ++ udelay(50000); ++ } while (--loops); ++ ++ return busy; ++} ++ ++void hipox_sata_output_data(int device, ulong *sect_buf, int words) ++{ ++ /* Only permit accesses to disks found to be present during ide_preinit() */ ++ if (!disk_present[device]) { ++ return; ++ } ++ ++ /* Select the required internal SATA drive */ ++ device_select(device); ++ ++ /* Start the DMA channel sending data from the passed buffer to the SATA core */ ++ dma_start_write(sect_buf, words << 2); ++ ++ /* Don't know why we need this delay, but without it the wait for DMA not ++ busy times soemtimes out, e.g. when saving environment to second disk */ ++ udelay(1000); ++ ++ /* Wait for DMA to finish */ ++ if (!wait_dma_not_busy(device)) { ++ printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n", device); ++ } ++ ++ /* Sata core should finish after DMA */ ++ if (wait_not_busy(device, 30)) { ++ printf("Timed out of wait for SATA device %d to have BUSY clear\n", device); ++ } ++ if (!wait_no_error(device)) { ++ printf("hipox_sata_output_data() Wait for ATA no-error timed-out\n"); ++ } ++} ++ ++void hipox_sata_input_data(int device, ulong *sect_buf, int words) ++{ ++ /* Only permit accesses to disks found to be present during ide_preinit() */ ++ if (!disk_present[device]) { ++ return; ++ } ++ ++ /* Select the required internal SATA drive */ ++ device_select(device); ++ ++ /* Start the DMA channel receiving data from the SATA core into the passed buffer */ ++ dma_start_read(sect_buf, words << 2); ++ ++ /* Sata core should finish before DMA */ ++ if (wait_not_busy(device, 30)) { ++ printf("Timed out of wait for SATA device %d to have BUSY clear\n", device); ++ } ++ if (!wait_no_error(device)) { ++ printf("hipox_sata_output_data() Wait for ATA no-error timed-out\n"); ++ } ++ ++ /* Wait for DMA to finish */ ++ if (!wait_dma_not_busy(device)) { ++ printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n", device); ++ } ++} ++ ++static u32 scr_read(int device, unsigned int sc_reg) ++{ ++ /* Setup adr of required register. std regs start eight into async region */ ++ *(sata_regs_base[device] + SATA_LINK_RD_ADDR) = sc_reg*4 + SATA_STD_ASYNC_REGS_OFF; ++ ++ /* Wait for data to be available */ ++ int loops = MAX_SRC_READ_LOOPS; ++ do { ++ if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) { ++ break; ++ } ++ udelay(10); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("scr_read() Timed out of wait for read completion\n"); ++ } ++ ++ /* Read the data from the async register */ ++ return *(sata_regs_base[device] + SATA_LINK_DATA); ++} ++ ++static void scr_write(int device, unsigned int sc_reg, u32 val) ++{ ++ /* Setup the data for the write */ ++ *(sata_regs_base[device] + SATA_LINK_DATA) = val; ++ ++ /* Setup adr of required register. std regs start eight into async region */ ++ *(sata_regs_base[device] + SATA_LINK_WR_ADDR) = sc_reg*4 + SATA_STD_ASYNC_REGS_OFF; ++ ++ /* Wait for data to be written */ ++ int loops = MAX_SRC_WRITE_LOOPS; ++ do { ++ if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) { ++ break; ++ } ++ udelay(10); ++ } while (--loops); ++ ++ if (!loops) { ++ printf("scr_write() Timed out of wait for write completion\n"); ++ } ++} ++ ++#define PHY_LOOP_COUNT 25 /* Wait for upto 5 seconds for PHY to be found */ ++static int phy_reset(int device) ++{ ++#ifdef FPGA ++ /* The FPGA thinks it can do 3G when infact only 1.5G is possible, so limit ++ it to Gen-1 SATA (1.5G) */ ++ scr_write(device, SATA_SCR_CONTROL, 0x311); /* Issue phy wake & core reset */ ++ scr_read(device, SATA_SCR_STATUS); /* Dummy read; flush */ ++ udelay(1000); ++ scr_write(device, SATA_SCR_CONTROL, 0x310); /* Issue phy wake & clear core reset */ ++#else ++ scr_write(device, SATA_SCR_CONTROL, 0x301); /* Issue phy wake & core reset */ ++ scr_read(device, SATA_SCR_STATUS); /* Dummy read; flush */ ++ udelay(1000); ++ scr_write(device, SATA_SCR_CONTROL, 0x300); /* Issue phy wake & clear core reset */ ++#endif ++ /* Wait for upto 5 seconds for PHY to become ready */ ++ int phy_status = 0; ++ int loops = 0; ++ do { ++ udelay(200000); ++ if ((scr_read(device, SATA_SCR_STATUS) & 0xf) != 1) { ++ phy_status = 1; ++ break; ++ } ++ printf("No SATA PHY found\n"); ++ } while (++loops < PHY_LOOP_COUNT); ++ ++ if (phy_status) { ++ udelay(500000); /* wait half a second */ ++ } ++ return phy_status; ++} ++ ++#define FIS_LOOP_COUNT 25 /* Wait for upto 5 seconds for FIS to be received */ ++static int wait_FIS(int device) ++{ ++ int status = 0; ++ int loops = 0; ++ ++ do { ++ udelay(200000); ++ if (hipox_sata_inb(device, ATA_PORT_NSECT) > 0) { ++ status = 1; ++ break; ++ } ++ } while (++loops < FIS_LOOP_COUNT); ++ ++ return status; ++} ++ ++int ide_preinit(void) ++{ ++ int num_disks_found = 0; ++ ++ /* Initialise records of which disks are present to all present */ ++ int i; ++ for (i=0; i < CONFIG_SYS_IDE_MAXDEVICE; i++) { ++ disk_present[i] = 1; ++ } ++ ++//udelay(1000000); ++ /* Enable clocks to SATA and DMA cores */ ++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_SATA_BIT); ++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_DMA_BIT); ++ ++ /* Block reset SATA and DMA cores */ ++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_SATA_BIT) | ++ (1UL << SYS_CTRL_RSTEN_SATA_LINK_BIT) | ++ (1UL << SYS_CTRL_RSTEN_SATA_PHY_BIT) | ++ (1UL << SYS_CTRL_RSTEN_DMA_BIT); ++ udelay(50); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_SATA_PHY_BIT); ++ udelay(50); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_SATA_LINK_BIT) | ++ (1UL << SYS_CTRL_RSTEN_SATA_BIT); ++ udelay(50); ++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_DMA_BIT); ++ udelay(50); ++//udelay(1000000); ++ ++ /* disable and clear core interrupts */ ++ *((unsigned long*)SATA_HOST_REGS_BASE + SATA_INT_ENABLE_CLR_OFF) = ~0UL; ++ *((unsigned long*)SATA_HOST_REGS_BASE + SATA_INT_CLR_OFF) = ~0UL; ++ ++ int device; ++ for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) { ++ int found = 0; ++ int retries = 1; ++ ++ /* Disable SATA interrupts */ ++ *(sata_regs_base[device] + SATA_INT_ENABLE_CLR_OFF) = ~0UL; ++ ++ /* Clear any pending SATA interrupts */ ++ *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL; ++ ++ do { ++ /* clear sector count register for FIS detection */ ++ hipox_sata_outb(device, ATA_PORT_NSECT, 0); ++ ++ /* Get the PHY working */ ++ if (!phy_reset(device)) { ++ printf("SATA PHY not ready for device %d\n", device); ++ break; ++ } ++ ++ if (!wait_FIS(device)) { ++ printf("No FIS received from device %d\n", device); ++ } else { ++ if ((scr_read(device, SATA_SCR_STATUS) & 0xf) == 0x3) { ++ if (wait_not_busy(device, 30)) { ++ printf("Timed out of wait for SATA device %d to have BUSY clear\n", device); ++ } else { ++ ++num_disks_found; ++ found = 1; ++ } ++ } else { ++ printf("No SATA device %d found, PHY status = 0x%08x\n", ++ device, scr_read(device, SATA_SCR_STATUS)); ++ } ++ break; ++ } ++ } while (retries--) ; ++ ++ /* Record whether disk is present, so won't attempt to access it later */ ++ disk_present[device] = found; ++ } ++ ++ /* post disk detection clean-up */ ++ for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) { ++ if ( disk_present[device] ) { ++ /* set as ata-5 (28-bit) */ ++ *(sata_regs_base[device] + SATA_DRIVE_CONTROL_OFF) = 0UL; ++ ++ /* clear phy/link errors */ ++ scr_write(device, SATA_SCR_ERROR, ~0); ++ ++ /* clear host errors */ ++ *(sata_regs_base[device] + SATA_CONTROL_OFF) |= SATA_SCTL_CLR_ERR; ++ ++ /* clear interrupt register as this clears the error bit in the IDE ++ status register */ ++ *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL; ++ } ++ } ++ ++ ++ return !num_disks_found; ++} ++ +diff -Nurd u-boot-2009.03.orig/board/hipox/platform-800.S u-boot-2009.03/board/hipox/platform-800.S +--- u-boot-2009.03.orig/board/hipox/platform-800.S 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/platform-800.S 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,254 @@ ++/* ++ * Board specific setup info ++ * ++ * (C) Copyright 2005 ++ * Oxford Semiconductor Ltd ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <config.h> ++#include <version.h> ++ ++/* use estimate of processor speed to calculate number of cycles delay */ ++/* delay count is nominal (PLL200 frequency x delay time) / loop count ++ * expressing 200us as 200/1000000 and re-arranging gives the expression below ++ */ ++ ++#define DELAY_200US ((NOMINAL_ARMCLK / (5 * 1000000)) * 200) ++/* this is 8 cycles of ? so choose 8 resulting in 40 cycles */ ++#define DELAY_1S ((DELAY_200US) * 5000) ++#define DELAY_8 8 ++#define DELAY_200 200 ++ ++.globl platformsetup ++platformsetup: ++/* register allocations ++ * r0 - delay counter and scratch ++ * r1 - address register ++ * r2 - data register ++ * r3 - index to table pointer ++ * r4 - iteration counter. ++ * ++ * r5 - hold return address. ++ * lr - (R14) link register ++ * pc - (R15) program counter. ++ */ ++ ++#ifdef INITIALISE_SDRAM ++/* ++ * Check that not in SDRAM execution. Suicide if re-initialise DRAM. ++ * Controller function is linked to execute in SDRAM must be in ROM if not ++ * there. Check for wrong place. ++ */ ++ adrl r0, platformsetup /* Relative location of function start.*/ ++ ldr r1, _platformsetup ++ cmp r0, r1 ++ moveq pc, lr ++#else ++ mov pc, lr ++#endif ++ ++ /* Establish a working setup for the SDRAM */ ++ mov r6, lr ++ ++#ifdef HIPOX_OVERCLOCK ++ /* Delay so the broken JTAG can get control */ ++ ldr r0, =DELAY_1S ++ bl delay ++ ++ /* Configure the PLL to run faster */ ++ ldr r1, =SYS_CTRL_PLLSYS_CTRL ++ ldr r2, =SYS_CTRL_PLLSYS_KEY_CTRL ++ ++ /* 0xBEADFACE -> PLL_KEY */ ++ /* Bypass PLL */ ++ ldr r3, [r1] ++ ldr r5, =0x20000 ++ orr r3, r3, r5 ++ ldr r4, =0xbeadface ++ str r4, [r2] ++ str r3, [r1] ++ ++ /* 0xBEADFACE -> PLL_KEY */ ++ /* Set m,p and s for PLL at 400MHz */ ++ ldr r5, =0xffff0000 ++ and r3, r3, r5 ++ ldr r5, =HIPOX_OVERCLOCK ++ orr r3, r3, r5 ++ str r4, [r2] ++ str r3, [r1] ++ ++ /* Wait at least 300uS */ ++ ldr r0, =DELAY_200US ++ bl delay ++ ldr r0, =DELAY_200US ++ bl delay ++ ++ /* 0xBEADFACE -> PLL_KEY */ ++ /* Disable PLL bypass */ ++ ldr r5, =0xfffdffff ++ and r3, r3, r5 ++ str r4, [r2] ++ str r3, [r1] ++#endif // HIPOX_OVERCLOCK ++ ++ /* Assert reset to the DDR core */ ++ ldr r0, =SYS_CTRL_RSTEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Deassert reset to the DDR core */ ++ ldr r0, =SYS_CTRL_RSTEN_CLR_CTRL ++ str r1, [r0] ++ ++ /* Turn on the DDR core clock */ ++ ldr r0, =SYS_CTRL_CKEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_CKEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Start using the initialisation value list */ ++ adrl r3, init_table ++ ++ /* Copy next 6 entries from DDR init table*/ ++ ldr r4, =6 ++loop0: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop0 ++ ++ /* Delay for 200uS while DRAM controller stabilises. */ ++ ldr r0, =DELAY_200US ++ bl delay ++ ++#if !TEST_BRD ++ /* Copy next entry */ ++ ldr r4, =1 ++loopx: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loopx ++ ++ /* Delay for 200uS while DRAM controller stabilises. */ ++ ldr r0, =DELAY_200US ++ bl delay ++#endif // TEST_BRD ++ ++ /* Copy next entry */ ++ ldr r4, =1 ++loop1: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop1 ++ ++ /* Delay for 200uS while DRAM controller stabilises. */ ++ ldr r0, =DELAY_200US ++ bl delay ++ ++ /* Copy next entry */ ++ ldr r4, =1 ++loop2: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop2 ++ ++ /* Delay for 200uS while DRAM controller stabilises. */ ++ ldr r0, =DELAY_200US ++ bl delay ++ ++ /* Copy next entry */ ++ ldr r4, =1 ++loop3: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop3 ++ ++ /* Delay for 200uS while DRAM controller stabilises. */ ++ ldr r0, =DELAY_200US ++ bl delay ++ ++ /* Copy next 5 entries */ ++ ldr r4, =5 ++loop4: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop4 ++ ++ /* SDRAM initialised so now exit. */ ++ mov lr, r6 ++ mov pc, lr ++ ++/* ++ * delay() ++ * ++ * uses 1 + r0 * 5 cycles ++ */ ++delay: ++ nop ++ nop ++ nop ++ subs r0, r0, #1 ++ bne delay ++ mov pc, lr ++ ++_platformsetup: ++ .word platformsetup ++ ++init_table: ++ /* Table of address, data for loading into the DRAM controller */ ++ /* Configure for a single DDR device */ ++ .word 0x4500002C, 0x08 ++ .word 0x45000038, 0x400 ++ .word 0x45800000, 0x80100000 ++ .word 0x45800004, 0x8000ffff // Enable DDR core and all clients ++ .word 0x45800024, 0x1e4 ++ .word 0x45800014, 0xe0000001 // DLL to automatic with starting value=1 ++/* 200uS delay */ ++#if !TEST_BRD ++ .word 0x45800014, 0xa0000003 // DLL to automatic with offset value=3 ++/* 200uS delay */ ++#endif // TEST_BRD ++#if (MEM_SIZE == 32) ++ .word 0x45800000, 0x801B030C ++#else ++ .word 0x45800000, 0x801D030C ++#endif // MEM_SIZE ++/* 200uS delay */ ++ .word 0x4580000c, 0x80280400 ++/* 200uS delay */ ++ .word 0x4580000c, 0x80210000 ++/* 200uS delay */ ++ .word 0x4580000c, 0x80200063 ++ .word 0x45800028, 0x0000001f // Enable all arbiter features ++ .word 0x45800018, 0x00000000 // Disable all monitoring ++ .word 0x45800010, 0xffffffff // Disable all read buffering, due to h/w bug ++ .word 0x4580002C, 0x00000000 // Do NOT disable HPROT, ie want write coherency ++ ++.ltorg ++ +diff -Nurd u-boot-2009.03.orig/board/hipox/platform-810-466-timings.S u-boot-2009.03/board/hipox/platform-810-466-timings.S +--- u-boot-2009.03.orig/board/hipox/platform-810-466-timings.S 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/platform-810-466-timings.S 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,473 @@ ++/* ++ * Board specific setup info ++ * ++ * (C) Copyright 2005 ++ * Oxford Semiconductor Ltd ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <config.h> ++#include <version.h> ++ ++/* use estimate of processor speed to calculate number of cycles delay */ ++/* delay count is nominal (PLL200 frequency x delay time) / loop count ++ * expressing 200us as 200/1000000 and re-arranging gives the expression below ++ */ ++ ++#define DELAY_200US ((NOMINAL_ARMCLK / (5 * 1000000)) * 200) ++#define DELAY_300US ((NOMINAL_ARMCLK / (5 * 1000000)) * 300) ++/* this is 8 cycles of ? so choose 8 resulting in 40 cycles */ ++#define DELAY_1S ((DELAY_200US) * 5000) ++#define DELAY_8 8 ++#define DELAY_200 200 ++ ++ ++.globl platformsetup ++platformsetup: ++/* register allocations ++ * r0 - delay counter and scratch ++ * r1 - address register ++ * r2 - data register ++ * r3 - index to table pointer ++ * r4 - iteration counter. ++ * ++ * r5 - hold return address. ++ * lr - (R14) link register ++ * pc - (R15) program counter. ++ */ ++ ++#ifdef INITIALISE_SDRAM ++/* ++ * Check that not in SDRAM execution. Suicide if re-initialise DRAM. ++ * Controller function is linked to execute in SDRAM must be in ROM if not ++ * there. Check for wrong place. ++ */ ++ adrl r0, platformsetup /* Relative location of function start.*/ ++ ldr r1, _platformsetup ++ cmp r0, r1 ++ moveq pc, lr ++#else ++ mov pc, lr ++#endif ++ ++#if (FPGA == 1) ++ /* Establish a working setup for the SDRAM */ ++ mov r6, lr ++ ++ /* Assert reset to the DDR core */ ++ ldr r0, =SYS_CTRL_RSTEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Deassert reset to the DDR core */ ++ ldr r0, =SYS_CTRL_RSTEN_CLR_CTRL ++ str r1, [r0] ++ ++ /* Turn on the DDR core clock */ ++ ldr r0, =SYS_CTRL_CKEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_CKEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Start using the initialisation value list */ ++ adrl r3, init_table ++ ++ /* Copy first 6 entries */ ++ ldr r4, =6 ++loop0: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop0 ++ ++ /* Delay for 200uS while DRAM controller stabilises. */ ++ ldr r0, =DELAY_200US ++ bl delay ++ ++ /* Copy next 4 entries */ ++ ldr r4, =4 ++loop1: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop1 ++ ++ /* Wait at least 200 clock cycles. */ ++ ldr r0, =DELAY_200 ++ bl delay ++ ++ /* Copy next 2 entries */ ++ ldr r4, =2 ++loop2: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop2 ++ ++ /* Wait at least 8 clock cycles. */ ++ ldr r0, =DELAY_8 ++ bl delay ++ ++ /* Copy next 9 entries */ ++ ldr r4, =9 ++loop3: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop3 ++ ++ /* SDRAM initialised so now exit. */ ++ mov lr, r6 ++ mov pc, lr ++ ++/* ++ * delay() ++ * ++ * uses 1 + r0 * 5 cycles ++ */ ++delay: ++ nop ++ nop ++ nop ++ subs r0, r0, #1 ++ bne delay ++ mov pc, lr ++ ++_platformsetup: ++ .word platformsetup ++#else // ASIC, (DDR-2) ++/* ++ * Check that not in SDRAM execution. Suicide if re-initialise DRAM. ++ * Controller function is linked to execute in SDRAM must be in ROM if not ++ * there. Check for wrong place. ++ */ ++ /* Establish a working setup for the SDRAM */ ++ mov r6, lr ++ ++#ifdef OVERCLOCK ++ /* ++ change clock speed on chip ++ */ ++ ++ /* read SYS_CTRL_PLLSYS_CTRL into r3*/ ++ mov r5, #0x45000000 ++ ldr r3, [r5, #72] ++ ++ /* load the value at dllkey (0xbeadface) into r7 */ ++ adrl r7, dllkey ++ ldr r7, [r7] ++ ++ /* pll_sys |= 0x20000; */ ++ orr r3, r3, #131072 /* 0x20000 */ ++ ++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */ ++ str r7, [r5, #108] ++ ++ /* write pll_sys (bypass pll)*/ ++ str r3, [r5, #72] ++ ++ /* pll_sys mask out lower 26 bits */ ++ mov r4, r3, lsr #26 ++ mov r4, r4, lsl #26 ++ ++ /* pll_sys |= (26 bits of (m,p and s)) */ ++ ldr r3, =OVERCLOCK ++ orr r4, r4, r3 ++ ++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */ ++ str r7, [r5, #108] ++ ++ /* write pll_sys (with new pll speeds) */ ++ str r4, [r5, #72] ++ ++ /* delay 300us */ ++ ldr r0, =DELAY_300US ++ bl delay ++ ++ /* clear bypass pll bit */ ++ bic r4, r4, #131072 /* 0x20000 */ ++ ++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */ ++ str r7, [r5, #108] ++ ++ /* write pll_sys (with new pll speeds and pll un-bypassed) */ ++ str r4, [r5, #72] ++#endif /* OVERCLOCK */ ++ ++ /* Turn on the DDR core and phy clocks */ ++ ldr r0, =SYS_CTRL_CKEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_CKEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_CKEN_DDR_PHY_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Assert reset to the DDR core and phy */ ++ ldr r0, =SYS_CTRL_RSTEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_PHY_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Deassert reset to the DDR core and phy*/ ++ ldr r0, =SYS_CTRL_RSTEN_CLR_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_PHY_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Start using the initialisation value list */ ++ adrl r3, init_table ++ ++ /* Copy first 14 entries of DDR core setup (section A)*/ ++ ldr r4, =14 ++loop0: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop0 ++ ++ /* Delay for 200uS while DDR controller stabilises. */ ++ ldr r0, =DELAY_200US ++ bl delay ++ ++ /* Copy next 13 entries of DDR device commands (section B)*/ ++ ldr r4, =13 ++loop1: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ ++ /* Wait at least 200 clock cycles between ram chip command writes */ ++ ldr r0, =DELAY_200 ++ bl delay ++ ++ subs r4, r4, #1 ++ bne loop1 ++ ++ /* Copy final DDR controller setup to set memory size/banks (section C)*/ ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ ++#if (PROBE_MEM_SIZE == 1) ++ /* Load the probe values into SDRAM */ ++ adrl r3, probe_table ++ mov r4, #4 ++.globl pl1 ++pl1: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne pl1 ++ ++ /* Get the current contents of the DDR controller core's config register */ ++ adrl r1, ddr_config_reg ++ ldr r1, [r1] ++ ldr r1, [r1] ++ ++ /* Zero the number of banks field - bit 23*/ ++ mov r2, #1 ++ bic r1, r1, r2, lsl #23 ++ ++ /* Zero the size field - bits 17-20 inclusive */ ++ mov r2, #15 ++ bic r1, r1, r2, lsl #17 ++ ++ /* First probe location tells us the SDRAM size */ ++ adrl r3, probe_table ++ ldr r0, [r3] ++ ldr r0, [r0] ++ ++ /* Is size 64MB? */ ++ ldr r2, [r3, #28] /* Get probe value 4 */ ++ cmp r0, r2 ++ moveq r4, #6 ++ orreq r1, r1, r4, lsl #17 ++ beq pl2 ++ ++ /* Is 128M or 256M so set banks to 8 */ ++ mov r4, #1 ++ orr r1, r1, r4, lsl #23 ++ ++ /* Is size 128MB? */ ++ ldr r2, [r3, #20] /* Get probe value 3 */ ++ cmp r0, r2 ++// moveq r4, #7 ++ moveq r4, #8 /* DDR controller does not work at 128M, use 256M instead ++ orreq r1, r1, r4, lsl #17 ++ beq pl2 ++ ++ /* Must be 256MB, or something is very wrong */ ++ mov r4, #8 ++ orr r1, r1, r4, lsl #17 ++ ++pl2: ++ /* Write the revised contents to the DDR controller core's config register */ ++ adrl r2, ddr_config_reg ++ ldr r2, [r2] ++ str r1, [r2] ++#endif ++ ++ /* SDRAM setup complete */ ++ mov lr, r6 ++ mov pc, lr ++ ++/* ++ * delay() ++ * ++ * uses 1 + r0 * 5 cycles ++ */ ++delay: ++ nop ++ nop ++ nop ++ subs r0, r0, #1 ++ bne delay ++ mov pc, lr ++ ++_platformsetup: ++ .word platformsetup ++#endif ++ ++ ++init_table: ++#if (FPGA == 1) ++ /* Table of address, data for loading into the DRAM controller on FPGA */ ++ .word 0x45800000, 0x000d0000 // Enable the DDR in SDR mode and width 32 bits ++ .word 0x45800034, 0x04442032 // SDR mode timings - #0 ++ .word 0x45800038, 0x570A0907 // SDR mode timings - #1 ++ .word 0x4580003C, 0x00000002 // SDR mode timings - #2 ++ .word 0x45800004, 0x80000000 // Enable DDR core, but not clients yet ++ .word 0x45800014, 0x80000001 // Enable CK and set DLL mode to manual ++/* 200uS delay */ ++ .word 0x4580000c, 0x80200000 // Assert CKE for all further commands ++ .word 0x4580000c, 0x80280400 // Issue precharge to all banks ++ .word 0x4580000c, 0x80200000 // NOP, as only DDR has real command here ++ .word 0x4580000c, 0x80200022 // Set burst length 4, sequential CAS 2 ++/* 200uS delay */ ++ .word 0x4580000c, 0x80280400 // Issue precharge to all banks ++ .word 0x4580000c, 0x80240000 // Issue auto-refresh command, CKE not asserted ++/* 200uS delay */ ++ .word 0x4580000c, 0x80240000 // Issue auto-refresh command, CKE not asserted ++ .word 0x4580000c, 0x80200000 // Assert CKE for all further commands ++ .word 0x4580000c, 0x80200022 // Set burst length 4, sequential CAS 2 ++ .word 0x45800000, 0x000d0186 // SDR, size and width and refresh rate, assuming ++ // 25Mhz clk to SDR, divide down to get 15.625uS ++ // refresh rate ++ .word 0x45800024, 0x00000124 // Set I/O drive strengths ++ .word 0x45800028, 0x0000001f // Enable all arbiter features ++ .word 0x45800018, 0x00000000 // Disable all monitoring ++ .word 0x45800010, 0xFFFFFFFF // Disable all read buffering ++ .word 0x45800004, 0x800000ff // Enable all client interfaces ++#else // ASIC DDR-2 ++ // SECTION A - DDR controller core configuration ++ .word 0x45800000, 0x802d0591 // enable in ddr-2 mode 16 bit wide ++ .word 0x45800034, 0x04442033 // ddr-2 mode timings ++ .word 0x45800038, 0x98110d2f // ddr-2 mode timings ++ .word 0x4580003c, 0x00000c34 // ddr-2 mode timings ++ .word 0x45800054, 0x00072000 // phy-3 settings ++ .word 0x45800050, 0x00022828 // phy-2 settings, start ++ .word 0x45800050, 0x00032828 // phy-2 settings, on ++ .word 0x45800028, 0x0000001f // Enable all arbiter features ++ .word 0x45800018, 0x00000000 // Disable all monitoring ++ .word 0x45800010, 0xffff0000 // Enable all read buffering ++ .word 0x4580002c, 0x00ff00fd // no burst accl, no hprot on arm data ++ .word 0x45800040, 0x00000000 // enable burst and read cache ++ .word 0x45800044, 0xffff0000 // enable write behind prot, disable timeout ++ .word 0x45800004, 0x8000ffff // Enable all client interfaces ++/* 200uS delay after configuring DDR controller core */ ++ ++ // SECTION B - Memory device configuration ++ .word 0x4580000c, 0x807c0000 // exit something or other ++ .word 0x4580000c, 0x803c0000 // nop - wake up ++ .word 0x4580000c, 0x80280400 // precharge all ++ .word 0x4580000c, 0x80220000 // emr2 ++ .word 0x4580000c, 0x80230000 // emr3 ++ ++#if (MEM_ODT == 150) ++ .word 0x4580000c, 0x80210042 // enable dll, odt to 150 ++#elif (MEM_ODT == 75) ++ .word 0x4580000c, 0x80210006 // enable dll, odt to 75 ++#elif (MEM_ODT == 50) ++ .word 0x4580000c, 0x80210046 // enable dll, odt to 50 ++#else ++#error Unsupported memory on-die termination, set MEM_ODT to 50, 75, or 150 ++#endif ++ ++ .word 0x4580000c, 0x80200743 // set WR CL BL and reset dll ++ .word 0x4580000c, 0x80280400 // precharge all ++ .word 0x4580000c, 0x80240000 // auto refresh ++ .word 0x4580000c, 0x80240000 // auto refresh ++ .word 0x4580000c, 0x80200743 // set WR CL BL and reset dll ++ ++#if (MEM_ODT == 150) ++ .word 0x4580000c, 0x802103c2 // enable OCD ++ .word 0x4580000c, 0x80210042 // disable OCD ++#elif (MEM_ODT == 75) ++ .word 0x4580000c, 0x80210386 // enable OCD ++ .word 0x4580000c, 0x80210006 // disable OCD ++#elif (MEM_ODT == 50) ++ .word 0x4580000c, 0x802103c6 // enable OCD ++ .word 0x4580000c, 0x80210046 // disable OCD ++#else ++#error Unsupported memory on-die termination, set MEM_ODT to 50, 75, or 150 ++#endif ++ ++ // SECTION C - Final memory size/bank configuration ++#if (PROBE_MEM_SIZE == 1) ++ .word 0x45800000, 0x80b10591 // 256M, 8 banks, 1425 clocks for 7.8us refresh. ++#elif (MEM_SIZE == 64) ++ .word 0x45800000, 0x802d0591 // 64M, 4 banks, 1425 clocks for 7.8us refresh. ++#elif (MEM_SIZE == 128) ++ .word 0x45800000, 0x80af0591 // 128M, 8 banks, 1425 clocks for 7.8us refresh. ++#elif (MEM_SIZE == 256) ++ .word 0x45800000, 0x80b10591 // 256M, 8 banks, 1425 clocks for 7.8us refresh. ++#else ++#error Unsupported memory size, set MEM_SIZE to 64, 128 or 256 ++#endif ++ ++#endif // FPGA or ASIC ++dllkey: ++ .word 0xbeadface ++ ++ddr_config_reg: ++ .word 0x45800000 ++ ++probe_table: ++ .word 0x48000000, 0x12345678 ++ .word 0x48000040, 0xdeadbeef ++ .word 0x50000000, 0xfafafafa ++ .word 0x50000040, 0xabcdef01 ++ ++.ltorg ++ +diff -Nurd u-boot-2009.03.orig/board/hipox/platform-810.S u-boot-2009.03/board/hipox/platform-810.S +--- u-boot-2009.03.orig/board/hipox/platform-810.S 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/platform-810.S 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,473 @@ ++/* ++ * Board specific setup info ++ * ++ * (C) Copyright 2005 ++ * Oxford Semiconductor Ltd ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <config.h> ++#include <version.h> ++ ++/* use estimate of processor speed to calculate number of cycles delay */ ++/* delay count is nominal (PLL200 frequency x delay time) / loop count ++ * expressing 200us as 200/1000000 and re-arranging gives the expression below ++ */ ++ ++#define DELAY_200US ((NOMINAL_ARMCLK / (5 * 1000000)) * 200) ++#define DELAY_300US ((NOMINAL_ARMCLK / (5 * 1000000)) * 300) ++/* this is 8 cycles of ? so choose 8 resulting in 40 cycles */ ++#define DELAY_1S ((DELAY_200US) * 5000) ++#define DELAY_8 8 ++#define DELAY_200 200 ++ ++ ++.globl lowlevel_init ++lowlevel_init: ++/* register allocations ++ * r0 - delay counter and scratch ++ * r1 - address register ++ * r2 - data register ++ * r3 - index to table pointer ++ * r4 - iteration counter. ++ * ++ * r5 - hold return address. ++ * lr - (R14) link register ++ * pc - (R15) program counter. ++ */ ++ ++#ifdef INITIALISE_SDRAM ++/* ++ * Check that not in SDRAM execution. Suicide if re-initialise DRAM. ++ * Controller function is linked to execute in SDRAM must be in ROM if not ++ * there. Check for wrong place. ++ */ ++ adrl r0, lowlevel_init /* Relative location of function start.*/ ++ ldr r1, _lowlevel_init ++ cmp r0, r1 ++ moveq pc, lr ++#else ++ mov pc, lr ++#endif ++ ++#if (FPGA == 1) ++ /* Establish a working setup for the SDRAM */ ++ mov r6, lr ++ ++ /* Assert reset to the DDR core */ ++ ldr r0, =SYS_CTRL_RSTEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Deassert reset to the DDR core */ ++ ldr r0, =SYS_CTRL_RSTEN_CLR_CTRL ++ str r1, [r0] ++ ++ /* Turn on the DDR core clock */ ++ ldr r0, =SYS_CTRL_CKEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_CKEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Start using the initialisation value list */ ++ adrl r3, init_table ++ ++ /* Copy first 6 entries */ ++ ldr r4, =6 ++loop0: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop0 ++ ++ /* Delay for 200uS while DRAM controller stabilises. */ ++ ldr r0, =DELAY_200US ++ bl delay ++ ++ /* Copy next 4 entries */ ++ ldr r4, =4 ++loop1: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop1 ++ ++ /* Wait at least 200 clock cycles. */ ++ ldr r0, =DELAY_200 ++ bl delay ++ ++ /* Copy next 2 entries */ ++ ldr r4, =2 ++loop2: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop2 ++ ++ /* Wait at least 8 clock cycles. */ ++ ldr r0, =DELAY_8 ++ bl delay ++ ++ /* Copy next 9 entries */ ++ ldr r4, =9 ++loop3: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop3 ++ ++ /* SDRAM initialised so now exit. */ ++ mov lr, r6 ++ mov pc, lr ++ ++/* ++ * delay() ++ * ++ * uses 1 + r0 * 5 cycles ++ */ ++delay: ++ nop ++ nop ++ nop ++ subs r0, r0, #1 ++ bne delay ++ mov pc, lr ++ ++_lowlevel_init: ++ .word lowlevel_init ++#else // ASIC, (DDR-2) ++/* ++ * Check that not in SDRAM execution. Suicide if re-initialise DRAM. ++ * Controller function is linked to execute in SDRAM must be in ROM if not ++ * there. Check for wrong place. ++ */ ++ /* Establish a working setup for the SDRAM */ ++ mov r6, lr ++ ++#ifdef OVERCLOCK ++ /* ++ change clock speed on chip ++ */ ++ ++ /* read SYS_CTRL_PLLSYS_CTRL into r3*/ ++ mov r5, #0x45000000 ++ ldr r3, [r5, #72] ++ ++ /* load the value at dllkey (0xbeadface) into r7 */ ++ adrl r7, dllkey ++ ldr r7, [r7] ++ ++ /* pll_sys |= 0x20000; */ ++ orr r3, r3, #131072 /* 0x20000 */ ++ ++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */ ++ str r7, [r5, #108] ++ ++ /* write pll_sys (bypass pll)*/ ++ str r3, [r5, #72] ++ ++ /* pll_sys mask out lower 26 bits */ ++ mov r4, r3, lsr #26 ++ mov r4, r4, lsl #26 ++ ++ /* pll_sys |= (26 bits of (m,p and s)) */ ++ ldr r3, =OVERCLOCK ++ orr r4, r4, r3 ++ ++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */ ++ str r7, [r5, #108] ++ ++ /* write pll_sys (with new pll speeds) */ ++ str r4, [r5, #72] ++ ++ /* delay 300us */ ++ ldr r0, =DELAY_300US ++ bl delay ++ ++ /* clear bypass pll bit */ ++ bic r4, r4, #131072 /* 0x20000 */ ++ ++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */ ++ str r7, [r5, #108] ++ ++ /* write pll_sys (with new pll speeds and pll un-bypassed) */ ++ str r4, [r5, #72] ++#endif /* OVERCLOCK */ ++ ++ /* Turn on the DDR core and phy clocks */ ++ ldr r0, =SYS_CTRL_CKEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_CKEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_CKEN_DDR_PHY_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Assert reset to the DDR core and phy */ ++ ldr r0, =SYS_CTRL_RSTEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_PHY_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Deassert reset to the DDR core and phy*/ ++ ldr r0, =SYS_CTRL_RSTEN_CLR_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_PHY_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Start using the initialisation value list */ ++ adrl r3, init_table ++ ++ /* Copy first 14 entries of DDR core setup (section A)*/ ++ ldr r4, =14 ++loop0: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop0 ++ ++ /* Delay for 200uS while DDR controller stabilises. */ ++ ldr r0, =DELAY_200US ++ bl delay ++ ++ /* Copy next 13 entries of DDR device commands (section B)*/ ++ ldr r4, =13 ++loop1: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ ++ /* Wait at least 200 clock cycles between ram chip command writes */ ++ ldr r0, =DELAY_200 ++ bl delay ++ ++ subs r4, r4, #1 ++ bne loop1 ++ ++ /* Copy final DDR controller setup to set memory size/banks (section C)*/ ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ ++#if (PROBE_MEM_SIZE == 1) ++ /* Load the probe values into SDRAM */ ++ adrl r3, probe_table ++ mov r4, #4 ++.globl pl1 ++pl1: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne pl1 ++ ++ /* Get the current contents of the DDR controller core's config register */ ++ adrl r1, ddr_config_reg ++ ldr r1, [r1] ++ ldr r1, [r1] ++ ++ /* Zero the number of banks field - bit 23*/ ++ mov r2, #1 ++ bic r1, r1, r2, lsl #23 ++ ++ /* Zero the size field - bits 17-20 inclusive */ ++ mov r2, #15 ++ bic r1, r1, r2, lsl #17 ++ ++ /* First probe location tells us the SDRAM size */ ++ adrl r3, probe_table ++ ldr r0, [r3] ++ ldr r0, [r0] ++ ++ /* Is size 64MB? */ ++ ldr r2, [r3, #28] /* Get probe value 4 */ ++ cmp r0, r2 ++ moveq r4, #6 ++ orreq r1, r1, r4, lsl #17 ++ beq pl2 ++ ++ /* Is 128M or 256M so set banks to 8 */ ++ mov r4, #1 ++ orr r1, r1, r4, lsl #23 ++ ++ /* Is size 128MB? */ ++ ldr r2, [r3, #20] /* Get probe value 3 */ ++ cmp r0, r2 ++// moveq r4, #7 ++ moveq r4, #8 /* DDR controller does not work at 128M, use 256M instead ++ orreq r1, r1, r4, lsl #17 ++ beq pl2 ++ ++ /* Must be 256MB, or something is very wrong */ ++ mov r4, #8 ++ orr r1, r1, r4, lsl #17 ++ ++pl2: ++ /* Write the revised contents to the DDR controller core's config register */ ++ adrl r2, ddr_config_reg ++ ldr r2, [r2] ++ str r1, [r2] ++#endif ++ ++ /* SDRAM setup complete */ ++ mov lr, r6 ++ mov pc, lr ++ ++/* ++ * delay() ++ * ++ * uses 1 + r0 * 5 cycles ++ */ ++delay: ++ nop ++ nop ++ nop ++ subs r0, r0, #1 ++ bne delay ++ mov pc, lr ++ ++_lowlevel_init: ++ .word lowlevel_init ++#endif ++ ++ ++init_table: ++#if (FPGA == 1) ++ /* Table of address, data for loading into the DRAM controller on FPGA */ ++ .word 0x45800000, 0x000d0000 // Enable the DDR in SDR mode and width 32 bits ++ .word 0x45800034, 0x04442032 // SDR mode timings - #0 ++ .word 0x45800038, 0x570A0907 // SDR mode timings - #1 ++ .word 0x4580003C, 0x00000002 // SDR mode timings - #2 ++ .word 0x45800004, 0x80000000 // Enable DDR core, but not clients yet ++ .word 0x45800014, 0x80000001 // Enable CK and set DLL mode to manual ++/* 200uS delay */ ++ .word 0x4580000c, 0x80200000 // Assert CKE for all further commands ++ .word 0x4580000c, 0x80280400 // Issue precharge to all banks ++ .word 0x4580000c, 0x80200000 // NOP, as only DDR has real command here ++ .word 0x4580000c, 0x80200022 // Set burst length 4, sequential CAS 2 ++/* 200uS delay */ ++ .word 0x4580000c, 0x80280400 // Issue precharge to all banks ++ .word 0x4580000c, 0x80240000 // Issue auto-refresh command, CKE not asserted ++/* 200uS delay */ ++ .word 0x4580000c, 0x80240000 // Issue auto-refresh command, CKE not asserted ++ .word 0x4580000c, 0x80200000 // Assert CKE for all further commands ++ .word 0x4580000c, 0x80200022 // Set burst length 4, sequential CAS 2 ++ .word 0x45800000, 0x000d0186 // SDR, size and width and refresh rate, assuming ++ // 25Mhz clk to SDR, divide down to get 15.625uS ++ // refresh rate ++ .word 0x45800024, 0x00000124 // Set I/O drive strengths ++ .word 0x45800028, 0x0000001f // Enable all arbiter features ++ .word 0x45800018, 0x00000000 // Disable all monitoring ++ .word 0x45800010, 0xFFFFFFFF // Disable all read buffering ++ .word 0x45800004, 0x800000ff // Enable all client interfaces ++#else // ASIC DDR-2 ++ // SECTION A - DDR controller core configuration ++ .word 0x45800000, 0x802d0591 // enable in ddr-2 mode 16 bit wide ++ .word 0x45800034, 0x04442032 // ddr-2 mode timings ++ .word 0x45800038, 0x870f0b25 // ddr-2 mode timings ++ .word 0x4580003c, 0x00000a23 // ddr-2 mode timings ++ .word 0x45800054, 0x00072000 // phy-3 settings ++ .word 0x45800050, 0x00022828 // phy-2 settings, start ++ .word 0x45800050, 0x00032828 // phy-2 settings, on ++ .word 0x45800028, 0x0000001f // Enable all arbiter features ++ .word 0x45800018, 0x00000000 // Disable all monitoring ++ .word 0x45800010, 0xffff0000 // Enable all read buffering ++ .word 0x4580002c, 0x00ff00fd // no burst accl, no hprot on arm data ++ .word 0x45800040, 0x00000000 // enable burst and read cache ++ .word 0x45800044, 0xffff0000 // enable write behind prot, disable timeout ++ .word 0x45800004, 0x8000ffff // Enable all client interfaces ++/* 200uS delay after configuring DDR controller core */ ++ ++ // SECTION B - Memory device configuration ++ .word 0x4580000c, 0x807c0000 // exit something or other ++ .word 0x4580000c, 0x803c0000 // nop - wake up ++ .word 0x4580000c, 0x80280400 // precharge all ++ .word 0x4580000c, 0x80220000 // emr2 ++ .word 0x4580000c, 0x80230000 // emr3 ++ ++#if (MEM_ODT == 150) ++ .word 0x4580000c, 0x80210042 // enable dll, odt to 150 ++#elif (MEM_ODT == 75) ++ .word 0x4580000c, 0x80210006 // enable dll, odt to 75 ++#elif (MEM_ODT == 50) ++ .word 0x4580000c, 0x80210046 // enable dll, odt to 50 ++#else ++#error Unsupported memory on-die termination, set MEM_ODT to 50, 75, or 150 ++#endif ++ ++ .word 0x4580000c, 0x80200733 // set WR CL BL and reset dll ++ .word 0x4580000c, 0x80280400 // precharge all ++ .word 0x4580000c, 0x80240000 // auto refresh ++ .word 0x4580000c, 0x80240000 // auto refresh ++ .word 0x4580000c, 0x80200733 // set WR CL BL and reset dll ++ ++#if (MEM_ODT == 150) ++ .word 0x4580000c, 0x802103c2 // enable OCD ++ .word 0x4580000c, 0x80210042 // disable OCD ++#elif (MEM_ODT == 75) ++ .word 0x4580000c, 0x80210386 // enable OCD ++ .word 0x4580000c, 0x80210006 // disable OCD ++#elif (MEM_ODT == 50) ++ .word 0x4580000c, 0x802103c6 // enable OCD ++ .word 0x4580000c, 0x80210046 // disable OCD ++#else ++#error Unsupported memory on-die termination, set MEM_ODT to 50, 75, or 150 ++#endif ++ ++ // SECTION C - Final memory size/bank configuration ++#if (PROBE_MEM_SIZE == 1) ++ .word 0x45800000, 0x80b10591 // 256M, 8 banks, 1425 clocks for 7.8us refresh. ++#elif (MEM_SIZE == 64) ++ .word 0x45800000, 0x802d0591 // 64M, 4 banks, 1425 clocks for 7.8us refresh. ++#elif (MEM_SIZE == 128) ++ .word 0x45800000, 0x80af0591 // 128M, 8 banks, 1425 clocks for 7.8us refresh. ++#elif (MEM_SIZE == 256) ++ .word 0x45800000, 0x80b10591 // 256M, 8 banks, 1425 clocks for 7.8us refresh. ++#else ++#error Unsupported memory size, set MEM_SIZE to 64, 128 or 256 ++#endif ++ ++#endif // FPGA or ASIC ++dllkey: ++ .word 0xbeadface ++ ++ddr_config_reg: ++ .word 0x45800000 ++ ++probe_table: ++ .word 0x48000000, 0x12345678 ++ .word 0x48000040, 0xdeadbeef ++ .word 0x50000000, 0xfafafafa ++ .word 0x50000040, 0xabcdef01 ++ ++.ltorg ++ +diff -Nurd u-boot-2009.03.orig/board/hipox/platform-820.S u-boot-2009.03/board/hipox/platform-820.S +--- u-boot-2009.03.orig/board/hipox/platform-820.S 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/platform-820.S 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,477 @@ ++/* ++ * Board specific setup info ++ * ++ * (C) Copyright 2008 ++ * Oxford Semiconductor Ltd ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <config.h> ++#include <version.h> ++ ++/* use estimate of processor speed to calculate number of cycles delay */ ++/* delay count is nominal (PLL200 frequency x delay time) / loop count ++ * expressing 200us as 200/1000000 and re-arranging gives the expression below ++ */ ++ ++#define DELAY_200US ((NOMINAL_ARMCLK / (5 * 1000000)) * 200) ++#define DELAY_300US ((NOMINAL_ARMCLK / (5 * 1000000)) * 300) ++/* this is 8 cycles of ? so choose 8 resulting in 40 cycles */ ++#define DELAY_1S ((DELAY_200US) * 5000) ++#define DELAY_8 8 ++#define DELAY_200 200 ++ ++ ++.globl platformsetup ++platformsetup: ++/* register allocations ++ * r0 - delay counter and scratch ++ * r1 - address register ++ * r2 - data register ++ * r3 - index to table pointer ++ * r4 - iteration counter. ++ * ++ * r5 - hold return address. ++ * lr - (R14) link register ++ * pc - (R15) program counter. ++ */ ++ ++#ifdef INITIALISE_SDRAM ++/* ++ * Check that not in SDRAM execution. Suicide if re-initialise DRAM. ++ * Controller function is linked to execute in SDRAM must be in ROM if not ++ * there. Check for wrong place. ++ */ ++ adrl r0, platformsetup /* Relative location of function start.*/ ++ ldr r1, _platformsetup ++ cmp r0, r1 ++ moveq pc, lr ++#else ++ mov pc, lr ++#endif ++ ++#if (FPGA == 1) ++ /* Establish a working setup for the SDRAM */ ++ mov r6, lr ++ ++ /* Assert reset to the DDR core */ ++ ldr r0, =SYS_CTRL_RSTEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Deassert reset to the DDR core */ ++ ldr r0, =SYS_CTRL_RSTEN_CLR_CTRL ++ str r1, [r0] ++ ++ /* Turn on the DDR core clock */ ++ ldr r0, =SYS_CTRL_CKEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_CKEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Start using the initialisation value list */ ++ adrl r3, init_table ++ ++ /* Copy first 6 entries */ ++ ldr r4, =6 ++loop0: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop0 ++ ++ /* Delay for 200uS while DRAM controller stabilises. */ ++ ldr r0, =DELAY_200US ++ bl delay ++ ++ /* Copy next 4 entries */ ++ ldr r4, =4 ++loop1: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop1 ++ ++ /* Wait at least 200 clock cycles. */ ++ ldr r0, =DELAY_200 ++ bl delay ++ ++ /* Copy next 2 entries */ ++ ldr r4, =2 ++loop2: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop2 ++ ++ /* Wait at least 8 clock cycles. */ ++ ldr r0, =DELAY_8 ++ bl delay ++ ++ /* Copy next 9 entries */ ++ ldr r4, =9 ++loop3: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop3 ++ ++ /* SDRAM initialised so now exit. */ ++ mov lr, r6 ++ mov pc, lr ++ ++/* ++ * delay() ++ * ++ * uses 1 + r0 * 5 cycles ++ */ ++delay: ++ nop ++ nop ++ nop ++ subs r0, r0, #1 ++ bne delay ++ mov pc, lr ++ ++_platformsetup: ++ .word platformsetup ++#else // ASIC, (DDR-2) ++/* ++ * Check that not in SDRAM execution. Suicide if re-initialise DRAM. ++ * Controller function is linked to execute in SDRAM must be in ROM if not ++ * there. Check for wrong place. ++ */ ++ /* Establish a working setup for the SDRAM */ ++ mov r6, lr ++ ++#ifdef OVERCLOCK ++ /* ++ change clock speed on chip ++ */ ++ ++ /* read SYS_CTRL_PLLSYS_CTRL into r3*/ ++ mov r5, #0x45000000 ++ ldr r3, [r5, #72] ++ ++ /* load the value at dllkey (0xbeadface) into r7 */ ++ adrl r7, dllkey ++ ldr r7, [r7] ++ ++ /* pll_sys |= 0x20000; */ ++ orr r3, r3, #131072 /* 0x20000 */ ++ ++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */ ++ str r7, [r5, #108] ++ ++ /* write pll_sys (bypass pll)*/ ++ str r3, [r5, #72] ++ ++ /* pll_sys &= 0xff000000; */ ++ mov r4, r3, lsr #16 ++ mov r4, r4, lsl #16 ++ ++ /* pll_sys |= 0x00F00061 */ ++ orr r4, r4, #15728640 /* 0xf00000 */ ++ orr r4, r4, #97 /* 0x61 */ ++#if 0 ++ orr r4, r4, #7864320 /* 0x780000 */ ++ orr r4, r4, #96 /* 0x60 */ ++#endif ++ ++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */ ++ str r7, [r5, #108] ++ ++ /* write pll_sys (with new pll speeds) */ ++ str r4, [r5, #72] ++ ++ /* delay 300us */ ++ ldr r0, =DELAY_300US ++ bl delay ++ ++ /* clear bypass pll bit */ ++ bic r4, r4, #131072 /* 0x20000 */ ++ ++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */ ++ str r7, [r5, #108] ++ ++ /* write pll_sys (with new pll speeds and pll un-bypassed) */ ++ str r4, [r5, #72] ++#endif /* OVERCLOCK */ ++ ++ /* Turn on the DDR core and phy clocks */ ++ ldr r0, =SYS_CTRL_CKEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_CKEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_CKEN_DDR_PHY_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Assert reset to the DDR core and phy */ ++ ldr r0, =SYS_CTRL_RSTEN_SET_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_PHY_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Deassert reset to the DDR core and phy*/ ++ ldr r0, =SYS_CTRL_RSTEN_CLR_CTRL ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_PHY_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ldr r1, =1 ++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT ++ mov r1, r1, LSL r2 ++ str r1, [r0] ++ ++ /* Start using the initialisation value list */ ++ adrl r3, init_table ++ ++ /* Copy first 14 entries of DDR core setup (section A)*/ ++ ldr r4, =14 ++loop0: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne loop0 ++ ++ /* Delay for 200uS while DDR controller stabilises. */ ++ ldr r0, =DELAY_200US ++ bl delay ++ ++ /* Copy next 13 entries of DDR device commands (section B)*/ ++ ldr r4, =13 ++loop1: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ ++ /* Wait at least 200 clock cycles between ram chip command writes */ ++ ldr r0, =DELAY_200 ++ bl delay ++ ++ subs r4, r4, #1 ++ bne loop1 ++ ++ /* Copy final DDR controller setup to set memory size/banks (section C)*/ ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ ++#if (PROBE_MEM_SIZE == 1) ++ /* Load the probe values into SDRAM */ ++ adrl r3, probe_table ++ mov r4, #4 ++.globl pl1 ++pl1: ++ ldmia r3!, {r1, r2} ++ str r2, [r1] ++ subs r4, r4, #1 ++ bne pl1 ++ ++ /* Get the current contents of the DDR controller core's config register */ ++ adrl r1, ddr_config_reg ++ ldr r1, [r1] ++ ldr r1, [r1] ++ ++ /* Zero the number of banks field - bit 23*/ ++ mov r2, #1 ++ bic r1, r1, r2, lsl #23 ++ ++ /* Zero the size field - bits 17-20 inclusive */ ++ mov r2, #15 ++ bic r1, r1, r2, lsl #17 ++ ++ /* First probe location tells us the SDRAM size */ ++ adrl r3, probe_table ++ ldr r0, [r3] ++ ldr r0, [r0] ++ ++ /* Is size 64MB? */ ++ ldr r2, [r3, #28] /* Get probe value 4 */ ++ cmp r0, r2 ++ moveq r4, #6 ++ orreq r1, r1, r4, lsl #17 ++ beq pl2 ++ ++ /* Is 128M or 256M so set banks to 8 */ ++ mov r4, #1 ++ orr r1, r1, r4, lsl #23 ++ ++ /* Is size 128MB? */ ++ ldr r2, [r3, #20] /* Get probe value 3 */ ++ cmp r0, r2 ++// moveq r4, #7 ++ moveq r4, #8 /* DDR controller does not work at 128M, use 256M instead ++ orreq r1, r1, r4, lsl #17 ++ beq pl2 ++ ++ /* Must be 256MB, or something is very wrong */ ++ mov r4, #8 ++ orr r1, r1, r4, lsl #17 ++ ++pl2: ++ /* Write the revised contents to the DDR controller core's config register */ ++ adrl r2, ddr_config_reg ++ ldr r2, [r2] ++ str r1, [r2] ++#endif ++ ++ /* SDRAM setup complete */ ++ mov lr, r6 ++ mov pc, lr ++ ++/* ++ * delay() ++ * ++ * uses 1 + r0 * 5 cycles ++ */ ++delay: ++ nop ++ nop ++ nop ++ subs r0, r0, #1 ++ bne delay ++ mov pc, lr ++ ++_platformsetup: ++ .word platformsetup ++#endif ++ ++ ++init_table: ++#if (FPGA == 1) ++ /* Table of address, data for loading into the DRAM controller on FPGA */ ++ .word 0x45800000, 0x000d0000 // Enable the DDR in SDR mode and width 32 bits ++ .word 0x45800034, 0x04442032 // SDR mode timings - #0 ++ .word 0x45800038, 0x570A0907 // SDR mode timings - #1 ++ .word 0x4580003C, 0x00000002 // SDR mode timings - #2 ++ .word 0x45800004, 0x80000000 // Enable DDR core, but not clients yet ++ .word 0x45800014, 0x80000001 // Enable CK and set DLL mode to manual ++/* 200uS delay */ ++ .word 0x4580000c, 0x80200000 // Assert CKE for all further commands ++ .word 0x4580000c, 0x80280400 // Issue precharge to all banks ++ .word 0x4580000c, 0x80200000 // NOP, as only DDR has real command here ++ .word 0x4580000c, 0x80200022 // Set burst length 4, sequential CAS 2 ++/* 200uS delay */ ++ .word 0x4580000c, 0x80280400 // Issue precharge to all banks ++ .word 0x4580000c, 0x80240000 // Issue auto-refresh command, CKE not asserted ++/* 200uS delay */ ++ .word 0x4580000c, 0x80240000 // Issue auto-refresh command, CKE not asserted ++ .word 0x4580000c, 0x80200000 // Assert CKE for all further commands ++ .word 0x4580000c, 0x80200022 // Set burst length 4, sequential CAS 2 ++ .word 0x45800000, 0x000d0186 // SDR, size and width and refresh rate, assuming ++ // 25Mhz clk to SDR, divide down to get 15.625uS ++ // refresh rate ++ .word 0x45800024, 0x00000124 // Set I/O drive strengths ++ .word 0x45800028, 0x0000001f // Enable all arbiter features ++ .word 0x45800018, 0x00000000 // Disable all monitoring ++ .word 0x45800010, 0xFFFFFFFF // Disable all read buffering ++ .word 0x45800004, 0x800000ff // Enable all client interfaces ++#else // ASIC DDR-2 ++ // SECTION A - DDR controller core configuration ++ .word 0x45800000, 0x802d0591 // enable in ddr-2 mode 16 bit wide ++ .word 0x45800034, 0x04442032 // ddr-2 mode timings ++ .word 0x45800038, 0x870f0b25 // ddr-2 mode timings ++ .word 0x4580003c, 0x00000a23 // ddr-2 mode timings ++ .word 0x45800054, 0x00072000 // phy-3 settings ++ .word 0x45800050, 0x00022828 // phy-2 settings, start ++ .word 0x45800050, 0x00032828 // phy-2 settings, on ++ .word 0x45800028, 0x0000001f // Enable all arbiter features ++ .word 0x45800018, 0x00000000 // Disable all monitoring ++ .word 0x45800010, 0xffff0000 // Enable all read buffering ++ .word 0x4580002c, 0x00ff00fd // no burst accl, no hprot on arm data ++ .word 0x45800040, 0x00000000 // enable burst and read cache ++ .word 0x45800044, 0xffff0000 // enable write behind prot, disable timeout ++ .word 0x45800004, 0x8000ffff // Enable all client interfaces ++/* 200uS delay after configuring DDR controller core */ ++ ++ // SECTION B - Memory device configuration ++ .word 0x4580000c, 0x807c0000 // exit something or other ++ .word 0x4580000c, 0x803c0000 // nop - wake up ++ .word 0x4580000c, 0x80280400 // precharge all ++ .word 0x4580000c, 0x80220000 // emr2 ++ .word 0x4580000c, 0x80230000 // emr3 ++ ++#if (MEM_ODT == 150) ++ .word 0x4580000c, 0x80210042 // enable dll, odt to 150 ++#elif (MEM_ODT == 75) ++ .word 0x4580000c, 0x80210006 // enable dll, odt to 75 ++#elif (MEM_ODT == 50) ++ .word 0x4580000c, 0x80210046 // enable dll, odt to 50 ++#else ++#error Unsupported memory on-die termination, set MEM_ODT to 50, 75, or 150 ++#endif ++ ++ .word 0x4580000c, 0x80200733 // set WR CL BL and reset dll ++ .word 0x4580000c, 0x80280400 // precharge all ++ .word 0x4580000c, 0x80240000 // auto refresh ++ .word 0x4580000c, 0x80240000 // auto refresh ++ .word 0x4580000c, 0x80200733 // set WR CL BL and reset dll ++ ++#if (MEM_ODT == 150) ++ .word 0x4580000c, 0x802103c2 // enable OCD ++ .word 0x4580000c, 0x80210042 // disable OCD ++#elif (MEM_ODT == 75) ++ .word 0x4580000c, 0x80210386 // enable OCD ++ .word 0x4580000c, 0x80210006 // disable OCD ++#elif (MEM_ODT == 50) ++ .word 0x4580000c, 0x802103c6 // enable OCD ++ .word 0x4580000c, 0x80210046 // disable OCD ++#else ++#error Unsupported memory on-die termination, set MEM_ODT to 50, 75, or 150 ++#endif ++ ++ // SECTION C - Final memory size/bank configuration ++#if (PROBE_MEM_SIZE == 1) ++ .word 0x45800000, 0x80b10591 // 256M, 8 banks, 1425 clocks for 7.8us refresh. ++#elif (MEM_SIZE == 64) ++ .word 0x45800000, 0x802d0591 // 64M, 4 banks, 1425 clocks for 7.8us refresh. ++#elif (MEM_SIZE == 128) ++ .word 0x45800000, 0x80af0591 // 128M, 8 banks, 1425 clocks for 7.8us refresh. ++#elif (MEM_SIZE == 256) ++ .word 0x45800000, 0x80b10591 // 256M, 8 banks, 1425 clocks for 7.8us refresh. ++#else ++#error Unsupported memory size, set MEM_SIZE to 64, 128 or 256 ++#endif ++ ++#endif // FPGA or ASIC ++dllkey: ++ .word 0xbeadface ++ ++ddr_config_reg: ++ .word 0x45800000 ++ ++probe_table: ++ .word 0x48000000, 0x12345678 ++ .word 0x48000040, 0xdeadbeef ++ .word 0x50000000, 0xfafafafa ++ .word 0x50000040, 0xabcdef01 ++ ++.ltorg ++ +diff -Nurd u-boot-2009.03.orig/board/hipox/u-boot-arm11.lds u-boot-2009.03/board/hipox/u-boot-arm11.lds +--- u-boot-2009.03.orig/board/hipox/u-boot-arm11.lds 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/u-boot-arm11.lds 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,50 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/arm11/start.o (.text) ++ *(.text) ++ } ++ .rodata : { *(.rodata) } ++ . = ALIGN(4); ++ .data : { *(.data) } ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +diff -Nurd u-boot-2009.03.orig/board/hipox/u-boot-arm926ejs.lds u-boot-2009.03/board/hipox/u-boot-arm926ejs.lds +--- u-boot-2009.03.orig/board/hipox/u-boot-arm926ejs.lds 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/board/hipox/u-boot-arm926ejs.lds 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,50 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/arm926ejs/start.o (.text) ++ *(.text) ++ } ++ .rodata : { *(.rodata) } ++ . = ALIGN(4); ++ .data : { *(.data) } ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +diff -Nurd u-boot-2009.03.orig/common/cmd_ide.c u-boot-2009.03/common/cmd_ide.c +--- u-boot-2009.03.orig/common/cmd_ide.c 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/common/cmd_ide.c 2009-04-15 11:08:18.000000000 +0200 +@@ -165,6 +165,13 @@ + + #define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */ + ++#ifdef CONFIG_HIPOX ++extern unsigned char ide_inb(int dev, int port); ++extern void ide_outb(int dev, int port, unsigned char val); ++extern void hipox_sata_output_data(int dev, ulong *sect_buf, int words); ++extern void hipox_sata_input_data(int dev, ulong *sect_buf, int words); ++#endif // CONFIG_HIPOX ++ + static void input_data(int dev, ulong *sect_buf, int words); + static void output_data(int dev, ulong *sect_buf, int words); + static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); +@@ -525,6 +532,7 @@ + + /* ------------------------------------------------------------------------- */ + ++#ifndef CONFIG_HIPOX + void inline + __ide_outb(int dev, int port, unsigned char val) + { +@@ -546,6 +554,7 @@ + } + unsigned char inline ide_inb(int dev, int port) + __attribute__((weak, alias("__ide_inb"))); ++#endif + + #ifdef CONFIG_TUNE_PIO + int inline +@@ -965,7 +974,11 @@ + static void + output_data(int dev, ulong *sect_buf, int words) + { ++#ifdef CONFIG_HIPOX ++ hipox_sata_output_data(dev, sect_buf, words); ++#else + outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words<<1); ++#endif + } + #endif /* __PPC__ */ + +@@ -1023,7 +1036,11 @@ + static void + input_data(int dev, ulong *sect_buf, int words) + { ++#ifdef CONFIG_HIPOX ++ hipox_sata_input_data(dev, sect_buf, words); ++#else + insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words << 1); ++#endif + } + + #endif /* __PPC__ */ +diff -Nurd u-boot-2009.03.orig/common/main.c u-boot-2009.03/common/main.c +--- u-boot-2009.03.orig/common/main.c 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/common/main.c 2009-04-15 11:08:18.000000000 +0200 +@@ -48,7 +48,7 @@ + * Board-specific Platform code can reimplement show_boot_progress () if needed + */ + void inline __show_boot_progress (int val) {} +-void inline show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress"))); ++void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress"))); + + #if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY) + extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* for do_reset() prototype */ +diff -Nurd u-boot-2009.03.orig/cpu/arm926ejs/interrupts.c u-boot-2009.03/cpu/arm926ejs/interrupts.c +--- u-boot-2009.03.orig/cpu/arm926ejs/interrupts.c 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/cpu/arm926ejs/interrupts.c 2009-04-15 11:08:18.000000000 +0200 +@@ -38,20 +38,312 @@ + #include <common.h> + #include <arm926ejs.h> + ++#include <asm/proc-armv/ptrace.h> ++ ++extern void reset_cpu(ulong addr); ++ ++#ifdef CONFIG_HIPOX ++#define TIMER_LOAD_VAL 0xffffUL ++#else // CONFIG_HIPOX ++#define TIMER_LOAD_VAL 0xffffffff ++#endif // CONFIG_HIPOX ++ ++/* macro to read the 32 bit timer */ ++#ifdef CONFIG_OMAP ++#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8)) ++#endif + #ifdef CONFIG_INTEGRATOR ++#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) ++#endif ++#ifdef CONFIG_VERSATILE ++#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) ++#endif ++#ifdef CONFIG_HIPOX ++#define READ_TIMER ((*(volatile ushort *)(CONFIG_SYS_TIMERBASE+4)) & 0xFFFFUL) /* RPS timer value register has only 16 defined bits */ ++#endif ++ ++#ifdef CONFIG_USE_IRQ ++/* enable IRQ interrupts */ ++void enable_interrupts (void) ++{ ++ unsigned long temp; ++ __asm__ __volatile__("mrs %0, cpsr\n" ++ "bic %0, %0, #0x80\n" ++ "msr cpsr_c, %0" ++ : "=r" (temp) ++ : ++ : "memory"); ++} + +- /* Timer functionality supplied by Integrator board (AP or CP) */ + ++/* ++ * disable IRQ/FIQ interrupts ++ * returns true if interrupts had been enabled before we disabled them ++ */ ++int disable_interrupts (void) ++{ ++ unsigned long old,temp; ++ __asm__ __volatile__("mrs %0, cpsr\n" ++ "orr %1, %0, #0xc0\n" ++ "msr cpsr_c, %1" ++ : "=r" (old), "=r" (temp) ++ : ++ : "memory"); ++ return (old & 0x80) == 0; ++} + #else ++void enable_interrupts (void) ++{ ++ return; ++} ++int disable_interrupts (void) ++{ ++ return 0; ++} ++#endif ++ ++ ++void bad_mode (void) ++{ ++ panic ("Resetting CPU ...\n"); ++ reset_cpu (0); ++} ++ ++void show_regs (struct pt_regs *regs) ++{ ++ unsigned long flags; ++ const char *processor_modes[] = { ++ "USER_26", "FIQ_26", "IRQ_26", "SVC_26", ++ "UK4_26", "UK5_26", "UK6_26", "UK7_26", ++ "UK8_26", "UK9_26", "UK10_26", "UK11_26", ++ "UK12_26", "UK13_26", "UK14_26", "UK15_26", ++ "USER_32", "FIQ_32", "IRQ_32", "SVC_32", ++ "UK4_32", "UK5_32", "UK6_32", "ABT_32", ++ "UK8_32", "UK9_32", "UK10_32", "UND_32", ++ "UK12_32", "UK13_32", "UK14_32", "SYS_32", ++ }; ++ ++ flags = condition_codes (regs); ++ ++ printf ("pc : [<%08lx>] lr : [<%08lx>]\n" ++ "sp : %08lx ip : %08lx fp : %08lx\n", ++ instruction_pointer (regs), ++ regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); ++ printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", ++ regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); ++ printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", ++ regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); ++ printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", ++ regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); ++ printf ("Flags: %c%c%c%c", ++ flags & CC_N_BIT ? 'N' : 'n', ++ flags & CC_Z_BIT ? 'Z' : 'z', ++ flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); ++ printf (" IRQs %s FIQs %s Mode %s%s\n", ++ interrupts_enabled (regs) ? "on" : "off", ++ fast_interrupts_enabled (regs) ? "on" : "off", ++ processor_modes[processor_mode (regs)], ++ thumb_mode (regs) ? " (T)" : ""); ++} ++ ++void do_undefined_instruction (struct pt_regs *pt_regs) ++{ ++ printf ("undefined instruction\n"); ++ show_regs (pt_regs); ++ bad_mode (); ++} ++ ++void do_software_interrupt (struct pt_regs *pt_regs) ++{ ++ printf ("software interrupt\n"); ++ show_regs (pt_regs); ++ bad_mode (); ++} ++ ++void do_prefetch_abort (struct pt_regs *pt_regs) ++{ ++ printf ("prefetch abort\n"); ++ show_regs (pt_regs); ++ bad_mode (); ++} ++ ++void do_data_abort (struct pt_regs *pt_regs) ++{ ++ printf ("data abort\n"); ++ show_regs (pt_regs); ++ bad_mode (); ++} ++ ++void do_not_used (struct pt_regs *pt_regs) ++{ ++ printf ("not used\n"); ++ show_regs (pt_regs); ++ bad_mode (); ++} ++ ++void do_fiq (struct pt_regs *pt_regs) ++{ ++ printf ("fast interrupt request\n"); ++ show_regs (pt_regs); ++ bad_mode (); ++} ++ ++void do_irq (struct pt_regs *pt_regs) ++{ ++ printf ("interrupt request\n"); ++ show_regs (pt_regs); ++ bad_mode (); ++} ++ ++static ulong timestamp; ++static ulong lastdec; + + /* nothing really to do with interrupts, just starts up a counter. */ + int interrupt_init (void) + { +- extern void timer_init(void); ++#ifdef CONFIG_OMAP ++ int32_t val; + +- timer_init(); ++ /* Start the decrementer ticking down from 0xffffffff */ ++ *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; ++ val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT); ++ *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val; ++#endif /* CONFIG_OMAP */ ++#ifdef CONFIG_INTEGRATOR ++ /* Load timer with initial value */ ++ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; ++ /* Set timer to be enabled, free-running, no interrupts, 256 divider */ ++ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x8C; ++#endif /* CONFIG_INTEGRATOR */ ++#ifdef CONFIG_VERSATILE ++ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = CONFIG_SYS_TIMER_RELOAD; /* TimerLoad */ ++ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 4) = CONFIG_SYS_TIMER_RELOAD; /* TimerValue */ ++ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x8C; ++#endif /* CONFIG_VERSATILE */ ++#ifdef CONFIG_HIPOX ++ // Setup timer 1 load value ++ *(volatile ulong*)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; + +- return 0; ++ // Setup timer 1 prescaler, periodic operation and start it ++ *(volatile ulong*)(CONFIG_SYS_TIMERBASE + 8) = ++ (TIMER_PRESCALE_ENUM << TIMER_PRESCALE_BIT) | ++ (TIMER_MODE_PERIODIC << TIMER_MODE_BIT) | ++ (TIMER_ENABLE_ENABLE << TIMER_ENABLE_BIT); ++#endif /* CONFIG_HIPOX */ ++ ++ /* init the timestamp and lastdec value */ ++ reset_timer_masked(); ++ ++ return (0); + } + +-#endif /* CONFIG_INTEGRATOR */ ++/* ++ * timer without interrupts ++ */ ++ ++void reset_timer (void) ++{ ++ reset_timer_masked (); ++} ++ ++ulong get_timer (ulong base) ++{ ++ return get_timer_masked () - base; ++} ++ ++void set_timer (ulong t) ++{ ++ timestamp = t; ++} ++ ++/* delay x useconds AND perserve advance timstamp value */ ++void udelay (unsigned long usec) ++{ ++ ulong tmo, tmp; ++ ++ if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ ++ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ ++ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ ++ tmo /= 1000; /* finish normalize. */ ++ }else{ /* else small number, don't kill it prior to HZ multiply */ ++ tmo = usec * CONFIG_SYS_HZ; ++ tmo /= (1000*1000); ++ } ++ ++ tmp = get_timer (0); /* get current timestamp */ ++ if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ ++ reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ ++ else ++ tmo += tmp; /* else, set advancing stamp wake up time */ ++ ++ while (get_timer_masked () < tmo)/* loop till event */ ++ /*NOP*/; ++} ++ ++void reset_timer_masked (void) ++{ ++ /* reset time */ ++ lastdec = READ_TIMER; /* capure current decrementer value time */ ++ timestamp = 0; /* start "advancing" time stamp from 0 */ ++} ++ ++ulong get_timer_masked (void) ++{ ++ ulong now = READ_TIMER; /* current tick value */ ++ ++ if (lastdec >= now) { /* normal mode (non roll) */ ++ /* normal mode */ ++ timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ ++ } else { /* we have overflow of the count down timer */ ++ /* nts = ts + ld + (TLV - now) ++ * ts=old stamp, ld=time that passed before passing through -1 ++ * (TLV-now) amount of time after passing though -1 ++ * nts = new "advancing time stamp"...it could also roll and cause problems. ++ */ ++ timestamp += lastdec + TIMER_LOAD_VAL - now; ++ } ++ lastdec = now; ++ ++ return timestamp; ++} ++ ++/* waits specified delay value and resets timestamp */ ++void udelay_masked (unsigned long usec) ++{ ++ ulong tmo; ++ ++ if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ ++ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ ++ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ ++ tmo /= 1000; /* finish normalize. */ ++ }else{ /* else small number, don't kill it prior to HZ multiply */ ++ tmo = usec * CONFIG_SYS_HZ; ++ tmo /= (1000*1000); ++ } ++ ++ reset_timer_masked (); /* set "advancing" timestamp to 0, set lastdec vaule */ ++ ++ while (get_timer_masked () < tmo) /* wait for time stamp to overtake tick number.*/ ++ /*NOP*/; ++} ++ ++/* ++ * This function is derived from PowerPC code (read timebase as long long). ++ * On ARM it just returns the timer value. ++ */ ++unsigned long long get_ticks(void) ++{ ++ return get_timer(0); ++} ++ ++/* ++ * This function is derived from PowerPC code (timebase clock frequency). ++ * On ARM it returns the number of timer ticks per second. ++ */ ++ulong get_tbclk (void) ++{ ++ ulong tbclk; ++ ++ tbclk = CONFIG_SYS_HZ; ++ return tbclk; ++} +diff -Nurd u-boot-2009.03.orig/cpu/arm926ejs/start.S u-boot-2009.03/cpu/arm926ejs/start.S +--- u-boot-2009.03.orig/cpu/arm926ejs/start.S 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/cpu/arm926ejs/start.S 2009-04-15 11:08:18.000000000 +0200 +@@ -94,6 +94,11 @@ + _TEXT_BASE: + .word TEXT_BASE + ++#ifdef CONFIG_HIPOX ++_EXCEPTION_BASE: ++ .word EXCEPTION_BASE ++#endif ++ + .globl _armboot_start + _armboot_start: + .word _start +@@ -135,6 +140,18 @@ + orr r0,r0,#0xd3 + msr cpsr,r0 + ++#ifdef CONFIG_HIPOX ++ /* ++ * Copy exception table to relocated address in internal SRAM ++ */ ++ adr r0, _start /* Address of exception table in flash */ ++ ldr r1, _EXCEPTION_BASE /* Relocated address of exception table */ ++ ldmia r0!, {r3-r10} /* Copy exception table and jump values from */ ++ stmia r1!, {r3-r10} /* FLASH to relocated address */ ++ ldmia r0!, {r3-r10} ++ stmia r1!, {r3-r10} ++#endif ++ + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! +diff -Nurd u-boot-2009.03.orig/drivers/mtd/cfi_flash.c u-boot-2009.03/drivers/mtd/cfi_flash.c +--- u-boot-2009.03.orig/drivers/mtd/cfi_flash.c 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/drivers/mtd/cfi_flash.c 2009-04-15 11:08:18.000000000 +0200 +@@ -1883,6 +1883,7 @@ + /* Do manufacturer-specific fixups */ + switch (info->manufacturer_id) { + case 0x0001: ++ case 0x00da: // Winbond + flash_fixup_amd(info, &qry); + break; + case 0x001f: +diff -Nurd u-boot-2009.03.orig/drivers/mtd/cfi_mtd.c u-boot-2009.03/drivers/mtd/cfi_mtd.c +--- u-boot-2009.03.orig/drivers/mtd/cfi_mtd.c 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/drivers/mtd/cfi_mtd.c 2009-04-15 11:08:18.000000000 +0200 +@@ -141,22 +141,12 @@ + int sect_size = 0; + int sect; + ++ /* ++ * Select the largest sector size as erasesize (e.g. for UBI) ++ */ + for (sect = 0; sect < fi->sector_count; sect++) { +- if (!sect_size) { ++ if (flash_sector_size(fi, sect) > sect_size) + sect_size = flash_sector_size(fi, sect); +- continue; +- } +- +- if (sect_size != flash_sector_size(fi, sect)) { +- sect_size = 0; +- break; +- } +- } +- +- if (!sect_size) { +- puts("cfi-mtd: devices with multiple sector sizes are" +- "not supported\n"); +- return -EINVAL; + } + + mtd->erasesize = sect_size; +diff -Nurd u-boot-2009.03.orig/drivers/mtd/nand/nand_base.c u-boot-2009.03/drivers/mtd/nand/nand_base.c +--- u-boot-2009.03.orig/drivers/mtd/nand/nand_base.c 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/drivers/mtd/nand/nand_base.c 2009-04-15 11:08:18.000000000 +0200 +@@ -50,14 +50,14 @@ + #include <linux/leds.h> + #include <asm/io.h> + +-#ifdef CONFIG_MTD_PARTITIONS +-#include <linux/mtd/partitions.h> +-#endif +- + #endif + + #include <common.h> + ++#ifdef CONFIG_MTD_PARTITIONS ++#include <linux/mtd/partitions.h> ++#endif ++ + #define ENOTSUPP 524 /* Operation is not supported */ + + #include <malloc.h> +diff -Nurd u-boot-2009.03.orig/include/asm-arm/mach-types.h u-boot-2009.03/include/asm-arm/mach-types.h +--- u-boot-2009.03.orig/include/asm-arm/mach-types.h 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/include/asm-arm/mach-types.h 2009-04-15 11:08:18.000000000 +0200 +@@ -1990,6 +1990,7 @@ + #define MACH_TYPE_BLAZE 2004 + #define MACH_TYPE_LINKSTATION_LS_HGL 2005 + #define MACH_TYPE_HTCVENUS 2006 ++#define MACH_TYPE_HIPOX 2151 + + #ifdef CONFIG_ARCH_EBSA110 + # ifdef machine_arch_type +@@ -25727,6 +25728,19 @@ + # define machine_is_htcvenus() (0) + #endif + ++#ifdef CONFIG_MACH_HIPOX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HIPOX ++# endif ++# define machine_is_hipox() (machine_arch_type == MACH_TYPE_HIPOX) ++#else ++# define machine_is_hipox() (0) ++#endif ++ ++ + /* + * These have not yet been registered + */ +diff -Nurd u-boot-2009.03.orig/include/asm-arm/u-boot.h u-boot-2009.03/include/asm-arm/u-boot.h +--- u-boot-2009.03.orig/include/asm-arm/u-boot.h 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/include/asm-arm/u-boot.h 2009-04-15 11:08:18.000000000 +0200 +@@ -48,6 +48,9 @@ + ulong start; + ulong size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; ++ unsigned long bi_sramstart; /* start of SRAM memory */ ++ unsigned long bi_sramsize; /* size of SRAM memory */ ++ + #ifdef CONFIG_HAS_ETH1 + /* second onboard ethernet port */ + unsigned char bi_enet1addr[6]; +diff -Nurd u-boot-2009.03.orig/include/ata.h u-boot-2009.03/include/ata.h +--- u-boot-2009.03.orig/include/ata.h 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/include/ata.h 2009-04-15 11:08:18.000000000 +0200 +@@ -82,7 +82,11 @@ + /* + * Device / Head Register Bits + */ ++#ifdef CONFIG_HIPOX ++#define ATA_DEVICE(x) (0) ++#else + #define ATA_DEVICE(x) ((x & 1)<<4) ++#endif + #define ATA_LBA 0xE0 + + /* +diff -Nurd u-boot-2009.03.orig/include/configs/hipox.h u-boot-2009.03/include/configs/hipox.h +--- u-boot-2009.03.orig/include/configs/hipox.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-2009.03/include/configs/hipox.h 2009-04-15 11:08:18.000000000 +0200 +@@ -0,0 +1,705 @@ ++/* ++ * (C) Copyright 2005 ++ * Oxford Semiconductor Ltd ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++//#define readb(p) (*(volatile u8 *)(p)) ++//#define readl(p) (*(volatile u32 *)(p)) ++//#define writeb(v, p) (*(volatile u8 *)(p)= (v)) ++//#define writel(v, p) (*(volatile u32*)(p)=(v)) ++ ++#include <config_cmd_default.h> ++ ++#define CONFIG_CMD_DHCP ++#define CONFIG_CMD_DIAG ++#define CONFIG_CMD_PING ++ ++/** ++ * Architecture ++ */ ++#if (NAS_VERSION == 820) ++ #define CONFIG_ARM11 1 ++#else ++ #define CONFIG_ARM926EJS 1 ++#endif ++#define CONFIG_HIPOX 1 ++#define CONFIG_HIPOX_ENABLE_PCI /* Enables PCI clock and takes out of reset - needed if require access to static bus */ ++#define CONFIG_HIPOX_FEEDBACK_PCI_CLKS /* Feedback PCI clock out 3 to drive PCI core clock - needed if require access to static bus */ ++#define CONFIG_HIPOX_MANUAL_STATIC_ARBITRATION ++#if (USE_SATA == 1) ++#define CONFIG_HIPOX_USE_SATA /* Define to include support for SATA disks */ ++#if (USE_SATA_ENV == 1) ++#define ENV_ON_SATA /* Define to have the U-Boot env. stored on SATA disk */ ++#endif // USE_SATA_ENV ++#endif // USE_SATA ++#if (USE_FLASH == 0) ++#define CONFIG_SYS_NO_FLASH /* Define to NOT include flash support on static bus*/ ++#endif //USE_FLASH ++ ++/* Won't be using any interrupts */ ++#undef CONFIG_USE_IRQ ++ ++/* Everything, incl board info, in Hz */ ++#undef CONFIG_SYS_CLKS_IN_HZ ++ ++#define CONFIG_SYS_HUSH_PARSER 1 ++#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " ++ ++/* Miscellaneous configurable options */ ++#define CONFIG_SYS_LONGHELP /* undef to save memory */ ++#ifdef CONFIG_SYS_HUSH_PARSER ++#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ ++#else ++#define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */ ++#endif ++#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ ++ ++/* Print Buffer Size */ ++#define CONFIG_SYS_PBSIZE ((CONFIG_SYS_CBSIZE)+sizeof(CONFIG_SYS_PROMPT)+16) ++#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ ++#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) /* Boot Argument Buffer Size */ ++ ++#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ ++#define CONFIG_INITRD_TAG 1 /* allow initrd tag to be generated */ ++ ++/* May want to do some setup prior to relocation */ ++//#define CONFIG_INIT_CRITICAL ++ ++/* ARM specific late initialisation */ ++#define BOARD_LATE_INIT ++ ++/** ++ * Stack sizes ++ * ++ * The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (128*1024) /* regular stack */ ++#ifdef CONFIG_USE_IRQ ++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++#endif ++ ++/** ++ * RAM ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of SDRAM */ ++#define PHYS_SDRAM_1_PA 0x48000000 /* SDRAM Bank #1 */ ++#if (NAS_VERSION == 810) ++#define PHYS_SDRAM_1_MAX_SIZE (256 * 1024 * 1024) ++#endif // NAS_VERSION ++ ++#if (NAS_VERSION == 820) ++#define PHYS_SDRAM_1_MAX_SIZE (256 * 1024 * 1024) ++#endif // NAS_VERSION ++#define CONFIG_SYS_SRAM_BASE ((PHYS_SDRAM_1_PA) + (PHYS_SDRAM_1_MAX_SIZE)) ++ ++#if (NAS_VERSION == 810) ++#define CONFIG_SYS_SRAM_SIZE (128 * 1024) ++#endif // NAS_VERSION ++ ++#if (NAS_VERSION == 820) ++#define CONFIG_SYS_SRAM_SIZE (128 * 1024) ++#endif // NAS_VERSION ++ ++#define INITIALISE_SDRAM ++ ++#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1_PA ++#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_1_MAX_SIZE) ++ ++/* ++ * PLLSYS = ((PLLSYS_S << 0) | (PLLSYS_P << 4) | (PLLSYS_M << 16)) ++ * ++ * Default S = 0 ++ * P = 6 ++ * M = 176 -> 733.33 MHz ++ */ ++//#define OVERCLOCK 12583008 /* S=0, P=6, M=192 -> 800MHz */ ++//#define OVERCLOCK 12845152 /* S=0, P=6, M=196 -> 816.66MHz */ ++//#define OVERCLOCK 13107296 /* S=0, P=6, M=200 -> 833.33MHz */ ++//#define OVERCLOCK 13631584 /* S=0, P=6, M=208 -> 866.66MHz */ ++//#define OVERCLOCK 14155872 /* S=0, P=6, M=216 -> 900MHz */ ++//#define OVERCLOCK 14680160 /* S=0, P=6, M=224 -> 933.33MHz */ ++//#define OVERCLOCK 18350176 /* S=0, P=6, M=280 -> 1000MHz */ ++ ++/* Default location from which bootm etc will load */ ++#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_PA) ++ ++/** ++ * Core addresses ++ */ ++#define MAC_BASE_PA 0x40400000 ++#define STATIC_CS0_BASE_PA 0x41000000 ++#define STATIC_CS1_BASE_PA 0x41400000 ++#define STATIC_CS2_BASE_PA 0x41800000 ++#define STATIC_CONTROL_BASE_PA 0x41C00000 ++#define SATA_DATA_BASE_PA 0x42000000 ++ ++#define APB_BRIDGE_A_BASE_PA 0x44000000 ++#define APB_BRIDGE_B_BASE_PA 0x45000000 ++ ++#define GPIO_1_PA ((APB_BRIDGE_A_BASE_PA) + 0x0) ++#define GPIO_2_PA ((APB_BRIDGE_A_BASE_PA) + 0x100000) ++ ++#define SYS_CONTROL_BASE_PA ((APB_BRIDGE_B_BASE_PA) + 0x0) ++#define DMA_BASE_PA ((APB_BRIDGE_B_BASE_PA) + 0x600000) ++#define RPS_BASE ((APB_BRIDGE_B_BASE_PA) + 0x300000) ++ ++/* Static bus registers */ ++#define STATIC_CONTROL_VERSION ((STATIC_CONTROL_BASE_PA) + 0x0) ++#define STATIC_CONTROL_BANK0 ((STATIC_CONTROL_BASE_PA) + 0x4) ++#define STATIC_CONTROL_BANK1 ((STATIC_CONTROL_BASE_PA) + 0x8) ++#define STATIC_CONTROL_BANK2 ((STATIC_CONTROL_BASE_PA) + 0xC) ++ ++/* Clock to the ARM/DDR */ ++#if (FPGA == 0) ++#define NOMINAL_ARMCLK ((PLL400) / 2) ++#define NOMINAL_SYSCLK ((PLL400) / 4) ++#else // !FPGA ++#define NOMINAL_ARMCLK (FPGA_ARM_CLK) ++#define NOMINAL_SYSCLK ((PLL400) / 4) ++#endif // !FPGA ++ ++/** ++ * Timer ++ */ ++#define CONFIG_SYS_TIMERBASE ((RPS_BASE) + 0x200) ++#define TIMER_PRESCALE_BIT 2 ++#define TIMER_PRESCALE_1_ENUM 0 ++#define TIMER_PRESCALE_16_ENUM 1 ++#define TIMER_PRESCALE_256_ENUM 2 ++#define TIMER_MODE_BIT 6 ++#define TIMER_MODE_FREE_RUNNING 0 ++#define TIMER_MODE_PERIODIC 1 ++#define TIMER_ENABLE_BIT 7 ++#define TIMER_ENABLE_DISABLE 0 ++#define TIMER_ENABLE_ENABLE 1 ++ ++#define TIMER_PRESCALE_ENUM (TIMER_PRESCALE_256_ENUM) ++#define CONFIG_SYS_HZ ((RPSCLK) / 256) ++ ++/** ++ * GPIO ++ */ ++#define GPIO_1_OE ((GPIO_1_PA) + 0x4) ++#define GPIO_1_SET_OE ((GPIO_1_PA) + 0x1C) ++#define GPIO_1_CLR_OE ((GPIO_1_PA) + 0x20) ++ ++#define GPIO_1_SET ((GPIO_1_PA) + 0x14) ++#define GPIO_1_CLR ((GPIO_1_PA) + 0x18) ++ ++#define GPIO_2_OE ((GPIO_2_PA) + 0x4) ++#define GPIO_2_SET_OE ((GPIO_2_PA) + 0x1C) ++#define GPIO_2_CLR_OE ((GPIO_2_PA) + 0x20) ++ ++#define GPIO_2_SET ((GPIO_2_PA) + 0x14) ++#define GPIO_2_CLR ((GPIO_2_PA) + 0x18) ++ ++/** ++ * Serial Configuration ++ */ ++#define EXT_UART_BASE 0x28000000 ++ ++#define UART_1_BASE (APB_BRIDGE_A_BASE_PA + 0x200000) ++#define UART_2_BASE (APB_BRIDGE_A_BASE_PA + 0x300000) ++#define UART_3_BASE (APB_BRIDGE_A_BASE_PA + 0x900000) ++#define UART_4_BASE (APB_BRIDGE_A_BASE_PA + 0xA00000) ++ ++#define CONFIG_SYS_NS16550 1 ++#define CONFIG_SYS_NS16550_SERIAL 1 ++#define CONFIG_SYS_NS16550_REG_SIZE 1 ++ ++#if (USE_EXTERNAL_UART != 0) ++#define CONFIG_SYS_NS16550_CLK 16000000 ++#define CONFIG_SYS_NS16550_COM1 (EXT_UART_BASE) ++#else // USE_EXTERNAL_UART ++#define CONFIG_SYS_NS16550_CLK (NOMINAL_SYSCLK) ++#define USE_UART_FRACTIONAL_DIVIDER ++#if (INTERNAL_UART == 1) ++#define CONFIG_HIPOX_UART1 ++#define CONFIG_SYS_NS16550_COM1 (UART_1_BASE) ++#elif (INTERNAL_UART == 2) ++#define CONFIG_HIPOX_UART2 ++#define CONFIG_SYS_NS16550_COM1 (UART_2_BASE) ++#elif (INTERNAL_UART == 3) ++#define CONFIG_HIPOX_UART3 ++#define CONFIG_SYS_NS16550_COM1 (UART_3_BASE) ++#else ++#define CONFIG_HIPOX_UART4 ++#define CONFIG_SYS_NS16550_COM1 (UART_4_BASE) ++#endif // CONFIG_HIPOX_UART ++#endif // USE_EXTERNAL_UART ++ ++#define CONFIG_CONS_INDEX 1 ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++#ifdef CONFIG_HIPOX_USE_SATA ++ ++#define CONFIG_CMD_FAT ++#define CONFIG_CMD_IDE ++#define CONFIG_CMD_EXT2 ++ ++// extern void hipox_sata_output_data(int dev, unsigned long *sect_buf, int words); ++// extern void hipox_sata_input_data(int dev, unsigned long *sect_buf, int words); ++ ++#define outsw(p,d,l) hipox_sata_output_data(p,d,l) ++#define insw(p,d,l) hipox_sata_input_data(p,d,l) ++ ++#endif ++ ++#ifndef CONFIG_SYS_NO_FLASH ++ ++// configure this for HIPOX with NAND-CS on GPIO33 ++#undef CONFIG_HIPOX_NAND_GPIO33 ++ ++#define CONFIG_CMD_NAND ++#define CONFIG_CMD_JFFS2 ++#define CONFIG_JFFS2_CMDLINE ++ ++#define CONFIG_JFFS2_NAND 1 ++#define CONFIG_JFFS2_NAND_OFF 0x800000 ++#define CONFIG_JFFS2_NAND_SIZE 0x3800000 ++#define CONFIG_JFFS2_NAND_DEV 0 ++ ++#endif ++ ++// number of pages to duplicate to allow for erorros in NAND flash, 2 for SLC more for MLC ++#define CONFIG_PAGE_REPLICATION 2 ++// number of blocks to duplicate to allow for errors in NAND flash, 2 for SLC more for MLC ++#define CONFIG_BLOCK_REPLICATION 2 ++ ++// space to allocate for kernel image, i.e. maximum kernel size ++#define CONFIG_FLASH_KERNEL_SPACE 3 * 1024 * 1024 // 3MB ++ ++ ++/* This must be included AFTER the definition of CONFIG_COMMANDS */ ++// #include <cmd_confdefs.h> ++ ++/** ++ * Booting ++ */ ++#if (LINUX_ROOT_RAIDED == 1) ++#define LINUX_ROOT_DEVICE "root=/dev/md1" ++#else ++#define LINUX_ROOT_DEVICE "root=/dev/sda1" ++#endif ++ ++#if 0 ++#define CONFIG_BOOTARGS LINUX_ROOT_DEVICE " console=ttyS0,115200 elevator=cfq mac_adr=0x00,0x30,0xe0,0x00,0x00,0x01" ++#define CONFIG_BOOTDELAY 2 ++#define CONFIG_BOOTCOMMAND "run select0 load boot || run select0 load2 boot || run lightled select1 load extinguishled boot || run lightled select1 load2 extinguishled boot || lightled" ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "select0=ide dev 0\0" \ ++ "select1=ide dev 1\0" \ ++ "load=ide read 0x48500000 122 1644\0" \ ++ "load2=ide read 0x48500000 e000 1644\0" \ ++ "lightled=ledfail 1\0" \ ++ "extinguishled=ledfail 0\0" \ ++ "boot=bootm 48500000\0" ++#elif 0 ++#define CONFIG_BOOTDELAY 2 ++#define CONFIG_BOOTARGS "console=ttyS0,115200 elevator=cfq mac_adr=0x00,0x30,0xe0,0x00,0x00,0x01 root=ubi0:rootfs ubi.mtd=2,2048 rootfstype=ubifs" ++#define CONFIG_BOOTCOMMAND "run boot" ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "boot=nboot 48500000 0 0 && bootm 48500000\0" ++#else ++#define CONFIG_BOOTDELAY 2 ++#define CONFIG_BOOTCOMMAND "bootm 0x41040000" ++#endif // CONFIG_HIPOX_USE_SATA ++ ++//#define CONFIG_SHOW_BOOT_PROGRESS 1 ++ ++/** ++ * Networking ++ */ ++#define CONFIG_ETHADDR 00:30:e0:00:00:01 ++#define CONFIG_NETMASK 255.255.0.0 ++#define CONFIG_IPADDR 172.31.0.128 ++#define CONFIG_SERVERIP 172.31.0.100 ++#define CONFIG_BOOTFILE "uImage" ++#define CONFIG_SYS_AUTOLOAD "n" ++#define CONFIG_NET_RETRY_COUNT 30 ++ ++/** ++ * Flash support ++ */ ++#ifndef CONFIG_SYS_NO_FLASH ++ ++#define CONFIG_SYS_FLASH_EMPTY_INFO ++ ++#define CONFIG_SYS_FLASH_CFI ++#define CONFIG_FLASH_CFI_DRIVER ++#define CONFIG_FLASH_CFI_MTD ++#define CONFIG_MTD_PARTITIONS ++#define CONFIG_CMD_UBI ++#define CONFIG_RBTREE ++ ++#define MTDIDS_DEFAULT "nand0=MT29FXX" ++#define MTDPARTS_DEFAULT "mtdparts=MT29FXX:" \ ++ "32m(boot)," \ ++ "224m(system)" ++ ++#define NUM_FLASH_MAIN_BLOCKS 63 /* For Intel 28F320B3T */ ++#define NUM_FLASH_PARAM_BLOCKS 8 /* For Intel 28F320B3T */ ++#define FLASH_MAIN_BLOCK_SIZE (64*1024) /* For Intel 28F320B3T family */ ++#define FLASH_PARAM_BLOCK_SIZE (8*1024) /* For Intel 28F320B3T family */ ++ ++/* Assuming counts main blocks and parameter blocks, as the Intel/AMD detection */ ++/* I'm intending to copy would seem to indicate */ ++#define CONFIG_SYS_MAX_FLASH_SECT (NUM_FLASH_MAIN_BLOCKS + NUM_FLASH_PARAM_BLOCKS) ++ ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Assume counts flash devices */ ++#define FLASH_BASE_OFF 0 ++#define CONFIG_SYS_FLASH_BASE ((STATIC_CS0_BASE_PA) + (FLASH_BASE_OFF)) ++#define PHYS_FLASH_1 (CONFIG_SYS_FLASH_BASE) ++ ++#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ ++#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ ++#define CONFIG_SYS_FLASH_WRITE_ATTEMPTS 5 ++ ++#define STATIC_BUS_FLASH_CONFIG 0x4f1f3f0d /* fast ASIC settings, 70ns */ ++ ++#endif // !CONFIG_SYS_NO_FLASH ++ ++/** ++ * Environment organization ++ */ ++#ifdef ENV_ON_SATA ++ ++/* Environment on SATA disk */ ++#define SIZE_TO_SECTORS(x) ((x) / 512) ++#define CONFIG_ENV_IS_IN_DISK ++#define CONFIG_ENV_SIZE (8*1024) ++#define ENVIRONMENT_OFFSET ((CONFIG_SYS_SRAM_SIZE) - (CONFIG_ENV_SIZE) - 1024) ++#define CONFIG_ENV_ADDR ((CONFIG_SYS_SRAM_BASE) + (ENVIRONMENT_OFFSET)) ++#define ROM_LOADER_LOAD_START_SECTOR 1 ++#define CONFIG_ENV_DISK_SECTOR ((ROM_LOADER_LOAD_START_SECTOR) + SIZE_TO_SECTORS(ENVIRONMENT_OFFSET)) ++#define ROM_LOADER_LOAD_REDUNDANT_START_SECTOR 10608 ++#define CONFIG_ENV_DISK_REDUNDANT_SECTOR ((ROM_LOADER_LOAD_REDUNDANT_START_SECTOR) + SIZE_TO_SECTORS(ENVIRONMENT_OFFSET)) ++ ++#else // ENV_ON_SATA ++ ++#if (USE_FLASH == 1) ++/** Flash based environment ++ * ++ * It appears that all flash env start/size info. has to be pre-defined. How ++ * this is supposed to work when the flash detection code could cope with all ++ * sorts of different flash is hard to see. ++ * It appears from the README that with bottom/top boot flashes with smaller ++ * parameter blocks available, the environment code will only use a single ++ * one of these smaller sectors for the environment, i.e. CONFIG__ENV_SECT_SIZE ++ * is the size of the environment. I hope this isn't really true. The defines ++ * below may well not work if this is the truth ++ */ ++#define CONFIG_ENV_IS_IN_FLASH ++#endif // (USE_FLASH == 1) ++ ++/* Environment in flash device parameter blocks */ ++#define CONFIG_ENV_SECT_SIZE (8*1024) ++/* First parameter block for environment */ ++#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE ++/* Second parameter block for backup environment */ ++#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) ++/* Main environment occupies first parameter block */ ++#define CONFIG_ENV_ADDR ((CONFIG_SYS_FLASH_BASE)+(NUM_FLASH_MAIN_BLOCKS)*(FLASH_MAIN_BLOCK_SIZE)) ++/* Backup environment occupies second parameter block */ ++#define CONFIG_ENV_ADDR_REDUND ((CONFIG_ENV_ADDR)+(CONFIG_ENV_SECT_SIZE)) ++#endif ++ ++#define CONFIG_ENV_OVERWRITE ++ ++/* Magic number that indicates rebooting into upgrade mode */ ++#define UPGRADE_MAGIC 0x31 /* ASCII '1' */ ++ ++/* Magic number that indicates user recovery on reboot */ ++/* Also defined in hipox_user_recovery.agent */ ++#define RECOVERY_MAGIC 0x31 /* ASCII '1' */ ++ ++/* Magic number that indicates controlled power down on reboot */ ++/* Also defined in controlled_power_down.sh in init.d */ ++#define CONTROLLED_POWER_DOWN_MAGIC 0x31 /* ASCII '1' */ ++ ++/* This flag is set in SRAM location by Co Proc */ ++#define CONTROLLED_POWER_UP_MAGIC 0x31 /* ASCII '1' */ ++/* 9k + a quad from top */ ++/* Be carefule on changing the location of this flag ++ * u-boot has other things to write in SRAM too ++ */ ++#define POWER_ON_FLAG_SRAM_OFFSET 9220 ++#if (USE_LEON_TIME_COUNT == 1) ++#define MS_TIME_COUNT_SRAM_OFFSET (POWER_ON_FLAG_SRAM_OFFSET + 4) ++#endif ++ ++/* Size of malloc() pool */ ++#define CONFIG_SYS_MALLOC_LEN (2048 << 10) ++#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++ ++/** ++ * ASM startup control ++ */ ++/* Start of address within SRAM of loader's exception table. */ ++/* ROM-based exception table will redirect to here */ ++#define EXCEPTION_BASE (CONFIG_SYS_SRAM_BASE) ++ ++/* ++ * NAND FLash support ++ */ ++ ++/* ++#define NAND_ChipID_UNKNOWN 0 ++#define CFG_MAX_NAND_DEVICE 1 ++#define NAND_MAX_FLOORS 1 ++#define NAND_MAX_CHIPS 1 ++#define SECTORSIZE (2 * 1024) ++#define ADDR_COLUMN 1 ++#define ADDR_PAGE 2 ++#define ADDR_COLUMN_PAGE 3 ++#define CFG_NAND_BASE STATIC_CS1_BASE_PA ++#define NAND_WAIT_READY(nand) udelay(25); ++#define NAND_CTL_CLRALE(n) ++#define NAND_CTL_SETALE(n) ++#define NAND_CTL_CLRCLE(n) ++#define NAND_CTL_SETCLE(n) ++#define NAND_ENABLE_CE(n) ++#define NAND_DISABLE_CE(n) ++#define WRITE_NAND_COMMAND(d,adr) *(volatile __u8 *)((unsigned long)adr + 0x4000) = (__u8)(d) ++#define WRITE_NAND_ADDRESS(d,adr) *(volatile __u8 *)((unsigned long)adr + 0x8000) = (__u8)(d) ++#define WRITE_NAND(d,adr) *(volatile __u8 *)((unsigned long)adr) = (__u8)d ++#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) ++*/ ++#define CONFIG_SYS_NAND_BASE STATIC_CS0_BASE_PA ++#define CONFIG_SYS_NAND_ADDRESS_LATCH CONFIG_SYS_NAND_BASE + 0x8000 ++#define CONFIG_SYS_NAND_COMMAND_LATCH CONFIG_SYS_NAND_BASE + 0x4000 ++#define CONFIG_SYS_MAX_NAND_DEVICE 1 ++//#define writeb(v,a) *(volatile __u8 *)((unsigned long)a) = (__u8)v ++//#define writew(v,a) *(volatile __u16 *)((unsigned long)a) = (__u16)v ++//#define readb(a) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)a)) ++//#define readw(a) ((volatile __u16)(*(volatile __u8 *)(unsigned long)a)) ++// #define show_boot_progress(n) ++ ++/** ++ * Disk related stuff ++ */ ++#define CONFIG_LBA48 ++#define CONFIG_DOS_PARTITION ++#define CONFIG_SYS_IDE_MAXDEVICE 2 ++#define CONFIG_SYS_IDE_MAXBUS 1 ++#define CONFIG_IDE_PREINIT ++#undef CONFIG_IDE_RESET ++#undef CONFIG_IDE_LED ++#define CONFIG_SYS_ATA_BASE_ADDR SATA_DATA_BASE_PA ++#define CONFIG_SYS_ATA_DATA_OFFSET 0 ++#define CONFIG_SYS_ATA_REG_OFFSET 0 ++#define CONFIG_SYS_ATA_ALT_OFFSET 0 ++ ++/** ++ * System block reset and clock control ++ */ ++#define SYS_CTRL_USB11_CTRL (SYS_CONTROL_BASE_PA + 0x00) ++#define SYS_CTRL_PCI_CTRL0 (SYS_CONTROL_BASE_PA + 0x04) ++#define SYS_CTRL_PCI_CTRL1 (SYS_CONTROL_BASE_PA + 0x08) ++#define SYS_CTRL_GPIO_PRIMSEL_CTRL_0 (SYS_CONTROL_BASE_PA + 0x0C) ++#define SYS_CTRL_GPIO_PRIMSEL_CTRL_1 (SYS_CONTROL_BASE_PA + 0x10) ++#define SYS_CTRL_GPIO_SECSEL_CTRL_0 (SYS_CONTROL_BASE_PA + 0x14) ++#define SYS_CTRL_GPIO_SECSEL_CTRL_1 (SYS_CONTROL_BASE_PA + 0x18) ++#define SYS_CTRL_GPIO_TERTSEL_CTRL_0 (SYS_CONTROL_BASE_PA + 0x8C) ++#define SYS_CTRL_GPIO_TERTSEL_CTRL_1 (SYS_CONTROL_BASE_PA + 0x90) ++#define SYS_CTRL_USB11_STAT (SYS_CONTROL_BASE_PA + 0x1c) ++#define SYS_CTRL_PCI_STAT (SYS_CONTROL_BASE_PA + 0x20) ++#define SYS_CTRL_CKEN_SET_CTRL (SYS_CONTROL_BASE_PA + 0x2C) ++#define SYS_CTRL_CKEN_CLR_CTRL (SYS_CONTROL_BASE_PA + 0x30) ++#define SYS_CTRL_RSTEN_SET_CTRL (SYS_CONTROL_BASE_PA + 0x34) ++#define SYS_CTRL_RSTEN_CLR_CTRL (SYS_CONTROL_BASE_PA + 0x38) ++#define SYS_CTRL_PLLSYS_CTRL (SYS_CONTROL_BASE_PA + 0x48) ++#define SYS_CTRL_PLLSYS_KEY_CTRL (SYS_CONTROL_BASE_PA + 0x6C) ++#define SYS_CTRL_GMAC_CTRL (SYS_CONTROL_BASE_PA + 0x78) ++#define SYS_CTRL_UART_CTRL (SYS_CONTROL_BASE_PA + 0x94) ++ ++#define SYS_CTRL_CKEN_COPRO_BIT 0 ++#define SYS_CTRL_CKEN_DMA_BIT 1 ++#define SYS_CTRL_CKEN_DPE_BIT 2 ++#define SYS_CTRL_CKEN_DDR_BIT 3 ++#define SYS_CTRL_CKEN_SATA_BIT 4 ++#define SYS_CTRL_CKEN_I2S_BIT 5 ++#define SYS_CTRL_CKEN_USBHS_BIT 6 ++#define SYS_CTRL_CKEN_MAC_BIT 7 ++#define SYS_CTRL_CKEN_PCI_BIT 8 ++#define SYS_CTRL_CKEN_STATIC_BIT 9 ++#define SYS_CTRL_CKEN_DDR_PHY_BIT 10 ++ ++#define SYS_CTRL_RSTEN_ARM_BIT 0 ++#define SYS_CTRL_RSTEN_COPRO_BIT 1 ++#define SYS_CTRL_RSTEN_USBHS_BIT 4 ++#define SYS_CTRL_RSTEN_USBHSPHY_BIT 5 ++#define SYS_CTRL_RSTEN_MAC_BIT 6 ++#define SYS_CTRL_RSTEN_PCI_BIT 7 ++#define SYS_CTRL_RSTEN_DMA_BIT 8 ++#define SYS_CTRL_RSTEN_DPE_BIT 9 ++#define SYS_CTRL_RSTEN_DDR_BIT 10 ++#define SYS_CTRL_RSTEN_SATA_BIT 11 ++#define SYS_CTRL_RSTEN_SATA_LINK_BIT 12 ++#define SYS_CTRL_RSTEN_SATA_PHY_BIT 13 ++#define SYS_CTRL_RSTEN_STATIC_BIT 15 ++#define SYS_CTRL_RSTEN_GPIO_BIT 16 ++#define SYS_CTRL_RSTEN_UART1_BIT 17 ++#define SYS_CTRL_RSTEN_UART2_BIT 18 ++#define SYS_CTRL_RSTEN_MISC_BIT 19 ++#define SYS_CTRL_RSTEN_I2S_BIT 20 ++#define SYS_CTRL_RSTEN_AHB_MON_BIT 21 ++#define SYS_CTRL_RSTEN_UART3_BIT 22 ++#define SYS_CTRL_RSTEN_UART4_BIT 23 ++#define SYS_CTRL_RSTEN_SGDMA_BIT 24 ++#define SYS_CTRL_RSTEN_DDR_PHY_BIT 25 ++#define SYS_CTRL_RSTEN_BUS_BIT 31 ++ ++#define SYS_CTRL_GMAC_RGMII 2 ++#define SYS_CTRL_GMAC_SIMPLE_MAX 1 ++#define SYS_CTRL_GMAC_CKEN_GTX 0 ++ ++#define SYS_CTRL_CKCTRL_CTRL_ADDR (SYS_CONTROL_BASE_PA + 0x64) ++ ++#define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0 ++#define SYS_CTRL_CKCTRL_SLOW_BIT 8 ++ ++#define SYS_CTRL_UART2_DEQ_EN 0 ++#define SYS_CTRL_UART3_DEQ_EN 1 ++#define SYS_CTRL_UART3_IQ_EN 2 ++#define SYS_CTRL_UART4_IQ_EN 3 ++#define SYS_CTRL_UART4_NOT_PCI_MODE 4 ++ ++#define SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT 11 ++ ++/** ++ * SATA related definitions ++ */ ++#define ATA_PORT_CTL 0 ++#define ATA_PORT_FEATURE 1 ++#define ATA_PORT_NSECT 2 ++#define ATA_PORT_LBAL 3 ++#define ATA_PORT_LBAM 4 ++#define ATA_PORT_LBAH 5 ++#define ATA_PORT_DEVICE 6 ++#define ATA_PORT_COMMAND 7 ++ ++#define SATA_0_REGS_BASE (APB_BRIDGE_B_BASE_PA + 0x900000) ++#define SATA_1_REGS_BASE (APB_BRIDGE_B_BASE_PA + 0x910000) ++#define SATA_HOST_REGS_BASE (APB_BRIDGE_B_BASE_PA + 0x9e0000) ++ ++/* The offsets to the SATA registers */ ++#define SATA_ORB1_OFF 0 ++#define SATA_ORB2_OFF 1 ++#define SATA_ORB3_OFF 2 ++#define SATA_ORB4_OFF 3 ++#define SATA_ORB5_OFF 4 ++ ++#define SATA_FIS_ACCESS 11 ++#define SATA_INT_STATUS_OFF 12 /* Read only */ ++#define SATA_INT_CLR_OFF 12 /* Write only */ ++#define SATA_INT_ENABLE_OFF 13 /* Read only */ ++#define SATA_INT_ENABLE_SET_OFF 13 /* Write only */ ++#define SATA_INT_ENABLE_CLR_OFF 14 /* Write only */ ++#define SATA_VERSION_OFF 15 ++#define SATA_CONTROL_OFF 23 ++#define SATA_COMMAND_OFF 24 ++#define SATA_PORT_CONTROL_OFF 25 ++#define SATA_DRIVE_CONTROL_OFF 26 ++ ++/* The offsets to the link registers that are access in an asynchronous manner */ ++#define SATA_LINK_DATA 28 ++#define SATA_LINK_RD_ADDR 29 ++#define SATA_LINK_WR_ADDR 30 ++#define SATA_LINK_CONTROL 31 ++ ++/* SATA interrupt status register fields */ ++#define SATA_INT_STATUS_EOC_RAW_BIT ( 0 + 16) ++#define SATA_INT_STATUS_ERROR_BIT ( 2 + 16) ++#define SATA_INT_STATUS_EOADT_RAW_BIT ( 1 + 16) ++ ++/* SATA core command register commands */ ++#define SATA_CMD_WRITE_TO_ORB_REGS 2 ++#define SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND 4 ++ ++#define SATA_CMD_BUSY_BIT 7 ++ ++#define SATA_SCTL_CLR_ERR 0x00000316UL ++ ++#define SATA_OPCODE_MASK 0x3 ++ ++#define SATA_LBAL_BIT 0 ++#define SATA_LBAM_BIT 8 ++#define SATA_LBAH_BIT 16 ++#define SATA_HOB_LBAH_BIT 24 ++#define SATA_DEVICE_BIT 24 ++#define SATA_NSECT_BIT 0 ++#define SATA_FEATURE_BIT 16 ++#define SATA_COMMAND_BIT 24 ++#define SATA_CTL_BIT 24 ++ ++/* ATA status (7) register field definitions */ ++#define ATA_STATUS_BSY_BIT 7 ++#define ATA_STATUS_DRDY_BIT 6 ++#define ATA_STATUS_DF_BIT 5 ++#define ATA_STATUS_DRQ_BIT 3 ++#define ATA_STATUS_ERR_BIT 0 ++ ++/* ATA device (6) register field definitions */ ++#define ATA_DEVICE_FIXED_MASK 0xA0 ++#define ATA_DEVICE_DRV_BIT 4 ++#define ATA_DEVICE_DRV_NUM_BITS 1 ++#define ATA_DEVICE_LBA_BIT 6 ++ ++/* ATA control (0) register field definitions */ ++#define ATA_CTL_SRST_BIT 2 ++ ++/* ATA Command register initiated commands */ ++#define ATA_CMD_INIT 0x91 ++#define ATA_CMD_IDENT 0xEC ++ ++#define SATA_STD_ASYNC_REGS_OFF 0x20 ++#define SATA_SCR_STATUS 0 ++#define SATA_SCR_ERROR 1 ++#define SATA_SCR_CONTROL 2 ++#define SATA_SCR_ACTIVE 3 ++#define SATA_SCR_NOTIFICAION 4 ++ ++#define SATA_BURST_BUF_FORCE_EOT_BIT 0 ++#define SATA_BURST_BUF_DATA_INJ_ENABLE_BIT 1 ++#define SATA_BURST_BUF_DIR_BIT 2 ++#define SATA_BURST_BUF_DATA_INJ_END_BIT 3 ++#define SATA_BURST_BUF_FIFO_DIS_BIT 4 ++#define SATA_BURST_BUF_DIS_DREQ_BIT 5 ++#define SATA_BURST_BUF_DREQ_BIT 6 ++ ++/* Button on GPIO 32 */ ++#define RECOVERY_BUTTON (0x00000001 << 0) ++#define RECOVERY_PRISEL_REG SYS_CTRL_GPIO_PRIMSEL_CTRL_1 ++#define RECOVERY_SECSEL_REG SYS_CTRL_GPIO_SECSEL_CTRL_1 ++#define RECOVERY_TERSEL_REG SYS_CTRL_GPIO_TERTSEL_CTRL_1 ++#define RECOVERY_CLR_OE_REG GPIO_2_CLR_OE ++#define RECOVERY_DEBOUNCE_REG GPIO_2_INPUT_DEBOUNCE_ENABLE ++#define RECOVERY_DATA GPIO_2_PA ++ ++#endif // CONFIG_H +diff -Nurd u-boot-2009.03.orig/lib_arm/board.c u-boot-2009.03/lib_arm/board.c +--- u-boot-2009.03.orig/lib_arm/board.c 2009-04-15 11:05:24.000000000 +0200 ++++ u-boot-2009.03/lib_arm/board.c 2009-04-15 11:08:18.000000000 +0200 +@@ -201,6 +201,10 @@ + } + puts("DRAM: "); + print_size(size, "\n"); ++ ++ puts("SRAM: "); ++ printf("%ld KB at 0x%08lx\n", (long)(gd->bd->bi_sramsize >> 10), ++ (unsigned long)gd->bd->bi_sramstart); + #endif + + return (0); diff --git a/recipes/u-boot/u-boot_2009.03.bb b/recipes/u-boot/u-boot_2009.03.bb new file mode 100644 index 0000000000..11f2a0e441 --- /dev/null +++ b/recipes/u-boot/u-boot_2009.03.bb @@ -0,0 +1,20 @@ +PR = "r1" +require u-boot.inc + +DEFAULT_PREFERENCE = "-1" +DEFAULT_PREFERENCE_hipox = "1" + +SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2 " + +SRC_URI_append_hipox = "file://00-hipox.patch;patch=1 " + +TARGET_LDFLAGS = "" + +UBOOT_MACHINE_hipox = "hipox_config" + +inherit base + +do_compile () { + oe_runmake ${UBOOT_MACHINE} + oe_runmake all +} diff --git a/recipes/uclibc/uclibc.inc b/recipes/uclibc/uclibc.inc index be085ab513..f2f3e9b605 100644 --- a/recipes/uclibc/uclibc.inc +++ b/recipes/uclibc/uclibc.inc @@ -208,7 +208,7 @@ do_install() { rmdir ${D}/usr/bin fi - oe_runmake utils + oe_runmake "SSP_ALL_CFLAGS=${TARGET_LINK_HASH_STYLE}" utils oe_runmake STRIPTOOL=true PREFIX=${D} DEVEL_PREFIX=${prefix}/ RUNTIME_PREFIX=/ \ install_utils diff --git a/recipes/udev/udev-141/init b/recipes/udev/udev-141/init new file mode 100644 index 0000000000..9e11f08989 --- /dev/null +++ b/recipes/udev/udev-141/init @@ -0,0 +1,60 @@ +#!/bin/sh -e + +### BEGIN INIT INFO +# Provides: udev +# Required-Start: mountvirtfs +# Required-Stop: +# Default-Start: S +# Default-Stop: +# Short-Description: Start udevd, populate /dev and load drivers. +### END INIT INFO + +export TZ=/etc/localtime + +[ -d /sys/class ] || exit 1 +[ -r /proc/mounts ] || exit 1 +[ -x /sbin/udevd ] || exit 1 +[ -f /etc/udev/udev.conf ] && . /etc/udev/udev.conf + +kill_udevd() { + if [ -x /sbin/pidof ]; then + pid=`/sbin/pidof -x udevd` + [ -n "$pid" ] && kill $pid + fi +} + +export ACTION=add +# propagate /dev from /sys +echo -n "Starting udev" + +# mount the tmpfs on /dev, if not already done +LANG=C awk "\$2 == \"/dev\" && \$4 == \"tmpfs\" { exit 1 }" /proc/mounts && { + mount -n -o mode=0755 -t tmpfs none "/dev" + mkdir -m 0755 /dev/pts + mkdir -m 0755 /dev/shm +} + +if [ -e /etc/dev.tar ]; then + (cd /; tar xf /etc/dev.tar) + not_first_boot=1 +fi + +# make_extra_nodes +kill_udevd > "/dev/null" 2>&1 + + # trigger the sorted events + echo -e '\000\000\000\000' > /proc/sys/kernel/hotplug + /sbin/udevd -d + + /sbin/udevadm control env STARTUP=1 + if [ "$not_first_boot" != "" ];then + /sbin/udevadm trigger --subsystem-nomatch=tty --subsystem-nomatch=mem --subsystem-nomatch=vc --subsystem-nomatch=vtconsole --subsystem-nomatch=misc --subsystem-nomatch=dcon --subsystem-nomatch=pci_bus --subsystem-nomatch=graphics --subsystem-nomatch=backlight --subsystem-nomatch=video4linux --subsystem-nomatch=platform + (/sbin/udevadm settle --timeout=3; /sbin/udevadm control env STARTUP=)& + else + /sbin/udevadm trigger + /sbin/udevadm settle + (cd /; tar cf /etc/dev.tar dev) + fi + +echo +exit 0 diff --git a/recipes/udev/udev-141/local.rules b/recipes/udev/udev-141/local.rules new file mode 100644 index 0000000000..a4866923fd --- /dev/null +++ b/recipes/udev/udev-141/local.rules @@ -0,0 +1,32 @@ +# There are a number of modifiers that are allowed to be used in some +# of the different fields. They provide the following subsitutions: +# +# %n the "kernel number" of the device. +# For example, 'sda3' has a "kernel number" of '3' +# %e the smallest number for that name which does not matches an existing node +# %k the kernel name for the device +# %M the kernel major number for the device +# %m the kernel minor number for the device +# %b the bus id for the device +# %c the string returned by the PROGRAM +# %s{filename} the content of a sysfs attribute +# %% the '%' char itself +# + +# Media automounting +SUBSYSTEM=="block", ACTION=="add" RUN+="/etc/udev/scripts/mount.sh" +SUBSYSTEM=="block", ACTION=="remove" RUN+="/etc/udev/scripts/mount.sh" + +# Handle network interface setup +SUBSYSTEM=="net", ACTION=="add" RUN+="/etc/udev/scripts/network.sh" +SUBSYSTEM=="net", ACTION=="remove" RUN+="/etc/udev/scripts/network.sh" + +# The first rtc device is symlinked to /dev/rtc +KERNEL=="rtc0", SYMLINK+="rtc" + +# Try and modprobe for drivers for new hardware +ACTION=="add", DEVPATH=="/devices/*", ENV{MODALIAS}=="?*", RUN+="/sbin/modprobe $env{MODALIAS}" + +# Create a symlink to any touchscreen input device +SUBSYSTEM=="input", KERNEL=="event[0-9]*", SYSFS{modalias}=="input:*-e0*,3,*a0,1,*18,*", SYMLINK+="input/touchscreen0" +SUBSYSTEM=="input", KERNEL=="event[0-9]*", SYSFS{modalias}=="ads7846", SYMLINK+="input/touchscreen0" diff --git a/recipes/udev/udev-141/permissions.rules b/recipes/udev/udev-141/permissions.rules new file mode 100644 index 0000000000..940d163047 --- /dev/null +++ b/recipes/udev/udev-141/permissions.rules @@ -0,0 +1,119 @@ +ACTION!="add", GOTO="permissions_end" + +# workarounds needed to synchronize with sysfs +# only needed for kernels < v2.6.18-rc1 +ENV{PHYSDEVPATH}!="?*", ENV{PHYSDEVBUS}=="?*", WAIT_FOR_SYSFS="bus" +SUBSYSTEM=="scsi", KERNEL=="[0-9]*:[0-9]*", WAIT_FOR_SYSFS="ioerr_cnt" +# only needed for kernels < 2.6.16 +SUBSYSTEM=="net", WAIT_FOR_SYSFS="address" +# only needed for kernels < 2.6.17 +SUBSYSTEM=="net", ENV{DRIVER}=="?*", WAIT_FOR_SYSFS="device/driver" + +# devices needed to load the drivers providing them +KERNEL=="tun", OPTIONS+="ignore_remove" +KERNEL=="ppp", OPTIONS+="ignore_remove" +KERNEL=="loop[0-9]*", OPTIONS+="ignore_remove" + +# default permissions for block devices +SUBSYSTEM=="block", GROUP="disk" +# the aacraid driver is broken and reports that disks removable (see #404927) +SUBSYSTEM=="block", ATTRS{removable}=="1", \ + DRIVERS!="aacraid", GROUP="floppy" +# all block devices on these buses are "removable" +SUBSYSTEM=="block", SUBSYSTEMS=="usb|ieee1394|mmc|pcmcia", GROUP="floppy" + +# IDE devices +KERNEL=="hd[a-z]|pcd[0-9]*", DRIVERS=="ide-cdrom|pcd", \ + IMPORT{program}="cdrom_id --export $tempnode" +ENV{ID_CDROM}=="?*", GROUP="cdrom" +KERNEL=="ht[0-9]*", GROUP="tape" +KERNEL=="nht[0-9]*", GROUP="tape" + +# SCSI devices +KERNEL=="sr[0-9]*", IMPORT{program}="cdrom_id --export $tempnode" +SUBSYSTEMS=="scsi", ATTRS{type}=="1", GROUP="tape" +SUBSYSTEMS=="scsi", ATTRS{type}=="4", GROUP="cdrom" +SUBSYSTEMS=="scsi", ATTRS{type}=="5", GROUP="cdrom" +SUBSYSTEMS=="scsi", ATTRS{type}=="8", GROUP="tape" + +# USB devices +KERNEL=="legousbtower*", MODE="0666" +KERNEL=="lp[0-9]*", SUBSYSTEMS=="usb", GROUP="lp" + +# usbfs-like devices +SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", \ + MODE="0664" + +# iRiver music players +SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", GROUP="plugdev", \ + ATTRS{idVendor}=="4102", ATTRS{idProduct}=="10[01][135789]" + +# serial devices +SUBSYSTEM=="tty", GROUP="dialout" +SUBSYSTEM=="capi", GROUP="dialout" +SUBSYSTEM=="slamr", GROUP="dialout" +SUBSYSTEM=="zaptel", GROUP="dialout" + +# vc devices (all members of the tty subsystem) +KERNEL=="ptmx", MODE="0666", GROUP="root" +KERNEL=="console", MODE="0600", GROUP="root" +KERNEL=="tty", MODE="0666", GROUP="root" +KERNEL=="tty[0-9]*", GROUP="root" +KERNEL=="pty*", MODE="0666", GROUP="tty" + +# video devices +SUBSYSTEM=="video4linux", GROUP="video" +SUBSYSTEM=="drm", GROUP="video" +SUBSYSTEM=="dvb", GROUP="video" +SUBSYSTEM=="em8300", GROUP="video" +SUBSYSTEM=="graphics", GROUP="video" +SUBSYSTEM=="nvidia", GROUP="video" + +# misc devices +KERNEL=="random", MODE="0666" +KERNEL=="urandom", MODE="0666" +KERNEL=="mem", MODE="0640", GROUP="kmem" +KERNEL=="kmem", MODE="0640", GROUP="kmem" +KERNEL=="port", MODE="0640", GROUP="kmem" +KERNEL=="full", MODE="0666" +KERNEL=="null", MODE="0666" +KERNEL=="zero", MODE="0666" +KERNEL=="inotify", MODE="0666" +KERNEL=="sgi_fetchop", MODE="0666" +KERNEL=="sonypi", MODE="0666" +KERNEL=="agpgart", GROUP="video" +KERNEL=="rtc|rtc[0-9]*", GROUP="audio" +KERNEL=="kqemu", MODE="0666" +KERNEL=="tun", MODE="0666", + +KERNEL=="cdemu[0-9]*", GROUP="cdrom" +KERNEL=="pktcdvd[0-9]*", GROUP="cdrom" +KERNEL=="pktcdvd", MODE="0644" + +# printers and parallel devices +SUBSYSTEM=="printer", GROUP="lp" +SUBSYSTEM=="ppdev", GROUP="lp" +KERNEL=="irlpt*", GROUP="lp" +KERNEL=="pt[0-9]*", GROUP="tape" +KERNEL=="pht[0-9]*", GROUP="tape" + +# sound devices +SUBSYSTEM=="sound", GROUP="audio" + +# ieee1394 devices +KERNEL=="raw1394", GROUP="disk" +KERNEL=="dv1394*", GROUP="video" +KERNEL=="video1394*", GROUP="video" + +# input devices +KERNEL=="event[0-9]*", ATTRS{name}=="*dvb*|*DVB*|* IR *" \ + MODE="0664", GROUP="video" +KERNEL=="js[0-9]*", MODE="0664" +KERNEL=="lirc[0-9]*", GROUP="video" + +# AOE character devices +SUBSYSTEM=="aoe", MODE="0220", GROUP="disk" +SUBSYSTEM=="aoe", KERNEL=="err", MODE="0440" + +LABEL="permissions_end" + diff --git a/recipes/udev/udev-141/run.rules b/recipes/udev/udev-141/run.rules new file mode 100644 index 0000000000..75d71375bb --- /dev/null +++ b/recipes/udev/udev-141/run.rules @@ -0,0 +1,14 @@ +# debugging monitor +RUN+="socket:/org/kernel/udev/monitor" + +# run a command on remove events +ACTION=="remove", ENV{REMOVE_CMD}!="", RUN+="$env{REMOVE_CMD}" + +# ignore the events generated by virtual consoles +KERNEL=="ptmx", OPTIONS+="last_rule" +KERNEL=="console", OPTIONS+="last_rule" +KERNEL=="tty" , OPTIONS+="last_rule" +KERNEL=="tty[0-9]*", OPTIONS+="last_rule" +KERNEL=="pty*", OPTIONS+="last_rule" +SUBSYSTEM=="vc", OPTIONS+="last_rule" + diff --git a/recipes/udev/udev-141/udev.rules b/recipes/udev/udev-141/udev.rules new file mode 100644 index 0000000000..a19d4a0bf6 --- /dev/null +++ b/recipes/udev/udev-141/udev.rules @@ -0,0 +1,116 @@ +# There are a number of modifiers that are allowed to be used in some +# of the different fields. They provide the following subsitutions: +# +# %n the "kernel number" of the device. +# For example, 'sda3' has a "kernel number" of '3' +# %e the smallest number for that name which does not matches an existing node +# %k the kernel name for the device +# %M the kernel major number for the device +# %m the kernel minor number for the device +# %b the bus id for the device +# %c the string returned by the PROGRAM +# %s{filename} the content of a sysfs attribute +# %% the '%' char itself +# + +# workaround for devices which do not report media changes +SUBSYSTEMS=="ide", KERNEL=="hd[a-z]", ATTR{removable}=="1", \ + ENV{ID_MODEL}=="IOMEGA_ZIP*", NAME="%k", OPTIONS+="all_partitions" +SUBSYSTEMS=="ide", KERNEL=="hd[a-z]", ATTRS{media}=="floppy", \ + OPTIONS+="all_partitions" + +# SCSI devices +SUBSYSTEMS=="scsi", KERNEL=="sr[0-9]*", NAME="scd%n", SYMLINK+="sr%n" + +# USB devices +SUBSYSTEMS=="usb", KERNEL=="auer[0-9]*", NAME="usb/%k" +SUBSYSTEMS=="usb", KERNEL=="cpad[0-9]*", NAME="usb/%k" +SUBSYSTEMS=="usb", KERNEL=="dabusb*", NAME="usb/%k" +SUBSYSTEMS=="usb", KERNEL=="hiddev*", NAME="usb/%k" +SUBSYSTEMS=="usb", KERNEL=="legousbtower*", NAME="usb/%k" +SUBSYSTEMS=="usb", KERNEL=="lp[0-9]*", NAME="usb/%k" +SUBSYSTEMS=="usb", KERNEL=="ttyUSB*", \ + ATTRS{product}=="Palm Handheld*|Handspring Visor|palmOne Handheld", \ + SYMLINK+="pilot" + +# usbfs-like devices +SUBSYSTEM=="usb_device", PROGRAM="/bin/sh -c 'K=%k; K=$${K#usbdev}; printf bus/usb/%%03i/%%03i $${K%%%%.*} $${K#*.}'", ACTION=="add", \ + NAME="%c" +SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}" + +# serial devices +KERNEL=="capi", NAME="capi20", SYMLINK+="isdn/capi20" +KERNEL=="capi[0-9]*", NAME="capi/%n" + +# video devices +KERNEL=="dvb*", PROGRAM="/bin/sh -c 'K=%k; K=$${K#dvb}; printf dvb/adapter%%i/%%s $${K%%%%.*} $${K#*.}", ACTION=="add", \ + NAME="%c" +KERNEL=="card[0-9]*", NAME="dri/%k" + +# misc devices +KERNEL=="hw_random", NAME="hwrng" +KERNEL=="tun", NAME="net/%k" +KERNEL=="evtchn", NAME="xen/%k" + +KERNEL=="cdemu[0-9]*", NAME="cdemu/%n" +KERNEL=="pktcdvd[0-9]*", NAME="pktcdvd/%n" +KERNEL=="pktcdvd", NAME="pktcdvd/control" + +KERNEL=="cpu[0-9]*", NAME="cpu/%n/cpuid" +KERNEL=="msr[0-9]*", NAME="cpu/%n/msr" +KERNEL=="microcode", NAME="cpu/microcode" + +KERNEL=="umad*", NAME="infiniband/%k" +KERNEL=="issm*", NAME="infiniband/%k" +KERNEL=="uverbs*", NAME="infiniband/%k" +KERNEL=="ucm*", NAME="infiniband/%k" +KERNEL=="rdma_ucm", NAME="infiniband/%k" + +# ALSA devices +KERNEL=="controlC[0-9]*", NAME="snd/%k" +KERNEL=="hwC[D0-9]*", NAME="snd/%k" +KERNEL=="pcmC[D0-9cp]*", NAME="snd/%k" +KERNEL=="midiC[D0-9]*", NAME="snd/%k" +KERNEL=="timer", NAME="snd/%k" +KERNEL=="seq", NAME="snd/%k" + +# ieee1394 devices +KERNEL=="dv1394*", NAME="dv1394/%n" +KERNEL=="video1394*", NAME="video1394/%n" + +# input devices +KERNEL=="mice", NAME="input/%k" +KERNEL=="mouse[0-9]*", NAME="input/%k" +KERNEL=="event[0-9]*", NAME="input/%k" +KERNEL=="js[0-9]*", NAME="input/%k" +KERNEL=="ts[0-9]*", NAME="input/%k" +KERNEL=="uinput", NAME="input/%k" + +# Zaptel +KERNEL=="zapctl", NAME="zap/ctl" +KERNEL=="zaptimer", NAME="zap/timer" +KERNEL=="zapchannel", NAME="zap/channel" +KERNEL=="zappseudo", NAME="zap/pseudo" +KERNEL=="zap[0-9]*", NAME="zap/%n" + +# AOE character devices +SUBSYSTEM=="aoe", KERNEL=="discover", NAME="etherd/%k" +SUBSYSTEM=="aoe", KERNEL=="err", NAME="etherd/%k" +SUBSYSTEM=="aoe", KERNEL=="interfaces", NAME="etherd/%k" +SUBSYSTEM=="aoe", KERNEL=="revalidate", NAME="etherd/%k" + +# device mapper creates its own device nodes, so ignore these +KERNEL=="dm-[0-9]*", OPTIONS+="ignore_device" +KERNEL=="device-mapper", NAME="mapper/control" + +KERNEL=="rfcomm[0-9]*", NAME="%k", GROUP="users", MODE="0660" + +# Firmware Helper +ACTION=="add", SUBSYSTEM=="firmware", RUN+="/lib/udev/firmware.sh" + +# Samsung UARTS +KERNEL=="s3c2410_serial[0-9]", NAME="ttySAC%n" + +# MXC UARTs +KERNEL=="ttymxc[0-4]", NAME="ttymxc%n" + diff --git a/recipes/udev/udev_141.bb b/recipes/udev/udev_141.bb new file mode 100644 index 0000000000..a11c13d563 --- /dev/null +++ b/recipes/udev/udev_141.bb @@ -0,0 +1,55 @@ +DESCRIPTION = "udev is a daemon which dynamically creates and removes device nodes from \ +/dev/, handles hotplug events and loads drivers at boot time. It replaces \ +the hotplug package and requires a kernel not older than 2.6.12." +RPROVIDES_${PN} = "hotplug" + +# Untested, fails to creat shared libs +DEFAULT_PREFERENCE = "-1" + +SRC_URI = "http://kernel.org/pub/linux/utils/kernel/hotplug/udev-${PV}.tar.gz \ + file://mount.blacklist \ + file://run.rules \ + " + +SRC_URI_append_h2200 = " file://50-hostap_cs.rules " +PACKAGE_ARCH_h2200 = "h2200" + +require udev.inc + +INITSCRIPT_PARAMS = "start 03 S ." + +FILES_${PN} += "${base_libdir}/udev/*" +FILES_${PN}-dbg += "${base_libdir}/udev/.debug" +UDEV_EXTRAS = "extras/firmware/ extras/scsi_id/ extras/volume_id/" +EXTRA_OEMAKE += "libudevdir=/lib/udev libdir=${base_libdir} prefix=" + +do_install () { + install -d ${D}${usrsbindir} \ + ${D}${sbindir} + oe_runmake 'DESTDIR=${D}' INSTALL=install install + install -d ${D}${sysconfdir}/init.d + install -m 0755 ${WORKDIR}/init ${D}${sysconfdir}/init.d/udev + + install -d ${D}${sysconfdir}/udev/rules.d/ + + install -m 0644 ${WORKDIR}/mount.blacklist ${D}${sysconfdir}/udev/ + install -m 0644 ${WORKDIR}/local.rules ${D}${sysconfdir}/udev/rules.d/local.rules + install -m 0644 ${WORKDIR}/permissions.rules ${D}${sysconfdir}/udev/rules.d/permissions.rules + install -m 0644 ${WORKDIR}/run.rules ${D}${sysconfdir}/udev/rules.d/run.rules + install -m 0644 ${WORKDIR}/udev.rules ${D}${sysconfdir}/udev/rules.d/udev.rules + install -m 0644 ${WORKDIR}/links.conf ${D}${sysconfdir}/udev/links.conf + if [ "${UDEV_DEVFS_RULES}" = "1" ]; then + install -m 0644 ${WORKDIR}/devfs-udev.rules ${D}${sysconfdir}/udev/rules.d/devfs-udev.rules + fi + + install -d ${D}${sysconfdir}/udev/scripts/ + + install -m 0755 ${WORKDIR}/mount.sh ${D}${sysconfdir}/udev/scripts/mount.sh + install -m 0755 ${WORKDIR}/network.sh ${D}${sysconfdir}/udev/scripts + + install -d ${D}${base_libdir}/udev/ +} + +do_install_append_h2200() { + install -m 0644 ${WORKDIR}/50-hostap_cs.rules ${D}${sysconfdir}/udev/rules.d/50-hostap_cs.rules +} diff --git a/recipes/xorg-xserver/xserver-xorg_1.5.3.bb b/recipes/xorg-xserver/xserver-xorg_1.5.3.bb index 79df5b3bf2..74ea3c41e5 100644 --- a/recipes/xorg-xserver/xserver-xorg_1.5.3.bb +++ b/recipes/xorg-xserver/xserver-xorg_1.5.3.bb @@ -4,10 +4,12 @@ DESCRIPTION = "the X.Org X server" DEPENDS += "pixman libpciaccess openssl" RDEPENDS += "hal" PE = "2" -PR = "r4" +PR = "r5" SRC_URI += "file://drmfix.patch;patch=1 \ - file://sysroot_fix.patch;patch=1" + file://sysroot_fix.patch;patch=1 \ + file://xorg-avr32-support.diff;patch=1 \ +" MESA_VER = "7.2" diff --git a/recipes/xserver-kdrive-common/xserver-kdrive-common/Xserver b/recipes/xserver-kdrive-common/xserver-kdrive-common/Xserver index f6f5943847..584cb0a53c 100644 --- a/recipes/xserver-kdrive-common/xserver-kdrive-common/Xserver +++ b/recipes/xserver-kdrive-common/xserver-kdrive-common/Xserver @@ -155,7 +155,7 @@ case `module_id` in "Freescale MX21ADS") # That's what /proc/cpuinfo shows as hardware on the chumby ARGS="$ARGS -dpi 121 -screen 320x240 -hide-cursor -mouse tslib" ;; - "OMAP3 Beagle Board") + "OMAP3 Beagle Board" | "Gumstix Overo") ARGS="$ARGS ${PPM}" # 32bpp - we'll enable it once newer kernels are.. working. # ARGS="$ARGS -fbbpp32" diff --git a/recipes/xserver-kdrive-common/xserver-kdrive-common_0.1.bb b/recipes/xserver-kdrive-common/xserver-kdrive-common_0.1.bb index 6b585c44e0..abd7191863 100644 --- a/recipes/xserver-kdrive-common/xserver-kdrive-common_0.1.bb +++ b/recipes/xserver-kdrive-common/xserver-kdrive-common_0.1.bb @@ -1,7 +1,7 @@ DESCRIPTION = "Common X11 scripts" LICENSE = "GPL" SECTION = "x11" -PR = "r36" +PR = "r37" SRC_URI = "\ file://Xdefaults \ |