rename packages/ to recipes/ per earlier agreement

See links below for more details:
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21326
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21816

Signed-off-by: Denys Dmytriyenko <denis@denix.org>
Acked-by: Mike Westerhof <mwester@dls.net>
Acked-by: Philip Balister <philip@balister.org>
Acked-by: Khem Raj <raj.khem@gmail.com>
Acked-by: Marcin Juszkiewicz <hrw@openembedded.org>
Acked-by: Koen Kooi <koen@openembedded.org>
Acked-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>

1 files changed, 1233 insertions, 0 deletions

diff --git a/recipes/u-boot/u-boot-mkimage-openmoko-native/uboot-20061030-qt2410.patch b/recipes/u-boot/u-boot-mkimage-openmoko-native/uboot-20061030-qt2410.patch
new file mode 100644
index 0000000000..feedd8bb39
--- /dev/null
+++ b/recipes/u-boot/u-boot-mkimage-openmoko-native/uboot-20061030-qt2410.patch
@@ -0,0 +1,1233 @@
+This patch adds 'board' support for the Armzone QT2410
+development board to u-boot.
+
+Signed-off-by: Harald Welte <laforge@openmoko.org>
+
+Index: u-boot/Makefile
+===================================================================
+--- u-boot.orig/Makefile
++++ u-boot/Makefile
+@@ -2009,6 +2009,9 @@
+ sbc2410x_config: unconfig
+ 	@$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
+ 
++qt2410_config	:	unconfig
++	@./mkconfig $(@:_config=) arm arm920t qt2410 NULL s3c24x0
++
+ scb9328_config	:	unconfig
+ 	@$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx
+ 
+Index: u-boot/board/qt2410/Makefile
+===================================================================
+--- /dev/null
++++ u-boot/board/qt2410/Makefile
+@@ -0,0 +1,47 @@
++#
++# (C) Copyright 2000, 2001, 2002
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= lib$(BOARD).a
++
++OBJS	:= qt2410.o flash.o
++SOBJS	:= lowlevel_init.o
++
++$(LIB):	$(OBJS) $(SOBJS)
++	$(AR) crv $@ $(OBJS) $(SOBJS)
++
++clean:
++	rm -f $(SOBJS) $(OBJS)
++
++distclean:	clean
++	rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+Index: u-boot/board/qt2410/config.mk
+===================================================================
+--- /dev/null
++++ u-boot/board/qt2410/config.mk
+@@ -0,0 +1,29 @@
++#
++# (C) Copyright 2002
++# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
++#
++# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
++#
++# see http://www.samsung.com/ for more information on SAMSUNG
++#
++
++CONFIG_USB_DFU_VENDOR=0x1457
++CONFIG_USB_DFU_PRODUCT=0x511d
++CONFIG_USB_DFU_REVISION=0x0100
++
++#
++# SMDK2410 has 1 bank of 64 MB DRAM
++#
++# 3000'0000 to 3400'0000
++#
++# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
++# optionally with a ramdisk at 3080'0000
++#
++# we load ourself to 33F8'0000
++#
++# download area is 3300'0000
++#
++
++
++TEXT_BASE = 0x33F80000
+Index: u-boot/board/qt2410/flash.c
+===================================================================
+--- /dev/null
++++ u-boot/board/qt2410/flash.c
+@@ -0,0 +1,435 @@
++/*
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Alex Zuepke <azu@sysgo.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++
++ulong myflush (void);
++
++
++#define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
++#define MAIN_SECT_SIZE  0x10000	/* 64 KB */
++
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
++
++
++#define CMD_READ_ARRAY		0x000000F0
++#define CMD_UNLOCK1		0x000000AA
++#define CMD_UNLOCK2		0x00000055
++#define CMD_ERASE_SETUP		0x00000080
++#define CMD_ERASE_CONFIRM	0x00000030
++#define CMD_PROGRAM		0x000000A0
++#define CMD_UNLOCK_BYPASS	0x00000020
++
++#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
++#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
++
++#define BIT_ERASE_DONE		0x00000080
++#define BIT_RDY_MASK		0x00000080
++#define BIT_PROGRAM_ERROR	0x00000020
++#define BIT_TIMEOUT		0x80000000	/* our flag */
++
++#define READY 1
++#define ERR   2
++#define TMO   4
++
++/*-----------------------------------------------------------------------
++ */
++
++ulong flash_init (void)
++{
++	int i, j;
++	ulong size = 0;
++
++	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
++		ulong flashbase = 0;
++
++		flash_info[i].flash_id =
++#if defined(CONFIG_AMD_LV400)
++			(AMD_MANUFACT & FLASH_VENDMASK) |
++			(AMD_ID_LV400B & FLASH_TYPEMASK);
++#elif defined(CONFIG_AMD_LV800)
++			(AMD_MANUFACT & FLASH_VENDMASK) |
++			(AMD_ID_LV800B & FLASH_TYPEMASK);
++#else
++#error "Unknown flash configured"
++#endif
++			flash_info[i].size = FLASH_BANK_SIZE;
++		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
++		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
++		if (i == 0)
++			flashbase = PHYS_FLASH_1;
++		else
++			panic ("configured too many flash banks!\n");
++		for (j = 0; j < flash_info[i].sector_count; j++) {
++			if (j <= 3) {
++				/* 1st one is 16 KB */
++				if (j == 0) {
++					flash_info[i].start[j] =
++						flashbase + 0;
++				}
++
++				/* 2nd and 3rd are both 8 KB */
++				if ((j == 1) || (j == 2)) {
++					flash_info[i].start[j] =
++						flashbase + 0x4000 + (j -
++								      1) *
++						0x2000;
++				}
++
++				/* 4th 32 KB */
++				if (j == 3) {
++					flash_info[i].start[j] =
++						flashbase + 0x8000;
++				}
++			} else {
++				flash_info[i].start[j] =
++					flashbase + (j - 3) * MAIN_SECT_SIZE;
++			}
++		}
++		size += flash_info[i].size;
++	}
++
++	flash_protect (FLAG_PROTECT_SET,
++		       CFG_FLASH_BASE,
++		       CFG_FLASH_BASE + monitor_flash_len - 1,
++		       &flash_info[0]);
++
++#if 0
++	flash_protect (FLAG_PROTECT_SET,
++		       CFG_ENV_ADDR,
++		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
++#endif
++
++	return size;
++}
++
++/*-----------------------------------------------------------------------
++ */
++void flash_print_info (flash_info_t * info)
++{
++	int i;
++
++	switch (info->flash_id & FLASH_VENDMASK) {
++	case (AMD_MANUFACT & FLASH_VENDMASK):
++		printf ("AMD: ");
++		break;
++	default:
++		printf ("Unknown Vendor ");
++		break;
++	}
++
++	switch (info->flash_id & FLASH_TYPEMASK) {
++	case (AMD_ID_LV400B & FLASH_TYPEMASK):
++		printf ("1x Amd29LV400BB (4Mbit)\n");
++		break;
++	case (AMD_ID_LV800B & FLASH_TYPEMASK):
++		printf ("1x Amd29LV800BB (8Mbit)\n");
++		break;
++	default:
++		printf ("Unknown Chip Type\n");
++		goto Done;
++		break;
++	}
++
++	printf ("  Size: %ld MB in %d Sectors\n",
++		info->size >> 20, info->sector_count);
++
++	printf ("  Sector Start Addresses:");
++	for (i = 0; i < info->sector_count; i++) {
++		if ((i % 5) == 0) {
++			printf ("\n   ");
++		}
++		printf (" %08lX%s", info->start[i],
++			info->protect[i] ? " (RO)" : "     ");
++	}
++	printf ("\n");
++
++      Done:;
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t * info, int s_first, int s_last)
++{
++	ushort result;
++	int iflag, cflag, prot, sect;
++	int rc = ERR_OK;
++	int chip;
++
++	/* first look for protection bits */
++
++	if (info->flash_id == FLASH_UNKNOWN)
++		return ERR_UNKNOWN_FLASH_TYPE;
++
++	if ((s_first < 0) || (s_first > s_last)) {
++		return ERR_INVAL;
++	}
++
++	if ((info->flash_id & FLASH_VENDMASK) !=
++	    (AMD_MANUFACT & FLASH_VENDMASK)) {
++		return ERR_UNKNOWN_FLASH_VENDOR;
++	}
++
++	prot = 0;
++	for (sect = s_first; sect <= s_last; ++sect) {
++		if (info->protect[sect]) {
++			prot++;
++		}
++	}
++	if (prot)
++		return ERR_PROTECTED;
++
++	/*
++	 * Disable interrupts which might cause a timeout
++	 * here. Remember that our exception vectors are
++	 * at address 0 in the flash, and we don't want a
++	 * (ticker) exception to happen while the flash
++	 * chip is in programming mode.
++	 */
++	cflag = icache_status ();
++	icache_disable ();
++	iflag = disable_interrupts ();
++
++	/* Start erase on unprotected sectors */
++	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
++		printf ("Erasing sector %2d ... ", sect);
++
++		/* arm simple, non interrupt dependent timer */
++		reset_timer_masked ();
++
++		if (info->protect[sect] == 0) {	/* not protected */
++			vu_short *addr = (vu_short *) (info->start[sect]);
++
++			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
++			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
++			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
++
++			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
++			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
++			*addr = CMD_ERASE_CONFIRM;
++
++			/* wait until flash is ready */
++			chip = 0;
++
++			do {
++				result = *addr;
++
++				/* check timeout */
++				if (get_timer_masked () >
++				    CFG_FLASH_ERASE_TOUT) {
++					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
++					chip = TMO;
++					break;
++				}
++
++				if (!chip
++				    && (result & 0xFFFF) & BIT_ERASE_DONE)
++					chip = READY;
++
++				if (!chip
++				    && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
++					chip = ERR;
++
++			} while (!chip);
++
++			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
++
++			if (chip == ERR) {
++				rc = ERR_PROG_ERROR;
++				goto outahere;
++			}
++			if (chip == TMO) {
++				rc = ERR_TIMOUT;
++				goto outahere;
++			}
++
++			printf ("ok.\n");
++		} else {	/* it was protected */
++
++			printf ("protected!\n");
++		}
++	}
++
++	if (ctrlc ())
++		printf ("User Interrupt!\n");
++
++      outahere:
++	/* allow flash to settle - wait 10 ms */
++	udelay_masked (10000);
++
++	if (iflag)
++		enable_interrupts ();
++
++	if (cflag)
++		icache_enable ();
++
++	return rc;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash
++ */
++
++volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
++{
++	vu_short *addr = (vu_short *) dest;
++	ushort result;
++	int rc = ERR_OK;
++	int cflag, iflag;
++	int chip;
++
++	/*
++	 * Check if Flash is (sufficiently) erased
++	 */
++	result = *addr;
++	if ((result & data) != data)
++		return ERR_NOT_ERASED;
++
++
++	/*
++	 * Disable interrupts which might cause a timeout
++	 * here. Remember that our exception vectors are
++	 * at address 0 in the flash, and we don't want a
++	 * (ticker) exception to happen while the flash
++	 * chip is in programming mode.
++	 */
++	cflag = icache_status ();
++	icache_disable ();
++	iflag = disable_interrupts ();
++
++	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
++	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
++	MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
++	*addr = CMD_PROGRAM;
++	*addr = data;
++
++	/* arm simple, non interrupt dependent timer */
++	reset_timer_masked ();
++
++	/* wait until flash is ready */
++	chip = 0;
++	do {
++		result = *addr;
++
++		/* check timeout */
++		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
++			chip = ERR | TMO;
++			break;
++		}
++		if (!chip && ((result & 0x80) == (data & 0x80)))
++			chip = READY;
++
++		if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
++			result = *addr;
++
++			if ((result & 0x80) == (data & 0x80))
++				chip = READY;
++			else
++				chip = ERR;
++		}
++
++	} while (!chip);
++
++	*addr = CMD_READ_ARRAY;
++
++	if (chip == ERR || *addr != data)
++		rc = ERR_PROG_ERROR;
++
++	if (iflag)
++		enable_interrupts ();
++
++	if (cflag)
++		icache_enable ();
++
++	return rc;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash.
++ */
++
++int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
++{
++	ulong cp, wp;
++	int l;
++	int i, rc;
++	ushort data;
++
++	wp = (addr & ~1);	/* get lower word aligned address */
++
++	/*
++	 * handle unaligned start bytes
++	 */
++	if ((l = addr - wp) != 0) {
++		data = 0;
++		for (i = 0, cp = wp; i < l; ++i, ++cp) {
++			data = (data >> 8) | (*(uchar *) cp << 8);
++		}
++		for (; i < 2 && cnt > 0; ++i) {
++			data = (data >> 8) | (*src++ << 8);
++			--cnt;
++			++cp;
++		}
++		for (; cnt == 0 && i < 2; ++i, ++cp) {
++			data = (data >> 8) | (*(uchar *) cp << 8);
++		}
++
++		if ((rc = write_hword (info, wp, data)) != 0) {
++			return (rc);
++		}
++		wp += 2;
++	}
++
++	/*
++	 * handle word aligned part
++	 */
++	while (cnt >= 2) {
++		data = *((vu_short *) src);
++		if ((rc = write_hword (info, wp, data)) != 0) {
++			return (rc);
++		}
++		src += 2;
++		wp += 2;
++		cnt -= 2;
++	}
++
++	if (cnt == 0) {
++		return ERR_OK;
++	}
++
++	/*
++	 * handle unaligned tail bytes
++	 */
++	data = 0;
++	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
++		data = (data >> 8) | (*src++ << 8);
++		--cnt;
++	}
++	for (; i < 2; ++i, ++cp) {
++		data = (data >> 8) | (*(uchar *) cp << 8);
++	}
++
++	return write_hword (info, wp, data);
++}
+Index: u-boot/board/qt2410/lowlevel_init.S
+===================================================================
+--- /dev/null
++++ u-boot/board/qt2410/lowlevel_init.S
+@@ -0,0 +1,171 @@
++/*
++ * Memory Setup stuff - taken from blob memsetup.S
++ *
++ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
++ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
++ *
++ * Modified for the Samsung SMDK2410 by
++ * (C) Copyright 2002
++ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++
++#include <config.h>
++#include <version.h>
++
++
++/* some parameters for the board */
++
++/*
++ *
++ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
++ *
++ * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar@sec.samsung.com>
++ *
++ */
++
++#define BWSCON	0x48000000
++
++/* BWSCON */
++#define DW8		 	(0x0)
++#define DW16		 	(0x1)
++#define DW32		 	(0x2)
++#define WAIT		 	(0x1<<2)
++#define UBLB		 	(0x1<<3)
++
++#define B1_BWSCON	  	(DW32)
++#define B2_BWSCON	  	(DW16)
++#define B3_BWSCON	  	(DW16 + WAIT + UBLB)
++#define B4_BWSCON	  	(DW16)
++#define B5_BWSCON	  	(DW16)
++#define B6_BWSCON	  	(DW32)
++#define B7_BWSCON	  	(DW32)
++
++/* BANK0CON */
++#define B0_Tacs		 	0x0	/*  0clk */
++#define B0_Tcos		 	0x0	/*  0clk */
++#define B0_Tacc		 	0x7	/* 14clk */
++#define B0_Tcoh		 	0x0	/*  0clk */
++#define B0_Tah		 	0x0	/*  0clk */
++#define B0_Tacp		 	0x0
++#define B0_PMC		 	0x0	/* normal */
++
++/* BANK1CON */
++#define B1_Tacs		 	0x0	/*  0clk */
++#define B1_Tcos		 	0x0	/*  0clk */
++#define B1_Tacc		 	0x7	/* 14clk */
++#define B1_Tcoh		 	0x0	/*  0clk */
++#define B1_Tah		 	0x0	/*  0clk */
++#define B1_Tacp		 	0x0
++#define B1_PMC		 	0x0
++
++#define B2_Tacs		 	0x0
++#define B2_Tcos		 	0x0
++#define B2_Tacc		 	0x7
++#define B2_Tcoh		 	0x0
++#define B2_Tah		 	0x0
++#define B2_Tacp		 	0x0
++#define B2_PMC		 	0x0
++
++#define B3_Tacs		 	0x0	/*  0clk */
++#define B3_Tcos		 	0x3	/*  4clk */
++#define B3_Tacc		 	0x7	/* 14clk */
++#define B3_Tcoh		 	0x1	/*  1clk */
++#define B3_Tah		 	0x0	/*  0clk */
++#define B3_Tacp		 	0x3     /*  6clk */
++#define B3_PMC		 	0x0	/* normal */
++
++#define B4_Tacs		 	0x0	/*  0clk */
++#define B4_Tcos		 	0x0	/*  0clk */
++#define B4_Tacc		 	0x7	/* 14clk */
++#define B4_Tcoh		 	0x0	/*  0clk */
++#define B4_Tah		 	0x0	/*  0clk */
++#define B4_Tacp		 	0x0
++#define B4_PMC		 	0x0	/* normal */
++
++#define B5_Tacs		 	0x0	/*  0clk */
++#define B5_Tcos		 	0x0	/*  0clk */
++#define B5_Tacc		 	0x7	/* 14clk */
++#define B5_Tcoh		 	0x0	/*  0clk */
++#define B5_Tah		 	0x0	/*  0clk */
++#define B5_Tacp		 	0x0
++#define B5_PMC		 	0x0	/* normal */
++
++#define B6_MT		 	0x3	/* SDRAM */
++#define B6_Trcd	 	 	0x1
++#define B6_SCAN		 	0x1	/* 9bit */
++
++#define B7_MT		 	0x3	/* SDRAM */
++#define B7_Trcd		 	0x1	/* 3clk */
++#define B7_SCAN		 	0x1	/* 9bit */
++
++/* REFRESH parameter */
++#define REFEN		 	0x1	/* Refresh enable */
++#define TREFMD		 	0x0	/* CBR(CAS before RAS)/Auto refresh */
++#define Trp		 	0x1	/* 3clk */
++#define Trc		 	0x3	/* 7clk */
++#define Tchr		 	0x2	/* 3clk */
++//#define REFCNT		 	1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
++#define REFCNT		 	997	/* period=17.5us, HCLK=60Mhz, (2048+1-15.6*60) */
++/**************************************/
++
++_TEXT_BASE:
++	.word	TEXT_BASE
++
++.globl lowlevel_init
++lowlevel_init:
++	/* memory control configuration */
++	/* make r0 relative the current location so that it */
++	/* reads SMRDATA out of FLASH rather than memory ! */
++	adr	r0, SMRDATA
++	ldr	r1, =BWSCON	/* Bus Width Status Controller */
++	add     r2, r0, #13*4
++0:
++	ldr     r3, [r0], #4
++	str     r3, [r1], #4
++	cmp     r2, r0
++	bne     0b
++
++	/* setup asynchronous bus mode */
++	mrc	p15, 0, r1 ,c1 ,c0, 0
++	orr	r1, r1, #0xc0000000
++	mcr	p15, 0, r1, c1, c0, 0
++
++	/* everything is fine now */
++	mov	pc, lr
++
++	.ltorg
++/* the literal pools origin */
++
++SMRDATA:
++    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
++    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
++    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
++    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
++    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
++    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
++    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
++    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
++    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
++    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
++    .word 0xb2
++    .word 0x30
++    .word 0x30
+Index: u-boot/board/qt2410/qt2410.c
+===================================================================
+--- /dev/null
++++ u-boot/board/qt2410/qt2410.c
+@@ -0,0 +1,152 @@
++/*
++ * (C) 2006 by Openmoko, Inc.
++ * Author: Harald Welte <laforge@openmoko.org>
++ *
++ * based on existing S3C2410 startup code in u-boot:
++ *
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Marius Groeger <mgroeger@sysgo.de>
++ *
++ * (C) Copyright 2002
++ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <video_fb.h>
++#include <usbdcore.h>
++#include <s3c2410.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#if 1
++//#define M_MDIV	0xA1		/* Fout = 202.8MHz */
++//#define M_PDIV	0x3
++//#define M_SDIV	0x1
++#define M_MDIV	0x90		/* Fout = 202.8MHz */
++#define M_PDIV	0x7
++#define M_SDIV	0x0
++#else
++#define M_MDIV	0x5c		/* Fout = 150.0MHz */
++#define M_PDIV	0x4
++#define M_SDIV	0x0
++#endif
++
++#if 1
++#define U_M_MDIV	0x78
++#define U_M_PDIV	0x2
++#define U_M_SDIV	0x3
++#else
++#define U_M_MDIV	0x48
++#define U_M_PDIV	0x3
++#define U_M_SDIV	0x2
++#endif
++
++static inline void delay (unsigned long loops)
++{
++	__asm__ volatile ("1:\n"
++	  "subs %0, %1, #1\n"
++	  "bne 1b":"=r" (loops):"0" (loops));
++}
++
++/*
++ * Miscellaneous platform dependent initialisations
++ */
++
++int board_init (void)
++{
++	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
++	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++
++	/* to reduce PLL lock time, adjust the LOCKTIME register */
++	clk_power->LOCKTIME = 0xFFFFFF;
++
++	/* configure MPLL */
++	clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
++
++	/* some delay between MPLL and UPLL */
++	delay (4000);
++
++	/* configure UPLL */
++	clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
++
++	/* some delay between MPLL and UPLL */
++	delay (8000);
++
++	/* set up the I/O ports */
++	gpio->GPACON = 0x007FFFFF;
++	gpio->GPBCON = 0x00044555;
++	gpio->GPBUP = 0x000007FF;
++	gpio->GPCCON = 0xAAAAAAAA;
++	gpio->GPCUP = 0x0000FFFF;
++	gpio->GPDCON = 0xAAAAAAAA;
++	gpio->GPDUP = 0x0000FFFF;
++	gpio->GPECON = 0xAAAAAAAA;
++	gpio->GPEUP = 0x0000FFFF;
++	gpio->GPFCON = 0x000055AA;
++	gpio->GPFUP = 0x000000FF;
++	gpio->GPGCON = 0xFF95FFBA;
++	//gpio->GPGUP = 0x0000FFFF;
++	gpio->GPGUP = 0x0000AFEF;
++	gpio->GPHCON = 0x0028FAAA;
++	gpio->GPHUP = 0x000007FF;
++
++	/* arch number of SMDK2410-Board */
++	gd->bd->bi_arch_number = MACH_TYPE_QT2410;
++
++	/* adress of boot parameters */
++	gd->bd->bi_boot_params = 0x30000100;
++
++	icache_enable();
++	dcache_enable();
++
++	return 0;
++}
++
++#if defined(CONFIG_USB_DEVICE)
++void udc_ctrl(enum usbd_event event, int param)
++{
++}
++#endif
++
++void board_video_init(GraphicDevice *pGD)
++{
++	S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
++
++	/* FIXME: select LCM type by env variable */
++
++	/* Configuration for GTA01 LCM on QT2410 */
++	lcd->LCDCON1 = 0x00000178; /* CLKVAL=1, BPPMODE=16bpp, TFT, ENVID=0 */
++
++	lcd->LCDCON2 = 0x019fc3c1;
++	lcd->LCDCON3 = 0x0039df67;
++	lcd->LCDCON4 = 0x00000007;
++	lcd->LCDCON5 = 0x0001cf09;
++	lcd->LPCSEL  = 0x00000000;
++}
++
++int dram_init (void)
++{
++	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++	return 0;
++}
+Index: u-boot/board/qt2410/u-boot.lds
+===================================================================
+--- /dev/null
++++ u-boot/board/qt2410/u-boot.lds
+@@ -0,0 +1,58 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++	. = 0x00000000;
++
++	. = ALIGN(4);
++	.text      :
++	{
++	  cpu/arm920t/start.o	(.text)
++	  cpu/arm920t/s3c24x0/nand_read.o (.text)
++	  *(.text)
++	}
++
++	. = ALIGN(4);
++	.rodata : { *(.rodata) }
++
++	. = ALIGN(4);
++	.data : { *(.data) }
++
++	. = ALIGN(4);
++	.got : { *(.got) }
++
++	. = .;
++	__u_boot_cmd_start = .;
++	.u_boot_cmd : { *(.u_boot_cmd) }
++	__u_boot_cmd_end = .;
++
++	. = ALIGN(4);
++	__bss_start = .;
++	.bss : { *(.bss) }
++	_end = .;
++}
+Index: u-boot/include/configs/qt2410.h
+===================================================================
+--- /dev/null
++++ u-boot/include/configs/qt2410.h
+@@ -0,0 +1,287 @@
++/*
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Marius Groeger <mgroeger@sysgo.de>
++ * Gary Jennejohn <gj@denx.de>
++ * David Mueller <d.mueller@elsoft.ch>
++ *
++ * Configuation settings for the Armzone QT2410 board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#if 0
++/* If we want to start u-boot from usb bootloader in NOR flash */
++#define CONFIG_SKIP_RELOCATE_UBOOT	1
++#define	CONFIG_SKIP_LOWLEVEL_INIT	1
++#else
++/* If we want to start u-boot directly from within NAND flash */
++#define CONFIG_S3C2410_NAND_BOOT	1
++#define CONFIG_S3C2410_NAND_SKIP_BAD	1
++#endif
++
++#define CFG_UBOOT_SIZE            0x40000
++
++/*
++ * High Level Configuration Options
++ * (easy to change)
++ */
++#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
++#define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */
++#define CONFIG_SMDK2410		1	/* on a SAMSUNG SMDK2410 Board  */
++
++/* input clock of PLL */
++#define CONFIG_SYS_CLK_FREQ	12000000/* the SMDK2410 has 12MHz input clock */
++
++
++#define USE_920T_MMU		1
++#define CONFIG_USE_IRQ		1
++
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 400*1024)
++#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
++
++/*
++ * Hardware drivers
++ */
++#if 0
++#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
++#define CS8900_BASE		0x19000300
++#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
++#endif
++
++/*
++ * select serial console configuration
++ */
++#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SMDK2410 */
++#define CONFIG_HWFLOW		1
++
++/************************************************************
++ * RTC
++ ************************************************************/
++#define	CONFIG_RTC_S3C24X0	1
++
++/* allow to overwrite serial and ethaddr */
++#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_BAUDRATE		115200
++
++/***********************************************************
++ * Command definition
++ ***********************************************************/
++#define CONFIG_COMMANDS (\
++			CFG_CMD_BDI	 | \
++			CFG_CMD_LOADS	 | \
++			CFG_CMD_LOADB	 | \
++			CFG_CMD_IMI	 | \
++			CFG_CMD_CACHE	 | \
++			CFG_CMD_MEMORY	 | \
++			CFG_CMD_ENV	 | \
++			/* CFG_CMD_IRQ	 | */ \
++			CFG_CMD_BOOTD	 | \
++			CFG_CMD_CONSOLE	 | \
++			CFG_CMD_BMP	 | \
++			CFG_CMD_ASKENV	 | \
++			CFG_CMD_RUN	 | \
++			CFG_CMD_ECHO 	 | \
++			CFG_CMD_I2C 	 | \
++			CFG_CMD_REGINFO	 | \
++			CFG_CMD_IMMAP	 | \
++			CFG_CMD_DATE	 | \
++			CFG_CMD_AUTOSCRIPT | \
++			CFG_CMD_BSP	 | \
++			CFG_CMD_ELF	 | \
++			CFG_CMD_MISC	 | \
++			/* CFG_CMD_USB	 | */ \
++			CFG_CMD_JFFS2	 | \
++			CFG_CMD_DIAG	 | \
++			CFG_CMD_HWFLOW	 | \
++			CFG_CMD_SAVES	 | \
++			CFG_CMD_NAND	 | \
++			CFG_CMD_PORTIO	 | \
++			CFG_CMD_MMC	 | \
++			CFG_CMD_FAT	 | \
++			CFG_CMD_EXT2	 | \
++			0)
++
++#if 0
++			CFG_CMD_DHCP	 | \
++			CFG_CMD_PING	 | \
++			CFG_CMD_NET	 | \
++
++#endif
++
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <cmd_confdefs.h>
++
++#define CONFIG_BOOTDELAY	3
++#define CONFIG_BOOTARGS    	"rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC0,115200 console=tty0 loglevel=8"
++#define CONFIG_ETHADDR		01:ab:cd:ef:fe:dc
++#define CONFIG_NETMASK          255.255.255.0
++#define CONFIG_IPADDR		10.0.0.110
++#define CONFIG_SERVERIP		10.0.0.1
++/*#define CONFIG_BOOTFILE	"elinos-lart" */
++#define CONFIG_BOOTCOMMAND	"nand load 0x32000000 0x34000 0x200000; bootm 0x32000000"
++
++#define CONFIG_DOS_PARTITION	1
++
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
++/* what's this ? it's not used anywhere */
++#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
++#endif
++
++/*
++ * Miscellaneous configurable options
++ */
++#define	CFG_LONGHELP				/* undef to save memory		*/
++#define	CFG_PROMPT		"QT2410 # "	/* Monitor Command Prompt	*/
++#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
++#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
++#define	CFG_MAXARGS		64		/* max number of command args	*/
++#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
++
++#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
++#define CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/
++
++#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
++
++#define	CFG_LOAD_ADDR		0x33000000	/* default load address	*/
++
++/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
++/* it to wrap 100 times (total 1562500) to get 1 sec. */
++#define	CFG_HZ			1562500
++
++/* valid baudrates */
++#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
++
++/*-----------------------------------------------------------------------
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
++#endif
++
++#define CONFIG_USB_OHCI		1
++
++#define CONFIG_USB_DEVICE	1
++#define CONFIG_USB_TTY		1
++#define CFG_CONSOLE_IS_IN_ENV	1
++#define CONFIG_USBD_VENDORID		0x1457     /* Linux/NetChip */
++#define CONFIG_USBD_PRODUCTID_GSERIAL	0x5120    /* gserial */
++#define CONFIG_USBD_PRODUCTID_CDCACM	0x511d    /* CDC ACM */
++#define CONFIG_USBD_MANUFACTURER	"Armzone"
++#define CONFIG_USBD_PRODUCT_NAME	"QT2410 Bootloader " U_BOOT_VERSION
++#define CONFIG_EXTRA_ENV_SETTINGS	"usbtty=cdc_acm\0"
++#define CONFIG_USBD_DFU			1
++#define CONFIG_USBD_DFU_XFER_SIZE	0x4000
++
++/*-----------------------------------------------------------------------
++ * Physical Memory Map
++ */
++#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
++#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
++#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
++#define PHYS_SDRAM_RES_SIZE	0x00200000 /* 2 MB for frame buffer */
++
++#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
++
++#define CFG_FLASH_BASE		PHYS_FLASH_1
++
++/*-----------------------------------------------------------------------
++ * FLASH and environment organization
++ */
++
++#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
++
++#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
++#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
++#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
++
++/* timeout values are in ticks */
++#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
++#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
++
++#define	CFG_ENV_IS_IN_NAND	1
++#define CFG_ENV_SIZE		0x4000		/* 16k Total Size of Environment Sector */
++#define CFG_ENV_OFFSET_OOB	1		/* Location of ENV stored in block 0 OOB */
++
++#define NAND_MAX_CHIPS		1
++#define CFG_NAND_BASE		0x4e000000
++#define CFG_MAX_NAND_DEVICE	1
++
++#define CONFIG_MMC		1
++#define CFG_MMC_BASE		0xff000000
++
++#define CONFIG_EXT2		1
++
++/* FAT driver in u-boot is broken currently */
++#define CONFIG_FAT		1
++#define CONFIG_SUPPORT_VFAT
++
++#if 1
++/* JFFS2 driver */
++#define CONFIG_JFFS2_CMDLINE	1
++#define CONFIG_JFFS2_NAND	1
++#define CONFIG_JFFS2_NAND_DEV	0
++//#define CONFIG_JFFS2_NAND_OFF		0x634000
++//#define CONFIG_JFFS2_NAND_SIZE	0x39cc000
++#endif
++
++/* ATAG configuration */
++#define CONFIG_INITRD_TAG		1
++#define CONFIG_SETUP_MEMORY_TAGS	1
++#define CONFIG_CMDLINE_TAG		1
++
++#define CONFIG_DRIVER_S3C24X0_I2C	1
++#define CONFIG_HARD_I2C			1
++#define CFG_I2C_SPEED			400000  /* 400kHz according to PCF50606 data sheet */
++#define CFG_I2C_SLAVE			0x7f
++
++#define CONFIG_VIDEO
++#define CONFIG_VIDEO_S3C2410
++#define CONFIG_CFB_CONSOLE
++#define CONFIG_VIDEO_LOGO
++#define CONFIG_SPLASH_SCREEN
++#define CFG_VIDEO_LOGO_MAX_SIZE		(640*480+1024+100) /* 100 = slack */
++#define CONFIG_VIDEO_BMP_GZIP
++#define CONFIG_VGA_AS_SINGLE_DEVICE
++#define CONFIG_UNZIP
++
++#define VIDEO_KBD_INIT_FCT     0
++#define VIDEO_TSTC_FCT         serial_tstc
++#define VIDEO_GETC_FCT         serial_getc
++
++#define LCD_VIDEO_ADDR         0x33d00000
++
++#define CONFIG_S3C2410_NAND_BBT	1
++
++#define MTDIDS_DEFAULT		"nand0=qt2410-nand"
++#define MTPARTS_DEFAULT		"qt2410-nand:192k(u-boot),8k(u-boot_env),2M(kernel),2M(splash),-(jffs2)"
++
++#endif	/* __CONFIG_H */