linux-omap: add recipe for 2.6.29 and update git version to that as well

32 files changed, 24083 insertions, 21450 deletions

diff --git a/recipes/linux/linux-omap/0001-DSS-New-display-subsystem-driver-for-OMAP2-3.patch b/recipes/linux/linux-omap/0001-DSS-New-display-subsystem-driver-for-OMAP2-3.patch
deleted file mode 100644
index fda5191421..0000000000
--- a/recipes/linux/linux-omap/0001-DSS-New-display-subsystem-driver-for-OMAP2-3.patch
+++ /dev/null
@@ -1,10365 +0,0 @@
-From 3128e95ff7e6a1bed47cc5c64a138cc3bbab492a Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Wed, 7 Jan 2009 14:30:09 +0200
-Subject: [PATCH] DSS: New display subsystem driver for OMAP2/3
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- Documentation/arm/OMAP/DSS                |  266 +++
- arch/arm/plat-omap/Kconfig                |    2 +
- arch/arm/plat-omap/Makefile               |    2 +
- arch/arm/plat-omap/dss/Kconfig            |   69 +
- arch/arm/plat-omap/dss/Makefile           |    6 +
- arch/arm/plat-omap/dss/dispc.c            | 2113 +++++++++++++++++++
- arch/arm/plat-omap/dss/display.c          |  787 +++++++
- arch/arm/plat-omap/dss/dpi.c              |  344 ++++
- arch/arm/plat-omap/dss/dsi.c              | 3187 +++++++++++++++++++++++++++++
- arch/arm/plat-omap/dss/dss.c              |  774 +++++++
- arch/arm/plat-omap/dss/dss.h              |  274 +++
- arch/arm/plat-omap/dss/rfbi.c             | 1262 ++++++++++++
- arch/arm/plat-omap/dss/sdi.c              |  174 ++
- arch/arm/plat-omap/dss/venc.c             |  506 +++++
- arch/arm/plat-omap/include/mach/display.h |  462 +++++
- 15 files changed, 10228 insertions(+), 0 deletions(-)
- create mode 100644 Documentation/arm/OMAP/DSS
- create mode 100644 arch/arm/plat-omap/dss/Kconfig
- create mode 100644 arch/arm/plat-omap/dss/Makefile
- create mode 100644 arch/arm/plat-omap/dss/dispc.c
- create mode 100644 arch/arm/plat-omap/dss/display.c
- create mode 100644 arch/arm/plat-omap/dss/dpi.c
- create mode 100644 arch/arm/plat-omap/dss/dsi.c
- create mode 100644 arch/arm/plat-omap/dss/dss.c
- create mode 100644 arch/arm/plat-omap/dss/dss.h
- create mode 100644 arch/arm/plat-omap/dss/rfbi.c
- create mode 100644 arch/arm/plat-omap/dss/sdi.c
- create mode 100644 arch/arm/plat-omap/dss/venc.c
- create mode 100644 arch/arm/plat-omap/include/mach/display.h
-
-diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
-new file mode 100644
-index 0000000..a5e608c
---- /dev/null
-+++ b/Documentation/arm/OMAP/DSS
-@@ -0,0 +1,266 @@
-+OMAP2/3 Display Subsystem
-+-------------------------
-+
-+This is an almost total rewrite of the OMAP FB driver in drivers/video/omap
-+(let's call it DSS1). The main differences between DSS1 and DSS2 are DSI,
-+TV-out and multiple display support.
-+
-+The DSS2 driver (omap-dss module) is in arch/arm/plat-omap/dss/, and the FB,
-+panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live
-+currently side by side, you can choose which one to use.
-+
-+Features
-+--------
-+
-+Working and tested features include:
-+
-+- MIPI DPI (parallel) output
-+- MIPI DSI output in command mode
-+- MIPI DBI (RFBI) output (not tested for a while, might've gotten broken)
-+- SDI output
-+- TV output
-+- All pieces can be compiled as a module or inside kernel
-+- Use DISPC to update any of the outputs
-+- Use CPU to update RFBI or DSI output
-+- OMAP DISPC planes
-+- RGB16, RGB24 packed, RGB24 unpacked
-+- YUV2, UYVY
-+- Scaling
-+- Adjusting DSS FCK to find a good pixel clock
-+- Use DSI DPLL to create DSS FCK
-+
-+omap-dss driver
-+------------
-+
-+The DSS driver does not itself have any support for Linux framebuffer, V4L or
-+such like the current ones, but it has an internal kernel API that upper level
-+drivers can use.
-+
-+The DSS driver models OMAP's overlays, overlay managers and displays in a
-+flexible way to enable non-common multi-display configuration. In addition to
-+modelling the hardware overlays, omap-dss supports virtual overlays and overlay
-+managers. These can be used when updating a display with CPU or system DMA.
-+
-+Panel and controller drivers
-+----------------------------
-+
-+The drivers implement panel or controller specific functionality and are not
-+visible to users except through omapfb driver.  They register themselves to the
-+DSS driver.
-+
-+omapfb driver
-+-------------
-+
-+The omapfb driver implements arbitrary number of standard linux framebuffers.
-+These framebuffers can be routed flexibly to any overlays, thus allowing very
-+dynamic display architecture.
-+
-+The driver exports some omapfb specific ioctls, which are compatible with the
-+ioctls in the old driver.
-+
-+The rest of the non standard features are exported via sysfs. Whether the final
-+implementation will use sysfs, or ioctls, is still open.
-+
-+V4L2 drivers
-+------------
-+
-+Currently there are no V4L2 display drivers planned, but it is possible to
-+implement such either to omapfb driver, or as a separate one. From omap-dss
-+point of view the V4L2 drivers should be similar to framebuffer driver.
-+
-+Architecture
-+--------------------
-+
-+Some clarification what the different components do:
-+
-+    - Framebuffer is a memory area inside OMAP's SDRAM that contains the pixel
-+      data for the image. Framebuffer has width and height and color depth.
-+    - Overlay defines where the pixels are read from and where they go on the
-+      screen. The overlay may be smaller than framebuffer, thus displaying only
-+      part of the framebuffer. The position of the overlay may be changed if
-+      the overlay is smaller than the display.
-+    - Overlay manager combines the overlays in to one image and feeds them to
-+      display.
-+    - Display is the actual physical display device.
-+
-+A framebuffer can be connected to multiple overlays to show the same pixel data
-+on all of the overlays. Note that in this case the overlay input sizes must be
-+the same, but, in case of video overlays, the output size can be different. Any
-+framebuffer can be connected to any overlay.
-+
-+An overlay can be connected to one overlay manager. Also DISPC overlays can be
-+connected only to DISPC overlay managers, and virtual overlays can be only
-+connected to virtual overlays.
-+
-+An overlay manager can be connected to one display. There are certain
-+restrictions which kinds of displays an overlay manager can be connected:
-+
-+    - DISPC TV overlay manager can be only connected to TV display.
-+    - Virtual overlay managers can only be connected to DBI or DSI displays.
-+    - DISPC LCD overlay manager can be connected to all displays, except TV
-+      display.
-+
-+Sysfs
-+-----
-+The sysfs interface is a hack, but works for testing. I don't think sysfs
-+interface is the best for this in the final version, but I don't quite know
-+what would be the best interfaces for these things.
-+
-+In /sys/devices/platform/omapfb we have four files: framebuffers,
-+overlays, managers and displays. You can read them so see the current
-+setup, and change them by writing to it in the form of
-+"<item-id> <opt1>:<val1> <opt2>:<val2>..."
-+
-+"framebuffers" lists all framebuffers. Its format is:
-+	<fb number>
-+	p:<physical address, read only>
-+	v:<virtual address, read only>
-+	s:<size, read only>
-+	t:<target overlay>
-+
-+"overlays" lists all overlays. Its format is:
-+	<overlay name>
-+	t:<target manager>
-+	x:<xpos>
-+	y:<ypos>
-+	iw:<input width, read only>
-+	ih:<input height, read only>
-+	w:<output width>
-+	h:<output height>
-+	e:<enabled>
-+
-+"managers" lists all overlay managers. Its format is:
-+	<manager name>
-+	t:<target display>
-+
-+"displays" lists all displays. Its format is:
-+	<display name>
-+	e:<enabled>
-+	u:<update mode>
-+	t:<tear sync on/off>
-+	h:<xres/hfp/hbp/hsw>
-+	v:<yres/vfp/vbp/vsw>
-+	p:<pix clock, in kHz>
-+	m:<mode str, as in drivers/video/modedb.c:fb_find_mode>
-+
-+There is also a debug sysfs file at /sys/devices/platform/omap-dss/clk which
-+shows how DSS has configured the clocks.
-+
-+Examples
-+--------
-+
-+In the example scripts "omapfb" is a symlink to /sys/devices/platform/omapfb/.
-+
-+Default setup on OMAP3 SDP
-+--------------------------
-+
-+Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI
-+and TV-out are not in use. The columns from left to right are:
-+framebuffers, overlays, overlay managers, displays. Framebuffers are
-+handled by omapfb, and the rest by the DSS.
-+
-+FB0 --- GFX  -\            DVI
-+FB1 --- VID1 --+- LCD ---- LCD
-+FB2 --- VID2 -/   TV ----- TV
-+
-+Switch from LCD to DVI
-+----------------------
-+
-+dviline=`cat omapfb/displays |grep dvi`
-+w=`echo $dviline | cut -d " " -f 5 | cut -d ":" -f 2 | cut -d "/" -f 1`
-+h=`echo $dviline | cut -d " " -f 6 | cut -d ":" -f 2 | cut -d "/" -f 1`
-+
-+echo "lcd e:0" > omapfb/displays
-+echo "lcd t:none" > omapfb/managers
-+fbset -fb /dev/fb0 -xres $w -yres $h
-+# at this point you have to switch the dvi/lcd dip-switch from the omap board
-+echo "lcd t:dvi" > omapfb/managers
-+echo "dvi e:1" > omapfb/displays
-+
-+After this the configuration looks like:
-+
-+FB0 --- GFX  -\         -- DVI
-+FB1 --- VID1 --+- LCD -/   LCD
-+FB2 --- VID2 -/   TV ----- TV
-+
-+Clone GFX overlay to LCD and TV
-+-------------------------------
-+
-+tvline=`cat /sys/devices/platform/omapfb/displays |grep tv`
-+w=`echo $tvline | cut -d " " -f 5 | cut -d ":" -f 2 | cut -d "/" -f 1`
-+h=`echo $tvline | cut -d " " -f 6 | cut -d ":" -f 2 | cut -d "/" -f 1`
-+
-+echo "1 t:none" > omapfb/framebuffers
-+echo "0 t:gfx,vid1" > omapfb/framebuffers
-+echo "gfx e:1" > omapfb/overlays
-+echo "vid1 t:tv w:$w h:$h e:1" > omapfb/overlays
-+echo "tv e:1" > omapfb/displays
-+
-+After this the configuration looks like (only relevant parts shown):
-+
-+FB0 +-- GFX  ---- LCD ---- LCD
-+     \- VID1 ---- TV  ---- TV
-+
-+Misc notes
-+----------
-+
-+OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator. If
-+that fails, it will fall back to dma_alloc_writecombine().
-+
-+Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
-+of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
-+
-+Arguments
-+---------
-+
-+vram
-+	- Amount of total VRAM to preallocate. For example, "10M".
-+
-+omapfb.video_mode
-+	- Default video mode for default display. For example,
-+	  "800x400MR-24@60".  See drivers/video/modedb.c
-+
-+omapfb.vram
-+	- VRAM allocated for each framebuffer. Normally omapfb allocates vram
-+	  depending on the display size. With this you can manually allocate
-+	  more. For example "4M,3M" allocates 4M for fb0, 3M for fb1.
-+
-+omapfb.debug
-+	- Enable debug printing. You have to have OMAPFB debug support enabled
-+	  in kernel config.
-+
-+omap-dss.def_disp
-+	- Name of default display, to which all overlays will be connected.
-+	  Common examples are "lcd" or "tv".
-+
-+omap-dss.debug
-+	- Enable debug printing. You have to have DSS debug support enabled in
-+	  kernel config.
-+
-+TODO
-+----
-+
-+DSS locking
-+
-+Error checking
-+- Lots of checks are missing or implemented just as BUG()
-+
-+Rotate (external FB)
-+Rotate (VRFB)
-+Rotate (SMS)
-+
-+System DMA update for DSI
-+- Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how
-+  to skip the empty byte?)
-+
-+Power management
-+- Context saving
-+
-+Resolution change
-+- The x/y res of the framebuffer are not display resolutions, but the size
-+  of the overlay.
-+- The display resolution affects all planes on the display.
-+
-+OMAP1 support
-+- Not sure if needed
-+
-diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
-index 2465aea..cd7d9e2 100644
---- a/arch/arm/plat-omap/Kconfig
-+++ b/arch/arm/plat-omap/Kconfig
-@@ -245,6 +245,8 @@ config OMAP_SERIAL_WAKE
- 	  to data on the serial RX line. This allows you to wake the
- 	  system from serial console.
- 
-+source "arch/arm/plat-omap/dss/Kconfig"
-+
- endmenu
- 
- endif
-diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
-index 1259846..2740497 100644
---- a/arch/arm/plat-omap/Makefile
-+++ b/arch/arm/plat-omap/Makefile
-@@ -29,3 +29,5 @@ obj-$(CONFIG_OMAP_MMU_FWK) += mmu.o
- # OMAP mailbox framework
- obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
- 
-+# OMAP2/3 Display Subsystem
-+obj-y += dss/
-diff --git a/arch/arm/plat-omap/dss/Kconfig b/arch/arm/plat-omap/dss/Kconfig
-new file mode 100644
-index 0000000..6b342df
---- /dev/null
-+++ b/arch/arm/plat-omap/dss/Kconfig
-@@ -0,0 +1,69 @@
-+config OMAP2_DSS
-+        tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)"
-+        depends on ARCH_OMAP2 || ARCH_OMAP3
-+        help
-+          OMAP2/3 Display Subsystem support.
-+
-+if OMAP2_DSS
-+
-+config OMAP2_DSS_DEBUG_SUPPORT
-+        bool "Debug support"
-+	default y
-+	help
-+	  This enables debug messages. You need to enable printing
-+	  with 'debug' module parameter.
-+
-+config OMAP2_DSS_RFBI
-+	bool "RFBI support"
-+        default y
-+
-+config OMAP2_DSS_VENC
-+	bool "VENC support"
-+        default y
-+
-+if ARCH_OMAP3
-+
-+config OMAP2_DSS_SDI
-+	bool "SDI support"
-+        default y
-+
-+config OMAP2_DSS_DSI
-+	bool "DSI support"
-+        default y
-+
-+endif
-+
-+config OMAP2_DSS_USE_DSI_PLL
-+	bool "Use DSI PLL for PCLK (EXPERIMENTAL)"
-+	default n
-+	depends on OMAP2_DSS_DSI
-+	help
-+	  Use DSI PLL to generate pixel clock.
-+	  Currently only for DPI output.
-+
-+config OMAP2_DSS_FAKE_VSYNC
-+	bool "Fake VSYNC irq from manual update displays"
-+	default n
-+	help
-+	  If this is selected, DSI will fake a DISPC VSYNC interrupt
-+	  when DSI has sent a frame.
-+
-+config OMAP2_DSS_MIN_FCK_PER_PCK
-+	int "Minimum FCK/PCK ratio (for scaling)"
-+	range 0 32
-+	default 0
-+	help
-+	  This can be used to adjust the minimum FCK/PCK ratio.
-+
-+	  With this you can make sure that DISPC FCK is at least
-+	  n x PCK. Video plane scaling requires higher FCK than
-+	  normally.
-+
-+	  If this is set to 0, there's no extra constraint on the
-+	  DISPC FCK. However, the FCK will at minimum be
-+	  2xPCK (if active matrix) or 3xPCK (if passive matrix).
-+
-+	  Max FCK is 173MHz, so this doesn't work if your PCK
-+	  is very high.
-+
-+endif
-diff --git a/arch/arm/plat-omap/dss/Makefile b/arch/arm/plat-omap/dss/Makefile
-new file mode 100644
-index 0000000..e98c6c1
---- /dev/null
-+++ b/arch/arm/plat-omap/dss/Makefile
-@@ -0,0 +1,6 @@
-+obj-$(CONFIG_OMAP2_DSS) += omap-dss.o
-+omap-dss-y := dss.o display.o dispc.o dpi.o
-+omap-dss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
-+omap-dss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
-+omap-dss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
-+omap-dss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
-diff --git a/arch/arm/plat-omap/dss/dispc.c b/arch/arm/plat-omap/dss/dispc.c
-new file mode 100644
-index 0000000..20caa48
---- /dev/null
-+++ b/arch/arm/plat-omap/dss/dispc.c
-@@ -0,0 +1,2113 @@
-+/*
-+ * linux/arch/arm/plat-omap/dss/dispc.c
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "DISPC"
-+
-+#include <linux/kernel.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/vmalloc.h>
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/jiffies.h>
-+
-+#include <mach/sram.h>
-+#include <mach/board.h>
-+#include <mach/clock.h>
-+
-+#include <mach/display.h>
-+
-+#include "dss.h"
-+
-+/* DISPC */
-+#define DISPC_BASE			0x48050400
-+
-+#define DISPC_SZ_REGS			SZ_1K
-+
-+struct dispc_reg { u16 idx; };
-+
-+#define DISPC_REG(idx)			((const struct dispc_reg) { idx })
-+
-+/* DISPC common */
-+#define DISPC_REVISION			DISPC_REG(0x0000)
-+#define DISPC_SYSCONFIG			DISPC_REG(0x0010)
-+#define DISPC_SYSSTATUS			DISPC_REG(0x0014)
-+#define DISPC_IRQSTATUS			DISPC_REG(0x0018)
-+#define DISPC_IRQENABLE			DISPC_REG(0x001C)
-+#define DISPC_CONTROL			DISPC_REG(0x0040)
-+#define DISPC_CONFIG			DISPC_REG(0x0044)
-+#define DISPC_CAPABLE			DISPC_REG(0x0048)
-+#define DISPC_DEFAULT_COLOR0		DISPC_REG(0x004C)
-+#define DISPC_DEFAULT_COLOR1		DISPC_REG(0x0050)
-+#define DISPC_TRANS_COLOR0		DISPC_REG(0x0054)
-+#define DISPC_TRANS_COLOR1		DISPC_REG(0x0058)
-+#define DISPC_LINE_STATUS		DISPC_REG(0x005C)
-+#define DISPC_LINE_NUMBER		DISPC_REG(0x0060)
-+#define DISPC_TIMING_H			DISPC_REG(0x0064)
-+#define DISPC_TIMING_V			DISPC_REG(0x0068)
-+#define DISPC_POL_FREQ			DISPC_REG(0x006C)
-+#define DISPC_DIVISOR			DISPC_REG(0x0070)
-+#define DISPC_GLOBAL_ALPHA		DISPC_REG(0x0074)
-+#define DISPC_SIZE_DIG			DISPC_REG(0x0078)
-+#define DISPC_SIZE_LCD			DISPC_REG(0x007C)
-+
-+/* DISPC GFX plane */
-+#define DISPC_GFX_BA0			DISPC_REG(0x0080)
-+#define DISPC_GFX_BA1			DISPC_REG(0x0084)
-+#define DISPC_GFX_POSITION		DISPC_REG(0x0088)
-+#define DISPC_GFX_SIZE			DISPC_REG(0x008C)
-+#define DISPC_GFX_ATTRIBUTES		DISPC_REG(0x00A0)
-+#define DISPC_GFX_FIFO_THRESHOLD	DISPC_REG(0x00A4)
-+#define DISPC_GFX_FIFO_SIZE_STATUS	DISPC_REG(0x00A8)
-+#define DISPC_GFX_ROW_INC		DISPC_REG(0x00AC)
-+#define DISPC_GFX_PIXEL_INC		DISPC_REG(0x00B0)
-+#define DISPC_GFX_WINDOW_SKIP		DISPC_REG(0x00B4)
-+#define DISPC_GFX_TABLE_BA		DISPC_REG(0x00B8)
-+
-+#define DISPC_DATA_CYCLE1		DISPC_REG(0x01D4)
-+#define DISPC_DATA_CYCLE2		DISPC_REG(0x01D8)
-+#define DISPC_DATA_CYCLE3		DISPC_REG(0x01DC)
-+
-+#define DISPC_CPR_COEF_R		DISPC_REG(0x0220)
-+#define DISPC_CPR_COEF_G		DISPC_REG(0x0224)
-+#define DISPC_CPR_COEF_B		DISPC_REG(0x0228)
-+
-+#define DISPC_GFX_PRELOAD		DISPC_REG(0x022C)
-+
-+/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
-+#define DISPC_VID_REG(n, idx)		DISPC_REG(0x00BC + (n)*0x90 + idx)
-+
-+#define DISPC_VID_BA0(n)		DISPC_VID_REG(n, 0x0000)
-+#define DISPC_VID_BA1(n)		DISPC_VID_REG(n, 0x0004)
-+#define DISPC_VID_POSITION(n)		DISPC_VID_REG(n, 0x0008)
-+#define DISPC_VID_SIZE(n)		DISPC_VID_REG(n, 0x000C)
-+#define DISPC_VID_ATTRIBUTES(n)		DISPC_VID_REG(n, 0x0010)
-+#define DISPC_VID_FIFO_THRESHOLD(n)	DISPC_VID_REG(n, 0x0014)
-+#define DISPC_VID_FIFO_SIZE_STATUS(n)	DISPC_VID_REG(n, 0x0018)
-+#define DISPC_VID_ROW_INC(n)		DISPC_VID_REG(n, 0x001C)
-+#define DISPC_VID_PIXEL_INC(n)		DISPC_VID_REG(n, 0x0020)
-+#define DISPC_VID_FIR(n)		DISPC_VID_REG(n, 0x0024)
-+#define DISPC_VID_PICTURE_SIZE(n)	DISPC_VID_REG(n, 0x0028)
-+#define DISPC_VID_ACCU0(n)		DISPC_VID_REG(n, 0x002C)
-+#define DISPC_VID_ACCU1(n)		DISPC_VID_REG(n, 0x0030)
-+
-+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-+#define DISPC_VID_FIR_COEF_H(n, i)	DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
-+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-+#define DISPC_VID_FIR_COEF_HV(n, i)	DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
-+/* coef index i = {0, 1, 2, 3, 4} */
-+#define DISPC_VID_CONV_COEF(n, i)	DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
-+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-+#define DISPC_VID_FIR_COEF_V(n, i)	DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
-+
-+#define DISPC_VID_PRELOAD(n)		DISPC_REG(0x230 + (n)*0x04)
-+
-+
-+#define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
-+					 DISPC_IRQ_OCP_ERR | \
-+					 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
-+					 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
-+					 DISPC_IRQ_SYNC_LOST | \
-+					 DISPC_IRQ_SYNC_LOST_DIGIT)
-+
-+#define DISPC_MAX_NR_ISRS		8
-+
-+static struct {
-+	omap_dispc_isr_t	isr;
-+	void			*arg;
-+	u32			mask;
-+} registered_isr[DISPC_MAX_NR_ISRS];
-+
-+#define REG_GET(idx, start, end) \
-+	FLD_GET(dispc_read_reg(idx), start, end)
-+
-+#define REG_FLD_MOD(idx, val, start, end)				\
-+	dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
-+
-+static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
-+	DISPC_VID_ATTRIBUTES(0),
-+	DISPC_VID_ATTRIBUTES(1) };
-+
-+static struct {
-+	void __iomem    *base;
-+
-+	struct clk	*dpll4_m4_ck;
-+
-+	spinlock_t	irq_lock;
-+
-+	unsigned long	cache_req_pck;
-+	unsigned long	cache_prate;
-+	struct dispc_clock_info cache_cinfo;
-+
-+	u32		ctx[DISPC_SZ_REGS / sizeof(u32)];
-+} dispc;
-+
-+static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
-+{
-+	__raw_writel(val, dispc.base + idx.idx);
-+}
-+
-+static inline u32 dispc_read_reg(const struct dispc_reg idx)
-+{
-+	return __raw_readl(dispc.base + idx.idx);
-+}
-+
-+#define SR(reg) \
-+	dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
-+#define RR(reg) \
-+	dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
-+
-+void dispc_save_context(void)
-+{
-+	if (cpu_is_omap24xx())
-+		return;
-+
-+	SR(SYSCONFIG);
-+	SR(IRQENABLE);
-+	SR(CONTROL);
-+	SR(CONFIG);
-+	SR(DEFAULT_COLOR0);
-+	SR(DEFAULT_COLOR1);
-+	SR(TRANS_COLOR0);
-+	SR(TRANS_COLOR1);
-+	SR(LINE_NUMBER);
-+	SR(TIMING_H);
-+	SR(TIMING_V);
-+	SR(POL_FREQ);
-+	SR(DIVISOR);
-+	SR(GLOBAL_ALPHA);
-+	SR(SIZE_DIG);
-+	SR(SIZE_LCD);
-+
-+	SR(GFX_BA0);
-+	SR(GFX_BA1);
-+	SR(GFX_POSITION);
-+	SR(GFX_SIZE);
-+	SR(GFX_ATTRIBUTES);
-+	SR(GFX_FIFO_THRESHOLD);
-+	SR(GFX_ROW_INC);
-+	SR(GFX_PIXEL_INC);
-+	SR(GFX_WINDOW_SKIP);
-+	SR(GFX_TABLE_BA);
-+
-+	SR(DATA_CYCLE1);
-+	SR(DATA_CYCLE2);
-+	SR(DATA_CYCLE3);
-+
-+	SR(CPR_COEF_R);
-+	SR(CPR_COEF_G);
-+	SR(CPR_COEF_B);
-+
-+	SR(GFX_PRELOAD);
-+
-+	/* VID1 */
-+	SR(VID_BA0(0));
-+	SR(VID_BA1(0));
-+	SR(VID_POSITION(0));
-+	SR(VID_SIZE(0));
-+	SR(VID_ATTRIBUTES(0));
-+	SR(VID_FIFO_THRESHOLD(0));
-+	SR(VID_ROW_INC(0));
-+	SR(VID_PIXEL_INC(0));
-+	SR(VID_FIR(0));
-+	SR(VID_PICTURE_SIZE(0));
-+	SR(VID_ACCU0(0));
-+	SR(VID_ACCU1(0));
-+
-+	SR(VID_FIR_COEF_H(0, 0));
-+	SR(VID_FIR_COEF_H(0, 1));
-+	SR(VID_FIR_COEF_H(0, 2));
-+	SR(VID_FIR_COEF_H(0, 3));
-+	SR(VID_FIR_COEF_H(0, 4));
-+	SR(VID_FIR_COEF_H(0, 5));
-+	SR(VID_FIR_COEF_H(0, 6));
-+	SR(VID_FIR_COEF_H(0, 7));
-+
-+	SR(VID_FIR_COEF_HV(0, 0));
-+	SR(VID_FIR_COEF_HV(0, 1));
-+	SR(VID_FIR_COEF_HV(0, 2));
-+	SR(VID_FIR_COEF_HV(0, 3));
-+	SR(VID_FIR_COEF_HV(0, 4));
-+	SR(VID_FIR_COEF_HV(0, 5));
-+	SR(VID_FIR_COEF_HV(0, 6));
-+	SR(VID_FIR_COEF_HV(0, 7));
-+
-+	SR(VID_CONV_COEF(0, 0));
-+	SR(VID_CONV_COEF(0, 1));
-+	SR(VID_CONV_COEF(0, 2));
-+	SR(VID_CONV_COEF(0, 3));
-+	SR(VID_CONV_COEF(0, 4));
-+
-+	SR(VID_FIR_COEF_V(0, 0));
-+	SR(VID_FIR_COEF_V(0, 1));
-+	SR(VID_FIR_COEF_V(0, 2));
-+	SR(VID_FIR_COEF_V(0, 3));
-+	SR(VID_FIR_COEF_V(0, 4));
-+	SR(VID_FIR_COEF_V(0, 5));
-+	SR(VID_FIR_COEF_V(0, 6));
-+	SR(VID_FIR_COEF_V(0, 7));
-+
-+	SR(VID_PRELOAD(0));
-+
-+	/* VID2 */
-+	SR(VID_BA0(1));
-+	SR(VID_BA1(1));
-+	SR(VID_POSITION(1));
-+	SR(VID_SIZE(1));
-+	SR(VID_ATTRIBUTES(1));
-+	SR(VID_FIFO_THRESHOLD(1));
-+	SR(VID_ROW_INC(1));
-+	SR(VID_PIXEL_INC(1));
-+	SR(VID_FIR(1));
-+	SR(VID_PICTURE_SIZE(1));
-+	SR(VID_ACCU0(1));
-+	SR(VID_ACCU1(1));
-+
-+	SR(VID_FIR_COEF_H(1, 0));
-+	SR(VID_FIR_COEF_H(1, 1));
-+	SR(VID_FIR_COEF_H(1, 2));
-+	SR(VID_FIR_COEF_H(1, 3));
-+	SR(VID_FIR_COEF_H(1, 4));
-+	SR(VID_FIR_COEF_H(1, 5));
-+	SR(VID_FIR_COEF_H(1, 6));
-+	SR(VID_FIR_COEF_H(1, 7));
-+
-+	SR(VID_FIR_COEF_HV(1, 0));
-+	SR(VID_FIR_COEF_HV(1, 1));
-+	SR(VID_FIR_COEF_HV(1, 2));
-+	SR(VID_FIR_COEF_HV(1, 3));
-+	SR(VID_FIR_COEF_HV(1, 4));
-+	SR(VID_FIR_COEF_HV(1, 5));
-+	SR(VID_FIR_COEF_HV(1, 6));
-+	SR(VID_FIR_COEF_HV(1, 7));
-+
-+	SR(VID_CONV_COEF(1, 0));
-+	SR(VID_CONV_COEF(1, 1));
-+	SR(VID_CONV_COEF(1, 2));
-+	SR(VID_CONV_COEF(1, 3));
-+	SR(VID_CONV_COEF(1, 4));
-+
-+	SR(VID_FIR_COEF_V(1, 0));
-+	SR(VID_FIR_COEF_V(1, 1));
-+	SR(VID_FIR_COEF_V(1, 2));
-+	SR(VID_FIR_COEF_V(1, 3));
-+	SR(VID_FIR_COEF_V(1, 4));
-+	SR(VID_FIR_COEF_V(1, 5));
-+	SR(VID_FIR_COEF_V(1, 6));
-+	SR(VID_FIR_COEF_V(1, 7));
-+
-+	SR(VID_PRELOAD(1));
-+}
-+
-+void dispc_restore_context(void)
-+{
-+	RR(SYSCONFIG);
-+	RR(IRQENABLE);
-+	/*RR(CONTROL);*/
-+	RR(CONFIG);
-+	RR(DEFAULT_COLOR0);
-+	RR(DEFAULT_COLOR1);
-+	RR(TRANS_COLOR0);
-+	RR(TRANS_COLOR1);
-+	RR(LINE_NUMBER);
-+	RR(TIMING_H);
-+	RR(TIMING_V);
-+	RR(POL_FREQ);