diff options
| author | Denys Dmytriyenko <denis@denix.org> | 2009-03-17 14:32:59 -0400 |
|---|---|---|
| committer | Denys Dmytriyenko <denis@denix.org> | 2009-03-17 14:32:59 -0400 |
| commit | 709c4d66e0b107ca606941b988bad717c0b45d9b (patch) | |
| tree | 37ee08b1eb308f3b2b6426d5793545c38396b838 /recipes/linux/linux-omap/fix-dpll-m4.diff | |
| parent | fa6cd5a3b993f16c27de4ff82b42684516d433ba (diff) | |
rename packages/ to recipes/ per earlier agreement
See links below for more details:
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21326
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21816
Signed-off-by: Denys Dmytriyenko <denis@denix.org>
Acked-by: Mike Westerhof <mwester@dls.net>
Acked-by: Philip Balister <philip@balister.org>
Acked-by: Khem Raj <raj.khem@gmail.com>
Acked-by: Marcin Juszkiewicz <hrw@openembedded.org>
Acked-by: Koen Kooi <koen@openembedded.org>
Acked-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
Diffstat (limited to 'recipes/linux/linux-omap/fix-dpll-m4.diff')
| -rw-r--r-- | recipes/linux/linux-omap/fix-dpll-m4.diff | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/recipes/linux/linux-omap/fix-dpll-m4.diff b/recipes/linux/linux-omap/fix-dpll-m4.diff new file mode 100644 index 0000000000..1fa3bfe7fe --- /dev/null +++ b/recipes/linux/linux-omap/fix-dpll-m4.diff @@ -0,0 +1,37 @@ +From linux-omap-owner@vger.kernel.org Mon Dec 08 14:41:05 2008 + +This fixes commit e42218d45afbc3e654e289e021e6b80c657b16c2. The commit +was based on old kernel tree, and with bad luck applied ok but to wrong +position, modifying dpll4_m6_ck instead of dpll4_m4_ck. + +Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com> +--- + arch/arm/mach-omap2/clock34xx.h | 4 ++-- + 1 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h +index 1c2b49f..5357507 100644 +--- a/arch/arm/mach-omap2/clock34xx.h ++++ b/arch/arm/mach-omap2/clock34xx.h +@@ -825,6 +825,8 @@ static struct clk dpll4_m4_ck = { + PARENT_CONTROLS_CLOCK, + .clkdm = { .name = "dpll4_clkdm" }, + .recalc = &omap2_clksel_recalc, ++ .set_rate = &omap2_clksel_set_rate, ++ .round_rate = &omap2_clksel_round_rate, + }; + + /* The PWRDN bit is apparently only available on 3430ES2 and above */ +@@ -879,8 +881,6 @@ static struct clk dpll4_m6_ck = { + PARENT_CONTROLS_CLOCK, + .clkdm = { .name = "dpll4_clkdm" }, + .recalc = &omap2_clksel_recalc, +- .set_rate = &omap2_clksel_set_rate, +- .round_rate = &omap2_clksel_round_rate, + }; + + /* The PWRDN bit is apparently only available on 3430ES2 and above */ +-- +1.6.0.3 + + |