diff options
author | Denys Dmytriyenko <denis@denix.org> | 2009-03-17 14:32:59 -0400 |
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committer | Denys Dmytriyenko <denis@denix.org> | 2009-03-17 14:32:59 -0400 |
commit | 709c4d66e0b107ca606941b988bad717c0b45d9b (patch) | |
tree | 37ee08b1eb308f3b2b6426d5793545c38396b838 /recipes/linux/linux-omap-2.6.26/beagleboard | |
parent | fa6cd5a3b993f16c27de4ff82b42684516d433ba (diff) |
rename packages/ to recipes/ per earlier agreement
See links below for more details:
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21326
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21816
Signed-off-by: Denys Dmytriyenko <denis@denix.org>
Acked-by: Mike Westerhof <mwester@dls.net>
Acked-by: Philip Balister <philip@balister.org>
Acked-by: Khem Raj <raj.khem@gmail.com>
Acked-by: Marcin Juszkiewicz <hrw@openembedded.org>
Acked-by: Koen Kooi <koen@openembedded.org>
Acked-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
Diffstat (limited to 'recipes/linux/linux-omap-2.6.26/beagleboard')
48 files changed, 84811 insertions, 0 deletions
diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch new file mode 100644 index 0000000000..6e31ead2bd --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch @@ -0,0 +1,55 @@ +From a1dbb6dd28e9815a307b87b8d96dcf371d6cfd58 Mon Sep 17 00:00:00 2001 +From: Jarkko Nikula <jarkko.nikula@nokia.com> +Date: Mon, 19 May 2008 13:24:41 +0300 +Subject: [PATCH] ASoC: OMAP: Add basic support for OMAP34xx in McBSP DAI driver + +This adds support for OMAP34xx McBSP port 1 and 2. + +Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com> +--- + sound/soc/omap/omap-mcbsp.c | 20 +++++++++++++++++++- + 1 files changed, 19 insertions(+), 1 deletions(-) + +diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c +index 40d87e6..8e6ec9d 100644 +--- a/sound/soc/omap/omap-mcbsp.c ++++ b/sound/soc/omap/omap-mcbsp.c +@@ -99,6 +99,21 @@ static const unsigned long omap2420_mcbsp_port[][2] = { + static const int omap2420_dma_reqs[][2] = {}; + static const unsigned long omap2420_mcbsp_port[][2] = {}; + #endif ++#if defined(CONFIG_ARCH_OMAP34XX) ++static const int omap34xx_dma_reqs[][2] = { ++ { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX }, ++ { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX }, ++}; ++static const unsigned long omap34xx_mcbsp_port[][2] = { ++ { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR2, ++ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR2 }, ++ { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR2, ++ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR2 }, ++}; ++#else ++static const int omap34xx_dma_reqs[][2] = {}; ++static const unsigned long omap34xx_mcbsp_port[][2] = {}; ++#endif + + static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream) + { +@@ -169,9 +184,12 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, + } else if (cpu_is_omap2420()) { + dma = omap2420_dma_reqs[bus_id][substream->stream]; + port = omap2420_mcbsp_port[bus_id][substream->stream]; ++ } else if (cpu_is_omap343x()) { ++ dma = omap34xx_dma_reqs[bus_id][substream->stream]; ++ port = omap34xx_mcbsp_port[bus_id][substream->stream]; + } else { + /* +- * TODO: Add support for 2430 and 3430 ++ * TODO: Add support for 2430 + */ + return -ENODEV; + } +-- +1.5.5.1 + diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/0001-omap3-cpuidle.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/0001-omap3-cpuidle.patch new file mode 100644 index 0000000000..cdc9447b4c --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/0001-omap3-cpuidle.patch @@ -0,0 +1,450 @@ +From: "Rajendra Nayak" <rnayak@ti.com> +To: <linux-omap@vger.kernel.org> +Subject: [PATCH 01/02] OMAP3 CPUidle driver +Date: Tue, 10 Jun 2008 12:39:00 +0530 + +This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver +before it queries the governor for the next state. + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> + +--- + arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++ + arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++ + arch/arm/mach-omap2/pm34xx.c | 5 + drivers/cpuidle/cpuidle.c | 10 + + 5 files changed, 359 insertions(+), 2 deletions(-) + +Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530 +@@ -20,7 +20,7 @@ obj-y += pm.o + obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o + obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o + obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o +-obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o ++obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o + obj-$(CONFIG_PM_DEBUG) += pm-debug.o + endif + +Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530 +@@ -0,0 +1,293 @@ ++/* ++ * linux/arch/arm/mach-omap2/cpuidle34xx.c ++ * ++ * OMAP3 CPU IDLE Routines ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Rajendra Nayak <rnayak@ti.com> ++ * ++ * Copyright (C) 2007 Texas Instruments, Inc. ++ * Karthik Dasu <karthik-dp@ti.com> ++ * ++ * Copyright (C) 2006 Nokia Corporation ++ * Tony Lindgren <tony@atomide.com> ++ * ++ * Copyright (C) 2005 Texas Instruments, Inc. ++ * Richard Woodruff <r-woodruff2@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/cpuidle.h> ++#include <asm/arch/pm.h> ++#include <asm/arch/prcm.h> ++#include <asm/arch/powerdomain.h> ++#include <asm/arch/clockdomain.h> ++#include <asm/arch/irqs.h> ++#include "cpuidle34xx.h" ++ ++#ifdef CONFIG_CPU_IDLE ++ ++struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; ++struct omap3_processor_cx current_cx_state; ++ ++static int omap3_idle_bm_check(void) ++{ ++ /* Check for omap3_fclks_active() here once available */ ++ return 0; ++} ++ ++/* omap3_enter_idle - Programs OMAP3 to enter the specified state. ++ * returns the total time during which the system was idle. ++ */ ++static int omap3_enter_idle(struct cpuidle_device *dev, ++ struct cpuidle_state *state) ++{ ++ struct omap3_processor_cx *cx = cpuidle_get_statedata(state); ++ struct timespec ts_preidle, ts_postidle, ts_idle; ++ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd; ++ int neon_pwrst; ++ ++ current_cx_state = *cx; ++ ++ if (cx->type == OMAP3_STATE_C0) { ++ /* Do nothing for C0, not even a wfi */ ++ return 0; ++ } ++ ++ /* Used to keep track of the total time in idle */ ++ getnstimeofday(&ts_preidle); ++ ++ mpu_pd = pwrdm_lookup("mpu_pwrdm"); ++ core_pd = pwrdm_lookup("core_pwrdm"); ++ per_pd = pwrdm_lookup("per_pwrdm"); ++ neon_pd = pwrdm_lookup("neon_pwrdm"); ++ ++ /* Reset previous power state registers */ ++ pwrdm_clear_all_prev_pwrst(mpu_pd); ++ pwrdm_clear_all_prev_pwrst(neon_pd); ++ pwrdm_clear_all_prev_pwrst(core_pd); ++ pwrdm_clear_all_prev_pwrst(per_pd); ++ ++ if (omap_irq_pending()) ++ return 0; ++ ++ neon_pwrst = pwrdm_read_pwrst(neon_pd); ++ ++ /* Program MPU/NEON to target state */ ++ if (cx->mpu_state < PWRDM_POWER_ON) { ++ if (neon_pwrst == PWRDM_POWER_ON) { ++ if (cx->mpu_state == PWRDM_POWER_RET) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET); ++ else if (cx->mpu_state == PWRDM_POWER_OFF) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF); ++ } ++ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state); ++ } ++ ++ /* Program CORE to target state */ ++ if (cx->core_state < PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(core_pd, cx->core_state); ++ ++ /* Execute ARM wfi */ ++ omap_sram_idle(); ++ ++ /* Program MPU/NEON to ON */ ++ if (cx->mpu_state < PWRDM_POWER_ON) { ++ if (neon_pwrst == PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON); ++ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON); ++ } ++ ++ if (cx->core_state < PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON); ++ ++ getnstimeofday(&ts_postidle); ++ ts_idle = timespec_sub(ts_postidle, ts_preidle); ++ return timespec_to_ns(&ts_idle); ++} ++ ++/* ++ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM ++ * ++ * This function checks for all the pre-requisites needed for OMAP3 to enter ++ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired ++ * C state. ++ */ ++static int omap3_enter_idle_bm(struct cpuidle_device *dev, ++ struct cpuidle_state *state) ++{ ++ struct cpuidle_state *new_state = NULL; ++ int i, j; ++ ++ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { ++ ++ /* Find current state in list */ ++ for (i = 0; i < OMAP3_MAX_STATES; i++) ++ if (state == &dev->states[i]) ++ break; ++ BUG_ON(i == OMAP3_MAX_STATES); ++ ++ /* Back up to non 'CHECK_BM' state */ ++ for (j = i - 1; j > 0; j--) { ++ struct cpuidle_state *s = &dev->states[j]; ++ ++ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) { ++ new_state = s; ++ break; ++ } ++ } ++ ++ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n", ++ __FUNCTION__, new_state->name, state->name); ++ } ++ ++ return omap3_enter_idle(dev, new_state ? : state); ++} ++ ++DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); ++ ++/* omap3_init_power_states - Initialises the OMAP3 specific C states. ++ * Below is the desciption of each C state. ++ * ++ C0 . System executing code ++ C1 . MPU WFI + Core active ++ C2 . MPU CSWR + Core active ++ C3 . MPU OFF + Core active ++ C4 . MPU CSWR + Core CSWR ++ C5 . MPU OFF + Core CSWR ++ C6 . MPU OFF + Core OFF ++ */ ++void omap_init_power_states(void) ++{ ++ /* C0 . System executing code */ ++ omap3_power_states[0].valid = 1; ++ omap3_power_states[0].type = OMAP3_STATE_C0; ++ omap3_power_states[0].sleep_latency = 0; ++ omap3_power_states[0].wakeup_latency = 0; ++ omap3_power_states[0].threshold = 0; ++ omap3_power_states[0].mpu_state = PWRDM_POWER_ON; ++ omap3_power_states[0].core_state = PWRDM_POWER_ON; ++ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_SHALLOW; ++ ++ /* C1 . MPU WFI + Core active */ ++ omap3_power_states[1].valid = 1; ++ omap3_power_states[1].type = OMAP3_STATE_C1; ++ omap3_power_states[1].sleep_latency = 10; ++ omap3_power_states[1].wakeup_latency = 10; ++ omap3_power_states[1].threshold = 30; ++ omap3_power_states[1].mpu_state = PWRDM_POWER_ON; ++ omap3_power_states[1].core_state = PWRDM_POWER_ON; ++ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_SHALLOW; ++ ++ /* C2 . MPU CSWR + Core active */ ++ omap3_power_states[2].valid = 1; ++ omap3_power_states[2].type = OMAP3_STATE_C2; ++ omap3_power_states[2].sleep_latency = 50; ++ omap3_power_states[2].wakeup_latency = 50; ++ omap3_power_states[2].threshold = 300; ++ omap3_power_states[2].mpu_state = PWRDM_POWER_RET; ++ omap3_power_states[2].core_state = PWRDM_POWER_ON; ++ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED; ++ ++ /* C3 . MPU OFF + Core active */ ++ omap3_power_states[3].valid = 0; ++ omap3_power_states[3].type = OMAP3_STATE_C3; ++ omap3_power_states[3].sleep_latency = 1500; ++ omap3_power_states[3].wakeup_latency = 1800; ++ omap3_power_states[3].threshold = 4000; ++ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[3].core_state = PWRDM_POWER_RET; ++ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED; ++ ++ /* C4 . MPU CSWR + Core CSWR*/ ++ omap3_power_states[4].valid = 1; ++ omap3_power_states[4].type = OMAP3_STATE_C4; ++ omap3_power_states[4].sleep_latency = 2500; ++ omap3_power_states[4].wakeup_latency = 7500; ++ omap3_power_states[4].threshold = 12000; ++ omap3_power_states[4].mpu_state = PWRDM_POWER_RET; ++ omap3_power_states[4].core_state = PWRDM_POWER_RET; ++ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; ++ ++ /* C5 . MPU OFF + Core CSWR */ ++ omap3_power_states[5].valid = 0; ++ omap3_power_states[5].type = OMAP3_STATE_C5; ++ omap3_power_states[5].sleep_latency = 3000; ++ omap3_power_states[5].wakeup_latency = 8500; ++ omap3_power_states[5].threshold = 15000; ++ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[5].core_state = PWRDM_POWER_RET; ++ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; ++ ++ /* C6 . MPU OFF + Core OFF */ ++ omap3_power_states[6].valid = 0; ++ omap3_power_states[6].type = OMAP3_STATE_C6; ++ omap3_power_states[6].sleep_latency = 10000; ++ omap3_power_states[6].wakeup_latency = 30000; ++ omap3_power_states[6].threshold = 300000; ++ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[6].core_state = PWRDM_POWER_OFF; ++ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM; ++} ++ ++struct cpuidle_driver omap3_idle_driver = { ++ .name = "omap3_idle", ++ .owner = THIS_MODULE, ++}; ++/* ++ * omap3_idle_init - Init routine for OMAP3 idle. ++ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w ++ * with the valid set of states. ++ */ ++int omap3_idle_init(void) ++{ ++ int i, count = 0; ++ struct omap3_processor_cx *cx; ++ struct cpuidle_state *state; ++ struct cpuidle_device *dev; ++ ++ omap_init_power_states(); ++ cpuidle_register_driver(&omap3_idle_driver); ++ ++ dev = &per_cpu(omap3_idle_dev, smp_processor_id()); ++ ++ for (i = 0; i < OMAP3_MAX_STATES; i++) { ++ cx = &omap3_power_states[i]; ++ state = &dev->states[count]; ++ ++ if (!cx->valid) ++ continue; ++ cpuidle_set_statedata(state, cx); ++ state->exit_latency = cx->sleep_latency + cx->wakeup_latency; ++ state->target_residency = cx->threshold; ++ state->flags = cx->flags; ++ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? ++ omap3_enter_idle_bm : omap3_enter_idle; ++ sprintf(state->name, "C%d", count+1); ++ count++; ++ } ++ ++ if (!count) ++ return -EINVAL; ++ dev->state_count = count; ++ ++ if (cpuidle_register_device(dev)) { ++ printk(KERN_ERR "%s: CPUidle register device failed\n", ++ __FUNCTION__); ++ return -EIO; ++ } ++ ++ return 0; ++} ++__initcall(omap3_idle_init); ++#endif /* CONFIG_CPU_IDLE */ +Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530 +@@ -0,0 +1,51 @@ ++/* ++ * linux/arch/arm/mach-omap2/cpuidle34xx.h ++ * ++ * OMAP3 cpuidle structure definitions ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Written by Rajendra Nayak <rnayak@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ * ++ * History: ++ * ++ */ ++ ++#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX ++#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX ++ ++#define OMAP3_MAX_STATES 7 ++#define OMAP3_STATE_C0 0 /* C0 - System executing code */ ++#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */ ++#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */ ++#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */ ++#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */ ++#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */ ++#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */ ++ ++extern void omap_sram_idle(void); ++extern int omap3_irq_pending(void); ++ ++struct omap3_processor_cx { ++ u8 valid; ++ u8 type; ++ u32 sleep_latency; ++ u32 wakeup_latency; ++ u32 mpu_state; ++ u32 core_state; ++ u32 threshold; ++ u32 flags; ++}; ++ ++void omap_init_power_states(void); ++int omap3_idle_init(void); ++ ++#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */ ++ +Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530 +@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle + return IRQ_HANDLED; + } + +-static void omap_sram_idle(void) ++void omap_sram_idle(void) + { + /* Variable to tell what needs to be saved and restored + * in omap_sram_idle*/ +@@ -156,6 +156,7 @@ static void omap_sram_idle(void) + + mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); + switch (mpu_next_state) { ++ case PWRDM_POWER_ON: + case PWRDM_POWER_RET: + /* No need to save context */ + save_state = 0; +@@ -386,7 +387,9 @@ int __init omap3_pm_init(void) + + prcm_setup_regs(); + ++#ifndef CONFIG_CPU_IDLE + pm_idle = omap3_pm_idle; ++#endif + + err1: + return ret; +Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c +=================================================================== +--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530 ++++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530 +@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void) + return; + } + ++#ifdef CONFIG_ARCH_OMAP3 ++ local_irq_disable(); ++ local_fiq_disable(); ++#endif ++ + /* ask the governor for the next state */ + next_state = cpuidle_curr_governor->select(dev); + if (need_resched()) +@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void) + target_state->time += (unsigned long long)dev->last_residency; + target_state->usage++; + ++#ifdef CONFIG_ARCH_OMAP3 ++ local_irq_enable(); ++ local_fiq_enable(); ++#endif ++ + /* give the governor an opportunity to reflect on the outcome */ + if (cpuidle_curr_governor->reflect) + cpuidle_curr_governor->reflect(dev); + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch new file mode 100644 index 0000000000..17329be29b --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch @@ -0,0 +1,69 @@ +From 7a444ee080c5f1a62ac5042f1e7926622b3e1ce7 Mon Sep 17 00:00:00 2001 +From: Koen Kooi <koen@openembedded.org> +Date: Fri, 30 May 2008 13:43:36 +0200 +Subject: [PATCH] ARM: OMAP: omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver + +omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver + * on revision A5 and earlier board the two leds can't be controlled seperately, should be fixed in rev. B and C boards. + +Signed-off-by: Koen Kooi <koen@openembedded.org> +--- + arch/arm/mach-omap2/board-omap3beagle.c | 28 ++++++++++++++++++++++++++++ + 1 files changed, 28 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c +index c992cc7..83891fc 100644 +--- a/arch/arm/mach-omap2/board-omap3beagle.c ++++ b/arch/arm/mach-omap2/board-omap3beagle.c +@@ -19,6 +19,7 @@ + #include <linux/err.h> + #include <linux/clk.h> + #include <linux/io.h> ++#include <linux/leds.h> + + #include <asm/hardware.h> + #include <asm/mach-types.h> +@@ -72,6 +73,32 @@ static struct omap_lcd_config omap3_beagle_lcd_config __initdata = { + .ctrl_name = "internal", + }; + ++struct gpio_led gpio_leds[] = { ++ { ++ .name = "beagleboard::led0", ++ .default_trigger = "none", ++ .gpio = 149, ++ }, ++ { ++ .name = "beagleboard::led1", ++ .default_trigger = "none", ++ .gpio = 150, ++ }, ++}; ++ ++static struct gpio_led_platform_data gpio_led_info = { ++ .leds = gpio_leds, ++ .num_leds = ARRAY_SIZE(gpio_leds), ++}; ++ ++static struct platform_device leds_gpio = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = &gpio_led_info, ++ }, ++}; ++ + static struct omap_board_config_kernel omap3_beagle_config[] __initdata = { + { OMAP_TAG_UART, &omap3_beagle_uart_config }, + { OMAP_TAG_MMC, &omap3beagle_mmc_config }, +@@ -83,6 +110,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = { + #ifdef CONFIG_RTC_DRV_TWL4030 + &omap3_beagle_twl4030rtc_device, + #endif ++ &leds_gpio, + }; + + static void __init omap3_beagle_init(void) +-- +1.5.4.3 + diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/0002-omap3-cpuidle.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/0002-omap3-cpuidle.patch new file mode 100644 index 0000000000..d35fd47567 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/0002-omap3-cpuidle.patch @@ -0,0 +1,88 @@ +From: "Rajendra Nayak" <rnayak@ti.com> +To: <linux-omap@vger.kernel.org> +Subject: [PATCH 02/02] Kconfig changes +Date: Tue, 10 Jun 2008 12:39:02 +0530 + +Updates the CPUidle Kconfig + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> + +--- + arch/arm/Kconfig | 10 ++++++++++ + drivers/cpuidle/Kconfig | 28 ++++++++++++++++++++++------ + 2 files changed, 32 insertions(+), 6 deletions(-) + +Index: linux-omap-2.6/arch/arm/Kconfig +=================================================================== +--- linux-omap-2.6.orig/arch/arm/Kconfig 2008-06-10 11:43:10.790502713 +0530 ++++ linux-omap-2.6/arch/arm/Kconfig 2008-06-10 11:43:38.701604549 +0530 +@@ -954,6 +954,16 @@ config ATAGS_PROC + + endmenu + ++if (ARCH_OMAP) ++ ++menu "CPUIdle" ++ ++source "drivers/cpuidle/Kconfig" ++ ++endmenu ++ ++endif ++ + if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) + + menu "CPU Frequency scaling" +Index: linux-omap-2.6/drivers/cpuidle/Kconfig +=================================================================== +--- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-06-10 11:43:10.790502713 +0530 ++++ linux-omap-2.6/drivers/cpuidle/Kconfig 2008-06-10 12:06:36.139332151 +0530 +@@ -1,20 +1,36 @@ ++menu "CPU idle PM support" + + config CPU_IDLE + bool "CPU idle PM support" +- default ACPI ++ default n + help + CPU idle is a generic framework for supporting software-controlled + idle processor power management. It includes modular cross-platform + governors that can be swapped during runtime. + +- If you're using an ACPI-enabled platform, you should say Y here. ++ If you're using a mobile platform that supports CPU idle PM (e.g. ++ an ACPI-capable notebook), you should say Y here. ++ ++if CPU_IDLE ++ ++comment "Governors" + + config CPU_IDLE_GOV_LADDER +- bool ++ bool "ladder" + depends on CPU_IDLE +- default y ++ default n + + config CPU_IDLE_GOV_MENU +- bool ++ bool "menu" + depends on CPU_IDLE && NO_HZ +- default y ++ default n ++ help ++ This cpuidle governor evaluates all available states and chooses the ++ deepest state that meets all of the following constraints: BM activity, ++ expected time until next timer interrupt, and last break event time ++ delta. It is designed to minimize power consumption. Currently ++ dynticks is required. ++ ++endif # CPU_IDLE ++ ++endmenu + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/01-beagle-cpufreq.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/01-beagle-cpufreq.diff new file mode 100644 index 0000000000..5343f3276b --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/01-beagle-cpufreq.diff @@ -0,0 +1,178 @@ +--- /tmp/board-omap3beagle.h 2008-08-11 15:40:17.000000000 +0200 ++++ git/include/asm-arm/arch-omap/board-omap3beagle.h 2008-08-11 15:41:32.433198000 +0200 +@@ -29,5 +29,41 @@ + #ifndef __ASM_ARCH_OMAP3_BEAGLE_H + #define __ASM_ARCH_OMAP3_BEAGLE_H + ++/* MPU speeds */ ++#define S600M 600000000 ++#define S550M 550000000 ++#define S500M 500000000 ++#define S250M 250000000 ++#define S125M 125000000 ++ ++/* IVA speeds */ ++#define S430M 430000000 ++#define S400M 400000000 ++#define S360M 360000000 ++#define S180M 180000000 ++#define S90M 90000000 ++ ++/* L3 speeds */ ++#define S83M 83000000 ++#define S166M 166000000 ++ ++/* VDD1 OPPS */ ++#define VDD1_OPP1 0x1 ++#define VDD1_OPP2 0x2 ++#define VDD1_OPP3 0x3 ++#define VDD1_OPP4 0x4 ++#define VDD1_OPP5 0x5 ++ ++/* VDD2 OPPS */ ++#define VDD2_OPP1 0x1 ++#define VDD2_OPP2 0x2 ++#define VDD2_OPP3 0x3 ++ ++#define MIN_VDD1_OPP VDD1_OPP1 ++#define MAX_VDD1_OPP VDD1_OPP5 ++#define MIN_VDD2_OPP VDD2_OPP1 ++#define MAX_VDD2_OPP VDD2_OPP3 ++ ++ + #endif /* __ASM_ARCH_OMAP3_BEAGLE_H */ + +--- /tmp/resource34xx.c 2008-08-11 16:11:28.000000000 +0200 ++++ git/arch/arm/mach-omap2/resource34xx.c 2008-08-11 16:20:18.803198000 +0200 +@@ -173,7 +173,7 @@ + + int set_opp(struct shared_resource *resp, u32 target_level) + { +-#ifdef CONFIG_MACH_OMAP_3430SDP ++#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP3_BEAGLE) + unsigned long mpu_freq, l3_freq, tput; + int ind; + struct bus_throughput_db *tput_db; +@@ -248,7 +248,7 @@ + */ + void init_freq(struct shared_resource *resp) + { +-#ifdef CONFIG_MACH_OMAP_3430SDP ++#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP3_BEAGLE) + char *linked_res_name; + resp->no_of_users = 0; + +@@ -269,7 +269,7 @@ + + int set_freq(struct shared_resource *resp, u32 target_level) + { +-#ifdef CONFIG_MACH_OMAP_3430SDP ++#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP3_BEAGLE) + unsigned int vdd1_opp; + + if (strcmp(resp->name, "mpu_freq") == 0) +--- /tmp/clock34xx.c 2008-08-11 15:57:48.000000000 +0200 ++++ git/arch/arm/mach-omap2/clock34xx.c 2008-08-11 16:22:43.093198000 +0200 +@@ -773,7 +773,7 @@ + dpll2_clk = clk_get(NULL, "dpll2_ck"); + dpll3_clk = clk_get(NULL, "dpll3_ck"); + +-#ifdef CONFIG_MACH_OMAP_3430SDP ++#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP3_BEAGLE) + mpu_speed = dpll1_clk->rate; + prcm_vdd = vdd1_rate_table + MAX_VDD1_OPP; + for (; prcm_vdd->speed; prcm_vdd--) { +@@ -836,7 +836,7 @@ + return (prcm_config+1)->opp; + } + +-#ifdef CONFIG_MACH_OMAP_3430SDP ++#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP3_BEAGLE) + static void omap3_table_recalc(struct clk *clk) + { + if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set)) +--- /tmp/board-omap3beagle.c 2008-08-11 15:54:04.000000000 +0200 ++++ git/arch/arm/mach-omap2/board-omap3beagle.c 2008-08-11 16:25:11.333198000 +0200 +@@ -39,9 +39,62 @@ + #include <asm/arch/gpmc.h> + #include <asm/arch/nand.h> + ++#include <asm/arch/clock.h> ++ + #define GPMC_CS0_BASE 0x60 + #define GPMC_CS_SIZE 0x30 + ++struct vdd_prcm_config vdd1_rate_table[] = { ++ {0, 0, 0}, ++ /*OPP1*/ ++ {S125M, VDD1_OPP1, 0}, ++ /*OPP2*/ ++ {S250M, VDD1_OPP2, 0}, ++ /*OPP3*/ ++ {S500M, VDD1_OPP3, 0}, ++ /*OPP4*/ ++ {S550M, VDD1_OPP4, 0}, ++ /*OPP5*/ ++ {S600M, VDD1_OPP5, 0}, ++}; ++ ++struct vdd_prcm_config vdd2_rate_table[] = { ++ {0, 0, 0}, ++ /*OPP1*/ ++ {0, VDD2_OPP1, 0}, ++ /*OPP2*/ ++ {S83M, VDD2_OPP2, 0}, ++ /*OPP3*/ ++ {S166M, VDD2_OPP3, 0}, ++}; ++ ++struct vdd_prcm_config iva2_rate_table[] = { ++ {0, 0, 0}, ++ /*OPP1*/ ++ {S90M, VDD1_OPP1, 0}, ++ /*OPP2*/ ++ {S180M, VDD1_OPP2, 0}, ++ /*OPP3*/ ++ {S360M, VDD1_OPP3, 0}, ++ /*OPP4*/ ++ {S400M, VDD1_OPP4, 0}, ++ /*OPP5*/ ++ {S430M, VDD1_OPP5, 0}, ++}; ++ ++u8 vdd1_volts[MAX_VDD1_OPP] = { ++ /* Vsel corresponding to 0.9V (OPP1), 1.00V (OPP2), ++ * 1.20V (OPP3), 1.27V (OPP4), 1.35 (OPP5) ++ */ ++ 0x18, 0x20, 0x30, 0x36, 0x3C ++}; ++ ++u8 vdd2_volts[MAX_VDD2_OPP] = { ++ /* Vsel corresponding to 0.9V (OPP1), 1.00V (OPP2), 1.15 (OPP3) */ ++ 0x18, 0x20, 0x2C ++}; ++ ++ + static struct mtd_partition omap3beagle_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { +--- /tmp/cpu-omap.c 2008-08-11 15:43:01.000000000 +0200 ++++ git/arch/arm/plat-omap/cpu-omap.c 2008-08-11 16:31:24.943198000 +0200 +@@ -47,7 +47,7 @@ + + static struct clk *mpu_clk; + +-#ifdef CONFIG_MACH_OMAP_3430SDP ++#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP3_BEAGLE) + extern struct vdd_prcm_config vdd1_rate_table[]; + extern struct vdd_prcm_config vdd2_rate_table[]; + extern struct vdd_prcm_config iva2_rate_table[]; +@@ -127,7 +127,7 @@ + ret = clk_set_rate(mpu_clk, freqs.new * 1000); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + #elif defined(CONFIG_ARCH_OMAP3) && !defined(CONFIG_OMAP_PM_NONE)\ +- && defined(CONFIG_MACH_OMAP_3430SDP) ++ && (defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP3_BEAGLE)) + { + int ind; + for (ind = 1; ind <= MAX_VDD1_OPP; ind++) { diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/01-fix-timing-print.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/01-fix-timing-print.diff new file mode 100644 index 0000000000..89fbe3a836 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/01-fix-timing-print.diff @@ -0,0 +1,23 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sat, 5 Jul 2008 20:31:56 +0000 (+0100) +Subject: omapfb: fix video timings message +X-Git-Tag: beagle-5~3 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=2929b75035ebe8702ba2ff2c81b654c487701f64 + +omapfb: fix video timings message +--- + +diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c +index 418ed9f..1166a01 100644 +--- a/drivers/video/omap/omapfb_main.c ++++ b/drivers/video/omap/omapfb_main.c +@@ -1789,7 +1789,8 @@ static int omapfb_do_probe(struct platform_device *pdev, + vram, fbdev->mem_desc.region_cnt); + pr_info("omapfb: Pixclock %lu kHz hfreq %lu.%lu kHz " + "vfreq %lu.%lu Hz\n", +- phz / 1000, hhz / 10000, hhz % 10, vhz / 10, vhz % 10); ++ phz / 1000, hhz / 10000, hhz % 10000, ++ vhz / 10, vhz % 10); + + return 0; + diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/01-make_tick_gptimer_configurable b/recipes/linux/linux-omap-2.6.26/beagleboard/01-make_tick_gptimer_configurable new file mode 100644 index 0000000000..bcf0fa79f8 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/01-make_tick_gptimer_configurable @@ -0,0 +1,58 @@ +OMAP2/3 GPTIMER: allow system tick GPTIMER to be configurable at build + +From: Paul Walmsley <paul@pwsan.com> + +Add Kbuild code to allow the builder to select which GPTIMER block to use +for the Linux clockevents timer. Practical choices at this point are +GPTIMER1 or GPTIMER12. Both of these timers are in the WKUP powerdomain, +and so are unaffected by chip power management. GPTIMER1 can use sys_clk +as a source, for applications where a high-resolution timer is more important +than power management. GPTIMER12 has the special property that it has +the secure 32kHz oscillator as its source clock, which may be less prone +to glitches than the off-chip 32kHz oscillator. + +At this point, it appears that most boards are fine with GPTIMER1, +but Beagle should use GPTIMER12. +--- + + arch/arm/mach-omap2/Kconfig | 16 ++++++++++++++++ + arch/arm/mach-omap2/timer-gp.c | 2 +- + 2 files changed, 17 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig +index bb6d695..0002cb6 100644 +--- a/arch/arm/mach-omap2/Kconfig ++++ b/arch/arm/mach-omap2/Kconfig +@@ -122,3 +122,19 @@ config MACH_OMAP3EVM + config MACH_OMAP3_BEAGLE + bool "OMAP3 BEAGLE board" + depends on ARCH_OMAP3 && ARCH_OMAP34XX ++ ++config OMAP_TICK_GPTIMER ++ int "GPTIMER used for system tick timer" ++ depends on ARCH_OMAP2 || ARCH_OMAP3 ++ range 1 12 ++ default 1 ++ help ++ Linux uses one of the twelve on-board OMAP GPTIMER blocks to generate ++ system tick interrupts. The twelve GPTIMERs have slightly ++ different powerdomain, source clock, and security properties ++ (mostly documented in the OMAP3 TRMs) that can affect the selection ++ of which GPTIMER to use. The historical default is GPTIMER1. ++ If CONFIG_OMAP_32K_TIMER is selected, Beagle may require GPTIMER12 ++ due to hardware sensitivity to glitches on the OMAP 32kHz clock ++ input. ++ +diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c +index 557603f..ec80af5 100644 +--- a/arch/arm/mach-omap2/timer-gp.c ++++ b/arch/arm/mach-omap2/timer-gp.c +@@ -99,7 +99,7 @@ static void __init omap2_gp_clockevent_init(void) + { + u32 tick_rate; + +- gptimer = omap_dm_timer_request_specific(1); ++ gptimer = omap_dm_timer_request_specific(CONFIG_OMAP_TICK_GPTIMER); + BUG_ON(gptimer == NULL); + + #if defined(CONFIG_OMAP_32K_TIMER) diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/01-omap3-cpufreq.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/01-omap3-cpufreq.eml new file mode 100644 index 0000000000..b45a81edce --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/01-omap3-cpufreq.eml @@ -0,0 +1,319 @@ +CPUFreq driver for OMAP3 + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> +--- + arch/arm/configs/omap_3430sdp_defconfig | 19 +++++++ + arch/arm/mach-omap2/clock34xx.c | 42 ++++++++++++++++- + arch/arm/mach-omap2/resource34xx.c | 6 -- + arch/arm/plat-omap/cpu-omap.c | 78 ++++++++++++++++++++++++++++++-- + drivers/cpufreq/cpufreq.c | 2 + 5 files changed, 136 insertions(+), 11 deletions(-) + +Index: linux-omap-2.6/arch/arm/mach-omap2/clock34xx.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/clock34xx.c 2008-08-11 +17:21:57.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/clock34xx.c 2008-08-11 +17:36:53.000000000 +0530 +@@ -31,6 +31,7 @@ + #include <asm/arch/sram.h> + #include <asm/div64.h> + #include <asm/bitops.h> ++#include <linux/cpufreq.h> + + #include <asm/arch/sdrc.h> + #include "clock.h" +@@ -637,6 +638,35 @@ static void omap3_clkoutx2_recalc(struct + */ + #if defined(CONFIG_ARCH_OMAP3) + ++#ifdef CONFIG_CPU_FREQ ++static struct cpufreq_frequency_table freq_table[MAX_VDD1_OPP+1]; ++ ++void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) ++{ ++ struct vdd_prcm_config *prcm; ++ int i = 0; ++ ++ prcm = vdd1_rate_table + MAX_VDD1_OPP; ++ for (; prcm->speed; prcm--) { ++ freq_table[i].index = i; ++ freq_table[i].frequency = prcm->speed / 1000; ++ i++; ++ } ++ ++ if (i == 0) { ++ printk(KERN_WARNING "%s: failed to initialize frequency \ ++ table\n", ++ __func__); ++ return; ++ } ++ ++ freq_table[i].index = i; ++ freq_table[i].frequency = CPUFREQ_TABLE_END; ++ ++ *table = &freq_table[0]; ++} ++#endif ++ + static struct clk_functions omap2_clk_functions = { + .clk_enable = omap2_clk_enable, + .clk_disable = omap2_clk_disable, +@@ -644,6 +674,9 @@ static struct clk_functions omap2_clk_fu + .clk_set_rate = omap2_clk_set_rate, + .clk_set_parent = omap2_clk_set_parent, + .clk_disable_unused = omap2_clk_disable_unused, ++#ifdef CONFIG_CPU_FREQ ++ .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, ++#endif + }; + + /* +@@ -793,12 +826,11 @@ inline unsigned int get_opp(struct vdd_p + + if (prcm_config->speed <= freq) + return prcm_config->opp; /* Return the Highest OPP */ +- for (; prcm_config->speed; prcm_config--) { ++ for (; prcm_config->speed; prcm_config--) + if (prcm_config->speed < freq) + return (prcm_config+1)->opp; + else if (prcm_config->speed == freq) + return prcm_config->opp; +- } + /* Return the least OPP */ + return (prcm_config+1)->opp; + } +@@ -878,6 +910,10 @@ static int omap3_select_table_rate(struc + clk_set_rate(dpll1_clk, prcm_vdd->speed); + clk_set_rate(dpll2_clk, iva2_rate_table[index].speed); + curr_vdd1_prcm_set = prcm_vdd; ++ omap2_clksel_recalc(&mpu_ck); ++ propagate_rate(&mpu_ck); ++ omap2_clksel_recalc(&iva2_ck); ++ propagate_rate(&iva2_ck); + #ifndef CONFIG_CPU_FREQ + /*Update loops_per_jiffy if processor speed is being changed*/ + loops_per_jiffy = compute_lpj(loops_per_jiffy, +@@ -886,6 +922,8 @@ static int omap3_select_table_rate(struc + } else { + clk_set_rate(dpll3_clk, prcm_vdd->speed); + curr_vdd2_prcm_set = prcm_vdd; ++ omap2_clksel_recalc(&core_ck); ++ propagate_rate(&core_ck); + } + return 0; + } +Index: linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/resource34xx.c 2008-08-11 +17:36:52.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c 2008-08-11 +17:36:53.000000000 +0530 +@@ -278,11 +278,7 @@ int set_freq(struct shared_resource *res + else if (strcmp(resp->name, "dsp_freq") == 0) + vdd1_opp = get_opp(iva2_rate_table + MAX_VDD1_OPP, + target_level); +- +- if (vdd1_opp == MIN_VDD1_OPP) +- resource_release("vdd1_opp", &dummy_srf_dev); +- else +- resource_request("vdd1_opp", &dummy_srf_dev, vdd1_opp); ++ resource_request("vdd1_opp", &dummy_srf_dev, vdd1_opp); + + resp->curr_level = target_level; + #endif +Index: linux-omap-2.6/arch/arm/plat-omap/cpu-omap.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/plat-omap/cpu-omap.c 2008-08-11 +17:21:57.000000000 +0530 ++++ linux-omap-2.6/arch/arm/plat-omap/cpu-omap.c 2008-08-11 17:36:53.000000000 ++0530 +@@ -8,6 +8,10 @@ + * + * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King + * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Updated to support OMAP3 ++ * Rajendra Nayak <rnayak@ti.com> ++ * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +@@ -25,6 +29,9 @@ + #include <asm/io.h> + #include <asm/system.h> + #include <asm/arch/clock.h> ++#if defined(CONFIG_ARCH_OMAP3) && !defined(CONFIG_OMAP_PM_NONE) ++#include <asm/arch/omap-pm.h> ++#endif + + #define VERY_HI_RATE 900000000 + +@@ -32,12 +39,34 @@ static struct cpufreq_frequency_table *f + + #ifdef CONFIG_ARCH_OMAP1 + #define MPU_CLK "mpu" ++#elif CONFIG_ARCH_OMAP3 ++#define MPU_CLK "virt_vdd1_prcm_set" + #else + #define MPU_CLK "virt_prcm_set" + #endif + + static struct clk *mpu_clk; + ++#ifdef CONFIG_MACH_OMAP_3430SDP ++extern struct vdd_prcm_config vdd1_rate_table[]; ++extern struct vdd_prcm_config vdd2_rate_table[]; ++extern struct vdd_prcm_config iva2_rate_table[]; ++#endif ++ ++#if defined(CONFIG_ARCH_OMAP3) && !defined(CONFIG_OMAP_PM_NONE) ++int cpufreq_pre_func(struct notifier_block *n, unsigned long event, void *ptr); ++int cpufreq_post_func(struct notifier_block *n, unsigned long event, void *ptr); ++static struct notifier_block cpufreq_pre = { ++ cpufreq_pre_func, ++ NULL, ++}; ++ ++static struct notifier_block cpufreq_post = { ++ cpufreq_post_func, ++ NULL, ++}; ++#endif ++ + /* TODO: Add support for SDRAM timing changes */ + + int omap_verify_speed(struct cpufreq_policy *policy) +@@ -89,7 +118,7 @@ static int omap_target(struct cpufreq_po + + if (freqs.old == freqs.new) + return ret; +- ++#ifdef CONFIG_ARCH_OMAP1 + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + #ifdef CONFIG_CPU_FREQ_DEBUG + printk(KERN_DEBUG "cpufreq-omap: transition: %u --> %u\n", +@@ -97,10 +126,50 @@ static int omap_target(struct cpufreq_po + #endif + ret = clk_set_rate(mpu_clk, freqs.new * 1000); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); +- ++#elif defined(CONFIG_ARCH_OMAP3) && !defined(CONFIG_OMAP_PM_NONE)\ ++ && defined(CONFIG_MACH_OMAP_3430SDP) ++ { ++ int ind; ++ for (ind = 1; ind <= MAX_VDD1_OPP; ind++) { ++ if (vdd1_rate_table[ind].speed/1000 >= freqs.new) { ++ omap_pm_cpu_set_freq ++ (vdd1_rate_table[ind].speed); ++ break; ++ } ++ } ++ } ++#endif + return ret; + } + ++#if defined(CONFIG_ARCH_OMAP3) && !defined(CONFIG_OMAP_PM_NONE) ++static struct cpufreq_freqs freqs_notify; ++int cpufreq_pre_func(struct notifier_block *n, unsigned long event, void *ptr) ++{ ++ struct clk_notifier_data *cnd; ++ ++ cnd = (struct clk_notifier_data *)ptr; ++ freqs_notify.old = cnd->old_rate/1000; ++ freqs_notify.new = cnd->new_rate/1000; ++ /* HACK: The clk_notify_post_rate_chg currently ++ * returns a zero for old_rate at bootup ++ */ ++ if (freqs_notify.old == 0) ++ freqs_notify.old = 500000; ++ cpufreq_notify_transition(&freqs_notify, CPUFREQ_PRECHANGE); ++ return 0; ++} ++ ++int cpufreq_post_func(struct notifier_block *n, unsigned long event, void *ptr) ++{ ++ struct clk_notifier_data *cnd; ++ ++ cnd = (struct clk_notifier_data *)ptr; ++ cpufreq_notify_transition(&freqs_notify, CPUFREQ_POSTCHANGE); ++ return 0; ++} ++#endif ++ + static int __init omap_cpu_init(struct cpufreq_policy *policy) + { + int result = 0; +@@ -128,7 +197,10 @@ static int __init omap_cpu_init(struct c + + /* FIXME: what's the actual transition time? */ + policy->cpuinfo.transition_latency = 10 * 1000 * 1000; +- ++#if defined(CONFIG_ARCH_OMAP3) && !defined(CONFIG_OMAP_PM_NONE) ++ clk_notifier_register(mpu_clk, &cpufreq_pre); ++ clk_notifier_register(mpu_clk, &cpufreq_post); ++#endif + return 0; + } + +Index: linux-omap-2.6/drivers/cpufreq/cpufreq.c +=================================================================== +--- linux-omap-2.6.orig/drivers/cpufreq/cpufreq.c 2008-08-11 17:21:57.000000000 ++0530 ++++ linux-omap-2.6/drivers/cpufreq/cpufreq.c 2008-08-11 17:36:53.000000000 +0530 +@@ -321,7 +321,9 @@ void cpufreq_notify_transition(struct cp + { + struct cpufreq_policy *policy; + ++#if 0 /*This causes an issue if clk_notify_post_rate_chg is used*/ + BUG_ON(irqs_disabled()); ++#endif + + freqs->flags = cpufreq_driver->flags; + dprintk("notification %u of frequency transition to %u kHz\n", +Index: linux-omap-2.6/arch/arm/configs/omap_3430sdp_defconfig +=================================================================== +--- linux-omap-2.6.orig/arch/arm/configs/omap_3430sdp_defconfig 2008-08-11 +17:36:43.000000000 +0530 ++++ linux-omap-2.6/arch/arm/configs/omap_3430sdp_defconfig 2008-08-11 +17:37:33.000000000 +0530 +@@ -193,6 +193,9 @@ CONFIG_OMAP_LL_DEBUG_UART1=y + # CONFIG_OMAP_LL_DEBUG_UART2 is not set + # CONFIG_OMAP_LL_DEBUG_UART3 is not set + CONFIG_OMAP_SERIAL_WAKE=y ++# CONFIG_OMAP_PM_NONE is not set ++# CONFIG_OMAP_PM_NOOP is not set ++CONFIG_OMAP_PM_SRF=y + CONFIG_ARCH_OMAP34XX=y + CONFIG_ARCH_OMAP3430=y + +@@ -288,7 +291,21 @@ CONFIG_CMDLINE="root=/dev/nfs nfsroot=19 + # + # CPU Frequency scaling + # +-# CONFIG_CPU_FREQ is not set ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_TABLE=y ++# CONFIG_CPU_FREQ_DEBUG is not set ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set + + # + # Floating point emulation + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/01-omappm-srf.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/01-omappm-srf.eml new file mode 100644 index 0000000000..8b8b183808 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/01-omappm-srf.eml @@ -0,0 +1,513 @@ +Adds Generic Shared Resource Framework structures and API's + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> +--- + arch/arm/plat-omap/resource.c | 389 +++++++++++++++++++++++++++++++++++ + include/asm-arm/arch-omap/resource.h | 97 ++++++++ + 2 files changed, 486 insertions(+) + +Index: linux-omap-2.6/arch/arm/plat-omap/resource.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/plat-omap/resource.c 2008-08-07 15:06:58.000000000 ++0530 +@@ -0,0 +1,389 @@ ++/* ++ * linux/arch/arm/plat-omap/resource.c ++ * Shared Resource Framework API implementation ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Written by Rajendra Nayak <rnayak@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ * History: ++ * ++ */ ++ ++#include <linux/errno.h> ++#include <linux/err.h> ++#include <asm/arch/resource.h> ++#include <linux/slab.h> ++ ++/* res_list contains all registered struct shared_resource */ ++static LIST_HEAD(res_list); ++ ++/* res_mutex protects res_list add and del ops */ ++static DEFINE_MUTEX(res_mutex); ++ ++/* Static Pool of users for a resource */ ++/* used till kmalloc becomes availabel */ ++struct users_list usr_list[MAX_USERS]; ++ ++/* Private/Internal functions */ ++ ++/** ++ * resource_lookup - loop up a resource by its name, return a pointer ++ * @name: The name of the resource to lookup ++ * ++ * Looks for a registered resource by its name. Returns a pointer to ++ * the struct shared_resource if found, else returns NULL. ++ */ ++static struct shared_resource *resource_lookup(const char *name) ++{ ++ struct shared_resource *res, *tmp_res; ++ ++ if (!name) ++ return NULL; ++ ++ res = NULL; ++ ++ srf_mutex_lock(&res_mutex); ++ list_for_each_entry(tmp_res, &res_list, node) { ++ if (!strcmp(name, tmp_res->name)) { ++ res = tmp_res; ++ break; ++ } ++ } ++ srf_mutex_unlock(&res_mutex); ++ return res; ++} ++ ++/** ++ * update_resource_level - Regenerates and updates the curr_level of the res ++ * @resp: Pointer to the resource ++ * ++ * This function looks at all the users of the given resource and the levels ++ * requested by each of them, and recomputes a target level for the resource ++ * acceptable to all its current usres. It then calls platform specific ++ * change_level to change the level of the resource. ++ * Returns 0 on success, else a non-zero value returned by the platform ++ * specific change_level function. ++ **/ ++static int update_resource_level(struct shared_resource *resp) ++{ ++ struct users_list *user; ++ unsigned long target_level; ++ int ret; ++ ++ /* Regenerate the target_value for the resource */ ++ target_level = RES_DEFAULTLEVEL; ++ list_for_each_entry(user, &resp->users_list, node) ++ if (user->level > target_level) ++ target_level = user->level; ++ ++ pr_debug("SRF: Changing Level for resource %s to %ld\n", ++ resp->name, target_level); ++ ret = resp->ops->change_level(resp, target_level); ++ if (ret) { ++ printk(KERN_ERR "Unable to Change" ++ "level for resource %s to %ld\n", ++ resp->name, target_level); ++ return ret; ++ } ++ return ret; ++} ++ ++/** ++ * get_user - gets a new users_list struct from static pool or dynamically ++ * ++ * This function initally looks for availability in the static pool and ++ * tries to dynamcially allocate only once the static pool is empty. ++ * We hope that during bootup by the time we hit a case of dynamic allocation ++ * slab initialization would have happened. ++ * Returns a pointer users_list struct on success. On dynamic allocation failure ++ * returns a ERR_PTR(-ENOMEM). ++ */ ++static struct users_list *get_user(void) ++{ ++ int ind = 0; ++ struct users_list *user; ++ ++ /* See if something available in the static pool */ ++ while (ind < MAX_USERS) { ++ if (usr_list[ind].usage == UNUSED) ++ break; ++ else ++ ind++; ++ } ++ if (ind < MAX_USERS) { ++ /* Pick from the static pool */ ++ user = &usr_list[ind]; ++ user->usage = STATIC_ALLOC; ++ } else { ++ /* By this time we hope slab is initialized */ ++ if (slab_is_available()) { ++ user = kmalloc(sizeof(struct users_list), GFP_KERNEL); ++ if (!user) { ++ printk(KERN_ERR "SRF:FATAL ERROR: kmalloc" ++ "failed\n"); ++ return ERR_PTR(-ENOMEM); ++ } ++ user->usage = DYNAMIC_ALLOC; ++ } else { ++ /* Dynamic alloc not available yet */ ++ printk(KERN_ERR "SRF: FATAL ERROR: users_list" ++ "initial POOL EMPTY before slab init\n"); ++ return ERR_PTR(-ENOMEM); ++ } ++ } ++ return user; ++} ++ ++/** ++ * free_user - frees the dynamic users_list and marks the static one unused ++ * @user: The struct users_list to be freed ++ * ++ * Looks at the usage flag and either frees the users_list if it was ++ * dynamically allocated, and if its from the static pool, marks it unused. ++ * No return value. ++ */ ++void free_user(struct users_list *user) ++{ ++ if (user->usage == DYNAMIC_ALLOC) ++ kfree(user); ++ else { ++ user->usage = UNUSED; ++ user->level = RES_DEFAULTLEVEL; ++ user->dev = NULL; ++ } ++} ++ ++/** ++ * resource_init - Initializes the Shared resource framework. ++ * @resources: List of all the resources modelled ++ * ++ * Loops through the list of resources and registers all that ++ * are available for the current CPU. ++ * No return value ++ */ ++void resource_init(struct shared_resource **resources) ++{ ++ struct shared_resource **resp; ++ int ind; ++ ++ pr_debug("Initializing Shared Resource Framework\n"); ++ ++ if (!cpu_is_omap343x()) { ++ /* This CPU is not supported */ ++ printk(KERN_WARNING "Shared Resource Framework does not" ++ "support this CPU type.\n"); ++ WARN_ON(1); ++ } ++ ++ /* Init the users_list POOL */ ++ for (ind = 0; ind < MAX_USERS; ind++) { ++ usr_list[ind].usage = UNUSED; ++ usr_list[ind].dev = NULL; ++ usr_list[ind].level = RES_DEFAULTLEVEL; ++ } ++ ++ if (resources) ++ for (resp = resources; *resp; resp++) ++ resource_register(*resp); ++} ++ ++/** ++ * resource_register - registers and initializes a resource ++ * @res: struct shared_resource * to register ++ * ++ * Initializes the given resource and adds it to the resource list ++ * for the current CPU. ++ * Returns 0 on success, -EINVAL if given a NULL pointer, -EEXIST if the ++ * resource is already registered. ++ */ ++int resource_register(struct shared_resource *resp) ++{ ++ if (!resp) ++ return -EINVAL; ++ ++ if (!omap_chip_is(resp->omap_chip)) ++ return -EINVAL; ++ ++ /* Verify that the resource is not already registered */ ++ if (resource_lookup(resp->name)) ++ return -EEXIST; ++ ++ INIT_LIST_HEAD(&resp->users_list); ++ mutex_init(&resp->res_mutex); ++ ++ srf_mutex_lock(&res_mutex); ++ /* Add the resource to the resource list */ ++ list_add(&resp->node, &res_list); ++ srf_mutex_unlock(&res_mutex); ++ ++ /* Call the resource specific init*/ ++ if (resp->ops->init) ++ resp->ops->init(resp); ++ ++ pr_debug("resource: registered %s\n", resp->name); ++ ++ return 0; ++} ++EXPORT_SYMBOL(resource_register); ++ ++/** ++ * resource_unregister - unregister a resource ++ * @res: struct shared_resource * to unregister ++ * ++ * Removes a resource from the resource list. ++ * Returns 0 on success, -EINVAL if passed a NULL pointer. ++ */ ++int resource_unregister(struct shared_resource *resp) ++{ ++ if (!resp) ++ return -EINVAL; ++ ++ srf_mutex_lock(&res_mutex); ++ /* delete the resource from the resource list */ ++ list_del(&resp->node); ++ srf_mutex_unlock(&res_mutex); ++ ++ pr_debug("resource: unregistered %s\n", resp->name); ++ ++ return 0; ++} ++EXPORT_SYMBOL(resource_unregister); ++ ++/** ++ * resource_request - Request for a required level of a resource ++ * @name: The name of the resource requested ++ * @dev: Uniquely identifes the caller ++ * @level: The requested level for the resource ++ * ++ * This function recomputes the target level of the resource based on ++ * the level requested by the user. The level of the resource is ++ * changed to the target level, if it is not the same as the existing level ++ * of the resource. Multiple calls to this function by the same device will ++ * replace the previous level requested ++ * Returns 0 on success, -EINVAL if the resource name passed in invalid. ++ * -ENOMEM if no static pool available or dynamic allocations fails. ++ * Else returns a non-zero error value returned by one of the failing ++ * shared_resource_ops. ++ */ ++int resource_request(const char *name, struct device *dev, ++ unsigned long level) ++{ ++ struct shared_resource *resp; ++ struct users_list *user; ++ int found = 0, ret = 0; ++ ++ resp = resource_lookup(name); ++ if (!resp) { ++ printk(KERN_ERR "resource_request: Invalid resource name\n"); ++ return -EINVAL; ++ } ++ ++ /* Call the resource specific validate function */ ++ if (resp->ops->validate_level) ++ ret = resp->ops->validate_level(resp, level); ++ if (ret) ++ return ret; ++ ++ srf_mutex_lock(&resp->res_mutex); ++ list_for_each_entry(user, &(resp->users_list), node) ++ if (user->dev == dev) { ++ found = 1; ++ break; ++ } ++ if (!found) { ++ /* First time user */ ++ user = get_user(); ++ if (IS_ERR(user)) { ++ srf_mutex_unlock(&resp->res_mutex); ++ return -ENOMEM; ++ } ++ user->dev = dev; ++ list_add(&user->node, &resp->users_list); ++ resp->no_of_users++; ++ } ++ user->level = level; ++ srf_mutex_unlock(&resp->res_mutex); ++ ++ /* Recompute and set the current level for the resource */ ++ return update_resource_level(resp); ++} ++EXPORT_SYMBOL(resource_request); ++ ++/** ++ * resource_release - Release a previously requested level of a resource ++ * @name: The name of the resource to be released ++ * @dev: Uniquely identifes the caller ++ * ++ * This function recomputes the target level of the resource after removing ++ * the level requested by the user. The level of the resource is ++ * changed to the target level, if it is not the same as the existing level ++ * of the resource. ++ * Returns 0 on success, -EINVAL if the resource name or dev structure ++ * is invalid. ++ */ ++int resource_release(const char *name, struct device *dev) ++{ ++ struct shared_resource *resp; ++ struct users_list *user; ++ int found = 0; ++ ++ resp = resource_lookup(name); ++ if (!resp) { ++ printk(KERN_ERR "resource_release: Invalid resource name\n"); ++ return -EINVAL; ++ } ++ ++ srf_mutex_lock(&resp->res_mutex); ++ list_for_each_entry(user, &(resp->users_list), node) ++ if (user->dev == dev) { ++ found = 1; ++ break; ++ } ++ ++ if (!found) { ++ srf_mutex_unlock(&resp->res_mutex); ++ /* No such user exists */ ++ return -EINVAL; ++ } ++ ++ resp->no_of_users--; ++ list_del(&user->node); ++ free_user(user); ++ srf_mutex_unlock(&resp->res_mutex); ++ ++ /* Recompute and set the current level for the resource */ ++ return update_resource_level(resp); ++} ++EXPORT_SYMBOL(resource_release); ++ ++/** ++ * resource_get_level - Returns the current level of the resource ++ * @name: Name of the resource ++ * ++ * Returns the current level of the resource if found, else returns ++ * -EINVAL if the resource name is invalid. ++ */ ++int resource_get_level(const char *name) ++{ ++ struct shared_resource *resp; ++ u32 ret; ++ ++ resp = resource_lookup(name); ++ if (!resp) { ++ printk(KERN_ERR "resource_release: Invalid resource name\n"); ++ return -EINVAL; ++ } ++ ++ srf_mutex_lock(&resp->res_mutex); ++ ret = resp->curr_level; ++ srf_mutex_unlock(&resp->res_mutex); ++ return ret; ++} ++EXPORT_SYMBOL(resource_get_level); +Index: linux-omap-2.6/include/asm-arm/arch-omap/resource.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/include/asm-arm/arch-omap/resource.h 2008-08-07 +15:06:58.000000000 +0530 +@@ -0,0 +1,97 @@ ++/* ++ * linux/include/asm-arm/arch-omap/resource.h ++ * Structure definitions for Shared resource Framework ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Written by Rajendra Nayak <rnayak@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ * ++ * History: ++ * ++ */ ++ ++#ifndef __ARCH_ARM_OMAP_RESOURCE_H ++#define __ARCH_ARM_OMAP_RESOURCE_H ++ ++#include <linux/list.h> ++#include <linux/mutex.h> ++#include <linux/device.h> ++#include <asm/arch/cpu.h> ++ ++#define srf_mutex_lock(x) { \ ++ if (!(in_atomic() || irqs_disabled())) \ ++ mutex_lock(x); \ ++ } ++#define srf_mutex_unlock(x) { \ ++ if (!(in_atomic() || irqs_disabled())) \ ++ mutex_unlock(x); \ ++ } ++ ++#define RES_DEFAULTLEVEL 0x0 ++ ++struct shared_resource_ops; /* forward declaration */ ++ ++/* Used to model a Shared Multilevel Resource */ ++struct shared_resource { ++ /* Resource name */ ++ const char *name; ++ /* Used to represent the OMAP chip types containing this res */ ++ const struct omap_chip_id omap_chip; ++ /* Total no of users at any point of this resource */ ++ u8 no_of_users; ++ /* Current level of this resource */ ++ u32 curr_level; ++ /* Used to store any resource specific data */ ++ void *resource_data; ++ /* List of all the current users for this resource */ ++ struct list_head users_list; ++ /* Used to guard the resource */ ++ struct mutex res_mutex; ++ /* Shared resource operations */ ++ struct shared_resource_ops *ops; ++ struct list_head node; ++}; ++ ++struct shared_resource_ops { ++ /* Init function for the resource */ ++ void (*init)(struct shared_resource *res); ++ /* Function to change the level of the resource */ ++ int (*change_level)(struct shared_resource *res, u32 target_level); ++ /* Function to validate the requested level of the resource */ ++ int (*validate_level)(struct shared_resource *res, u32 target_level); ++}; ++ ++/* This is to statically defining the users pool */ ++/* This static pool is used till kmalloc becomes available */ ++#define MAX_USERS 10 ++#define UNUSED 0x0 ++#define DYNAMIC_ALLOC 0x1 ++#define STATIC_ALLOC 0x2 ++ ++/* Used to represent a user of a shared resource */ ++struct users_list { ++ /* Device pointer used to uniquely identify the user */ ++ struct device *dev; ++ /* Current level as requested for the resource by the user */ ++ u32 level; ++ struct list_head node; ++ u8 usage; ++}; ++ ++/* Shared resource Framework API's */ ++void resource_init(struct shared_resource **resources); ++int resource_register(struct shared_resource *res); ++int resource_unregister(struct shared_resource *res); ++int resource_request(const char *name, struct device *dev, ++ unsigned long level); ++int resource_release(const char *name, struct device *dev); ++int resource_get_level(const char *name); ++ ++#endif /* __ARCH_ARM_OMAP_RESOURCE_H */ + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/01-postrate-notifier.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/01-postrate-notifier.eml new file mode 100644 index 0000000000..8e72afeb3f --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/01-postrate-notifier.eml @@ -0,0 +1,392 @@ +Add the infrastructure necessary to support clock post-rate-change notifiers +in the OMAP clock framework. This includes: + +- adding the clk_notify_post_rate_chg() function, which will trigger a + notifier call chain when a clock rate is changed (but which currently + does nothing); and + +- adding calls to clk_notify_post_rate_chg() everywhere clk->rate is + assigned (mostly *_recalc() functions). + +This patch has no functional effect by itself; the actual notifier +implementation follows in a separate patch. + +One item to note is that the post-rate-change notifier is called even +if the new clock rate is identical to the old rate. This is because +the process of changing the rate may have temporarily disabled or +glitched the clock or one of its parents, and some devices may be +sensitive to such changes. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + arch/arm/mach-omap2/clock.c | 37 +++++++++++++++++++++++++++------ + arch/arm/mach-omap2/clock24xx.c | 42 +++++++++++++++++++++++++++++++++++-- + arch/arm/mach-omap2/clock34xx.c | 10 +++++++++ + arch/arm/plat-omap/clock.c | 32 ++++++++++++++++++++++++++++ + include/asm-arm/arch-omap/clock.h | 21 +++++++++++++++++++ + 5 files changed, 134 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c +index ed15868..bd3c1f8 100644 +--- a/arch/arm/mach-omap2/clock.c ++++ b/arch/arm/mach-omap2/clock.c +@@ -165,10 +165,15 @@ u32 omap2_get_dpll_rate(struct clk *clk) + */ + void omap2_fixed_divisor_recalc(struct clk *clk) + { ++ unsigned long orig_rate; ++ + WARN_ON(!clk->fixed_div); + ++ orig_rate = clk->rate; + clk->rate = clk->parent->rate / clk->fixed_div; + ++ clk_notify_post_rate_chg(clk, orig_rate, clk->rate); ++ + if (clk->flags & RATE_PROPAGATES) + propagate_rate(clk); + } +@@ -376,6 +381,7 @@ int omap2_clk_enable(struct clk *clk) + void omap2_clksel_recalc(struct clk *clk) + { + u32 div = 0; ++ unsigned long orig_rate; + + pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); + +@@ -385,10 +391,13 @@ void omap2_clksel_recalc(struct clk *clk) + + if (clk->rate == (clk->parent->rate / div)) + return; ++ orig_rate = clk->rate; + clk->rate = clk->parent->rate / div; + + pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); + ++ clk_notify_post_rate_chg(clk, orig_rate, clk->rate); ++ + if (clk->flags & RATE_PROPAGATES) + propagate_rate(clk); + } +@@ -662,6 +671,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) + wmb(); + } + ++ /* post-rate-change notifier will be called by omap2_clk_set_rate() */ ++ + return 0; + } + +@@ -670,20 +681,30 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) + int omap2_clk_set_rate(struct clk *clk, unsigned long rate) + { + int ret = -EINVAL; +- +- pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); ++ unsigned long orig_rate; + + /* CONFIG_PARTICIPANT clocks are changed only in sets via the + rate table mechanism, driven by mpu_speed */ + if (clk->flags & CONFIG_PARTICIPANT) + return -EINVAL; + ++ if (!clk->set_rate) ++ return -EINVAL; ++ ++ orig_rate = clk->rate; ++ ++ pr_debug("clock: set_rate for clock %s from %ld Hz to %ld Hz\n", ++ clk->name, orig_rate, rate); ++ + /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ +- if (clk->set_rate) +- ret = clk->set_rate(clk, rate); ++ ret = clk->set_rate(clk, rate); + +- if (ret == 0 && (clk->flags & RATE_PROPAGATES)) +- propagate_rate(clk); ++ if (ret == 0) { ++ clk_notify_post_rate_chg(clk, orig_rate, rate); ++ ++ if (clk->flags & RATE_PROPAGATES) ++ propagate_rate(clk); ++ } + + return ret; + } +@@ -732,6 +753,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) + { + void __iomem *src_addr; + u32 field_val, field_mask, reg_val, parent_div; ++ unsigned long orig_rate; + + if (clk->flags & CONFIG_PARTICIPANT) + return -EINVAL; +@@ -765,11 +787,14 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) + clk->parent = new_parent; + + /* CLKSEL clocks follow their parents' rates, divided by a divisor */ ++ orig_rate = clk->rate; + clk->rate = new_parent->rate; + + if (parent_div > 0) + clk->rate /= parent_div; + ++ clk_notify_post_rate_chg(clk, orig_rate, clk->rate); ++ + pr_debug("clock: set parent of %s to %s (new rate %ld)\n", + clk->name, clk->parent->name, clk->rate); + +diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c +index 54cc6e1..e001549 100644 +--- a/arch/arm/mach-omap2/clock24xx.c ++++ b/arch/arm/mach-omap2/clock24xx.c +@@ -172,11 +172,22 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) + + static void omap2_dpllcore_recalc(struct clk *clk) + { ++ unsigned long orig_rate; ++ ++ orig_rate = clk->rate; + clk->rate = omap2_get_dpll_rate_24xx(clk); + ++ clk_notify_post_rate_chg(clk, orig_rate, clk->rate); ++ + propagate_rate(clk); + } + ++/* ++ * XXX REVISIT: This code needs to keep track of the underlying struct ++ * clocks that it is changing, so it can call post-rate-change notifiers ++ * on them. This function probably should be rewritten to use the clock ++ * fw. ++ */ + static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) + { + u32 cur_rate, low, mult, div, valid_rate, done_rate; +@@ -259,7 +270,14 @@ dpll_exit: + */ + static void omap2_table_mpu_recalc(struct clk *clk) + { ++ unsigned long orig_rate; ++ ++ orig_rate = clk->rate; + clk->rate = curr_prcm_set->mpu_speed; ++ ++ clk_notify_post_rate_chg(clk, orig_rate, clk->rate); ++ ++ /* No rate propagation since table clocks have no children */ + } + + /* +@@ -294,7 +312,14 @@ static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) + return highest_rate; + } + +-/* Sets basic clocks based on the specified rate */ ++/* ++ * Sets basic clocks based on the specified rate ++ * ++ * XXX REVISIT: This code needs to keep track of the underlying struct ++ * clocks that it is changing, so it can call post-rate-change notifiers ++ * on them. This function probably should be rewritten to use the clock ++ * fw. ++ */ + static int omap2_select_table_rate(struct clk *clk, unsigned long rate) + { + u32 cur_rate, done_rate, bypass = 0, tmp; +@@ -353,7 +378,8 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate) + cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); + + /* Major subsystem dividers */ +- tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; ++ tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & ++ OMAP24XX_CLKSEL_DSS2_MASK; + cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, + CM_CLKSEL1); + +@@ -460,13 +486,25 @@ static u32 omap2_get_sysclkdiv(void) + + static void omap2_osc_clk_recalc(struct clk *clk) + { ++ unsigned long orig_rate; ++ ++ orig_rate = clk->rate; + clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); ++ ++ clk_notify_post_rate_chg(clk, orig_rate, clk->rate); ++ + propagate_rate(clk); + } + + static void omap2_sys_clk_recalc(struct clk *clk) + { ++ unsigned long orig_rate; ++ ++ orig_rate = clk->rate; + clk->rate = clk->parent->rate / omap2_get_sysclkdiv(); ++ ++ clk_notify_post_rate_chg(clk, orig_rate, clk->rate); ++ + propagate_rate(clk); + } + +diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c +index 408b51a..7b89b61 100644 +--- a/arch/arm/mach-omap2/clock34xx.c ++++ b/arch/arm/mach-omap2/clock34xx.c +@@ -53,8 +53,13 @@ + */ + static void omap3_dpll_recalc(struct clk *clk) + { ++ unsigned long orig_rate; ++ ++ orig_rate = clk->rate; + clk->rate = omap2_get_dpll_rate(clk); + ++ clk_notify_post_rate_chg(clk, orig_rate, clk->rate); ++ + propagate_rate(clk); + } + +@@ -500,6 +505,7 @@ static void omap3_clkoutx2_recalc(struct clk *clk) + const struct dpll_data *dd; + u32 v; + struct clk *pclk; ++ unsigned long orig_rate; + + /* Walk up the parents of clk, looking for a DPLL */ + pclk = clk->parent; +@@ -513,6 +519,8 @@ static void omap3_clkoutx2_recalc(struct clk *clk) + + WARN_ON(!dd->control_reg || !dd->enable_mask); + ++ orig_rate = clk->rate; ++ + v = __raw_readl(dd->control_reg) & dd->enable_mask; + v >>= __ffs(dd->enable_mask); + if (v != DPLL_LOCKED) +@@ -520,6 +528,8 @@ static void omap3_clkoutx2_recalc(struct clk *clk) + else + clk->rate = clk->parent->rate * 2; + ++ clk_notify_post_rate_chg(clk, orig_rate, clk->rate); ++ + if (clk->flags & RATE_PROPAGATES) + propagate_rate(clk); + } +diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c +index c2e741d..421d076 100644 +--- a/arch/arm/plat-omap/clock.c ++++ b/arch/arm/plat-omap/clock.c +@@ -254,10 +254,16 @@ __setup("mpurate=", omap_clk_setup); + /* Used for clocks that always have same value as the parent clock */ + void followparent_recalc(struct clk *clk) + { ++ unsigned long orig_rate; ++ + if (clk == NULL || IS_ERR(clk)) + return; + ++ orig_rate = clk->rate; + clk->rate = clk->parent->rate; ++ ++ clk_notify_post_rate_chg(clk, orig_rate, clk->rate); ++ + if (unlikely(clk->flags & RATE_PROPAGATES)) + propagate_rate(clk); + } +@@ -373,6 +379,32 @@ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) + EXPORT_SYMBOL(clk_init_cpufreq_table); + #endif + ++/** ++ * clk_notify_post_rate_chg - call post-clk-rate-change notifier chain ++ * @clk: struct clk * that is changing rate ++ * @old_rate: old rate ++ * @new_rate: new rate ++ * ++ * Triggers a notifier call chain on the post-clk-rate-change notifier ++ * for clock 'clk'. Passes a pointer to the struct clk and the ++ * previous and current rates to the notifier callback. Intended to be ++ * called by internal clock code only. No return value. ++ */ ++void clk_notify_post_rate_chg(struct clk *clk, unsigned long old_rate, ++ unsigned long new_rate) ++{ ++ struct clk_notifier *cn; ++ struct clk_notifier_data cnd; ++ ++ cnd.clk = clk; ++ cnd.old_rate = old_rate; ++ cnd.new_rate = new_rate; ++ ++ /* XXX Call notifier here */ ++ ++} ++ ++ + /*-------------------------------------------------------------------------*/ + + #ifdef CONFIG_OMAP_RESET_CLOCKS +diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h +index bfaf7b6..e3c9aeb 100644 +--- a/include/asm-arm/arch-omap/clock.h ++++ b/include/asm-arm/arch-omap/clock.h +@@ -10,6 +10,8 @@ + * published by the Free Software Foundation. + */ + ++#include <linux/notifier.h> ++ + #ifndef __ARCH_ARM_OMAP_CLOCK_H + #define __ARCH_ARM_OMAP_CLOCK_H + +@@ -58,6 +60,19 @@ struct dpll_data { + + #endif + ++struct clk_notifier { ++ struct clk *clk; ++ struct atomic_notifier_head notifier_head; ++ struct list_head node; ++}; ++ ++struct clk_notifier_data { ++ struct clk *clk; ++ unsigned long old_rate; ++ unsigned long new_rate; ++}; ++ ++ + struct clk { + struct list_head node; + struct module *owner; +@@ -121,6 +136,10 @@ extern void clk_allow_idle(struct clk *clk); + extern void clk_deny_idle(struct clk *clk); + extern int clk_get_usecount(struct clk *clk); + extern void clk_enable_init_clocks(void); ++extern int clk_notifier_register(struct clk *clk, struct notifier_block *nb); ++extern int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb); ++extern void clk_notify_post_rate_chg(struct clk *clk, unsigned long old_rate, ++ unsigned long new_rate); + #ifdef CONFIG_CPU_FREQ + extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); + #endif +@@ -161,6 +180,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); + + #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) + ++/* Clk rate change notifier callback type */ ++#define CLK_POST_RATE_CHANGE 1 + + /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ + #define CORE_CLK_SRC_32K 0 + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/02-beagle_use_gptimer12 b/recipes/linux/linux-omap-2.6.26/beagleboard/02-beagle_use_gptimer12 new file mode 100644 index 0000000000..51d2c8cff0 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/02-beagle_use_gptimer12 @@ -0,0 +1,38 @@ +BeagleBoard: make Beagle use GPTIMER12 for system ticks + +From: Paul Walmsley <paul@pwsan.com> + +There is suspicion that the 32kHz input clock to the OMAP may be noisy +on BeagleBoards. On OMAP2/3 GPTIMER1, this can cause the timer +counter register to warp to unknown values or miss interrupt +conditions. So, use GPTIMER12 instead, which apparently has its own +secure 32kHz oscillator and will hopefully not be prone to the 32kHz +glitches. +--- + + arch/arm/configs/omap3_beagle_defconfig | 5 +++-- + 1 files changed, 3 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/configs/omap3_beagle_defconfig b/arch/arm/configs/omap3_beagle_defconfig +index e1b16d0..7805995 100644 +--- a/arch/arm/configs/omap3_beagle_defconfig ++++ defconfig +@@ -182,8 +182,8 @@ CONFIG_OMAP_BOOT_REASON=y + # CONFIG_OMAP_MCBSP is not set + # CONFIG_OMAP_MMU_FWK is not set + # CONFIG_OMAP_MBOX_FWK is not set +-CONFIG_OMAP_MPU_TIMER=y +-# CONFIG_OMAP_32K_TIMER is not set ++# CONFIG_OMAP_MPU_TIMER is not set ++CONFIG_OMAP_32K_TIMER=y + CONFIG_OMAP_DM_TIMER=y + # CONFIG_OMAP_LL_DEBUG_UART1 is not set + # CONFIG_OMAP_LL_DEBUG_UART2 is not set +@@ -198,6 +198,7 @@ CONFIG_ARCH_OMAP3430=y + # CONFIG_MACH_OMAP_3430SDP is not set + # CONFIG_MACH_OMAP3EVM is not set + CONFIG_MACH_OMAP3_BEAGLE=y ++CONFIG_OMAP_TICK_GPTIMER=12 + + # + # Boot options diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/02-omappm-mpu-latency-modeling.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/02-omappm-mpu-latency-modeling.eml new file mode 100644 index 0000000000..35ef87bdf0 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/02-omappm-mpu-latency-modeling.eml @@ -0,0 +1,245 @@ +Adds resource def's for mpu/core/powerdomain latencies for OMAP3 + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> +--- + arch/arm/mach-omap2/resource34xx.h | 226 +++++++++++++++++++++++++++++++++++++ + 1 files changed, 226 insertions(+) + +Index: linux-omap-2.6/arch/arm/mach-omap2/resource34xx.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/mach-omap2/resource34xx.h 2008-08-07 +15:07:02.000000000 +0530 +@@ -0,0 +1,226 @@ ++/* ++ * linux/arch/arm/mach-omap2/resource34xx.h ++ * ++ * OMAP3 resource definitions ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Written by Rajendra Nayak <rnayak@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ * ++ * History: ++ * ++ */ ++ ++#ifndef __ARCH_ARM_MACH_OMAP2_RESOURCE_H ++#define __ARCH_ARM_MACH_OMAP2_RESOURCE_H ++ ++#include <asm/arch/resource.h> ++#include <asm/arch/powerdomain.h> ++ ++/** ++ * mpu_latency/core_latency are used to control the cpuidle C state. ++ */ ++void init_latency(struct shared_resource *resp); ++int set_latency(struct shared_resource *resp, u32 target_level); ++ ++static u8 mpu_qos_req_added; ++static u8 core_qos_req_added; ++ ++static struct shared_resource_ops lat_res_ops = { ++ .init = init_latency, ++ .change_level = set_latency, ++}; ++ ++static struct shared_resource mpu_latency = { ++ .name = "mpu_latency", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .resource_data = &mpu_qos_req_added, ++ .ops = &lat_res_ops, ++}; ++ ++static struct shared_resource core_latency = { ++ .name = "core_latency", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .resource_data = &core_qos_req_added, ++ .ops = &lat_res_ops, ++}; ++ ++/** ++ * Power domain Latencies are used to control the target Power ++ * domain state once all clocks for the power domain ++ * are released. ++ */ ++void init_pd_latency(struct shared_resource *resp); ++int set_pd_latency(struct shared_resource *resp, u32 target_level); ++ ++/* Power Domain Latency levels */ ++#define PD_LATENCY_OFF 0x0 ++#define PD_LATENCY_RET 0x1 ++#define PD_LATENCY_INACT 0x2 ++#define PD_LATENCY_ON 0x3 ++ ++#define PD_LATENCY_MAXLEVEL 0x4 ++ ++struct pd_latency_db { ++ char *pwrdm_name; ++ struct powerdomain *pd; ++ /* Latencies for each state transition, stored in us */ ++ unsigned long latency[PD_LATENCY_MAXLEVEL]; ++}; ++ ++static struct shared_resource_ops pd_lat_res_ops = { ++ .init = init_pd_latency, ++ .change_level = set_pd_latency, ++}; ++ ++static struct pd_latency_db iva2_pwrdm_lat_db = { ++ .pwrdm_name = "iva2_pwrdm", ++ .latency[PD_LATENCY_OFF] = 1000, ++ .latency[PD_LATENCY_RET] = 100, ++ .latency[PD_LATENCY_INACT] = 0, ++ .latency[PD_LATENCY_ON] = 0 ++}; ++ ++static struct shared_resource iva2_pwrdm_latency = { ++ .name = "iva2_pwrdm_latency", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .resource_data = &iva2_pwrdm_lat_db, ++ .ops = &pd_lat_res_ops, ++}; ++ ++static struct pd_latency_db gfx_pwrdm_lat_db = { ++ .pwrdm_name = "gfx_pwrdm", ++ .latency[PD_LATENCY_OFF] = 1000, ++ .latency[PD_LATENCY_RET] = 100, ++ .latency[PD_LATENCY_INACT] = 0, ++ .latency[PD_LATENCY_ON] = 0 ++}; ++ ++static struct shared_resource gfx_pwrdm_latency = { ++ .name = "gfx_pwrdm_latency", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), ++ .resource_data = &gfx_pwrdm_lat_db, ++ .ops = &pd_lat_res_ops, ++}; ++ ++static struct shared_resource sgx_pwrdm_latency = { ++ .name = "sgx_pwrdm_latency", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), ++ .resource_data = &gfx_pwrdm_lat_db, ++ .ops = &pd_lat_res_ops, ++}; ++ ++static struct pd_latency_db dss_pwrdm_lat_db = { ++ .pwrdm_name = "dss_pwrdm", ++ .latency[PD_LATENCY_OFF] = 70, ++ .latency[PD_LATENCY_RET] = 20, ++ .latency[PD_LATENCY_INACT] = 0, ++ .latency[PD_LATENCY_ON] = 0 ++}; ++ ++static struct shared_resource dss_pwrdm_latency = { ++ .name = "dss_pwrdm_latency", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .resource_data = &dss_pwrdm_lat_db, ++ .ops = &pd_lat_res_ops, ++}; ++ ++static struct pd_latency_db cam_pwrdm_lat_db = { ++ .pwrdm_name = "cam_pwrdm", ++ .latency[PD_LATENCY_OFF] = 850, ++ .latency[PD_LATENCY_RET] = 35, ++ .latency[PD_LATENCY_INACT] = 0, ++ .latency[PD_LATENCY_ON] = 0 ++}; ++ ++static struct shared_resource cam_pwrdm_latency = { ++ .name = "cam_pwrdm_latency", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .resource_data = &cam_pwrdm_lat_db, ++ .ops = &pd_lat_res_ops, ++}; ++ ++static struct pd_latency_db per_pwrdm_lat_db = { ++ .pwrdm_name = "per_pwrdm", ++ .latency[PD_LATENCY_OFF] = 200, ++ .latency[PD_LATENCY_RET] = 110, ++ .latency[PD_LATENCY_INACT] = 0, ++ .latency[PD_LATENCY_ON] = 0 ++}; ++ ++static struct shared_resource per_pwrdm_latency = { ++ .name = "per_pwrdm_latency", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .resource_data = &per_pwrdm_lat_db, ++ .ops = &pd_lat_res_ops, ++}; ++ ++static struct pd_latency_db neon_pwrdm_lat_db = { ++ .pwrdm_name = "neon_pwrdm", ++ .latency[PD_LATENCY_OFF] = 1000, ++ .latency[PD_LATENCY_RET] = 100, ++ .latency[PD_LATENCY_INACT] = 0, ++ .latency[PD_LATENCY_ON] = 0 ++}; ++ ++static struct shared_resource neon_pwrdm_latency = { ++ .name = "neon_pwrdm_latency", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .resource_data = &neon_pwrdm_lat_db, ++ .ops = &pd_lat_res_ops, ++}; ++ ++static struct pd_latency_db usbhost_pwrdm_lat_db = { ++ .pwrdm_name = "usbhost_pwrdm", ++ .latency[PD_LATENCY_OFF] = 1000, ++ .latency[PD_LATENCY_RET] = 100, ++ .latency[PD_LATENCY_INACT] = 0, ++ .latency[PD_LATENCY_ON] = 0 ++}; ++ ++static struct shared_resource usbhost_pwrdm_latency = { ++ .name = "usbhost_pwrdm_latency", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), ++ .resource_data = &usbhost_pwrdm_lat_db, ++ .ops = &pd_lat_res_ops, ++}; ++ ++static struct pd_latency_db emu_pwrdm_lat_db = { ++ .pwrdm_name = "emu_pwrdm", ++ .latency[PD_LATENCY_OFF] = 1000, ++ .latency[PD_LATENCY_RET] = 100, ++ .latency[PD_LATENCY_INACT] = 0, ++ .latency[PD_LATENCY_ON] = 0 ++}; ++ ++static struct shared_resource emu_pwrdm_latency = { ++ .name = "emu_pwrdm", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .resource_data = &emu_pwrdm_lat_db, ++ .ops = &pd_lat_res_ops, ++}; ++ ++struct shared_resource *resources_omap[] __initdata = { ++ &mpu_latency, ++ &core_latency, ++ /* Power Domain Latency resources */ ++ &iva2_pwrdm_latency, ++ &gfx_pwrdm_latency, ++ &sgx_pwrdm_latency, ++ &dss_pwrdm_latency, ++ &cam_pwrdm_latency, ++ &per_pwrdm_latency, ++ &neon_pwrdm_latency, ++ &usbhost_pwrdm_latency, ++ &emu_pwrdm_latency, ++ NULL ++}; ++ ++#endif /* __ARCH_ARM_MACH_OMAP2_RESOURCE_H */ + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/02-postrate-notifier.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/02-postrate-notifier.eml new file mode 100644 index 0000000000..97058f99e1 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/02-postrate-notifier.eml @@ -0,0 +1,186 @@ +This patch implements the remaining code for notification of clock +rate changes via the clock framework: + +- a notifier registration function, clk_notifier_register() + +- a notifier unregistration function, clk_notifier_unregister() + +- the clk_notify_post_rate_chg() call-chain function, has been fleshed out + +The implementation is via an atomic notifier, called with the clockfw +spinlock held. Callback functions must not sleep and must not re-enter +the clock framework, and should execute quickly. + +In the medium-term future, there are likely to be few users of these +notifiers. So, rather than storing one notifier per struct clk, +notifiers are stored in a separate, dynamically allocated list, +effectively trading execution speed (in terms of a sequential scan of +the notifier list) for memory savings. The implementation is +completely hidden from the callbacks and is easily changed if +necessary. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + arch/arm/plat-omap/clock.c | 118 +++++++++++++++++++++++++++++++++++++++++++- + 1 files changed, 115 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c +index 421d076..354f45f 100644 +--- a/arch/arm/plat-omap/clock.c ++++ b/arch/arm/plat-omap/clock.c +@@ -22,6 +22,7 @@ + #include <linux/mutex.h> + #include <linux/platform_device.h> + #include <linux/cpufreq.h> ++#include <linux/notifier.h> + #include <linux/debugfs.h> + + #include <asm/io.h> +@@ -34,6 +35,8 @@ static DEFINE_SPINLOCK(clockfw_lock); + + static struct clk_functions *arch_clock; + ++static LIST_HEAD(clk_notifier_list); ++ + /*------------------------------------------------------------------------- + * Standard clock functions defined in include/linux/clk.h + *-------------------------------------------------------------------------*/ +@@ -380,6 +383,110 @@ EXPORT_SYMBOL(clk_init_cpufreq_table); + #endif + + /** ++<<<<<<< current:arch/arm/plat-omap/clock.c ++======= ++ * clk_notifier_register - add a clock rate change notifier ++ * @clk: struct clk * to watch for rate echanges ++ * @nb: struct notifier_block * with callback info ++ * ++ * Request notification after a frequency change on clock 'clk'. This ++ * uses an atomic notifier. The callback will be called with ++ * interrupts disabled; therefore callback code should be very ++ * lightweight. Callback code must not call back into the clock ++ * framework. Callback code will be passed the previous and new rate ++ * of the clock. ++ * ++ * clk_notifier_register() must be called from process ++ * context. Returns -EINVAL if called with null arguments, -ENOMEM ++ * upon allocation failure; otherwise, passes along the return value ++ * of atomic_notifier_chain_register(). ++ */ ++int clk_notifier_register(struct clk *clk, struct notifier_block *nb) ++{ ++ struct clk_notifier *cn = NULL, *cn_new = NULL; ++ int r; ++ unsigned long flags; ++ ++ if (!clk || !nb) ++ return -EINVAL; ++ ++ /* Allocate this here speculatively so we can avoid GFP_ATOMIC */ ++ cn_new = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL); ++ if (!cn_new) ++ return -ENOMEM; ++ ++ spin_lock_irqsave(&clockfw_lock, flags); ++ ++ list_for_each_entry(cn, &clk_notifier_list, node) { ++ if (cn->clk == clk) ++ break; ++ } ++ ++ if (cn->clk != clk) { ++ cn_new->clk = clk; ++ ATOMIC_INIT_NOTIFIER_HEAD(&cn_new->notifier_head); ++ ++ list_add(&cn_new->node, &clk_notifier_list); ++ cn = cn_new; ++ } else { ++ kfree(cn_new); /* didn't need it after all */ ++ } ++ ++ r = atomic_notifier_chain_register(&cn->notifier_head, nb); ++ ++ spin_unlock_irqrestore(&clockfw_lock, flags); ++ ++ return r; ++} ++ ++/** ++ * clk_notifier_unregister - remove a clock rate change notifier ++ * @clk: struct clk * ++ * @nb: struct notifier_block * with callback info ++ * ++ * Request no further notification for frequency changes on clock ++ * 'clk'. This function presently does not release memory allocated ++ * by its corresponding _register function; see inline comments for ++ * more informations. Returns -EINVAL if called with null arguments; ++ * otherwise, passes along the return value of ++ * atomic_notifier_chain_unregister(). ++ */ ++int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb) ++{ ++ struct clk_notifier *cn = NULL; ++ int r = -EINVAL; ++ unsigned long flags; ++ ++ if (!clk || !nb) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&clockfw_lock, flags); ++ ++ list_for_each_entry(cn, &clk_notifier_list, node) { ++ if (cn->clk == clk) ++ break; ++ } ++ ++ if (cn->clk == clk) { ++ r = atomic_notifier_chain_unregister(&cn->notifier_head, nb); ++ ++ /* ++ * XXX unfortunately it seems that there is no polite ++ * way to test if a notifier has zero users. So once ++ * a post-notifier has been registered on a clock, ++ * that struct clk_notifier will not be freed, even if ++ * all of its users unregister. ++ */ ++ } else { ++ r = -ENOENT; ++ } ++ ++ spin_unlock_irqrestore(&clockfw_lock, flags); ++ ++ return r; ++} ++ ++/** + * clk_notify_post_rate_chg - call post-clk-rate-change notifier chain + * @clk: struct clk * that is changing rate + * @old_rate: old rate +@@ -400,11 +507,16 @@ void clk_notify_post_rate_chg(struct clk *clk, unsigned long old_rate, + cnd.old_rate = old_rate; + cnd.new_rate = new_rate; + +- /* XXX Call notifier here */ +- ++ list_for_each_entry(cn, &clk_notifier_list, node) { ++ if (cn->clk == clk) { ++ atomic_notifier_call_chain(&cn->notifier_head, ++ CLK_POST_RATE_CHANGE, ++ &cnd); ++ break; ++ } ++ } + } + +- + /*-------------------------------------------------------------------------*/ + + #ifdef CONFIG_OMAP_RESET_CLOCKS + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/02-set-clkseld11.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/02-set-clkseld11.diff new file mode 100644 index 0000000000..c437f145d3 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/02-set-clkseld11.diff @@ -0,0 +1,22 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sat, 5 Jul 2008 20:32:38 +0000 (+0100) +Subject: omap: set CLKSEL_DSS1 to 2 +X-Git-Tag: beagle-5~2 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=d23f9c3c5c6243b626f7ec4c255469de2536e488 + +omap: set CLKSEL_DSS1 to 2 +--- + +diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c +index 8fdf8f3..04dedec 100644 +--- a/arch/arm/mach-omap2/clock34xx.c ++++ b/arch/arm/mach-omap2/clock34xx.c +@@ -596,6 +596,8 @@ int __init omap2_clk_init(void) + /* u32 clkrate; */ + u32 cpu_clkflg; + ++ __raw_writel(0x1002, io_p2v(0x48004e40)); ++ + /* REVISIT: Ultimately this will be used for multiboot */ + #if 0 + if (cpu_is_omap242x()) { diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/03-enable-overlay-opt.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/03-enable-overlay-opt.diff new file mode 100644 index 0000000000..9fa749f5fc --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/03-enable-overlay-opt.diff @@ -0,0 +1,27 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sun, 6 Jul 2008 13:15:36 +0000 (+0100) +Subject: omapfb: enable overlay optimisation when possible +X-Git-Tag: beagle-5~1 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=a63ac3abdf6781f863112321260fe7a5da757802 + +omapfb: enable overlay optimisation when possible +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 6aff476..3b36227 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -582,11 +582,13 @@ static int omap_dispc_enable_plane(int plane, int enable) + const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES, + DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES, + DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES }; ++ unsigned overlay_opt = plane & !!enable & !dispc.color_key.key_type; + if ((unsigned int)plane > dispc.mem_desc.region_cnt) + return -EINVAL; + + enable_lcd_clocks(1); + MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0); ++ MOD_REG_FLD(DISPC_CONTROL, 1<<12 | 1<<5, overlay_opt<<12 | 1<<5); + enable_lcd_clocks(0); + + return 0; diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/03-omappm-omap3srf.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/03-omappm-omap3srf.eml new file mode 100644 index 0000000000..d052023f12 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/03-omappm-omap3srf.eml @@ -0,0 +1,167 @@ +Adds init/change_level/validate_level calls for OMAP3 resources + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> +--- + arch/arm/mach-omap2/resource34xx.c | 148 +++++++++++++++++++++++++++++++++++++ + 1 files changed, 148 insertions(+) + +Index: linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c 2008-08-07 +15:07:04.000000000 +0530 +@@ -0,0 +1,148 @@ ++/* ++ * linux/arch/arm/mach-omap2/resource34xx.c ++ * OMAP3 resource init/change_level/validate_level functions ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Written by Rajendra Nayak <rnayak@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ * History: ++ * ++ */ ++ ++#include <linux/pm_qos_params.h> ++#include <asm/arch/powerdomain.h> ++#include <asm/arch/clockdomain.h> ++#include "resource34xx.h" ++ ++/** ++ * init_latency - Initializes the mpu/core latency resource. ++ * @resp: Latency resource to be initalized ++ * ++ * No return value. ++ */ ++void init_latency(struct shared_resource *resp) ++{ ++ resp->no_of_users = 0; ++ resp->curr_level = RES_DEFAULTLEVEL; ++ *((u8 *)resp->resource_data) = 0; ++ return; ++} ++ ++/** ++ * set_latency - Adds/Updates and removes the CPU_DMA_LATENCY in *pm_qos_params. ++ * @resp: resource pointer ++ * @latency: target latency to be set ++ * ++ * Returns 0 on success, or error values as returned by ++ * pm_qos_update_requirement/pm_qos_add_requirement. ++ */ ++int set_latency(struct shared_resource *resp, u32 latency) ++{ ++ u8 *pm_qos_req_added; ++ ++ if (resp->curr_level == latency) ++ return 0; ++ else ++ /* Update the resources current level */ ++ resp->curr_level = latency; ++ ++ pm_qos_req_added = resp->resource_data; ++ if (latency == RES_DEFAULTLEVEL) ++ /* No more users left, remove the pm_qos_req if present */ ++ if (*pm_qos_req_added) { ++ pm_qos_remove_requirement(PM_QOS_CPU_DMA_LATENCY, ++ resp->name); ++ *pm_qos_req_added = 0; ++ return 0; ++ } ++ ++ if (*pm_qos_req_added) { ++ return pm_qos_update_requirement(PM_QOS_CPU_DMA_LATENCY, ++ resp->name, latency); ++ } else { ++ *pm_qos_req_added = 1; ++ return pm_qos_add_requirement(PM_QOS_CPU_DMA_LATENCY, ++ resp->name, latency); ++ } ++} ++ ++/** ++ * init_pd_latency - Initializes the power domain latency resource. ++ * @resp: Power Domain Latency resource to be initialized. ++ * ++ * No return value. ++ */ ++void init_pd_latency(struct shared_resource *resp) ++{ ++ struct pd_latency_db *pd_lat_db; ++ ++ resp->no_of_users = 0; ++ resp->curr_level = PD_LATENCY_OFF; ++ pd_lat_db = resp->resource_data; ++ /* Populate the power domain associated with the latency resource */ ++ pd_lat_db->pd = pwrdm_lookup(pd_lat_db->pwrdm_name); ++ return; ++} ++ ++/** ++ * set_pd_latency - Updates the curr_level of the power domain resource. ++ * @resp: Power domain latency resource. ++ * @latency: New latency value acceptable. ++ * ++ * This function maps the latency in microsecs to the acceptable ++ * Power domain state using the latency DB. ++ * It then programs the power domain to enter the target state. ++ * Always returns 0. ++ */ ++int set_pd_latency(struct shared_resource *resp, u32 latency) ++{ ++ u32 pd_lat_level, ind, i; ++ struct pd_latency_db *pd_lat_db; ++ struct powerdomain *pwrdm; ++ ++ pd_lat_db = resp->resource_data; ++ pwrdm = pd_lat_db->pd; ++ pd_lat_level = PD_LATENCY_OFF; ++ /* using the latency db map to the appropriate PD state */ ++ for (ind = 0; ind < PD_LATENCY_MAXLEVEL; ind++) ++ if (pd_lat_db->latency[ind] < latency) ++ pd_lat_level = ind; ++ ++ resp->curr_level = pd_lat_level; ++ switch (pd_lat_level) { ++ case PWRDM_POWER_OFF: ++ case PWRDM_POWER_RET: ++ /* Errata 1.29: No transitions from INACTIVE to RET/OFF ++ * possible. ++ * Need to be taken care of here. ++ */ ++ if (pwrdm_read_pwrst(pwrdm) != PWRDM_POWER_ON) { ++ /* Force the clock domains to ON */ ++ for (i = 0; pwrdm->pwrdm_clkdms[i]; i++) { ++ omap2_clkdm_deny_idle(pwrdm->pwrdm_clkdms[i]); ++ omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[i]); ++ } ++ pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_ON); ++ pwrdm_set_next_pwrst(pwrdm, pd_lat_level); ++ for (i = 0; pwrdm->pwrdm_clkdms[i]; i++) { ++ omap2_clkdm_sleep(pwrdm->pwrdm_clkdms[i]); ++ omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[i]); ++ } ++ } else ++ pwrdm_set_next_pwrst(pwrdm, pd_lat_level); ++ break; ++ case PWRDM_POWER_ON: ++ pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_ON); ++ break; ++ default: ++ break; ++ } ++ return 0; ++} + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/04-omappm-srf-noop.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/04-omappm-srf-noop.eml new file mode 100644 index 0000000000..32d767a342 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/04-omappm-srf-noop.eml @@ -0,0 +1,497 @@ +Adds SRF calls into OMAP PM skeleton layer developed by Paul W. + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> +--- + arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/clockdomain.c | 7 + arch/arm/plat-omap/Kconfig | 3 + arch/arm/plat-omap/Makefile | 4 + arch/arm/plat-omap/omap-pm-srf.c | 367 ++++++++++++++++++++++++++++++++ + include/asm-arm/arch-omap/powerdomain.h | 1 + include/asm-arm/arch-omap/resource.h | 1 + 7 files changed, 383 insertions(+), 1 deletion(-) + +Index: linux-omap-2.6/arch/arm/plat-omap/omap-pm-srf.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/plat-omap/omap-pm-srf.c 2008-08-11 +17:38:37.000000000 +0530 +@@ -0,0 +1,367 @@ ++/* ++ * omap-pm-srf.c - OMAP power management interface implemented ++ * using Shared resource framework ++ * ++ * This code implements the OMAP power management interface to ++ * drivers, CPUIdle, CPUFreq, and DSP Bridge. It is strictly for ++ * debug/demonstration use, as it does nothing but printk() whenever a ++ * function is called (when DEBUG is defined, below) ++ * ++ * Copyright (C) 2008 Texas Instruments, Inc. ++ * Copyright (C) 2008 Nokia Corporation ++ * Paul Walmsley ++ * ++ * Interface developed by (in alphabetical order): ++ * Karthik Dasu, Amish Lakhani, Tony Lindgren, Rajendra Nayak, Sakari ++ * Poussa, Veeramanikandan Raju, Igor Stoppa, Paul Walmsley, Richard ++ * Woodruff ++ * ++ * Interfaces defined by Paul Walmsley ++ * Updated with SRF calls by Rajendra Nayak ++ */ ++ ++#undef DEBUG ++ ++#include <linux/init.h> ++#include <linux/cpufreq.h> ++#include <linux/device.h> ++ ++/* Interface documentation is in asm/arch/omap-pm.h */ ++#include <asm/arch/omap-pm.h> ++ ++#include <asm/arch/powerdomain.h> ++#include <asm/arch/resource.h> ++/* ++#include <asm/arch/tiocp.h> ++*/ ++ ++#define LAT_RES_POSTAMBLE "_latency" ++char latency_res_name[30]; ++/* lat_name_mutex protects latency_res_name*/ ++static DEFINE_MUTEX(lat_name_mutex); ++ ++ ++/** ++ * get_lat_res_name - gets the latency resource name given a power domain name ++ * @pwrdm_name: Name of the power domain. ++ * ++ * Returns a pointer to the latency resource name. ++ */ ++static char *get_lat_res_name(const char *pwrdm_name) ++{ ++ strcpy(latency_res_name, ""); ++ if (!(in_atomic() || irqs_disabled())) ++ mutex_lock(&lat_name_mutex); ++ WARN_ON(strlen(pwrdm_name) + strlen(LAT_RES_POSTAMBLE) > ++ sizeof(latency_res_name)); ++ strcpy(latency_res_name, pwrdm_name); ++ strcat(latency_res_name, LAT_RES_POSTAMBLE); ++ if (!(in_atomic() || irqs_disabled())) ++ mutex_unlock(&lat_name_mutex); ++ return latency_res_name; ++} ++ ++static struct omap_opp *dsp_opps; ++static struct omap_opp *mpu_opps; ++ ++/* ++ * Device-driver-originated constraints (via board-*.c files) ++ */ ++ ++void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) ++{ ++ if (!dev || t < -1) { ++ WARN_ON(1); ++ return; ++ }; ++ ++ if (t == -1) { ++ pr_debug("OMAP PM: remove max MPU wakeup latency constraint: " ++ "dev %s\n", dev_name(dev)); ++ resource_release("mpu_latency", dev); ++ } else { ++ pr_debug("OMAP PM: add max MPU wakeup latency constraint: " ++ "dev %s, t = %ld usec\n", dev_name(dev), t); ++ resource_request("mpu_latency", dev, t); ++ } ++} ++ ++void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) ++{ ++ if (!dev || agent_id != OCP_INITIATOR_AGENT || ++ agent_id != OCP_TARGET_AGENT) { ++ WARN_ON(1); ++ return; ++ }; ++ ++ if (r == 0) ++ pr_debug("OMAP PM: remove min bus tput constraint: " ++ "dev %s for agent_id %d\n", dev_name(dev), agent_id); ++ else ++ pr_debug("OMAP PM: add min bus tput constraint: " ++ "dev %s for agent_id %d: rate %ld KiB\n", ++ dev_name(dev), agent_id, r); ++ ++ /* ++ * This code should model the interconnect and compute the ++ * required clock frequency, convert that to a VDD2 OPP ID, then ++ * set the VDD2 OPP appropriately. ++ * ++ * TI CDP code can call constraint_set here on the VDD2 OPP. ++ */ ++} ++ ++void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t) ++{ ++ /* struct tiocp *tiocp_dev; */ ++ struct powerdomain *pwrdm_dev; ++ char *res_name; ++ ++ if (!dev || t < -1) { ++ WARN_ON(1); ++ return; ++ }; ++ /* Look for the devices Power Domain */ ++ /* TODO: Put this back in once tiocp layer is available ++ tiocp_dev = container_of(dev, struct tiocp, dev); ++ pwrdm_dev = tiocp_dev->pwrdm; ++ */ ++ ++ if (t == -1) { ++ pr_debug("OMAP PM: remove max device latency constraint: " ++ "dev %s\n", dev_name(dev)); ++ res_name = get_lat_res_name(pwrdm_dev->name); ++ resource_release(res_name, dev); ++ } else { ++ pr_debug("OMAP PM: add max device latency constraint: " ++ "dev %s, t = %ld usec\n", dev_name(dev), t); ++ res_name = get_lat_res_name(pwrdm_dev->name); ++ resource_request(res_name, dev, t); ++ } ++ ++ /* ++ * For current Linux, this needs to map the device to a ++ * powerdomain, then go through the list of current max lat ++ * constraints on that powerdomain and find the smallest. If ++ * the latency constraint has changed, the code should ++ * recompute the state to enter for the next powerdomain ++ * state. Conceivably, this code should also determine ++ * whether to actually disable the device clocks or not, ++ * depending on how long it takes to re-enable the clocks. ++ * ++ * TI CDP code can call constraint_set here. ++ */ ++} ++ ++void omap_pm_set_max_sdma_lat(struct device *dev, long t) ++{ ++ if (!dev || t < -1) { ++ WARN_ON(1); ++ return; ++ }; ++ ++ if (t == -1) { ++ pr_debug("OMAP PM: remove max DMA latency constraint: " ++ "dev %s\n", dev_name(dev)); ++ resource_release("core_latency", dev); ++ } else { ++ pr_debug("OMAP PM: add max DMA latency constraint: " ++ "dev %s, t = %ld usec\n", dev_name(dev), t); ++ resource_request("core_latency", dev, t); ++ } ++ ++ /* ++ * For current Linux PM QOS params, this code should scan the ++ * list of maximum CPU and DMA latencies and select the ++ * smallest, then set cpu_dma_latency pm_qos_param ++ * accordingly. ++ * ++ * For future Linux PM QOS params, with separate CPU and DMA ++ * latency params, this code should just set the dma_latency param. ++ * ++ * TI CDP code can call constraint_set here. ++ */ ++ ++} ++ ++ ++/* ++ * DSP Bridge-specific constraints ++ */ ++ ++const struct omap_opp *omap_pm_dsp_get_opp_table(void) ++{ ++ pr_debug("OMAP PM: DSP request for OPP table\n"); ++ ++ /* ++ * Return DSP frequency table here: The final item in the ++ * array should have .rate = .opp_id = 0. ++ */ ++ ++ return NULL; ++} ++ ++void omap_pm_dsp_set_min_opp(u8 opp_id) ++{ ++ if (opp_id == 0) { ++ WARN_ON(1); ++ return; ++ } ++ ++ pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id); ++ ++ /* ++ * ++ * For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we ++ * can just test to see which is higher, the CPU's desired OPP ++ * ID or the DSP's desired OPP ID, and use whichever is ++ * highest. ++ * ++ * In CDP12.14+, the VDD1 OPP custom clock that controls the DSP ++ * rate is keyed on MPU speed, not the OPP ID. So we need to ++ * map the OPP ID to the MPU speed for use with clk_set_rate() ++ * if it is higher than the current OPP clock rate. ++ * ++ */ ++} ++ ++ ++u8 omap_pm_dsp_get_opp(void) ++{ ++ pr_debug("OMAP PM: DSP requests current DSP OPP ID\n"); ++ ++ /* ++ * For l-o dev tree, call clk_get_rate() on VDD1 OPP clock ++ * ++ * CDP12.14+: ++ * Call clk_get_rate() on the OPP custom clock, map that to an ++ * OPP ID using the tables defined in board-*.c/chip-*.c files. ++ */ ++ ++ return 0; ++} ++ ++/* ++ * CPUFreq-originated constraint ++ * ++ * In the future, this should be handled by custom OPP clocktype ++ * functions. ++ */ ++ ++struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void) ++{ ++ pr_debug("OMAP PM: CPUFreq request for frequency table\n"); ++ ++ /* ++ * Return CPUFreq frequency table here: loop over ++ * all VDD1 clkrates, pull out the mpu_ck frequencies, build ++ * table ++ */ ++ ++ return NULL; ++} ++ ++void omap_pm_cpu_set_freq(unsigned long f) ++{ ++ if (f == 0) { ++ WARN_ON(1); ++ return; ++ } ++ ++ pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n", ++ f); ++ ++ /* ++ * For l-o dev tree, determine whether MPU freq or DSP OPP id ++ * freq is higher. Find the OPP ID corresponding to the ++ * higher frequency. Call clk_round_rate() and clk_set_rate() ++ * on the OPP custom clock. ++ * ++ * CDP should just be able to set the VDD1 OPP clock rate here. ++ */ ++} ++ ++unsigned long omap_pm_cpu_get_freq(void) ++{ ++ pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n"); ++ ++ /* ++ * Call clk_get_rate() on the mpu_ck. ++ */ ++ ++ return 0; ++} ++ ++struct device omap_pm_dev; ++ ++/* ++ * Powerdomain usecounting hooks ++ */ ++ ++void omap_pm_pwrdm_active(struct powerdomain *pwrdm) ++{ ++ char *res_name; ++ ++ if (!pwrdm) { ++ WARN_ON(1); ++ return; ++ }; ++ ++ if (!strcmp(pwrdm->name, "wkup_pwrdm") || ++ !strcmp(pwrdm->name, "core_pwrdm")) ++ return; ++ ++ pr_debug("OMAP PM: powerdomain %s is becoming active\n", pwrdm->name); ++ ++ res_name = get_lat_res_name(pwrdm->name); ++ /* Request for a zero latency which puts the Power Domain in ON state*/ ++ resource_request(res_name, &omap_pm_dev, 0); ++ return; ++} ++ ++void omap_pm_pwrdm_inactive(struct powerdomain *pwrdm) ++{ ++ char *res_name; ++ ++ if (!pwrdm) { ++ WARN_ON(1); ++ return; ++ }; ++ ++ if (!strcmp(pwrdm->name, "wkup_pwrdm") || ++ !strcmp(pwrdm->name, "core_pwrdm")) ++ return; ++ ++ pr_debug("OMAP PM: powerdomain %s is becoming inactive\n", ++ pwrdm->name); ++ ++ res_name = get_lat_res_name(pwrdm->name); ++ /* Release the latency requested */ ++ resource_release(res_name, &omap_pm_dev); ++ return; ++} ++ ++/* ++ * Should be called before clk framework since clk fw will call ++ * omap_pm_pwrdm_{in,}active() ++ */ ++int __init omap_pm_if_early_init(void) ++{ ++ return 0; ++} ++ ++/* Must be called after clock framework is initialized */ ++int __init omap_pm_if_init(struct omap_opp *mpu_opp_table, ++ struct omap_opp *dsp_opp_table) ++{ ++ mpu_opps = mpu_opp_table; ++ dsp_opps = dsp_opp_table; ++ resource_init(resources_omap); ++ return 0; ++} ++ ++void omap_pm_if_exit(void) ++{ ++ /* Deallocate CPUFreq frequency table here */ ++} ++ +Index: linux-omap-2.6/arch/arm/mach-omap2/clockdomain.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/clockdomain.c 2008-08-11 +17:12:19.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/clockdomain.c 2008-08-11 +17:14:31.000000000 +0530 +@@ -35,6 +35,7 @@ + + #include <asm/arch/powerdomain.h> + #include <asm/arch/clockdomain.h> ++#include <asm/arch/omap-pm.h> + + /* clkdm_list contains all registered struct clockdomains */ + static LIST_HEAD(clkdm_list); +@@ -561,6 +562,9 @@ int omap2_clkdm_clk_enable(struct clockd + else + omap2_clkdm_wakeup(clkdm); + ++ /*Hook to inform the OMAP PM layer that the pwrdm has become active */ ++ omap_pm_pwrdm_active(clkdm->pwrdm.ptr); ++ + return 0; + } + +@@ -612,6 +616,9 @@ int omap2_clkdm_clk_disable(struct clock + else + omap2_clkdm_sleep(clkdm); + ++ /*Hook to inform the OMAP PM layer that the pwrdm has become inactive */ ++ omap_pm_pwrdm_inactive(clkdm->pwrdm.ptr); ++ + return 0; + } + +Index: linux-omap-2.6/include/asm-arm/arch-omap/powerdomain.h +=================================================================== +--- linux-omap-2.6.orig/include/asm-arm/arch-omap/powerdomain.h 2008-08-11 +17:12:19.000000000 +0530 ++++ linux-omap-2.6/include/asm-arm/arch-omap/powerdomain.h 2008-08-11 +17:14:31.000000000 +0530 +@@ -148,6 +148,7 @@ int pwrdm_read_next_pwrst(struct powerdo + int pwrdm_read_pwrst(struct powerdomain *pwrdm); + int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); + int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); ++int pwrdm_read_pwrst(struct powerdomain *pwrdm); + + int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); + int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); +Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-08-11 +17:12:19.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-08-11 17:14:31.000000000 ++0530 +@@ -34,6 +34,7 @@ obj-$(CONFIG_OMAP_SMARTREFLEX) += smart + # Clock framework + obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o + obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o ++obj-$(CONFIG_OMAP_PM_SRF) += resource34xx.o + + # DSP + obj-$(CONFIG_OMAP_MMU_FWK) += mmu_mach.o +Index: linux-omap-2.6/arch/arm/plat-omap/Kconfig +=================================================================== +--- linux-omap-2.6.orig/arch/arm/plat-omap/Kconfig 2008-08-11 +17:12:25.000000000 +0530 ++++ linux-omap-2.6/arch/arm/plat-omap/Kconfig 2008-08-11 17:14:31.000000000 +0530 +@@ -258,6 +258,9 @@ config OMAP_PM_NONE + config OMAP_PM_NOOP + bool "No-op/debug PM layer" + ++config OMAP_PM_SRF ++ bool "PM layer implemented using SRF" ++ + endchoice + + endif +Index: linux-omap-2.6/arch/arm/plat-omap/Makefile +=================================================================== +--- linux-omap-2.6.orig/arch/arm/plat-omap/Makefile 2008-08-11 +17:12:25.000000000 +0530 ++++ linux-omap-2.6/arch/arm/plat-omap/Makefile 2008-08-11 17:14:31.000000000 +0530 +@@ -29,4 +29,6 @@ obj-$(CONFIG_OMAP_MMU_FWK) += mmu.o + # OMAP mailbox framework + obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o + +-obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o +\ No newline at end of file ++obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o ++obj-$(CONFIG_OMAP_PM_SRF) += omap-pm-srf.o \ ++ resource.o +Index: linux-omap-2.6/include/asm-arm/arch-omap/resource.h +=================================================================== +--- linux-omap-2.6.orig/include/asm-arm/arch-omap/resource.h 2008-08-11 +17:12:30.000000000 +0530 ++++ linux-omap-2.6/include/asm-arm/arch-omap/resource.h 2008-08-11 +17:14:31.000000000 +0530 +@@ -85,6 +85,7 @@ struct users_list { + u8 usage; + }; + ++extern struct shared_resource *resources_omap[]; + /* Shared resource Framework API's */ + void resource_init(struct shared_resource **resources); + int resource_register(struct shared_resource *res); + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/04-use-pcd.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/04-use-pcd.diff new file mode 100644 index 0000000000..bdf8ab5f0b --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/04-use-pcd.diff @@ -0,0 +1,28 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sun, 6 Jul 2008 13:22:54 +0000 (+0100) +Subject: omapfb: use PCD if set in panel config +X-Git-Tag: beagle-5 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=c8060d36ae156771f00a7a27cabf1b4435c378bd + +omapfb: use PCD if set in panel config +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 3b36227..4e1a8e3 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -798,7 +798,13 @@ static void set_lcd_timings(void) + l |= panel->acb & 0xff; + dispc_write_reg(DISPC_POL_FREQ, l); + +- calc_ck_div(is_tft, panel->pixel_clock * 1000, &lck_div, &pck_div); ++ if (panel->pcd) { ++ pck_div = panel->pcd; ++ lck_div = 1; ++ } else { ++ calc_ck_div(is_tft, panel->pixel_clock * 1000, ++ &lck_div, &pck_div); ++ } + + l = dispc_read_reg(DISPC_DIVISOR); + l &= ~(FLD_MASK(16, 8) | FLD_MASK(0, 8)); diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/05-fix-display-panning.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/05-fix-display-panning.diff new file mode 100644 index 0000000000..d3c9fffcda --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/05-fix-display-panning.diff @@ -0,0 +1,45 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Mon, 7 Jul 2008 00:13:00 +0000 (+0100) +Subject: omapfb: fix display panning +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=9fec252c96b0e69bcef0afd9cb9dd72b7179c239 + +omapfb: fix display panning +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 4e1a8e3..c17371c 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -435,6 +435,8 @@ static inline int _setup_plane(int plane, int channel_out, + + dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1); + ++ MOD_REG_FLD(DISPC_CONTROL, 1<<5, 1<<5); ++ + return height * screen_width * bpp / 8; + } + +diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c +index 1166a01..3e4959e 100644 +--- a/drivers/video/omap/omapfb_main.c ++++ b/drivers/video/omap/omapfb_main.c +@@ -206,8 +206,8 @@ static int ctrl_change_mode(struct fb_info *fbi) + struct omapfb_device *fbdev = plane->fbdev; + struct fb_var_screeninfo *var = &fbi->var; + +- offset = var->yoffset * fbi->fix.line_length + +- var->xoffset * var->bits_per_pixel / 8; ++ offset = (var->yoffset * var->xres_virtual + var->xoffset) * ++ var->bits_per_pixel / 8; + + if (fbdev->ctrl->sync) + fbdev->ctrl->sync(); +@@ -423,6 +423,8 @@ static void set_fb_fix(struct fb_info *fbi) + } + fix->accel = FB_ACCEL_OMAP1610; + fix->line_length = var->xres_virtual * bpp / 8; ++ fix->xpanstep = 1; ++ fix->ypanstep = 1; + } + + static int set_color_mode(struct omapfb_plane_struct *plane, diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/05-omappm-virtualclocks.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/05-omappm-virtualclocks.eml new file mode 100644 index 0000000000..0aaed7b91c --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/05-omappm-virtualclocks.eml @@ -0,0 +1,456 @@ +The patch defines virtual nodes for VDD1 and VDD2 + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> +--- + arch/arm/mach-omap2/board-3430sdp.c | 38 +++++ + arch/arm/mach-omap2/clock34xx.c | 206 +++++++++++++++++++++++++----- + arch/arm/mach-omap2/clock34xx.h | 29 ++++ + include/asm-arm/arch-omap/board-3430sdp.h | 35 +++++ + include/asm-arm/arch-omap/clock.h | 8 + + 5 files changed, 287 insertions(+), 29 deletions(-) + +Index: linux-omap-2.6/arch/arm/mach-omap2/clock34xx.h +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/clock34xx.h 2008-08-06 +14:55:12.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/clock34xx.h 2008-08-07 +15:07:19.000000000 +0530 +@@ -36,6 +36,14 @@ static int omap3_noncore_dpll_enable(str + static void omap3_noncore_dpll_disable(struct clk *clk); + static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); + static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); ++static void omap3_table_recalc(struct clk *clk); ++static long omap3_round_to_table_rate(struct clk *clk, unsigned long rate); ++static int omap3_select_table_rate(struct clk *clk, unsigned long rate); ++ ++extern struct vdd_prcm_config vdd1_rate_table[]; ++extern struct vdd_prcm_config vdd2_rate_table[]; ++extern struct vdd_prcm_config iva2_rate_table[]; ++ + + /* Maximum DPLL multiplier, divider values for OMAP3 */ + #define OMAP3_MAX_DPLL_MULT 2048 +@@ -3064,6 +3072,24 @@ static struct clk wdt1_fck = { + .recalc = &followparent_recalc, + }; + ++static struct clk virt_vdd1_prcm_set = { ++ .name = "virt_vdd1_prcm_set", ++ .flags = CLOCK_IN_OMAP343X | VIRTUAL_CLOCK | ALWAYS_ENABLED, ++ .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ ++ .recalc = &omap3_table_recalc, /*sets are keyed on mpu rate */ ++ .set_rate = &omap3_select_table_rate, ++ .round_rate = &omap3_round_to_table_rate, ++}; ++ ++static struct clk virt_vdd2_prcm_set = { ++ .name = "virt_vdd2_prcm_set", ++ .flags = CLOCK_IN_OMAP343X | VIRTUAL_CLOCK | ALWAYS_ENABLED, ++ .parent = &core_ck, ++ .recalc = &omap3_table_recalc, ++ .set_rate = &omap3_select_table_rate, ++ .round_rate = &omap3_round_to_table_rate, ++}; ++ + static struct clk *onchip_34xx_clks[] __initdata = { + &omap_32k_fck, + &virt_12m_ck, +@@ -3276,6 +3302,9 @@ static struct clk *onchip_34xx_clks[] __ + &secure_32k_fck, + &gpt12_fck, + &wdt1_fck, ++ /* virtual group clock */ ++ &virt_vdd1_prcm_set, ++ &virt_vdd2_prcm_set, + }; + + #endif +Index: linux-omap-2.6/arch/arm/mach-omap2/clock34xx.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/clock34xx.c 2008-08-07 +14:34:23.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/clock34xx.c 2008-08-07 +15:07:19.000000000 +0530 +@@ -25,6 +25,7 @@ + #include <linux/clk.h> + #include <linux/io.h> + #include <linux/limits.h> ++#include <linux/err.h> + + #include <asm/arch/clock.h> + #include <asm/arch/sram.h> +@@ -45,6 +46,32 @@ + + #define MAX_DPLL_WAIT_TRIES 1000000 + ++struct vdd_prcm_config *curr_vdd1_prcm_set; ++struct vdd_prcm_config *curr_vdd2_prcm_set; ++static struct clk *dpll1_clk, *dpll2_clk, *dpll3_clk; ++ ++#ifndef CONFIG_CPU_FREQ ++static unsigned long compute_lpj(unsigned long ref, u_int div, u_int mult) ++{ ++ unsigned long new_jiffy_l, new_jiffy_h; ++ ++ /* ++ * Recalculate loops_per_jiffy. We do it this way to ++ * avoid math overflow on 32-bit machines. Maybe we ++ * should make this architecture dependent? If you have ++ * a better way of doing this, please replace! ++ * ++ * new = old * mult / div ++ */ ++ new_jiffy_h = ref / div; ++ new_jiffy_l = (ref % div) / 100; ++ new_jiffy_h *= mult; ++ new_jiffy_l = new_jiffy_l * mult / div; ++ ++ return new_jiffy_h + new_jiffy_l * 100; ++} ++#endif ++ + /** + * omap3_dpll_recalc - recalculate DPLL rate + * @clk: DPLL struct clk +@@ -644,15 +671,6 @@ void omap2_clk_prepare_for_reboot(void) + */ + static int __init omap2_clk_arch_init(void) + { +- if (!mpurate) +- return -EINVAL; +- +- /* REVISIT: not yet ready for 343x */ +-#if 0 +- if (omap2_select_table_rate(&virt_prcm_set, mpurate)) +- printk(KERN_ERR "Could not find matching MPU rate\n"); +-#endif +- + recalculate_root_clocks(); + + printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): " +@@ -670,6 +688,9 @@ int __init omap2_clk_init(void) + struct clk **clkp; + /* u32 clkrate; */ + u32 cpu_clkflg; ++ unsigned long mpu_speed, core_speed; ++ struct vdd_prcm_config *prcm_vdd; ++ + + /* REVISIT: Ultimately this will be used for multiboot */ + #if 0 +@@ -712,22 +733,31 @@ int __init omap2_clk_init(void) + } + } + +- /* REVISIT: Not yet ready for OMAP3 */ +-#if 0 +- /* Check the MPU rate set by bootloader */ +- clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); +- for (prcm = rate_table; prcm->mpu_speed; prcm++) { +- if (!(prcm->flags & cpu_mask)) +- continue; +- if (prcm->xtal_speed != sys_ck.rate) +- continue; +- if (prcm->dpll_speed <= clkrate) +- break; ++ recalculate_root_clocks(); ++ ++ dpll1_clk = clk_get(NULL, "dpll1_ck"); ++ dpll2_clk = clk_get(NULL, "dpll2_ck"); ++ dpll3_clk = clk_get(NULL, "dpll3_ck"); ++ ++#ifdef CONFIG_MACH_OMAP_3430SDP ++ mpu_speed = dpll1_clk->rate; ++ prcm_vdd = vdd1_rate_table + MAX_VDD1_OPP; ++ for (; prcm_vdd->speed; prcm_vdd--) { ++ if (prcm_vdd->speed <= mpu_speed) { ++ curr_vdd1_prcm_set = prcm_vdd; ++ break; ++ } + } +- curr_prcm_set = prcm; +-#endif + +- recalculate_root_clocks(); ++ core_speed = dpll3_clk->rate; ++ prcm_vdd = vdd2_rate_table + MAX_VDD2_OPP; ++ for (; prcm_vdd->speed; prcm_vdd--) { ++ if (prcm_vdd->speed <= core_speed) { ++ curr_vdd2_prcm_set = prcm_vdd; ++ break; ++ } ++ } ++#endif + + printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): " + "%ld.%01ld/%ld/%ld MHz\n", +@@ -740,13 +770,131 @@ int __init omap2_clk_init(void) + */ + clk_enable_init_clocks(); + +- /* Avoid sleeping during omap2_clk_prepare_for_reboot() */ +- /* REVISIT: not yet ready for 343x */ +-#if 0 +- vclk = clk_get(NULL, "virt_prcm_set"); +- sclk = clk_get(NULL, "sys_ck"); +-#endif + return 0; + } + ++inline unsigned int get_freq(struct vdd_prcm_config *opp_freq_table, ++ unsigned long opp) ++{ ++ struct vdd_prcm_config *prcm_config; ++ prcm_config = opp_freq_table; ++ ++ for (; prcm_config->opp; prcm_config--) ++ if (prcm_config->opp == opp) ++ return prcm_config->speed; ++ return 0; ++} ++ ++inline unsigned int get_opp(struct vdd_prcm_config *opp_freq_table, ++ unsigned long freq) ++{ ++ struct vdd_prcm_config *prcm_config; ++ prcm_config = opp_freq_table; ++ ++ if (prcm_config->speed <= freq) ++ return prcm_config->opp; /* Return the Highest OPP */ ++ for (; prcm_config->speed; prcm_config--) { ++ if (prcm_config->speed < freq) ++ return (prcm_config+1)->opp; ++ else if (prcm_config->speed == freq) ++ return prcm_config->opp; ++ } ++ /* Return the least OPP */ ++ return (prcm_config+1)->opp; ++} ++ ++#ifdef CONFIG_MACH_OMAP_3430SDP ++static void omap3_table_recalc(struct clk *clk) ++{ ++ if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set)) ++ return; ++ ++ if ((curr_vdd1_prcm_set) && (clk == &virt_vdd1_prcm_set)) ++ clk->rate = curr_vdd1_prcm_set->speed; ++ else if ((curr_vdd2_prcm_set) && (clk == &virt_vdd2_prcm_set)) ++ clk->rate = curr_vdd2_prcm_set->speed; ++ pr_debug("CLK RATE:%lu\n", clk->rate); ++} ++ ++static long omap3_round_to_table_rate(struct clk *clk, unsigned long rate) ++{ ++ struct vdd_prcm_config *ptr; ++ long highest_rate; ++ ++ if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set)) ++ return -EINVAL; ++ ++ highest_rate = -EINVAL; ++ ++ if (clk == &virt_vdd1_prcm_set) ++ ptr = vdd1_rate_table + MAX_VDD1_OPP; ++ else ++ ptr = vdd2_rate_table + MAX_VDD2_OPP; ++ ++ for (; ptr->speed; ptr--) { ++ highest_rate = ptr->speed; ++ pr_debug("Highest speed : %lu, rate: %lu\n", highest_rate, ++ rate); ++ if (ptr->speed <= rate) ++ break; ++ } ++ return highest_rate; ++} ++ ++static int omap3_select_table_rate(struct clk *clk, unsigned long rate) ++{ ++ struct vdd_prcm_config *prcm_vdd; ++ unsigned long found_speed = 0, curr_mpu_speed; ++ int index; ++ ++ if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set)) ++ return -EINVAL; ++ ++ if (clk == &virt_vdd1_prcm_set) { ++ prcm_vdd = vdd1_rate_table + MAX_VDD1_OPP; ++ index = MAX_VDD1_OPP; ++ } else if (clk == &virt_vdd2_prcm_set) { ++ prcm_vdd = vdd2_rate_table + MAX_VDD2_OPP; ++ index = MAX_VDD2_OPP; ++ } ++ ++ for (; prcm_vdd->speed; prcm_vdd--, index--) { ++ if (prcm_vdd->speed <= rate) { ++ found_speed = prcm_vdd->speed; ++ pr_debug("Found speed = %lu\n", found_speed); ++ break; ++ } ++ } ++ ++ if (!found_speed) { ++ printk(KERN_INFO "Could not set table rate to %luMHz\n", ++ rate / 1000000); ++ return -EINVAL; ++ } ++ ++ ++ if (clk == &virt_vdd1_prcm_set) { ++ curr_mpu_speed = curr_vdd1_prcm_set->speed; ++ clk_set_rate(dpll1_clk, prcm_vdd->speed); ++ clk_set_rate(dpll2_clk, iva2_rate_table[index].speed); ++ curr_vdd1_prcm_set = prcm_vdd; ++#ifndef CONFIG_CPU_FREQ ++ /*Update loops_per_jiffy if processor speed is being changed*/ ++ loops_per_jiffy = compute_lpj(loops_per_jiffy, ++ curr_mpu_speed/1000, found_speed/1000); + #endif ++ } else { ++ clk_set_rate(dpll3_clk, prcm_vdd->speed); ++ curr_vdd2_prcm_set = prcm_vdd; ++ } ++ return 0; ++} ++#else /* CONFIG_MACH_OMAP_3430SDP */ ++static void omap3_table_recalc(struct clk *clk) {} ++static long omap3_round_to_table_rate(struct clk *clk, unsigned long rate) ++{ return 0; } ++static int omap3_select_table_rate(struct clk *clk, unsigned long rate) ++{ return 0; } ++#endif /* CONFIG_MACH_OMAP_3430SDP */ ++ ++#endif /* CONFIG_ARCH_OMAP3 */ +Index: linux-omap-2.6/include/asm-arm/arch-omap/clock.h +=================================================================== +--- linux-omap-2.6.orig/include/asm-arm/arch-omap/clock.h 2008-08-07 +14:34:23.000000000 +0530 ++++ linux-omap-2.6/include/asm-arm/arch-omap/clock.h 2008-08-07 +15:07:19.000000000 +0530 +@@ -126,6 +126,14 @@ struct clk_functions { + #endif + }; + ++#ifdef CONFIG_ARCH_OMAP3 ++struct vdd_prcm_config { ++ unsigned long speed; ++ unsigned long opp; ++ unsigned long flags; ++}; ++#endif ++ + extern unsigned int mpurate; + + extern int clk_init(struct clk_functions *custom_clocks); +Index: linux-omap-2.6/arch/arm/mach-omap2/board-3430sdp.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/board-3430sdp.c 2008-08-06 +14:55:12.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/board-3430sdp.c 2008-08-07 +15:07:50.000000000 +0530 +@@ -40,6 +40,7 @@ + #include <asm/arch/keypad.h> + #include <asm/arch/dma.h> + #include <asm/arch/gpmc.h> ++#include <asm/arch/clock.h> + #include <linux/i2c/twl4030-rtc.h> + + #include <asm/io.h> +@@ -53,6 +54,43 @@ + #define ENABLE_VAUX3_DEDICATED 0x03 + #define ENABLE_VAUX3_DEV_GRP 0x20 + ++struct vdd_prcm_config vdd1_rate_table[] = { ++ {0, 0, 0}, ++ /*OPP1*/ ++ {S125M, VDD1_OPP1, 0}, ++ /*OPP2*/ ++ {S250M, VDD1_OPP2, 0}, ++ /*OPP3*/ ++ {S500M, VDD1_OPP3, 0}, ++ /*OPP4*/ ++ {S550M, VDD1_OPP4, 0}, ++ /*OPP5*/ ++ {S600M, VDD1_OPP5, 0}, ++}; ++ ++struct vdd_prcm_config vdd2_rate_table[] = { ++ {0, 0, 0}, ++ /*OPP1*/ ++ {0, VDD2_OPP1, 0}, ++ /*OPP2*/ ++ {S83M, VDD2_OPP2, 0}, ++ /*OPP3*/ ++ {S166M, VDD2_OPP3, 0}, ++}; ++ ++struct vdd_prcm_config iva2_rate_table[] = { ++ {0, 0, 0}, ++ /*OPP1*/ ++ {S90M, VDD1_OPP1, 0}, ++ /*OPP2*/ ++ {S180M, VDD1_OPP2, 0}, ++ /*OPP3*/ ++ {S360M, VDD1_OPP3, 0}, ++ /*OPP4*/ ++ {S400M, VDD1_OPP4, 0}, ++ /*OPP5*/ ++ {S430M, VDD1_OPP5, 0}, ++}; + + #define TWL4030_MSECURE_GPIO 22 + +Index: linux-omap-2.6/include/asm-arm/arch-omap/board-3430sdp.h +=================================================================== +--- linux-omap-2.6.orig/include/asm-arm/arch-omap/board-3430sdp.h 2008-08-06 +14:55:22.000000000 +0530 ++++ linux-omap-2.6/include/asm-arm/arch-omap/board-3430sdp.h 2008-08-07 +15:07:19.000000000 +0530 +@@ -68,5 +68,40 @@ extern void twl4030_bci_battery_init(voi + #define FLASH_SIZE_SDPV1 SZ_64M + #define FLASH_SIZE_SDPV2 SZ_128M + ++/* MPU speeds */ ++#define S600M 600000000 ++#define S550M 550000000 ++#define S500M 500000000 ++#define S250M 250000000 ++#define S125M 125000000 ++ ++/* IVA speeds */ ++#define S430M 430000000 ++#define S400M 400000000 ++#define S360M 360000000 ++#define S180M 180000000 ++#define S90M 90000000 ++ ++/* L3 speeds */ ++#define S83M 83000000 ++#define S166M 166000000 ++ ++/* VDD1 OPPS */ ++#define VDD1_OPP1 0x1 ++#define VDD1_OPP2 0x2 ++#define VDD1_OPP3 0x3 ++#define VDD1_OPP4 0x4 ++#define VDD1_OPP5 0x5 ++ ++/* VDD2 OPPS */ ++#define VDD2_OPP1 0x1 ++#define VDD2_OPP2 0x2 ++#define VDD2_OPP3 0x3 ++ ++#define MIN_VDD1_OPP VDD1_OPP1 ++#define MAX_VDD1_OPP VDD1_OPP5 ++#define MIN_VDD2_OPP VDD2_OPP1 ++#define MAX_VDD2_OPP VDD2_OPP3 ++ + #endif /* __ASM_ARCH_OMAP_3430SDP_H */ + + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/06-ensure-fclk.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/06-ensure-fclk.diff new file mode 100644 index 0000000000..79871a7208 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/06-ensure-fclk.diff @@ -0,0 +1,31 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Mon, 7 Jul 2008 23:59:08 +0000 (+0100) +Subject: omapfb: ensure fck/lcd < 173MHz +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=0523ece1bad659c48c66aea364d83f7490e7e5ae + +omapfb: ensure fck/lcd < 173MHz +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index c17371c..85d6cad 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -738,14 +738,16 @@ static void setup_color_conv_coef(void) + MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range); + } + ++#define MAX_FCK_LCD 173000000 ++ + static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div) + { + unsigned long fck, lck; + +- *lck_div = 1; + pck = max(1, pck); + fck = clk_get_rate(dispc.dss1_fck); +- lck = fck; ++ *lck_div = (fck + MAX_FCK_LCD - 1) / MAX_FCK_LCD; ++ lck = fck / *lck_div; + *pck_div = (lck + pck - 1) / pck; + if (is_tft) + *pck_div = max(2, *pck_div); diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/06-omappm-opp-resource-modeling.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/06-omappm-opp-resource-modeling.eml new file mode 100644 index 0000000000..69ed0f748c --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/06-omappm-opp-resource-modeling.eml @@ -0,0 +1,228 @@ +Adds OPP/Frequency resources to SRF + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> +--- + arch/arm/mach-omap2/resource34xx.c | 101 +++++++++++++++++++++++++++++++++++++ + arch/arm/mach-omap2/resource34xx.h | 74 +++++++++++++++++++++++++++ + 2 files changed, 175 insertions(+) + +Index: linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/resource34xx.c 2008-08-07 +15:07:08.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c 2008-08-07 +15:09:01.000000000 +0530 +@@ -146,3 +146,104 @@ int set_pd_latency(struct shared_resourc + } + return 0; + } ++ ++static struct clk *vdd1_clk; ++static struct clk *vdd2_clk; ++static struct device dummy_srf_dev; ++ ++/** ++ * init_opp - Initialize the OPP resource ++ */ ++void init_opp(struct shared_resource *resp) ++{ ++ resp->no_of_users = 0; ++ /* Initialize the current level of the OPP resource ++ * to the opp set by u-boot. ++ */ ++ if (strcmp(resp->name, "vdd1_opp") == 0) { ++ resp->curr_level = curr_vdd1_prcm_set->opp; ++ vdd1_clk = clk_get(NULL, "virt_vdd1_prcm_set"); ++ } else if (strcmp(resp->name, "vdd2_opp") == 0) { ++ resp->curr_level = curr_vdd2_prcm_set->opp; ++ vdd2_clk = clk_get(NULL, "virt_vdd2_prcm_set"); ++ } ++ return; ++} ++ ++int set_opp(struct shared_resource *resp, u32 target_level) ++{ ++#ifdef CONFIG_MACH_OMAP_3430SDP ++ unsigned long mpu_freq; ++ if (strcmp(resp->name, "vdd1_opp") == 0) { ++ mpu_freq = get_freq(vdd1_rate_table + MAX_VDD1_OPP, ++ target_level); ++ clk_set_rate(vdd1_clk, mpu_freq); ++ resp->curr_level = curr_vdd1_prcm_set->opp; ++ } else if (strcmp(resp->name, "vdd2_opp") == 0) { ++ /* Not supported yet */ ++ } ++#endif ++ return 0; ++} ++ ++/** ++ * validate_opp - Validates if valid VDD1 OPP's are passed as the ++ * target_level. ++ * VDD2 OPP levels are passed as L3 throughput, which are then mapped ++ * to an appropriate OPP. ++ */ ++int validate_opp(struct shared_resource *resp, u32 target_level) ++{ ++ return 0; ++} ++ ++/** ++ * init_freq - Initialize the frequency resource. ++ */ ++void init_freq(struct shared_resource *resp) ++{ ++#ifdef CONFIG_MACH_OMAP_3430SDP ++ char *linked_res_name; ++ resp->no_of_users = 0; ++ ++ linked_res_name = (char *)resp->resource_data; ++ /* Initialize the current level of the Freq resource ++ * to the frequency set by u-boot. ++ */ ++ if (strcmp(resp->name, "mpu_freq") == 0) ++ /* MPU freq in Mhz */ ++ resp->curr_level = curr_vdd1_prcm_set->speed; ++ else if (strcmp(resp->name, "dsp_freq") == 0) ++ /* DSP freq in Mhz */ ++ resp->curr_level = get_freq(iva2_rate_table + MAX_VDD2_OPP, ++ curr_vdd1_prcm_set->opp); ++#endif ++ return; ++} ++ ++int set_freq(struct shared_resource *resp, u32 target_level) ++{ ++#ifdef CONFIG_MACH_OMAP_3430SDP ++ unsigned int vdd1_opp; ++ ++ if (strcmp(resp->name, "mpu_freq") == 0) ++ vdd1_opp = get_opp(vdd1_rate_table + MAX_VDD1_OPP, ++ target_level); ++ else if (strcmp(resp->name, "dsp_freq") == 0) ++ vdd1_opp = get_opp(iva2_rate_table + MAX_VDD1_OPP, ++ target_level); ++ ++ if (vdd1_opp == MIN_VDD1_OPP) ++ resource_release("vdd1_opp", &dummy_srf_dev); ++ else ++ resource_request("vdd1_opp", &dummy_srf_dev, vdd1_opp); ++ ++ resp->curr_level = target_level; ++#endif ++ return 0; ++} ++ ++int validate_freq(struct shared_resource *resp, u32 target_level) ++{ ++ return 0; ++} +Index: linux-omap-2.6/arch/arm/mach-omap2/resource34xx.h +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/resource34xx.h 2008-08-07 +15:07:02.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/resource34xx.h 2008-08-07 +15:31:42.000000000 +0530 +@@ -22,8 +22,17 @@ + #define __ARCH_ARM_MACH_OMAP2_RESOURCE_H + + #include <asm/arch/resource.h> ++#include <linux/clk.h> ++#include <asm/arch/clock.h> + #include <asm/arch/powerdomain.h> + ++extern struct vdd_prcm_config *curr_vdd1_prcm_set; ++extern struct vdd_prcm_config *curr_vdd2_prcm_set; ++extern unsigned int get_freq(struct vdd_prcm_config *, unsigned long); ++extern unsigned int get_opp(struct vdd_prcm_config *, unsigned long); ++extern struct vdd_prcm_config vdd1_rate_table[]; ++extern struct vdd_prcm_config vdd2_rate_table[]; ++extern struct vdd_prcm_config iva2_rate_table[]; + /** + * mpu_latency/core_latency are used to control the cpuidle C state. + */ +@@ -207,6 +216,66 @@ static struct shared_resource emu_pwrdm_ + .ops = &pd_lat_res_ops, + }; + ++void init_opp(struct shared_resource *resp); ++int set_opp(struct shared_resource *resp, u32 target_level); ++int validate_opp(struct shared_resource *resp, u32 target_level); ++void init_freq(struct shared_resource *resp); ++int set_freq(struct shared_resource *resp, u32 target_level); ++int validate_freq(struct shared_resource *resp, u32 target_level); ++ ++struct bus_throughput_db { ++ /* Throughput for each OPP/Freq of the bus */ ++ unsigned long throughput[3]; ++}; ++ ++static struct shared_resource_ops opp_res_ops = { ++ .init = init_opp, ++ .change_level = set_opp, ++ .validate_level = validate_opp, ++}; ++ ++static struct shared_resource vdd1_opp = { ++ .name = "vdd1_opp", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .ops = &opp_res_ops, ++}; ++ ++/* Throughput in KiB/s */ ++static struct bus_throughput_db l3_throughput_db = { ++ .throughput[0] = 0, ++ .throughput[1] = 100, ++ .throughput[2] = 250, ++}; ++ ++static struct shared_resource vdd2_opp = { ++ .name = "vdd2_opp", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .resource_data = &l3_throughput_db, ++ .ops = &opp_res_ops, ++}; ++ ++static char linked_res[] = "vdd1_opp"; ++ ++static struct shared_resource_ops freq_res_ops = { ++ .init = init_freq, ++ .change_level = set_freq, ++ .validate_level = validate_freq, ++}; ++ ++static struct shared_resource mpu_freq = { ++ .name = "mpu_freq", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .resource_data = &linked_res, ++ .ops = &freq_res_ops, ++}; ++ ++static struct shared_resource dsp_freq = { ++ .name = "dsp_freq", ++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), ++ .resource_data = &linked_res, ++ .ops = &freq_res_ops, ++}; ++ + struct shared_resource *resources_omap[] __initdata = { + &mpu_latency, + &core_latency, +@@ -220,6 +289,11 @@ struct shared_resource *resources_omap[] + &neon_pwrdm_latency, + &usbhost_pwrdm_latency, + &emu_pwrdm_latency, ++ /* OPP/frequency resources */ ++ &vdd1_opp, ++ &vdd2_opp, ++ &mpu_freq, ++ &dsp_freq, + NULL + }; + + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/07-omappm-srf-updates.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/07-omappm-srf-updates.eml new file mode 100644 index 0000000000..735e991298 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/07-omappm-srf-updates.eml @@ -0,0 +1,173 @@ +Updates the omap-pm apis with calls to SRF implementation + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> +--- + arch/arm/plat-omap/omap-pm-srf.c | 84 +++++++++------------------------------ + 1 files changed, 20 insertions(+), 64 deletions(-) + +Index: linux-omap-2.6/arch/arm/plat-omap/omap-pm-srf.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/plat-omap/omap-pm-srf.c 2008-07-21 +12:10:19.824596984 +0530 ++++ linux-omap-2.6/arch/arm/plat-omap/omap-pm-srf.c 2008-07-21 +12:10:21.626540178 +0530 +@@ -25,6 +25,7 @@ + #include <linux/init.h> + #include <linux/cpufreq.h> + #include <linux/device.h> ++#include <linux/module.h> + + /* Interface documentation is in asm/arch/omap-pm.h */ + #include <asm/arch/omap-pm.h> +@@ -121,6 +122,7 @@ void omap_pm_set_max_dev_wakeup_lat(stru + WARN_ON(1); + return; + }; ++ + /* Look for the devices Power Domain */ + /* TODO: Put this back in once tiocp layer is available + tiocp_dev = container_of(dev, struct tiocp, dev); +@@ -138,19 +140,6 @@ void omap_pm_set_max_dev_wakeup_lat(stru + res_name = get_lat_res_name(pwrdm_dev->name); + resource_request(res_name, dev, t); + } +- +- /* +- * For current Linux, this needs to map the device to a +- * powerdomain, then go through the list of current max lat +- * constraints on that powerdomain and find the smallest. If +- * the latency constraint has changed, the code should +- * recompute the state to enter for the next powerdomain +- * state. Conceivably, this code should also determine +- * whether to actually disable the device clocks or not, +- * depending on how long it takes to re-enable the clocks. +- * +- * TI CDP code can call constraint_set here. +- */ + } + + void omap_pm_set_max_sdma_lat(struct device *dev, long t) +@@ -169,21 +158,9 @@ void omap_pm_set_max_sdma_lat(struct dev + "dev %s, t = %ld usec\n", dev_name(dev), t); + resource_request("core_latency", dev, t); + } +- +- /* +- * For current Linux PM QOS params, this code should scan the +- * list of maximum CPU and DMA latencies and select the +- * smallest, then set cpu_dma_latency pm_qos_param +- * accordingly. +- * +- * For future Linux PM QOS params, with separate CPU and DMA +- * latency params, this code should just set the dma_latency param. +- * +- * TI CDP code can call constraint_set here. +- */ +- + } + ++static struct device dummy_dsp_dev; + + /* + * DSP Bridge-specific constraints +@@ -200,6 +177,7 @@ const struct omap_opp *omap_pm_dsp_get_o + + return NULL; + } ++EXPORT_SYMBOL(omap_pm_dsp_get_opp_table); + + void omap_pm_dsp_set_min_opp(u8 opp_id) + { +@@ -210,36 +188,21 @@ void omap_pm_dsp_set_min_opp(u8 opp_id) + + pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id); + +- /* +- * +- * For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we +- * can just test to see which is higher, the CPU's desired OPP +- * ID or the DSP's desired OPP ID, and use whichever is +- * highest. +- * +- * In CDP12.14+, the VDD1 OPP custom clock that controls the DSP +- * rate is keyed on MPU speed, not the OPP ID. So we need to +- * map the OPP ID to the MPU speed for use with clk_set_rate() +- * if it is higher than the current OPP clock rate. +- * +- */ +-} ++ /* For now pass a dummy_dev struct for SRF to identify the caller. ++ * Maybe its good to have DSP pass this as an argument ++ */ ++ resource_request("vdd1_opp", &dummy_dsp_dev, opp_id); ++ return; + ++} ++EXPORT_SYMBOL(omap_pm_dsp_set_min_opp); + + u8 omap_pm_dsp_get_opp(void) + { + pr_debug("OMAP PM: DSP requests current DSP OPP ID\n"); +- +- /* +- * For l-o dev tree, call clk_get_rate() on VDD1 OPP clock +- * +- * CDP12.14+: +- * Call clk_get_rate() on the OPP custom clock, map that to an +- * OPP ID using the tables defined in board-*.c/chip-*.c files. +- */ +- +- return 0; ++ return resource_get_level("vdd1_opp"); + } ++EXPORT_SYMBOL(omap_pm_dsp_get_opp); + + /* + * CPUFreq-originated constraint +@@ -261,6 +224,8 @@ struct cpufreq_frequency_table **omap_pm + return NULL; + } + ++static struct device dummy_cpufreq_dev; ++ + void omap_pm_cpu_set_freq(unsigned long f) + { + if (f == 0) { +@@ -271,26 +236,17 @@ void omap_pm_cpu_set_freq(unsigned long + pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n", + f); + +- /* +- * For l-o dev tree, determine whether MPU freq or DSP OPP id +- * freq is higher. Find the OPP ID corresponding to the +- * higher frequency. Call clk_round_rate() and clk_set_rate() +- * on the OPP custom clock. +- * +- * CDP should just be able to set the VDD1 OPP clock rate here. +- */ ++ resource_request("mpu_freq", &dummy_cpufreq_dev, f); ++ return; + } ++EXPORT_SYMBOL(omap_pm_cpu_set_freq); + + unsigned long omap_pm_cpu_get_freq(void) + { + pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n"); +- +- /* +- * Call clk_get_rate() on the mpu_ck. +- */ +- +- return 0; ++ return resource_get_level("mpu_freq"); + } ++EXPORT_SYMBOL(omap_pm_cpu_get_freq); + + struct device omap_pm_dev; + + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/07-set-burst-size.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/07-set-burst-size.diff new file mode 100644 index 0000000000..99bd80eae0 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/07-set-burst-size.diff @@ -0,0 +1,21 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Tue, 8 Jul 2008 18:26:43 +0000 (+0100) +Subject: omapfb: set graphics burst size to 16x32 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=4f9e415dfcd5613a8de973f6c9878cab959c5869 + +omapfb: set graphics burst size to 16x32 +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 85d6cad..fd06ca2 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -409,7 +409,7 @@ static inline int _setup_plane(int plane, int channel_out, + l |= cconv_en << 9; + + l &= ~(0x03 << burst_shift); +- l |= DISPC_BURST_8x32 << burst_shift; ++ l |= DISPC_BURST_16x32 << burst_shift; + + l &= ~(1 << chout_shift); + l |= chout_val << chout_shift; diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/08-omappm-voltagescaling.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/08-omappm-voltagescaling.eml new file mode 100644 index 0000000000..a7885774f4 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/08-omappm-voltagescaling.eml @@ -0,0 +1,96 @@ +Adds Voltage scaling support + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> +--- + arch/arm/mach-omap2/board-3430sdp.c | 12 ++++++++++++ + arch/arm/mach-omap2/resource34xx.c | 17 ++++++++++++++++- + arch/arm/mach-omap2/resource34xx.h | 3 +++ + 3 files changed, 31 insertions(+), 1 deletion(-) + +Index: linux-omap-2.6/arch/arm/mach-omap2/board-3430sdp.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/board-3430sdp.c 2008-08-11 +17:16:07.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/board-3430sdp.c 2008-08-11 +17:17:58.000000000 +0530 +@@ -94,6 +94,18 @@ struct vdd_prcm_config iva2_rate_table[] + + #define TWL4030_MSECURE_GPIO 22 + ++u8 vdd1_volts[MAX_VDD1_OPP] = { ++ /* Vsel corresponding to 0.9V (OPP1), 1.00V (OPP2), ++ * 1.20V (OPP3), 1.27V (OPP4), 1.35 (OPP5) ++ */ ++ 0x18, 0x20, 0x30, 0x36, 0x3C ++}; ++ ++u8 vdd2_volts[MAX_VDD2_OPP] = { ++ /* Vsel corresponding to 0.9V (OPP1), 1.00V (OPP2), 1.15 (OPP3) */ ++ 0x18, 0x20, 0x2C ++}; ++ + static struct resource sdp3430_smc91x_resources[] = { + [0] = { + .start = OMAP34XX_ETHR_START, +Index: linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/resource34xx.c 2008-08-11 +17:17:23.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c 2008-08-11 +17:22:02.000000000 +0530 +@@ -19,6 +19,7 @@ + #include <linux/pm_qos_params.h> + #include <asm/arch/powerdomain.h> + #include <asm/arch/clockdomain.h> ++#include "smartreflex.h" + #include "resource34xx.h" + + /** +@@ -174,10 +175,24 @@ int set_opp(struct shared_resource *resp + { + #ifdef CONFIG_MACH_OMAP_3430SDP + unsigned long mpu_freq; ++ ++ if (resp->curr_level == target_level) ++ return 0; ++ + if (strcmp(resp->name, "vdd1_opp") == 0) { + mpu_freq = get_freq(vdd1_rate_table + MAX_VDD1_OPP, + target_level); +- clk_set_rate(vdd1_clk, mpu_freq); ++ if (resp->curr_level > target_level) { ++ /* Scale Frequency and then voltage */ ++ clk_set_rate(vdd1_clk, mpu_freq); ++ sr_voltagescale_vcbypass(PRCM_VDD1, ++ vdd1_volts[target_level-1]); ++ } else { ++ /* Scale Voltage and then frequency */ ++ sr_voltagescale_vcbypass(PRCM_VDD1, ++ vdd1_volts[target_level-1]); ++ clk_set_rate(vdd1_clk, mpu_freq); ++ } + resp->curr_level = curr_vdd1_prcm_set->opp; + } else if (strcmp(resp->name, "vdd2_opp") == 0) { + /* Not supported yet */ +Index: linux-omap-2.6/arch/arm/mach-omap2/resource34xx.h +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/resource34xx.h 2008-08-11 +17:17:23.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/resource34xx.h 2008-08-11 +17:17:58.000000000 +0530 +@@ -33,6 +33,9 @@ extern unsigned int get_opp(struct vdd_p + extern struct vdd_prcm_config vdd1_rate_table[]; + extern struct vdd_prcm_config vdd2_rate_table[]; + extern struct vdd_prcm_config iva2_rate_table[]; ++extern u8 vdd1_volts[]; ++extern u8 vdd2_volts[]; ++extern int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel); + /** + * mpu_latency/core_latency are used to control the cpuidle C state. + */ + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/09-omappm-vdd2-scaling.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/09-omappm-vdd2-scaling.eml new file mode 100644 index 0000000000..532a9f7975 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/09-omappm-vdd2-scaling.eml @@ -0,0 +1,102 @@ +Adds VDD2 scaling support + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> +--- + arch/arm/mach-omap2/resource34xx.c | 35 +++++++++++++++++++++++++++++++++-- + arch/arm/plat-omap/omap-pm-srf.c | 15 +++++---------- + 2 files changed, 38 insertions(+), 12 deletions(-) + +Index: linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/resource34xx.c 2008-07-21 +12:10:22.032527379 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c 2008-07-21 +12:10:22.479513287 +0530 +@@ -174,7 +174,9 @@ void init_opp(struct shared_resource *re + int set_opp(struct shared_resource *resp, u32 target_level) + { + #ifdef CONFIG_MACH_OMAP_3430SDP +- unsigned long mpu_freq; ++ unsigned long mpu_freq, l3_freq, tput; ++ int ind; ++ struct bus_throughput_db *tput_db; + + if (resp->curr_level == target_level) + return 0; +@@ -195,7 +197,36 @@ int set_opp(struct shared_resource *resp + } + resp->curr_level = curr_vdd1_prcm_set->opp; + } else if (strcmp(resp->name, "vdd2_opp") == 0) { +- /* Not supported yet */ ++ tput_db = resp->resource_data; ++ tput = target_level; ++ /* using the throughput db map to the appropriate L3 Freq */ ++ for (ind = 1; ind < MAX_VDD2_OPP; ind++) ++ if (tput_db->throughput[ind] > tput) ++ target_level = ind; ++ ++ /* Set the highest OPP possible */ ++ if (ind == MAX_VDD2_OPP) ++ target_level = ind-1; ++ ++ if (resp->curr_level == target_level) ++ return 0; ++ ++ resp->curr_level = target_level; ++ ++ l3_freq = get_freq(vdd2_rate_table + MAX_VDD2_OPP, ++ target_level); ++ if (resp->curr_level > target_level) { ++ /* Scale Frequency and then voltage */ ++ clk_set_rate(vdd2_clk, l3_freq); ++ sr_voltagescale_vcbypass(PRCM_VDD2, ++ vdd2_volts[target_level-1]); ++ } else { ++ /* Scale Voltage and then frequency */ ++ sr_voltagescale_vcbypass(PRCM_VDD2, ++ vdd2_volts[target_level-1]); ++ clk_set_rate(vdd1_clk, l3_freq); ++ } ++ resp->curr_level = curr_vdd2_prcm_set->opp; + } + #endif + return 0; +Index: linux-omap-2.6/arch/arm/plat-omap/omap-pm-srf.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/plat-omap/omap-pm-srf.c 2008-07-21 +12:10:21.626540178 +0530 ++++ linux-omap-2.6/arch/arm/plat-omap/omap-pm-srf.c 2008-07-21 +12:10:22.479513287 +0530 +@@ -95,21 +95,16 @@ void omap_pm_set_min_bus_tput(struct dev + return; + }; + +- if (r == 0) ++ if (r == 0) { + pr_debug("OMAP PM: remove min bus tput constraint: " + "dev %s for agent_id %d\n", dev_name(dev), agent_id); +- else ++ resource_release("vdd2_opp", r); ++ } else { + pr_debug("OMAP PM: add min bus tput constraint: " + "dev %s for agent_id %d: rate %ld KiB\n", + dev_name(dev), agent_id, r); +- +- /* +- * This code should model the interconnect and compute the +- * required clock frequency, convert that to a VDD2 OPP ID, then +- * set the VDD2 OPP appropriately. +- * +- * TI CDP code can call constraint_set here on the VDD2 OPP. +- */ ++ resource_request("vdd2_opp", dev, r); ++ } + } + + void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t) + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/10-omappm-off-mode.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/10-omappm-off-mode.eml new file mode 100644 index 0000000000..3728440159 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/10-omappm-off-mode.eml @@ -0,0 +1,35 @@ +A Temp patch needed only till OFF mode is implemented. + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> +--- + arch/arm/mach-omap2/resource34xx.c | 4 ++-- + 1 files changed, 2 insertions(+), 2 deletions(-) + +Index: linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/resource34xx.c 2008-08-11 +17:39:00.000000000 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/resource34xx.c 2008-08-11 +17:39:00.000000000 +0530 +@@ -131,13 +131,13 @@ int set_pd_latency(struct shared_resourc + omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[i]); + } + pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_ON); +- pwrdm_set_next_pwrst(pwrdm, pd_lat_level); ++ pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_RET); + for (i = 0; pwrdm->pwrdm_clkdms[i]; i++) { + omap2_clkdm_sleep(pwrdm->pwrdm_clkdms[i]); + omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[i]); + } + } else +- pwrdm_set_next_pwrst(pwrdm, pd_lat_level); ++ pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_RET); + break; + case PWRDM_POWER_ON: + pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_ON); + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/16bpp.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/16bpp.patch new file mode 100644 index 0000000000..d2bff4b018 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/16bpp.patch @@ -0,0 +1,137 @@ +diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig +index bdeb8fb..bf256f3 100644 +--- a/drivers/video/omap/Kconfig ++++ b/drivers/video/omap/Kconfig +@@ -7,6 +7,27 @@ config FB_OMAP + help + Frame buffer driver for OMAP based boards. + ++choice ++ depends on FB_OMAP && MACH_OMAP3_BEAGLE ++ prompt "Screen resolution" ++ default FB_OMAP_079M3R ++ help ++ Selected desired screen resolution ++ ++config FB_OMAP_031M3R ++ boolean "640 x 480 @ 60 Hz Reduced blanking" ++ ++config FB_OMAP_048M3R ++ boolean "800 x 600 @ 60 Hz Reduced blanking" ++ ++config FB_OMAP_079M3R ++ boolean "1024 x 768 @ 60 Hz Reduced blanking" ++ ++config FB_OMAP_092M9R ++ boolean "1280 x 720 @ 60 Hz Reduced blanking" ++ ++endchoice ++ + config FB_OMAP_LCDC_EXTERNAL + bool "External LCD controller support" + depends on FB_OMAP +diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c +index 69d4e06..5e098c2 100644 +--- a/drivers/video/omap/lcd_omap3beagle.c ++++ b/drivers/video/omap/lcd_omap3beagle.c +@@ -31,10 +31,6 @@ + + #define LCD_PANEL_ENABLE_GPIO 170 + +-#define LCD_XRES 1024 +-#define LCD_YRES 768 +-#define LCD_PIXCLOCK 64000 /* in kHz */ +- + static int omap3beagle_panel_init(struct lcd_panel *panel, + struct omapfb_device *fbdev) + { +@@ -65,19 +61,76 @@ static unsigned long omap3beagle_panel_get_caps(struct lcd_panel *panel) + struct lcd_panel omap3beagle_panel = { + .name = "omap3beagle", + .config = OMAP_LCDC_PANEL_TFT, +- +- .bpp = 24, ++ .bpp = 16, + .data_lines = 24, +- .x_res = LCD_XRES, +- .y_res = LCD_YRES, +- .hsw = 3, /* hsync_len (4) - 1 */ +- .hfp = 3, /* right_margin (4) - 1 */ +- .hbp = 39, /* left_margin (40) - 1 */ +- .vsw = 1, /* vsync_len (2) - 1 */ +- .vfp = 2, /* lower_margin */ +- .vbp = 7, /* upper_margin (8) - 1 */ +- +- .pixel_clock = LCD_PIXCLOCK, ++ ++#if defined CONFIG_FB_OMAP_031M3R ++ ++ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */ ++ .x_res = 640, ++ .y_res = 480, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 7, ++ .pixel_clock = 23500, ++ ++#elif defined CONFIG_FB_OMAP_048M3R ++ ++ /* 800 x 600 @ 60 Hz Reduced blanking VESA CVT 0.48M3-R */ ++ .x_res = 800, ++ .y_res = 600, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 11, ++ .pixel_clock = 35500, ++ ++#elif defined CONFIG_FB_OMAP_079M3R ++ ++ /* 1024 x 768 @ 60 Hz Reduced blanking VESA CVT 0.79M3-R */ ++ .x_res = 1024, ++ .y_res = 768, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 15, ++ .pixel_clock = 56000, ++ ++#elif defined CONFIG_FB_OMAP_092M9R ++ ++ /* 1280 x 720 @ 60 Hz Reduced blanking VESA CVT 0.92M9-R */ ++ .x_res = 1280, ++ .y_res = 720, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 5, ++ .vbp = 13, ++ .pixel_clock = 64000, ++ ++#else ++ ++ /* use 640 x 480 if no config option */ ++ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */ ++ .x_res = 640, ++ .y_res = 480, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 7, ++ .pixel_clock = 23500, ++ ++#endif + + .init = omap3beagle_panel_init, + .cleanup = omap3beagle_panel_cleanup, + diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/400khz-i2c.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/400khz-i2c.diff new file mode 100644 index 0000000000..f749dbcf5b --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/400khz-i2c.diff @@ -0,0 +1,22 @@ +From: Steve Sakoman <steve@sakoman.com> +Date: Wed, 16 Jul 2008 19:38:43 +0000 (-0700) +Subject: omap3beagle: set data rate on i2c-1 to 400, since 2600 seems to be +X-Git-Url: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=commitdiff_plain;h=12d6504334a830774ff1d42cee4b7296ac9fb7d2 + +omap3beagle: set data rate on i2c-1 to 400, since 2600 seems to be +flakey +--- + +diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c +index fdce787..938ad73 100644 +--- a/arch/arm/mach-omap2/board-omap3beagle.c ++++ b/arch/arm/mach-omap2/board-omap3beagle.c +@@ -39,7 +39,7 @@ static struct omap_uart_config omap3_beagle_uart_config __initdata = { + + static int __init omap3_beagle_i2c_init(void) + { +- omap_register_i2c_bus(1, 2600, NULL, 0); ++ omap_register_i2c_bus(1, 400, NULL, 0); + omap_register_i2c_bus(2, 400, NULL, 0); + omap_register_i2c_bus(3, 400, NULL, 0); + return 0; diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/4bitmmc.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/4bitmmc.diff new file mode 100644 index 0000000000..5cd120c544 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/4bitmmc.diff @@ -0,0 +1,38 @@ +From: Purushotam Kumar <purushotam@ti.com> +Date: Fri, 18 Jul 2008 23:28:57 +0000 (-0700) +Subject: OMAP3:devices.c:Enabling 4-bit for SD card +X-Git-Url: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=commitdiff_plain;h=6c4d34031c80ca4b50ffe73a4ef7fe197a760a60 + +OMAP3:devices.c:Enabling 4-bit for SD card + +SD card was working in 1-bit mode.This patch will configure SD card in +4-bit mode and hence performance will increase. + +Signed-off-by: Purushotam Kumar <purushotam@ti.com> +Acked-by: Madhusudhan Chikkature Rajashekar <madhu.cr@ti.com> +--- + +diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c +index b83f9a6..d0cfceb 100644 +--- a/arch/arm/plat-omap/devices.c ++++ b/arch/arm/plat-omap/devices.c +@@ -296,13 +296,17 @@ static void __init omap_init_mmc(void) + mmc = &mmc_conf->mmc[0]; + + if (cpu_is_omap2430() || cpu_is_omap34xx()) { +- if (mmc->enabled) ++ if (mmc->enabled) { ++ mmc1_data.conf = *mmc; + (void) platform_device_register(&mmc_omap_device1); ++ } + + #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) + mmc = &mmc_conf->mmc[1]; +- if (mmc->enabled) ++ if (mmc->enabled) { ++ mmc2_data.conf = *mmc; + (void) platform_device_register(&mmc_omap_device2); ++ } + #endif + + return; diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/ASoC-TWL4030-codec-driver.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/ASoC-TWL4030-codec-driver.patch new file mode 100644 index 0000000000..ef9a0ed0fe --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/ASoC-TWL4030-codec-driver.patch @@ -0,0 +1,831 @@ +From: Steve Sakoman <steve@sakoman.com> +Date: Fri, 18 Jul 2008 16:41:27 +0000 (-0700) +Subject: ASoC TWL4030 codec driver +X-Git-Url: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=commitdiff_plain;h=67b73de03016cc31b1f91af93c57b8e749c13520;hp=d3b3ae0fe6c71641da19c8de466ec366d39847e3 + +ASoC TWL4030 codec driver + +Basic audio support for the TWL4030 + +Signed-off-by: Steve Sakoman <steve@sakoman.com> +--- + +diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig +index 3903ab7..468536d 100644 +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -44,3 +44,7 @@ config SND_SOC_CS4270_VD33_ERRATA + config SND_SOC_TLV320AIC3X + tristate + depends on SND_SOC && I2C ++ ++config SND_SOC_TWL4030 ++ tristate ++ depends on SND_SOC && I2C +diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile +index 4e1314c..d2c0b12 100644 +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -6,6 +6,7 @@ snd-soc-wm9712-objs := wm9712.o + snd-soc-wm9713-objs := wm9713.o + snd-soc-cs4270-objs := cs4270.o + snd-soc-tlv320aic3x-objs := tlv320aic3x.o ++snd-soc-twl4030-objs := twl4030.o + + obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o + obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o +@@ -15,3 +16,4 @@ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o + obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o + obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o + obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o ++obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o +diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c +new file mode 100644 +index 0000000..25a154c +--- /dev/null ++++ b/sound/soc/codecs/twl4030.c +@@ -0,0 +1,626 @@ ++/* ++ * ALSA SoC TWL4030 codec driver ++ * ++ * Author: Steve Sakoman, <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/init.h> ++#include <linux/delay.h> ++#include <linux/pm.h> ++#include <linux/i2c.h> ++#include <linux/platform_device.h> ++#include <linux/i2c/twl4030.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/pcm_params.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++#include <sound/initval.h> ++ ++#include "twl4030.h" ++ ++/* ++ * twl4030 register cache & default register settings ++ */ ++static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { ++ 0x00, /* this register not used */ ++ 0x93, /* REG_CODEC_MODE (0x1) */ ++ 0xc3, /* REG_OPTION (0x2) */ ++ 0x00, /* REG_UNKNOWN (0x3) */ ++ 0x00, /* REG_MICBIAS_CTL (0x4) */ ++ 0x34, /* REG_ANAMICL (0x5) */ ++ 0x14, /* REG_ANAMICR (0x6) */ ++ 0x0a, /* REG_AVADC_CTL (0x7) */ ++ 0x00, /* REG_ADCMICSEL (0x8) */ ++ 0x00, /* REG_DIGMIXING (0x9) */ ++ 0x0c, /* REG_ATXL1PGA (0xA) */ ++ 0x0c, /* REG_ATXR1PGA (0xB) */ ++ 0x00, /* REG_AVTXL2PGA (0xC) */ ++ 0x00, /* REG_AVTXR2PGA (0xD) */ ++ 0x01, /* REG_AUDIO_IF (0xE) */ ++ 0x00, /* REG_VOICE_IF (0xF) */ ++ 0x00, /* REG_ARXR1PGA (0x10) */ ++ 0x00, /* REG_ARXL1PGA (0x11) */ ++ 0x6c, /* REG_ARXR2PGA (0x12) */ ++ 0x6c, /* REG_ARXL2PGA (0x13) */ ++ 0x00, /* REG_VRXPGA (0x14) */ ++ 0x00, /* REG_VSTPGA (0x15) */ ++ 0x00, /* REG_VRX2ARXPGA (0x16) */ ++ 0x0c, /* REG_AVDAC_CTL (0x17) */ ++ 0x00, /* REG_ARX2VTXPGA (0x18) */ ++ 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ ++ 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ ++ 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */ ++ 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */ ++ 0x00, /* REG_ATX2ARXPGA (0x1D) */ ++ 0x00, /* REG_BT_IF (0x1E) */ ++ 0x00, /* REG_BTPGA (0x1F) */ ++ 0x00, /* REG_BTSTPGA (0x20) */ ++ 0x00, /* REG_EAR_CTL (0x21) */ ++ 0x24, /* REG_HS_SEL (0x22) */ ++ 0x0a, /* REG_HS_GAIN_SET (0x23) */ ++ 0x00, /* REG_HS_POPN_SET (0x24) */ ++ 0x00, /* REG_PREDL_CTL (0x25) */ ++ 0x00, /* REG_PREDR_CTL (0x26) */ ++ 0x00, /* REG_PRECKL_CTL (0x27) */ ++ 0x00, /* REG_PRECKR_CTL (0x28) */ ++ 0x00, /* REG_HFL_CTL (0x29) */ ++ 0x00, /* REG_HFR_CTL (0x2A) */ ++ 0x00, /* REG_ALC_CTL (0x2B) */ ++ 0x00, /* REG_ALC_SET1 (0x2C) */ ++ 0x00, /* REG_ALC_SET2 (0x2D) */ ++ 0x00, /* REG_BOOST_CTL (0x2E) */ ++ 0x01, /* REG_SOFTVOL_CTL (0x2F) */ ++ 0x00, /* REG_DTMF_FREQSEL (0x30) */ ++ 0x00, /* REG_DTMF_TONEXT1H (0x31) */ ++ 0x00, /* REG_DTMF_TONEXT1L (0x32) */ ++ 0x00, /* REG_DTMF_TONEXT2H (0x33) */ ++ 0x00, /* REG_DTMF_TONEXT2L (0x34) */ ++ 0x00, /* REG_DTMF_TONOFF (0x35) */ ++ 0x00, /* REG_DTMF_WANONOFF (0x36) */ ++ 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ ++ 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ ++ 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ ++ 0x16, /* REG_APLL_CTL (0x3A) */ ++ 0x00, /* REG_DTMF_CTL (0x3B) */ ++ 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ ++ 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ ++ 0x00, /* REG_MISC_SET_1 (0x3E) */ ++ 0x00, /* REG_PCMBTMUX (0x3F) */ ++ 0x00, /* not used (0x40) */ ++ 0x00, /* not used (0x41) */ ++ 0x00, /* not used (0x42) */ ++ 0x00, /* REG_RX_PATH_SEL (0x43) */ ++ 0x00, /* REG_VDL_APGA_CTL (0x44) */ ++ 0x00, /* REG_VIBRA_CTL (0x45) */ ++ 0x00, /* REG_VIBRA_SET (0x46) */ ++ 0x00, /* REG_VIBRA_PWM_SET (0x47) */ ++ 0x00, /* REG_ANAMIC_GAIN (0x48) */ ++ 0x00, /* REG_MISC_SET_2 (0x49) */ ++}; ++ ++static void twl4030_dump_registers(void) ++{ ++ int i = 0; ++ u8 data; ++ ++ printk(KERN_INFO "TWL 4030 Register dump for Audio Module\n"); ++ ++ for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &data, i); ++ printk(KERN_INFO "Register[0x%02x]=0x%02x\n", i, data); ++ } ++} ++ ++struct twl4030_priv { ++ unsigned int dummy; ++}; ++ ++/* ++ * read twl4030 register cache ++ */ ++static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, ++ unsigned int reg) ++{ ++ u8 *cache = codec->reg_cache; ++ ++ return cache[reg]; ++} ++ ++/* ++ * write twl4030 register cache ++ */ ++static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, ++ u8 reg, u8 value) ++{ ++ u8 *cache = codec->reg_cache; ++ ++ if (reg >= TWL4030_CACHEREGNUM) ++ return; ++ cache[reg] = value; ++} ++ ++/* ++ * write to the twl4030 register space ++ */ ++static int twl4030_write(struct snd_soc_codec *codec, ++ unsigned int reg, unsigned int value) ++{ ++ twl4030_write_reg_cache(codec, reg, value); ++ return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); ++} ++ ++static void twl4030_init_chip(void) ++{ ++ unsigned char byte; ++ int i; ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_CODEC_MODE] & 0xfd, REG_CODEC_MODE); ++ ++ udelay(10); /* delay for power settling */ ++ ++ for (i = REG_OPTION; i <= REG_MISC_SET_2; i++) ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[i], i); ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_CODEC_MODE], REG_CODEC_MODE); ++ ++ udelay(10); /* delay for power settling */ ++ ++ /* initiate offset cancellation */ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_ANAMICL] | 0x80, REG_ANAMICL); ++ ++ /* wait for offset cancellation to complete */ ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL); ++ while ((byte & 0x80) == 0x80) ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, ++ &byte, REG_ANAMICL); ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_MISC_SET_1] | 0x02, REG_MISC_SET_1); ++ ++} ++ ++static const struct snd_kcontrol_new twl4030_snd_controls[] = { ++ SOC_DOUBLE_R("Master Playback Volume", ++ REG_ARXL2PGA, REG_ARXR2PGA, ++ 0, 127, 0), ++ SOC_DOUBLE_R("Capture Volume", ++ REG_ATXL1PGA, REG_ATXR1PGA, ++ 0, 127, 0), ++}; ++ ++/* add non dapm controls */ ++static int twl4030_add_controls(struct snd_soc_codec *codec) ++{ ++ int err, i; ++ ++ for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) { ++ err = snd_ctl_add(codec->card, ++ snd_soc_cnew(&twl4030_snd_controls[i], ++ codec, NULL)); ++ if (err < 0) ++ return err; ++ } ++ ++ return 0; ++} ++ ++static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { ++ SND_SOC_DAPM_INPUT("INL"), ++ SND_SOC_DAPM_INPUT("INR"), ++ ++ SND_SOC_DAPM_OUTPUT("OUTL"), ++ SND_SOC_DAPM_OUTPUT("OUTR"), ++ ++ SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), ++ SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), ++ ++ SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0), ++ SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0), ++}; ++ ++static const char *intercon[][3] = { ++ /* outputs */ ++ {"OUTL", NULL, "DACL"}, ++ {"OUTR", NULL, "DACR"}, ++ ++ /* inputs */ ++ {"ADCL", NULL, "INL"}, ++ {"ADCR", NULL, "INR"}, ++ ++ /* terminator */ ++ {NULL, NULL, NULL}, ++}; ++ ++static int twl4030_add_widgets(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++) ++ snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]); ++ ++ /* set up audio path interconnects */ ++ for (i = 0; intercon[i][0] != NULL; i++) ++ snd_soc_dapm_connect_input(codec, intercon[i][0], ++ intercon[i][1], intercon[i][2]); ++ ++ snd_soc_dapm_new_widgets(codec); ++ return 0; ++} ++ ++static int twl4030_dapm_event(struct snd_soc_codec *codec, int event) ++{ ++ ++ printk(KERN_INFO "TWL4030 Audio Codec dapm event\n"); ++ switch (event) { ++ case SNDRV_CTL_POWER_D0: /* full On */ ++ break; ++ case SNDRV_CTL_POWER_D1: /* partial On */ ++ case SNDRV_CTL_POWER_D2: /* partial On */ ++ break; ++ case SNDRV_CTL_POWER_D3hot: /* off, with power */ ++ break; ++ case SNDRV_CTL_POWER_D3cold: /* off, without power */ ++ break; ++ } ++ codec->dapm_state = event; ++ ++ return 0; ++} ++ ++static void twl4030_power_up(struct snd_soc_codec *codec, u8 mode) ++{ ++ u8 popn, hsgain; ++ ++ twl4030_write(codec, REG_CODEC_MODE, mode & ~CODECPDZ); ++ twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ); ++ udelay(10); ++ ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); ++ popn &= RAMP_DELAY; ++ popn |= VMID_EN | RAMP_DELAY_161MS; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ hsgain = HSR_GAIN_0DB | HSL_GAIN_0DB; ++ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); ++ ++ popn |= RAMP_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++} ++ ++static void twl4030_power_down(struct snd_soc_codec *codec) ++{ ++ u8 popn, hsgain, mode; ++ ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); ++ popn &= ~RAMP_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ hsgain = HSR_GAIN_PWR_DOWN | HSL_GAIN_PWR_DOWN; ++ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); ++ ++ popn &= ~VMID_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ udelay(10); ++} ++ ++ ++static int twl4030_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_device *socdev = rtd->socdev; ++ struct snd_soc_codec *codec = socdev->codec; ++ struct twl4030_priv *twl4030 = codec->private_data; ++ u8 mode, old_mode, format, old_format; ++ ++ ++ /* bit rate */ ++ old_mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ; ++ mode = old_mode; ++ mode &= ~APLL_RATE; ++ switch (params_rate(params)) { ++ case 44100: ++ mode |= APLL_RATE_44100; ++ break; ++ case 48000: ++ mode |= APLL_RATE_48000; ++ break; ++ default: ++ printk(KERN_INFO "TWL4030 hw params: unknown rate %d\n", ++ params_rate(params)); ++ return -EINVAL; ++ } ++ ++ if (mode != old_mode) { ++ /* change rate and turn codec back on */ ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ ++ /* sample size */ ++ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ format = old_format; ++ format &= ~DATA_WIDTH; ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ format |= DATA_WIDTH_16S_16W; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ format |= DATA_WIDTH_32S_24W; ++ break; ++ default: ++ printk(KERN_INFO "TWL4030 hw params: unknown format %d\n", ++ params_format(params)); ++ return -EINVAL; ++ } ++ ++ if (format != old_format) { ++ ++ /* turn off codec before changing format */ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ ++ /* change format */ ++ twl4030_write(codec, REG_AUDIO_IF, format); ++ ++ /* turn on codec */ ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ return 0; ++} ++ ++static int twl4030_mute(struct snd_soc_codec_dai *dai, int mute) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ ++ u8 ldac_reg = twl4030_read_reg_cache(codec, REG_ARXL2PGA); ++ u8 rdac_reg = twl4030_read_reg_cache(codec, REG_ARXR2PGA); ++ ++ if (mute) { ++ twl4030_write(codec, REG_ARXL2PGA, 0x00); ++ twl4030_write(codec, REG_ARXR2PGA, 0x00); ++ twl4030_write_reg_cache(codec, REG_ARXL2PGA, ldac_reg); ++ twl4030_write_reg_cache(codec, REG_ARXR2PGA, rdac_reg); ++ } else { ++ twl4030_write(codec, REG_ARXL2PGA, ldac_reg); ++ twl4030_write(codec, REG_ARXR2PGA, rdac_reg); ++ } ++ ++ return 0; ++} ++ ++static int twl4030_set_dai_fmt(struct snd_soc_codec_dai *codec_dai, ++ unsigned int fmt) ++{ ++ struct snd_soc_codec *codec = codec_dai->codec; ++ struct twl4030_priv *twl4030 = codec->private_data; ++ u8 mode, old_format, format; ++ ++ /* get format */ ++ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ format = old_format; ++ ++ /* set master/slave audio interface */ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++ format &= ~(AIF_SLAVE_EN); ++ format |= CLK256FS_EN; ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ format &= ~(CLK256FS_EN); ++ format |= AIF_SLAVE_EN; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* interface format */ ++ format &= ~AIF_FORMAT; ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ /* printk(KERN_INFO "TWL4030 set dai fmt: i2s\n"); */ ++ format |= AIF_FORMAT_CODEC; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (format != old_format) { ++ ++ /* turn off codec before changing format */ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ ++ /* change format */ ++ twl4030_write(codec, REG_AUDIO_IF, format); ++ ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ ++ return 0; ++} ++ ++#define TWL4030_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) ++#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) ++ ++struct snd_soc_codec_dai twl4030_dai = { ++ .name = "twl4030", ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = TWL4030_RATES, ++ .formats = TWL4030_FORMATS,}, ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = TWL4030_RATES, ++ .formats = TWL4030_FORMATS,}, ++ .ops = { ++ .hw_params = twl4030_hw_params, ++ }, ++ .dai_ops = { ++ .digital_mute = twl4030_mute, ++ .set_fmt = twl4030_set_dai_fmt, ++ } ++}; ++EXPORT_SYMBOL_GPL(twl4030_dai); ++ ++static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec suspend\n"); ++ twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3cold); ++ ++ return 0; ++} ++ ++static int twl4030_resume(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ int i; ++ u16 *cache = codec->reg_cache; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec resume\n"); ++ /* Sync reg_cache with the hardware */ ++ for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, cache[i], i); ++ ++ twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3hot); ++ twl4030_dapm_event(codec, codec->suspend_dapm_state); ++ return 0; ++} ++ ++/* ++ * initialize the driver ++ * register the mixer and dsp interfaces with the kernel ++ */ ++ ++static int twl4030_init(struct snd_soc_device *socdev) ++{ ++ struct snd_soc_codec *codec = socdev->codec; ++ int ret = 0; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec init \n"); ++ ++ codec->name = "twl4030"; ++ codec->owner = THIS_MODULE; ++ codec->read = twl4030_read_reg_cache; ++ codec->write = twl4030_write; ++ codec->dapm_event = twl4030_dapm_event; ++ codec->dai = &twl4030_dai; ++ codec->num_dai = 1; ++ codec->reg_cache_size = sizeof(twl4030_reg); ++ codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), ++ GFP_KERNEL); ++ if (codec->reg_cache == NULL) ++ return -ENOMEM; ++ ++ /* register pcms */ ++ ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); ++ if (ret < 0) { ++ printk(KERN_ERR "twl4030: failed to create pcms\n"); ++ goto pcm_err; ++ } ++ ++ twl4030_add_controls(codec); ++ twl4030_add_widgets(codec); ++ ++ ret = snd_soc_register_card(socdev); ++ if (ret < 0) { ++ printk(KERN_ERR "twl4030: failed to register card\n"); ++ goto card_err; ++ } ++ ++ twl4030_init_chip(); ++ twl4030_power_up(codec, APLL_RATE_44100 | OPT_MODE); ++ ++ return ret; ++ ++card_err: ++ printk(KERN_INFO "TWL4030 Audio Codec init card error\n"); ++ snd_soc_free_pcms(socdev); ++ snd_soc_dapm_free(socdev); ++pcm_err: ++ printk(KERN_INFO "TWL4030 Audio Codec init pcm error\n"); ++ kfree(codec->reg_cache); ++ return ret; ++} ++ ++static struct snd_soc_device *twl4030_socdev; ++ ++static int twl4030_probe(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec; ++ struct twl4030_priv *twl4030; ++ ++ codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); ++ if (codec == NULL) ++ return -ENOMEM; ++ ++ twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL); ++ if (twl4030 == NULL) { ++ kfree(codec); ++ return -ENOMEM; ++ } ++ ++ codec->private_data = twl4030; ++ socdev->codec = codec; ++ mutex_init(&codec->mutex); ++ INIT_LIST_HEAD(&codec->dapm_widgets); ++ INIT_LIST_HEAD(&codec->dapm_paths); ++ ++ twl4030_socdev = socdev; ++ twl4030_init(socdev); ++ ++ return 0; ++} ++ ++static int twl4030_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec remove\n"); ++ kfree(codec->private_data); ++ kfree(codec); ++ ++ return 0; ++} ++ ++struct snd_soc_codec_device soc_codec_dev_twl4030 = { ++ .probe = twl4030_probe, ++ .remove = twl4030_remove, ++ .suspend = twl4030_suspend, ++ .resume = twl4030_resume, ++}; ++EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); ++ ++MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); ++MODULE_AUTHOR("Steve Sakoman"); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h +new file mode 100644 +index 0000000..6eecde1 +--- /dev/null ++++ b/sound/soc/codecs/twl4030.h +@@ -0,0 +1,152 @@ ++/* ++ * ALSA SoC TWL4030 codec driver ++ * ++ * Author: Steve Sakoman, <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __TWL4030_AUDIO_H__ ++#define __TWL4030_AUDIO_H__ ++ ++#define REG_CODEC_MODE 0x1 ++#define REG_OPTION 0x2 ++#define REG_UNKNOWN 0x3 ++#define REG_MICBIAS_CTL 0x4 ++#define REG_ANAMICL 0x5 ++#define REG_ANAMICR 0x6 ++#define REG_AVADC_CTL 0x7 ++#define REG_ADCMICSEL 0x8 ++#define REG_DIGMIXING 0x9 ++#define REG_ATXL1PGA 0xA ++#define REG_ATXR1PGA 0xB ++#define REG_AVTXL2PGA 0xC ++#define REG_AVTXR2PGA 0xD ++#define REG_AUDIO_IF 0xE ++#define REG_VOICE_IF 0xF ++#define REG_ARXR1PGA 0x10 ++#define REG_ARXL1PGA 0x11 ++#define REG_ARXR2PGA 0x12 ++#define REG_ARXL2PGA 0x13 ++#define REG_VRXPGA 0x14 ++#define REG_VSTPGA 0x15 ++#define REG_VRX2ARXPGA 0x16 ++#define REG_AVDAC_CTL 0x17 ++#define REG_ARX2VTXPGA 0x18 ++#define REG_ARXL1_APGA_CTL 0x19 ++#define REG_ARXR1_APGA_CTL 0x1A ++#define REG_ARXL2_APGA_CTL 0x1B ++#define REG_ARXR2_APGA_CTL 0x1C ++#define REG_ATX2ARXPGA 0x1D ++#define REG_BT_IF 0x1E ++#define REG_BTPGA 0x1F ++#define REG_BTSTPGA 0x20 ++#define REG_EAR_CTL 0x21 ++#define REG_HS_SEL 0x22 ++#define REG_HS_GAIN_SET 0x23 ++#define REG_HS_POPN_SET 0x24 ++#define REG_PREDL_CTL 0x25 ++#define REG_PREDR_CTL 0x26 ++#define REG_PRECKL_CTL 0x27 ++#define REG_PRECKR_CTL 0x28 ++#define REG_HFL_CTL 0x29 ++#define REG_HFR_CTL 0x2A ++#define REG_ALC_CTL 0x2B ++#define REG_ALC_SET1 0x2C ++#define REG_ALC_SET2 0x2D ++#define REG_BOOST_CTL 0x2E ++#define REG_SOFTVOL_CTL 0x2F ++#define REG_DTMF_FREQSEL 0x30 ++#define REG_DTMF_TONEXT1H 0x31 ++#define REG_DTMF_TONEXT1L 0x32 ++#define REG_DTMF_TONEXT2H 0x33 ++#define REG_DTMF_TONEXT2L 0x34 ++#define REG_DTMF_TONOFF 0x35 ++#define REG_DTMF_WANONOFF 0x36 ++#define REG_I2S_RX_SCRAMBLE_H 0x37 ++#define REG_I2S_RX_SCRAMBLE_M 0x38 ++#define REG_I2S_RX_SCRAMBLE_L 0x39 ++#define REG_APLL_CTL 0x3A ++#define REG_DTMF_CTL 0x3B ++#define REG_DTMF_PGA_CTL2 0x3C ++#define REG_DTMF_PGA_CTL1 0x3D ++#define REG_MISC_SET_1 0x3E ++#define REG_PCMBTMUX 0x3F ++#define REG_RX_PATH_SEL 0x43 ++#define REG_VDL_APGA_CTL 0x44 ++#define REG_VIBRA_CTL 0x45 ++#define REG_VIBRA_SET 0x46 ++#define REG_VIBRA_PWM_SET 0x47 ++#define REG_ANAMIC_GAIN 0x48 ++#define REG_MISC_SET_2 0x49 ++ ++#define TWL4030_CACHEREGNUM (REG_MISC_SET_2 + 1) ++ ++/* Bitfield Definitions */ ++ ++/* CODEC_MODE (0x01) Fields */ ++ ++#define APLL_RATE 0xF0 ++#define APLL_RATE_8000 0x00 ++#define APLL_RATE_11025 0x10 ++#define APLL_RATE_12000 0x20 ++#define APLL_RATE_16000 0x40 ++#define APLL_RATE_22050 0x50 ++#define APLL_RATE_24000 0x60 ++#define APLL_RATE_32000 0x80 ++#define APLL_RATE_44100 0x90 ++#define APLL_RATE_48000 0xa0 ++#define SEL_16K 0x04 ++#define CODECPDZ 0x02 ++#define OPT_MODE 0x01 ++ ++/* AUDIO_IF (0x0E) Fields */ ++ ++#define AIF_SLAVE_EN 0x80 ++#define DATA_WIDTH 0x60 ++#define DATA_WIDTH_16S_16W 0x00 ++#define DATA_WIDTH_32S_16W 0x40 ++#define DATA_WIDTH_32S_24W 0x60 ++#define AIF_FORMAT 0x18 ++#define AIF_FORMAT_CODEC 0x00 ++#define AIF_FORMAT_LEFT 0x08 ++#define AIF_FORMAT_RIGHT 0x10 ++#define AIF_FORMAT_TDM 0x18 ++#define AIF_TRI_EN 0x04 ++#define CLK256FS_EN 0x02 ++#define AIF_EN 0x01 ++ ++/* HS_GAIN_SET (0x23) Fields */ ++ ++#define HSR_GAIN 0x0c ++#define HSR_GAIN_PWR_DOWN 0x00 ++#define HSR_GAIN_PLUS_6DB 0x04 ++#define HSR_GAIN_0DB 0x08 ++#define HSR_GAIN_MINUS_6DB 0x0c ++#define HSL_GAIN 0x0c ++#define HSL_GAIN_PWR_DOWN 0x00 ++#define HSL_GAIN_PLUS_6DB 0x01 ++#define HSL_GAIN_0DB 0x02 ++#define HSL_GAIN_MINUS_6DB 0x03 ++ ++/* HS_POPN_SET (0x24) Fields */ ++ ++#define VMID_EN 0x40 ++#define EXTMUTE 0x20 ++#define RAMP_DELAY 0x1C ++#define RAMP_DELAY_20MS 0x00 ++#define RAMP_DELAY_40MS 0x04 ++#define RAMP_DELAY_81MS 0x08 ++#define RAMP_DELAY_161MS 0x0c ++#define RAMP_DELAY_323MS 0x10 ++#define RAMP_DELAY_645MS 0x14 ++#define RAMP_DELAY_1291MS 0x18 ++#define RAMP_DELAY_2581MS 0x1c ++#define RAMP_EN 0x02 ++ ++extern struct snd_soc_codec_dai twl4030_dai; ++extern struct snd_soc_codec_device soc_codec_dev_twl4030; ++ ++#endif /* End of __TWL4030_AUDIO_H__ */ diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/ASoC-machine-driver-for-OMAP3-EVM.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/ASoC-machine-driver-for-OMAP3-EVM.patch new file mode 100644 index 0000000000..ea8108e090 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/ASoC-machine-driver-for-OMAP3-EVM.patch @@ -0,0 +1,278 @@ +From: Steve Sakoman <steve@sakoman.com> +Date: Fri, 18 Jul 2008 16:41:37 +0000 (-0700) +Subject: ASoC machine driver for OMAP3 EVM +X-Git-Url: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=commitdiff_plain;h=2e6af042b4af677e62e32d048e770f6755e67a7f + +ASoC machine driver for OMAP3 EVM + +Add basic audio support for OMAP3 EVM + +Signed-off-by: Steve Sakoman <steve@sakoman.com> +--- + +diff --git a/arch/arm/configs/omap3_beagle_defconfig b/arch/arm/configs/omap3_beagle_defconfig +index cce83e5..a48780a 100644 +--- a/arch/arm/configs/omap3_beagle_defconfig ++++ b/arch/arm/configs/omap3_beagle_defconfig +@@ -735,7 +735,82 @@ CONFIG_FONT_8x16=y + # + # Sound + # +-# CONFIG_SOUND is not set ++CONFIG_SOUND=y ++ ++# ++# Advanced Linux Sound Architecture ++# ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_HWDEP=y ++CONFIG_SND_RAWMIDI=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++CONFIG_SND_VERBOSE_PRINTK=y ++CONFIG_SND_DEBUG=y ++CONFIG_SND_DEBUG_DETECT=y ++CONFIG_SND_PCM_XRUN_DEBUG=y ++ ++# ++# Generic devices ++# ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# ALSA ARM devices ++# ++# CONFIG_SND_OMAP_AIC23 is not set ++# CONFIG_SND_OMAP_TSC2101 is not set ++# CONFIG_SND_SX1 is not set ++# CONFIG_SND_OMAP_TSC2102 is not set ++# CONFIG_SND_OMAP24XX_EAC is not set ++ ++# ++# SPI devices ++# ++ ++# ++# USB devices ++# ++CONFIG_SND_USB_AUDIO=y ++# CONFIG_SND_USB_CAIAQ is not set ++ ++# ++# System on Chip audio support ++# ++CONFIG_SND_SOC=y ++ ++# ++# ALSA SoC audio for Freescale SOCs ++# ++ ++# ++# SoC Audio for the Texas Instruments OMAP ++# ++CONFIG_SND_OMAP_SOC=y ++CONFIG_SND_OMAP_SOC_MCBSP=y ++CONFIG_SND_OMAP_SOC_OMAP3BEAGLE=y ++CONFIG_SND_SOC_TWL4030=y ++ ++# ++# Open Sound System ++# ++CONFIG_SOUND_PRIME=y ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++# CONFIG_HID_DEBUG is not set ++# CONFIG_HIDRAW is not set ++ + # CONFIG_HID_SUPPORT is not set + CONFIG_USB_SUPPORT=y + CONFIG_USB_ARCH_HAS_HCD=y +diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig +index 0230d83..0def5ba 100644 +--- a/sound/soc/omap/Kconfig ++++ b/sound/soc/omap/Kconfig +@@ -16,4 +16,12 @@ config SND_OMAP_SOC_N810 + help + Say Y if you want to add support for SoC audio on Nokia N810. + ++config SND_OMAP_SOC_OMAP3EVM ++ tristate "SoC Audio support for OMAP3 EVM" ++ depends on SND_OMAP_SOC && MACH_OMAP3EVM ++ select SND_OMAP_SOC_MCBSP ++ select SND_SOC_TWL4030 ++ help ++ Say Y if you want to add support for SoC audio on the OMAP3 EVM. ++ + endmenu +diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile +index d8d8d58..985eddc 100644 +--- a/sound/soc/omap/Makefile ++++ b/sound/soc/omap/Makefile +@@ -7,5 +7,8 @@ obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o + + # OMAP Machine Support + snd-soc-n810-objs := n810.o ++snd-soc-omap3evm-objs := omap3evm.o + + obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o ++obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o ++ +diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c +new file mode 100644 +index 0000000..d436bb4 +--- /dev/null ++++ b/sound/soc/omap/omap3evm.c +@@ -0,0 +1,142 @@ ++/* ++ * omap3evm.c -- SoC audio for OMAP3 EVM ++ * ++ * Author: Steve Sakoman <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include <linux/clk.h> ++#include <linux/platform_device.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++ ++#include <asm/mach-types.h> ++#include <asm/arch/hardware.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/mcbsp.h> ++ ++#include "omap-mcbsp.h" ++#include "omap-pcm.h" ++#include "../codecs/twl4030.h" ++ ++static int omap3evm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; ++ int ret; ++ ++ /* Set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set codec DAI configuration\n"); ++ return ret; ++ } ++ ++ /* Set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set cpu DAI configuration\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops omap3evm_ops = { ++ .hw_params = omap3evm_hw_params, ++}; ++ ++/* Digital audio interface glue - connects codec <--> CPU */ ++static struct snd_soc_dai_link omap3evm_dai = { ++ .name = "TWL4030", ++ .stream_name = "TWL4030", ++ .cpu_dai = &omap_mcbsp_dai[0], ++ .codec_dai = &twl4030_dai, ++ .ops = &omap3evm_ops, ++}; ++ ++/* Audio machine driver */ ++static struct snd_soc_machine snd_soc_machine_omap3evm = { ++ .name = "omap3evm", ++ .dai_link = &omap3evm_dai, ++ .num_links = 1, ++}; ++ ++/* Audio subsystem */ ++static struct snd_soc_device omap3evm_snd_devdata = { ++ .machine = &snd_soc_machine_omap3evm, ++ .platform = &omap_soc_platform, ++ .codec_dev = &soc_codec_dev_twl4030, ++}; ++ ++static struct platform_device *omap3evm_snd_device; ++ ++static int __init omap3evm_soc_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "OMAP3 EVM SoC init\n"); ++ if (!machine_is_omap3evm()) { ++ printk(KERN_INFO "Not OMAP3 EVM!\n"); ++ return -ENODEV; ++ } ++ ++ omap3evm_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!omap3evm_snd_device) { ++ printk(KERN_INFO "Platform device allocation failed\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(omap3evm_snd_device, &omap3evm_snd_devdata); ++ omap3evm_snd_devdata.dev = &omap3evm_snd_device->dev; ++ *(unsigned int *)omap3evm_dai.cpu_dai->private_data = 1; /* McBSP2 */ ++ ++ ret = platform_device_add(omap3evm_snd_device); ++ if (ret) ++ goto err1; ++ ++ return 0; ++ ++err1: ++ printk(KERN_INFO "Unable to add platform device\n"); ++ platform_device_put(omap3evm_snd_device); ++ ++ return ret; ++} ++ ++static void __exit omap3evm_soc_exit(void) ++{ ++ printk(KERN_INFO "OMAP3 EVM SoC exit\n"); ++ platform_device_unregister(omap3evm_snd_device); ++} ++ ++module_init(omap3evm_soc_init); ++module_exit(omap3evm_soc_exit); ++ ++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>"); ++MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM"); ++MODULE_LICENSE("GPL"); diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/ASoC-machine-driver-for_OMAP3-Beagle.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/ASoC-machine-driver-for_OMAP3-Beagle.patch new file mode 100644 index 0000000000..9343a9c59a --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/ASoC-machine-driver-for_OMAP3-Beagle.patch @@ -0,0 +1,279 @@ +From: Steve Sakoman <steve@sakoman.com> +Date: Fri, 18 Jul 2008 16:41:49 +0000 (-0700) +Subject: ASoC machine driver for OMAP3 Beagle +X-Git-Url: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=commitdiff_plain;h=543a3a0cd4c6f68be6f084ccfe63ec5a514eba59 + +ASoC machine driver for OMAP3 Beagle + +Add basic audio support for OMAP3 Beagle + +Signed-off-by: Steve Sakoman <steve@sakoman.com> +--- + +diff --git a/arch/arm/configs/omap3_evm_defconfig b/arch/arm/configs/omap3_evm_defconfig +index 718c914..4ac730c 100644 +--- a/arch/arm/configs/omap3_evm_defconfig ++++ b/arch/arm/configs/omap3_evm_defconfig +@@ -835,7 +835,82 @@ CONFIG_DUMMY_CONSOLE=y + # + # Sound + # +-# CONFIG_SOUND is not set ++CONFIG_SOUND=y ++ ++# ++# Advanced Linux Sound Architecture ++# ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_HWDEP=y ++CONFIG_SND_RAWMIDI=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++CONFIG_SND_VERBOSE_PRINTK=y ++CONFIG_SND_DEBUG=y ++CONFIG_SND_DEBUG_DETECT=y ++CONFIG_SND_PCM_XRUN_DEBUG=y ++ ++# ++# Generic devices ++# ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# ALSA ARM devices ++# ++# CONFIG_SND_OMAP_AIC23 is not set ++# CONFIG_SND_OMAP_TSC2101 is not set ++# CONFIG_SND_SX1 is not set ++# CONFIG_SND_OMAP_TSC2102 is not set ++# CONFIG_SND_OMAP24XX_EAC is not set ++ ++# ++# SPI devices ++# ++ ++# ++# USB devices ++# ++CONFIG_SND_USB_AUDIO=y ++# CONFIG_SND_USB_CAIAQ is not set ++ ++# ++# System on Chip audio support ++# ++CONFIG_SND_SOC=y ++ ++# ++# ALSA SoC audio for Freescale SOCs ++# ++ ++# ++# SoC Audio for the Texas Instruments OMAP ++# ++CONFIG_SND_OMAP_SOC=y ++CONFIG_SND_OMAP_SOC_MCBSP=y ++CONFIG_SND_OMAP_SOC_OMAP3EVM=y ++CONFIG_SND_SOC_TWL4030=y ++ ++# ++# Open Sound System ++# ++CONFIG_SOUND_PRIME=y ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++# CONFIG_HID_DEBUG is not set ++# CONFIG_HIDRAW is not set ++ + # CONFIG_HID_SUPPORT is not set + # CONFIG_USB_SUPPORT is not set + # CONFIG_MMC is not set +diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig +index 0def5ba..8703cea 100644 +--- a/sound/soc/omap/Kconfig ++++ b/sound/soc/omap/Kconfig +@@ -24,4 +24,12 @@ config SND_OMAP_SOC_OMAP3EVM + help + Say Y if you want to add support for SoC audio on the OMAP3 EVM. + ++config SND_OMAP_SOC_OMAP3BEAGLE ++ tristate "SoC Audio support for OMAP3 Beagle" ++ depends on SND_OMAP_SOC && MACH_OMAP3_BEAGLE ++ select SND_OMAP_SOC_MCBSP ++ select SND_SOC_TWL4030 ++ help ++ Say Y if you want to add support for SoC audio on the OMAP3 Beagle. ++ + endmenu +diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile +index 985eddc..638a240 100644 +--- a/sound/soc/omap/Makefile ++++ b/sound/soc/omap/Makefile +@@ -8,7 +8,9 @@ obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o + # OMAP Machine Support + snd-soc-n810-objs := n810.o + snd-soc-omap3evm-objs := omap3evm.o ++snd-soc-omap3beagle-objs := omap3beagle.o + + obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o + obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o ++obj-$(CONFIG_SND_OMAP_SOC_OMAP3BEAGLE) += snd-soc-omap3beagle.o + +diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c +new file mode 100644 +index 0000000..336d50a +--- /dev/null ++++ b/sound/soc/omap/omap3beagle.c +@@ -0,0 +1,142 @@ ++/* ++ * omap3beagle.c -- SoC audio for OMAP3 Beagle ++ * ++ * Author: Steve Sakoman <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include <linux/clk.h> ++#include <linux/platform_device.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++ ++#include <asm/mach-types.h> ++#include <asm/arch/hardware.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/mcbsp.h> ++ ++#include "omap-mcbsp.h" ++#include "omap-pcm.h" ++#include "../codecs/twl4030.h" ++ ++static int omap3beagle_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; ++ int ret; ++ ++ /* Set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set codec DAI configuration\n"); ++ return ret; ++ } ++ ++ /* Set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set cpu DAI configuration\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops omap3beagle_ops = { ++ .hw_params = omap3beagle_hw_params, ++}; ++ ++/* Digital audio interface glue - connects codec <--> CPU */ ++static struct snd_soc_dai_link omap3beagle_dai = { ++ .name = "TWL4030", ++ .stream_name = "TWL4030", ++ .cpu_dai = &omap_mcbsp_dai[0], ++ .codec_dai = &twl4030_dai, ++ .ops = &omap3beagle_ops, ++}; ++ ++/* Audio machine driver */ ++static struct snd_soc_machine snd_soc_machine_omap3beagle = { ++ .name = "omap3beagle", ++ .dai_link = &omap3beagle_dai, ++ .num_links = 1, ++}; ++ ++/* Audio subsystem */ ++static struct snd_soc_device omap3beagle_snd_devdata = { ++ .machine = &snd_soc_machine_omap3beagle, ++ .platform = &omap_soc_platform, ++ .codec_dev = &soc_codec_dev_twl4030, ++}; ++ ++static struct platform_device *omap3beagle_snd_device; ++ ++static int __init omap3beagle_soc_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "OMAP3 Beagle SoC init\n"); ++ if (!machine_is_omap3_beagle()) { ++ printk(KERN_INFO "Not OMAP3 Beagle!\n"); ++ return -ENODEV; ++ } ++ ++ omap3beagle_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!omap3beagle_snd_device) { ++ printk(KERN_INFO "Platform device allocation failed\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(omap3beagle_snd_device, &omap3beagle_snd_devdata); ++ omap3beagle_snd_devdata.dev = &omap3beagle_snd_device->dev; ++ *(unsigned int *)omap3beagle_dai.cpu_dai->private_data = 1; /* McBSP2 */ ++ ++ ret = platform_device_add(omap3beagle_snd_device); ++ if (ret) ++ goto err1; ++ ++ return 0; ++ ++err1: ++ printk(KERN_INFO "Unable to add platform device\n"); ++ platform_device_put(omap3beagle_snd_device); ++ ++ return ret; ++} ++ ++static void __exit omap3beagle_soc_exit(void) ++{ ++ printk(KERN_INFO "OMAP3 Beagle SoC exit\n"); ++ platform_device_unregister(omap3beagle_snd_device); ++} ++ ++module_init(omap3beagle_soc_init); ++module_exit(omap3beagle_soc_exit); ++ ++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>"); ++MODULE_DESCRIPTION("ALSA SoC OMAP3 Beagle"); ++MODULE_LICENSE("GPL"); diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/cache-display-fix.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/cache-display-fix.patch new file mode 100644 index 0000000000..c96b95f2f4 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/cache-display-fix.patch @@ -0,0 +1,238 @@ +On Tue, 2008-07-01 at 06:23 +0100, Dirk Behme wrote: +> Catalin Marinas wrote: +> > But, anyway, if you want a patch, Harry is updating it to a recent +> > kernel. +> +> Any news on this? I think there are some people wanting a patch ;) + +See below for a preliminary patch updated to 2.6.26-rc8. Note that I +don't plan to submit it in its current form but clean it up a bit first. + + +Show the cache type of ARMv7 CPUs + +From: Catalin Marinas <catalin.marinas@arm.com> + +Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> +--- + + arch/arm/kernel/setup.c | 137 +++++++++++++++++++++++++++++++++++++++++++++- + include/asm-arm/system.h | 18 ++++++ + 2 files changed, 153 insertions(+), 2 deletions(-) + + +diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c +index 5ae0eb2..0cd238d 100644 +--- a/arch/arm/kernel/setup.c ++++ b/arch/arm/kernel/setup.c +@@ -256,6 +256,24 @@ static const char *proc_arch[] = { + "?(17)", + }; + ++static const char *v7_cache_policy[4] = { ++ "reserved", ++ "AVIVT", ++ "VIPT", ++ "PIPT", ++}; ++ ++static const char *v7_cache_type[8] = { ++ "none", ++ "instruction only", ++ "data only", ++ "separate instruction and data", ++ "unified", ++ "unknown type", ++ "unknown type", ++ "unknown type", ++}; ++ + #define CACHE_TYPE(x) (((x) >> 25) & 15) + #define CACHE_S(x) ((x) & (1 << 24)) + #define CACHE_DSIZE(x) (((x) >> 12) & 4095) /* only if S=1 */ +@@ -266,6 +284,22 @@ static const char *proc_arch[] = { + #define CACHE_M(y) ((y) & (1 << 2)) + #define CACHE_LINE(y) ((y) & 3) + ++#define CACHE_TYPE_V7(x) (((x) >> 14) & 3) ++#define CACHE_UNIFIED(x) ((((x) >> 27) & 7)+1) ++#define CACHE_COHERENT(x) ((((x) >> 24) & 7)+1) ++ ++#define CACHE_ID_LEVEL_MASK 7 ++#define CACHE_ID_LEVEL_BITS 3 ++ ++#define CACHE_LINE_V7(v) ((1 << (((v) & 7)+4))) ++#define CACHE_ASSOC_V7(v) ((((v) >> 3) & ((1<<10)-1))+1) ++#define CACHE_SETS_V7(v) ((((v) >> 13) & ((1<<15)-1))+1) ++#define CACHE_SIZE_V7(v) (CACHE_LINE_V7(v)*CACHE_ASSOC_V7(v)*CACHE_SETS_V7(v)) ++#define CACHE_WA_V7(v) (((v) & (1<<28)) != 0) ++#define CACHE_RA_V7(v) (((v) & (1<<29)) != 0) ++#define CACHE_WB_V7(v) (((v) & (1<<30)) != 0) ++#define CACHE_WT_V7(v) (((v) & (1<<31)) != 0) ++ + static inline void dump_cache(const char *prefix, int cpu, unsigned int cache) + { + unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0); +@@ -279,11 +313,57 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache) + CACHE_LINE(cache))); + } + ++static void dump_v7_cache(const char *type, int cpu, unsigned int level) ++{ ++ unsigned int cachesize; ++ ++ write_extended_cpuid(2,0,0,0,level); /* Set the cache size selection register */ ++ write_extended_cpuid(0,7,5,4,0); /* Prefetch flush to wait for above */ ++ cachesize = read_extended_cpuid(1,0,0,0); ++ ++ printk("CPU%u: %s cache: %d bytes, associativity %d, %d byte lines, %d sets,\n supports%s%s%s%s\n", ++ cpu, type, ++ CACHE_SIZE_V7(cachesize),CACHE_ASSOC_V7(cachesize), ++ CACHE_LINE_V7(cachesize),CACHE_SETS_V7(cachesize), ++ CACHE_WA_V7(cachesize) ? " WA" : "", ++ CACHE_RA_V7(cachesize) ? " RA" : "", ++ CACHE_WB_V7(cachesize) ? " WB" : "", ++ CACHE_WT_V7(cachesize) ? " WT" : ""); ++} ++ + static void __init dump_cpu_info(int cpu) + { + unsigned int info = read_cpuid(CPUID_CACHETYPE); + +- if (info != processor_id) { ++ if (info != processor_id && (info & (1 << 31))) { ++ /* ARMv7 style of cache info register */ ++ unsigned int id = read_extended_cpuid(1,0,0,1); ++ unsigned int level = 0; ++ printk("CPU%u: L1 I %s cache. Caches unified at level %u, coherent at level %u\n", ++ cpu, ++ v7_cache_policy[CACHE_TYPE_V7(info)], ++ CACHE_UNIFIED(id), ++ CACHE_COHERENT(id)); ++ ++ while (id & CACHE_ID_LEVEL_MASK) { ++ printk("CPU%u: Level %u cache is %s\n", ++ cpu, (level >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]); ++ ++ if (id & 1) { ++ /* Dump I at this level */ ++ dump_v7_cache("I", cpu, level | 1); ++ } ++ ++ if (id & (4 | 2)) { ++ /* Dump D or unified at this level */ ++ dump_v7_cache((id & 4) ? "unified" : "D", cpu, level); ++ } ++ ++ /* Next level out */ ++ level += 2; ++ id >>= CACHE_ID_LEVEL_BITS; ++ } ++ } else if (info != processor_id) { + printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT", + cache_types[CACHE_TYPE(info)]); + if (CACHE_S(info)) { +@@ -916,6 +996,30 @@ c_show_cache(struct seq_file *m, const char *type, unsigned int cache) + CACHE_LINE(cache))); + } + ++static void c_show_v7_cache(struct seq_file *m, const char *type, unsigned int levelselect) ++{ ++ unsigned int cachesize; ++ unsigned int level = (levelselect >> 1) + 1; ++ ++ write_extended_cpuid(2,0,0,0,levelselect); /* Set the cache size selection register */ ++ write_extended_cpuid(0,7,5,4,0); /* Prefetch flush to wait for above */ ++ cachesize = read_extended_cpuid(1,0,0,0); ++ ++ seq_printf(m, "L%u %s size\t\t: %d bytes\n" ++ "L%u %s assoc\t\t: %d\n" ++ "L%u %s line length\t: %d\n" ++ "L%u %s sets\t\t: %d\n" ++ "L%u %s supports\t\t:%s%s%s%s\n", ++ level, type, CACHE_SIZE_V7(cachesize), ++ level, type, CACHE_ASSOC_V7(cachesize), ++ level, type, CACHE_LINE_V7(cachesize), ++ level, type, CACHE_SETS_V7(cachesize), ++ level, type, CACHE_WA_V7(cachesize) ? " WA" : "", ++ CACHE_RA_V7(cachesize) ? " RA" : "", ++ CACHE_WB_V7(cachesize) ? " WB" : "", ++ CACHE_WT_V7(cachesize) ? " WT" : ""); ++} ++ + static int c_show(struct seq_file *m, void *v) + { + int i; +@@ -971,7 +1075,36 @@ static int c_show(struct seq_file *m, void *v) + + { + unsigned int cache_info = read_cpuid(CPUID_CACHETYPE); +- if (cache_info != processor_id) { ++ if (cache_info != processor_id && (cache_info & (1<<31))) { ++ /* V7 style of cache info register */ ++ unsigned int id = read_extended_cpuid(1,0,0,1); ++ unsigned int levelselect = 0; ++ seq_printf(m, "L1 I cache\t:%s\n" ++ "Cache unification level\t: %u\n" ++ "Cache coherency level\t: %u\n", ++ v7_cache_policy[CACHE_TYPE_V7(cache_info)], ++ CACHE_UNIFIED(id), ++ CACHE_COHERENT(id)); ++ ++ while (id & CACHE_ID_LEVEL_MASK) { ++ seq_printf(m, "Level %u cache\t\t: %s\n", ++ (levelselect >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]); ++ ++ if (id & 1) { ++ /* Dump I at this level */ ++ c_show_v7_cache(m, "I", levelselect | 1); ++ } ++ ++ if (id & (4 | 2)) { ++ /* Dump D or unified at this level */ ++ c_show_v7_cache(m, (id & 4) ? "cache" : "D", levelselect); ++ } ++ ++ /* Next level out */ ++ levelselect += 2; ++ id >>= CACHE_ID_LEVEL_BITS; ++ } ++ } else if (cache_info != processor_id) { + seq_printf(m, "Cache type\t: %s\n" + "Cache clean\t: %s\n" + "Cache lockdown\t: %s\n" +diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h +index 514af79..704738e 100644 +--- a/include/asm-arm/system.h ++++ b/include/asm-arm/system.h +@@ -74,6 +74,24 @@ + : "cc"); \ + __val; \ + }) ++#define read_extended_cpuid(op1,op2,op3,op4) \ ++ ({ \ ++ unsigned int __val; \ ++ asm("mrc p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4) \ ++ : "=r" (__val) \ ++ : \ ++ : "cc"); \ ++ __val; \ ++ }) ++ ++#define write_extended_cpuid(op1,op2,op3,op4,v) \ ++ ({ \ ++ unsigned int __val = v; \ ++ asm("mcr p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4) \ ++ : \ ++ : "r" (__val) \ ++ : "cc"); \ ++ }) + #else + extern unsigned int processor_id; + #define read_cpuid(reg) (processor_id) + + +-- +Catalin + + diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/defconfig b/recipes/linux/linux-omap-2.6.26/beagleboard/defconfig new file mode 100644 index 0000000000..413167de7e --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/defconfig @@ -0,0 +1,2017 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-omap1 +# Wed Oct 22 12:01:26 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_OPROFILE_ARMV7=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_MARKERS is not set +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_LSF=y +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y +# CONFIG_ARCH_MSM7X00A is not set + +# +# TI OMAP Implementations +# +CONFIG_ARCH_OMAP_OTG=y +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_OMAP2 is not set +CONFIG_ARCH_OMAP3=y + +# +# OMAP Feature Selections +# +# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set +# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set +CONFIG_OMAP_SMARTREFLEX=y +# CONFIG_OMAP_SMARTREFLEX_TESTING is not set +CONFIG_OMAP_RESET_CLOCKS=y +CONFIG_OMAP_BOOT_TAG=y +CONFIG_OMAP_BOOT_REASON=y +# CONFIG_OMAP_COMPONENT_VERSION is not set +# CONFIG_OMAP_GPIO_SWITCH is not set +# CONFIG_OMAP_MUX is not set +CONFIG_OMAP_MCBSP=y +# CONFIG_OMAP_MMU_FWK is not set +# CONFIG_OMAP_MBOX_FWK is not set +# CONFIG_OMAP_MPU_TIMER is not set +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_32K_TIMER_HZ=128 +CONFIG_OMAP_DM_TIMER=y +# CONFIG_OMAP_LL_DEBUG_UART1 is not set +# CONFIG_OMAP_LL_DEBUG_UART2 is not set +CONFIG_OMAP_LL_DEBUG_UART3=y +# CONFIG_OMAP_PM_NONE is not set +# CONFIG_OMAP_PM_NOOP is not set +CONFIG_OMAP_PM_SRF=y +CONFIG_ARCH_OMAP34XX=y +CONFIG_ARCH_OMAP3430=y + +# +# OMAP Board Type +# +# CONFIG_MACH_OMAP_LDP is not set +# CONFIG_MACH_OMAP_3430SDP is not set +# CONFIG_MACH_OMAP3EVM is not set +CONFIG_MACH_OMAP3_BEAGLE=y +CONFIG_OMAP_TICK_GPTIMER=12 + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_IFAR=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=128 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_LEDS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE=" debug " +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPUIdle +# + +# +# CPU idle PM support +# +CONFIG_CPU_IDLE=y + +# +# Governors +# +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_DEBUG=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +CONFIG_NEON_CACHE_BUG=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +CONFIG_NET_SCH_FIFO=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIUSB=y +CONFIG_BT_HCIUSB_SCO=y +CONFIG_BT_HCIBTSDIO=y +# CONFIG_BT_HCIUART is not set +CONFIG_BT_HCIBCM203X=y +CONFIG_BT_HCIBPA10X=y +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIBRF6150 is not set +# CONFIG_BT_HCIH4P is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_NL80211=y +CONFIG_WIRELESS_EXT=y +CONFIG_MAC80211=y + +# +# Rate control algorithm selection +# +CONFIG_MAC80211_RC_DEFAULT_PID=y +# CONFIG_MAC80211_RC_DEFAULT_NONE is not set + +# +# Selecting 'y' for an algorithm will +# + +# +# build the algorithm into mac80211. +# +CONFIG_MAC80211_RC_DEFAULT="pid" +CONFIG_MAC80211_RC_PID=y +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set +# CONFIG_MAC80211_DEBUG is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_OMAP2=y +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +CONFIG_EEPROM_93CX6=m +# CONFIG_OMAP_STI is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_RAID5_RESHAPE=y +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m +# CONFIG_DM_MULTIPATH_RDAC is not set +# CONFIG_DM_MULTIPATH_HP is not set +CONFIG_DM_DELAY=m +# CONFIG_DM_UEVENT is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +CONFIG_DUMMY=m +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_MII=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_USB_ZD1201=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_RTL8187=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +# CONFIG_IWLWIFI_LEDS is not set +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_B43=m +CONFIG_B43_LEDS=y +# CONFIG_B43_DEBUG is not set +# CONFIG_B43LEGACY is not set +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_RT2X00=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_LEDS=y +CONFIG_RT2500USB=m +CONFIG_RT2500USB_LEDS=y +CONFIG_RT73USB=m +CONFIG_RT73USB_LEDS=y +# CONFIG_RT2X00_DEBUG is not set + +# +# USB Network Adapters +# +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_CDCETHER=y +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_OMAP=y +# CONFIG_I2C2_OMAP_BEAGLE is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_PCA_PLATFORM is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +CONFIG_SENSORS_EEPROM=y +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_ISP1301_OMAP is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_TLV320AIC23 is not set +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_GPIO=y +CONFIG_TWL4030_MADC=m +CONFIG_TWL4030_USB=y +CONFIG_TWL4030_USB_HS_ULPI=y +CONFIG_TWL4030_PWRBUTTON=y +CONFIG_TWL4030_POWEROFF=y +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_LP5521 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_OMAP24XX is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +CONFIG_SPI_TSC2101=y +CONFIG_SPI_TSC2102=y +# CONFIG_SPI_TSC210X is not set +# CONFIG_SPI_TSC2301 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_HAVE_GPIO_LIB=y + +# +# GPIO Support +# +# CONFIG_DEBUG_GPIO is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=m +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_BQ27x00 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_TSC210X is not set +CONFIG_SENSORS_OMAP34XX=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_OMAP_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +CONFIG_SSB=m +# CONFIG_SSB_SILENT is not set +# CONFIG_SSB_DEBUG is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_DVB_CORE=m +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_TUNER=m +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_CX25840=m +CONFIG_VIDEO_CX2341X=m +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_TUNER_3036 is not set +# CONFIG_VIDEO_AU0828 is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +# CONFIG_VIDEO_EM28XX is not set +CONFIG_VIDEO_USBVISION=m +CONFIG_VIDEO_USBVIDEO=m +CONFIG_USB_VICAM=m +CONFIG_USB_IBMCAM=m +CONFIG_USB_KONICAWC=m +CONFIG_USB_QUICKCAM_MESSENGER=m +# CONFIG_USB_ET61X251 is not set +CONFIG_VIDEO_OVCAMCHIP=m +CONFIG_USB_W9968CF=m +CONFIG_USB_OV511=m +CONFIG_USB_SE401=m +CONFIG_USB_SN9C102=m +CONFIG_USB_STV680=m +# CONFIG_USB_ZC0301 is not set +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_ZR364XX=m +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_TEA5761 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_USB_SI470X is not set +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set + +# +# Supported USB Adapters +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_DVB_CINERGYT2=m +# CONFIG_DVB_CINERGYT2_TUNING is not set + +# +# Supported FlexCopII (B2C2) Adapters +# +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_TDA10048=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_S5H1411=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_LNBP21=m +# CONFIG_DVB_ISL6405 is not set +CONFIG_DVB_ISL6421=m +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +CONFIG_FB_OMAP=y +# CONFIG_FB_OMAP_031M3R is not set +# CONFIG_FB_OMAP_048M3R is not set +CONFIG_FB_OMAP_079M3R=y +# CONFIG_FB_OMAP_092M9R is not set +# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set +# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set +CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=8 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# ALSA ARM devices +# +# CONFIG_SND_OMAP_AIC23 is not set +# CONFIG_SND_OMAP_TSC2101 is not set +# CONFIG_SND_SX1 is not set +# CONFIG_SND_OMAP_TSC2102 is not set +# CONFIG_SND_OMAP24XX_EAC is not set + +# +# SPI devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y + +# +# System on Chip audio support +# +CONFIG_SND_SOC=y + +# +# ALSA SoC audio for Freescale SOCs +# + +# +# SoC Audio for the Texas Instruments OMAP +# +CONFIG_SND_OMAP_SOC=y +CONFIG_SND_OMAP_SOC_MCBSP=y +CONFIG_SND_OMAP_SOC_OMAP3BEAGLE=y +CONFIG_SND_SOC_TWL4030=y + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_OMAP_EHCI_PHY_MODE=y +# CONFIG_OMAP_EHCI_TLL_MODE is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_SOC=y + +# +# OMAP 343x high speed USB support +# +# CONFIG_USB_MUSB_HOST is not set +# CONFIG_USB_MUSB_PERIPHERAL is not set +CONFIG_USB_MUSB_OTG=y +CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_USB_MUSB_HDRC_HCD=y +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_USB_INVENTRA_DMA=y +CONFIG_MUSB_USE_SYSTEM_DMA_RX=y +# CONFIG_USB_TI_CPPI_DMA is not set +CONFIG_USB_MUSB_LOGLEVEL=0 + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +CONFIG_USB_EZUSB=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_AIRPRIME=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP2101=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_FUNSOFT=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_MPR=y +CONFIG_USB_SERIAL_KEYSPAN_USA28=y +CONFIG_USB_SERIAL_KEYSPAN_USA28X=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y +CONFIG_USB_SERIAL_KEYSPAN_USA19=y +CONFIG_USB_SERIAL_KEYSPAN_USA18X=y +CONFIG_USB_SERIAL_KEYSPAN_USA19W=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y +CONFIG_USB_SERIAL_KEYSPAN_USA49W=y +CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MOTOROLA=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_HP4X=m +CONFIG_USB_SERIAL_SAFE=m +# CONFIG_USB_SERIAL_SAFE_PADDED is not set +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_DEBUG=m + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +# CONFIG_USB_BERRY_CHARGE is not set +CONFIG_USB_LED=m +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +CONFIG_USB_ETH=y +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=y +# CONFIG_MMC_TEST is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_OMAP_HS=y +CONFIG_MMC_SPI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_OMAP_DEBUG is not set +# CONFIG_LEDS_OMAP is not set +# CONFIG_LEDS_OMAP_PWM is not set +CONFIG_LEDS_GPIO=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +CONFIG_RTC_DRV_TWL4030=y +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_UIO is not set + +# +# CBUS support +# +# CONFIG_CBUS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_BIND34 is not set +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_CRYPTD=m +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=m +CONFIG_CRYPTO_XCBC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=m +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y 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Rullgard <mans@mansr.com> +Date: Tue, 22 Jul 2008 00:31:11 +0000 (+0100) +Subject: ARM: OMAP: make dpll4_m4_ck programmable with clk_set_rate() +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=2b7b958dc79e51127d7a4ecf88ce12dbc6c31426 + +ARM: OMAP: make dpll4_m4_ck programmable with clk_set_rate() + +Filling the set_rate and round_rate fields of dpll4_m4_ck makes +this clock programmable through clk_set_rate(). This is needed +to give omapfb control over the dss1_alwon_fck rate. +--- + +diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h +index 161da12..876eb13 100644 +--- a/arch/arm/mach-omap2/clock34xx.h ++++ b/arch/arm/mach-omap2/clock34xx.h +@@ -815,6 +815,8 @@ static struct clk dpll4_m4_ck = { + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, ++ .set_rate = &omap2_clksel_set_rate, ++ .round_rate = &omap2_clksel_round_rate, + }; + + /* The PWRDN bit is apparently only available on 3430ES2 and above */ diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/mru-clocks2.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/mru-clocks2.diff new file mode 100644 index 0000000000..c8b370da03 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/mru-clocks2.diff @@ -0,0 +1,62 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Tue, 22 Jul 2008 00:58:18 +0000 (+0100) +Subject: ARM: OMAP: add clk_get_parent() for OMAP2/3 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=e2de5e5578fbaa9b4b75074796da0608fc93e6ae + +ARM: OMAP: add clk_get_parent() for OMAP2/3 + +Signed-off-by: Mans Rullgard <mans@mansr.com> +--- + +diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c +index 577be44..28aec36 100644 +--- a/arch/arm/mach-omap2/clock.c ++++ b/arch/arm/mach-omap2/clock.c +@@ -824,6 +824,11 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) + return 0; + } + ++struct clk *omap2_clk_get_parent(struct clk *clk) ++{ ++ return clk->parent; ++} ++ + /* DPLL rate rounding code */ + + /** +diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h +index 49245f7..4aa69d5 100644 +--- a/arch/arm/mach-omap2/clock.h ++++ b/arch/arm/mach-omap2/clock.h +@@ -29,6 +29,7 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate); + int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); + int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); + long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); ++struct clk *omap2_clk_get_parent(struct clk *clk); + + #ifdef CONFIG_OMAP_RESET_CLOCKS + void omap2_clk_disable_unused(struct clk *clk); +diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c +index 54cc6e1..ed7af21 100644 +--- a/arch/arm/mach-omap2/clock24xx.c ++++ b/arch/arm/mach-omap2/clock24xx.c +@@ -422,6 +422,7 @@ static struct clk_functions omap2_clk_functions = { + .clk_round_rate = omap2_clk_round_rate, + .clk_set_rate = omap2_clk_set_rate, + .clk_set_parent = omap2_clk_set_parent, ++ .clk_get_parent = omap2_clk_get_parent, + .clk_disable_unused = omap2_clk_disable_unused, + #ifdef CONFIG_CPU_FREQ + .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, +diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c +index 04dedec..08c8c46 100644 +--- a/arch/arm/mach-omap2/clock34xx.c ++++ b/arch/arm/mach-omap2/clock34xx.c +@@ -541,6 +541,7 @@ static struct clk_functions omap2_clk_functions = { + .clk_round_rate = omap2_clk_round_rate, + .clk_set_rate = omap2_clk_set_rate, + .clk_set_parent = omap2_clk_set_parent, ++ .clk_get_parent = omap2_clk_get_parent, + .clk_disable_unused = omap2_clk_disable_unused, + }; + diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/mru-clocks3.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/mru-clocks3.diff new file mode 100644 index 0000000000..f8407fc2d5 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/mru-clocks3.diff @@ -0,0 +1,94 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Wed, 23 Jul 2008 08:40:07 +0000 (+0100) +Subject: ARM: OMAP: Set DSS1_ALWON_FCLK to a multiple of the pixel clock +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=01ee28c50701caa94739e764c3dae9298edd8216 + +ARM: OMAP: Set DSS1_ALWON_FCLK to a multiple of the pixel clock + +This sets the DSS1_ALWON_FCLK clock as close as possible to a +multiple of the requested pixel clock, while keeping it below +the 173MHz limit. + +Due to of the structure of the clock tree, dss1_alwon_fck cannot +be set directly, and we must use dpll4_m4_ck instead. + +Signed-off-by: Mans Rullgard <mans@mansr.com> +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index fd06ca2..e0e8528 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -176,6 +176,7 @@ static struct { + + struct clk *dss_ick, *dss1_fck; + struct clk *dss_54m_fck; ++ struct clk *dpll4_m4_ck; + + enum omapfb_update_mode update_mode; + struct omapfb_device *fbdev; +@@ -738,21 +739,34 @@ static void setup_color_conv_coef(void) + MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range); + } + +-#define MAX_FCK_LCD 173000000 ++#define MAX_FCK 173000000 + + static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div) + { ++ unsigned long prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck)); ++ unsigned long pcd_min = is_tft? 2: 3; ++ unsigned long fck_div; + unsigned long fck, lck; + + pck = max(1, pck); ++ ++ if (pck * pcd_min > MAX_FCK) { ++ dev_warn(dispc.fbdev->dev, "pixclock %d kHz too high.\n", ++ pck / 1000); ++ pck = MAX_FCK / pcd_min; ++ } ++ ++ fck = pck * 2; ++ fck_div = (prate + pck) / fck; ++ if (fck_div > 16) ++ fck_div /= (fck_div + 15) / 16; ++ if (fck_div < 1) ++ fck_div = 1; ++ clk_set_rate(dispc.dpll4_m4_ck, prate / fck_div); + fck = clk_get_rate(dispc.dss1_fck); +- *lck_div = (fck + MAX_FCK_LCD - 1) / MAX_FCK_LCD; +- lck = fck / *lck_div; +- *pck_div = (lck + pck - 1) / pck; +- if (is_tft) +- *pck_div = max(2, *pck_div); +- else +- *pck_div = max(3, *pck_div); ++ ++ *lck_div = 1; ++ *pck_div = (fck + pck - 1) / pck; + if (*pck_div > 255) { + *pck_div = 255; + lck = pck * *pck_div; +@@ -914,11 +928,21 @@ static int get_dss_clocks(void) + return PTR_ERR(dispc.dss_54m_fck); + } + ++ if (IS_ERR((dispc.dpll4_m4_ck = ++ clk_get(dispc.fbdev->dev, "dpll4_m4_ck")))) { ++ dev_err(dispc.fbdev->dev, "can't get dpll4_m4_ck"); ++ clk_put(dispc.dss_ick); ++ clk_put(dispc.dss1_fck); ++ clk_put(dispc.dss_54m_fck); ++ return PTR_ERR(dispc.dss_54m_fck); ++ } ++ + return 0; + } + + static void put_dss_clocks(void) + { ++ clk_put(dispc.dpll4_m4_ck); + clk_put(dispc.dss_54m_fck); + clk_put(dispc.dss1_fck); + clk_put(dispc.dss_ick); diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/musb-dmafix.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/musb-dmafix.patch new file mode 100644 index 0000000000..968cc6cf73 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/musb-dmafix.patch @@ -0,0 +1,275 @@ +From: Gadiyar, Anand <gadiyar@ti.com> +Date: Wed, 13 Aug 2008 07:05:29 +0000 (+0530) +Subject: MUSB: Workaround for simultaneous TX and RX usage +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=2e6aa4efb0e14c51ff0427927b1b38136911fa93 + +MUSB: Workaround for simultaneous TX and RX usage + +MUSB: Workaround for simultaneous TX and RX usage + +MUSB RTL V1.4 has a hardware issue which results in a DMA controller +hang when TX and RX DMA channels are simultaneously enabled. This +affects at least OMAP2430 and OMAP34XX. + +Since RX transfers are in Mode 0 and anyway result in one DMA interrupt +per packet, we can use System DMA to unload the RX fifos. MUSB DMA can +be used for all TX channels as before. + +Tested with full-duplex TX and RX transfers using g_ether. Runs for 24 +hours without a hang. Without this patch, the hang occurs within minutes. + +This issue was first reported by Jon Hunter on [1] + +[1] http://marc.info/?l=linux-omap&m=119634480534453&w=2 + +Signed-off-by: Anand Gadiyar <gadiyar@ti.com> +--- + +diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig +index a485a86..8583e54 100644 +--- a/drivers/usb/musb/Kconfig ++++ b/drivers/usb/musb/Kconfig +@@ -150,6 +150,14 @@ config USB_INVENTRA_DMA + help + Enable DMA transfers using Mentor's engine. + ++config MUSB_USE_SYSTEM_DMA_RX ++ bool 'Use System DMA for RX endpoints' ++ depends on USB_MUSB_HDRC && USB_INVENTRA_DMA ++ help ++ MUSB RTL version 1.4 has a hardware issue when TX and RX DMA ++ channels are simultaneously enabled. To work around this issue, ++ you can choose to use System DMA for RX channels. ++ + config USB_TI_CPPI_DMA + bool + depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY +diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c +index 32bb1e2..d1c1ea0 100644 +--- a/drivers/usb/musb/musbhsdma.c ++++ b/drivers/usb/musb/musbhsdma.c +@@ -34,6 +34,7 @@ + #include <linux/interrupt.h> + #include <linux/platform_device.h> + #include "musb_core.h" ++#include <asm/arch/dma.h> + + #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) + #include "omap2430.h" +@@ -64,6 +65,9 @@ + + #define MUSB_HSDMA_CHANNELS 8 + ++#define MUSB_FIFO_ADDRESS(epnum) \ ++ ((unsigned long) (OMAP_HSOTG_BASE + MUSB_FIFO_OFFSET(epnum))) ++ + struct musb_dma_controller; + + struct musb_dma_channel { +@@ -75,6 +79,8 @@ struct musb_dma_channel { + u8 bIndex; + u8 epnum; + u8 transmit; ++ ++ int sysdma_channel; + }; + + struct musb_dma_controller { +@@ -93,6 +99,42 @@ static int dma_controller_start(struct dma_controller *c) + return 0; + } + ++#ifdef CONFIG_MUSB_USE_SYSTEM_DMA_RX ++static void musb_sysdma_completion(int lch, u16 ch_status, void *data) ++{ ++ u32 dwAddress; ++ unsigned long flags; ++ ++ struct dma_channel *pChannel; ++ ++ struct musb_dma_channel *pImplChannel = ++ (struct musb_dma_channel *) data; ++ struct musb_dma_controller *controller = pImplChannel->controller; ++ struct musb *musb = controller->pDmaPrivate; ++ pChannel = &pImplChannel->Channel; ++ ++ DBG(2, "lch = 0x%d, ch_status = 0x%x\n", lch, ch_status); ++ spin_lock_irqsave(&musb->lock, flags); ++ ++ dwAddress = (u32) omap_get_dma_dst_pos(pImplChannel->sysdma_channel); ++ pChannel->actual_len = dwAddress - pImplChannel->dwStartAddress; ++ ++ DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n", ++ pChannel, pImplChannel->dwStartAddress, dwAddress, ++ pChannel->actual_len, pImplChannel->len, ++ (pChannel->actual_len < pImplChannel->len) ? ++ "=> reconfig 0": "=> complete"); ++ ++ pChannel->status = MUSB_DMA_STATUS_FREE; ++ musb_dma_completion(musb, pImplChannel->epnum, pImplChannel->transmit); ++ ++ spin_unlock_irqrestore(&musb->lock, flags); ++ return; ++} ++#else ++#define musb_sysdma_completion NULL ++#endif ++ + static void dma_channel_release(struct dma_channel *pChannel); + + static int dma_controller_stop(struct dma_controller *c) +@@ -144,6 +186,29 @@ static struct dma_channel *dma_channel_allocate(struct dma_controller *c, + /* Tx => mode 1; Rx => mode 0 */ + pChannel->desired_mode = transmit; + pChannel->actual_len = 0; ++ pImplChannel->sysdma_channel = -1; ++ ++#ifdef CONFIG_MUSB_USE_SYSTEM_DMA_RX ++ if (!transmit) { ++ int ret; ++ ret = omap_request_dma(OMAP24XX_DMA_NO_DEVICE, ++ "MUSB SysDMA", musb_sysdma_completion, ++ (void *) pImplChannel, ++ &(pImplChannel->sysdma_channel)); ++ ++ if (ret) { ++ printk(KERN_ERR "request_dma failed:" ++ " %d\n", ret); ++ controller->bmUsedChannels &= ++ ~(1 << bBit); ++ pChannel->status = ++ MUSB_DMA_STATUS_UNKNOWN; ++ pImplChannel->sysdma_channel = -1; ++ pChannel = NULL; ++ } ++ } ++#endif ++ + break; + } + } +@@ -163,6 +228,12 @@ static void dma_channel_release(struct dma_channel *pChannel) + ~(1 << pImplChannel->bIndex); + + pChannel->status = MUSB_DMA_STATUS_UNKNOWN; ++ ++ if (pImplChannel->sysdma_channel != -1) { ++ omap_stop_dma(pImplChannel->sysdma_channel); ++ omap_free_dma(pImplChannel->sysdma_channel); ++ pImplChannel->sysdma_channel = -1; ++ } + } + + static void configure_channel(struct dma_channel *pChannel, +@@ -179,41 +250,69 @@ static void configure_channel(struct dma_channel *pChannel, + DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", + pChannel, packet_sz, dma_addr, len, mode); + +- if (mode) { +- csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; +- BUG_ON(len < packet_sz); ++ if (pImplChannel->sysdma_channel != -1) { ++ /* System DMA */ ++ /* RX: set src = FIFO */ ++ ++ omap_set_dma_transfer_params(pImplChannel->sysdma_channel, ++ OMAP_DMA_DATA_TYPE_S8, ++ len, 1, /* One frame */ ++ OMAP_DMA_SYNC_ELEMENT, ++ OMAP24XX_DMA_NO_DEVICE, ++ 0); /* Src Sync */ ++ ++ omap_set_dma_src_params(pImplChannel->sysdma_channel, 0, ++ OMAP_DMA_AMODE_CONSTANT, ++ MUSB_FIFO_ADDRESS(pImplChannel->epnum), ++ 0, 0); + +- if (packet_sz >= 64) { +- csr |= MUSB_HSDMA_BURSTMODE_INCR16 ++ omap_set_dma_dest_params(pImplChannel->sysdma_channel, 0, ++ OMAP_DMA_AMODE_POST_INC, dma_addr, ++ 0, 0); ++ ++ omap_set_dma_dest_data_pack(pImplChannel->sysdma_channel, 1); ++ omap_set_dma_dest_burst_mode(pImplChannel->sysdma_channel, ++ OMAP_DMA_DATA_BURST_16); ++ ++ omap_start_dma(pImplChannel->sysdma_channel); ++ ++ } else { /* Mentor DMA */ ++ if (mode) { ++ csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; ++ BUG_ON(len < packet_sz); ++ ++ if (packet_sz >= 64) { ++ csr |= MUSB_HSDMA_BURSTMODE_INCR16 + << MUSB_HSDMA_BURSTMODE_SHIFT; +- } else if (packet_sz >= 32) { +- csr |= MUSB_HSDMA_BURSTMODE_INCR8 ++ } else if (packet_sz >= 32) { ++ csr |= MUSB_HSDMA_BURSTMODE_INCR8 + << MUSB_HSDMA_BURSTMODE_SHIFT; +- } else if (packet_sz >= 16) { +- csr |= MUSB_HSDMA_BURSTMODE_INCR4 ++ } else if (packet_sz >= 16) { ++ csr |= MUSB_HSDMA_BURSTMODE_INCR4 + << MUSB_HSDMA_BURSTMODE_SHIFT; ++ } + } +- } + +- csr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) +- | (1 << MUSB_HSDMA_ENABLE_SHIFT) +- | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) +- | (pImplChannel->transmit +- ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) +- : 0); +- +- /* address/count */ +- musb_writel(mbase, +- MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS), +- dma_addr); +- musb_writel(mbase, +- MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT), +- len); +- +- /* control (this should start things) */ +- musb_writew(mbase, +- MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL), +- csr); ++ csr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) ++ | (1 << MUSB_HSDMA_ENABLE_SHIFT) ++ | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) ++ | (pImplChannel->transmit ++ ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) ++ : 0); ++ ++ /* address/count */ ++ musb_writel(mbase, ++ MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS), ++ dma_addr); ++ musb_writel(mbase, ++ MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT), ++ len); ++ ++ /* control (this should start things) */ ++ musb_writew(mbase, ++ MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL), ++ csr); ++ } /* Mentor DMA */ + } + + static int dma_channel_program(struct dma_channel *pChannel, +@@ -265,6 +364,12 @@ static int dma_channel_abort(struct dma_channel *pChannel) + MUSB_EP_OFFSET(pImplChannel->epnum, MUSB_TXCSR), + csr); + } else { ++ if (pImplChannel->sysdma_channel != -1) { ++ omap_stop_dma(pImplChannel->sysdma_channel); ++ omap_free_dma(pImplChannel->sysdma_channel); ++ pImplChannel->sysdma_channel = -1; ++ } ++ + csr = musb_readw(mbase, + MUSB_EP_OFFSET(pImplChannel->epnum, MUSB_RXCSR)); + csr &= ~(MUSB_RXCSR_AUTOCLEAR | diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/no-cortex-deadlock.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/no-cortex-deadlock.patch new file mode 100644 index 0000000000..32ec4c2d33 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/no-cortex-deadlock.patch @@ -0,0 +1,75 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Wed, 30 Jul 2008 08:25:51 +0000 (+0100) +Subject: ARM: NEON L1 cache bug workaround (erratum 451034) +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=26023493baf13e0a67fd6cf08d87be5ff6f7c56d + +ARM: NEON L1 cache bug workaround (erratum 451034) + +On Cortex-A8 r1p0 and r1p1, executing a NEON store with an integer +store in the store buffer, can cause a processor deadlock under +certain conditions. + +Executing a DMB instruction before saving NEON/VFP registers and before +return to userspace makes it safe to run code which includes similar +counter-measures. Userspace code can still trigger the deadlock, so +a different workaround is required to safely run untrusted code. + +See ARM Cortex-A8 Errata Notice (PR120-PRDC-008070) for full details. +--- + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 8c75840..1172e14 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1071,6 +1071,22 @@ config NEON + Say Y to include support code for NEON, the ARMv7 Advanced SIMD + Extension. + ++config NEON_CACHE_BUG ++ bool "NEON L1 cache bug workaround (erratum 451034)" ++ depends on VFPv3 ++ help ++ On Cortex-A8 r1p0 and r1p1, executing a NEON store with an integer ++ store in the store buffer, can cause a processor deadlock under ++ certain conditions. ++ ++ See ARM Cortex-A8 Errata Notice (PR120-PRDC-008070) for full details. ++ ++ Say Y to include a workaround. ++ ++ WARNING: Even with this option enabled, userspace code can trigger ++ the deadlock. To safely run untrusted code, a different fix is ++ required. ++ + endmenu + + menu "Userspace binary formats" +diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S +index 597ed00..e50094e 100644 +--- a/arch/arm/kernel/entry-common.S ++++ b/arch/arm/kernel/entry-common.S +@@ -68,6 +68,10 @@ no_work_pending: + /* perform architecture specific actions before user return */ + arch_ret_to_user r1, lr + ++#ifdef CONFIG_NEON_CACHE_BUG ++ dmb ++#endif ++ + @ slow_restore_user_regs + ldr r1, [sp, #S_PSR] @ get calling cpsr + ldr lr, [sp, #S_PC]! @ get pc +diff --git a/include/asm-arm/vfpmacros.h b/include/asm-arm/vfpmacros.h +index cccb389..c9d2976 100644 +--- a/include/asm-arm/vfpmacros.h ++++ b/include/asm-arm/vfpmacros.h +@@ -32,6 +32,9 @@ + + @ write all the working registers out of the VFP + .macro VFPFSTMIA, base, tmp ++#ifdef CONFIG_NEON_CACHE_BUG ++ dmb ++#endif + #if __LINUX_ARM_ARCH__ < 6 + STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15} + #else diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/no-empty-flash-warnings.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/no-empty-flash-warnings.patch new file mode 100644 index 0000000000..ab344b0449 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/no-empty-flash-warnings.patch @@ -0,0 +1,15 @@ +diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c +index 1d437de..33b3feb 100644 +--- a/fs/jffs2/scan.c ++++ b/fs/jffs2/scan.c +@@ -647,8 +647,8 @@ scan_more: + inbuf_ofs = ofs - buf_ofs; + while (inbuf_ofs < scan_end) { + if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) { +- printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", +- empty_start, ofs); ++// printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", ++// empty_start, ofs); + if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start))) + return err; + goto scan_more; diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/no-harry-potter.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/no-harry-potter.diff new file mode 100644 index 0000000000..2bb20ab9c0 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/no-harry-potter.diff @@ -0,0 +1,11 @@ +--- /tmp/Makefile 2008-04-24 14:36:20.509598016 +0200 ++++ git/arch/arm/Makefile 2008-04-24 14:36:31.949546584 +0200 +@@ -47,7 +47,7 @@ + # Note that GCC does not numerically define an architecture version + # macro, but instead defines a whole series of macros which makes + # testing for a specific architecture or later rather impossible. +-arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a) ++arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a) + arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6) + # Only override the compiler option if ARMv6. The ARMv6K extensions are + # always available in ARMv7 diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/omap23-pm-noop.eml b/recipes/linux/linux-omap-2.6.26/beagleboard/omap23-pm-noop.eml new file mode 100644 index 0000000000..48ff5da822 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/omap23-pm-noop.eml @@ -0,0 +1,894 @@ +The interface provides device drivers, CPUFreq, and DSP Bridge with a +means of controlling OMAP power management parameters that are not yet +supported by the Linux PM PMQOS interface. Copious documentation and +rationale is in the patch in Documentation/arm/OMAP/omap_pm and the +interface header file, include/asm-arm/arch-omap/omap-pm.h. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + Documentation/arm/OMAP/omap_pm | 185 +++++++++++++++++++++ + arch/arm/mach-omap2/io.c | 4 + arch/arm/plat-omap/Kconfig | 13 + + arch/arm/plat-omap/Makefile | 1 + arch/arm/plat-omap/omap-pm-noop.c | 309 +++++++++++++++++++++++++++++++++++ + include/asm-arm/arch-omap/omap-pm.h | 300 ++++++++++++++++++++++++++++++++++ + 6 files changed, 812 insertions(+), 0 deletions(-) + create mode 100644 Documentation/arm/OMAP/omap_pm + create mode 100644 arch/arm/plat-omap/omap-pm-noop.c + create mode 100644 include/asm-arm/arch-omap/omap-pm.h + +diff --git a/Documentation/arm/OMAP/omap_pm b/Documentation/arm/OMAP/omap_pm +new file mode 100644 +index 0000000..2ec2034 +--- /dev/null ++++ b/Documentation/arm/OMAP/omap_pm +@@ -0,0 +1,185 @@ ++ ++Rationale: the OMAP PM interface ++================================ ++ ++ ++Existing PM interfaces are currently not ideal for OMAP ++------------------------------------------------------- ++ ++There are two PM interfaces in use with publicly-distributed OMAP ++Linux code: the TI Shared Resource Framework (SRF) and the Linux PM ++QoS parameters code. Neither interface is ideal for Linux OMAP code. ++ ++TI Shared Resource Framework: ++ ++The TI CDP 12.14 tree drivers currently use the TI Shared Resource ++Framework (SRF) to control chip power management. Use of the SRF ++allowed TI to get the drivers up and running quickly with considerable ++power savings; and the SRF provided debugging support. However, many ++of the SRF parameters are specified in OMAP-specific terms, such as ++target OPPs, rather than in terms of actual latency or throughput ++requirements. OPPs change depending on OMAP silicon revisions or OMAP ++types, and are meaningless for other architectures, so drivers shared ++between OMAP and other architectures would also have to #ifdef out the ++SRF constraints. ++ ++Linux PM QoS parameters: ++ ++In February 2008, the mainline Linux kernel added code that is ++somewhat similar to the SRF: the Linux PM QoS parameters code, located ++in kernel/pm_qos_params.c. (This code replaced the latency management ++code that was present in earlier kernels.) Ideally, OMAP drivers ++would be able to use this Linux PM QoS code directly, but the PM QoS ++code has some drawbacks: ++ ++- It combines some power management parameters that should be kept ++ separate for maximum power savings on OMAP3. For example, in the PM ++ QoS code, CPU and system DMA wakeup latency are combined into one ++ parameter; but on OMAP3, these are distinct parameters. The Linux ++ PM QoS code also combines all network power management knobs into ++ two non-device-specific parameters. OMAP2/3 systems can have ++ different network devices with different power management ++ requirements - for example, a wired Ethernet interface may have ++ different latency and throughput constraints than a WiFi interface. ++ ++- It does not yet cover all of the power management capabilities of ++ the OMAP3 architecture. It does not express latency constraints on ++ a per-device or per-powerdomain basis; it only covers ++ cpu_dma_latency and network throughput and latency, which would not ++ cover most of the OMAP3 devices. ++ ++The result is that drivers using the current Linux PM QoS layer ++directly are unlikely to reach the same level of power efficiency as ++driver code using the Shared Resource Framework. ++ ++To summarize, the SRF provides significant power savings, but ++expresses power constraints in an OMAP- and silicon-revision-specific ++way; and the PM QoS layer expresses PM constraints in a cross-platform ++manner (in terms of fundamental physical units), but does not support ++per-powerdomain constraints and does not cover many of the OMAP power ++management features. ++ ++ ++A medium-term alternative: the OMAP PM interface ++------------------------------------------------ ++ ++We need a way for driver code to express PM parameters which: ++ ++- supports the range of power management parameters present in the TI SRF; ++ ++- separates the drivers from the underlying PM parameter ++ implementation, whether it is the TI SRF or Linux PM QoS or Linux ++ latency framework or something else; ++ ++- specifies PM parameters in terms of fundamental units, such as ++ latency and throughput, rather than units which are specific to OMAP ++ or to particular OMAP variants; ++ ++- allows drivers which are shared with other architectures (e.g., ++ DaVinci) to add these constraints in a way which won't affect non-OMAP ++ systems, ++ ++- can be implemented immediately with minimal disruption of other ++ architectures. ++ ++ ++We therefore propose the OMAP PM interface, including the following ++four power management functions for driver code: ++ ++1. Set the maximum MPU wakeup latency: ++ (*pdata->set_max_mpu_wakeup_lat)(struct device *dev, unsigned long t) ++ ++2. Set the maximum device wakeup latency: ++ (*pdata->set_max_dev_wakeup_lat)(struct device *dev, unsigned long t) ++ ++3. Set the maximum system DMA transfer start latency (CORE pwrdm): ++ (*pdata->set_max_sdma_lat)(struct device *dev, long t) ++ ++4. Set the minimum bus throughput needed by a device: ++ (*pdata->set_min_bus_tput)(struct device *dev, u8 agent_id, unsigned long r) ++ ++ ++These functions are extensively documented in the OMAP PM interface header ++file, included in the patch. ++ ++ ++The OMAP PM layer is intended to be temporary ++--------------------------------------------- ++ ++The intention is that, in time, the Linux PM QoS layer should support ++the range of power management features present in OMAP3. As this ++happens, existing drivers using the OMAP PM interface can be modified ++to use the Linux PM QoS code; and the OMAP PM interface can disappear. ++ ++ ++Driver usage of the OMAP PM functions ++------------------------------------- ++ ++As the 'pdata' in the above examples indicates, these functions are ++exposed to drivers through function pointers in driver .platform_data ++structures. The function pointers are initialized by the board-*.c ++files to point to the corresponding OMAP PM functions: ++.set_max_dev_wakeup_lat will point to ++omap_pm_set_max_dev_wakeup_lat(), etc. Other architectures which do ++not support these functions should leave these function pointers set ++to NULL. Drivers should use the following idiom: ++ ++ if (pdata->set_max_dev_wakeup_lat) ++ (*pdata->set_max_dev_wakeup_lat)(dev, t); ++ ++The most common usage of these functions will probably be to specify ++the maximum time from when an interrupt occurs, to when the device ++becomes accessible. To accomplish this, driver writers should use the ++set_max_mpu_wakeup_lat() function to to constrain the MPU wakeup ++latency, and the set_max_dev_wakeup_lat() function to constrain the ++device wakeup latency (from clk_enable() to accessibility). For ++example, ++ ++ /* Limit MPU wakeup latency */ ++ if (pdata->set_max_mpu_wakeup_lat) ++ (*pdata->set_max_mpu_wakeup_lat)(dev, tc); ++ ++ /* Limit device powerdomain wakeup latency */ ++ if (pdata->set_max_dev_wakeup_lat) ++ (*pdata->set_max_dev_wakeup_lat)(dev, td); ++ ++ /* total wakeup latency in this example: (tc + td) */ ++ ++ ++The PM parameters can be overwritten by calling the function again ++with the new value. The settings can be removed by calling the ++function with a t argument of -1 (except in the case of ++set_max_bus_tput(), which should be called with an r argument of 0). ++ ++ ++Other specialized interface functions ++------------------------------------- ++ ++The four functions listed above are intended to be usable by any ++device driver. However, DSPBridge and CPUFreq have special ++requirements. DSPBridge expresses target DSP performance levels in ++terms of OPP IDs. CPUFreq expresses target MPU performance levels in ++terms of MPU frequency. The OMAP PM interface contains functions for ++these specialized cases to convert that input information (OPPs/MPU ++frequency) into the form that the underlying power management ++implementation needs: ++ ++5. (*pdata->omap_pm_dsp_get_opp_table)(void) ++ ++6. (*pdata->omap_pm_dsp_set_min_opp)(u8 opp_id) ++ ++7. (*pdata->omap_pm_dsp_get_opp)(void) ++ ++8. (*pdata->omap_pm_cpu_get_freq_table)(void) ++ ++9. (*pdata->omap_pm_cpu_set_freq)(unsigned long f) ++ ++10. (*pdata->omap_pm_cpu_get_freq)(void) ++ ++ ++There are also functions for use by the clockdomain layer to indicate ++that a powerdomain should wake up or be put to sleep: ++ ++11. (*pdata->omap_pm_pwrdm_active)(struct powerdomain *pwrdm) ++ ++12. (*pdata->omap_pm_pwrdm_inactive)(struct powerdomain *pwrdm) +diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig +index 960c13f..ca790ac 100644 +--- a/arch/arm/plat-omap/Kconfig ++++ b/arch/arm/plat-omap/Kconfig +@@ -247,4 +247,17 @@ config OMAP_SERIAL_WAKE + + endmenu + ++choice ++ prompt "OMAP PM layer selection" ++ depends on ARCH_OMAP ++ default OMAP_PM_NOOP ++ ++config OMAP_PM_NONE ++ bool "No PM layer" ++ ++config OMAP_PM_NOOP ++ bool "No-op/debug PM layer" ++ ++endchoice ++ + endif +diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile +index 93bbb64..d5453d5 100644 +--- a/arch/arm/plat-omap/Makefile ++++ b/arch/arm/plat-omap/Makefile +@@ -29,3 +29,4 @@ obj-$(CONFIG_OMAP_MMU_FWK) += mmu.o + # OMAP mailbox framework + obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o + ++obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o +\ No newline at end of file +diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c +new file mode 100644 +index 0000000..5ff7962 +--- /dev/null ++++ b/arch/arm/plat-omap/omap-pm-noop.c +@@ -0,0 +1,309 @@ ++/* ++ * omap-pm-noop.c - OMAP power management interface - dummy version ++ * ++ * This code implements the OMAP power management interface to ++ * drivers, CPUIdle, CPUFreq, and DSP Bridge. It is strictly for ++ * debug/demonstration use, as it does nothing but printk() whenever a ++ * function is called (when DEBUG is defined, below) ++ * ++ * Copyright (C) 2008 Texas Instruments, Inc. ++ * Copyright (C) 2008 Nokia Corporation ++ * Paul Walmsley ++ * ++ * Interface developed by (in alphabetical order): ++ * Karthik Dasu, Amish Lakhani, Tony Lindgren, Rajendra Nayak, Sakari ++ * Poussa, Veeramanikandan Raju, Igor Stoppa, Paul Walmsley, Richard ++ * Woodruff ++ */ ++ ++#undef DEBUG ++ ++#include <linux/init.h> ++#include <linux/cpufreq.h> ++#include <linux/device.h> ++ ++/* Interface documentation is in asm/arch/omap-pm.h */ ++#include <asm/arch/omap-pm.h> ++ ++#include <asm/arch/powerdomain.h> ++ ++static struct omap_opp *dsp_opps; ++static struct omap_opp *mpu_opps; ++ ++/* ++ * Device-driver-originated constraints (via board-*.c files) ++ */ ++ ++void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) ++{ ++ if (!dev || t < -1) { ++ WARN_ON(1); ++ return; ++ }; ++ ++ if (t == -1) ++ pr_debug("OMAP PM: remove max MPU wakeup latency constraint: " ++ "dev %s\n", dev_name(dev)); ++ else ++ pr_debug("OMAP PM: add max MPU wakeup latency constraint: " ++ "dev %s, t = %ld usec\n", dev_name(dev), t); ++ ++ /* ++ * For current Linux, this needs to map the MPU to a ++ * powerdomain, then go through the list of current max lat ++ * constraints on the MPU and find the smallest. If ++ * the latency constraint has changed, the code should ++ * recompute the state to enter for the next powerdomain ++ * state. ++ * ++ * TI CDP code can call constraint_set here. ++ */ ++} ++ ++void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) ++{ ++ if (!dev || agent_id != OCP_INITIATOR_AGENT || ++ agent_id != OCP_TARGET_AGENT) { ++ WARN_ON(1); ++ return; ++ }; ++ ++ if (r == 0) ++ pr_debug("OMAP PM: remove min bus tput constraint: " ++ "dev %s for agent_id %d\n", dev_name(dev), agent_id); ++ else ++ pr_debug("OMAP PM: add min bus tput constraint: " ++ "dev %s for agent_id %d: rate %ld KiB\n", ++ dev_name(dev), agent_id, r); ++ ++ /* ++ * This code should model the interconnect and compute the ++ * required clock frequency, convert that to a VDD2 OPP ID, then ++ * set the VDD2 OPP appropriately. ++ * ++ * TI CDP code can call constraint_set here on the VDD2 OPP. ++ */ ++} ++ ++void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t) ++{ ++ if (!dev || t < -1) { ++ WARN_ON(1); ++ return; ++ }; ++ ++ if (t == -1) ++ pr_debug("OMAP PM: remove max device latency constraint: " ++ "dev %s\n", dev_name(dev)); ++ else ++ pr_debug("OMAP PM: add max device latency constraint: " ++ "dev %s, t = %ld usec\n", dev_name(dev), t); ++ ++ /* ++ * For current Linux, this needs to map the device to a ++ * powerdomain, then go through the list of current max lat ++ * constraints on that powerdomain and find the smallest. If ++ * the latency constraint has changed, the code should ++ * recompute the state to enter for the next powerdomain ++ * state. Conceivably, this code should also determine ++ * whether to actually disable the device clocks or not, ++ * depending on how long it takes to re-enable the clocks. ++ * ++ * TI CDP code can call constraint_set here. ++ */ ++} ++ ++void omap_pm_set_max_sdma_lat(struct device *dev, long t) ++{ ++ if (!dev || t < -1) { ++ WARN_ON(1); ++ return; ++ }; ++ ++ if (t == -1) ++ pr_debug("OMAP PM: remove max DMA latency constraint: " ++ "dev %s\n", dev_name(dev)); ++ else ++ pr_debug("OMAP PM: add max DMA latency constraint: " ++ "dev %s, t = %ld usec\n", dev_name(dev), t); ++ ++ /* ++ * For current Linux PM QOS params, this code should scan the ++ * list of maximum CPU and DMA latencies and select the ++ * smallest, then set cpu_dma_latency pm_qos_param ++ * accordingly. ++ * ++ * For future Linux PM QOS params, with separate CPU and DMA ++ * latency params, this code should just set the dma_latency param. ++ * ++ * TI CDP code can call constraint_set here. ++ */ ++ ++} ++ ++ ++/* ++ * DSP Bridge-specific constraints ++ */ ++ ++const struct omap_opp *omap_pm_dsp_get_opp_table(void) ++{ ++ pr_debug("OMAP PM: DSP request for OPP table\n"); ++ ++ /* ++ * Return DSP frequency table here: The final item in the ++ * array should have .rate = .opp_id = 0. ++ */ ++ ++ return NULL; ++} ++ ++void omap_pm_dsp_set_min_opp(u8 opp_id) ++{ ++ if (opp_id == 0) { ++ WARN_ON(1); ++ return; ++ } ++ ++ pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id); ++ ++ /* ++ * ++ * For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we ++ * can just test to see which is higher, the CPU's desired OPP ++ * ID or the DSP's desired OPP ID, and use whichever is ++ * highest. ++ * ++ * In CDP12.14+, the VDD1 OPP custom clock that controls the DSP ++ * rate is keyed on MPU speed, not the OPP ID. So we need to ++ * map the OPP ID to the MPU speed for use with clk_set_rate() ++ * if it is higher than the current OPP clock rate. ++ * ++ */ ++} ++ ++ ++u8 omap_pm_dsp_get_opp(void) ++{ ++ pr_debug("OMAP PM: DSP requests current DSP OPP ID\n"); ++ ++ /* ++ * For l-o dev tree, call clk_get_rate() on VDD1 OPP clock ++ * ++ * CDP12.14+: ++ * Call clk_get_rate() on the OPP custom clock, map that to an ++ * OPP ID using the tables defined in board-*.c/chip-*.c files. ++ */ ++ ++ return 0; ++} ++ ++/* ++ * CPUFreq-originated constraint ++ * ++ * In the future, this should be handled by custom OPP clocktype ++ * functions. ++ */ ++ ++struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void) ++{ ++ pr_debug("OMAP PM: CPUFreq request for frequency table\n"); ++ ++ /* ++ * Return CPUFreq frequency table here: loop over ++ * all VDD1 clkrates, pull out the mpu_ck frequencies, build ++ * table ++ */ ++ ++ return NULL; ++} ++ ++void omap_pm_cpu_set_freq(unsigned long f) ++{ ++ if (f == 0) { ++ WARN_ON(1); ++ return; ++ } ++ ++ pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n", ++ f); ++ ++ /* ++ * For l-o dev tree, determine whether MPU freq or DSP OPP id ++ * freq is higher. Find the OPP ID corresponding to the ++ * higher frequency. Call clk_round_rate() and clk_set_rate() ++ * on the OPP custom clock. ++ * ++ * CDP should just be able to set the VDD1 OPP clock rate here. ++ */ ++} ++ ++unsigned long omap_pm_cpu_get_freq(void) ++{ ++ pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n"); ++ ++ /* ++ * Call clk_get_rate() on the mpu_ck. ++ */ ++ ++ return 0; ++} ++ ++/* ++ * Powerdomain usecounting hooks ++ */ ++ ++void omap_pm_pwrdm_active(struct powerdomain *pwrdm) ++{ ++ if (!pwrdm) { ++ WARN_ON(1); ++ return; ++ }; ++ ++ pr_debug("OMAP PM: powerdomain %s is becoming active\n", pwrdm->name); ++ ++ /* ++ * CDP code apparently will need these for the enable_power_domain() ++ * and disable_power_domain() functions. ++ */ ++} ++ ++void omap_pm_pwrdm_inactive(struct powerdomain *pwrdm) ++{ ++ if (!pwrdm) { ++ WARN_ON(1); ++ return; ++ }; ++ ++ pr_debug("OMAP PM: powerdomain %s is becoming inactive\n", ++ pwrdm->name); ++ ++ /* ++ * CDP code apparently will need these for the enable_power_domain() ++ * and disable_power_domain() functions. ++ */ ++} ++ ++/* ++ * Should be called before clk framework since clk fw will call ++ * omap_pm_pwrdm_{in,}active() ++ */ ++int __init omap_pm_if_early_init(void) ++{ ++ return 0; ++} ++ ++/* Must be called after clock framework is initialized */ ++int __init omap_pm_if_init(struct omap_opp *mpu_opp_table, ++ struct omap_opp *dsp_opp_table) ++{ ++ mpu_opps = mpu_opp_table; ++ dsp_opps = dsp_opp_table; ++ return 0; ++} ++ ++void omap_pm_if_exit(void) ++{ ++ /* Deallocate CPUFreq frequency table here */ ++} ++ +diff --git a/include/asm-arm/arch-omap/omap-pm.h b/include/asm-arm/arch-omap/omap-pm.h +new file mode 100644 +index 0000000..d272dba +--- /dev/null ++++ b/include/asm-arm/arch-omap/omap-pm.h +@@ -0,0 +1,300 @@ ++/* ++ * omap-pm.h - OMAP power management interface ++ * ++ * Copyright (C) 2008 Texas Instruments, Inc. ++ * Copyright (C) 2008 Nokia Corporation ++ * Paul Walmsley ++ * ++ * Interface developed by (in alphabetical order): Karthik Dasu, Jouni ++ * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa, ++ * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, ++ * Richard Woodruff ++ */ ++ ++#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H ++#define ASM_ARM_ARCH_OMAP_OMAP_PM_H ++ ++#include <linux/device.h> ++#include <linux/cpufreq.h> ++ ++#include "powerdomain.h" ++ ++/** ++ * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU ++ * @rate: target clock rate ++ * @opp_id: OPP ID ++ * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP ++ * ++ * Operating performance point data. Can vary by OMAP chip and board. ++ */ ++struct omap_opp { ++ unsigned long rate; ++ u8 opp_id; ++ u16 min_vdd; ++}; ++ ++/* ++ * agent_id values for use with omap_pm_set_min_bus_tput(): ++ * ++ * OCP_INITIATOR_AGENT is only valid for devices that can act as ++ * initiators -- it represents the device's L3 interconnect ++ * connection. OCP_TARGET_AGENT represents the device's L4 ++ * interconnect connection. ++ */ ++#define OCP_TARGET_AGENT 1 ++#define OCP_INITIATOR_AGENT 2 ++ ++/** ++ * omap_pm_if_early_init - OMAP PM init code called before clock fw init ++ * ++ * Initialize anything that must be configured before the clock ++ * framework starts. The "_if_" is to avoid name collisions with the ++ * PM idle-loop code. ++ */ ++int __init omap_pm_if_early_init(void); ++ ++/** ++ * omap_pm_if_init - OMAP PM init code called after clock fw init ++ * @mpu_opp_table: array ptr to struct omap_opp for MPU ++ * @dsp_opp_table: array ptr to struct omap_opp for DSP ++ * ++ * The main initialization code. OPP tables are passed in here. The ++ * "_if_" is to avoid name collisions with the PM idle-loop code. ++ */ ++int __init omap_pm_if_init(struct omap_opp *mpu_opp_table, ++ struct omap_opp *dsp_opp_table); ++ ++/** ++ * omap_pm_if_exit - OMAP PM exit code ++ * ++ * Exit code; currently unused. The "_if_" is to avoid name ++ * collisions with the PM idle-loop code. ++ */ ++void omap_pm_if_exit(void); ++ ++/* ++ * Device-driver-originated constraints (via board-*.c files, platform_data) ++ */ ++ ++ ++/** ++ * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency ++ * @dev: struct device * requesting the constraint ++ * @t: maximum MPU wakeup latency in microseconds ++ * ++ * Request that the maximum interrupt latency for the MPU to be no ++ * greater than 't' microseconds. "Interrupt latency" in this case is ++ * defined as the elapsed time from the occurrence of a hardware or ++ * timer interrupt to the time when the device driver's interrupt ++ * service routine has been entered by the MPU. ++ * ++ * It is intended that underlying PM code will use this information to ++ * determine what power state to put the MPU powerdomain into, and ++ * possibly the CORE powerdomain as well, since interrupt handling ++ * code currently runs from SDRAM. Advanced PM or board*.c code may ++ * also configure interrupt controller priorities, OCP bus priorities, ++ * CPU speed(s), etc. ++ * ++ * This function will not affect device wakeup latency, e.g., time ++ * elapsed from when a device driver enables a hardware device with ++ * clk_enable(), to when the device is ready for register access or ++ * other use. To control this device wakeup latency, use ++ * set_max_dev_wakeup_lat() ++ * ++ * Multiple calls to set_max_mpu_wakeup_lat() will replace the ++ * previous t value. To remove the latency target for the MPU, call ++ * with t = -1. ++ * ++ * No return value. ++ */ ++void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); ++ ++ ++/** ++ * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device ++ * @dev: struct device * requesting the constraint ++ * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT) ++ * @r: minimum throughput (in KiB/s) ++ * ++ * Request that the minimum data throughput on the OCP interconnect ++ * attached to device 'dev' interconnect agent 'tbus_id' be no less ++ * than 'r' KiB/s. ++ * ++ * It is expected that the OMAP PM or bus code will use this ++ * information to set the interconnect clock to run at the lowest ++ * possible speed that satisfies all current system users. The PM or ++ * bus code will adjust the estimate based on its model of the bus, so ++ * device driver authors should attempt to specify an accurate ++ * quantity for their device use case, and let the PM or bus code ++ * overestimate the numbers as necessary to handle request/response ++ * latency, other competing users on the system, etc. On OMAP2/3, if ++ * a driver requests a minimum L4 interconnect speed constraint, the ++ * code will also need to add an minimum L3 interconnect speed ++ * constraint, ++ * ++ * Multiple calls to set_min_bus_tput() will replace the previous rate ++ * value for this device. To remove the interconnect throughput ++ * restriction for this device, call with r = 0. ++ * ++ * No return value. ++ */ ++void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); ++ ++ ++/** ++ * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency ++ * @dev: struct device * ++ * @t: maximum device wakeup latency in microseconds ++ * ++ * Request that the maximum amount of time necessary for a device to ++ * become accessible after its clocks are enabled should be no greater ++ * than 't' microseconds. Specifically, this represents the time from ++ * when a device driver enables device clocks with clk_enable(), to ++ * when the register reads and writes on the device will succeed. ++ * This function should be called before clk_disable() is called, ++ * since the power state transition decision may be made during ++ * clk_disable(). ++ * ++ * It is intended that underlying PM code will use this information to ++ * determine what power state to put the powerdomain enclosing this ++ * device into. ++ * ++ * Multiple calls to set_max_dev_wakeup_lat() will replace the ++ * previous wakeup latency values for this device. To remove the wakeup ++ * latency restriction for this device, call with t = -1. ++ * ++ * No return value. ++ */ ++void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t); ++ ++ ++/** ++ * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency ++ * @dev: struct device * ++ * @t: maximum DMA transfer start latency in microseconds ++ * ++ * Request that the maximum system DMA transfer start latency for this ++ * device 'dev' should be no greater than 't' microseconds. "DMA ++ * transfer start latency" here is defined as the elapsed time from ++ * when a device (e.g., McBSP) requests that a system DMA transfer ++ * start or continue, to the time at which data starts to flow into ++ * that device from the system DMA controller. ++ * ++ * It is intended that underlying PM code will use this information to ++ * determine what power state to put the CORE powerdomain into. ++ * ++ * Since system DMA transfers may not involve the MPU, this function ++ * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do ++ * so. Similarly, this function will not affect device wakeup latency ++ * -- use set_max_dev_wakeup_lat() to affect that. ++ * ++ * Multiple calls to set_max_sdma_lat() will replace the previous t ++ * value for this device. To remove the maximum DMA latency for this ++ * device, call with t = -1. ++ * ++ * No return value. ++ */ ++void omap_pm_set_max_sdma_lat(struct device *dev, long t); ++ ++ ++/* ++ * DSP Bridge-specific constraints ++ */ ++ ++/** ++ * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table ++ * ++ * Intended for use by DSPBridge. Returns an array of OPP->DSP clock ++ * frequency entries. The final item in the array should have .rate = ++ * .opp_id = 0. ++ */ ++const struct omap_opp *omap_pm_dsp_get_opp_table(void); ++ ++/** ++ * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge ++ * @opp_id: target DSP OPP ID ++ * ++ * Set a minimum OPP ID for the DSP. This is intended to be called ++ * only from the DSP Bridge MPU-side driver. Unfortunately, the only ++ * information that code receives from the DSP/BIOS load estimator is the ++ * target OPP ID; hence, this interface. No return value. ++ */ ++void omap_pm_dsp_set_min_opp(u8 opp_id); ++ ++/** ++ * omap_pm_dsp_get_opp - report the current DSP OPP ID ++ * ++ * Report the current OPP for the DSP. Since on OMAP3, the DSP and ++ * MPU share a single voltage domain, the OPP ID returned back may ++ * represent a higher DSP speed than the OPP requested via ++ * omap_pm_dsp_set_min_opp(). ++ * ++ * Returns the current VDD1 OPP ID, or 0 upon error. ++ */ ++u8 omap_pm_dsp_get_opp(void); ++ ++ ++/* ++ * CPUFreq-originated constraint ++ * ++ * In the future, this should be handled by custom OPP clocktype ++ * functions. ++ */ ++ ++/** ++ * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr ++ * ++ * Provide a frequency table usable by CPUFreq for the current chip/board. ++ * Returns a pointer to a struct cpufreq_frequency_table array or NULL ++ * upon error. ++ */ ++struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void); ++ ++/** ++ * omap_pm_cpu_set_freq - set the current minimum MPU frequency ++ * @f: MPU frequency in Hz ++ * ++ * Set the current minimum CPU frequency. The actual CPU frequency ++ * used could end up higher if the DSP requested a higher OPP. ++ * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No ++ * return value. ++ */ ++void omap_pm_cpu_set_freq(unsigned long f); ++ ++/** ++ * omap_pm_cpu_get_freq - report the current CPU frequency ++ * ++ * Returns the current MPU frequency, or 0 upon error. ++ */ ++unsigned long omap_pm_cpu_get_freq(void); ++ ++ ++/* ++ * Powerdomain usecounting hooks ++ */ ++ ++/** ++ * omap_pm_pwrdm_active - indicate that a power domain has become active ++ * @pwrdm: struct powerdomain * ++ * ++ * Notify the OMAP PM layer that the power domain 'pwrdm' has become active, ++ * presumably due to a device driver enabling an underlying clock. This ++ * function is intended to be called by a clockdomain node in the clock ++ * framework. No return value. ++ */ ++void omap_pm_pwrdm_active(struct powerdomain *pwrdm); ++ ++ ++/** ++ * omap_pm_pwrdm_inactive - indicate that a power domain has become inactive ++ * @pwrdm: struct powerdomain * ++ * ++ * Notify the OMAP PM layer that the power domain 'pwrdm' has become ++ * inactive, presumably due to a device driver disabling an underlying ++ * clock. This function is intended to be called by a clockdomain ++ * node in the clock framework. No return value. ++ */ ++void omap_pm_pwrdm_inactive(struct powerdomain *pwrdm); ++ ++ ++#endif + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + +--- /tmp/io.c 2008-08-11 15:29:32.000000000 +0200 ++++ git/arch/arm/mach-omap2/io.c 2008-08-11 15:30:20.083198000 +0200 +@@ -38,6 +38,8 @@ + #include <asm/arch/clockdomain.h> + #include "clockdomains.h" + ++#include <asm/arch/omap-pm.h> ++ + /* + * The machine specific code may provide the extra mapping besides the + * default mapping provided here. +@@ -197,9 +199,11 @@ + void __init omap2_init_common_hw(struct omap_sdrc_params *sp) + { + omap2_mux_init(); ++ omap_pm_if_early_init(); + pwrdm_init(powerdomains_omap); + clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); + omap2_clk_init(); ++ omap_pm_if_init(NULL, NULL); + omap2_sdrc_init(sp); + gpmc_init(); + } diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/oprofile-0.9.3.armv7.diff b/recipes/linux/linux-omap-2.6.26/beagleboard/oprofile-0.9.3.armv7.diff new file mode 100644 index 0000000000..dbc11fbe7d --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/oprofile-0.9.3.armv7.diff @@ -0,0 +1,611 @@ +Hi, + +This patch adds Oprofile support on ARMv7, using the PMNC unit. +Tested on OMAP3430 SDP. + +Feedback and comments are welcome. + +The patch to user space components is attached for reference. It i applies +against version 0.9.3 of oprofile source +(http://prdownloads.sourceforge.net/oprofile/oprofile-0.9.3.tar.gz). + +Regards, +Jean. + +--- + +From: Jean Pihet <jpihet@mvista.com> +Date: Tue, 6 May 2008 17:21:44 +0200 +Subject: [PATCH] ARM: Add ARMv7 oprofile support + +Add ARMv7 Oprofile support to kernel + +Signed-off-by: Jean Pihet <jpihet@mvista.com> +--- + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index c60a27d..60b50a0 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -161,6 +161,11 @@ config OPROFILE_MPCORE + config OPROFILE_ARM11_CORE + bool + ++config OPROFILE_ARMV7 ++ def_bool y ++ depends on CPU_V7 && !SMP ++ bool ++ + endif + + config VECTORS_BASE +diff --git a/arch/arm/oprofile/Makefile b/arch/arm/oprofile/Makefile +index e61d0cc..88e31f5 100644 +--- a/arch/arm/oprofile/Makefile ++++ b/arch/arm/oprofile/Makefile +@@ -11,3 +11,4 @@ oprofile-$(CONFIG_CPU_XSCALE) += op_model_xscale.o + oprofile-$(CONFIG_OPROFILE_ARM11_CORE) += op_model_arm11_core.o + oprofile-$(CONFIG_OPROFILE_ARMV6) += op_model_v6.o + oprofile-$(CONFIG_OPROFILE_MPCORE) += op_model_mpcore.o ++oprofile-$(CONFIG_OPROFILE_ARMV7) += op_model_v7.o +diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c +index 0a5cf3a..3fcd752 100644 +--- a/arch/arm/oprofile/common.c ++++ b/arch/arm/oprofile/common.c +@@ -145,6 +145,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) + spec = &op_mpcore_spec; + #endif + ++#ifdef CONFIG_OPROFILE_ARMV7 ++ spec = &op_armv7_spec; ++#endif ++ + if (spec) { + ret = spec->init(); + if (ret < 0) +diff --git a/arch/arm/oprofile/op_arm_model.h +b/arch/arm/oprofile/op_arm_model.h +index 4899c62..8c4e4f6 100644 +--- a/arch/arm/oprofile/op_arm_model.h ++++ b/arch/arm/oprofile/op_arm_model.h +@@ -26,6 +26,7 @@ extern struct op_arm_model_spec op_xscale_spec; + + extern struct op_arm_model_spec op_armv6_spec; + extern struct op_arm_model_spec op_mpcore_spec; ++extern struct op_arm_model_spec op_armv7_spec; + + extern void arm_backtrace(struct pt_regs * const regs, unsigned int depth); + +diff --git a/arch/arm/oprofile/op_model_v7.c b/arch/arm/oprofile/op_model_v7.c +new file mode 100644 +index 0000000..a159bc1 +--- /dev/null ++++ b/arch/arm/oprofile/op_model_v7.c +@@ -0,0 +1,407 @@ ++/** ++ * @file op_model_v7.c ++ * ARM V7 (Cortex A8) Event Monitor Driver ++ * ++ * @remark Copyright 2008 Jean Pihet <jpihet@mvista.com> ++ * @remark Copyright 2004 ARM SMP Development Team ++ */ ++#include <linux/types.h> ++#include <linux/errno.h> ++#include <linux/oprofile.h> ++#include <linux/interrupt.h> ++#include <linux/irq.h> ++#include <linux/smp.h> ++ ++#include "op_counter.h" ++#include "op_arm_model.h" ++#include "op_model_v7.h" ++ ++/* #define DEBUG */ ++ ++ ++/* ++ * ARM V7 PMNC support ++ */ ++ ++static u32 cnt_en[CNTMAX]; ++ ++static inline void armv7_pmnc_write(u32 val) ++{ ++ val &= PMNC_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val)); ++} ++ ++static inline u32 armv7_pmnc_read(void) ++{ ++ u32 val; ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); ++ return val; ++} ++ ++static inline u32 armv7_pmnc_enable_counter(unsigned int cnt) ++{ ++ u32 val; ++ ++ if (cnt >= CNTMAX) { ++ printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter" ++ " %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ if (cnt == CCNT) ++ val = CNTENS_C; ++ else ++ val = (1 << (cnt - CNT0)); ++ ++ val &= CNTENS_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline u32 armv7_pmnc_disable_counter(unsigned int cnt) ++{ ++ u32 val; ++ ++ if (cnt >= CNTMAX) { ++ printk(KERN_ERR "oprofile: CPU%u disabling wrong PMNC counter" ++ " %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ if (cnt == CCNT) ++ val = CNTENC_C; ++ else ++ val = (1 << (cnt - CNT0)); ++ ++ val &= CNTENC_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline u32 armv7_pmnc_enable_intens(unsigned int cnt) ++{ ++ u32 val; ++ ++ if (cnt >= CNTMAX) { ++ printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter" ++ " interrupt enable %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ if (cnt == CCNT) ++ val = INTENS_C; ++ else ++ val = (1 << (cnt - CNT0)); ++ ++ val &= INTENS_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline u32 armv7_pmnc_getreset_flags(void) ++{ ++ u32 val; ++ ++ /* Read */ ++ asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); ++ ++ /* Write to clear flags */ ++ val &= FLAG_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); ++ ++ return val; ++} ++ ++static inline int armv7_pmnc_select_counter(unsigned int cnt) ++{ ++ u32 val; ++ ++ if ((cnt == CCNT) || (cnt >= CNTMAX)) { ++ printk(KERN_ERR "oprofile: CPU%u selecting wrong PMNC counteri" ++ " %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ val = (cnt - CNT0) & SELECT_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline void armv7_pmnc_write_evtsel(unsigned int cnt, u32 val) ++{ ++ if (armv7_pmnc_select_counter(cnt) == cnt) { ++ val &= EVTSEL_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); ++ } ++} ++ ++static void armv7_pmnc_reset_counter(unsigned int cnt) ++{ ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); ++ u32 val = -(u32)counter_config[cpu_cnt].count; ++ ++ switch (cnt) { ++ case CCNT: ++ armv7_pmnc_disable_counter(cnt); ++ ++ asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val)); ++ ++ if (cnt_en[cnt] != 0) ++ armv7_pmnc_enable_counter(cnt); ++ ++ break; ++ ++ case CNT0: ++ case CNT1: ++ case CNT2: ++ case CNT3: ++ armv7_pmnc_disable_counter(cnt); ++ ++ if (armv7_pmnc_select_counter(cnt) == cnt) ++ asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val)); ++ ++ if (cnt_en[cnt] != 0) ++ armv7_pmnc_enable_counter(cnt); ++ ++ break; ++ ++ default: ++ printk(KERN_ERR "oprofile: CPU%u resetting wrong PMNC counter" ++ " %d\n", smp_processor_id(), cnt); ++ break; ++ } ++} ++ ++int armv7_setup_pmnc(void) ++{ ++ unsigned int cnt; ++ ++ if (armv7_pmnc_read() & PMNC_E) { ++ printk(KERN_ERR "oprofile: CPU%u PMNC still enabled when setup" ++ " new event counter.\n", smp_processor_id()); ++ return -EBUSY; ++ } ++ ++ /* ++ * Initialize & Reset PMNC: C bit, D bit and P bit. ++ * Note: Using a slower count for CCNT (D bit: divide by 64) results ++ * in a more stable system ++ */ ++ armv7_pmnc_write(PMNC_P | PMNC_C | PMNC_D); ++ ++ ++ for (cnt = CCNT; cnt < CNTMAX; cnt++) { ++ unsigned long event; ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); ++ ++ /* ++ * Disable counter ++ */ ++ armv7_pmnc_disable_counter(cnt); ++ cnt_en[cnt] = 0; ++ ++ if (!counter_config[cpu_cnt].enabled) ++ continue; ++ ++ event = counter_config[cpu_cnt].event & 255; ++ ++ /* ++ * Set event (if destined for PMNx counters) ++ * We don't need to set the event if it's a cycle count ++ */ ++ if (cnt != CCNT) ++ armv7_pmnc_write_evtsel(cnt, event); ++ ++ /* ++ * Enable interrupt for this counter ++ */ ++ armv7_pmnc_enable_intens(cnt); ++ ++ /* ++ * Reset counter ++ */ ++ armv7_pmnc_reset_counter(cnt); ++ ++ /* ++ * Enable counter ++ */ ++ armv7_pmnc_enable_counter(cnt); ++ cnt_en[cnt] = 1; ++ } ++ ++ return 0; ++} ++ ++static inline void armv7_start_pmnc(void) ++{ ++ armv7_pmnc_write(armv7_pmnc_read() | PMNC_E); ++} ++ ++static inline void armv7_stop_pmnc(void) ++{ ++ armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E); ++} ++ ++/* ++ * CPU counters' IRQ handler (one IRQ per CPU) ++ */ ++static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg) ++{ ++ struct pt_regs *regs = get_irq_regs(); ++ unsigned int cnt; ++ u32 flags; ++ ++ ++ /* ++ * Stop IRQ generation ++ */ ++ armv7_stop_pmnc(); ++ ++ /* ++ * Get and reset overflow status flags ++ */ ++ flags = armv7_pmnc_getreset_flags(); ++ ++ /* ++ * Cycle counter ++ */ ++ if (flags & FLAG_C) { ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), CCNT); ++ armv7_pmnc_reset_counter(CCNT); ++ oprofile_add_sample(regs, cpu_cnt); ++ } ++ ++ /* ++ * PMNC counters 0:3 ++ */ ++ for (cnt = CNT0; cnt < CNTMAX; cnt++) { ++ if (flags & (1 << (cnt - CNT0))) { ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); ++ armv7_pmnc_reset_counter(cnt); ++ oprofile_add_sample(regs, cpu_cnt); ++ } ++ } ++ ++ /* ++ * Allow IRQ generation ++ */ ++ armv7_start_pmnc(); ++ ++ return IRQ_HANDLED; ++} ++ ++int armv7_request_interrupts(int *irqs, int nr) ++{ ++ unsigned int i; ++ int ret = 0; ++ ++ for (i = 0; i < nr; i++) { ++ ret = request_irq(irqs[i], armv7_pmnc_interrupt, ++ IRQF_DISABLED, "CP15 PMNC", NULL); ++ if (ret != 0) { ++ printk(KERN_ERR "oprofile: unable to request IRQ%u" ++ " for ARMv7\n", ++ irqs[i]); ++ break; ++ } ++ } ++ ++ if (i != nr) ++ while (i-- != 0) ++ free_irq(irqs[i], NULL); ++ ++ return ret; ++} ++ ++void armv7_release_interrupts(int *irqs, int nr) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr; i++) ++ free_irq(irqs[i], NULL); ++} ++ ++#ifdef DEBUG ++static void armv7_pmnc_dump_regs(void) ++{ ++ u32 val; ++ unsigned int cnt; ++ ++ printk(KERN_INFO "PMNC registers dump:\n"); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); ++ printk(KERN_INFO "PMNC =0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); ++ printk(KERN_INFO "CNTENS=0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); ++ printk(KERN_INFO "INTENS=0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); ++ printk(KERN_INFO "FLAGS =0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); ++ printk(KERN_INFO "SELECT=0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); ++ printk(KERN_INFO "CCNT =0x%08x\n", val); ++ ++ for (cnt = CNT0; cnt < CNTMAX; cnt++) { ++ armv7_pmnc_select_counter(cnt); ++ asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); ++ printk(KERN_INFO "CNT[%d] count =0x%08x\n", cnt-CNT0, val); ++ asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); ++ printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", cnt-CNT0, val); ++ } ++} ++#endif ++ ++ ++static int irqs[] = { ++#ifdef CONFIG_ARCH_OMAP3 ++ INT_34XX_BENCH_MPU_EMUL, ++#endif ++}; ++ ++static void armv7_pmnc_stop(void) ++{ ++#ifdef DEBUG ++ armv7_pmnc_dump_regs(); ++#endif ++ armv7_stop_pmnc(); ++ armv7_release_interrupts(irqs, ARRAY_SIZE(irqs)); ++} ++ ++static int armv7_pmnc_start(void) ++{ ++ int ret; ++ ++#ifdef DEBUG ++ armv7_pmnc_dump_regs(); ++#endif ++ ret = armv7_request_interrupts(irqs, ARRAY_SIZE(irqs)); ++ if (ret >= 0) ++ armv7_start_pmnc(); ++ ++ return ret; ++} ++ ++static int armv7_detect_pmnc(void) ++{ ++ return 0; ++} ++ ++struct op_arm_model_spec op_armv7_spec = { ++ .init = armv7_detect_pmnc, ++ .num_counters = 5, ++ .setup_ctrs = armv7_setup_pmnc, ++ .start = armv7_pmnc_start, ++ .stop = armv7_pmnc_stop, ++ .name = "arm/armv7", ++}; +diff --git a/arch/arm/oprofile/op_model_v7.h b/arch/arm/oprofile/op_model_v7.h +new file mode 100644 +index 0000000..08f40ea +--- /dev/null ++++ b/arch/arm/oprofile/op_model_v7.h +@@ -0,0 +1,101 @@ ++/** ++ * @file op_model_v7.h ++ * ARM v7 (Cortex A8) Event Monitor Driver ++ * ++ * @remark Copyright 2008 Jean Pihet <jpihet@mvista.com> ++ * @remark Copyright 2004 ARM SMP Development Team ++ * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com> ++ * @remark Copyright 2000-2004 MontaVista Software Inc ++ * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com> ++ * @remark Copyright 2004 Intel Corporation ++ * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk> ++ * @remark Copyright 2004 Oprofile Authors ++ * ++ * @remark Read the file COPYING ++ * ++ * @author Zwane Mwaikambo ++ */ ++#ifndef OP_MODEL_V7_H ++#define OP_MODEL_V7_H ++ ++/* ++ * Per-CPU PMNC: config reg ++ */ ++#define PMNC_E (1 << 0) /* Enable all counters */ ++#define PMNC_P (1 << 1) /* Reset all counters */ ++#define PMNC_C (1 << 2) /* Cycle counter reset */ ++#define PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ ++#define PMNC_X (1 << 4) /* Export to ETM */ ++#define PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ ++#define PMNC_MASK 0x3f /* Mask for writable bits */ ++ ++/* ++ * Available counters ++ */ ++#define CCNT 0 ++#define CNT0 1 ++#define CNT1 2 ++#define CNT2 3 ++#define CNT3 4 ++#define CNTMAX 5 ++ ++#define CPU_COUNTER(cpu, counter) ((cpu) * CNTMAX + (counter)) ++ ++/* ++ * CNTENS: counters enable reg ++ */ ++#define CNTENS_P0 (1 << 0) ++#define CNTENS_P1 (1 << 1) ++#define CNTENS_P2 (1 << 2) ++#define CNTENS_P3 (1 << 3) ++#define CNTENS_C (1 << 31) ++#define CNTENS_MASK 0x8000000f /* Mask for writable bits */ ++ ++/* ++ * CNTENC: counters disable reg ++ */ ++#define CNTENC_P0 (1 << 0) ++#define CNTENC_P1 (1 << 1) ++#define CNTENC_P2 (1 << 2) ++#define CNTENC_P3 (1 << 3) ++#define CNTENC_C (1 << 31) ++#define CNTENC_MASK 0x8000000f /* Mask for writable bits */ ++ ++/* ++ * INTENS: counters overflow interrupt enable reg ++ */ ++#define INTENS_P0 (1 << 0) ++#define INTENS_P1 (1 << 1) ++#define INTENS_P2 (1 << 2) ++#define INTENS_P3 (1 << 3) ++#define INTENS_C (1 << 31) ++#define INTENS_MASK 0x8000000f /* Mask for writable bits */ ++ ++/* ++ * EVTSEL: Event selection reg ++ */ ++#define EVTSEL_MASK 0x7f /* Mask for writable bits */ ++ ++/* ++ * SELECT: Counter selection reg ++ */ ++#define SELECT_MASK 0x1f /* Mask for writable bits */ ++ ++/* ++ * FLAG: counters overflow flag status reg ++ */ ++#define FLAG_P0 (1 << 0) ++#define FLAG_P1 (1 << 1) ++#define FLAG_P2 (1 << 2) ++#define FLAG_P3 (1 << 3) ++#define FLAG_C (1 << 31) ++#define FLAG_MASK 0x8000000f /* Mask for writable bits */ ++ ++ ++int armv7_setup_pmu(void); ++int armv7_start_pmu(void); ++int armv7_stop_pmu(void); ++int armv7_request_interrupts(int *, int); ++void armv7_release_interrupts(int *, int); ++ ++#endif +diff --git a/include/asm-arm/arch-omap/irqs.h +b/include/asm-arm/arch-omap/irqs.h +index c80e160..89ca90e 100644 +--- a/include/asm-arm/arch-omap/irqs.h ++++ b/include/asm-arm/arch-omap/irqs.h +@@ -297,6 +297,7 @@ + #define INT_243X_HS_USB_DMA 93 + #define INT_243X_CARKIT_IRQ 94 + ++#define INT_34XX_BENCH_MPU_EMUL 3 + #define INT_34XX_ST_MCBSP2_IRQ 4 + #define INT_34XX_ST_MCBSP3_IRQ 5 + #define INT_34XX_SYS_NIRQ 7 diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/read_die_ids.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/read_die_ids.patch new file mode 100644 index 0000000000..3f6c930cc1 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/read_die_ids.patch @@ -0,0 +1,23 @@ +OMAP2/3 TAP: enable debug messages + +From: Paul Walmsley <paul@pwsan.com> + +This patch causes the OMAP2/3 chip ID code to display the full DIE_ID registers at boot. + +--- + + arch/arm/mach-omap2/id.c | 1 + + 1 files changed, 1 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c +index c7f9ab7..a154b5e 100644 +--- a/arch/arm/mach-omap2/id.c ++++ b/arch/arm/mach-omap2/id.c +@@ -10,6 +10,7 @@ + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ ++#define DEBUG + + #include <linux/module.h> + #include <linux/kernel.h> diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/soc.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/soc.patch new file mode 100644 index 0000000000..f4cce21ca7 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/soc.patch @@ -0,0 +1,1154 @@ +diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig +index 3903ab7..468536d 100644 +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -44,3 +44,7 @@ config SND_SOC_CS4270_VD33_ERRATA + config SND_SOC_TLV320AIC3X + tristate + depends on SND_SOC && I2C ++ ++config SND_SOC_TWL4030 ++ tristate ++ depends on SND_SOC && I2C +diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile +index 4e1314c..d2c0b12 100644 +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -6,6 +6,7 @@ snd-soc-wm9712-objs := wm9712.o + snd-soc-wm9713-objs := wm9713.o + snd-soc-cs4270-objs := cs4270.o + snd-soc-tlv320aic3x-objs := tlv320aic3x.o ++snd-soc-twl4030-objs := twl4030.o + + obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o + obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o +@@ -15,3 +16,4 @@ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o + obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o + obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o + obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o ++obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o +diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c +new file mode 100644 +index 0000000..eb8370c +--- /dev/null ++++ b/sound/soc/codecs/twl4030.c +@@ -0,0 +1,625 @@ ++/* ++ * ALSA SoC TWL4030 codec driver ++ * ++ * Author: Steve Sakoman, <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/init.h> ++#include <linux/delay.h> ++#include <linux/pm.h> ++#include <linux/i2c.h> ++#include <linux/platform_device.h> ++#include <linux/i2c/twl4030.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/pcm_params.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++#include <sound/initval.h> ++ ++#include "twl4030.h" ++ ++/* ++ * twl4030 register cache & default register settings ++ */ ++static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { ++ 0x00, // this register not used ++ 0x93, // REG_CODEC_MODE (0x1) ++ 0xc3, // REG_OPTION (0x2) ++ 0x00, // REG_UNKNOWN (0x3) ++ 0x00, // REG_MICBIAS_CTL (0x4) ++ 0x34, // REG_ANAMICL (0x5) ++ 0x14, // REG_ANAMICR (0x6) ++ 0x0a, // REG_AVADC_CTL (0x7) ++ 0x00, // REG_ADCMICSEL (0x8) ++ 0x00, // REG_DIGMIXING (0x9) ++ 0x0c, // REG_ATXL1PGA (0xA) ++ 0x0c, // REG_ATXR1PGA (0xB) ++ 0x00, // REG_AVTXL2PGA (0xC) ++ 0x00, // REG_AVTXR2PGA (0xD) ++ 0x01, // REG_AUDIO_IF (0xE) ++ 0x00, // REG_VOICE_IF (0xF) ++ 0x00, // REG_ARXR1PGA (0x10) ++ 0x00, // REG_ARXL1PGA (0x11) ++ 0x6c, // REG_ARXR2PGA (0x12) ++ 0x6c, // REG_ARXL2PGA (0x13) ++ 0x00, // REG_VRXPGA (0x14) ++ 0x00, // REG_VSTPGA (0x15) ++ 0x00, // REG_VRX2ARXPGA (0x16) ++ 0x0c, // REG_AVDAC_CTL (0x17) ++ 0x00, // REG_ARX2VTXPGA (0x18) ++ 0x00, // REG_ARXL1_APGA_CTL (0x19) ++ 0x00, // REG_ARXR1_APGA_CTL (0x1A) ++ 0x4b, // REG_ARXL2_APGA_CTL (0x1B) ++ 0x4b, // REG_ARXR2_APGA_CTL (0x1C) ++ 0x00, // REG_ATX2ARXPGA (0x1D) ++ 0x00, // REG_BT_IF (0x1E) ++ 0x00, // REG_BTPGA (0x1F) ++ 0x00, // REG_BTSTPGA (0x20) ++ 0x00, // REG_EAR_CTL (0x21) ++ 0x24, // REG_HS_SEL (0x22) ++ 0x0a, // REG_HS_GAIN_SET (0x23) ++ 0x00, // REG_HS_POPN_SET (0x24) ++ 0x00, // REG_PREDL_CTL (0x25) ++ 0x00, // REG_PREDR_CTL (0x26) ++ 0x00, // REG_PRECKL_CTL (0x27) ++ 0x00, // REG_PRECKR_CTL (0x28) ++ 0x00, // REG_HFL_CTL (0x29) ++ 0x00, // REG_HFR_CTL (0x2A) ++ 0x00, // REG_ALC_CTL (0x2B) ++ 0x00, // REG_ALC_SET1 (0x2C) ++ 0x00, // REG_ALC_SET2 (0x2D) ++ 0x00, // REG_BOOST_CTL (0x2E) ++ 0x01, // REG_SOFTVOL_CTL (0x2F) ++ 0x00, // REG_DTMF_FREQSEL (0x30) ++ 0x00, // REG_DTMF_TONEXT1H (0x31) ++ 0x00, // REG_DTMF_TONEXT1L (0x32) ++ 0x00, // REG_DTMF_TONEXT2H (0x33) ++ 0x00, // REG_DTMF_TONEXT2L (0x34) ++ 0x00, // REG_DTMF_TONOFF (0x35) ++ 0x00, // REG_DTMF_WANONOFF (0x36) ++ 0x00, // REG_I2S_RX_SCRAMBLE_H (0x37) ++ 0x00, // REG_I2S_RX_SCRAMBLE_M (0x38) ++ 0x00, // REG_I2S_RX_SCRAMBLE_L (0x39) ++ 0x16, // REG_APLL_CTL (0x3A) ++ 0x00, // REG_DTMF_CTL (0x3B) ++ 0x00, // REG_DTMF_PGA_CTL2 (0x3C) ++ 0x00, // REG_DTMF_PGA_CTL1 (0x3D) ++ 0x00, // REG_MISC_SET_1 (0x3E) ++ 0x00, // REG_PCMBTMUX (0x3F) ++ 0x00, // REG_RX_PATH_SEL (0x43) ++ 0x00, // REG_VDL_APGA_CTL (0x44) ++ 0x00, // REG_VIBRA_CTL (0x45) ++ 0x00, // REG_VIBRA_SET (0x46) ++ 0x00, // REG_VIBRA_PWM_SET (0x47) ++ 0x00, // REG_ANAMIC_GAIN (0x48) ++ 0x00, // REG_MISC_SET_2 (0x49) ++}; ++ ++static void twl4030_dump_registers(void) ++{ ++ int i = 0; ++ u8 data; ++ ++ printk(KERN_INFO "TWL 4030 Register dump for Audio Module\n"); ++ ++ for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &data, i); ++ printk(KERN_INFO "Register[0x%02x]=0x%02x\n", i, data); ++ } ++} ++ ++struct twl4030_priv { ++ unsigned int dummy; ++}; ++ ++/* ++ * read twl4030 register cache ++ */ ++static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, ++ unsigned int reg) ++{ ++ u8 *cache = codec->reg_cache; ++ ++ return cache[reg]; ++} ++ ++/* ++ * write twl4030 register cache ++ */ ++static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, ++ u8 reg, u8 value) ++{ ++ u8 *cache = codec->reg_cache; ++ ++ if (reg >= TWL4030_CACHEREGNUM) ++ return; ++ cache[reg] = value; ++} ++ ++/* ++ * write to the twl4030 register space ++ */ ++static int twl4030_write(struct snd_soc_codec *codec, ++ unsigned int reg, unsigned int value) ++{ ++ twl4030_write_reg_cache(codec, reg, value); ++ return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); ++} ++ ++static void twl4030_init_chip(void) ++{ ++ unsigned char byte; ++ int i; ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_CODEC_MODE] & 0xfd, REG_CODEC_MODE); ++ ++ udelay(10); /* delay for power settling */ ++ ++ for (i = REG_OPTION; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, twl4030_reg[i], i); ++ } ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_CODEC_MODE], REG_CODEC_MODE); ++ ++ udelay(10); /* delay for power settling */ ++ ++ /* initiate offset cancellation */ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_ANAMICL] | 0x80, REG_ANAMICL); ++ ++ /* wait for offset cancellation to complete */ ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL); ++ while ((byte & 0x80) == 0x80) ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL); ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_MISC_SET_1] | 0x02, REG_MISC_SET_1); ++ ++} ++ ++static const struct snd_kcontrol_new twl4030_snd_controls[] = { ++ SOC_DOUBLE_R("Master Playback Volume", ++ REG_ARXL2PGA, REG_ARXR2PGA, ++ 0, 127, 0), ++ SOC_DOUBLE_R("Capture Volume", ++ REG_ATXL1PGA, REG_ATXR1PGA, ++ 0, 127, 0), ++}; ++ ++/* add non dapm controls */ ++static int twl4030_add_controls(struct snd_soc_codec *codec) ++{ ++ int err, i; ++ ++ for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) { ++ err = snd_ctl_add(codec->card, ++ snd_soc_cnew(&twl4030_snd_controls[i], ++ codec, NULL)); ++ if (err < 0) ++ return err; ++ } ++ ++ return 0; ++} ++ ++static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { ++ SND_SOC_DAPM_INPUT("INL"), ++ SND_SOC_DAPM_INPUT("INR"), ++ ++ SND_SOC_DAPM_OUTPUT("OUTL"), ++ SND_SOC_DAPM_OUTPUT("OUTR"), ++ ++ SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), ++ SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), ++ ++ SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0), ++ SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0), ++}; ++ ++static const char *intercon[][3] = { ++ /* outputs */ ++ {"OUTL", NULL, "DACL"}, ++ {"OUTR", NULL, "DACR"}, ++ ++ /* inputs */ ++ {"ADCL", NULL, "INL"}, ++ {"ADCR", NULL, "INR"}, ++ ++ /* terminator */ ++ {NULL, NULL, NULL}, ++}; ++ ++static int twl4030_add_widgets(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++) ++ snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]); ++ ++ /* set up audio path interconnects */ ++ for (i = 0; intercon[i][0] != NULL; i++) ++ snd_soc_dapm_connect_input(codec, intercon[i][0], ++ intercon[i][1], intercon[i][2]); ++ ++ snd_soc_dapm_new_widgets(codec); ++ return 0; ++} ++ ++static int twl4030_dapm_event(struct snd_soc_codec *codec, int event) ++{ ++ ++ printk(KERN_INFO "TWL4030 Audio Codec dapm event\n"); ++ switch (event) { ++ case SNDRV_CTL_POWER_D0: /* full On */ ++ break; ++ case SNDRV_CTL_POWER_D1: /* partial On */ ++ case SNDRV_CTL_POWER_D2: /* partial On */ ++ break; ++ case SNDRV_CTL_POWER_D3hot: /* off, with power */ ++ break; ++ case SNDRV_CTL_POWER_D3cold: /* off, without power */ ++ break; ++ } ++ codec->dapm_state = event; ++ ++ return 0; ++} ++ ++static void twl4030_power_up (struct snd_soc_codec *codec, u8 mode) ++{ ++ u8 popn, hsgain; ++ ++ twl4030_write(codec, REG_CODEC_MODE, mode & ~CODECPDZ); ++ twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ); ++ udelay(10); ++ ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); ++ popn &= RAMP_DELAY; ++ popn |= VMID_EN | RAMP_DELAY_161MS; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ hsgain = HSR_GAIN_0DB| HSL_GAIN_0DB; ++ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); ++ ++ popn |= RAMP_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++} ++ ++static void twl4030_power_down (struct snd_soc_codec *codec) ++{ ++ u8 popn, hsgain, mode; ++ ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); ++ popn &= ~RAMP_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ hsgain = HSR_GAIN_PWR_DOWN | HSL_GAIN_PWR_DOWN; ++ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); ++ ++ popn &= ~VMID_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ udelay(10); ++} ++ ++ ++static int twl4030_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_device *socdev = rtd->socdev; ++ struct snd_soc_codec *codec = socdev->codec; ++ struct twl4030_priv *twl4030 = codec->private_data; ++ u8 mode, old_mode, format, old_format; ++ ++ ++ /* bit rate */ ++ old_mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ; ++ mode = old_mode; ++ mode &= ~APLL_RATE; ++ switch (params_rate(params)) { ++ case 44100: ++ mode |= APLL_RATE_44100; ++ break; ++ case 48000: ++ mode |= APLL_RATE_48000; ++ break; ++ default: ++ printk(KERN_INFO "TWL4030 hw params: unknown rate %d\n", params_rate(params)); ++ return -EINVAL; ++ } ++ ++ if (mode != old_mode) { ++ /* change rate and turn codec back on */ ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ ++ /* sample size */ ++ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ format = old_format; ++ format &= ~DATA_WIDTH; ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ format |= DATA_WIDTH_16S_16W; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ format |= DATA_WIDTH_32S_24W; ++ break; ++ default: ++ printk(KERN_INFO "TWL4030 hw params: unknown format %d\n", params_format(params)); ++ return -EINVAL; ++ } ++ ++ if (format != old_format) { ++ ++ /* turn off codec before changing format */ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ ++ /* change format */ ++ twl4030_write(codec, REG_AUDIO_IF, format); ++ ++ /* turn on codec */ ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ return 0; ++} ++ ++static int twl4030_mute(struct snd_soc_codec_dai *dai, int mute) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ ++ u8 ldac_reg = twl4030_read_reg_cache(codec, REG_ARXL2PGA); ++ u8 rdac_reg = twl4030_read_reg_cache(codec, REG_ARXR2PGA); ++ ++ if (mute) { ++ /* printk(KERN_INFO "TWL4030 Audio Codec mute\n"); */ ++ twl4030_write(codec, REG_ARXL2PGA, 0x00); ++ twl4030_write(codec, REG_ARXR2PGA, 0x00); ++ twl4030_write_reg_cache(codec, REG_ARXL2PGA, ldac_reg); ++ twl4030_write_reg_cache(codec, REG_ARXR2PGA, rdac_reg); ++ } ++ else { ++ /* printk(KERN_INFO "TWL4030 Audio Codec unmute: %02x/%02x\n", ldac_reg, rdac_reg); */ ++ twl4030_write(codec, REG_ARXL2PGA, ldac_reg); ++ twl4030_write(codec, REG_ARXR2PGA, rdac_reg); ++ } ++ ++ return 0; ++} ++ ++static int twl4030_set_dai_fmt(struct snd_soc_codec_dai *codec_dai, ++ unsigned int fmt) ++{ ++ struct snd_soc_codec *codec = codec_dai->codec; ++ struct twl4030_priv *twl4030 = codec->private_data; ++ u8 mode, old_format, format; ++ ++ /* get format */ ++ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ format = old_format; ++ ++ /* set master/slave audio interface */ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++ /* printk(KERN_INFO "TWL4030 set dai fmt: master\n"); */ ++ format &= ~(AIF_SLAVE_EN); ++ format |= CLK256FS_EN; ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ /* printk(KERN_INFO "TWL4030 set dai fmt: slave\n"); */ ++ format &= ~(CLK256FS_EN); ++ format |= AIF_SLAVE_EN; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* interface format */ ++ format &= ~AIF_FORMAT; ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ /* printk(KERN_INFO "TWL4030 set dai fmt: i2s\n"); */ ++ format |= AIF_FORMAT_CODEC; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (format != old_format) { ++ ++ /* turn off codec before changing format */ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ ++ /* change format */ ++ twl4030_write(codec, REG_AUDIO_IF, format); ++ ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ ++ return 0; ++} ++ ++#define TWL4030_RATES SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 ++#define TWL4030_FORMATS SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE ++ ++struct snd_soc_codec_dai twl4030_dai = { ++ .name = "twl4030", ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = TWL4030_RATES, ++ .formats = TWL4030_FORMATS,}, ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = TWL4030_RATES, ++ .formats = TWL4030_FORMATS,}, ++ .ops = { ++ .hw_params = twl4030_hw_params, ++ }, ++ .dai_ops = { ++ .digital_mute = twl4030_mute, ++ .set_fmt = twl4030_set_dai_fmt, ++ } ++}; ++ ++EXPORT_SYMBOL_GPL(twl4030_dai); ++ ++static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec suspend\n"); ++ twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3cold); ++ ++ return 0; ++} ++ ++static int twl4030_resume(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ int i; ++ u16 *cache = codec->reg_cache; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec resume\n"); ++ /* Sync reg_cache with the hardware */ ++ for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, cache[i], i); ++ } ++ twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3hot); ++ twl4030_dapm_event(codec, codec->suspend_dapm_state); ++ return 0; ++} ++ ++/* ++ * initialize the driver ++ * register the mixer and dsp interfaces with the kernel ++ */ ++ ++static int twl4030_init(struct snd_soc_device *socdev) ++{ ++ struct snd_soc_codec *codec = socdev->codec; ++ int ret = 0; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec init \n"); ++ ++ codec->name = "twl4030"; ++ codec->owner = THIS_MODULE; ++ codec->read = twl4030_read_reg_cache; ++ codec->write = twl4030_write; ++ codec->dapm_event = twl4030_dapm_event; ++ codec->dai = &twl4030_dai; ++ codec->num_dai = 1; ++ codec->reg_cache_size = sizeof(twl4030_reg); ++ codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), GFP_KERNEL); ++ if (codec->reg_cache == NULL) ++ return -ENOMEM; ++ ++ /* register pcms */ ++ ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); ++ if (ret < 0) { ++ printk(KERN_ERR "twl4030: failed to create pcms\n"); ++ goto pcm_err; ++ } ++ ++ twl4030_add_controls(codec); ++ twl4030_add_widgets(codec); ++ ++ ret = snd_soc_register_card(socdev); ++ if (ret < 0) { ++ printk(KERN_ERR "twl4030: failed to register card\n"); ++ goto card_err; ++ } ++ ++ twl4030_init_chip(); ++ twl4030_power_up(codec, APLL_RATE_44100 | OPT_MODE); ++ ++ return ret; ++ ++card_err: ++ printk(KERN_INFO "TWL4030 Audio Codec init card error\n"); ++ snd_soc_free_pcms(socdev); ++ snd_soc_dapm_free(socdev); ++pcm_err: ++ printk(KERN_INFO "TWL4030 Audio Codec init pcm error\n"); ++ kfree(codec->reg_cache); ++ return ret; ++} ++ ++static struct snd_soc_device *twl4030_socdev; ++ ++static int twl4030_probe(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec; ++ struct twl4030_priv *twl4030; ++ ++ codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); ++ if (codec == NULL) ++ return -ENOMEM; ++ ++ twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL); ++ if (twl4030 == NULL) { ++ kfree(codec); ++ return -ENOMEM; ++ } ++ ++ codec->private_data = twl4030; ++ socdev->codec = codec; ++ mutex_init(&codec->mutex); ++ INIT_LIST_HEAD(&codec->dapm_widgets); ++ INIT_LIST_HEAD(&codec->dapm_paths); ++ ++ twl4030_socdev = socdev; ++ twl4030_init(socdev); ++ ++ return 0; ++} ++ ++static int twl4030_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec remove\n"); ++ kfree(codec->private_data); ++ kfree(codec); ++ ++ return 0; ++} ++ ++struct snd_soc_codec_device soc_codec_dev_twl4030 = { ++ .probe = twl4030_probe, ++ .remove = twl4030_remove, ++ .suspend = twl4030_suspend, ++ .resume = twl4030_resume, ++}; ++EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); ++ ++MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); ++MODULE_AUTHOR("Steve Sakoman"); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h +new file mode 100644 +index 0000000..e126f96 +--- /dev/null ++++ b/sound/soc/codecs/twl4030.h +@@ -0,0 +1,152 @@ ++/* ++ * ALSA SoC TWL4030 codec driver ++ * ++ * Author: Steve Sakoman, <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __TWL4030_AUDIO_H__ ++#define __TWL4030_AUDIO_H__ ++ ++#define REG_CODEC_MODE 0x1 ++#define REG_OPTION 0x2 ++#define REG_UNKNOWN 0x3 ++#define REG_MICBIAS_CTL 0x4 ++#define REG_ANAMICL 0x5 ++#define REG_ANAMICR 0x6 ++#define REG_AVADC_CTL 0x7 ++#define REG_ADCMICSEL 0x8 ++#define REG_DIGMIXING 0x9 ++#define REG_ATXL1PGA 0xA ++#define REG_ATXR1PGA 0xB ++#define REG_AVTXL2PGA 0xC ++#define REG_AVTXR2PGA 0xD ++#define REG_AUDIO_IF 0xE ++#define REG_VOICE_IF 0xF ++#define REG_ARXR1PGA 0x10 ++#define REG_ARXL1PGA 0x11 ++#define REG_ARXR2PGA 0x12 ++#define REG_ARXL2PGA 0x13 ++#define REG_VRXPGA 0x14 ++#define REG_VSTPGA 0x15 ++#define REG_VRX2ARXPGA 0x16 ++#define REG_AVDAC_CTL 0x17 ++#define REG_ARX2VTXPGA 0x18 ++#define REG_ARXL1_APGA_CTL 0x19 ++#define REG_ARXR1_APGA_CTL 0x1A ++#define REG_ARXL2_APGA_CTL 0x1B ++#define REG_ARXR2_APGA_CTL 0x1C ++#define REG_ATX2ARXPGA 0x1D ++#define REG_BT_IF 0x1E ++#define REG_BTPGA 0x1F ++#define REG_BTSTPGA 0x20 ++#define REG_EAR_CTL 0x21 ++#define REG_HS_SEL 0x22 ++#define REG_HS_GAIN_SET 0x23 ++#define REG_HS_POPN_SET 0x24 ++#define REG_PREDL_CTL 0x25 ++#define REG_PREDR_CTL 0x26 ++#define REG_PRECKL_CTL 0x27 ++#define REG_PRECKR_CTL 0x28 ++#define REG_HFL_CTL 0x29 ++#define REG_HFR_CTL 0x2A ++#define REG_ALC_CTL 0x2B ++#define REG_ALC_SET1 0x2C ++#define REG_ALC_SET2 0x2D ++#define REG_BOOST_CTL 0x2E ++#define REG_SOFTVOL_CTL 0x2F ++#define REG_DTMF_FREQSEL 0x30 ++#define REG_DTMF_TONEXT1H 0x31 ++#define REG_DTMF_TONEXT1L 0x32 ++#define REG_DTMF_TONEXT2H 0x33 ++#define REG_DTMF_TONEXT2L 0x34 ++#define REG_DTMF_TONOFF 0x35 ++#define REG_DTMF_WANONOFF 0x36 ++#define REG_I2S_RX_SCRAMBLE_H 0x37 ++#define REG_I2S_RX_SCRAMBLE_M 0x38 ++#define REG_I2S_RX_SCRAMBLE_L 0x39 ++#define REG_APLL_CTL 0x3A ++#define REG_DTMF_CTL 0x3B ++#define REG_DTMF_PGA_CTL2 0x3C ++#define REG_DTMF_PGA_CTL1 0x3D ++#define REG_MISC_SET_1 0x3E ++#define REG_PCMBTMUX 0x3F ++#define REG_RX_PATH_SEL 0x43 ++#define REG_VDL_APGA_CTL 0x44 ++#define REG_VIBRA_CTL 0x45 ++#define REG_VIBRA_SET 0x46 ++#define REG_VIBRA_PWM_SET 0x47 ++#define REG_ANAMIC_GAIN 0x48 ++#define REG_MISC_SET_2 0x49 ++ ++#define TWL4030_CACHEREGNUM REG_MISC_SET_2 + 1 ++ ++/* Bitfield Definitions */ ++ ++/* CODEC_MODE (0x01) Fields */ ++ ++#define APLL_RATE 0xF0 ++#define APLL_RATE_8000 0x00 ++#define APLL_RATE_11025 0x10 ++#define APLL_RATE_12000 0x20 ++#define APLL_RATE_16000 0x40 ++#define APLL_RATE_22050 0x50 ++#define APLL_RATE_24000 0x60 ++#define APLL_RATE_32000 0x80 ++#define APLL_RATE_44100 0x90 ++#define APLL_RATE_48000 0xa0 ++#define SEL_16K 0x04 ++#define CODECPDZ 0x02 ++#define OPT_MODE 0x01 ++ ++/* AUDIO_IF (0x0E) Fields */ ++ ++#define AIF_SLAVE_EN 0x80 ++#define DATA_WIDTH 0x60 ++#define DATA_WIDTH_16S_16W 0x00 ++#define DATA_WIDTH_32S_16W 0x40 ++#define DATA_WIDTH_32S_24W 0x60 ++#define AIF_FORMAT 0x18 ++#define AIF_FORMAT_CODEC 0x00 ++#define AIF_FORMAT_LEFT 0x08 ++#define AIF_FORMAT_RIGHT 0x10 ++#define AIF_FORMAT_TDM 0x18 ++#define AIF_TRI_EN 0x04 ++#define CLK256FS_EN 0x02 ++#define AIF_EN 0x01 ++ ++/* HS_GAIN_SET (0x23) Fields */ ++ ++#define HSR_GAIN 0x0c ++#define HSR_GAIN_PWR_DOWN 0x00 ++#define HSR_GAIN_PLUS_6DB 0x04 ++#define HSR_GAIN_0DB 0x08 ++#define HSR_GAIN_MINUS_6DB 0x0c ++#define HSL_GAIN 0x0c ++#define HSL_GAIN_PWR_DOWN 0x00 ++#define HSL_GAIN_PLUS_6DB 0x01 ++#define HSL_GAIN_0DB 0x02 ++#define HSL_GAIN_MINUS_6DB 0x03 ++ ++/* HS_POPN_SET (0x24) Fields */ ++ ++#define VMID_EN 0x40 ++#define EXTMUTE 0x20 ++#define RAMP_DELAY 0x1C ++#define RAMP_DELAY_20MS 0x00 ++#define RAMP_DELAY_40MS 0x04 ++#define RAMP_DELAY_81MS 0x08 ++#define RAMP_DELAY_161MS 0x0c ++#define RAMP_DELAY_323MS 0x10 ++#define RAMP_DELAY_645MS 0x14 ++#define RAMP_DELAY_1291MS 0x18 ++#define RAMP_DELAY_2581MS 0x1c ++#define RAMP_EN 0x02 ++ ++extern struct snd_soc_codec_dai twl4030_dai; ++extern struct snd_soc_codec_device soc_codec_dev_twl4030; ++ ++#endif /* End of __TWL4030_AUDIO_H__ */ +diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig +index 0230d83..8703cea 100644 +--- a/sound/soc/omap/Kconfig ++++ b/sound/soc/omap/Kconfig +@@ -16,4 +16,20 @@ config SND_OMAP_SOC_N810 + help + Say Y if you want to add support for SoC audio on Nokia N810. + ++config SND_OMAP_SOC_OMAP3EVM ++ tristate "SoC Audio support for OMAP3 EVM" ++ depends on SND_OMAP_SOC && MACH_OMAP3EVM ++ select SND_OMAP_SOC_MCBSP ++ select SND_SOC_TWL4030 ++ help ++ Say Y if you want to add support for SoC audio on the OMAP3 EVM. ++ ++config SND_OMAP_SOC_OMAP3BEAGLE ++ tristate "SoC Audio support for OMAP3 Beagle" ++ depends on SND_OMAP_SOC && MACH_OMAP3_BEAGLE ++ select SND_OMAP_SOC_MCBSP ++ select SND_SOC_TWL4030 ++ help ++ Say Y if you want to add support for SoC audio on the OMAP3 Beagle. ++ + endmenu +diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile +index d8d8d58..638a240 100644 +--- a/sound/soc/omap/Makefile ++++ b/sound/soc/omap/Makefile +@@ -7,5 +7,10 @@ obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o + + # OMAP Machine Support + snd-soc-n810-objs := n810.o ++snd-soc-omap3evm-objs := omap3evm.o ++snd-soc-omap3beagle-objs := omap3beagle.o + + obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o ++obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o ++obj-$(CONFIG_SND_OMAP_SOC_OMAP3BEAGLE) += snd-soc-omap3beagle.o ++ +diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c +new file mode 100644 +index 0000000..878f894 +--- /dev/null ++++ b/sound/soc/omap/omap3beagle.c +@@ -0,0 +1,142 @@ ++/* ++ * omap3beagle.c -- SoC audio for OMAP3 Beagle ++ * ++ * Author: Steve Sakoman <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include <linux/clk.h> ++#include <linux/platform_device.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++ ++#include <asm/mach-types.h> ++#include <asm/arch/hardware.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/mcbsp.h> ++ ++#include "omap-mcbsp.h" ++#include "omap-pcm.h" ++#include "../codecs/twl4030.h" ++ ++static int omap3beagle_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; ++ int ret; ++ ++ /* Set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set codec DAI configuration\n"); ++ return ret; ++ } ++ ++ /* Set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set cpu DAI configuration\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops omap3beagle_ops = { ++ .hw_params = omap3beagle_hw_params, ++}; ++ ++/* Digital audio interface glue - connects codec <--> CPU */ ++static struct snd_soc_dai_link omap3beagle_dai = { ++ .name = "TWL4030", ++ .stream_name = "TWL4030", ++ .cpu_dai = &omap_mcbsp_dai[0], ++ .codec_dai = &twl4030_dai, ++ .ops = &omap3beagle_ops, ++}; ++ ++/* Audio machine driver */ ++static struct snd_soc_machine snd_soc_machine_omap3beagle = { ++ .name = "omap3beagle", ++ .dai_link = &omap3beagle_dai, ++ .num_links = 1, ++}; ++ ++/* Audio subsystem */ ++static struct snd_soc_device omap3beagle_snd_devdata = { ++ .machine = &snd_soc_machine_omap3beagle, ++ .platform = &omap_soc_platform, ++ .codec_dev = &soc_codec_dev_twl4030, ++}; ++ ++static struct platform_device *omap3beagle_snd_device; ++ ++static int __init omap3beagle_soc_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "OMAP3 Beagle SoC init\n"); ++ if (!machine_is_omap3_beagle()) { ++ printk(KERN_INFO "Not OMAP3 Beagle!\n"); ++ return -ENODEV; ++ } ++ ++ omap3beagle_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!omap3beagle_snd_device) { ++ printk(KERN_INFO "Platform device allocation failed\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(omap3beagle_snd_device, &omap3beagle_snd_devdata); ++ omap3beagle_snd_devdata.dev = &omap3beagle_snd_device->dev; ++ *(unsigned int *)omap3beagle_dai.cpu_dai->private_data = 1; /* McBSP2 */ ++ ++ ret = platform_device_add(omap3beagle_snd_device); ++ if (ret) ++ goto err1; ++ ++ return 0; ++ ++err1: ++ printk(KERN_INFO "Unable to add platform device\n"); ++ platform_device_put(omap3beagle_snd_device); ++ ++ return ret; ++} ++ ++static void __exit omap3beagle_soc_exit(void) ++{ ++ printk(KERN_INFO "OMAP3 Beagle SoC exit\n"); ++ platform_device_unregister(omap3beagle_snd_device); ++} ++ ++module_init(omap3beagle_soc_init); ++module_exit(omap3beagle_soc_exit); ++ ++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>"); ++MODULE_DESCRIPTION("ALSA SoC OMAP3 Beagle"); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c +new file mode 100644 +index 0000000..a64c788 +--- /dev/null ++++ b/sound/soc/omap/omap3evm.c +@@ -0,0 +1,142 @@ ++/* ++ * omap3evm.c -- SoC audio for OMAP3 EVM ++ * ++ * Author: Steve Sakoman <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include <linux/clk.h> ++#include <linux/platform_device.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++ ++#include <asm/mach-types.h> ++#include <asm/arch/hardware.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/mcbsp.h> ++ ++#include "omap-mcbsp.h" ++#include "omap-pcm.h" ++#include "../codecs/twl4030.h" ++ ++static int omap3evm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; ++ int ret; ++ ++ /* Set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set codec DAI configuration\n"); ++ return ret; ++ } ++ ++ /* Set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set cpu DAI configuration\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops omap3evm_ops = { ++ .hw_params = omap3evm_hw_params, ++}; ++ ++/* Digital audio interface glue - connects codec <--> CPU */ ++static struct snd_soc_dai_link omap3evm_dai = { ++ .name = "TWL4030", ++ .stream_name = "TWL4030", ++ .cpu_dai = &omap_mcbsp_dai[0], ++ .codec_dai = &twl4030_dai, ++ .ops = &omap3evm_ops, ++}; ++ ++/* Audio machine driver */ ++static struct snd_soc_machine snd_soc_machine_omap3evm = { ++ .name = "omap3evm", ++ .dai_link = &omap3evm_dai, ++ .num_links = 1, ++}; ++ ++/* Audio subsystem */ ++static struct snd_soc_device omap3evm_snd_devdata = { ++ .machine = &snd_soc_machine_omap3evm, ++ .platform = &omap_soc_platform, ++ .codec_dev = &soc_codec_dev_twl4030, ++}; ++ ++static struct platform_device *omap3evm_snd_device; ++ ++static int __init omap3evm_soc_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "OMAP3 EVM SoC init\n"); ++ if (!machine_is_omap3evm()) { ++ printk(KERN_INFO "Not OMAP3 EVM!\n"); ++ return -ENODEV; ++ } ++ ++ omap3evm_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!omap3evm_snd_device) { ++ printk(KERN_INFO "Platform device allocation failed\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(omap3evm_snd_device, &omap3evm_snd_devdata); ++ omap3evm_snd_devdata.dev = &omap3evm_snd_device->dev; ++ *(unsigned int *)omap3evm_dai.cpu_dai->private_data = 1; /* McBSP2 */ ++ ++ ret = platform_device_add(omap3evm_snd_device); ++ if (ret) ++ goto err1; ++ ++ return 0; ++ ++err1: ++ printk(KERN_INFO "Unable to add platform device\n"); ++ platform_device_put(omap3evm_snd_device); ++ ++ return ret; ++} ++ ++static void __exit omap3evm_soc_exit(void) ++{ ++ printk(KERN_INFO "OMAP3 EVM SoC exit\n"); ++ platform_device_unregister(omap3evm_snd_device); ++} ++ ++module_init(omap3evm_soc_init); ++module_exit(omap3evm_soc_exit); ++ ++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>"); ++MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM"); ++MODULE_LICENSE("GPL"); diff --git a/recipes/linux/linux-omap-2.6.26/beagleboard/timer-suppression.patch b/recipes/linux/linux-omap-2.6.26/beagleboard/timer-suppression.patch new file mode 100644 index 0000000000..04362c96e3 --- /dev/null +++ b/recipes/linux/linux-omap-2.6.26/beagleboard/timer-suppression.patch @@ -0,0 +1,43 @@ +diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c +index b854a89..26f5569 100644 +--- a/kernel/time/tick-sched.c ++++ b/kernel/time/tick-sched.c +@@ -253,6 +253,16 @@ void tick_nohz_stop_sched_tick(void) + + /* Schedule the tick, if we are at least one jiffie off */ + if ((long)delta_jiffies >= 1) { ++ /* ++ * calculate the expiry time for the next timer wheel ++ * timer ++ */ ++ expires = ktime_add_ns(last_update, tick_period.tv64 * ++ delta_jiffies); ++ ++ /* Skip reprogram of event if its not changed */ ++ if(ts->tick_stopped && ktime_equal(expires, dev->next_event)) ++ goto out2; + + if (delta_jiffies > 1) + cpu_set(cpu, nohz_cpu_mask); +@@ -304,12 +314,7 @@ void tick_nohz_stop_sched_tick(void) + goto out; + } + +- /* +- * calculate the expiry time for the next timer wheel +- * timer +- */ +- expires = ktime_add_ns(last_update, tick_period.tv64 * +- delta_jiffies); ++ /* Mark expiries */ + ts->idle_expires = expires; + + if (ts->nohz_mode == NOHZ_MODE_HIGHRES) { +@@ -328,6 +333,7 @@ void tick_nohz_stop_sched_tick(void) + tick_do_update_jiffies64(ktime_get()); + cpu_clear(cpu, nohz_cpu_mask); + } ++out2: + raise_softirq_irqoff(TIMER_SOFTIRQ); + out: + ts->next_jiffies = next_jiffies; |