diff options
| author | Phil Blundell <philb@gnu.org> | 2010-03-04 22:51:13 +0000 |
|---|---|---|
| committer | Phil Blundell <philb@gnu.org> | 2010-03-04 22:51:13 +0000 |
| commit | fdf8185913576006aa3c69bd132fb247d0a869bf (patch) | |
| tree | 69fc8d4b276b6ac9ad8198478e8feea6cf9d9693 /recipes/linux/linux-2.6.27/ts72xx/0023-Clean-and-invalidate-D-cache-entry.patch | |
| parent | 1ae7c5f36d8a6a94053ba4d7919fb7daf9ff2ae1 (diff) | |
| parent | 78c7106f99efcbabc9ccc00343c87a900644cda3 (diff) | |
Merge branch 'org.openembedded.dev' of new.openembedded.org:openembedded into org.openembedded.dev
Diffstat (limited to 'recipes/linux/linux-2.6.27/ts72xx/0023-Clean-and-invalidate-D-cache-entry.patch')
| -rw-r--r-- | recipes/linux/linux-2.6.27/ts72xx/0023-Clean-and-invalidate-D-cache-entry.patch | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/recipes/linux/linux-2.6.27/ts72xx/0023-Clean-and-invalidate-D-cache-entry.patch b/recipes/linux/linux-2.6.27/ts72xx/0023-Clean-and-invalidate-D-cache-entry.patch new file mode 100644 index 0000000000..09ea797d66 --- /dev/null +++ b/recipes/linux/linux-2.6.27/ts72xx/0023-Clean-and-invalidate-D-cache-entry.patch @@ -0,0 +1,29 @@ +From b19911010ed38171f71a321428fafc9e02e9edc4 Mon Sep 17 00:00:00 2001 +From: Matthieu Crapet <mcrapet@gmail.com> +Date: Sun, 4 Jan 2009 14:06:17 +0100 +Subject: [PATCH] Clean and invalidate D cache entry +MIME-Version: 1.0 +Content-Type: text/plain; charset=utf-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Petr Štetiar <ynezz@true.cz> +--- + arch/arm/mm/proc-arm920.S | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S +index 12f59db..e0041c9 100644 +--- a/arch/arm/mm/proc-arm920.S ++++ b/arch/arm/mm/proc-arm920.S +@@ -198,7 +198,7 @@ ENTRY(arm920_coherent_kern_range) + */ + ENTRY(arm920_coherent_user_range) + bic r0, r0, #CACHE_DLINESIZE - 1 +-1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry ++1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry + mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 +-- +1.6.0.4 + |