rename packages/ to recipes/ per earlier agreement

See links below for more details:
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21326
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21816

Signed-off-by: Denys Dmytriyenko <denis@denix.org>
Acked-by: Mike Westerhof <mwester@dls.net>
Acked-by: Philip Balister <philip@balister.org>
Acked-by: Khem Raj <raj.khem@gmail.com>
Acked-by: Marcin Juszkiewicz <hrw@openembedded.org>
Acked-by: Koen Kooi <koen@openembedded.org>
Acked-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>

66 files changed, 4371 insertions, 0 deletions

diff --git a/recipes/ixp4xx/ixp-osal-1.5/2.6.patch b/recipes/ixp4xx/ixp-osal-1.5/2.6.patch
new file mode 100644
index 0000000000..3e47fe28de
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-1.5/2.6.patch
@@ -0,0 +1,413 @@
+diff -Naur ixp_osal.orig/Makefile ixp_osal/Makefile
+--- ixp_osal.orig/Makefile	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/Makefile	2005-08-24 00:18:02.000000000 +0200
+@@ -172,7 +172,7 @@
+ 
+ # TODO push this to linux make
+ ifeq ($(IX_OSAL_MK_HOST_OS), linux)
+-INCLUDE_DIRS += $(LINUX_SRC)/include/asm-arm/arch-ixp425/
++INCLUDE_DIRS += $(LINUX_SRC)/include/asm-arm/arch-ixp4xx/
+ endif
+ 
+ CFLAGS += $(INCLUDE_DIRS:%=-I%)
+diff -Naur ixp_osal.orig/include/linux-2.6.h ixp_osal/include/linux-2.6.h
+--- ixp_osal.orig/include/linux-2.6.h	1970-01-01 01:00:00.000000000 +0100
++++ ixp_osal/include/linux-2.6.h	2005-08-26 15:20:23.000000000 +0200
+@@ -0,0 +1,52 @@
++/* */
++
++#include "asm/page.h"
++
++#if !defined (IXP425_TIMER_BASE_PHYS)
++# define IXP425_TIMER_BASE_PHYS 	IXP4XX_TIMER_BASE_PHYS
++#endif
++#if !defined (IRQ_IXP425_XSCALE_PMU)
++# define IRQ_IXP425_XSCALE_PMU		IRQ_IXP4XX_XSCALE_PMU
++#endif
++#if !defined (IXP425_QMGR_BASE_PHYS)
++# define IXP425_QMGR_BASE_PHYS		IXP4XX_QMGR_BASE_PHYS
++#endif
++#if !defined (IXP425_PERIPHERAL_BASE_PHYS)
++# define IXP425_PERIPHERAL_BASE_PHYS	IXP4XX_PERIPHERAL_BASE_PHYS
++#endif
++#if !defined (IXP425_PERIPHERAL_BASE_VIRT)
++# define IXP425_PERIPHERAL_BASE_VIRT	IXP4XX_PERIPHERAL_BASE_VIRT
++#endif
++#if !defined (IXP425_EXP_CFG_BASE_PHYS)
++# define IXP425_EXP_CFG_BASE_PHYS	IXP4XX_EXP_CFG_BASE_PHYS
++#endif
++#if !defined (IXP425_EXP_CFG_BASE_VIRT)
++# define IXP425_EXP_CFG_BASE_VIRT	IXP4XX_EXP_CFG_BASE_VIRT
++#endif
++#if !defined (IXP425_PCI_CFG_BASE_PHYS)
++# define IXP425_PCI_CFG_BASE_PHYS	IXP4XX_PCI_CFG_BASE_PHYS
++#endif
++#if !defined (IXP425_PCI_CFG_BASE_VIRT)
++# define IXP425_PCI_CFG_BASE_VIRT	IXP4XX_PCI_CFG_BASE_VIRT
++#endif
++#if !defined (IXP425_EXP_BUS_BASE2_PHYS)
++# define IXP425_EXP_BUS_BASE2_PHYS	IXP4XX_EXP_BUS_CS2_BASE_PHYS
++#endif
++#if !defined (IXP425_EthA_BASE_PHYS)
++# define IXP425_EthA_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
++#endif
++#if !defined (IXP425_EthB_BASE_PHYS)
++# define IXP425_EthB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
++#endif
++#if !defined (IXP425_ICMR)
++# define IXP425_ICMR			IXP4XX_ICMR
++#endif
++#if !defined (IXP425_USB_BASE_PHYS)
++# define IXP425_USB_BASE_PHYS		IXP4XX_USB_BASE_PHYS
++#endif
++#if !defined (IXP425_INTC_BASE_PHYS)
++# define IXP425_INTC_BASE_PHYS		IXP4XX_INTC_BASE_PHYS
++#endif
++#if !defined (IRQ_IXP425_USB)
++# define IRQ_IXP425_USB			IRQ_IXP4XX_USB
++#endif
+diff -Naur ixp_osal.orig/os/linux/include/core/IxOsalOs.h ixp_osal/os/linux/include/core/IxOsalOs.h
+--- ixp_osal.orig/os/linux/include/core/IxOsalOs.h	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/include/core/IxOsalOs.h	2005-08-26 01:56:22.000000000 +0200
+@@ -56,6 +56,7 @@
+ #include <linux/cache.h>
+ #include <linux/mm.h>
+ #include <linux/config.h>
++#include <linux/version.h>
+ #include <asm/pgalloc.h>
+ 
+ /**
+@@ -66,9 +67,23 @@
+ 
+ #define IX_OSAL_OS_MMU_PHYS_TO_VIRT(addr)  ((addr) ? phys_to_virt((unsigned int)(addr)) : 0)
+ 
+-#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)  ( invalidate_dcache_range((__u32)addr, (__u32)addr + size )) 
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++/*
++ * 2.6 kernels do not export the required cache functions.
++ */
++extern void ixOsalCacheInvalidateRange(unsigned long start, unsigned long size);
++extern void ixOsalCacheFlushRange(unsigned long start, unsigned long size);
++
++#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size) \
++ixOsalCacheInvalidateRange((unsigned long)addr, (unsigned long)addr + size)
++#define IX_OSAL_OS_CACHE_FLUSH(addr, size) \
++ixOsalCacheFlushRange((unsigned long)addr, (unsigned long)addr + size )
+ 
++#else
++
++#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)  ( invalidate_dcache_range((__u32)addr, (__u32)addr + size )) 
+ #define IX_OSAL_OS_CACHE_FLUSH(addr, size) ( clean_dcache_range((__u32)addr, (__u32)addr + size ))
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) */
+ 
+ #define printf	printk /* For backword compatibility, needs to move to better location */
+ 
+diff -Naur ixp_osal.orig/os/linux/include/platforms/ixp400/IxOsalOsIxp400.h ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400.h
+--- ixp_osal.orig/os/linux/include/platforms/ixp400/IxOsalOsIxp400.h	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400.h	2005-08-26 15:20:23.000000000 +0200
+@@ -53,6 +53,8 @@
+ #include "asm/hardware.h"
+ #include "asm/arch/irqs.h"
+ 
++#include <linux-2.6.h>		/* Glue */
++
+ /* physical addresses to be used when requesting memory with IX_OSAL_MEM_MAP */
+ #define IX_OSAL_IXP400_INTC_PHYS_BASE          IXP425_INTC_BASE_PHYS
+ #define IX_OSAL_IXP400_GPIO_PHYS_BASE          IXP425_GPIO_BASE_PHYS
+@@ -108,7 +110,6 @@
+ #define IX_OSAL_IXP400_NPEB_VIRT_BASE          IXP425_NPEB_BASE_VIRT
+ #define IX_OSAL_IXP400_NPEC_VIRT_BASE          IXP425_NPEC_BASE_VIRT
+ #define IX_OSAL_IXP400_PERIPHERAL_VIRT_BASE    IXP425_PERIPHERAL_BASE_VIRT
+-#define IX_OSAL_IXP400_QMGR_VIRT_BASE          IXP425_QMGR_BASE_VIRT
+ #define IX_OSAL_IXP400_OSTS_VIRT_BASE          IXP425_TIMER_BASE_VIRT
+ #define IX_OSAL_IXP400_USB_VIRT_BASE           IXP425_USB_BASE_VIRT
+ #define IX_OSAL_IXP400_EXP_CFG_VIRT_BASE       IXP425_EXP_CFG_BASE_VIRT
+@@ -239,12 +240,21 @@
+      * Queue Manager 
+      */
+     {
++#ifdef IXP425_QMGR_BASE_VIRT
+      IX_OSAL_STATIC_MAP,	/* type            */
+      IX_OSAL_IXP400_QMGR_PHYS_BASE,	/* physicalAddress */
+      IX_OSAL_IXP400_QMGR_MAP_SIZE,	/* size            */
+      IX_OSAL_IXP400_QMGR_VIRT_BASE,	/* virtualAddress  */
+      NULL,			/* mapFunction     */
+      NULL,			/* unmapFunction   */
++#else
++     IX_OSAL_DYNAMIC_MAP,                  /* type            */
++     IX_OSAL_IXP400_QMGR_PHYS_BASE,   /* physicalAddress */
++     IX_OSAL_IXP400_QMGR_MAP_SIZE,    /* size            */
++     0,                               /* virtualAddress  */
++     ixOsalLinuxMemMap,		/* mapFunction     */
++     ixOsalLinuxMemUnmap,	/* unmapFunction   */
++#endif
+      0,				/* refCount        */
+      IX_OSAL_BE | IX_OSAL_LE_DC,	/* endianType      */   
+      "qMgr"			/* name            */
+diff -Naur ixp_osal.orig/os/linux/make/macros.mk ixp_osal/os/linux/make/macros.mk
+--- ixp_osal.orig/os/linux/make/macros.mk	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/make/macros.mk	2005-08-26 15:17:37.000000000 +0200
+@@ -71,10 +71,12 @@
+ ################################################################
+ # Linux Compiler & linker commands
+ 
+-ifeq ($(IX_OSAL_MK_TARGET_ENDIAN), linuxbe)
+-LINUX_CROSS_COMPILE := $(HARDHAT_BASE)/devkit/arm/xscale_be/bin/xscale_be-
+-else
+-LINUX_CROSS_COMPILE := $(HARDHAT_BASE)/devkit/arm/xscale_le/bin/xscale_le-
++ifeq "$(LINUX_CROSS_COMPILE)" "" 
++ ifeq ($(IX_OSAL_MK_TARGET_ENDIAN), linuxbe)
++  LINUX_CROSS_COMPILE := $(HARDHAT_BASE)/devkit/arm/xscale_be/bin/xscale_be-
++ else
++  LINUX_CROSS_COMPILE := $(HARDHAT_BASE)/devkit/arm/xscale_le/bin/xscale_le-
++ endif
+ endif
+ 
+ LINUX_SRC := $($(IX_TARGET)_KERNEL_DIR)
+@@ -91,9 +93,11 @@
+ LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mcpu=xscale -mtune=xscale
+ 
+ CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common \
+-          -pipe -mapcs-32 -mshort-load-bytes -msoft-float -DMODULE \
++          -pipe -mapcs-32 -msoft-float -DMODULE \
+           -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS) -DEXPORT_SYMTAB
+ 
++# -mshort-load-bytes removed by Marc Singer's patch TODO(hannes) why?
++
+ # Linux linker flags
+ LDFLAGS := -r
+ 
+diff -Naur ixp_osal.orig/os/linux/src/core/IxOsalOsCacheMMU.c ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c
+--- ixp_osal.orig/os/linux/src/core/IxOsalOsCacheMMU.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c	2005-08-26 01:56:22.000000000 +0200
+@@ -210,3 +210,59 @@
+ 	free_pages ((unsigned int) memptr, order);
+     }
+ }
++
++
++/*
++ * 2.6 kernels do not export the required cache functions.
++ */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++
++#define _IX_STR(x) #x
++#define IX_STR(x) _IX_STR(x)
++#define IX_CLM IX_STR(IX_OSAL_CACHE_LINE_SIZE-1)
++
++/*
++ * reimplementation of kernel's invalidate_dcache_range()
++ */
++void
++ixOsalCacheInvalidateRange(unsigned long start, unsigned long size)
++{
++  __asm__
++    ("    tst    %0, #" IX_CLM "\n"
++     "    mcrne  p15, 0, %0, c7, c10, 1      @ clean D cache line\n"
++     "    bic    %0, %0, #" IX_CLM "\n"
++     "    tst    %1, #" IX_CLM "\n"
++     "    mcrne  p15, 0, %1, c7, c10, 1      @ clean D cache line\n"
++     "1:  mcr    p15, 0, %0, c7, c6, 1       @ invalidate D cache line\n"
++     "    add    %0, %0, #" IX_STR(IX_OSAL_CACHE_LINE_SIZE) "\n"
++     "    cmp    %0, %1\n"
++     "    blo    1b\n"
++     "    mcr    p15, 0, %0, c7, c10, 4      @ drain write & fill buffer\n"
++     : /* no output */
++     : "r"(start), "r"(size)
++     : "cc");
++}
++
++/*
++ * reimplementation of kernel's invalidate_dcache_range()
++ */
++void
++ixOsalCacheFlushRange(unsigned long start, unsigned long size)
++{
++  __asm__
++    ("    bic    %0, %0, #" IX_CLM "\n"
++     "1:  mcr    p15, 0, %0, c7, c10, 1      @ clean D cache line\n"
++     "    add    %0, %0, #" IX_STR(IX_OSAL_CACHE_LINE_SIZE) "\n"
++     "    cmp    %0, %1\n"
++     "    blo    1b\n"
++     "    mcr    p15, 0, %0, c7, c10, 4      @ drain write & fill buffer\n"
++     : /* no output */
++     : "r"(start), "r"(size)
++     : "cc");
++}
++
++#undef _IX_STR
++#undef IX_STR
++#undef IX_CLM
++
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) */
+diff -Naur ixp_osal.orig/os/linux/src/core/IxOsalOsMsgQ.c ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c
+--- ixp_osal.orig/os/linux/src/core/IxOsalOsMsgQ.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c	2005-08-24 00:18:02.000000000 +0200
+@@ -45,9 +45,9 @@
+  * -- End Intel Copyright Notice --
+  */
+ #include <linux/linkage.h>
++#include <linux/spinlock.h>
+ #include <linux/ipc.h>
+ #include <linux/msg.h>
+-#include <linux/spinlock.h>
+ #include <linux/interrupt.h>
+ 
+ #include "IxOsal.h"
+diff -Naur ixp_osal.orig/os/linux/src/core/IxOsalOsSemaphore.c ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c
+--- ixp_osal.orig/os/linux/src/core/IxOsalOsSemaphore.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c	2005-08-26 15:58:16.000000000 +0200
+@@ -46,7 +46,7 @@
+  */
+ 
+ #include <linux/slab.h>
+-#include <asm-arm/hardirq.h>
++#include <linux/hardirq.h>
+ #include "IxOsal.h"
+ 
+ /* Define a large number */
+@@ -93,7 +93,7 @@
+ {
+ 
+     IX_STATUS ixStatus = IX_SUCCESS;
+-    UINT32 timeoutTime;
++    unsigned long timeoutTime;
+ 
+     if (sid == NULL)
+     {
+diff -Naur ixp_osal.orig/os/linux/src/core/IxOsalOsServices.c ixp_osal/os/linux/src/core/IxOsalOsServices.c
+--- ixp_osal.orig/os/linux/src/core/IxOsalOsServices.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/core/IxOsalOsServices.c	2005-08-26 15:53:22.000000000 +0200
+@@ -53,6 +53,7 @@
+ #include <linux/time.h>
+ #include <linux/sched.h>
+ #include <linux/slab.h>
++#include <linux/interrupt.h>
+ 
+ #include "IxOsal.h"
+ 
+@@ -88,7 +89,7 @@
+ /*
+  * General interrupt handler
+  */
+-static void
++static irqreturn_t
+ ixOsalOsIsrProxy (int irq, void *dev_id, struct pt_regs *regs)
+ {
+     IxOsalInfoType *isr_proxy_info = (IxOsalInfoType *) dev_id;
+@@ -97,6 +98,7 @@
+ 		   "ixOsalOsIsrProxy: Interrupt used before ixOsalIrqBind was invoked");
+ 
+     isr_proxy_info->routine (isr_proxy_info->parameter);
++    return IRQ_HANDLED;
+ }
+ 
+ /*
+@@ -104,11 +106,12 @@
+  * This handler saves the interrupted Program Counter (PC)
+  * into a global variable
+  */
+-static void
++static irqreturn_t
+ ixOsalOsIsrProxyWithPC (int irq, void *dev_id, struct pt_regs *regs)
+ {
+     ixOsalLinuxInterruptedPc = regs->ARM_pc;
+     ixOsalOsIsrProxy(irq, dev_id, regs);
++    return IRQ_HANDLED;
+ }
+ 
+ /**************************************
+@@ -190,10 +193,15 @@
+ PUBLIC UINT32
+ ixOsalIrqLock ()
+ {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++    unsigned long flags;
++    local_irq_save(flags);
++#else
+     UINT32 flags;
+     save_flags (flags);
+     cli ();
+-    return flags;
++#endif
++    return (UINT32)flags;
+ }
+ 
+ /* Enable interrupts and task scheduling,
+@@ -203,7 +211,11 @@
+ PUBLIC void
+ ixOsalIrqUnlock (UINT32 lockKey)
+ {
++# if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++    local_irq_restore((unsigned long)lockKey);
++# else
+     restore_flags (lockKey);
++# endif
+ }
+ 
+ PUBLIC UINT32
+@@ -315,10 +327,11 @@
+ PUBLIC void
+ ixOsalSleep (UINT32 milliseconds)
+ {
+-    if (milliseconds != 0)
++    signed long delay = milliseconds*HZ;
++    if ( delay >= 1000 )
+     {
+         current->state = TASK_INTERRUPTIBLE;
+-        schedule_timeout ((milliseconds * HZ) / 1000);
++        schedule_timeout (delay / 1000);
+     }
+     else
+     {
+diff -Naur ixp_osal.orig/os/linux/src/core/IxOsalOsSymbols.c ixp_osal/os/linux/src/core/IxOsalOsSymbols.c
+--- ixp_osal.orig/os/linux/src/core/IxOsalOsSymbols.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/core/IxOsalOsSymbols.c	2005-08-30 19:19:33.000000000 +0200
+@@ -64,6 +64,10 @@
+ 
+ EXPORT_SYMBOL (ixOsalCacheDmaMalloc);
+ EXPORT_SYMBOL (ixOsalCacheDmaFree);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++EXPORT_SYMBOL (ixOsalCacheInvalidateRange);
++EXPORT_SYMBOL (ixOsalCacheFlushRange);
++#endif
+ 
+ EXPORT_SYMBOL (ixOsalThreadCreate);
+ EXPORT_SYMBOL (ixOsalThreadStart);
+diff -Naur ixp_osal.orig/os/linux/src/core/IxOsalOsThread.c ixp_osal/os/linux/src/core/IxOsalOsThread.c
+--- ixp_osal.orig/os/linux/src/core/IxOsalOsThread.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/core/IxOsalOsThread.c	2005-08-26 00:50:32.000000000 +0200
+@@ -46,6 +46,7 @@
+  */
+ 
+ #include <linux/sched.h>
++#include <linux/version.h>
+ 
+ #include "IxOsal.h"
+ 
+@@ -65,11 +66,11 @@
+     void *arg = IxOsalOsThreadData.arg;
+     static int seq = 0;
+ 
+-    daemonize ();
++    daemonize ("IxOsal %d", ++seq);
+ 
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
+     exit_files (current);
+-
+-    snprintf(current->comm, sizeof(current->comm), "IxOsal %d", ++seq);
++#endif
+ 
+     up (&IxOsalThreadMutex);
+ 
+diff -Naur ixp_osal.orig/os/linux/src/modules/ioMem/IxOsalOsIoMem.c ixp_osal/os/linux/src/modules/ioMem/IxOsalOsIoMem.c
+--- ixp_osal.orig/os/linux/src/modules/ioMem/IxOsalOsIoMem.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/modules/ioMem/IxOsalOsIoMem.c	2005-08-24 00:18:02.000000000 +0200
+@@ -45,6 +45,7 @@
+  * -- End Intel Copyright Notice --
+  */
+ 
++#include <asm/page.h>
+ #include <asm/io.h>
+ #include <linux/ioport.h>
+ 
diff --git a/recipes/ixp4xx/ixp-osal-2.0/2.6.patch b/recipes/ixp4xx/ixp-osal-2.0/2.6.patch
new file mode 100644
index 0000000000..6c143859a4
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.0/2.6.patch
@@ -0,0 +1,363 @@
+diff -Naur ixp_osal.orig/include/linux-2.6.h ixp_osal/include/linux-2.6.h
+--- ixp_osal.orig/include/linux-2.6.h	1970-01-01 01:00:00.000000000 +0100
++++ ixp_osal/include/linux-2.6.h	2005-08-26 15:20:23.000000000 +0200
+@@ -0,0 +1,52 @@
++/* */
++
++#include "asm/page.h"
++
++#if !defined (IXP425_TIMER_BASE_PHYS)
++# define IXP425_TIMER_BASE_PHYS 	IXP4XX_TIMER_BASE_PHYS
++#endif
++#if !defined (IRQ_IXP425_XSCALE_PMU)
++# define IRQ_IXP425_XSCALE_PMU		IRQ_IXP4XX_XSCALE_PMU
++#endif
++#if !defined (IXP425_QMGR_BASE_PHYS)
++# define IXP425_QMGR_BASE_PHYS		IXP4XX_QMGR_BASE_PHYS
++#endif
++#if !defined (IXP425_PERIPHERAL_BASE_PHYS)
++# define IXP425_PERIPHERAL_BASE_PHYS	IXP4XX_PERIPHERAL_BASE_PHYS
++#endif
++#if !defined (IXP425_PERIPHERAL_BASE_VIRT)
++# define IXP425_PERIPHERAL_BASE_VIRT	IXP4XX_PERIPHERAL_BASE_VIRT
++#endif
++#if !defined (IXP425_EXP_CFG_BASE_PHYS)
++# define IXP425_EXP_CFG_BASE_PHYS	IXP4XX_EXP_CFG_BASE_PHYS
++#endif
++#if !defined (IXP425_EXP_CFG_BASE_VIRT)
++# define IXP425_EXP_CFG_BASE_VIRT	IXP4XX_EXP_CFG_BASE_VIRT
++#endif
++#if !defined (IXP425_PCI_CFG_BASE_PHYS)
++# define IXP425_PCI_CFG_BASE_PHYS	IXP4XX_PCI_CFG_BASE_PHYS
++#endif
++#if !defined (IXP425_PCI_CFG_BASE_VIRT)
++# define IXP425_PCI_CFG_BASE_VIRT	IXP4XX_PCI_CFG_BASE_VIRT
++#endif
++#if !defined (IXP425_EXP_BUS_BASE2_PHYS)
++# define IXP425_EXP_BUS_BASE2_PHYS	IXP4XX_EXP_BUS_CS2_BASE_PHYS
++#endif
++#if !defined (IXP425_EthA_BASE_PHYS)
++# define IXP425_EthA_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
++#endif
++#if !defined (IXP425_EthB_BASE_PHYS)
++# define IXP425_EthB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
++#endif
++#if !defined (IXP425_ICMR)
++# define IXP425_ICMR			IXP4XX_ICMR
++#endif
++#if !defined (IXP425_USB_BASE_PHYS)
++# define IXP425_USB_BASE_PHYS		IXP4XX_USB_BASE_PHYS
++#endif
++#if !defined (IXP425_INTC_BASE_PHYS)
++# define IXP425_INTC_BASE_PHYS		IXP4XX_INTC_BASE_PHYS
++#endif
++#if !defined (IRQ_IXP425_USB)
++# define IRQ_IXP425_USB			IRQ_IXP4XX_USB
++#endif
+diff -Naur ixp_osal.orig/os/linux/include/core/IxOsalOs.h ixp_osal/os/linux/include/core/IxOsalOs.h
+--- ixp_osal.orig/os/linux/include/core/IxOsalOs.h	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/include/core/IxOsalOs.h	2005-08-26 01:56:22.000000000 +0200
+@@ -56,6 +56,7 @@
+ #include <linux/cache.h>
+ #include <linux/mm.h>
+ #include <linux/config.h>
++#include <linux/version.h>
+ #include <asm/pgalloc.h>
+ 
+ /**
+@@ -66,9 +67,23 @@
+ 
+ #define IX_OSAL_OS_MMU_PHYS_TO_VIRT(addr)  ((addr) ? phys_to_virt((unsigned int)(addr)) : 0)
+ 
+-#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)  ( invalidate_dcache_range((__u32)addr, (__u32)addr + size )) 
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++/*
++ * 2.6 kernels do not export the required cache functions.
++ */
++extern void ixOsalCacheInvalidateRange(unsigned long start, unsigned long size);
++extern void ixOsalCacheFlushRange(unsigned long start, unsigned long size);
++
++#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size) \
++ixOsalCacheInvalidateRange((unsigned long)addr, (unsigned long)addr + size)
++#define IX_OSAL_OS_CACHE_FLUSH(addr, size) \
++ixOsalCacheFlushRange((unsigned long)addr, (unsigned long)addr + size )
+ 
++#else
++
++#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)  ( invalidate_dcache_range((__u32)addr, (__u32)addr + size )) 
+ #define IX_OSAL_OS_CACHE_FLUSH(addr, size) ( clean_dcache_range((__u32)addr, (__u32)addr + size ))
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) */
+ 
+ #define printf	printk /* For backword compatibility, needs to move to better location */
+ 
+diff -Naur ixp_osal.orig/os/linux/src/core/IxOsalOsCacheMMU.c ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c
+--- ixp_osal.orig/os/linux/src/core/IxOsalOsCacheMMU.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c	2005-08-26 01:56:22.000000000 +0200
+@@ -210,3 +210,59 @@
+ 	free_pages ((unsigned int) memptr, order);
+     }
+ }
++
++
++/*
++ * 2.6 kernels do not export the required cache functions.
++ */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++
++#define _IX_STR(x) #x
++#define IX_STR(x) _IX_STR(x)
++#define IX_CLM IX_STR(IX_OSAL_CACHE_LINE_SIZE-1)
++
++/*
++ * reimplementation of kernel's invalidate_dcache_range()
++ */
++void
++ixOsalCacheInvalidateRange(unsigned long start, unsigned long size)
++{
++  __asm__
++    ("    tst    %0, #" IX_CLM "\n"
++     "    mcrne  p15, 0, %0, c7, c10, 1      @ clean D cache line\n"
++     "    bic    %0, %0, #" IX_CLM "\n"
++     "    tst    %1, #" IX_CLM "\n"
++     "    mcrne  p15, 0, %1, c7, c10, 1      @ clean D cache line\n"
++     "1:  mcr    p15, 0, %0, c7, c6, 1       @ invalidate D cache line\n"
++     "    add    %0, %0, #" IX_STR(IX_OSAL_CACHE_LINE_SIZE) "\n"
++     "    cmp    %0, %1\n"
++     "    blo    1b\n"
++     "    mcr    p15, 0, %0, c7, c10, 4      @ drain write & fill buffer\n"
++     : /* no output */
++     : "r"(start), "r"(size)
++     : "cc");
++}
++
++/*
++ * reimplementation of kernel's invalidate_dcache_range()
++ */
++void
++ixOsalCacheFlushRange(unsigned long start, unsigned long size)
++{
++  __asm__
++    ("    bic    %0, %0, #" IX_CLM "\n"
++     "1:  mcr    p15, 0, %0, c7, c10, 1      @ clean D cache line\n"
++     "    add    %0, %0, #" IX_STR(IX_OSAL_CACHE_LINE_SIZE) "\n"
++     "    cmp    %0, %1\n"
++     "    blo    1b\n"
++     "    mcr    p15, 0, %0, c7, c10, 4      @ drain write & fill buffer\n"
++     : /* no output */
++     : "r"(start), "r"(size)
++     : "cc");
++}
++
++#undef _IX_STR
++#undef IX_STR
++#undef IX_CLM
++
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) */
+diff -Naur ixp_osal.orig/os/linux/src/core/IxOsalOsMsgQ.c ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c
+--- ixp_osal.orig/os/linux/src/core/IxOsalOsMsgQ.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c	2005-08-24 00:18:02.000000000 +0200
+@@ -45,9 +45,9 @@
+  * -- End Intel Copyright Notice --
+  */
+ #include <linux/linkage.h>
++#include <linux/spinlock.h>
+ #include <linux/ipc.h>
+ #include <linux/msg.h>
+-#include <linux/spinlock.h>
+ #include <linux/interrupt.h>
+ 
+ #include "IxOsal.h"
+diff -Naur ixp_osal.orig/os/linux/src/core/IxOsalOsSemaphore.c ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c
+--- ixp_osal.orig/os/linux/src/core/IxOsalOsSemaphore.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c	2005-08-26 15:58:16.000000000 +0200
+@@ -46,7 +46,7 @@
+  */
+ 
+ #include <linux/slab.h>
+-#include <asm-arm/hardirq.h>
++#include <linux/hardirq.h>
+ #include "IxOsal.h"
+ 
+ /* Define a large number */
+@@ -93,7 +93,7 @@
+ {
+ 
+     IX_STATUS ixStatus = IX_SUCCESS;
+-    UINT32 timeoutTime;
++    unsigned long timeoutTime;
+ 
+     if (sid == NULL)
+     {
+diff -Naur ixp_osal.orig/os/linux/src/core/IxOsalOsSymbols.c ixp_osal/os/linux/src/core/IxOsalOsSymbols.c
+--- ixp_osal.orig/os/linux/src/core/IxOsalOsSymbols.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/core/IxOsalOsSymbols.c	2005-08-30 19:19:33.000000000 +0200
+@@ -64,6 +64,10 @@
+ 
+ EXPORT_SYMBOL (ixOsalCacheDmaMalloc);
+ EXPORT_SYMBOL (ixOsalCacheDmaFree);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++EXPORT_SYMBOL (ixOsalCacheInvalidateRange);
++EXPORT_SYMBOL (ixOsalCacheFlushRange);
++#endif
+ 
+ EXPORT_SYMBOL (ixOsalThreadCreate);
+ EXPORT_SYMBOL (ixOsalThreadStart);
+diff -Naur ixp_osal.orig/os/linux/src/modules/ioMem/IxOsalOsIoMem.c ixp_osal/os/linux/src/modules/ioMem/IxOsalOsIoMem.c
+--- ixp_osal.orig/os/linux/src/modules/ioMem/IxOsalOsIoMem.c	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/os/linux/src/modules/ioMem/IxOsalOsIoMem.c	2005-08-24 00:18:02.000000000 +0200
+@@ -45,6 +45,7 @@
+  * -- End Intel Copyright Notice --
+  */
+ 
++#include <asm/page.h>
+ #include <asm/io.h>
+ #include <linux/ioport.h>
+ 
+--- ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400.h.orig	2005-04-17 20:56:27.000000000 -0700
++++ ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400.h	2005-10-01 16:27:05.566984144 -0700
+@@ -53,6 +53,8 @@
+ #include "asm/hardware.h"
+ #include "asm/arch/irqs.h"
+ 
++#include <linux-2.6.h>		/* Glue */
++
+ /* physical addresses to be used when requesting memory with IX_OSAL_MEM_MAP */
+ #define IX_OSAL_IXP400_INTC_PHYS_BASE          IXP425_INTC_BASE_PHYS
+ #define IX_OSAL_IXP400_GPIO_PHYS_BASE          IXP425_GPIO_BASE_PHYS
+@@ -108,7 +110,6 @@
+ #define IX_OSAL_IXP400_NPEB_VIRT_BASE          IXP425_NPEB_BASE_VIRT
+ #define IX_OSAL_IXP400_NPEC_VIRT_BASE          IXP425_NPEC_BASE_VIRT
+ #define IX_OSAL_IXP400_PERIPHERAL_VIRT_BASE    IXP425_PERIPHERAL_BASE_VIRT
+-#define IX_OSAL_IXP400_QMGR_VIRT_BASE          IXP425_QMGR_BASE_VIRT
+ #define IX_OSAL_IXP400_OSTS_VIRT_BASE          IXP425_TIMER_BASE_VIRT
+ #define IX_OSAL_IXP400_USB_VIRT_BASE           IXP425_USB_BASE_VIRT
+ #define IX_OSAL_IXP400_EXP_CFG_VIRT_BASE       IXP425_EXP_CFG_BASE_VIRT
+--- ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h.orig	2005-04-17 20:56:27.000000000 -0700
++++ ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h	2005-10-01 16:31:05.670092880 -0700
+@@ -85,12 +85,21 @@
+      * Queue Manager 
+      */
+     {
++#ifdef IXP425_QMGR_BASE_VIRT
+      IX_OSAL_STATIC_MAP,	/* type            */
+      IX_OSAL_IXP400_QMGR_PHYS_BASE,	/* physicalAddress */
+      IX_OSAL_IXP400_QMGR_MAP_SIZE,	/* size            */
+      IX_OSAL_IXP400_QMGR_VIRT_BASE,	/* virtualAddress  */
+      NULL,			/* mapFunction     */
+      NULL,			/* unmapFunction   */
++#else
++     IX_OSAL_DYNAMIC_MAP,                  /* type            */
++     IX_OSAL_IXP400_QMGR_PHYS_BASE,   /* physicalAddress */
++     IX_OSAL_IXP400_QMGR_MAP_SIZE,    /* size            */
++     0,                               /* virtualAddress  */
++     ixOsalLinuxMemMap,		/* mapFunction     */
++     ixOsalLinuxMemUnmap,	/* unmapFunction   */
++#endif
+      0,				/* refCount        */
+      IX_OSAL_BE | IX_OSAL_LE_DC,	/* endianType      */   
+      "qMgr"			/* name            */
+--- ixp_osal/os/linux/src/core/IxOsalOsServices.c.orig	2005-04-17 20:56:28.000000000 -0700
++++ ixp_osal/os/linux/src/core/IxOsalOsServices.c	2005-10-01 16:37:00.876444607 -0700
+@@ -54,6 +54,7 @@
+ #include <linux/time.h>
+ #include <linux/sched.h>
+ #include <linux/slab.h>
++#include <linux/interrupt.h>
+ 
+ #include "IxOsal.h"
+ 
+@@ -89,7 +90,7 @@
+ /*
+  * General interrupt handler
+  */
+-static void
++static irqreturn_t
+ ixOsalOsIsrProxy (int irq, void *dev_id, struct pt_regs *regs)
+ {
+     IxOsalInfoType *isr_proxy_info = (IxOsalInfoType *) dev_id;
+@@ -98,6 +99,7 @@
+ 		   "ixOsalOsIsrProxy: Interrupt used before ixOsalIrqBind was invoked");
+ 
+     isr_proxy_info->routine (isr_proxy_info->parameter);
++    return IRQ_HANDLED;
+ }
+ 
+ /*
+@@ -105,11 +107,12 @@
+  * This handler saves the interrupted Program Counter (PC)
+  * into a global variable
+  */
+-static void
++static irqreturn_t
+ ixOsalOsIsrProxyWithPC (int irq, void *dev_id, struct pt_regs *regs)
+ {
+     ixOsalLinuxInterruptedPc = regs->ARM_pc;
+     ixOsalOsIsrProxy(irq, dev_id, regs);
++    return IRQ_HANDLED;
+ }
+ 
+ /**************************************
+@@ -191,10 +194,15 @@
+ PUBLIC UINT32
+ ixOsalIrqLock ()
+ {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++    unsigned long flags;
++    local_irq_save(flags);
++#else
+     UINT32 flags;
+     save_flags (flags);
+     cli ();
+-    return flags;
++#endif
++    return (UINT32)flags;
+ }
+ 
+ /* Enable interrupts and task scheduling,
+@@ -204,7 +212,11 @@
+ PUBLIC void
+ ixOsalIrqUnlock (UINT32 lockKey)
+ {
++# if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++    local_irq_restore((unsigned long)lockKey);
++# else
+     restore_flags (lockKey);
++# endif
+ }
+ 
+ PUBLIC UINT32
+@@ -329,7 +341,7 @@
+ PUBLIC void
+ ixOsalSleep (UINT32 milliseconds)
+ {
+-    if (milliseconds != 0)
++    if (milliseconds*HZ >= 1000)
+     {
+         set_current_state(TASK_INTERRUPTIBLE); 
+         schedule_timeout ((milliseconds * HZ) / 1000);
+--- ixp_osal/os/linux/src/core/IxOsalOsThread.c.orig	2005-04-17 20:56:28.000000000 -0700
++++ ixp_osal/os/linux/src/core/IxOsalOsThread.c	2005-10-01 16:38:58.227829064 -0700
+@@ -46,6 +46,7 @@
+  */
+ 
+ #include <linux/sched.h>
++#include <linux/version.h>
+ 
+ #include "IxOsal.h"
+ 
+@@ -65,12 +66,12 @@
+     void *arg = IxOsalOsThreadData.arg;
+     static int seq = 0;
+ 
+-    daemonize ();
++    daemonize ("IxOsal %d", ++seq);
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
+     reparent_to_init ();
+ 
+     exit_files (current);
+-
+-    snprintf(current->comm, sizeof(current->comm), "IxOsal %d", ++seq);
++#endif
+ 
+     up (&IxOsalThreadMutex);
+ 
diff --git a/recipes/ixp4xx/ixp-osal-2.0/Makefile.patch b/recipes/ixp4xx/ixp-osal-2.0/Makefile.patch
new file mode 100644
index 0000000000..f852ea2b26
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.0/Makefile.patch
@@ -0,0 +1,27 @@
+diff -Naur ixp_osal.orig/Makefile ixp_osal/Makefile
+--- ixp_osal.orig/Makefile	2005-08-24 00:16:37.000000000 +0200
++++ ixp_osal/Makefile	2005-08-24 00:18:02.000000000 +0200
+@@ -172,7 +172,7 @@
+ 
+ # TODO push this to linux make
+ ifeq ($(IX_OSAL_MK_HOST_OS), linux)
+-INCLUDE_DIRS += $(LINUX_SRC)/include/asm-arm/arch-ixp425/
++INCLUDE_DIRS += $(LINUX_SRC)/include/asm-arm/arch-ixp4xx/
+ endif
+ 
+ CFLAGS += $(INCLUDE_DIRS:%=-I%)
+--- ixp_osal/os/linux/make/macros.mk.orig	2005-10-01 15:50:19.544167880 -0700
++++ ixp_osal/os/linux/make/macros.mk	2005-10-01 15:50:43.053647239 -0700
+@@ -88,10 +88,10 @@
+ # Compiler & linker options
+ 
+ # Compiler flags
+-LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mcpu=xscale -mtune=xscale
++LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mtune=xscale
+ 
+ CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common \
+-          -pipe -mapcs-32 -mshort-load-bytes -msoft-float -DMODULE \
++          -pipe -mapcs-32 -msoft-float -DMODULE \
+           -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS) -DEXPORT_SYMTAB
+ 
+ # Linux linker flags
diff --git a/recipes/ixp4xx/ixp-osal-2.0/le.patch b/recipes/ixp4xx/ixp-osal-2.0/le.patch
new file mode 100644
index 0000000000..ecb93d7d76
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.0/le.patch
@@ -0,0 +1,50 @@
+diff -urp ixp_osal/.pc/le.patch/include/modules/ioMem/IxOsalMemAccess.h ixp_osal/include/modules/ioMem/IxOsalMemAccess.h
+--- ixp_osal/.pc/le.patch/include/modules/ioMem/IxOsalMemAccess.h	2005-04-17 20:56:25.000000000 -0700
++++ ixp_osal/include/modules/ioMem/IxOsalMemAccess.h	2005-11-19 16:44:33.414684841 -0800
+@@ -84,7 +84,7 @@
+ 
+ #elif defined (IX_OSAL_LINUX_LE)
+ 
+-#define IX_SDRAM_LE_DATA_COHERENT
++#define IX_SDRAM_LE_ADDRESS_COHERENT
+ 
+ #elif defined (IX_OSAL_WINCE_LE)
+ 
+diff -urp ixp_osal/.pc/le.patch/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h
+--- ixp_osal/.pc/le.patch/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h	2005-04-17 20:56:27.000000000 -0700
++++ ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h	2005-11-19 16:45:35.298578949 -0800
+@@ -171,7 +171,7 @@
+  ***************************/
+ #if (IX_COMPONENT_NAME == ix_qmgr)
+ 
+-#define IX_OSAL_LE_DC_MAPPING
++#define IX_OSAL_LE_AC_MAPPING
+ 
+ #endif /* qmgr */
+ 
+diff -urp ixp_osal/.pc/le.patch/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h
+--- ixp_osal/.pc/le.patch/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h	2005-11-19 15:53:11.808771607 -0800
++++ ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h	2005-11-19 16:51:40.729574072 -0800
+@@ -101,7 +101,7 @@ IxOsalMemoryMap ixOsalGlobalMemoryMap[] 
+      ixOsalLinuxMemUnmap,	/* unmapFunction   */
+ #endif
+      0,				/* refCount        */
+-     IX_OSAL_BE | IX_OSAL_LE_DC,	/* endianType      */   
++     IX_OSAL_BE | IX_OSAL_LE_AC,	/* endianType      */   
+      "qMgr"			/* name            */
+      },
+ 
+diff -bBdurN hannes/ixp_osal/include/modules/ioMem/IxOsalIoMem.h merged/ixp_osal/include/modules/ioMem/IxOsalIoMem.h
+--- ixp_osal/include/modules/ioMem/IxOsalIoMem.h	2005-04-17 20:56:25.000000000 -0700
++++ ixp_osal/include/modules/ioMem/IxOsalIoMem.h	2005-10-07 16:20:27.786083595 -0700
+@@ -105,8 +105,8 @@
+ #endif /* ndef __wince */
+ 
+ #define IX_OSAL_SWAP_SHORT(sData)         ((sData >> 8) | ((sData & 0xFF) << 8))
+-#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((sAddr) ^ 0x2)
+-#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)  ((bAddr) ^ 0x3)
++#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((UINT16*)((UINT32)(sAddr) ^ 0x2))
++#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)  ((UINT8*)((UINT32)(bAddr) ^ 0x3))
+ 
+ #define IX_OSAL_BE_XSTOBUSL(wData)  (wData)
+ #define IX_OSAL_BE_XSTOBUSS(sData)  (sData)
diff --git a/recipes/ixp4xx/ixp-osal-2.1.1/2.6.patch b/recipes/ixp4xx/ixp-osal-2.1.1/2.6.patch
new file mode 100644
index 0000000000..9725b447c8
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1.1/2.6.patch
@@ -0,0 +1,143 @@
+ os/linux/src/core/IxOsalOsMsgQ.c      |    2 +-
+ os/linux/src/core/IxOsalOsSemaphore.c |    6 +++---
+ os/linux/src/core/IxOsalOsServices.c  |   20 ++++++++++++++++----
+ os/linux/src/core/IxOsalOsThread.c    |    7 +------
+ 4 files changed, 21 insertions(+), 14 deletions(-)
+
+--- ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c	1970-01-01 00:00:00.000000000 +0000
+@@ -45,9 +45,9 @@
+  * -- End Intel Copyright Notice --
+  */
+ #include <linux/linkage.h>
++#include <linux/spinlock.h>
+ #include <linux/ipc.h>
+ #include <linux/msg.h>
+-#include <linux/spinlock.h>
+ #include <linux/interrupt.h>
+ 
+ #include "IxOsal.h"
+--- ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c	1970-01-01 00:00:00.000000000 +0000
+@@ -46,7 +46,7 @@
+  */
+ 
+ #include <linux/slab.h>
+-#include <asm-arm/hardirq.h>
++#include <linux/hardirq.h>
+ #include "IxOsal.h"
+ 
+ /* Define a large number */
+@@ -93,7 +93,7 @@ ixOsalSemaphoreWait (IxOsalOsSemaphore *
+ {
+ 
+     IX_STATUS ixStatus = IX_SUCCESS;
+-    UINT32 timeoutTime;
++    unsigned long timeoutTime;
+ 
+     if (sid == NULL)
+     {
+@@ -261,7 +261,7 @@ ixOsalMutexInit (IxOsalMutex * mutex)
+ PUBLIC IX_STATUS
+ ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout)
+ {
+-    UINT32 timeoutTime;
++    unsigned long timeoutTime;
+ 
+     if (in_irq ())
+     {
+--- ixp_osal/os/linux/src/core/IxOsalOsServices.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsServices.c	1970-01-01 00:00:00.000000000 +0000
+@@ -54,6 +54,7 @@
+ #include <linux/time.h>
+ #include <linux/sched.h>
+ #include <linux/slab.h>
++#include <linux/interrupt.h>
+ 
+ #include "IxOsal.h"
+ 
+@@ -89,7 +90,7 @@ static IxOsalInfoType IxOsalInfo[NR_IRQS
+ /*
+  * General interrupt handler
+  */
+-static void
++static irqreturn_t
+ ixOsalOsIsrProxy (int irq, void *dev_id, struct pt_regs *regs)
+ {
+     IxOsalInfoType *isr_proxy_info = (IxOsalInfoType *) dev_id;
+@@ -98,6 +99,7 @@ ixOsalOsIsrProxy (int irq, void *dev_id,
+ 		   "ixOsalOsIsrProxy: Interrupt used before ixOsalIrqBind was invoked");
+ 
+     isr_proxy_info->routine (isr_proxy_info->parameter);
++    return IRQ_HANDLED;
+ }
+ 
+ /*
+@@ -105,11 +107,12 @@ ixOsalOsIsrProxy (int irq, void *dev_id,
+  * This handler saves the interrupted Program Counter (PC)
+  * into a global variable
+  */
+-static void
++static irqreturn_t
+ ixOsalOsIsrProxyWithPC (int irq, void *dev_id, struct pt_regs *regs)
+ {
+     ixOsalLinuxInterruptedPc = regs->ARM_pc;
+     ixOsalOsIsrProxy(irq, dev_id, regs);
++    return IRQ_HANDLED;
+ }
+ 
+ /**************************************
+@@ -191,10 +194,15 @@ ixOsalIrqUnbind (UINT32 vector)
+ PUBLIC UINT32
+ ixOsalIrqLock ()
+ {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++    unsigned long flags;
++    local_irq_save(flags);
++#else
+     UINT32 flags;
+     save_flags (flags);
+     cli ();
+-    return flags;
++#endif
++    return (UINT32)flags;
+ }
+ 
+ /* Enable interrupts and task scheduling,
+@@ -204,7 +212,11 @@ ixOsalIrqLock ()
+ PUBLIC void
+ ixOsalIrqUnlock (UINT32 lockKey)
+ {
++# if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++    local_irq_restore((unsigned long)lockKey);
++# else
+     restore_flags (lockKey);
++# endif
+ }
+ 
+ PUBLIC UINT32
+@@ -329,7 +341,7 @@ ixOsalBusySleep (UINT32 microseconds)
+ PUBLIC void
+ ixOsalSleep (UINT32 milliseconds)
+ {
+-    if (milliseconds != 0)
++    if (milliseconds*HZ >= 1000)
+     {
+         set_current_state(TASK_INTERRUPTIBLE); 
+         schedule_timeout ((milliseconds * HZ) / 1000);
+--- ixp_osal/os/linux/src/core/IxOsalOsThread.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsThread.c	1970-01-01 00:00:00.000000000 +0000
+@@ -65,12 +65,7 @@ thread_internal (void *unused)
+     void *arg = IxOsalOsThreadData.arg;
+     static int seq = 0;
+ 
+-    daemonize ();
+-    reparent_to_init ();
+-
+-    exit_files (current);
+-
+-    snprintf(current->comm, sizeof(current->comm), "IxOsal %d", ++seq);
++    daemonize ("IxOsal %d", ++seq);
+ 
+     up (&IxOsalThreadMutex);
+ 
diff --git a/recipes/ixp4xx/ixp-osal-2.1.1/Makefile.patch b/recipes/ixp4xx/ixp-osal-2.1.1/Makefile.patch
new file mode 100644
index 0000000000..1558e9cdb3
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1.1/Makefile.patch
@@ -0,0 +1,30 @@
+ Makefile                |    2 +-
+ os/linux/make/macros.mk |    4 ++--
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+--- ixp_osal/Makefile	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/Makefile	1970-01-01 00:00:00.000000000 +0000
+@@ -185,7 +185,7 @@ endif
+ INCLUDE_DIRS = include $(OSAL_DIRS:%=$(MAIN_INC_PREFIX)/%) $(OSAL_DIRS:%=$(OS_INC_PREFIX)/%)  
+ 
+ ifeq ($(IX_OSAL_MK_HOST_OS), linux)
+-INCLUDE_DIRS += $(LINUX_SRC)/include/asm-arm/arch-ixp425/
++INCLUDE_DIRS += $(LINUX_SRC)/include/asm-arm/arch-ixp4xx/
+ endif
+ 
+ CFLAGS += $(INCLUDE_DIRS:%=-I%) 
+--- ixp_osal/os/linux/make/macros.mk	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/make/macros.mk	1970-01-01 00:00:00.000000000 +0000
+@@ -88,10 +88,10 @@ AR := $(LINUX_CROSS_COMPILE)ar
+ # Compiler & linker options
+ 
+ # Compiler flags
+-LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mcpu=xscale -mtune=xscale
++LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mtune=xscale
+ 
+ CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common \
+-          -pipe -mapcs-32 -mshort-load-bytes -msoft-float -DMODULE \
++          -pipe -msoft-float -DMODULE \
+           -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS) -DEXPORT_SYMTAB
+ 
+ # Linux linker flags
diff --git a/recipes/ixp4xx/ixp-osal-2.1.1/assert.patch b/recipes/ixp4xx/ixp-osal-2.1.1/assert.patch
new file mode 100644
index 0000000000..a03113dcc2
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1.1/assert.patch
@@ -0,0 +1,41 @@
+# Unnecessary patch - reduces the code size slightly, gives clearer
+# messages if IX_OSAL_ENSURE_ON is set
+# include/IxOsalAssert.h                 |    4 ++--
+# os/linux/include/core/IxOsalOsAssert.h |    9 ++++++++-
+# 2 files changed, 10 insertions(+), 3 deletions(-)
+#
+--- ixp_osal/include/IxOsalAssert.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/include/IxOsalAssert.h	1970-01-01 00:00:00.000000000 +0000
+@@ -72,8 +72,8 @@
+  */
+ #ifdef IX_OSAL_ENSURE_ON
+ #define IX_OSAL_ENSURE(c, str) do { \
+-if (!(c)) ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, str, \
+-0, 0, 0, 0, 0, 0); } while (0)
++if (!(c)) ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, __FILE__ ": line %d: " str, \
++__LINE__, 0, 0, 0, 0, 0); } while (0)
+ 
+ #else
+ #define IX_OSAL_ENSURE(c, str)
+--- ixp_osal/os/linux/include/core/IxOsalOsAssert.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/core/IxOsalOsAssert.h	1970-01-01 00:00:00.000000000 +0000
+@@ -47,11 +47,18 @@
+ 
+ #ifndef IxOsalOsAssert_H
+ #define IxOsalOsAssert_H
++#ifdef IX_OSAL_ENSURE_ON
+ #define IX_OSAL_OS_ASSERT(c)    if(!(c)) \
+                                 { \
+-                                    ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "Assertion failure \n", 0, 0, 0, 0, 0, 0);\
++                                    ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "%s line %d: Assertion failure: %s\n", (int)__FILE__, __LINE__, (int)#c, 0, 0, 0);\
+                                     BUG(); \
+                                 }
++#else
++#define IX_OSAL_OS_ASSERT(c)    if(!(c)) \
++                                { \
++                                    BUG(); \
++                                }
++#endif
+ 
+ /* 
+  * Place holder.
diff --git a/recipes/ixp4xx/ixp-osal-2.1.1/invalidate-cache.patch b/recipes/ixp4xx/ixp-osal-2.1.1/invalidate-cache.patch
new file mode 100644
index 0000000000..33c1d132db
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1.1/invalidate-cache.patch
@@ -0,0 +1,115 @@
+ os/linux/include/core/IxOsalOs.h     |   17 ++++++++++
+ os/linux/src/core/IxOsalOsCacheMMU.c |   56 +++++++++++++++++++++++++++++++++++
+ os/linux/src/core/IxOsalOsSymbols.c  |    4 ++
+ 3 files changed, 76 insertions(+), 1 deletion(-)
+
+--- ixp_osal/os/linux/include/core/IxOsalOs.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/core/IxOsalOs.h	1970-01-01 00:00:00.000000000 +0000
+@@ -56,6 +56,7 @@
+ #include <linux/cache.h>
+ #include <linux/mm.h>
+ #include <linux/config.h>
++#include <linux/version.h>
+ #include <asm/pgalloc.h>
+ 
+ /**
+@@ -66,9 +67,23 @@
+ 
+ #define IX_OSAL_OS_MMU_PHYS_TO_VIRT(addr)  ((addr) ? phys_to_virt((unsigned int)(addr)) : 0)
+ 
+-#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)  ( invalidate_dcache_range((__u32)addr, (__u32)addr + size )) 
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++/*
++ * 2.6 kernels do not export the required cache functions.
++ */
++extern void ixOsalCacheInvalidateRange(unsigned long start, unsigned long size);
++extern void ixOsalCacheFlushRange(unsigned long start, unsigned long size);
++
++#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size) \
++ixOsalCacheInvalidateRange((unsigned long)addr, (unsigned long)addr + size)
++#define IX_OSAL_OS_CACHE_FLUSH(addr, size) \
++ixOsalCacheFlushRange((unsigned long)addr, (unsigned long)addr + size )
+ 
++#else
++
++#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)  ( invalidate_dcache_range((__u32)addr, (__u32)addr + size ))
+ #define IX_OSAL_OS_CACHE_FLUSH(addr, size) ( clean_dcache_range((__u32)addr, (__u32)addr + size ))
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) */
+ 
+ /* Cache preload not available*/
+ #define IX_OSAL_OS_CACHE_PRELOAD(addr,size) {}
+--- ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c	1970-01-01 00:00:00.000000000 +0000
+@@ -210,3 +210,59 @@ ixOsalCacheDmaFree (void *ptr)
+ 	free_pages ((unsigned int) memptr, order);
+     }
+ }
++
++
++/*
++ * 2.6 kernels do not export the required cache functions.
++ */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++
++#define _IX_STR(x) #x
++#define IX_STR(x) _IX_STR(x)
++#define IX_CLM IX_STR(IX_OSAL_CACHE_LINE_SIZE-1)
++
++/*
++ * reimplementation of kernel's invalidate_dcache_range()
++ */
++void
++ixOsalCacheInvalidateRange(unsigned long start, unsigned long size)
++{
++  __asm__
++    ("    tst    %0, #" IX_CLM "\n"
++     "    mcrne  p15, 0, %0, c7, c10, 1      @ clean D cache line\n"
++     "    bic    %0, %0, #" IX_CLM "\n"
++     "    tst    %1, #" IX_CLM "\n"
++     "    mcrne  p15, 0, %1, c7, c10, 1      @ clean D cache line\n"
++     "1:  mcr    p15, 0, %0, c7, c6, 1       @ invalidate D cache line\n"
++     "    add    %0, %0, #" IX_STR(IX_OSAL_CACHE_LINE_SIZE) "\n"
++     "    cmp    %0, %1\n"
++     "    blo    1b\n"
++     "    mcr    p15, 0, %0, c7, c10, 4      @ drain write & fill buffer\n"
++     : /* no output */
++     : "r"(start), "r"(size)
++     : "cc");
++}
++
++/*
++ * reimplementation of kernel's invalidate_dcache_range()
++ */
++void
++ixOsalCacheFlushRange(unsigned long start, unsigned long size)
++{
++  __asm__
++    ("    bic    %0, %0, #" IX_CLM "\n"
++     "1:  mcr    p15, 0, %0, c7, c10, 1      @ clean D cache line\n"
++     "    add    %0, %0, #" IX_STR(IX_OSAL_CACHE_LINE_SIZE) "\n"
++     "    cmp    %0, %1\n"
++     "    blo    1b\n"
++     "    mcr    p15, 0, %0, c7, c10, 4      @ drain write & fill buffer\n"
++     : /* no output */
++     : "r"(start), "r"(size)
++     : "cc");
++}
++
++#undef _IX_STR
++#undef IX_STR
++#undef IX_CLM
++
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) */
+--- ixp_osal/os/linux/src/core/IxOsalOsSymbols.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsSymbols.c	1970-01-01 00:00:00.000000000 +0000
+@@ -64,6 +64,10 @@ EXPORT_SYMBOL (ixOsalMemSet);
+ 
+ EXPORT_SYMBOL (ixOsalCacheDmaMalloc);
+ EXPORT_SYMBOL (ixOsalCacheDmaFree);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++EXPORT_SYMBOL (ixOsalCacheInvalidateRange);
++EXPORT_SYMBOL (ixOsalCacheFlushRange);
++#endif
+ 
+ EXPORT_SYMBOL (ixOsalThreadCreate);
+ EXPORT_SYMBOL (ixOsalThreadStart);
diff --git a/recipes/ixp4xx/ixp-osal-2.1.1/ixp4xx-header.patch b/recipes/ixp4xx/ixp-osal-2.1.1/ixp4xx-header.patch
new file mode 100644
index 0000000000..a9d87d4b56
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1.1/ixp4xx-header.patch
@@ -0,0 +1,115 @@
+ os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Base.h |   72 ++++++++++
+ os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h  |   10 -
+ 2 files changed, 78 insertions(+), 4 deletions(-)
+
+--- ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h	1970-01-01 00:00:00.000000000 +0000
+@@ -53,6 +53,8 @@
+ #error "Error: IxOsalOsIxp425Sys.h cannot be included directly before IxOsalOsIxp400.h"
+ #endif
+ 
++#include "IxOsalOsIxp425Base.h"
++
+ /* Memory Base Address */
+ #define IX_OSAL_IXP400_EXP_BUS_PHYS_BASE       	IXP425_EXP_BUS_BASE2_PHYS
+ #define IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE  	IXP425_EXP_BUS_BASE1_PHYS
+@@ -98,12 +100,12 @@ IxOsalMemoryMap ixOsalGlobalMemoryMap[] 
+      * Queue Manager 
+      */
+     {
+-     IX_OSAL_STATIC_MAP,	/* type            */
++     IX_OSAL_DYNAMIC_MAP,	/* type            */
+      IX_OSAL_IXP400_QMGR_PHYS_BASE,	/* physicalAddress */
+      IX_OSAL_IXP400_QMGR_MAP_SIZE,	/* size            */
+-     IX_OSAL_IXP400_QMGR_VIRT_BASE,	/* virtualAddress  */
+-     NULL,			/* mapFunction     */
+-     NULL,			/* unmapFunction   */
++     0,				/* virtualAddress  */
++     ixOsalLinuxMemMap,		/* mapFunction     */
++     ixOsalLinuxMemUnmap,	/* unmapFunction   */
+      0,				/* refCount        */
+      IX_OSAL_BE | IX_OSAL_LE_DC,	/* endianType      */   
+      "qMgr"			/* name            */
+--- ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Base.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Base.h	1970-01-01 00:00:00.000000000 +0000
+@@ -0,0 +1,80 @@
++/*
++ * Glue for the current linux definitons of this stuff.
++ */
++#ifndef IxOsalOsIxp425Base_H
++#define IxOsalOsIxp425Base_H 1
++#include <asm-arm/arch-ixp4xx/ixp4xx-regs.h>
++#include <linux/version.h>
++
++/* Force Address Coherent (the default) mapping on LE - Linux 2.6
++ * does not have a way of changing it.
++ */
++#if defined IX_OSAL_LINUX_LE
++# if !defined IX_OSAL_ENFORCED_LE_AC_MAPPING
++#  define IX_OSAL_ENFORCED_LE_AC_MAPPING
++# endif
++# if defined IX_OSAL_LE_DC_MAPPING
++#  error Little Endian Data Coherent mapping not supported on this platform
++# endif
++
++/* This doesn't matter on a BE build because it will never be used,
++ * however it will be selected and will fail on an LE build.
++ */
++# undef IX_OSAL_LE_DC
++# define IX_OSAL_LE_DC IX_OSAL_LE_DC_IS_INVALID_ON_THIS_PLATFORM
++#endif
++
++/* Physical addresses. */
++#define IXP425_PERIPHERAL_BASE_PHYS	IXP4XX_PERIPHERAL_BASE_PHYS
++#define IXP425_EXP_CFG_BASE_PHYS	IXP4XX_EXP_CFG_BASE_PHYS
++#define IXP425_PCI_CFG_BASE_PHYS	IXP4XX_PCI_CFG_BASE_PHYS
++
++//#define IXP425_EXP_BUS_BASE1_PHYS
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)
++#define IXP425_EXP_BUS_BASE2_PHYS	IXP4XX_EXP_BUS_CS2_BASE_PHYS
++#else
++/* The following definition should be IXP4XX_EXP_BUS_BASE(2), but that is not
++   static and causes compilation problems later.  So we need to hard-code it.
++   Note that this hard-coded value is only correct for IXP42X. */
++#define IXP425_EXP_BUS_BASE2_PHYS	(IXP4XX_EXP_BUS_BASE_PHYS + (2 * SZ_16M))
++#endif
++//#define IXP425_EXP_BUS_CS0_BASE_PHYS
++//#define IXP425_EXP_BUS_CS1_BASE_PHYS
++//#define IXP425_EXP_BUS_CS4_BASE_PHYS
++#define IXP425_EthA_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
++#define IXP425_EthB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
++//#define IXP425_GPIO_BASE_PHYS
++#define IXP425_INTC_BASE_PHYS		IXP4XX_INTC_BASE_PHYS
++//#define IXP425_NPEA_BASE_PHYS
++//#define IXP425_NPEB_BASE_PHYS
++//#define IXP425_NPEC_BASE_PHYS
++//#define IXP425_PMU_BASE_PHYS
++#define IXP425_QMGR_BASE_PHYS		IXP4XX_QMGR_BASE_PHYS
++#define IXP425_TIMER_BASE_PHYS 		IXP4XX_TIMER_BASE_PHYS
++//#define IXP425_UART1_BASE_PHYS
++//#define IXP425_UART2_BASE_PHYS
++#define IXP425_USB_BASE_PHYS		IXP4XX_USB_BASE_PHYS
++
++/* Virtual addresses. */
++#define IXP425_PERIPHERAL_BASE_VIRT	IXP4XX_PERIPHERAL_BASE_VIRT
++#define IXP425_PERIPHERAL_REGION_SIZE	IXP4XX_PERIPHERAL_REGION_SIZE
++#define IXP425_EXP_CFG_BASE_VIRT	IXP4XX_EXP_CFG_BASE_VIRT
++#define IXP425_PCI_CFG_BASE_VIRT	IXP4XX_PCI_CFG_BASE_VIRT
++
++//#define IXP425_EthA_BASE_VIRT
++//#define IXP425_EthB_BASE_VIRT
++//#define IXP425_GPIO_BASE_VIRT
++//#define IXP425_NPEA_BASE_VIRT
++//#define IXP425_NPEB_BASE_VIRT
++//#define IXP425_NPEC_BASE_VIRT
++//#define IXP425_QMGR_BASE_VIRT	/* must be ioremapped on Linux 2.6 */
++//#define IXP425_TIMER_BASE_VIRT
++//#define IXP425_UART1_BASE_VIRT
++//#define IXP425_UART2_BASE_VIRT
++//#define IXP425_USB_BASE_VIRT
++
++/* Miscellaneous stuff. */
++#define IRQ_IXP425_XSCALE_PMU		IRQ_IXP4XX_XSCALE_PMU
++#define IXP425_ICMR			IXP4XX_ICMR
++#define IRQ_IXP425_USB			IRQ_IXP4XX_USB
++#endif
diff --git a/recipes/ixp4xx/ixp-osal-2.1.1/le.patch b/recipes/ixp4xx/ixp-osal-2.1.1/le.patch
new file mode 100644
index 0000000000..a6936ea33b
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1.1/le.patch
@@ -0,0 +1,72 @@
+ include/modules/ioMem/IxOsalIoMem.h                                 |    4 ++--
+ include/modules/ioMem/IxOsalMemAccess.h                             |    2 +-
+ os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h |    2 +-
+ os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h        |    2 +-
+ os/linux/src/modules/ioMem/IxOsalOsIoMem.c                          |    3 +++
+ 5 files changed, 8 insertions(+), 5 deletions(-)
+
+--- ixp_osal/include/modules/ioMem/IxOsalIoMem.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/include/modules/ioMem/IxOsalIoMem.h	1970-01-01 00:00:00.000000000 +0000
+@@ -117,8 +117,8 @@ ixOsalCoreWordSwap (UINT32 wordIn)
+ #endif /* ndef __wince */
+ 
+ #define IX_OSAL_SWAP_SHORT(sData)         ((sData >> 8) | ((sData & 0xFF) << 8))
+-#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((sAddr) ^ 0x2)
+-#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)  ((bAddr) ^ 0x3)
++#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((UINT16*)((UINT32)(sAddr) ^ 0x2))
++#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)  ((UINT8*)((UINT32)(bAddr) ^ 0x3))
+ 
+ #define IX_OSAL_BE_XSTOBUSL(wData)  (wData)
+ #define IX_OSAL_BE_XSTOBUSS(sData)  (sData)
+--- ixp_osal/include/modules/ioMem/IxOsalMemAccess.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/include/modules/ioMem/IxOsalMemAccess.h	1970-01-01 00:00:00.000000000 +0000
+@@ -84,7 +84,7 @@
+ 
+ #elif defined (IX_OSAL_LINUX_LE)
+ 
+-#define IX_SDRAM_LE_DATA_COHERENT
++#define IX_SDRAM_LE_ADDRESS_COHERENT
+ 
+ #elif defined (IX_OSAL_WINCE_LE)
+ 
+--- ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h	1970-01-01 00:00:00.000000000 +0000
+@@ -171,7 +171,7 @@
+  ***************************/
+ #if (IX_COMPONENT_NAME == ix_qmgr)
+ 
+-#define IX_OSAL_LE_DC_MAPPING
++#define IX_OSAL_LE_AC_MAPPING
+ 
+ #endif /* qmgr */
+ 
+--- ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h	1970-01-01 00:00:00.000000000 +0000
+@@ -107,7 +107,7 @@ IxOsalMemoryMap ixOsalGlobalMemoryMap[] 
+      ixOsalLinuxMemMap,		/* mapFunction     */
+      ixOsalLinuxMemUnmap,	/* unmapFunction   */
+      0,				/* refCount        */
+-     IX_OSAL_BE | IX_OSAL_LE_DC,	/* endianType      */   
++     IX_OSAL_BE | IX_OSAL_LE_AC,	/* endianType      */
+      "qMgr"			/* name            */
+      },
+ 
+--- ixp_osal/os/linux/src/modules/ioMem/IxOsalOsIoMem.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/modules/ioMem/IxOsalOsIoMem.c	1970-01-01 00:00:00.000000000 +0000
+@@ -45,6 +45,7 @@
+  * -- End Intel Copyright Notice --
+  */
+ 
++#include <asm/page.h>
+ #include <asm/io.h>
+ #include <linux/ioport.h>
+ 
+@@ -54,6 +55,8 @@
+ PUBLIC void
+ ixOsalLinuxMemMap (IxOsalMemoryMap * map)
+ {
++    /* Linux requires LE mappings to use address coherency */
++    IX_OSAL_ENSURE((map->mapEndianType & IX_OSAL_LE_DC) == 0, "LE Data Coherency not supported");
+     map->virtualAddress = (UINT32) ioremap (map->physicalAddress, map->size);
+ }
+ 
diff --git a/recipes/ixp4xx/ixp-osal-2.1/2.6.patch b/recipes/ixp4xx/ixp-osal-2.1/2.6.patch
new file mode 100644
index 0000000000..9725b447c8
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1/2.6.patch
@@ -0,0 +1,143 @@
+ os/linux/src/core/IxOsalOsMsgQ.c      |    2 +-
+ os/linux/src/core/IxOsalOsSemaphore.c |    6 +++---
+ os/linux/src/core/IxOsalOsServices.c  |   20 ++++++++++++++++----
+ os/linux/src/core/IxOsalOsThread.c    |    7 +------
+ 4 files changed, 21 insertions(+), 14 deletions(-)
+
+--- ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c	1970-01-01 00:00:00.000000000 +0000
+@@ -45,9 +45,9 @@
+  * -- End Intel Copyright Notice --
+  */
+ #include <linux/linkage.h>
++#include <linux/spinlock.h>
+ #include <linux/ipc.h>
+ #include <linux/msg.h>
+-#include <linux/spinlock.h>
+ #include <linux/interrupt.h>
+ 
+ #include "IxOsal.h"
+--- ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c	1970-01-01 00:00:00.000000000 +0000
+@@ -46,7 +46,7 @@
+  */
+ 
+ #include <linux/slab.h>
+-#include <asm-arm/hardirq.h>
++#include <linux/hardirq.h>
+ #include "IxOsal.h"
+ 
+ /* Define a large number */
+@@ -93,7 +93,7 @@ ixOsalSemaphoreWait (IxOsalOsSemaphore *
+ {
+ 
+     IX_STATUS ixStatus = IX_SUCCESS;
+-    UINT32 timeoutTime;
++    unsigned long timeoutTime;
+ 
+     if (sid == NULL)
+     {
+@@ -261,7 +261,7 @@ ixOsalMutexInit (IxOsalMutex * mutex)
+ PUBLIC IX_STATUS
+ ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout)
+ {
+-    UINT32 timeoutTime;
++    unsigned long timeoutTime;
+ 
+     if (in_irq ())
+     {
+--- ixp_osal/os/linux/src/core/IxOsalOsServices.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsServices.c	1970-01-01 00:00:00.000000000 +0000
+@@ -54,6 +54,7 @@
+ #include <linux/time.h>
+ #include <linux/sched.h>
+ #include <linux/slab.h>
++#include <linux/interrupt.h>
+ 
+ #include "IxOsal.h"
+ 
+@@ -89,7 +90,7 @@ static IxOsalInfoType IxOsalInfo[NR_IRQS
+ /*
+  * General interrupt handler
+  */
+-static void
++static irqreturn_t
+ ixOsalOsIsrProxy (int irq, void *dev_id, struct pt_regs *regs)
+ {
+     IxOsalInfoType *isr_proxy_info = (IxOsalInfoType *) dev_id;
+@@ -98,6 +99,7 @@ ixOsalOsIsrProxy (int irq, void *dev_id,
+ 		   "ixOsalOsIsrProxy: Interrupt used before ixOsalIrqBind was invoked");
+ 
+     isr_proxy_info->routine (isr_proxy_info->parameter);
++    return IRQ_HANDLED;
+ }
+ 
+ /*
+@@ -105,11 +107,12 @@ ixOsalOsIsrProxy (int irq, void *dev_id,
+  * This handler saves the interrupted Program Counter (PC)
+  * into a global variable
+  */
+-static void
++static irqreturn_t
+ ixOsalOsIsrProxyWithPC (int irq, void *dev_id, struct pt_regs *regs)
+ {
+     ixOsalLinuxInterruptedPc = regs->ARM_pc;
+     ixOsalOsIsrProxy(irq, dev_id, regs);
++    return IRQ_HANDLED;
+ }
+ 
+ /**************************************
+@@ -191,10 +194,15 @@ ixOsalIrqUnbind (UINT32 vector)
+ PUBLIC UINT32
+ ixOsalIrqLock ()
+ {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++    unsigned long flags;
++    local_irq_save(flags);
++#else
+     UINT32 flags;
+     save_flags (flags);
+     cli ();
+-    return flags;
++#endif
++    return (UINT32)flags;
+ }
+ 
+ /* Enable interrupts and task scheduling,
+@@ -204,7 +212,11 @@ ixOsalIrqLock ()
+ PUBLIC void
+ ixOsalIrqUnlock (UINT32 lockKey)
+ {
++# if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++    local_irq_restore((unsigned long)lockKey);
++# else
+     restore_flags (lockKey);
++# endif
+ }
+ 
+ PUBLIC UINT32
+@@ -329,7 +341,7 @@ ixOsalBusySleep (UINT32 microseconds)
+ PUBLIC void
+ ixOsalSleep (UINT32 milliseconds)
+ {
+-    if (milliseconds != 0)
++    if (milliseconds*HZ >= 1000)
+     {
+         set_current_state(TASK_INTERRUPTIBLE); 
+         schedule_timeout ((milliseconds * HZ) / 1000);
+--- ixp_osal/os/linux/src/core/IxOsalOsThread.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsThread.c	1970-01-01 00:00:00.000000000 +0000
+@@ -65,12 +65,7 @@ thread_internal (void *unused)
+     void *arg = IxOsalOsThreadData.arg;
+     static int seq = 0;
+ 
+-    daemonize ();
+-    reparent_to_init ();
+-
+-    exit_files (current);
+-
+-    snprintf(current->comm, sizeof(current->comm), "IxOsal %d", ++seq);
++    daemonize ("IxOsal %d", ++seq);
+ 
+     up (&IxOsalThreadMutex);
+ 
diff --git a/recipes/ixp4xx/ixp-osal-2.1/Makefile.patch b/recipes/ixp4xx/ixp-osal-2.1/Makefile.patch
new file mode 100644
index 0000000000..1558e9cdb3
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1/Makefile.patch
@@ -0,0 +1,30 @@
+ Makefile                |    2 +-
+ os/linux/make/macros.mk |    4 ++--
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+--- ixp_osal/Makefile	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/Makefile	1970-01-01 00:00:00.000000000 +0000
+@@ -185,7 +185,7 @@ endif
+ INCLUDE_DIRS = include $(OSAL_DIRS:%=$(MAIN_INC_PREFIX)/%) $(OSAL_DIRS:%=$(OS_INC_PREFIX)/%)  
+ 
+ ifeq ($(IX_OSAL_MK_HOST_OS), linux)
+-INCLUDE_DIRS += $(LINUX_SRC)/include/asm-arm/arch-ixp425/
++INCLUDE_DIRS += $(LINUX_SRC)/include/asm-arm/arch-ixp4xx/
+ endif
+ 
+ CFLAGS += $(INCLUDE_DIRS:%=-I%) 
+--- ixp_osal/os/linux/make/macros.mk	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/make/macros.mk	1970-01-01 00:00:00.000000000 +0000
+@@ -88,10 +88,10 @@ AR := $(LINUX_CROSS_COMPILE)ar
+ # Compiler & linker options
+ 
+ # Compiler flags
+-LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mcpu=xscale -mtune=xscale
++LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mtune=xscale
+ 
+ CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common \
+-          -pipe -mapcs-32 -mshort-load-bytes -msoft-float -DMODULE \
++          -pipe -msoft-float -DMODULE \
+           -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS) -DEXPORT_SYMTAB
+ 
+ # Linux linker flags
diff --git a/recipes/ixp4xx/ixp-osal-2.1/assert.patch b/recipes/ixp4xx/ixp-osal-2.1/assert.patch
new file mode 100644
index 0000000000..a03113dcc2
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1/assert.patch
@@ -0,0 +1,41 @@
+# Unnecessary patch - reduces the code size slightly, gives clearer
+# messages if IX_OSAL_ENSURE_ON is set
+# include/IxOsalAssert.h                 |    4 ++--
+# os/linux/include/core/IxOsalOsAssert.h |    9 ++++++++-
+# 2 files changed, 10 insertions(+), 3 deletions(-)
+#
+--- ixp_osal/include/IxOsalAssert.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/include/IxOsalAssert.h	1970-01-01 00:00:00.000000000 +0000
+@@ -72,8 +72,8 @@
+  */
+ #ifdef IX_OSAL_ENSURE_ON
+ #define IX_OSAL_ENSURE(c, str) do { \
+-if (!(c)) ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, str, \
+-0, 0, 0, 0, 0, 0); } while (0)
++if (!(c)) ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, __FILE__ ": line %d: " str, \
++__LINE__, 0, 0, 0, 0, 0); } while (0)
+ 
+ #else
+ #define IX_OSAL_ENSURE(c, str)
+--- ixp_osal/os/linux/include/core/IxOsalOsAssert.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/core/IxOsalOsAssert.h	1970-01-01 00:00:00.000000000 +0000
+@@ -47,11 +47,18 @@
+ 
+ #ifndef IxOsalOsAssert_H
+ #define IxOsalOsAssert_H
++#ifdef IX_OSAL_ENSURE_ON
+ #define IX_OSAL_OS_ASSERT(c)    if(!(c)) \
+                                 { \
+-                                    ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "Assertion failure \n", 0, 0, 0, 0, 0, 0);\
++                                    ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "%s line %d: Assertion failure: %s\n", (int)__FILE__, __LINE__, (int)#c, 0, 0, 0);\
+                                     BUG(); \
+                                 }
++#else
++#define IX_OSAL_OS_ASSERT(c)    if(!(c)) \
++                                { \
++                                    BUG(); \
++                                }
++#endif
+ 
+ /* 
+  * Place holder.
diff --git a/recipes/ixp4xx/ixp-osal-2.1/invalidate-cache.patch b/recipes/ixp4xx/ixp-osal-2.1/invalidate-cache.patch
new file mode 100644
index 0000000000..33c1d132db
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1/invalidate-cache.patch
@@ -0,0 +1,115 @@
+ os/linux/include/core/IxOsalOs.h     |   17 ++++++++++
+ os/linux/src/core/IxOsalOsCacheMMU.c |   56 +++++++++++++++++++++++++++++++++++
+ os/linux/src/core/IxOsalOsSymbols.c  |    4 ++
+ 3 files changed, 76 insertions(+), 1 deletion(-)
+
+--- ixp_osal/os/linux/include/core/IxOsalOs.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/core/IxOsalOs.h	1970-01-01 00:00:00.000000000 +0000
+@@ -56,6 +56,7 @@
+ #include <linux/cache.h>
+ #include <linux/mm.h>
+ #include <linux/config.h>
++#include <linux/version.h>
+ #include <asm/pgalloc.h>
+ 
+ /**
+@@ -66,9 +67,23 @@
+ 
+ #define IX_OSAL_OS_MMU_PHYS_TO_VIRT(addr)  ((addr) ? phys_to_virt((unsigned int)(addr)) : 0)
+ 
+-#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)  ( invalidate_dcache_range((__u32)addr, (__u32)addr + size )) 
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++/*
++ * 2.6 kernels do not export the required cache functions.
++ */
++extern void ixOsalCacheInvalidateRange(unsigned long start, unsigned long size);
++extern void ixOsalCacheFlushRange(unsigned long start, unsigned long size);
++
++#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size) \
++ixOsalCacheInvalidateRange((unsigned long)addr, (unsigned long)addr + size)
++#define IX_OSAL_OS_CACHE_FLUSH(addr, size) \
++ixOsalCacheFlushRange((unsigned long)addr, (unsigned long)addr + size )
+ 
++#else
++
++#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)  ( invalidate_dcache_range((__u32)addr, (__u32)addr + size ))
+ #define IX_OSAL_OS_CACHE_FLUSH(addr, size) ( clean_dcache_range((__u32)addr, (__u32)addr + size ))
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) */
+ 
+ /* Cache preload not available*/
+ #define IX_OSAL_OS_CACHE_PRELOAD(addr,size) {}
+--- ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c	1970-01-01 00:00:00.000000000 +0000
+@@ -210,3 +210,59 @@ ixOsalCacheDmaFree (void *ptr)
+ 	free_pages ((unsigned int) memptr, order);
+     }
+ }
++
++
++/*
++ * 2.6 kernels do not export the required cache functions.
++ */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++
++#define _IX_STR(x) #x
++#define IX_STR(x) _IX_STR(x)
++#define IX_CLM IX_STR(IX_OSAL_CACHE_LINE_SIZE-1)
++
++/*
++ * reimplementation of kernel's invalidate_dcache_range()
++ */
++void
++ixOsalCacheInvalidateRange(unsigned long start, unsigned long size)
++{
++  __asm__
++    ("    tst    %0, #" IX_CLM "\n"
++     "    mcrne  p15, 0, %0, c7, c10, 1      @ clean D cache line\n"
++     "    bic    %0, %0, #" IX_CLM "\n"
++     "    tst    %1, #" IX_CLM "\n"
++     "    mcrne  p15, 0, %1, c7, c10, 1      @ clean D cache line\n"
++     "1:  mcr    p15, 0, %0, c7, c6, 1       @ invalidate D cache line\n"
++     "    add    %0, %0, #" IX_STR(IX_OSAL_CACHE_LINE_SIZE) "\n"
++     "    cmp    %0, %1\n"
++     "    blo    1b\n"
++     "    mcr    p15, 0, %0, c7, c10, 4      @ drain write & fill buffer\n"
++     : /* no output */
++     : "r"(start), "r"(size)
++     : "cc");
++}
++
++/*
++ * reimplementation of kernel's invalidate_dcache_range()
++ */
++void
++ixOsalCacheFlushRange(unsigned long start, unsigned long size)
++{
++  __asm__
++    ("    bic    %0, %0, #" IX_CLM "\n"
++     "1:  mcr    p15, 0, %0, c7, c10, 1      @ clean D cache line\n"
++     "    add    %0, %0, #" IX_STR(IX_OSAL_CACHE_LINE_SIZE) "\n"
++     "    cmp    %0, %1\n"
++     "    blo    1b\n"
++     "    mcr    p15, 0, %0, c7, c10, 4      @ drain write & fill buffer\n"
++     : /* no output */
++     : "r"(start), "r"(size)
++     : "cc");
++}
++
++#undef _IX_STR
++#undef IX_STR
++#undef IX_CLM
++
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) */
+--- ixp_osal/os/linux/src/core/IxOsalOsSymbols.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/core/IxOsalOsSymbols.c	1970-01-01 00:00:00.000000000 +0000
+@@ -64,6 +64,10 @@ EXPORT_SYMBOL (ixOsalMemSet);
+ 
+ EXPORT_SYMBOL (ixOsalCacheDmaMalloc);
+ EXPORT_SYMBOL (ixOsalCacheDmaFree);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++EXPORT_SYMBOL (ixOsalCacheInvalidateRange);
++EXPORT_SYMBOL (ixOsalCacheFlushRange);
++#endif
+ 
+ EXPORT_SYMBOL (ixOsalThreadCreate);
+ EXPORT_SYMBOL (ixOsalThreadStart);
diff --git a/recipes/ixp4xx/ixp-osal-2.1/ixp4xx-header.patch b/recipes/ixp4xx/ixp-osal-2.1/ixp4xx-header.patch
new file mode 100644
index 0000000000..a9d87d4b56
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1/ixp4xx-header.patch
@@ -0,0 +1,115 @@
+ os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Base.h |   72 ++++++++++
+ os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h  |   10 -
+ 2 files changed, 78 insertions(+), 4 deletions(-)
+
+--- ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h	1970-01-01 00:00:00.000000000 +0000
+@@ -53,6 +53,8 @@
+ #error "Error: IxOsalOsIxp425Sys.h cannot be included directly before IxOsalOsIxp400.h"
+ #endif
+ 
++#include "IxOsalOsIxp425Base.h"
++
+ /* Memory Base Address */
+ #define IX_OSAL_IXP400_EXP_BUS_PHYS_BASE       	IXP425_EXP_BUS_BASE2_PHYS
+ #define IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE  	IXP425_EXP_BUS_BASE1_PHYS
+@@ -98,12 +100,12 @@ IxOsalMemoryMap ixOsalGlobalMemoryMap[] 
+      * Queue Manager 
+      */
+     {
+-     IX_OSAL_STATIC_MAP,	/* type            */
++     IX_OSAL_DYNAMIC_MAP,	/* type            */
+      IX_OSAL_IXP400_QMGR_PHYS_BASE,	/* physicalAddress */
+      IX_OSAL_IXP400_QMGR_MAP_SIZE,	/* size            */
+-     IX_OSAL_IXP400_QMGR_VIRT_BASE,	/* virtualAddress  */
+-     NULL,			/* mapFunction     */
+-     NULL,			/* unmapFunction   */
++     0,				/* virtualAddress  */
++     ixOsalLinuxMemMap,		/* mapFunction     */
++     ixOsalLinuxMemUnmap,	/* unmapFunction   */
+      0,				/* refCount        */
+      IX_OSAL_BE | IX_OSAL_LE_DC,	/* endianType      */   
+      "qMgr"			/* name            */
+--- ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Base.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Base.h	1970-01-01 00:00:00.000000000 +0000
+@@ -0,0 +1,80 @@
++/*
++ * Glue for the current linux definitons of this stuff.
++ */
++#ifndef IxOsalOsIxp425Base_H
++#define IxOsalOsIxp425Base_H 1
++#include <asm-arm/arch-ixp4xx/ixp4xx-regs.h>
++#include <linux/version.h>
++
++/* Force Address Coherent (the default) mapping on LE - Linux 2.6
++ * does not have a way of changing it.
++ */
++#if defined IX_OSAL_LINUX_LE
++# if !defined IX_OSAL_ENFORCED_LE_AC_MAPPING
++#  define IX_OSAL_ENFORCED_LE_AC_MAPPING
++# endif
++# if defined IX_OSAL_LE_DC_MAPPING
++#  error Little Endian Data Coherent mapping not supported on this platform
++# endif
++
++/* This doesn't matter on a BE build because it will never be used,
++ * however it will be selected and will fail on an LE build.
++ */
++# undef IX_OSAL_LE_DC
++# define IX_OSAL_LE_DC IX_OSAL_LE_DC_IS_INVALID_ON_THIS_PLATFORM
++#endif
++
++/* Physical addresses. */
++#define IXP425_PERIPHERAL_BASE_PHYS	IXP4XX_PERIPHERAL_BASE_PHYS
++#define IXP425_EXP_CFG_BASE_PHYS	IXP4XX_EXP_CFG_BASE_PHYS
++#define IXP425_PCI_CFG_BASE_PHYS	IXP4XX_PCI_CFG_BASE_PHYS
++
++//#define IXP425_EXP_BUS_BASE1_PHYS
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)
++#define IXP425_EXP_BUS_BASE2_PHYS	IXP4XX_EXP_BUS_CS2_BASE_PHYS
++#else
++/* The following definition should be IXP4XX_EXP_BUS_BASE(2), but that is not
++   static and causes compilation problems later.  So we need to hard-code it.
++   Note that this hard-coded value is only correct for IXP42X. */
++#define IXP425_EXP_BUS_BASE2_PHYS	(IXP4XX_EXP_BUS_BASE_PHYS + (2 * SZ_16M))
++#endif
++//#define IXP425_EXP_BUS_CS0_BASE_PHYS
++//#define IXP425_EXP_BUS_CS1_BASE_PHYS
++//#define IXP425_EXP_BUS_CS4_BASE_PHYS
++#define IXP425_EthA_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
++#define IXP425_EthB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
++//#define IXP425_GPIO_BASE_PHYS
++#define IXP425_INTC_BASE_PHYS		IXP4XX_INTC_BASE_PHYS
++//#define IXP425_NPEA_BASE_PHYS
++//#define IXP425_NPEB_BASE_PHYS
++//#define IXP425_NPEC_BASE_PHYS
++//#define IXP425_PMU_BASE_PHYS
++#define IXP425_QMGR_BASE_PHYS		IXP4XX_QMGR_BASE_PHYS
++#define IXP425_TIMER_BASE_PHYS 		IXP4XX_TIMER_BASE_PHYS
++//#define IXP425_UART1_BASE_PHYS
++//#define IXP425_UART2_BASE_PHYS
++#define IXP425_USB_BASE_PHYS		IXP4XX_USB_BASE_PHYS
++
++/* Virtual addresses. */
++#define IXP425_PERIPHERAL_BASE_VIRT	IXP4XX_PERIPHERAL_BASE_VIRT
++#define IXP425_PERIPHERAL_REGION_SIZE	IXP4XX_PERIPHERAL_REGION_SIZE
++#define IXP425_EXP_CFG_BASE_VIRT	IXP4XX_EXP_CFG_BASE_VIRT
++#define IXP425_PCI_CFG_BASE_VIRT	IXP4XX_PCI_CFG_BASE_VIRT
++
++//#define IXP425_EthA_BASE_VIRT
++//#define IXP425_EthB_BASE_VIRT
++//#define IXP425_GPIO_BASE_VIRT
++//#define IXP425_NPEA_BASE_VIRT
++//#define IXP425_NPEB_BASE_VIRT
++//#define IXP425_NPEC_BASE_VIRT
++//#define IXP425_QMGR_BASE_VIRT	/* must be ioremapped on Linux 2.6 */
++//#define IXP425_TIMER_BASE_VIRT
++//#define IXP425_UART1_BASE_VIRT
++//#define IXP425_UART2_BASE_VIRT
++//#define IXP425_USB_BASE_VIRT
++
++/* Miscellaneous stuff. */
++#define IRQ_IXP425_XSCALE_PMU		IRQ_IXP4XX_XSCALE_PMU
++#define IXP425_ICMR			IXP4XX_ICMR
++#define IRQ_IXP425_USB			IRQ_IXP4XX_USB
++#endif
diff --git a/recipes/ixp4xx/ixp-osal-2.1/le.patch b/recipes/ixp4xx/ixp-osal-2.1/le.patch
new file mode 100644
index 0000000000..a6936ea33b
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal-2.1/le.patch
@@ -0,0 +1,72 @@
+ include/modules/ioMem/IxOsalIoMem.h                                 |    4 ++--
+ include/modules/ioMem/IxOsalMemAccess.h                             |    2 +-
+ os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h |    2 +-
+ os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h        |    2 +-
+ os/linux/src/modules/ioMem/IxOsalOsIoMem.c                          |    3 +++
+ 5 files changed, 8 insertions(+), 5 deletions(-)
+
+--- ixp_osal/include/modules/ioMem/IxOsalIoMem.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/include/modules/ioMem/IxOsalIoMem.h	1970-01-01 00:00:00.000000000 +0000
+@@ -117,8 +117,8 @@ ixOsalCoreWordSwap (UINT32 wordIn)
+ #endif /* ndef __wince */
+ 
+ #define IX_OSAL_SWAP_SHORT(sData)         ((sData >> 8) | ((sData & 0xFF) << 8))
+-#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((sAddr) ^ 0x2)
+-#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)  ((bAddr) ^ 0x3)
++#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((UINT16*)((UINT32)(sAddr) ^ 0x2))
++#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)  ((UINT8*)((UINT32)(bAddr) ^ 0x3))
+ 
+ #define IX_OSAL_BE_XSTOBUSL(wData)  (wData)
+ #define IX_OSAL_BE_XSTOBUSS(sData)  (sData)
+--- ixp_osal/include/modules/ioMem/IxOsalMemAccess.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/include/modules/ioMem/IxOsalMemAccess.h	1970-01-01 00:00:00.000000000 +0000
+@@ -84,7 +84,7 @@
+ 
+ #elif defined (IX_OSAL_LINUX_LE)
+ 
+-#define IX_SDRAM_LE_DATA_COHERENT
++#define IX_SDRAM_LE_ADDRESS_COHERENT
+ 
+ #elif defined (IX_OSAL_WINCE_LE)
+ 
+--- ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h	1970-01-01 00:00:00.000000000 +0000
+@@ -171,7 +171,7 @@
+  ***************************/
+ #if (IX_COMPONENT_NAME == ix_qmgr)
+ 
+-#define IX_OSAL_LE_DC_MAPPING
++#define IX_OSAL_LE_AC_MAPPING
+ 
+ #endif /* qmgr */
+ 
+--- ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h	1970-01-01 00:00:00.000000000 +0000
+@@ -107,7 +107,7 @@ IxOsalMemoryMap ixOsalGlobalMemoryMap[] 
+      ixOsalLinuxMemMap,		/* mapFunction     */
+      ixOsalLinuxMemUnmap,	/* unmapFunction   */
+      0,				/* refCount        */
+-     IX_OSAL_BE | IX_OSAL_LE_DC,	/* endianType      */   
++     IX_OSAL_BE | IX_OSAL_LE_AC,	/* endianType      */
+      "qMgr"			/* name            */
+      },
+ 
+--- ixp_osal/os/linux/src/modules/ioMem/IxOsalOsIoMem.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp_osal/os/linux/src/modules/ioMem/IxOsalOsIoMem.c	1970-01-01 00:00:00.000000000 +0000
+@@ -45,6 +45,7 @@
+  * -- End Intel Copyright Notice --
+  */
+ 
++#include <asm/page.h>
+ #include <asm/io.h>
+ #include <linux/ioport.h>
+ 
+@@ -54,6 +55,8 @@
+ PUBLIC void
+ ixOsalLinuxMemMap (IxOsalMemoryMap * map)
+ {
++    /* Linux requires LE mappings to use address coherency */
++    IX_OSAL_ENSURE((map->mapEndianType & IX_OSAL_LE_DC) == 0, "LE Data Coherency not supported");
+     map->virtualAddress = (UINT32) ioremap (map->physicalAddress, map->size);
+ }
+ 
diff --git a/recipes/ixp4xx/ixp-osal_1.5.bb b/recipes/ixp4xx/ixp-osal_1.5.bb
new file mode 100644
index 0000000000..eac1c1c28d
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal_1.5.bb
@@ -0,0 +1,72 @@
+# Intel ixp4xx access library software.  Note that this has an Intel
+# license which restricts its use.
+HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp420.htm"
+LICENSE = "http://www.intel.com/design/network/swsup/np_sla/ixp400.htm"
+LICENSE_HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp425swr1.htm"
+# You must download the following software to your OpenEmbedded downloads
+# directory before using this package:
+#
+#	ixp400AccessLibrary-1_5.zip
+#
+# To do this go to the LICENSE_HOMEPAGE above, register/login (using a
+# web browser which is supported by the login page), this will give you
+# access to the web page from which you can download the software - you
+# need the: "Intel® IXP400 Software and RedBoot* Boot Loader" and, from
+# this the "Intel Hardware Access Software" (versions 1.5 encryption is
+# not required.)
+#
+# Store the file with the name given below in your downloads directory
+#
+SRC_URI = "http://www.intel.com/Please-Read-The-BB-File/ixp400AccessLibrary-1_5.zip"
+SRC_URI += "file://2.6.patch;patch=1"
+S = "${WORKDIR}/ixp_osal"
+PR = "r1"
+
+COMPATIBLE_HOST = "^armeb-linux.*"
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+inherit module
+
+EXTRA_OEMAKE = "'CC=${KERNEL_CC}' \
+		'LD=${KERNEL_LD}' \
+		'AR=${AR}' \
+		'IX_XSCALE_SW=${S}' \
+		'IX_TARGET=linuxbe' \
+		'IX_MPHY=1' \
+		'IX_MPHYSINGLEPORT=1' \
+		'LINUX_SRC=${STAGING_KERNEL_DIR}' \
+		'LINUX_CROSS_COMPILE=${HOST_PREFIX}' \
+		"
+
+OSAL_PATH = "lib/linux/linuxbe/ixp400"
+# This is a somewhat arbitrary choice:
+OSAL_DIR = "${STAGING_KERNEL_DIR}/ixp_osal"
+
+do_compile () {
+	oe_runmake ${OSAL_PATH}/libosal.a ${OSAL_PATH}/ixp_osal.o
+}
+
+do_stage () {
+	install -d ${OSAL_DIR}
+
+	# First the include files, maintain the tree structure (ixp4xx-csr
+	# expects the exact same tree)
+	cp -RLf include ${OSAL_DIR}
+	install -d ${OSAL_DIR}/os/linux
+	cp -RLf os/linux/include ${OSAL_DIR}/os/linux
+
+	# Install the library/object
+	install -d ${OSAL_DIR}/${OSAL_PATH}
+	rm -f ${OSAL_DIR}/libosal
+	install -m 0644 ${OSAL_PATH}/libosal.a ${OSAL_DIR}/${OSAL_PATH}
+	touch ${OSAL_DIR}/libosal
+	rm -f ${OSAL_DIR}/module
+	install -m 0644 ${OSAL_PATH}/ixp_osal.o ${OSAL_DIR}/${OSAL_PATH}
+	touch ${OSAL_DIR}/module
+}
+
+# This stuff doesn't install anything...
+PACKAGES = ""
+
+do_install () {
+}
diff --git a/recipes/ixp4xx/ixp-osal_2.0.bb b/recipes/ixp4xx/ixp-osal_2.0.bb
new file mode 100644
index 0000000000..009d45d67a
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal_2.0.bb
@@ -0,0 +1,82 @@
+# Intel ixp4xx access library software.  Note that this has an Intel
+# license which restricts its use.
+HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp420.htm"
+LICENSE = "http://www.intel.com/design/network/swsup/np_sla/ixp400.htm"
+LICENSE_HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp425swr1.htm"
+# You must download the following software to your OpenEmbedded downloads
+# directory before using this package:
+#
+#	IPL_ixp400AccessLibrary-2_0.zip
+#
+# To do this go to the LICENSE_HOMEPAGE above, register/login (using a
+# web browser which is supported by the login page), this will give you
+# access to the web page from which you can download the software - you
+# need the: "Intel® IXP400 Software and RedBoot* Boot Loader" and, from
+# this the "Intel Hardware Access Software" (versions 2.0 encryption is
+# not required.)
+#
+# Store the file with the name given below in your downloads directory
+# and store the 32 character md5sum of the file in a file of the same
+# name with the additional extension .md5:
+#
+#	IPL_ixp400AccessLibrary-2_0.zip.md5
+#
+SRC_URI = "http://www.intel.com/Please-Read-The-BB-File/IPL_ixp400AccessLibrary-2_0.zip"
+SRC_URI += "file://Makefile.patch;patch=1"
+SRC_URI += "file://2.6.patch;patch=1"
+SRC_URI += "file://le.patch;patch=1"
+S = "${WORKDIR}/ixp_osal"
+PR = "r4"
+
+COMPATIBLE_HOST = "^arm.*-linux.*"
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+inherit module
+
+IX_TARGET = "linux${SITEINFO_ENDIANESS}"
+
+EXTRA_OEMAKE = "'CC=${KERNEL_CC}' \
+		'LD=${KERNEL_LD}' \
+		'AR=${AR}' \
+		'IX_XSCALE_SW=${S}' \
+		'IX_TARGET=${IX_TARGET}' \
+		'IX_DEVICE=ixp42X' \
+		'LINUX_SRC=${STAGING_KERNEL_DIR}' \
+		'LINUX_CROSS_COMPILE=${HOST_PREFIX}' \
+		"
+
+OSAL_PATH = "lib/ixp425/linux/${IX_TARGET}"
+# This is a somewhat arbitrary choice:
+OSAL_DIR = "${STAGING_KERNEL_DIR}/ixp_osal"
+
+do_compile () {
+	oe_runmake ${OSAL_PATH}/libosal.a ${OSAL_PATH}/ixp_osal.o
+}
+
+do_stage () {
+	# Clean the directory first, this ensures incremental builds have
+	# a slightly better chance of working
+	rm -rf ${OSAL_DIR}
+	install -d ${OSAL_DIR}
+
+	# First the include files, maintain the tree structure (ixp4xx-csr
+	# expects the exact same tree)
+	cp -RLf include ${OSAL_DIR}
+	install -d ${OSAL_DIR}/os/linux
+	cp -RLf os/linux/include ${OSAL_DIR}/os/linux
+
+	# Install the library/object
+	install -d ${OSAL_DIR}/${OSAL_PATH}
+	rm -f ${OSAL_DIR}/libosal
+	install -m 0644 ${OSAL_PATH}/libosal.a ${OSAL_DIR}/${OSAL_PATH}
+	touch ${OSAL_DIR}/libosal
+	rm -f ${OSAL_DIR}/module
+	install -m 0644 ${OSAL_PATH}/ixp_osal.o ${OSAL_DIR}/${OSAL_PATH}
+	touch ${OSAL_DIR}/module
+}
+
+# This stuff doesn't install anything...
+PACKAGES = ""
+
+do_install () {
+}
diff --git a/recipes/ixp4xx/ixp-osal_2.1.1.bb b/recipes/ixp4xx/ixp-osal_2.1.1.bb
new file mode 100644
index 0000000000..481033fd0a
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal_2.1.1.bb
@@ -0,0 +1,101 @@
+DEFAULT_PREFERENCE = "-1"
+# Intel ixp4xx access library software.  Note that this has an Intel
+# license which restricts its use.
+HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp420.htm"
+LICENSE = "http://www.intel.com/design/network/swsup/np_sla/ixp400.htm"
+LICENSE_HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp425swr1.htm"
+# You must download the following software to your OpenEmbedded downloads
+# directory before using this package:
+#
+#	BSD_ixp400AccessLibrary-2_1.zip
+#	BSD_ixp400AccessLibrary-2_1_1.zip
+#
+# To do this go to the LICENSE_HOMEPAGE above, register/login (using a
+# web browser which is supported by the login page), this will give you
+# access to the web page from which you can download the software - you
+# need the: "Intel® IXP400 Software and RedBoot* Boot Loader" and, from
+# this the "Intel Hardware Access Software" (versions 2.1 encryption is
+# not required.)
+#
+# Store the file with the name given below in your downloads directory
+# and store the 32 character md5sum of the file in a file of the same
+# name with the additional extension .md5:
+#
+#	BSD_ixp400AccessLibrary-2_1.zip.md5
+#	BSD_ixp400AccessLibrary-2_1_1.zip.md5
+#
+SRC_URI =  "http://www.intel.com/Please-Read-The-BB-File/BSD_ixp400AccessLibrary-2_1.zip"
+SRC_URI += "http://www.intel.com/Please-Read-The-BB-File/BSD_ixp400AccessLibrary-2_1_1.zip"
+SRC_URI += "file://Makefile.patch;patch=1"
+SRC_URI += "file://2.6.patch;patch=1"
+SRC_URI += "file://invalidate-cache.patch;patch=1"
+SRC_URI += "file://ixp4xx-header.patch;patch=1"
+SRC_URI += "file://le.patch;patch=1"
+SRC_URI += "file://assert.patch;patch=1"
+
+S = "${WORKDIR}/ixp_osal"
+PR = "r0"
+
+COMPATIBLE_HOST = "^arm.*-linux.*"
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+inherit module
+
+do_pre_patch () {
+	( cd ${WORKDIR} ; mkdir patches ; mv BSD_ixp400AccessLibrary-2_1_1.patch patches/ ; \
+	  echo "BSD_ixp400AccessLibrary-2_1_1.patch -p0" >> patches/series ; \
+	  quilt push )
+}
+
+addtask pre_patch before do_patch
+
+IX_TARGET = "linux${SITEINFO_ENDIANESS}"
+IX_ENSURE = ""
+#IX_ENSURE = "IX_OSAL_ENSURE_ON=1"
+
+EXTRA_OEMAKE = "'CC=${KERNEL_CC}' \
+		'LD=${KERNEL_LD}' \
+		'AR=${AR}' \
+		'IX_XSCALE_SW=${S}' \
+		'IX_TARGET=${IX_TARGET}' \
+		'IX_DEVICE=ixp42X' \
+		${IX_ENSURE} \
+		'LINUX_SRC=${STAGING_KERNEL_DIR}' \
+		'LINUX_CROSS_COMPILE=${HOST_PREFIX}' \
+		"
+
+OSAL_PATH = "lib/ixp425/linux/${IX_TARGET}"
+# This is a somewhat arbitrary choice:
+OSAL_DIR = "${STAGING_KERNEL_DIR}/ixp_osal"
+
+do_compile () {
+	oe_runmake ${OSAL_PATH}/libosal.a ${OSAL_PATH}/ixp_osal.o
+}
+
+do_stage () {
+	# Clean the directory first, this ensures incremental builds have
+	# a slightly better chance of working
+	rm -rf ${OSAL_DIR}
+	install -d ${OSAL_DIR}
+
+	# First the include files, maintain the tree structure (ixp4xx-csr
+	# expects the exact same tree)
+	cp -RLf include ${OSAL_DIR}
+	install -d ${OSAL_DIR}/os/linux
+	cp -RLf os/linux/include ${OSAL_DIR}/os/linux
+
+	# Install the library/object
+	install -d ${OSAL_DIR}/${OSAL_PATH}
+	rm -f ${OSAL_DIR}/libosal
+	install -m 0644 ${OSAL_PATH}/libosal.a ${OSAL_DIR}/${OSAL_PATH}
+	touch ${OSAL_DIR}/libosal
+	rm -f ${OSAL_DIR}/module
+	install -m 0644 ${OSAL_PATH}/ixp_osal.o ${OSAL_DIR}/${OSAL_PATH}
+	touch ${OSAL_DIR}/module
+}
+
+# This stuff doesn't install anything...
+PACKAGES = ""
+
+do_install () {
+}
diff --git a/recipes/ixp4xx/ixp-osal_2.1.bb b/recipes/ixp4xx/ixp-osal_2.1.bb
new file mode 100644
index 0000000000..dd70289598
--- /dev/null
+++ b/recipes/ixp4xx/ixp-osal_2.1.bb
@@ -0,0 +1,89 @@
+# Intel ixp4xx access library software.  Note that this has an Intel
+# license which restricts its use.
+HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp420.htm"
+LICENSE = "http://www.intel.com/design/network/swsup/np_sla/ixp400.htm"
+LICENSE_HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp425swr1.htm"
+# You must download the following software to your OpenEmbedded downloads
+# directory before using this package:
+#
+#	IPL_ixp400AccessLibrary-2_1.zip
+#
+# To do this go to the LICENSE_HOMEPAGE above, register/login (using a
+# web browser which is supported by the login page), this will give you
+# access to the web page from which you can download the software - you
+# need the: "Intel® IXP400 Software and RedBoot* Boot Loader" and, from
+# this the "Intel Hardware Access Software" (versions 2.1 encryption is
+# not required.)
+#
+# Store the file with the name given below in your downloads directory
+# and store the 32 character md5sum of the file in a file of the same
+# name with the additional extension .md5:
+#
+#	IPL_ixp400AccessLibrary-2_1.zip.md5
+#
+SRC_URI = "http://www.intel.com/Please-Read-The-BB-File/IPL_ixp400AccessLibrary-2_1.zip"
+SRC_URI += "file://Makefile.patch;patch=1"
+SRC_URI += "file://2.6.patch;patch=1"
+SRC_URI += "file://invalidate-cache.patch;patch=1"
+SRC_URI += "file://ixp4xx-header.patch;patch=1"
+SRC_URI += "file://le.patch;patch=1"
+SRC_URI += "file://assert.patch;patch=1"
+
+S = "${WORKDIR}/ixp_osal"
+PR = "r6"
+
+COMPATIBLE_HOST = "^arm.*-linux.*"
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+inherit module
+
+IX_TARGET = "linux${SITEINFO_ENDIANESS}"
+IX_ENSURE = ""
+#IX_ENSURE = "IX_OSAL_ENSURE_ON=1"
+
+EXTRA_OEMAKE = "'CC=${KERNEL_CC}' \
+		'LD=${KERNEL_LD}' \
+		'AR=${AR}' \
+		'IX_XSCALE_SW=${S}' \
+		'IX_TARGET=${IX_TARGET}' \
+		'IX_DEVICE=ixp42X' \
+		${IX_ENSURE} \
+		'LINUX_SRC=${STAGING_KERNEL_DIR}' \
+		'LINUX_CROSS_COMPILE=${HOST_PREFIX}' \
+		"
+
+OSAL_PATH = "lib/ixp425/linux/${IX_TARGET}"
+# This is a somewhat arbitrary choice:
+OSAL_DIR = "${STAGING_KERNEL_DIR}/ixp_osal"
+
+do_compile () {
+	oe_runmake ${OSAL_PATH}/libosal.a ${OSAL_PATH}/ixp_osal.o
+}
+
+do_stage () {
+	# Clean the directory first, this ensures incremental builds have
+	# a slightly better chance of working
+	rm -rf ${OSAL_DIR}
+	install -d ${OSAL_DIR}
+
+	# First the include files, maintain the tree structure (ixp4xx-csr
+	# expects the exact same tree)
+	cp -RLf include ${OSAL_DIR}
+	install -d ${OSAL_DIR}/os/linux
+	cp -RLf os/linux/include ${OSAL_DIR}/os/linux
+
+	# Install the library/object
+	install -d ${OSAL_DIR}/${OSAL_PATH}
+	rm -f ${OSAL_DIR}/libosal
+	install -m 0644 ${OSAL_PATH}/libosal.a ${OSAL_DIR}/${OSAL_PATH}
+	touch ${OSAL_DIR}/libosal
+	rm -f ${OSAL_DIR}/module
+	install -m 0644 ${OSAL_PATH}/ixp_osal.o ${OSAL_DIR}/${OSAL_PATH}
+	touch ${OSAL_DIR}/module
+}
+
+# This stuff doesn't install anything...
+PACKAGES = ""
+
+do_install () {
+}
diff --git a/recipes/ixp4xx/ixp4xx-csr-1.5/2.6.patch b/recipes/ixp4xx/ixp4xx-csr-1.5/2.6.patch
new file mode 100644
index 0000000000..58c3cbded5
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-1.5/2.6.patch
@@ -0,0 +1,238 @@
+diff -Naur ixp400_xscale_sw.orig/Makefile ixp400_xscale_sw/Makefile
+--- ixp400_xscale_sw.orig/Makefile	2005-08-24 00:16:35.000000000 +0200
++++ ixp400_xscale_sw/Makefile	2005-08-30 19:01:47.000000000 +0200
+@@ -93,15 +93,16 @@
+ # platforms. Components that work only for a subset of platforms
+ # should be added to the relevant *_COMPONENTS lists.
+ #
+-BI_ENDIAN_COMPONENTS := atmdAcc atmm atmsch qmgr npeMh npeDl ethAcc ethDB ethMii hssAcc usb uartAcc featureCtrl ossl osServices
+ 
++# Intel default value: atmdAcc atmm atmsch qmgr npeMh npeDl ethAcc ethDB ethMii hssAcc usb uartAcc featureCtrl ossl osServices
++BI_ENDIAN_COMPONENTS := qmgr npeMh npeDl ethAcc ethDB ethMii ossl osServices featureCtrl
+ 
+ # The lists below contain the set of components available for each target platform
+ vxbe_COMPONENTS := $(BI_ENDIAN_COMPONENTS) perfProfAcc dmaAcc
+ vxle_COMPONENTS := $(BI_ENDIAN_COMPONENTS) perfProfAcc
+ vxsim_COMPONENTS := $(BI_ENDIAN_COMPONENTS) dmaAcc
+-linuxbe_COMPONENTS := $(BI_ENDIAN_COMPONENTS) perfProfAcc dmaAcc 
+-linuxle_COMPONENTS := $(BI_ENDIAN_COMPONENTS) perfProfAcc
++linuxbe_COMPONENTS := $(BI_ENDIAN_COMPONENTS) # perfProfAcc dmaAcc 
++linuxle_COMPONENTS := $(BI_ENDIAN_COMPONENTS) # perfProfAcc
+ 
+ # To facilitate automated builds, do not modify the value of COMPONENTS directly - 
+ # just change the per-platform component lists above.
+@@ -222,10 +223,12 @@
+ else # IX_TARGET_OS == vxworks
+ 
+ # Linux tool names
+-ifeq ($(IX_TARGET), linuxbe)
+-LINUX_CROSS_COMPILE := $(HARDHAT_BASE)/devkit/arm/xscale_be/bin/xscale_be-
+-else
+-LINUX_CROSS_COMPILE := $(HARDHAT_BASE)/devkit/arm/xscale_le/bin/xscale_le-
++ifeq "$(LINUX_CROSS_COMPILE)" "" 
++ ifeq ($(IX_TARGET), linuxbe)
++  LINUX_CROSS_COMPILE := $(HARDHAT_BASE)/devkit/arm/xscale_be/bin/xscale_be-
++ else
++  LINUX_CROSS_COMPILE := $(HARDHAT_BASE)/devkit/arm/xscale_le/bin/xscale_le-
++ endif
+ endif
+ 
+ LD := $(LINUX_CROSS_COMPILE)ld
+@@ -253,7 +256,9 @@
+ 
+ LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mcpu=xscale -mtune=xscale
+ 
+-CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common -pipe -mapcs-32 -mshort-load-bytes -msoft-float -DMODULE -Isrc/include -I$(NPE_OUTPUT_DIR) -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS)
++CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common -pipe -mapcs-32 -msoft-float -DMODULE -Isrc/include -I$(NPE_OUTPUT_DIR) -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS)
++
++# -mshort-load-bytes removed by Marc Singer's patch TODO(hannes) why?
+ 
+ # Linux linker flags
+ LDFLAGS := -r
+@@ -1139,9 +1144,14 @@
+ 
+ ixp400.o : $(OBJ_DIR)/ixp400.o
+ 
++ixp400.ko : $(OBJ_DIR)/ixp400.o
+ 
+-$(OBJ_DIR)/ixp400.o: $(COMPONENTS:%=$(OBJ_DIR)/ixp400_%.o) $(NPE_PRODUCTION_HEADER_OBJ) $(OSAL_MODULE)
++$(OBJ_DIR)/ixp400.o: $(COMPONENTS:%=$(OBJ_DIR)/ixp400_%.o) $(NPE_PRODUCTION_HEADER_OBJ) $(OSAL_MODULE) # add this to hack in the ethAcc codelet: $(OBJ_DIR)/ixp400_codelets_ethAcc.o
++	touch $(OBJ_DIR)/ixp400.c
++	cp Makefile.kmod26 $(OBJ_DIR)/Makefile
++	make -C $(OBJ_DIR)
+ 	$(LD) $(LDFLAGS) $^ -o $@
++	make -C $(OBJ_DIR)
+ 
+ 
+ 
+diff -Naur ixp400_xscale_sw.orig/Makefile.kmod26 ixp400_xscale_sw/Makefile.kmod26
+--- ixp400_xscale_sw.orig/Makefile.kmod26	1970-01-01 01:00:00.000000000 +0100
++++ ixp400_xscale_sw/Makefile.kmod26	2005-08-24 22:33:12.000000000 +0200
+@@ -0,0 +1,11 @@
++obj-m := ixp400.o
++
++PWD         := $(shell pwd)
++
++LINUX_SRC := $($(IX_TARGET)_KERNEL_DIR)
++
++default:
++	$(MAKE) ARCH=arm CROSS_COMPILE=$(LINUX_CROSS_COMPILE) V=1 -C $(LINUX_SRC) SUBDIRS=$(PWD) modules
++
++clean:
++	rm -f ixp400.ko
+diff -Naur ixp400_xscale_sw.orig/Readme-Kernel-2_6-Patch.txt ixp400_xscale_sw/Readme-Kernel-2_6-Patch.txt
+--- ixp400_xscale_sw.orig/Readme-Kernel-2_6-Patch.txt	1970-01-01 01:00:00.000000000 +0100
++++ ixp400_xscale_sw/Readme-Kernel-2_6-Patch.txt	2005-09-28 19:50:30.000000000 +0200
+@@ -0,0 +1,49 @@
++This file describes a patch to use version 1.5 of the Intel Ixp4XX
++Access Library with Linux 2.6 kernels.
++
++Authors/History
++---------------
++
++This patch consists of the changes made by Marc Singer for use of
++version 1.5 of the library with the APEX bootloader, and a patch made
++by Robin Farine and Tom Winkler for use of version 1.4 of the library
++with Linux-2.6 kernels. These changes were merged together by Hannes
++Reich.
++
++Both patches are incorporated in their entirety, with the exception of
++some tweaks to sleep times in the ethAcc code and modifications to
++the code in src/codelets/usb/ from the Robin Farine / Tom Winkler
++patch.
++
++Status
++------
++
++This code has been tested on a Linksys NSLU2. It works in big-endian
++mode, performance seems around 10% faster than 1.4.
++
++The code does not work in little-endian mode. It appears as though the
++hardware is initialised correctly, but packet receive / transmit done
++callbacks are never called.
++
++Licence Information
++-------------------
++
++The patch is licenced under the same conditions as the original Access
++Library 1.5 (INTEL SOFTWARE LICENSE AGREEMENT). The full text of the
++licence can be downloaded from:
++http://www.intel.com/design/network/swsup/np_sla/ixp400.htm
++
++The patch is free, unsupported and the authors make no warranties.
++Use it at your own risk, do with it as you see fit so long as you do
++not violate the original licence agreement.
++
++The authors permit derivative works based upon the patch.
++
++References
++----------
++
++The version 1.4 patch by Robin Farine and Tom Winkler is available from
++http://www.wnk.at/ixp400_accesslib_kernel26/data/patch_accesslib_kernel26_20040811.diff
++
++The version 1.5 patch by Marc Singer is at
++http://wiki.buici.com/bin/view/Main/IXPAccessLibrary
+diff -Naur ixp400_xscale_sw.orig/src/codelets/dmaAcc/IxDmaAccCodelet_p.h ixp400_xscale_sw/src/codelets/dmaAcc/IxDmaAccCodelet_p.h
+--- ixp400_xscale_sw.orig/src/codelets/dmaAcc/IxDmaAccCodelet_p.h	2005-08-24 00:16:36.000000000 +0200
++++ ixp400_xscale_sw/src/codelets/dmaAcc/IxDmaAccCodelet_p.h	2005-08-24 00:18:02.000000000 +0200
+@@ -113,7 +113,7 @@
+  * @return IX_FAIL - Error initialising codelet
+  */
+ IX_STATUS
+-ixDmaAccCodeletInit(IxDmaNpeId npeId);
++ixDmaAccCodeletInit(IxNpeDlNpeId npeId);
+ 
+ /**
+  * @fn ixDmaAccCodeletTestPerform( UINT16 transferLength, 
+diff -Naur ixp400_xscale_sw.orig/src/ethDB/include/IxEthDB_p.h ixp400_xscale_sw/src/ethDB/include/IxEthDB_p.h
+--- ixp400_xscale_sw.orig/src/ethDB/include/IxEthDB_p.h	2005-08-24 00:16:36.000000000 +0200
++++ ixp400_xscale_sw/src/ethDB/include/IxEthDB_p.h	2005-08-24 00:18:02.000000000 +0200
+@@ -633,7 +633,7 @@
+ IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress);
+ 
+ /* Port updates */
+-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBFeature type);
++IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type);
+ IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts);
+ IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID);
+ IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void);
+diff -Naur ixp400_xscale_sw.orig/src/include/IxTypes.h ixp400_xscale_sw/src/include/IxTypes.h
+--- ixp400_xscale_sw.orig/src/include/IxTypes.h	2005-08-24 00:16:36.000000000 +0200
++++ ixp400_xscale_sw/src/include/IxTypes.h	2005-08-26 01:19:15.000000000 +0200
+@@ -79,6 +79,10 @@
+ #endif
+ #endif
+ 
++#ifndef BIT
++#define BIT(x)  ((1)<<(x))
++#endif
++
+ #include "IxOsalBackward.h"
+ 
+ #endif /* IxTypes_H */
+diff -Naur ixp400_xscale_sw.orig/src/usb/include/usbprivatetypes.h ixp400_xscale_sw/src/usb/include/usbprivatetypes.h
+--- ixp400_xscale_sw.orig/src/usb/include/usbprivatetypes.h	2005-08-24 00:16:36.000000000 +0200
++++ ixp400_xscale_sw/src/usb/include/usbprivatetypes.h	2005-08-24 00:18:02.000000000 +0200
+@@ -164,6 +164,53 @@
+ } USBEventProcessor;
+ 
+ /*  UDC Registers */
++
++#undef UDCCR
++#undef UDCCS0
++#undef UDCCS1
++#undef UDCCS2
++#undef UDCCS3
++#undef UDCCS4
++#undef UDCCS5
++#undef UDCCS6
++#undef UDCCS7
++#undef UDCCS8
++#undef UDCCS9
++#undef UDCCS10
++#undef UDCCS11
++#undef UDCCS12
++#undef UDCCS13
++#undef UDCCS14
++#undef UDCCS15
++#undef UICR0
++#undef UICR1
++#undef USIR0
++#undef USIR1
++#undef UFNHR
++#undef UFNLR
++#undef UBCR2
++#undef UBCR4
++#undef UBCR7
++#undef UBCR9
++#undef UBCR12
++#undef UBCR14
++#undef UDDR0
++#undef UDDR5
++#undef UDDR10
++#undef UDDR15
++#undef UDDR1
++#undef UDDR2
++#undef UDDR3
++#undef UDDR4
++#undef UDDR6
++#undef UDDR7
++#undef UDDR8
++#undef UDDR9
++#undef UDDR11
++#undef UDDR12
++#undef UDDR13
++#undef UDDR14
++
+ typedef struct  /* UDCRegisters */
+ {
+     volatile UINT32 UDCCR;
+@@ -229,6 +276,7 @@
+     volatile UINT32	UDDR14;			
+ } UDCRegisters;
+ 
++
+ typedef struct /* USBDeviceContext */
+ {
+     UINT32 checkPattern;                      /* Check pattern for verifying the context */
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.0/2.6.14.patch b/recipes/ixp4xx/ixp4xx-csr-2.0/2.6.14.patch
new file mode 100644
index 0000000000..9630e6cd4a
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.0/2.6.14.patch
@@ -0,0 +1,20 @@
+# Additional patches for v2.0 on 2.6.14
+--- ixp400_xscale_sw/src/oslinux/IxLinuxInit.c.orig	2005-10-01 18:21:34.731233399 -0700
++++ ixp400_xscale_sw/src/oslinux/IxLinuxInit.c	2005-10-01 18:21:45.811930663 -0700
+@@ -160,7 +160,6 @@
+ 	return -EEXIST;
+     }
+ 
+-    MOD_INC_USE_COUNT;   /* Increment use count to prevent premature rmmod-ing */
+     ixNpeDlSegmentedListHead = NULL;  /* Reset linked list which keeps track of Microcode fragments */
+     ixNpeDlSegmentedListTail = NULL;
+     ixNpeDlTotalBytesReadIn = 0;
+@@ -225,8 +224,6 @@
+ 	kfree (temp);
+     }
+ 
+-    MOD_DEC_USE_COUNT;
+-
+     return 0;
+ }
+ 
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.0/2.6.patch b/recipes/ixp4xx/ixp4xx-csr-2.0/2.6.patch
new file mode 100644
index 0000000000..37d390bf71
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.0/2.6.patch
@@ -0,0 +1,148 @@
+diff -Naur ixp400_xscale_sw.orig/Readme-Kernel-2_6-Patch.txt ixp400_xscale_sw/Readme-Kernel-2_6-Patch.txt
+--- ixp400_xscale_sw.orig/Readme-Kernel-2_6-Patch.txt	1970-01-01 01:00:00.000000000 +0100
++++ ixp400_xscale_sw/Readme-Kernel-2_6-Patch.txt	2005-09-28 19:50:30.000000000 +0200
+@@ -0,0 +1,49 @@
++This file describes a patch to use version 1.5 of the Intel Ixp4XX
++Access Library with Linux 2.6 kernels.
++
++Authors/History
++---------------
++
++This patch consists of the changes made by Marc Singer for use of
++version 1.5 of the library with the APEX bootloader, and a patch made
++by Robin Farine and Tom Winkler for use of version 1.4 of the library
++with Linux-2.6 kernels. These changes were merged together by Hannes
++Reich.
++
++Both patches are incorporated in their entirety, with the exception of
++some tweaks to sleep times in the ethAcc code and modifications to
++the code in src/codelets/usb/ from the Robin Farine / Tom Winkler
++patch.
++
++Status
++------
++
++This code has been tested on a Linksys NSLU2. It works in big-endian
++mode, performance seems around 10% faster than 1.4.
++
++The code does not work in little-endian mode. It appears as though the
++hardware is initialised correctly, but packet receive / transmit done
++callbacks are never called.
++
++Licence Information
++-------------------
++
++The patch is licenced under the same conditions as the original Access
++Library 1.5 (INTEL SOFTWARE LICENSE AGREEMENT). The full text of the
++licence can be downloaded from:
++http://www.intel.com/design/network/swsup/np_sla/ixp400.htm
++
++The patch is free, unsupported and the authors make no warranties.
++Use it at your own risk, do with it as you see fit so long as you do
++not violate the original licence agreement.
++
++The authors permit derivative works based upon the patch.
++
++References
++----------
++
++The version 1.4 patch by Robin Farine and Tom Winkler is available from
++http://www.wnk.at/ixp400_accesslib_kernel26/data/patch_accesslib_kernel26_20040811.diff
++
++The version 1.5 patch by Marc Singer is at
++http://wiki.buici.com/bin/view/Main/IXPAccessLibrary
+diff -Naur ixp400_xscale_sw.orig/src/codelets/dmaAcc/IxDmaAccCodelet_p.h ixp400_xscale_sw/src/codelets/dmaAcc/IxDmaAccCodelet_p.h
+--- ixp400_xscale_sw.orig/src/codelets/dmaAcc/IxDmaAccCodelet_p.h	2005-08-24 00:16:36.000000000 +0200
++++ ixp400_xscale_sw/src/codelets/dmaAcc/IxDmaAccCodelet_p.h	2005-08-24 00:18:02.000000000 +0200
+@@ -113,7 +113,7 @@
+  * @return IX_FAIL - Error initialising codelet
+  */
+ IX_STATUS
+-ixDmaAccCodeletInit(IxDmaNpeId npeId);
++ixDmaAccCodeletInit(IxNpeDlNpeId npeId);
+ 
+ /**
+  * @fn ixDmaAccCodeletTestPerform( UINT16 transferLength, 
+diff -Naur ixp400_xscale_sw.orig/src/ethDB/include/IxEthDB_p.h ixp400_xscale_sw/src/ethDB/include/IxEthDB_p.h
+--- ixp400_xscale_sw.orig/src/ethDB/include/IxEthDB_p.h	2005-08-24 00:16:36.000000000 +0200
++++ ixp400_xscale_sw/src/ethDB/include/IxEthDB_p.h	2005-08-24 00:18:02.000000000 +0200
+@@ -633,7 +633,7 @@
+ IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress);
+ 
+ /* Port updates */
+-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBFeature type);
++IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type);
+ IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts);
+ IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID);
+ IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void);
+diff -Naur ixp400_xscale_sw.orig/src/include/IxTypes.h ixp400_xscale_sw/src/include/IxTypes.h
+--- ixp400_xscale_sw.orig/src/include/IxTypes.h	2005-08-24 00:16:36.000000000 +0200
++++ ixp400_xscale_sw/src/include/IxTypes.h	2005-08-26 01:19:15.000000000 +0200
+@@ -79,6 +79,10 @@
+ #endif
+ #endif
+ 
++#ifndef BIT
++#define BIT(x)  ((1)<<(x))
++#endif
++
+ #include "IxOsalBackward.h"
+ 
+ #endif /* IxTypes_H */
+diff -Naur ixp400_xscale_sw.orig/src/usb/include/usbprivatetypes.h ixp400_xscale_sw/src/usb/include/usbprivatetypes.h
+--- ixp400_xscale_sw.orig/src/usb/include/usbprivatetypes.h	2005-08-24 00:16:36.000000000 +0200
++++ ixp400_xscale_sw/src/usb/include/usbprivatetypes.h	2005-08-24 00:18:02.000000000 +0200
+@@ -164,6 +164,53 @@
+ } USBEventProcessor;
+ 
+ /*  UDC Registers */
++
++#undef UDCCR
++#undef UDCCS0
++#undef UDCCS1
++#undef UDCCS2
++#undef UDCCS3
++#undef UDCCS4
++#undef UDCCS5
++#undef UDCCS6
++#undef UDCCS7
++#undef UDCCS8
++#undef UDCCS9
++#undef UDCCS10
++#undef UDCCS11
++#undef UDCCS12
++#undef UDCCS13
++#undef UDCCS14
++#undef UDCCS15
++#undef UICR0
++#undef UICR1
++#undef USIR0
++#undef USIR1
++#undef UFNHR
++#undef UFNLR
++#undef UBCR2
++#undef UBCR4
++#undef UBCR7
++#undef UBCR9
++#undef UBCR12
++#undef UBCR14
++#undef UDDR0
++#undef UDDR5
++#undef UDDR10
++#undef UDDR15
++#undef UDDR1
++#undef UDDR2
++#undef UDDR3
++#undef UDDR4
++#undef UDDR6
++#undef UDDR7
++#undef UDDR8
++#undef UDDR9
++#undef UDDR11
++#undef UDDR12
++#undef UDDR13
++#undef UDDR14
++
+ typedef struct  /* UDCRegisters */
+ {
+     volatile UINT32 UDCCR;
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.0/Makefile.patch b/recipes/ixp4xx/ixp4xx-csr-2.0/Makefile.patch
new file mode 100644
index 0000000000..c5a907e1f1
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.0/Makefile.patch
@@ -0,0 +1,61 @@
+diff -Naur ixp400_xscale_sw.orig/Makefile ixp400_xscale_sw/Makefile
+--- ixp400_xscale_sw/.pc/Makefile.patch/Makefile	2005-04-17 20:54:58.000000000 -0700
++++ ixp400_xscale_sw/Makefile	2005-10-01 18:15:08.422924549 -0700
+@@ -312,9 +312,9 @@
+ else
+ # linux compiler flags 
+ 
+-LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mcpu=xscale -mtune=xscale
++LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mtune=xscale
+ 
+-CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common -pipe -mapcs-32 -mshort-load-bytes -msoft-float -DMODULE -Isrc/include -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS)
++CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common -pipe -mapcs-32 -msoft-float -DMODULE -Isrc/include -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS)
+ ifndef IX_INCLUDE_MICROCODE
+ CFLAGS += -DIX_NPEDL_READ_MICROCODE_FROM_FILE
+ endif
+@@ -806,9 +806,11 @@
+ 
+ ifeq ($(IX_HOST_OS),linux)
+ ifndef IX_INCLUDE_MICROCODE
++ifdef IX_BUILD_MICROCODE
+ Makefile: $(NPE_CONVERTER) $(NPE_DAT)
+ endif
+ endif
++endif
+ 
+ ################################################################
+ # Rules to check that macros are defined.
+@@ -1253,10 +1255,18 @@
+ 
+ ifndef IX_INCLUDE_MICROCODE
+ $(OBJ_DIR)/ixp400.o: $(COMPONENTS:%=$(OBJ_DIR)/ixp400_%.o) $(OSAL_MODULE)
++	touch $(OBJ_DIR)/ixp400.c
++	cp Makefile.kmod26 $(OBJ_DIR)/Makefile
++	make -C $(OBJ_DIR)
+ 	$(LD) $(LDFLAGS) $^ -o $@
++	make -C $(OBJ_DIR)
+ else
+ $(OBJ_DIR)/ixp400.o: $(COMPONENTS:%=$(OBJ_DIR)/ixp400_%.o) $(NPE_PRODUCTION_HEADER_OBJ) $(OSAL_MODULE)
++	touch $(OBJ_DIR)/ixp400.c
++	cp Makefile.kmod26 $(OBJ_DIR)/Makefile
++	make -C $(OBJ_DIR)
+ 	$(LD) $(LDFLAGS) $^ -o $@
++	make -C $(OBJ_DIR)
+ endif
+ 
+ 
+diff -Naur ixp400_xscale_sw.orig/Makefile.kmod26 ixp400_xscale_sw/Makefile.kmod26
+--- ixp400_xscale_sw.orig/Makefile.kmod26	1970-01-01 01:00:00.000000000 +0100
++++ ixp400_xscale_sw/Makefile.kmod26	2005-08-24 22:33:12.000000000 +0200
+@@ -0,0 +1,11 @@
++obj-m := ixp400.o
++
++PWD         := $(shell pwd)
++
++LINUX_SRC := $($(IX_TARGET)_KERNEL_DIR)
++
++default:
++	$(MAKE) ARCH=arm CROSS_COMPILE=$(LINUX_CROSS_COMPILE) V=1 -C $(LINUX_SRC) SUBDIRS=$(PWD) modules
++
++clean:
++	rm -f ixp400.ko
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.0/le.patch b/recipes/ixp4xx/ixp4xx-csr-2.0/le.patch
new file mode 100644
index 0000000000..e32b795755
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.0/le.patch
@@ -0,0 +1,24 @@
+--- ixp400_xscale_sw/.pc/le.patch/src/include/IxQMgr.h	2005-04-17 20:55:31.000000000 -0700
++++ ixp400_xscale_sw/src/include/IxQMgr.h	2005-11-19 16:01:52.817556623 -0800
+@@ -87,7 +87,9 @@
+ /* 
+  * Define QMgr's IoMem macros, in DC mode if in LE 
+  * regular if in BE. (Note: For Linux LSP gold release
+- * may need to adjust mode.
++ * may need to adjust mode.  For standard Linux kernels
++ * data coherent access is not used, therefore address
++ * coherency must be set.
+  */
+ #if defined (__BIG_ENDIAN)
+ 
+@@ -96,8 +98,8 @@
+ 
+ #else
+ 
+-#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_DC
+-#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_DC
++#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_AC
++#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_AC
+ 
+ #endif
+ 
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/Makefile.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/Makefile.patch
new file mode 100644
index 0000000000..f082b713f0
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/Makefile.patch
@@ -0,0 +1,26 @@
+--- ixp400_xscale_sw/Makefile	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/Makefile	1970-01-01 00:00:00.000000000 +0000
+@@ -297,9 +297,9 @@ endif
+ else # IX_TARGET_OS == vxworks
+ # linux compiler flags 
+ MAKE_DEP_FLAG := -M
+-LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mcpu=xscale -mtune=xscale
++LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mtune=xscale
+ 
+-CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common -pipe -mapcs-32 -mshort-load-bytes -msoft-float -DMODULE -Isrc/include -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS)
++CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common -pipe -msoft-float -DMODULE -Isrc/include -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS)
+ ifndef IX_INCLUDE_MICROCODE
+ CFLAGS += -DIX_NPEDL_READ_MICROCODE_FROM_FILE
+ endif
+@@ -867,9 +867,11 @@ $(NPE_DAT) : $(NPE_CONVERTER)
+ 
+ ifeq ($(IX_HOST_OS),linux)
+ ifndef IX_INCLUDE_MICROCODE
++ifdef IX_BUILD_MICROCODE
+ Makefile: $(NPE_CONVERTER) $(NPE_DAT)
+ endif
+ endif
++endif
+ 
+ ################################################################
+ # Rules to check that macros are defined.
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/bit-macro.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/bit-macro.patch
new file mode 100644
index 0000000000..6efdba5c1e
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/bit-macro.patch
@@ -0,0 +1,14 @@
+--- ixp400_xscale_sw/src/include/IxTypes.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/include/IxTypes.h	1970-01-01 00:00:00.000000000 +0000
+@@ -79,6 +79,10 @@
+ #endif
+ #endif
+ 
++#ifndef BIT
++#define BIT(x)  ((1)<<(x))
++#endif
++
+ #include "IxOsalBackward.h"
+ 
+ #endif /* IxTypes_H */
+
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/gcc4.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/gcc4.patch
new file mode 100644
index 0000000000..a701328dd1
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/gcc4.patch
@@ -0,0 +1,23 @@
+--- ixp400/src/npeMh/IxNpeMhSymbols.c~	2006-01-08 03:13:28.000000000 +1030
++++ ixp400/src/npeMh/IxNpeMhSymbols.c	2006-01-09 00:56:57.000000000 +1030
+@@ -52,6 +52,7 @@
+ 
+ #include <linux/module.h>
+ #include <IxNpeMh.h>
++#include <IxNpeMhConfig_p.h>
+ 
+ EXPORT_SYMBOL(ixNpeMhInitialize);
+ EXPORT_SYMBOL(ixNpeMhUnload);
+@@ -67,9 +68,9 @@ extern BOOL ixNpeMhConfigInFifoIsFull(Ix
+ extern BOOL ixNpeMhConfigOutFifoIsEmpty (IxNpeMhNpeId npeId);
+ extern void ixNpeMhConfigLockRelease (IxNpeMhNpeId npeId);
+ extern void ixNpeMhConfigLockGet (IxNpeMhNpeId npeId);
+-extern void ixNpeMhConfigOutFifoRead (IxNpeMhNpeId npeId,IxNpeMhMessage *message);
+-extern void ixNpeMhConfigInFifoWrite (IxNpeMhNpeId npeId,IxNpeMhMessage message);
+-extern struct ixNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];
++extern IX_STATUS ixNpeMhConfigOutFifoRead (IxNpeMhNpeId npeId,IxNpeMhMessage *message);
++extern IX_STATUS ixNpeMhConfigInFifoWrite (IxNpeMhNpeId npeId,IxNpeMhMessage message);
++extern IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];
+ 
+ EXPORT_SYMBOL(ixNpeMhConfigInFifoIsFull);
+ EXPORT_SYMBOL(ixNpeMhConfigOutFifoIsEmpty);
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/ixethdb-header.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/ixethdb-header.patch
new file mode 100644
index 0000000000..8ab22bee89
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/ixethdb-header.patch
@@ -0,0 +1,11 @@
+--- ixp400_xscale_sw/src/ethDB/include/IxEthDB_p.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/ethDB/include/IxEthDB_p.h	1970-01-01 00:00:00.000000000 +0000
+@@ -693,7 +693,7 @@ IX_ETH_DB_PUBLIC UINT32 ixEthDBEntryXORH
+ IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress);
+ 
+ /* Port updates */
+-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBFeature type);
++IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type);
+ IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts);
+ IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID);
+ IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void);
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/ixnpemhconfigisr-is-private.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/ixnpemhconfigisr-is-private.patch
new file mode 100644
index 0000000000..54faadf34a
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/ixnpemhconfigisr-is-private.patch
@@ -0,0 +1,18 @@
+--- ixp400_xscale_sw/src/npeMh/IxNpeMhSymbols.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/npeMh/IxNpeMhSymbols.c	1970-01-01 00:00:00.000000000 +0000
+@@ -63,7 +63,6 @@ EXPORT_SYMBOL(ixNpeMhMessagesReceive);
+ EXPORT_SYMBOL(ixNpeMhShow);
+ EXPORT_SYMBOL(ixNpeMhShowReset);
+ 
+-extern void ixNpeMhConfigIsr (void *parameter);
+ extern BOOL ixNpeMhConfigInFifoIsFull(IxNpeMhNpeId npeId);
+ extern BOOL ixNpeMhConfigOutFifoIsEmpty (IxNpeMhNpeId npeId);
+ extern void ixNpeMhConfigLockRelease (IxNpeMhNpeId npeId);
+@@ -72,7 +71,6 @@ extern void ixNpeMhConfigOutFifoRead (Ix
+ extern void ixNpeMhConfigInFifoWrite (IxNpeMhNpeId npeId,IxNpeMhMessage message);
+ extern struct ixNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];
+ 
+-EXPORT_SYMBOL(ixNpeMhConfigIsr);
+ EXPORT_SYMBOL(ixNpeMhConfigInFifoIsFull);
+ EXPORT_SYMBOL(ixNpeMhConfigOutFifoIsEmpty);
+ EXPORT_SYMBOL(ixNpeMhConfigLockRelease);
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/le.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/le.patch
new file mode 100644
index 0000000000..c308493a08
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/le.patch
@@ -0,0 +1,13 @@
+--- ixp400_xscale_sw/src/include/IxQMgr.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/include/IxQMgr.h	1970-01-01 00:00:00.000000000 +0000
+@@ -96,8 +98,8 @@
+ 
+ #else
+ 
+-#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_DC
+-#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_DC
++#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_AC
++#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_AC
+ 
+ #endif
+ 
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/livelock.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/livelock.patch
new file mode 100644
index 0000000000..0b4e4ba026
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/livelock.patch
@@ -0,0 +1,19 @@
+*** ixp400_xscale_sw/src/oslinux/IxLinuxInit.c.orig	Sun Sep 25 05:59:03 2005
+--- ixp400_xscale_sw/src/oslinux/IxLinuxInit.c	Fri Jun  9 14:07:06 2006
+***************
+*** 91,97 ****
+  
+  
+  /* Module parameters */
+! static int livelock_dispatcher = 0;/* default: don't use livelock dispatcher*/
+  
+  MODULE_PARM(livelock_dispatcher, "i");
+  MODULE_PARM_DESC(livelock_dispatcher, "If non-zero, use the livelock prevention qmgr dispatcher");
+--- 91,97 ----
+  
+  
+  /* Module parameters */
+! int livelock_dispatcher = 0;/* default: don't use livelock dispatcher*/
+  
+  MODULE_PARM(livelock_dispatcher, "i");
+  MODULE_PARM_DESC(livelock_dispatcher, "If non-zero, use the livelock prevention qmgr dispatcher");
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/mii-debug.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/mii-debug.patch
new file mode 100644
index 0000000000..762743cef5
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/mii-debug.patch
@@ -0,0 +1,26 @@
+debug only patch to add information about MII id problems
+
+--- ixp400_xscale_sw/src/ethMii/IxEthMii.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/ethMii/IxEthMii.c	1970-01-01 00:00:00.000000000 +0000
+@@ -122,6 +122,10 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT3
+ 		    )
+ 		{
+ 		    /* supported phy */
++                    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
++                               IX_OSAL_LOG_DEV_STDOUT,
++				"ixEthMiiPhyScan, Mii %d: Mii PHY ID %8.8x\n", 
++				i, ixEthMiiPhyId[i], 3, 4, 5, 6);
+ 		    phyPresent[i] = TRUE;
+ 		} /* end of if(ixEthMiiPhyId) */
+ 		else
+@@ -131,8 +135,8 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT3
+ 			/* unsupported phy */
+                         ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
+                                    IX_OSAL_LOG_DEV_STDOUT,
+-				    "ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n", 
+-				    ixEthMiiPhyId[i], 2, 3, 4, 5, 6);
++				    "ixEthMiiPhyScan, Mii %d: unexpected Mii PHY ID %8.8x\n", 
++				    i, ixEthMiiPhyId[i], 3, 4, 5, 6);
+ 			ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID;
+ 			phyPresent[i] = TRUE;
+ 		    }
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/module-param.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/module-param.patch
new file mode 100644
index 0000000000..6472ef8b05
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/module-param.patch
@@ -0,0 +1,19 @@
+ src/oslinux/IxLinuxInit.c |    4 ++++
+ 1 files changed, 4 insertions(+)
+
+Index: ixp400_xscale_sw/src/oslinux/IxLinuxInit.c
+===================================================================
+--- ixp400_xscale_sw.orig/src/oslinux/IxLinuxInit.c
++++ ixp400_xscale_sw/src/oslinux/IxLinuxInit.c
+@@ -103,7 +103,11 @@
+ #if KERNEL_VERSION(2,6,0) <= LINUX_VERSION_CODE
+ MODULE_VERSION("2.1.1");
+ #endif
++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,16)
+ MODULE_PARM(livelock_dispatcher, "i");
++#else
++module_param(livelock_dispatcher, int, 0644);
++#endif
+ MODULE_PARM_DESC(livelock_dispatcher, "If non-zero, use the livelock prevention qmgr dispatcher");
+ 
+ /* Init and cleanup functions for module */
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/module-use-count.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/module-use-count.patch
new file mode 100644
index 0000000000..0fc2c5270e
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/module-use-count.patch
@@ -0,0 +1,24 @@
+ src/oslinux/IxLinuxInit.c |    3 ---
+ 1 files changed, 3 deletions(-)
+
+Index: ixp400_xscale_sw/src/oslinux/IxLinuxInit.c
+===================================================================
+--- ixp400_xscale_sw.orig/src/oslinux/IxLinuxInit.c
++++ ixp400_xscale_sw/src/oslinux/IxLinuxInit.c
+@@ -164,7 +164,6 @@
+ 	return -EEXIST;
+     }
+ 
+-    MOD_INC_USE_COUNT;   /* Increment use count to prevent premature rmmod-ing */
+     ixNpeDlSegmentedListHead = NULL;  /* Reset linked list which keeps track of Microcode fragments */
+     ixNpeDlSegmentedListTail = NULL;
+     ixNpeDlTotalBytesReadIn = 0;
+@@ -229,8 +228,6 @@
+ 	kfree (temp);
+     }
+ 
+-    MOD_DEC_USE_COUNT;
+-
+     return 0;
+ }
+ 
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/oe-makefile.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/oe-makefile.patch
new file mode 100644
index 0000000000..9f1d253a93
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/oe-makefile.patch
@@ -0,0 +1,61 @@
+changes to Makefile required only on OE
+
+ Makefile        |   11 ++++++++++-
+ Makefile.kmod26 |   11 +++++++++++
+ ixp400.c        |    1 +
+ 3 files changed, 22 insertions(+), 1 deletion(-)
+
+Index: ixp400_xscale_sw/Makefile
+===================================================================
+--- ixp400_xscale_sw.orig/Makefile
++++ ixp400_xscale_sw/Makefile
+@@ -1385,9 +1385,10 @@
+ 
+ ifeq ($(IX_LINUXVER),2.6)
+ ixp400 : $(OBJ_DIR)/ixp400.o
++	cp $(OSAL_MODULE) $(OBJ_DIR)
+ 	@echo 'EXTRA_LDFLAGS := --whole-archive' > $(OBJ_DIR)/Makefile
+ 	@echo ' ' >> $(OBJ_DIR)/Makefile
+-	@echo 'lib-m := $(COMPONENTS:%=ixp400_%.o) $(OBJ_DIR_EXIT)/$(OSAL_MODULE)'>> $(OBJ_DIR)/Makefile
++	@echo 'lib-m := $(COMPONENTS:%=ixp400_%.o) ixp_osal.o'>> $(OBJ_DIR)/Makefile
+ 	@echo ' ' >> $(OBJ_DIR)/Makefile
+ 	@echo 'obj-m := ixp400.o' >> $(OBJ_DIR)/Makefile
+ 	@echo ' ' >> $(OBJ_DIR)/Makefile
+@@ -1403,7 +1404,15 @@
+ 
+ $(OBJ_DIR)/ixp400.o: $(COMPONENTS:%=$(OBJ_DIR)/ixp400_%.o) $(OSAL_MODULE)
+ ifneq ($(IX_LINUXVER),2.6)
++	rm -f $(OBJ_DIR)/ixp400.c
++	touch $(OBJ_DIR)/ixp400.c
++	cp Makefile.kmod26 $(OBJ_DIR)/Makefile
++	make -C $(OBJ_DIR)
++	rm -f $(OBJ_DIR)/ixp400.c
++	cp ixp400.c $(OBJ_DIR)/ixp400.c
+ 	$(LD) $(LDFLAGS) $^ -o $@
++	rm -f $(OBJ_DIR)/ixp400.ko $(OBJ_DIR)/ixp400.mod.o
++	make -C $(OBJ_DIR)
+ endif
+ 
+ 
+Index: ixp400_xscale_sw/ixp400.c
+===================================================================
+--- /dev/null
++++ ixp400_xscale_sw/ixp400.c
+@@ -0,0 +1 @@
++#error this file must never be compiled
+Index: ixp400_xscale_sw/Makefile.kmod26
+===================================================================
+--- /dev/null
++++ ixp400_xscale_sw/Makefile.kmod26
+@@ -0,0 +1,11 @@
++obj-m := ixp400.o
++
++PWD         := $(shell pwd)
++
++LINUX_SRC := $($(IX_TARGET)_KERNEL_DIR)
++
++default:
++	$(MAKE) ARCH=arm CROSS_COMPILE=$(LINUX_CROSS_COMPILE) $(KERNEL_VERBOSE) -C $(LINUX_SRC) SUBDIRS=$(PWD) modules
++
++clean:
++	rm -f ixp400.ko
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/rtl8201-support.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/rtl8201-support.patch
new file mode 100644
index 0000000000..150dc27016
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/rtl8201-support.patch
@@ -0,0 +1,30 @@
+this patch adds support for the RTL8201CP PHY
+
+--- ixp400_xscale_sw/src/ethMii/IxEthMii.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/ethMii/IxEthMii.c	1970-01-01 00:00:00.000000000 +0000
+@@ -119,6 +119,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT3
+ 		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973_PHY_ID)
+ 		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973A3_PHY_ID)
+ 		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT9785_PHY_ID)
++		    || (ixEthMiiPhyId[i] == IX_ETH_MII_RTL8201_PHY_ID)
+ 		    )
+ 		{
+ 		    /* supported phy */
+@@ -287,6 +288,7 @@ ixEthMiiPhyReset(UINT32 phyAddr)
+ 	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID)	||
+ 	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973_PHY_ID)	||
+ 	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973A3_PHY_ID)	||
++	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_RTL8201_PHY_ID)	||
+ 		(ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
+ 	    )
+ 	{
+--- ixp400_xscale_sw/src/ethMii/IxEthMii_p.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/ethMii/IxEthMii_p.h	1970-01-01 00:00:00.000000000 +0000
+@@ -179,6 +179,7 @@
+ #define IX_ETH_MII_LXT973A3_PHY_ID   	0x00137A11
+ #define IX_ETH_MII_KS8995_PHY_ID   	0x00221450
+ #define IX_ETH_MII_LXT9785_PHY_ID       0x001378FF
++#define IX_ETH_MII_RTL8201_PHY_ID       0x00008201
+ #define IX_ETH_MII_RTL8305_FAKE_PHY_ID  0x83058305
+ 
+ #define IX_ETH_MII_INVALID_PHY_ID 	0x00000000
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1.1/undefined-attribute.patch b/recipes/ixp4xx/ixp4xx-csr-2.1.1/undefined-attribute.patch
new file mode 100644
index 0000000000..8a08f862f6
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1.1/undefined-attribute.patch
@@ -0,0 +1,16 @@
+ src/include/IxEthDB.h |    2 +-
+ 1 files changed, 1 insertion(+), 1 deletion(-)
+
+Index: ixp400_xscale_sw/src/include/IxEthDB.h
+===================================================================
+--- ixp400_xscale_sw.orig/src/include/IxEthDB.h
++++ ixp400_xscale_sw/src/include/IxEthDB.h
+@@ -273,7 +273,7 @@
+ typedef struct  
+ {
+    UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
+-} IX_OSAL_ATTRIBUTE_PACKED IxEthDBMacAddr;
++} IxEthDBMacAddr;
+ 
+ /**
+  *
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/Makefile.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/Makefile.patch
new file mode 100644
index 0000000000..f082b713f0
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/Makefile.patch
@@ -0,0 +1,26 @@
+--- ixp400_xscale_sw/Makefile	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/Makefile	1970-01-01 00:00:00.000000000 +0000
+@@ -297,9 +297,9 @@ endif
+ else # IX_TARGET_OS == vxworks
+ # linux compiler flags 
+ MAKE_DEP_FLAG := -M
+-LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mcpu=xscale -mtune=xscale
++LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mtune=xscale
+ 
+-CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common -pipe -mapcs-32 -mshort-load-bytes -msoft-float -DMODULE -Isrc/include -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS)
++CFLAGS := -D__KERNEL__ -I$(LINUX_SRC)/include -Wall -Wno-trigraphs -fno-common -pipe -msoft-float -DMODULE -Isrc/include -D__linux -DCPU=33 -DXSCALE=33 $(LINUX_MACH_CFLAGS)
+ ifndef IX_INCLUDE_MICROCODE
+ CFLAGS += -DIX_NPEDL_READ_MICROCODE_FROM_FILE
+ endif
+@@ -867,9 +867,11 @@ $(NPE_DAT) : $(NPE_CONVERTER)
+ 
+ ifeq ($(IX_HOST_OS),linux)
+ ifndef IX_INCLUDE_MICROCODE
++ifdef IX_BUILD_MICROCODE
+ Makefile: $(NPE_CONVERTER) $(NPE_DAT)
+ endif
+ endif
++endif
+ 
+ ################################################################
+ # Rules to check that macros are defined.
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/bit-macro.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/bit-macro.patch
new file mode 100644
index 0000000000..6efdba5c1e
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/bit-macro.patch
@@ -0,0 +1,14 @@
+--- ixp400_xscale_sw/src/include/IxTypes.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/include/IxTypes.h	1970-01-01 00:00:00.000000000 +0000
+@@ -79,6 +79,10 @@
+ #endif
+ #endif
+ 
++#ifndef BIT
++#define BIT(x)  ((1)<<(x))
++#endif
++
+ #include "IxOsalBackward.h"
+ 
+ #endif /* IxTypes_H */
+
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/gcc4.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/gcc4.patch
new file mode 100644
index 0000000000..a701328dd1
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/gcc4.patch
@@ -0,0 +1,23 @@
+--- ixp400/src/npeMh/IxNpeMhSymbols.c~	2006-01-08 03:13:28.000000000 +1030
++++ ixp400/src/npeMh/IxNpeMhSymbols.c	2006-01-09 00:56:57.000000000 +1030
+@@ -52,6 +52,7 @@
+ 
+ #include <linux/module.h>
+ #include <IxNpeMh.h>
++#include <IxNpeMhConfig_p.h>
+ 
+ EXPORT_SYMBOL(ixNpeMhInitialize);
+ EXPORT_SYMBOL(ixNpeMhUnload);
+@@ -67,9 +68,9 @@ extern BOOL ixNpeMhConfigInFifoIsFull(Ix
+ extern BOOL ixNpeMhConfigOutFifoIsEmpty (IxNpeMhNpeId npeId);
+ extern void ixNpeMhConfigLockRelease (IxNpeMhNpeId npeId);
+ extern void ixNpeMhConfigLockGet (IxNpeMhNpeId npeId);
+-extern void ixNpeMhConfigOutFifoRead (IxNpeMhNpeId npeId,IxNpeMhMessage *message);
+-extern void ixNpeMhConfigInFifoWrite (IxNpeMhNpeId npeId,IxNpeMhMessage message);
+-extern struct ixNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];
++extern IX_STATUS ixNpeMhConfigOutFifoRead (IxNpeMhNpeId npeId,IxNpeMhMessage *message);
++extern IX_STATUS ixNpeMhConfigInFifoWrite (IxNpeMhNpeId npeId,IxNpeMhMessage message);
++extern IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];
+ 
+ EXPORT_SYMBOL(ixNpeMhConfigInFifoIsFull);
+ EXPORT_SYMBOL(ixNpeMhConfigOutFifoIsEmpty);
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/ixethdb-header.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/ixethdb-header.patch
new file mode 100644
index 0000000000..8ab22bee89
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/ixethdb-header.patch
@@ -0,0 +1,11 @@
+--- ixp400_xscale_sw/src/ethDB/include/IxEthDB_p.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/ethDB/include/IxEthDB_p.h	1970-01-01 00:00:00.000000000 +0000
+@@ -693,7 +693,7 @@ IX_ETH_DB_PUBLIC UINT32 ixEthDBEntryXORH
+ IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress);
+ 
+ /* Port updates */
+-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBFeature type);
++IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type);
+ IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts);
+ IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID);
+ IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void);
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/ixnpemhconfigisr-is-private.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/ixnpemhconfigisr-is-private.patch
new file mode 100644
index 0000000000..54faadf34a
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/ixnpemhconfigisr-is-private.patch
@@ -0,0 +1,18 @@
+--- ixp400_xscale_sw/src/npeMh/IxNpeMhSymbols.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/npeMh/IxNpeMhSymbols.c	1970-01-01 00:00:00.000000000 +0000
+@@ -63,7 +63,6 @@ EXPORT_SYMBOL(ixNpeMhMessagesReceive);
+ EXPORT_SYMBOL(ixNpeMhShow);
+ EXPORT_SYMBOL(ixNpeMhShowReset);
+ 
+-extern void ixNpeMhConfigIsr (void *parameter);
+ extern BOOL ixNpeMhConfigInFifoIsFull(IxNpeMhNpeId npeId);
+ extern BOOL ixNpeMhConfigOutFifoIsEmpty (IxNpeMhNpeId npeId);
+ extern void ixNpeMhConfigLockRelease (IxNpeMhNpeId npeId);
+@@ -72,7 +71,6 @@ extern void ixNpeMhConfigOutFifoRead (Ix
+ extern void ixNpeMhConfigInFifoWrite (IxNpeMhNpeId npeId,IxNpeMhMessage message);
+ extern struct ixNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];
+ 
+-EXPORT_SYMBOL(ixNpeMhConfigIsr);
+ EXPORT_SYMBOL(ixNpeMhConfigInFifoIsFull);
+ EXPORT_SYMBOL(ixNpeMhConfigOutFifoIsEmpty);
+ EXPORT_SYMBOL(ixNpeMhConfigLockRelease);
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/le.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/le.patch
new file mode 100644
index 0000000000..c308493a08
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/le.patch
@@ -0,0 +1,13 @@
+--- ixp400_xscale_sw/src/include/IxQMgr.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/include/IxQMgr.h	1970-01-01 00:00:00.000000000 +0000
+@@ -96,8 +98,8 @@
+ 
+ #else
+ 
+-#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_DC
+-#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_DC
++#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_AC
++#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_AC
+ 
+ #endif
+ 
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/livelock.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/livelock.patch
new file mode 100644
index 0000000000..0b4e4ba026
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/livelock.patch
@@ -0,0 +1,19 @@
+*** ixp400_xscale_sw/src/oslinux/IxLinuxInit.c.orig	Sun Sep 25 05:59:03 2005
+--- ixp400_xscale_sw/src/oslinux/IxLinuxInit.c	Fri Jun  9 14:07:06 2006
+***************
+*** 91,97 ****
+  
+  
+  /* Module parameters */
+! static int livelock_dispatcher = 0;/* default: don't use livelock dispatcher*/
+  
+  MODULE_PARM(livelock_dispatcher, "i");
+  MODULE_PARM_DESC(livelock_dispatcher, "If non-zero, use the livelock prevention qmgr dispatcher");
+--- 91,97 ----
+  
+  
+  /* Module parameters */
+! int livelock_dispatcher = 0;/* default: don't use livelock dispatcher*/
+  
+  MODULE_PARM(livelock_dispatcher, "i");
+  MODULE_PARM_DESC(livelock_dispatcher, "If non-zero, use the livelock prevention qmgr dispatcher");
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/mii-debug.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/mii-debug.patch
new file mode 100644
index 0000000000..762743cef5
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/mii-debug.patch
@@ -0,0 +1,26 @@
+debug only patch to add information about MII id problems
+
+--- ixp400_xscale_sw/src/ethMii/IxEthMii.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/ethMii/IxEthMii.c	1970-01-01 00:00:00.000000000 +0000
+@@ -122,6 +122,10 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT3
+ 		    )
+ 		{
+ 		    /* supported phy */
++                    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
++                               IX_OSAL_LOG_DEV_STDOUT,
++				"ixEthMiiPhyScan, Mii %d: Mii PHY ID %8.8x\n", 
++				i, ixEthMiiPhyId[i], 3, 4, 5, 6);
+ 		    phyPresent[i] = TRUE;
+ 		} /* end of if(ixEthMiiPhyId) */
+ 		else
+@@ -131,8 +135,8 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT3
+ 			/* unsupported phy */
+                         ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
+                                    IX_OSAL_LOG_DEV_STDOUT,
+-				    "ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n", 
+-				    ixEthMiiPhyId[i], 2, 3, 4, 5, 6);
++				    "ixEthMiiPhyScan, Mii %d: unexpected Mii PHY ID %8.8x\n", 
++				    i, ixEthMiiPhyId[i], 3, 4, 5, 6);
+ 			ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID;
+ 			phyPresent[i] = TRUE;
+ 		    }
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/module-param.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/module-param.patch
new file mode 100644
index 0000000000..c61fcc00d3
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/module-param.patch
@@ -0,0 +1,19 @@
+ src/oslinux/IxLinuxInit.c |    4 ++++
+ 1 files changed, 4 insertions(+)
+
+Index: ixp400_xscale_sw/src/oslinux/IxLinuxInit.c
+===================================================================
+--- ixp400_xscale_sw.orig/src/oslinux/IxLinuxInit.c
++++ ixp400_xscale_sw/src/oslinux/IxLinuxInit.c
+@@ -93,7 +93,11 @@
+ /* Module parameters */
+ static int livelock_dispatcher = 0;/* default: don't use livelock dispatcher*/
+ 
++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,16)
+ MODULE_PARM(livelock_dispatcher, "i");
++#else
++module_param(livelock_dispatcher, int, 0644);
++#endif
+ MODULE_PARM_DESC(livelock_dispatcher, "If non-zero, use the livelock prevention qmgr dispatcher");
+ 
+ /* Init and cleanup functions for module */
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/oe-makefile.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/oe-makefile.patch
new file mode 100644
index 0000000000..492b1eab03
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/oe-makefile.patch
@@ -0,0 +1,49 @@
+changes to Makefile required only on OE
+
+--- ixp400_xscale_sw/Makefile	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/Makefile	1970-01-01 00:00:00.000000000 +0000
+@@ -1321,10 +1323,26 @@ ixp400.o : $(OBJ_DIR)/ixp400.o
+ 
+ ifndef IX_INCLUDE_MICROCODE
+ $(OBJ_DIR)/ixp400.o: $(COMPONENTS:%=$(OBJ_DIR)/ixp400_%.o) $(OSAL_MODULE)
++	rm -f $(OBJ_DIR)/ixp400.c
++	touch $(OBJ_DIR)/ixp400.c
++	cp Makefile.kmod26 $(OBJ_DIR)/Makefile
++	make -C $(OBJ_DIR)
++	rm -f $(OBJ_DIR)/ixp400.c
++	cp ixp400.c $(OBJ_DIR)/ixp400.c
+ 	$(LD) $(LDFLAGS) $^ -o $@
++	rm -f $(OBJ_DIR)/ixp400.ko $(OBJ_DIR)/ixp400.mod.o
++	make -C $(OBJ_DIR)
+ else
+ $(OBJ_DIR)/ixp400.o: $(COMPONENTS:%=$(OBJ_DIR)/ixp400_%.o) $(NPE_PRODUCTION_HEADER_OBJ) $(OSAL_MODULE)
++	rm -f $(OBJ_DIR)/ixp400.c
++	touch $(OBJ_DIR)/ixp400.c
++	cp Makefile.kmod26 $(OBJ_DIR)/Makefile
++	make -C $(OBJ_DIR)
++	rm -f $(OBJ_DIR)/ixp400.c
++	cp ixp400.c $(OBJ_DIR)/ixp400.c
+ 	$(LD) $(LDFLAGS) $^ -o $@
++	rm -f $(OBJ_DIR)/ixp400.ko $(OBJ_DIR)/ixp400.mod.o
++	make -C $(OBJ_DIR)
+ endif
+ 
+ 
+--- ixp400_xscale_sw/ixp400.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/ixp400.c	1970-01-01 00:00:00.000000000 +0000
+@@ -0,0 +1,1 @@
++#error this file must never be compiled
+--- ixp400_xscale_sw/Makefile.kmod26	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/Makefile.kmod26	1970-01-01 00:00:00.000000000 +0000
+@@ -0,0 +1,11 @@
++obj-m := ixp400.o
++
++PWD         := $(shell pwd)
++
++LINUX_SRC := $($(IX_TARGET)_KERNEL_DIR)
++
++default:
++	$(MAKE) ARCH=arm CROSS_COMPILE=$(LINUX_CROSS_COMPILE) $(KERNEL_VERBOSE) -C $(LINUX_SRC) SUBDIRS=$(PWD) modules
++
++clean:
++	rm -f ixp400.ko
diff --git a/recipes/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch b/recipes/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch
new file mode 100644
index 0000000000..150dc27016
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr-2.1/rtl8201-support.patch
@@ -0,0 +1,30 @@
+this patch adds support for the RTL8201CP PHY
+
+--- ixp400_xscale_sw/src/ethMii/IxEthMii.c	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/ethMii/IxEthMii.c	1970-01-01 00:00:00.000000000 +0000
+@@ -119,6 +119,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT3
+ 		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973_PHY_ID)
+ 		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973A3_PHY_ID)
+ 		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT9785_PHY_ID)
++		    || (ixEthMiiPhyId[i] == IX_ETH_MII_RTL8201_PHY_ID)
+ 		    )
+ 		{
+ 		    /* supported phy */
+@@ -287,6 +288,7 @@ ixEthMiiPhyReset(UINT32 phyAddr)
+ 	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID)	||
+ 	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973_PHY_ID)	||
+ 	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973A3_PHY_ID)	||
++	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_RTL8201_PHY_ID)	||
+ 		(ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
+ 	    )
+ 	{
+--- ixp400_xscale_sw/src/ethMii/IxEthMii_p.h	1970-01-01 00:00:00.000000000 +0000
++++ ixp400_xscale_sw/src/ethMii/IxEthMii_p.h	1970-01-01 00:00:00.000000000 +0000
+@@ -179,6 +179,7 @@
+ #define IX_ETH_MII_LXT973A3_PHY_ID   	0x00137A11
+ #define IX_ETH_MII_KS8995_PHY_ID   	0x00221450
+ #define IX_ETH_MII_LXT9785_PHY_ID       0x001378FF
++#define IX_ETH_MII_RTL8201_PHY_ID       0x00008201
+ #define IX_ETH_MII_RTL8305_FAKE_PHY_ID  0x83058305
+ 
+ #define IX_ETH_MII_INVALID_PHY_ID 	0x00000000
diff --git a/recipes/ixp4xx/ixp4xx-csr/badpaths.patch b/recipes/ixp4xx/ixp4xx-csr/badpaths.patch
new file mode 100644
index 0000000000..c5981aa3b7
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr/badpaths.patch
@@ -0,0 +1,18 @@
+
+#
+# Patch managed by http://www.mn-logistik.de/unsupported/pxa250/patcher
+#
+
+--- ixp400_xscale_sw/src/linux/vx.c~ugh	2003-12-12 14:58:34.000000000 -0500
++++ ixp400_xscale_sw/src/linux/vx.c	2004-11-14 17:50:07.610969440 -0500
+@@ -31,8 +31,8 @@
+  * 
+  * -- End Intel Copyright Notice --
+ */
+-#include <asm-arm/system.h>
+-#include <asm-arm/semaphore.h>
++#include <asm/system.h>
++#include <asm/semaphore.h>
+ #include <linux/kernel.h>
+ #include <linux/time.h>
+ #include <linux/sched.h> 
diff --git a/recipes/ixp4xx/ixp4xx-csr/build-timing-annoyance.patch b/recipes/ixp4xx/ixp4xx-csr/build-timing-annoyance.patch
new file mode 100644
index 0000000000..0c040ec2df
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr/build-timing-annoyance.patch
@@ -0,0 +1,10 @@
+--- ixp400_xscale_sw/Makefile~	2004-11-18 21:26:43.000000000 +1030
++++ ixp400_xscale_sw/Makefile	2004-11-18 21:31:20.000000000 +1030
+@@ -1015,6 +1015,7 @@
+ 	cp Makefile.kmod26 $(OBJ_DIR)/Makefile
+ 	make -C $(OBJ_DIR)
+ 	$(LD) $(LDFLAGS) $^ -o $@
++	sleep 2
+ 	make -C $(OBJ_DIR)
+ 
+ 
diff --git a/recipes/ixp4xx/ixp4xx-csr_1.4.bb b/recipes/ixp4xx/ixp4xx-csr_1.4.bb
new file mode 100644
index 0000000000..3e5b444002
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr_1.4.bb
@@ -0,0 +1,63 @@
+# Intel ixp4xx access library software.  Note that this has an Intel
+# license which restricts its use.
+HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp420.htm"
+LICENSE = "http://www.intel.com/design/network/swsup/np_sla/ixp400.htm"
+LICENSE_HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp425swr1.htm"
+# You must download the following software to your OpenEmbedded downloads
+# directory before using this package:
+#
+#	ixp400AccessLibrary-1_4.zip
+#
+# To do this go to the LICENSE_HOMEPAGE above, register/login (using a
+# web browser which is supported by the login page), this will give you
+# access to the web page from which you can download the software - you
+# need the: "Intel® IXP400 Software and RedBoot* Boot Loader", follow
+# the "Archived" link and the v1.4 software then select the the "Intel
+# Hardware Access Software" "1.4 download", this will take you to the
+# license agreement which you must accept to use this package.
+#
+# Store the file with the name given below in your downloads directory
+#
+SRC_URI  = "http://www.intel.com/Please-Read-The-BB-File/ixp400AccessLibrary-1_4.zip"
+SRC_URI += "http://www.wnk.at/ixp400_accesslib_kernel26/data/patch_accesslib_kernel26_20040811.diff;patch=1"
+SRC_URI += "file://badpaths.patch;patch=1"
+SRC_URI += "file://build-timing-annoyance.patch;patch=1"
+
+S = "${WORKDIR}/ixp400_xscale_sw"
+PR = "r6"
+
+COMPATIBLE_HOST = "^armeb-linux.*"
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+inherit module
+
+#LINUX_MACH_CFLAGS := -D__LINUX_ARM_ARCH__=5 -mcpu=xscale -mtune=xscale
+CFLAGS = "-fno-common -D__KERNEL__ -DMODULE -D__linux -DCPU=33 -DXSCALE=33 \
+	  -D__LINUX_ARM_ARCH__=5 \
+	  -I${S}/src/linux -I${S}/src/include \
+	  ${BUILD_OPTIMIZATION} \
+	  -I${STAGING_KERNEL_DIR}/include"
+
+EXTRA_OEMAKE = "'CFLAGS=${CFLAGS}' \
+		'CC=${KERNEL_CC}' \
+		'LD=${KERNEL_LD}' \
+		'IX_TARGET=linuxbe' \
+		'LINUX_SRC=${STAGING_KERNEL_DIR}' \
+		'ARCH=${ARCH}'"
+#EXTRA_OEMAKE = "'LINUX_SRC=${STAGING_KERNEL_DIR}' 'IX_TARGET=${IX_TARGET}' \
+#	        'ARCH=${TARGET_ARCH}' 'CROSS_COMPILE=${TARGET_PREFIX}'"
+
+do_compile () {
+	oe_runmake ixp400.ko
+}
+
+do_stage () {
+	install -d ${STAGING_INCDIR}/linux/ixp4xx-csr
+	install -m 0644 src/include/*.h ${STAGING_INCDIR}/linux/ixp4xx-csr/
+	cp -RLf src/linux/* ${STAGING_INCDIR}/linux/ixp4xx-csr/
+}
+
+do_install () {
+	install -d ${D}${base_libdir}/modules/${KERNEL_VERSION}/drivers/ixp400
+	install -m 0644 lib/linuxbe/ixp400.ko ${D}${base_libdir}/modules/${KERNEL_VERSION}/drivers/ixp400/
+}
diff --git a/recipes/ixp4xx/ixp4xx-csr_1.5.bb b/recipes/ixp4xx/ixp4xx-csr_1.5.bb
new file mode 100644
index 0000000000..d9c69564f7
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr_1.5.bb
@@ -0,0 +1,63 @@
+# Intel ixp4xx access library software.  Note that this has an Intel
+# license which restricts its use.
+HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp420.htm"
+LICENSE = "http://www.intel.com/design/network/swsup/np_sla/ixp400.htm"
+LICENSE_HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp425swr1.htm"
+# You must download the following software to your OpenEmbedded downloads
+# directory before using this package:
+#
+#	ixp400AccessLibrary-1_5.zip
+#	ixp400NpeLibrary-1_5.zip
+#
+# To do this go to the LICENSE_HOMEPAGE above, register/login (using a
+# web browser which is supported by the login page), this will give you
+# access to the web page from which you can download the software - you
+# need the: "Intel® IXP400 Software and RedBoot* Boot Loader" and, from
+# this the "Intel Hardware Access Software" and "NPE Microcode" (both
+# versions 1.5, encryption is not required.)
+#
+# Store the files with the names given below in your downloads directory
+#
+SRC_URI = "http://www.intel.com/Please-Read-The-BB-File/ixp400AccessLibrary-1_5.zip"
+SRC_URI += "http://www.intel.com/Please-Read-The-BB-File/ixp400NpeLibrary-1_5.zip"
+SRC_URI += "file://2.6.patch;patch=1"
+DEPENDS = "ixp-osal"
+S = "${WORKDIR}/ixp400_xscale_sw"
+PR = "r1"
+
+COMPATIBLE_HOST = "^armeb-linux.*"
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+inherit module
+
+OSAL_PATH = "lib/linux/linuxbe/ixp400"
+# This is a somewhat arbitrary choice:
+OSAL_DIR = "${STAGING_KERNEL_DIR}/ixp_osal"
+
+EXTRA_OEMAKE = "'CC=${KERNEL_CC}' \
+		'LD=${KERNEL_LD}' \
+		'AR=${AR}' \
+		'IX_XSCALE_SW=${S}' \
+		'IX_TARGET=linuxbe' \
+		'IX_MPHY=1' \
+		'IX_MPHYSINGLEPORT=1' \
+		'LINUX_SRC=${STAGING_KERNEL_DIR}' \
+		'LINUX_CROSS_COMPILE=${HOST_PREFIX}' \
+		'OSAL_DIR=${OSAL_DIR}' \
+		'OSAL_IMAGE=${OSAL_DIR}/${OSAL_PATH}/libosal.a' \
+		'OSAL_MODULE=${OSAL_DIR}/${OSAL_PATH}/ixp_osal.o' \
+		"
+
+do_compile () {
+	oe_runmake ixp400.ko
+}
+
+do_stage () {
+	install -d ${STAGING_INCDIR}/linux/ixp4xx-csr
+	install -m 0644 src/include/*.h ${STAGING_INCDIR}/linux/ixp4xx-csr/
+}
+
+do_install () {
+	install -d ${D}${base_libdir}/modules/${KERNEL_VERSION}/drivers/ixp400
+	install -m 0644 lib/linuxbe/ixp400.ko ${D}${base_libdir}/modules/${KERNEL_VERSION}/drivers/ixp400/
+}
diff --git a/recipes/ixp4xx/ixp4xx-csr_2.0.bb b/recipes/ixp4xx/ixp4xx-csr_2.0.bb
new file mode 100644
index 0000000000..e462c505fb
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr_2.0.bb
@@ -0,0 +1,89 @@
+# Intel ixp4xx access library software.  Note that this has an Intel
+# license which restricts its use.
+HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp420.htm"
+LICENSE = "http://www.intel.com/design/network/swsup/np_sla/ixp400.htm"
+LICENSE_HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp425swr1.htm"
+# You must download the following software to your OpenEmbedded downloads
+# directory before using this package:
+#
+#	IPL_ixp400AccessLibrary-2_0.zip
+#	IPL_ixp400NpeLibrary-2_0_5.zip
+#
+# To do this go to the LICENSE_HOMEPAGE above, register/login (using a
+# web browser which is supported by the login page), this will give you
+# access to the web page from which you can download the software - you
+# need the: "Intel® IXP400 Software and RedBoot* Boot Loader" and, from
+# this the "Intel Hardware Access Software" and "NPE Microcode" (both
+# versions 2.0, encryption is not required.)
+#
+# Store the files with the names given below in your downloads directory
+# and store the 32 character md5sum of the file in a file of the same
+# name with the additional extension .md5:
+#
+#	IPL_ixp400AccessLibrary-2_0.zip.md5
+#	IPL_ixp400NpeLibrary-2_0_5.zip.md5
+#
+SRC_URI = "http://www.intel.com/Please-Read-The-BB-File/IPL_ixp400AccessLibrary-2_0.zip"
+SRC_URI += "http://www.intel.com/Please-Read-The-BB-File/IPL_ixp400NpeLibrary-2_0_5.zip"
+SRC_URI += "file://Makefile.patch;patch=1"
+SRC_URI += "file://2.6.patch;patch=1"
+SRC_URI += "file://2.6.14.patch;patch=1"
+SRC_URI += "file://le.patch;patch=1"
+DEPENDS = "ixp-osal"
+S = "${WORKDIR}/ixp400_xscale_sw"
+PR = "r6"
+
+COMPATIBLE_HOST = "^arm.*-linux.*"
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+inherit module
+
+IX_TARGET = "linux${SITEINFO_ENDIANESS}"
+
+OSAL_PATH = "lib/ixp425/linux/${IX_TARGET}"
+# This is a somewhat arbitrary choice:
+OSAL_DIR = "${STAGING_KERNEL_DIR}/ixp_osal"
+
+# COMPONENTS: do not build all the components, this just creates a
+# ridiculously large module which duplicates functionality in the
+# available Linux drivers.
+COMPONENTS = "qmgr npeMh npeDl ethAcc ethDB ethMii featureCtrl osServices oslinux"
+CODELETS_COMPONENTS = ""
+
+# NOTE: IX_INCLUDE_MICROCODE causes the microcode to be included in
+# the ixp4xx-csr module, this *requires* the IPL_ixp400NpeLibrary-2_0.zip
+# to be added to the SRC_URI - see above.
+EXTRA_OEMAKE = "'CC=${KERNEL_CC}' \
+		'LD=${KERNEL_LD}' \
+		'AR=${AR}' \
+		'IX_XSCALE_SW=${S}' \
+		'IX_TARGET=${IX_TARGET}' \
+		'${IX_TARGET}_COMPONENTS=${COMPONENTS}' \
+		'${IX_TARGET}_CODELETS_COMPONENTS=${CODELETS_COMPONENTS}' \
+		'IX_DEVICE=ixp42X' \
+		'IX_MPHY=1' \
+		'IX_MPHYSINGLEPORT=1' \
+		'IX_INCLUDE_MICROCODE=1' \
+		'LINUX_SRC=${STAGING_KERNEL_DIR}' \
+		'LINUX_CROSS_COMPILE=${HOST_PREFIX}' \
+		'OSAL_DIR=${OSAL_DIR}' \
+		'OSAL_IMAGE=${OSAL_DIR}/${OSAL_PATH}/libosal.a' \
+		'OSAL_MODULE=${OSAL_DIR}/${OSAL_PATH}/ixp_osal.o' \
+		"
+
+do_compile () {
+	# The target makes the .ko as a side effect, as a result of the
+	# Makefile.patch
+	oe_runmake lib/${IX_TARGET}/ixp400.o
+}
+
+do_stage () {
+	install -d ${STAGING_INCDIR}/linux/ixp4xx-csr
+	install -m 0644 src/include/*.h ${STAGING_INCDIR}/linux/ixp4xx-csr/
+}
+
+
+do_install () {
+	install -d ${D}${base_libdir}/modules/${KERNEL_VERSION}/kernel/drivers/ixp400
+	install -m 0644 lib/${IX_TARGET}/ixp400.ko ${D}${base_libdir}/modules/${KERNEL_VERSION}/kernel/drivers/ixp400/
+}
diff --git a/recipes/ixp4xx/ixp4xx-csr_2.1.1.bb b/recipes/ixp4xx/ixp4xx-csr_2.1.1.bb
new file mode 100644
index 0000000000..32685d30f6
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr_2.1.1.bb
@@ -0,0 +1,121 @@
+DEFAULT_PREFERENCE = "-1"
+# Intel ixp4xx access library software.  Note that this has an Intel
+# license which restricts its use.
+HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp420.htm"
+LICENSE = "http://www.intel.com/design/network/swsup/np_sla/ixp400.htm"
+LICENSE_HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp425swr1.htm"
+# You must download the following software to your OpenEmbedded downloads
+# directory before using this package:
+#
+#	BSD_ixp400AccessLibrary-2_1.zip
+#	BSD_ixp400AccessLibrary-2_1_1.zip
+#	IPL_ixp400NpeLibrary-2_1.zip
+#
+# To do this go to the LICENSE_HOMEPAGE above, register/login (using a
+# web browser which is supported by the login page), this will give you
+# access to the web page from which you can download the software - you
+# need the: "Intel® IXP400 Software and RedBoot* Boot Loader" and, from
+# this the "Intel Hardware Access Software" and "NPE Microcode" (both
+# versions 2.1, encryption is not required.)
+#
+# Store the files with the names given below in your downloads directory
+# and store the 32 character md5sum of the file in a file of the same
+# name with the additional extension .md5:
+#
+#	BSD_ixp400AccessLibrary-2_1.zip.md5
+#	BSD_ixp400AccessLibrary-2_1_1.zip.md5
+#	IPL_ixp400NpeLibrary-2_1.zip.md5
+#
+SRC_URI =  "http://www.intel.com/Please-Read-The-BB-File/BSD_ixp400AccessLibrary-2_1.zip"
+SRC_URI += "http://www.intel.com/Please-Read-The-BB-File/BSD_ixp400AccessLibrary-2_1_1.zip"
+SRC_URI += "http://www.intel.com/Please-Read-The-BB-File/IPL_ixp400NpeLibrary-2_1.zip"
+SRC_URI += "file://bit-macro.patch;patch=1"
+SRC_URI += "file://le.patch;patch=1"
+SRC_URI += "file://mii-debug.patch;patch=1"
+SRC_URI += "file://rtl8201-support.patch;patch=1"
+SRC_URI += "file://oe-makefile.patch;patch=1"
+SRC_URI += "file://livelock.patch;patch=1"
+SRC_URI += "file://module-param.patch;patch=1"
+SRC_URI += "file://undefined-attribute.patch;patch=1"
+
+DEPENDS = "ixp-osal"
+S = "${WORKDIR}/ixp400_xscale_sw"
+PR = "r2"
+
+COMPATIBLE_HOST = "^arm.*-linux.*"
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+inherit module
+
+do_pre_patch () {
+	cd ${WORKDIR} ; patch -p0 < BSD_ixp400AccessLibrary-2_1_1.patch
+}
+
+addtask pre_patch before do_patch
+
+IX_TARGET = "linux${SITEINFO_ENDIANESS}"
+IX_ENSURE = ""
+#IX_ENSURE = "IX_OSAL_ENSURE_ON=1"
+
+OSAL_PATH = "lib/ixp425/linux/${IX_TARGET}"
+# This is a somewhat arbitrary choice:
+OSAL_DIR = "${STAGING_KERNEL_DIR}/ixp_osal"
+
+# COMPONENTS: do not build all the components, this just creates a
+# ridiculously large module which duplicates functionality in the
+# available Linux drivers.
+COMPONENTS = "qmgr npeMh npeDl ethAcc ethDB ethMii featureCtrl osServices oslinux"
+CODELETS_COMPONENTS = ""
+
+# NOTE: IX_INCLUDE_MICROCODE causes the microcode to be included in
+# the ixp4xx-csr module, this *requires* the IPL_ixp400NpeLibrary-2_1.zip
+# to be added to the SRC_URI - see above.
+EXTRA_OEMAKE = "'AR=${AR}' \
+		'IX_LINUXVER=2.6' \
+		'IX_XSCALE_SW=${S}' \
+		'IX_TARGET=${IX_TARGET}' \
+		'${IX_TARGET}_COMPONENTS=${COMPONENTS}' \
+		'${IX_TARGET}_CODELETS_COMPONENTS=${CODELETS_COMPONENTS}' \
+		'IX_DEVICE=ixp42X' \
+		'IX_BUILD_MICROCODE=1' \
+		'IX_UTOPIAMODE=0' \
+		'IX_MPHYSINGLEPORT=1' \
+		${IX_ENSURE} \
+		'LINUX_SRC=${STAGING_KERNEL_DIR}' \
+		'LINUX_CROSS_COMPILE=${HOST_PREFIX}' \
+		'OSAL_DIR=${OSAL_DIR}' \
+		'OSAL_IMAGE=${OSAL_DIR}/${OSAL_PATH}/libosal.a' \
+		'OSAL_MODULE=${OSAL_DIR}/${OSAL_PATH}/ixp_osal.o' \
+		"
+
+MAKE_TARGETS = "ixp400"
+
+KCONFIG_FILE = "${STAGING_KERNEL_DIR}/kernel-config"
+do_stage () {
+	install -d ${STAGING_INCDIR}/linux/ixp4xx-csr
+	install -m 0644 src/include/*.h ${STAGING_INCDIR}/linux/ixp4xx-csr/
+	# Since Module.symvers in the kernel staging directory doesn't include
+	# the symbols from ixp400.o we need to add them to another file for
+	# the ixp400-eth build
+	rm -f '${STAGING_KERNEL_DIR}/ixp400-csr.symvers'
+	. '${KCONFIG_FILE}'
+	if '${STAGING_KERNEL_DIR}/scripts/mod/modpost' \
+		${CONFIG_MODVERSIONS:+-m} \
+		${CONFIG_MODULE_SRCVERSION_ALL:+-a} \
+		-i '${STAGING_KERNEL_DIR}/Module.symvers' \
+		-o '${STAGING_KERNEL_DIR}/ixp400-csr.symvers' \
+		lib/${IX_TARGET}/ixp400.o 2>&1 | egrep .
+	then
+		echo "MODPOST errors - see above"
+		return 1
+	else
+		return 0
+	fi
+}
+
+
+do_install () {
+	install -d ${D}${base_libdir}/modules/${KERNEL_VERSION}/kernel/drivers/ixp400
+	install -m 0644 lib/${IX_TARGET}/ixp400.ko ${D}${base_libdir}/modules/${KERNEL_VERSION}/kernel/drivers/ixp400/
+	install -m 0644 lib/${IX_TARGET}/IxNpeMicrocode.dat ${D}${base_libdir}/modules/${KERNEL_VERSION}/kernel/drivers/ixp400/
+}
diff --git a/recipes/ixp4xx/ixp4xx-csr_2.1.bb b/recipes/ixp4xx/ixp4xx-csr_2.1.bb
new file mode 100644
index 0000000000..e95f807107
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-csr_2.1.bb
@@ -0,0 +1,112 @@
+# Intel ixp4xx access library software.  Note that this has an Intel
+# license which restricts its use.
+HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp420.htm"
+LICENSE = "http://www.intel.com/design/network/swsup/np_sla/ixp400.htm"
+LICENSE_HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp425swr1.htm"
+# You must download the following software to your OpenEmbedded downloads
+# directory before using this package:
+#
+#	IPL_ixp400AccessLibrary-2_1.zip
+#	IPL_ixp400NpeLibrary-2_1.zip
+#
+# To do this go to the LICENSE_HOMEPAGE above, register/login (using a
+# web browser which is supported by the login page), this will give you
+# access to the web page from which you can download the software - you
+# need the: "Intel® IXP400 Software and RedBoot* Boot Loader" and, from
+# this the "Intel Hardware Access Software" and "NPE Microcode" (both
+# versions 2.1, encryption is not required.)
+#
+# Store the files with the names given below in your downloads directory
+# and store the 32 character md5sum of the file in a file of the same
+# name with the additional extension .md5:
+#
+#	IPL_ixp400AccessLibrary-2_1.zip.md5
+#	IPL_ixp400NpeLibrary-2_1.zip.md5
+#
+SRC_URI = "http://www.intel.com/Please-Read-The-BB-File/IPL_ixp400AccessLibrary-2_1.zip"
+SRC_URI += "http://www.intel.com/Please-Read-The-BB-File/IPL_ixp400NpeLibrary-2_1.zip"
+SRC_URI += "file://Makefile.patch;patch=1"
+SRC_URI += "file://ixethdb-header.patch;patch=1"
+SRC_URI += "file://bit-macro.patch;patch=1"
+SRC_URI += "file://ixnpemhconfigisr-is-private.patch;patch=1"
+SRC_URI += "file://le.patch;patch=1"
+SRC_URI += "file://mii-debug.patch;patch=1"
+SRC_URI += "file://rtl8201-support.patch;patch=1"
+SRC_URI += "file://gcc4.patch;patch=1"
+SRC_URI += "file://oe-makefile.patch;patch=1"
+SRC_URI += "file://livelock.patch;patch=1"
+SRC_URI += "file://module-param.patch;patch=1"
+
+DEPENDS = "ixp-osal"
+S = "${WORKDIR}/ixp400_xscale_sw"
+PR = "r12"
+
+COMPATIBLE_HOST = "^arm.*-linux.*"
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+inherit module
+
+IX_TARGET = "linux${SITEINFO_ENDIANESS}"
+IX_ENSURE = ""
+#IX_ENSURE = "IX_OSAL_ENSURE_ON=1"
+
+OSAL_PATH = "lib/ixp425/linux/${IX_TARGET}"
+# This is a somewhat arbitrary choice:
+OSAL_DIR = "${STAGING_KERNEL_DIR}/ixp_osal"
+
+# COMPONENTS: do not build all the components, this just creates a
+# ridiculously large module which duplicates functionality in the
+# available Linux drivers.
+COMPONENTS = "qmgr npeMh npeDl ethAcc ethDB ethMii featureCtrl osServices oslinux"
+CODELETS_COMPONENTS = ""
+
+# NOTE: IX_INCLUDE_MICROCODE causes the microcode to be included in
+# the ixp4xx-csr module, this *requires* the IPL_ixp400NpeLibrary-2_1.zip
+# to be added to the SRC_URI - see above.
+EXTRA_OEMAKE = "'AR=${AR}' \
+		'IX_XSCALE_SW=${S}' \
+		'IX_TARGET=${IX_TARGET}' \
+		'${IX_TARGET}_COMPONENTS=${COMPONENTS}' \
+		'${IX_TARGET}_CODELETS_COMPONENTS=${CODELETS_COMPONENTS}' \
+		'IX_DEVICE=ixp42X' \
+		'IX_INCLUDE_MICROCODE=1' \
+		'IX_UTOPIAMODE=0' \
+		'IX_MPHYSINGLEPORT=1' \
+		${IX_ENSURE} \
+		'LINUX_SRC=${STAGING_KERNEL_DIR}' \
+		'LINUX_CROSS_COMPILE=${HOST_PREFIX}' \
+		'OSAL_DIR=${OSAL_DIR}' \
+		'OSAL_IMAGE=${OSAL_DIR}/${OSAL_PATH}/libosal.a' \
+		'OSAL_MODULE=${OSAL_DIR}/${OSAL_PATH}/ixp_osal.o' \
+		"
+
+MAKE_TARGETS = "lib/${IX_TARGET}/ixp400.o"
+
+KCONFIG_FILE = "${STAGING_KERNEL_DIR}/kernel-config"
+do_stage () {
+	install -d ${STAGING_INCDIR}/linux/ixp4xx-csr
+	install -m 0644 src/include/*.h ${STAGING_INCDIR}/linux/ixp4xx-csr/
+	# Since Module.symvers in the kernel staging directory doesn't include
+	# the symbols from ixp400.o we need to add them to another file for
+	# the ixp400-eth build
+	rm -f '${STAGING_KERNEL_DIR}/ixp400-csr.symvers'
+	. '${KCONFIG_FILE}'
+	if '${STAGING_KERNEL_DIR}/scripts/mod/modpost' \
+		${CONFIG_MODVERSIONS:+-m} \
+		${CONFIG_MODULE_SRCVERSION_ALL:+-a} \
+		-i '${STAGING_KERNEL_DIR}/Module.symvers' \
+		-o '${STAGING_KERNEL_DIR}/ixp400-csr.symvers' \
+		${MAKE_TARGETS} 2>&1 | egrep .
+	then
+		echo "MODPOST errors - see above"
+		return 1
+	else
+		return 0
+	fi
+}
+
+
+do_install () {
+	install -d ${D}${base_libdir}/modules/${KERNEL_VERSION}/kernel/drivers/ixp400
+	install -m 0644 lib/${IX_TARGET}/ixp400.ko ${D}${base_libdir}/modules/${KERNEL_VERSION}/kernel/drivers/ixp400/
+}
diff --git a/recipes/ixp4xx/ixp4xx-npe-2.4/Intel b/recipes/ixp4xx/ixp4xx-npe-2.4/Intel
new file mode 100644
index 0000000000..2d57fedc15
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-npe-2.4/Intel
@@ -0,0 +1,40 @@
+The ixp4xx-npe package (which installs unmodified Intel NPE microcode
+files in /lib/firmware/NPE-B and /lib/firmware/NPE-C) is licensed
+according to the following Intel Software License Agreement:
+
+INTEL SOFTWARE LICENSE AGREEMENT
+ 
+Copyright (c) 2007, Intel Corporation.
+All rights reserved.
+
+Redistribution. Redistribution and use in binary form, without
+modification, are permitted provided that the following conditions are
+met:
+* Redistributions must reproduce the above copyright notice and the
+following disclaimer in the documentation and/or other materials
+provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its suppliers
+may be used to endorse or promote products derived from this software
+without specific prior written permission.
+* No reverse engineering, decompilation, or disassembly of this software is permitted.
+
+Limited patent license. Intel Corporation grants a world-wide,
+royalty-free, non-exclusive license under patents it now or hereafter
+owns or controls to make, have made, use, import, offer to sell and
+sell (.Utilize.) this software, but solely to the extent that any such
+patent is necessary to Utilize the software alone. The patent license
+shall not apply to any combinations which include this software. No
+hardware per se is licensed hereunder.
+
+DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
+BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGE.
diff --git a/recipes/ixp4xx/ixp4xx-npe-native-2.1/IxNpeMicrocode.h b/recipes/ixp4xx/ixp4xx-npe-native-2.1/IxNpeMicrocode.h
new file mode 100644
index 0000000000..1c3d1ff473
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-npe-native-2.1/IxNpeMicrocode.h
@@ -0,0 +1,143 @@
+/*
+ * IxNpeMicrocode.h - Headerfile for compiling the Intel microcode C file
+ *
+ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
+ *
+ * This file is released under the GPLv2
+ *
+ *
+ * compile with
+ *
+ * gcc -Wall IxNpeMicrocode.c -o IxNpeMicrocode
+ *
+ * Executing the resulting binary on your build-host creates the
+ * "NPE-[ABC].xxxxxxxx" files containing the selected microcode
+ *
+ * fetch the IxNpeMicrocode.c from the Intel Access Library.
+ * It will include this header.
+ *
+ * select Images for every NPE from the following
+ * (used C++ comments for easy uncommenting ....)
+ */
+
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_TSLOT_SWITCH
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0
+// #define IX_NPEDL_NPEIMAGE_NPEA_WEP
+
+
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
+
+
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_SPAN
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_FIREWALL
+#define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_CCM_ETH
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_ETH_LEARN_FILTER_SPAN_FIREWALL
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
+
+
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <netinet/in.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <endian.h>
+#include <byteswap.h>
+#include <string.h>
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define to_le32(x) (x)
+#define to_be32(x) bswap_32(x)
+#else
+#define to_be32(x) (x)
+#define to_le32(x) bswap_32(x)
+#endif
+
+struct dl_image {
+	unsigned magic;
+	unsigned id;
+	unsigned size;
+	unsigned data[0];
+};
+
+const unsigned IxNpeMicrocode_array[];
+
+int main(int argc, char *argv[])
+{
+	struct dl_image *image = (struct dl_image *)IxNpeMicrocode_array;
+	int imgsiz, i, fd, cnt;
+	const unsigned *arrayptr = IxNpeMicrocode_array;
+	const char *names[] = { "IXP425", "IXP465", "unknown" };
+	int bigendian = 1;
+
+	if (argc > 1) {
+		if (!strcmp(argv[1], "-le"))
+			bigendian = 0;
+		else if (!strcmp(argv[1], "-be"))
+			bigendian = 1;
+		else {
+			printf("Usage: %s <-le|-be>\n", argv[0]);
+			return EXIT_FAILURE;
+		}
+	}
+
+	for (image = (struct dl_image *)arrayptr, cnt=0;
+		(image->id != 0xfeedf00d) && (image->magic == 0xfeedf00d);
+		image = (struct dl_image *)(arrayptr), cnt++)
+	{
+		unsigned char field[4];
+		imgsiz = image->size + 3;
+		*(unsigned*)field = to_be32(image->id);
+		char filename[40], slnk[10];
+
+		sprintf(filename, "NPE-%c.%08x", (field[0] & 0xf) + 'A',
+			image->id);
+		sprintf(slnk, "NPE-%c", (field[0] & 0xf) + 'A');
+		printf("Writing image: %s.NPE_%c Func: %2x Rev: %02x.%02x "
+			"Size: %5d to: '%s'\n",
+			names[field[0] >> 4], (field[0] & 0xf) + 'A',
+			field[1], field[2], field[3], imgsiz*4, filename);
+		fd = open(filename, O_CREAT | O_RDWR | O_TRUNC, 0644);
+		if (fd >= 0) {
+			for (i=0; i<imgsiz; i++) {
+				*(unsigned*)field = bigendian ?
+					to_be32(arrayptr[i]) :
+					to_le32(arrayptr[i]);
+				write(fd, field, sizeof(field));
+			}
+			close(fd);
+			unlink(slnk);
+			symlink(filename, slnk);
+		} else {
+			perror(filename);
+		}
+		arrayptr += imgsiz;
+	}
+	close(fd);
+	return 0;
+}
diff --git a/recipes/ixp4xx/ixp4xx-npe-native-2.3.2/IxNpeMicrocode.h b/recipes/ixp4xx/ixp4xx-npe-native-2.3.2/IxNpeMicrocode.h
new file mode 100644
index 0000000000..2229619a27
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-npe-native-2.3.2/IxNpeMicrocode.h
@@ -0,0 +1,143 @@
+/*
+ * IxNpeMicrocode.h - Headerfile for compiling the Intel microcode C file
+ *
+ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
+ *
+ * This file is released under the GPLv2
+ *
+ *
+ * compile with
+ *
+ * gcc -Wall IxNpeMicrocode.c -o IxNpeMicrocode
+ *
+ * Executing the resulting binary on your build-host creates the
+ * "NPE-[ABC].xxxxxxxx" files containing the selected microcode
+ *
+ * fetch the IxNpeMicrocode.c from the Intel Access Library.
+ * It will include this header.
+ *
+ * select Images for every NPE from the following
+ * (used C++ comments for easy uncommenting ....)
+ */
+
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_TSLOT_SWITCH
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0
+// #define IX_NPEDL_NPEIMAGE_NPEA_WEP
+
+
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
+
+
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_SPAN
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_FIREWALL
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_CCM_ETH
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_ETH_LEARN_FILTER_SPAN_FIREWALL
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
+
+
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <netinet/in.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <endian.h>
+#include <byteswap.h>
+#include <string.h>
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define to_le32(x) (x)
+#define to_be32(x) bswap_32(x)
+#else
+#define to_be32(x) (x)
+#define to_le32(x) bswap_32(x)
+#endif
+
+struct dl_image {
+	unsigned magic;
+	unsigned id;
+	unsigned size;
+	unsigned data[0];
+};
+
+const unsigned IxNpeMicrocode_array[];
+
+int main(int argc, char *argv[])
+{
+	struct dl_image *image = (struct dl_image *)IxNpeMicrocode_array;
+	int imgsiz, i, fd, cnt;
+	const unsigned *arrayptr = IxNpeMicrocode_array;
+	const char *names[] = { "IXP425", "IXP465", "unknown" };
+	int bigendian = 1;
+
+	if (argc > 1) {
+		if (!strcmp(argv[1], "-le"))
+			bigendian = 0;
+		else if (!strcmp(argv[1], "-be"))
+			bigendian = 1;
+		else {
+			printf("Usage: %s <-le|-be>\n", argv[0]);
+			return EXIT_FAILURE;
+		}
+	}
+
+	for (image = (struct dl_image *)arrayptr, cnt=0;
+		(image->id != 0xfeedf00d) && (image->magic == 0xfeedf00d);
+		image = (struct dl_image *)(arrayptr), cnt++)
+	{
+		unsigned char field[4];
+		imgsiz = image->size + 3;
+		*(unsigned*)field = to_be32(image->id);
+		char filename[40], slnk[10];
+
+		sprintf(filename, "NPE-%c.%08x", (field[0] & 0xf) + 'A',
+			image->id);
+		sprintf(slnk, "NPE-%c", (field[0] & 0xf) + 'A');
+		printf("Writing image: %s.NPE_%c Func: %2x Rev: %02x.%02x "
+			"Size: %5d to: '%s'\n",
+			names[field[0] >> 4], (field[0] & 0xf) + 'A',
+			field[1], field[2], field[3], imgsiz*4, filename);
+		fd = open(filename, O_CREAT | O_RDWR | O_TRUNC, 0644);
+		if (fd >= 0) {
+			for (i=0; i<imgsiz; i++) {
+				*(unsigned*)field = bigendian ?
+					to_be32(arrayptr[i]) :
+					to_le32(arrayptr[i]);
+				write(fd, field, sizeof(field));
+			}
+			close(fd);
+			unlink(slnk);
+			symlink(filename, slnk);
+		} else {
+			perror(filename);
+		}
+		arrayptr += imgsiz;
+	}
+	close(fd);
+	return 0;
+}
diff --git a/recipes/ixp4xx/ixp4xx-npe-native-2.4/IxNpeMicrocode.h b/recipes/ixp4xx/ixp4xx-npe-native-2.4/IxNpeMicrocode.h
new file mode 100644
index 0000000000..5cbb4b473c
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-npe-native-2.4/IxNpeMicrocode.h
@@ -0,0 +1,143 @@
+/*
+ * IxNpeMicrocode.h - Headerfile for compiling the Intel microcode C file
+ *
+ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
+ *
+ * This file is released under the GPLv2
+ *
+ *
+ * compile with
+ *
+ * gcc -Wall IxNpeMicrocode.c -o IxNpeMicrocode
+ *
+ * Executing the resulting binary on your build-host creates the
+ * "NPE-[ABC].xxxxxxxx" files containing the selected microcode
+ *
+ * fetch the IxNpeMicrocode.c from the Intel Access Library.
+ * It will include this header.
+ *
+ * select Images for every NPE from the following
+ * (used C++ comments for easy uncommenting ....)
+ */
+
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_TSLOT_SWITCH
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0
+// #define IX_NPEDL_NPEIMAGE_NPEA_WEP
+
+
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
+
+
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_SPAN
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_FIREWALL
+#define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_CCM_ETH
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_ETH_LEARN_FILTER_SPAN_FIREWALL
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
+
+
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <netinet/in.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <endian.h>
+#include <byteswap.h>
+#include <string.h>
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define to_le32(x) (x)
+#define to_be32(x) bswap_32(x)
+#else
+#define to_be32(x) (x)
+#define to_le32(x) bswap_32(x)
+#endif
+
+struct dl_image {
+	unsigned magic;
+	unsigned id;
+	unsigned size;
+	unsigned data[0];
+};
+
+const unsigned IxNpeMicrocode_array[];
+
+int main(int argc, char *argv[])
+{
+	struct dl_image *image = (struct dl_image *)IxNpeMicrocode_array;
+	int imgsiz, i, fd, cnt;
+	const unsigned *arrayptr = IxNpeMicrocode_array;
+	const char *names[] = { "IXP425", "IXP465", "unknown" };
+	int bigendian = 1;
+
+	if (argc > 1) {
+		if (!strcmp(argv[1], "-le"))
+			bigendian = 0;
+		else if (!strcmp(argv[1], "-be"))
+			bigendian = 1;
+		else {
+			printf("Usage: %s <-le|-be>\n", argv[0]);
+			return EXIT_FAILURE;
+		}
+	}
+
+	for (image = (struct dl_image *)arrayptr, cnt=0;
+		(image->id != 0xfeedf00d) && (image->magic == 0xfeedf00d);
+		image = (struct dl_image *)(arrayptr), cnt++)
+	{
+		unsigned char field[4];
+		imgsiz = image->size + 3;
+		*(unsigned*)field = to_be32(image->id);
+		char filename[40], slnk[10];
+
+		sprintf(filename, "NPE-%c.%08x", (field[0] & 0xf) + 'A',
+			image->id);
+		sprintf(slnk, "NPE-%c", (field[0] & 0xf) + 'A');
+		printf("Writing image: %s.NPE_%c Func: %2x Rev: %02x.%02x "
+			"Size: %5d to: '%s'\n",
+			names[field[0] >> 4], (field[0] & 0xf) + 'A',
+			field[1], field[2], field[3], imgsiz*4, filename);
+		fd = open(filename, O_CREAT | O_RDWR | O_TRUNC, 0644);
+		if (fd >= 0) {
+			for (i=0; i<imgsiz; i++) {
+				*(unsigned*)field = bigendian ?
+					to_be32(arrayptr[i]) :
+					to_le32(arrayptr[i]);
+				write(fd, field, sizeof(field));
+			}
+			close(fd);
+			unlink(slnk);
+			symlink(filename, slnk);
+		} else {
+			perror(filename);
+		}
+		arrayptr += imgsiz;
+	}
+	close(fd);
+	return 0;
+}
diff --git a/recipes/ixp4xx/ixp4xx-npe-native_2.1.bb b/recipes/ixp4xx/ixp4xx-npe-native_2.1.bb
new file mode 100644
index 0000000000..4f1d9383a5
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-npe-native_2.1.bb
@@ -0,0 +1,19 @@
+DESCRIPTION = "Firmware converter for the IXP4xx line of devices"
+LICENSE = "Intel Public Licence"
+PR = "r3"
+
+SRC_URI = "http://www.intel.com/Please-Read-The-BB-File/IPL_ixp400NpeLibrary-2_1.zip"
+SRC_URI += "file://IxNpeMicrocode.h"
+inherit native
+S = "${WORKDIR}/ixp400_xscale_sw/src/npeDl"
+
+do_compile() {
+	mv ${WORKDIR}/IxNpeMicrocode.h ${S}/
+	gcc -Wall IxNpeMicrocode.c -o IxNpeMicrocode
+}
+
+do_stage() {
+	mv ${S}/IxNpeMicrocode ${S}/IxNpeMicrocode-${PV}
+	install -d ${STAGING_BINDIR}/
+	install -m 0755 ${S}/IxNpeMicrocode-${PV} ${STAGING_BINDIR}/
+}
diff --git a/recipes/ixp4xx/ixp4xx-npe-native_2.3.2.bb b/recipes/ixp4xx/ixp4xx-npe-native_2.3.2.bb
new file mode 100644
index 0000000000..9db83352c4
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-npe-native_2.3.2.bb
@@ -0,0 +1,19 @@
+DESCRIPTION = "Firmware converter for the IXP4xx line of devices"
+LICENSE = "Intel Public Licence"
+PR = "r1"
+
+SRC_URI = "http://You-Have-To-Download-The-Microcode-Manually-So-Please-Read-ixp4xx-npe_2.3.2.bb-For-Instructions/IPL_ixp400NpeLibrary-2_3_2.zip"
+SRC_URI += "file://IxNpeMicrocode.h"
+inherit native
+S = "${WORKDIR}/ixp400_xscale_sw/src/npeDl"
+
+do_compile() {
+	mv ${WORKDIR}/IxNpeMicrocode.h ${S}/
+	gcc -Wall IxNpeMicrocode.c -o IxNpeMicrocode
+}
+
+do_stage() {
+	mv ${S}/IxNpeMicrocode ${S}/IxNpeMicrocode-${PV}
+	install -d ${STAGING_BINDIR}/
+	install -m 0755 ${S}/IxNpeMicrocode-${PV} ${STAGING_BINDIR}/
+}
diff --git a/recipes/ixp4xx/ixp4xx-npe-native_2.4.bb b/recipes/ixp4xx/ixp4xx-npe-native_2.4.bb
new file mode 100644
index 0000000000..2b3da60b5d
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-npe-native_2.4.bb
@@ -0,0 +1,19 @@
+DESCRIPTION = "Firmware converter for the IXP4xx line of devices"
+LICENSE = "Intel Software License Agreement"
+PR = "r0"
+
+SRC_URI = "http://You-Have-To-Download-The-Microcode-Manually-So-Please-Read-ixp4xx-npe_2.4.bb-For-Instructions/IPL_ixp400NpeLibrary-2_4.zip"
+SRC_URI += "file://IxNpeMicrocode.h"
+inherit native
+S = "${WORKDIR}/ixp400_xscale_sw/src/npeDl"
+
+do_compile() {
+	mv ${WORKDIR}/IxNpeMicrocode.h ${S}/
+	gcc -Wall IxNpeMicrocode.c -o IxNpeMicrocode
+}
+
+do_stage() {
+	mv ${S}/IxNpeMicrocode ${S}/IxNpeMicrocode-${PV}
+	install -d ${STAGING_BINDIR}/
+	install -m 0755 ${S}/IxNpeMicrocode-${PV} ${STAGING_BINDIR}/
+}
diff --git a/recipes/ixp4xx/ixp4xx-npe_2.1.bb b/recipes/ixp4xx/ixp4xx-npe_2.1.bb
new file mode 100644
index 0000000000..7fdc3abf63
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-npe_2.1.bb
@@ -0,0 +1,23 @@
+DESCRIPTION = "NPE firmware for the IXP4xx line of devices"
+LICENSE = "Intel Public Licence"
+PR = "r6"
+DEPENDS = "ixp4xx-npe-native"
+
+SRC_URI = "http://www.intel.com/Please-Read-The-BB-File/IPL_ixp400NpeLibrary-2_1.zip"
+S = "${WORKDIR}/ixp400_xscale_sw/src/npeDl"
+
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+FILES_${PN} = "${base_libdir}/firmware/NPE-B"
+
+do_compile() {
+	${STAGING_BINDIR_NATIVE}/IxNpeMicrocode-${PV} -be
+}
+
+do_install() {
+	install -d ${D}/${base_libdir}/firmware/
+	rm ${S}/NPE-B
+	mv ${S}/NPE-B.* ${S}/NPE-B
+	install ${S}/NPE-B ${D}/${base_libdir}/firmware/
+}
+
diff --git a/recipes/ixp4xx/ixp4xx-npe_2.3.2.bb b/recipes/ixp4xx/ixp4xx-npe_2.3.2.bb
new file mode 100644
index 0000000000..a53b9d703b
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-npe_2.3.2.bb
@@ -0,0 +1,37 @@
+DESCRIPTION = "NPE firmware for the IXP4xx line of devices"
+LICENSE = "Intel Public Licence"
+PR = "r1"
+DEPENDS = "ixp4xx-npe-native"
+
+# You need to download the IPL_ixp400NpeLibrary-2_3_2.zip file (without crypto) from:
+# http://www.intel.com/design/network/products/npfamily/ixp400_current.htm
+# and put it in your downloads directory so bitbake will find it.
+# Make sure you *read* and accept the license - it is not a standard one.
+
+SRC_URI = "http://You-Have-To-Download-The-Microcode-Manually-So-Please-Read-ixp4xx-npe_2.3.2.bb-For-Instructions/IPL_ixp400NpeLibrary-2_3_2.zip"
+S = "${WORKDIR}/ixp400_xscale_sw/src/npeDl"
+
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+FILES_${PN} = "${base_libdir}/firmware/NPE-B ${base_libdir}/firmware/NPE-C"
+
+do_compile() {
+	${STAGING_BINDIR_NATIVE}/IxNpeMicrocode-${PV} -be
+}
+
+do_install() {
+	install -d ${D}/${base_libdir}/firmware/
+	rm ${S}/NPE-B
+	mv ${S}/NPE-B.* ${S}/NPE-B
+	install ${S}/NPE-B ${D}/${base_libdir}/firmware/
+	rm ${S}/NPE-C
+	mv ${S}/NPE-C.* ${S}/NPE-C
+	install ${S}/NPE-C ${D}/${base_libdir}/firmware/
+}
+
+do_stage() {
+	install -d ${STAGING_FIRMWARE_DIR}
+	install ${S}/NPE-B ${STAGING_FIRMWARE_DIR}/
+	install ${S}/NPE-C ${STAGING_FIRMWARE_DIR}/
+}
+
diff --git a/recipes/ixp4xx/ixp4xx-npe_2.4.bb b/recipes/ixp4xx/ixp4xx-npe_2.4.bb
new file mode 100644
index 0000000000..121838684f
--- /dev/null
+++ b/recipes/ixp4xx/ixp4xx-npe_2.4.bb
@@ -0,0 +1,41 @@
+DESCRIPTION = "NPE firmware for the IXP4xx line of devices"
+LICENSE = "Intel"
+PR = "r1"
+DEPENDS = "ixp4xx-npe-native"
+
+# You need to download the IPL_ixp400NpeLibrary-2_4.zip file (without crypto) from:
+# http://www.intel.com/design/network/products/npfamily/download_ixp400.htm
+# "Intel IXP400 software - NPE microcode (non-crypto)" -> "2.4"
+# and put it in your downloads directory so bitbake will find it.
+# Make sure you *read* and accept the license - it is not a standard one.
+
+SRC_URI = "http://You-Have-To-Download-The-Microcode-Manually-So-Please-Read-ixp4xx-npe_2.4.bb-For-Instructions/IPL_ixp400NpeLibrary-2_4.zip \
+           file://Intel"
+S = "${WORKDIR}/ixp400_xscale_sw/src/npeDl"
+
+COMPATIBLE_MACHINE = "(nslu2|ixp4xx)"
+
+FILES_${PN} = "${base_libdir}/firmware/NPE-B ${base_libdir}/firmware/NPE-C"
+
+do_compile() {
+	${STAGING_BINDIR_NATIVE}/IxNpeMicrocode-${PV} -be
+}
+
+do_install() {
+	install -d ${D}/${base_libdir}/firmware/
+	rm ${S}/NPE-B
+	mv ${S}/NPE-B.* ${S}/NPE-B
+	install ${S}/NPE-B ${D}/${base_libdir}/firmware/
+	rm ${S}/NPE-C
+	mv ${S}/NPE-C.* ${S}/NPE-C
+	install ${S}/NPE-C ${D}/${base_libdir}/firmware/
+	install -d ${D}/${datadir}/common-licenses/
+	install -m 0644 ${WORKDIR}/Intel ${D}${datadir}/common-licenses/
+}
+
+do_stage() {
+	install -d ${STAGING_FIRMWARE_DIR}
+	install ${S}/NPE-B ${STAGING_FIRMWARE_DIR}/
+	install ${S}/NPE-C ${STAGING_FIRMWARE_DIR}/
+}
+