diff options
| author | Khem Raj <raj.khem@gmail.com> | 2009-10-06 15:29:34 -0700 |
|---|---|---|
| committer | Khem Raj <raj.khem@gmail.com> | 2009-10-06 15:31:34 -0700 |
| commit | 84011b0d22f56008f5fd7f9c53a0e34d5861e50d (patch) | |
| tree | eb993a5c387fe0239a5a8f3befcdac9d7abbe365 /recipes/gcc/gcc-4.4.1/gcc-ppc_single_precision_regs.patch | |
| parent | 44943f01becfb8e61bcaeb40f47e2fd64552b276 (diff) | |
gcc-4.4.1: Backport powerpc patches to improve code generation at -Os
* This also fixes the u-boot build errors we get with gcc 4.4
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Diffstat (limited to 'recipes/gcc/gcc-4.4.1/gcc-ppc_single_precision_regs.patch')
| -rw-r--r-- | recipes/gcc/gcc-4.4.1/gcc-ppc_single_precision_regs.patch | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/recipes/gcc/gcc-4.4.1/gcc-ppc_single_precision_regs.patch b/recipes/gcc/gcc-4.4.1/gcc-ppc_single_precision_regs.patch new file mode 100644 index 0000000000..5b35d6e74c --- /dev/null +++ b/recipes/gcc/gcc-4.4.1/gcc-ppc_single_precision_regs.patch @@ -0,0 +1,60 @@ +Index: gcc-4.4.1/gcc/config/rs6000/rs6000.c +=================================================================== +--- gcc-4.4.1.orig/gcc/config/rs6000/rs6000.c 2009-10-06 13:51:50.427316302 -0700 ++++ gcc-4.4.1/gcc/config/rs6000/rs6000.c 2009-10-06 14:09:04.737313663 -0700 +@@ -22580,7 +22580,8 @@ rs6000_function_value (const_tree valtyp + if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) + /* _Decimal128 must use an even/odd register pair. */ + regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN; +- else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS) ++ else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS ++ && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT)) + regno = FP_ARG_RETURN; + else if (TREE_CODE (valtype) == COMPLEX_TYPE + && targetm.calls.split_complex_arg) +Index: gcc-4.4.1/gcc/config/rs6000/rs6000.md +=================================================================== +--- gcc-4.4.1.orig/gcc/config/rs6000/rs6000.md 2009-10-06 14:08:35.827340958 -0700 ++++ gcc-4.4.1/gcc/config/rs6000/rs6000.md 2009-10-06 14:09:04.737313663 -0700 +@@ -8143,8 +8143,8 @@ + (define_insn "*movsi_internal1" + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") + (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] +- "gpc_reg_operand (operands[0], SImode) +- || gpc_reg_operand (operands[1], SImode)" ++ "!TARGET_SINGLE_FPU && ++ gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode)" + "@ + mr %0,%1 + {cal|la} %0,%a1 +@@ -8162,6 +8162,30 @@ + [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") + (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) + ++(define_insn "*movsi_internal1_single" ++ [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f") ++ (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))] ++ "TARGET_SINGLE_FPU && ++ gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode)" ++ "@ ++ mr %0,%1 ++ {cal|la} %0,%a1 ++ {l%U1%X1|lwz%U1%X1} %0,%1 ++ {st%U0%X0|stw%U0%X0} %1,%0 ++ {lil|li} %0,%1 ++ {liu|lis} %0,%v1 ++ # ++ {cal|la} %0,%a1 ++ mf%1 %0 ++ mt%0 %1 ++ mt%0 %1 ++ mt%0 %1 ++ {cror 0,0,0|nop} ++ stfs%U0%X0 %1, %0 ++ lfs%U1%X1 %0, %1" ++ [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*") ++ (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")]) ++ + ;; Split a load of a large constant into the appropriate two-insn + ;; sequence. + |