rename packages/ to recipes/ per earlier agreement

See links below for more details:
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21326
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21816

Signed-off-by: Denys Dmytriyenko <denis@denix.org>
Acked-by: Mike Westerhof <mwester@dls.net>
Acked-by: Philip Balister <philip@balister.org>
Acked-by: Khem Raj <raj.khem@gmail.com>
Acked-by: Marcin Juszkiewicz <hrw@openembedded.org>
Acked-by: Koen Kooi <koen@openembedded.org>
Acked-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>

5 files changed, 2310 insertions, 0 deletions

diff --git a/recipes/at91bootstrap/at91bootstrap_2.4.bb b/recipes/at91bootstrap/at91bootstrap_2.4.bb
new file mode 100644
index 0000000000..69c7d6c19b
--- /dev/null
+++ b/recipes/at91bootstrap/at91bootstrap_2.4.bb
@@ -0,0 +1,48 @@
+DESCRIPTION = "at91bootstrap"
+SRC_URI = "ftp://www.at91.com/pub/buildroot/${PN}-${PV}.tar.bz2 \
+           "
+SRC_URI_append_afeb9260 = " file://0001-Generic-code-changes.patch;patch=1 \
+           file://0002-Making-image-directly-flashable.patch;patch=1 \
+           file://0003-AFEB9260-board-support.patch;patch=1 \
+           file://0004-AFEB9260-133-board-support.patch;patch=1"
+
+PR = "r4"
+SECTION = "bootloaders"
+
+AT91BOOTSTRAP_MACHINE ?= "${MACHINE}"
+AT91BOOTSTRAP_FLAGS ?= ""
+AT91BOOTSTRAP_MEMORY ?= "dataflash"
+
+AT91BOOTSTRAP_IMAGE = "at91bootstrap-${MACHINE}-${AT91BOOTSTRAP_MEMORY}-${PV}-${PR}.bin"
+AT91BOOTSTRAP_SYMLINK = "at91bootstrap.bin"
+
+S = "${WORKDIR}/${PN}-${PV}"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+EXTRA_OEMAKE = "CROSS_COMPILE=${TARGET_PREFIX} MEMORY=${AT91BOOTSTRAP_MEMORY}"
+
+do_compile () {
+	unset LDFLAGS
+	unset CFLAGS
+	unset CPPFLAGS
+
+	rm -Rf ${S}/binaries
+	oe_runmake ${AT91BOOTSTRAP_MACHINE}_defconfig
+	oe_runmake AT91_CUSTOM_FLAGS="${AT91BOOTSTRAP_FLAGS}"
+	chmod +x ${S}/fixboot.py
+	${S}/fixboot.py ${S}/binaries/${AT91BOOTSTRAP_MACHINE}-${AT91BOOTSTRAP_MEMORY}boot-${PV}.bin
+}
+
+do_deploy () {
+	install -d ${DEPLOY_DIR_IMAGE}
+	install ${S}/binaries/${AT91BOOTSTRAP_MACHINE}-${AT91BOOTSTRAP_MEMORY}boot-${PV}.bin.fixboot \
+		${DEPLOY_DIR_IMAGE}/${AT91BOOTSTRAP_IMAGE}
+	package_stagefile_shell ${DEPLOY_DIR_IMAGE}/${AT91BOOTSTRAP_IMAGE}
+	cd ${DEPLOY_DIR_IMAGE}
+	rm -f ${AT91BOOTSTRAP_SYMLINK}
+	ln -sf ${AT91BOOTSTRAP_IMAGE} ${AT91BOOTSTRAP_SYMLINK}
+	package_stagefile_shell ${DEPLOY_DIR_IMAGE}/${AT91BOOTSTRAP_SYMLINK}
+}
+
+do_deploy[dirs] = "${S}"
+addtask deploy before do_build after do_compile
diff --git a/recipes/at91bootstrap/files/0001-Generic-code-changes.patch b/recipes/at91bootstrap/files/0001-Generic-code-changes.patch
new file mode 100644
index 0000000000..b48327767b
--- /dev/null
+++ b/recipes/at91bootstrap/files/0001-Generic-code-changes.patch
@@ -0,0 +1,781 @@
+From c73e4e2ebd5c818c8c1d70d0376d3b01630d97f4 Mon Sep 17 00:00:00 2001
+From: Sergey Lapin <slapin@ossfans.org>
+Date: Sat, 6 Dec 2008 20:57:03 +0300
+Subject: [PATCH] Generic code changes
+
+* Thumb mode binary
+* cp15 setting from assembler part
+* removed some of unused code
+* cloenup of code
+
+Signed-off-by: Sergey Lapin <slapin@ossfans.org>
+---
+ .config            |    7 --
+ Makefile           |   11 ++--
+ crt0_gnu.S         |    7 ++
+ driver/dataflash.c |  167 +++++++++++++++++++++++++++++++++++++++------------
+ driver/debug.c     |   46 ++++++++++++++
+ driver/driver.mk   |    2 +-
+ driver/gpio.c      |    2 +
+ driver/nandflash.c |    5 +-
+ driver/sdramc.c    |   27 +-------
+ include/debug.h    |   18 ++++++
+ include/nand_ids.h |    1 +
+ main.c             |  167 +++++++++++++++++++++++++++++++++++++++++++++++++--
+ 12 files changed, 376 insertions(+), 84 deletions(-)
+ delete mode 100644 .config
+
+diff --git a/.config b/.config
+deleted file mode 100644
+index 85a177f..0000000
+--- a/.config
++++ /dev/null
+@@ -1,7 +0,0 @@
+-BOARDNAME=at91sam9263ek
+-BOARD=at91sam9263ek
+-PROJECT=dataflash
+-CONFIG_DATAFLASH=y
+-SPI_MODE=SPI_MODE_0
+-SPI_BOOT=SPI_BOOT_CS0
+-SPI_CLK=5000000
+diff --git a/Makefile b/Makefile
+index 5bed79d..475784e 100644
+--- a/Makefile
++++ b/Makefile
+@@ -10,7 +10,7 @@ TOPDIR	:=	$(CURDIR)
+ 
+ VERSION:=2.4
+ 
+-include	.config
++-include	.config
+ 
+ ifeq	($(CONFIG_SPI_MODE),)
+ CONFIG_SPI_MODE=SPI_MODE_0
+@@ -58,15 +58,15 @@ endif
+ SRCS	:= $(COBJS-y:.o=.c)
+ OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+ 
+-INCL=board/$(BOARD)/$(PROJECT)
++INCL=-Iboard/$(BOARD)/$(PROJECT) -Iboard/$(BOARD)
+ 
+-CPPFLAGS=-g -mcpu=arm9 -Os -Wall -D$(TARGET)		\
+-	-I$(INCL) -Iinclude				\
++CPPFLAGS=-g -march=armv5te -mtune=arm926ej-s -mthumb -mthumb-interwork -Os -Wall -D$(TARGET)		\
++	$(INCL) -Iinclude				\
+ 	-DTOP_OF_MEM=$(TOP_OF_MEMORY) 			\
+ 	-D$(SPI_MODE) -D$(SPI_BOOT) -DSPI_CLK=$(SPI_CLK) \
+ 	$(AT91_CUSTOM_FLAGS)
+ 
+-ASFLAGS=-g -mcpu=arm9 -Os -Wall -D$(TARGET) -I$(INCL) -Iinclude -DTOP_OF_MEM=$(TOP_OF_MEMORY)
++ASFLAGS=-g -mcpu=arm9 -Os -Wall -D$(TARGET) $(INCL) -Iinclude -DTOP_OF_MEM=$(TOP_OF_MEMORY)
+ 
+ # Linker flags.
+ #  -Wl,...:     tell GCC to pass this to linker.
+@@ -77,6 +77,7 @@ ASFLAGS=-g -mcpu=arm9 -Os -Wall -D$(TARGET) -I$(INCL) -Iinclude -DTOP_OF_MEM=$(T
+ LDFLAGS+=-nostartfiles -Map=result/$(BOOT_NAME).map --cref
+ #LDFLAGS+=-lc -lgcc
+ LDFLAGS+=-T elf32-littlearm.lds -Ttext $(LINK_ADDR)
++LDFLAGS+= --gc-sections
+ 
+ all: 	binaries/$(BOOT_NAME).bin
+ 
+diff --git a/crt0_gnu.S b/crt0_gnu.S
+index 4811eef..e8379d7 100644
+--- a/crt0_gnu.S
++++ b/crt0_gnu.S
+@@ -115,6 +115,7 @@ _enable_mosc:
+ 	
+ /* Test if MCK == SLOW CLOCK */
+ _switch_to_mosc:
++#if 0
+ 	ldr 	r0,=AT91C_PMC_MCKR
+ 	ldr 	r1,=AT91C_PMC_CSS
+ 	ldr 	r2, [r0]
+@@ -123,6 +124,9 @@ _switch_to_mosc:
+ 	cmp    	r1, r2
+ /* No => Do nothing */
+ 	bne	_init_bss
++#else
++	ldr 	r0,=AT91C_PMC_MCKR
++#endif
+ /* Yes => Switch to the main oscillator */
+ 	ldr 	r1,=AT91C_PMC_CSS_MAIN_CLK
+ 	ldr 	r2,=AT91C_PMC_PRES_CLK
+@@ -147,6 +151,9 @@ _init_bss:
+ 
+ /* Branch on C code Main function (with interworking) */
+ _branch_main:
++	mrc	p15, 0, r4, c1, c0, 0
++	orr	r4, #(1 << 12)
++	mcr	p15, 0, r4, c1, c0, 0
+ 	ldr     r4, = main
+ 	mov     lr, pc
+ 	bx      r4
+diff --git a/driver/dataflash.c b/driver/dataflash.c
+index baf7575..0f0388a 100644
+--- a/driver/dataflash.c
++++ b/driver/dataflash.c
+@@ -59,6 +59,64 @@ static inline unsigned int read_spi(unsigned int offset)
+ 	return readl(offset + AT91C_BASE_SPI);
+ }
+ 
++
++static void msg_df_print(int i)
++{
++	msg_print(MSG_DATAFLASH);
++	msg_print(MSG_SPACE);
++	msg_print(i);
++	msg_print(MSG_NEWLINE);
++}
++static void msg_df_detect(int i)
++{
++	char * pn;
++	msg_print(MSG_DATAFLASH);
++	msg_print(MSG_SPACE);
++	msg_print(MSG_CODE);
++	msg_print(MSG_SPACE);
++	dbg_print_hex(i);
++	msg_print(MSG_AT45);
++	msg_print(MSG_DB);
++	switch(i) {
++		case AT45DB011B:
++			pn = "011B";
++			break;
++		case AT45DB021B:
++			pn = "021B";
++			break;
++		case AT45DB041B:
++			pn = "041B";
++			break;
++		case AT45DB081B:
++			pn = "081B";
++			break;
++		case AT45DB161B:
++			pn = "161B";
++			break;
++		case AT45DB321B:
++			pn = "321B";
++			break;
++		case AT45DB642:
++			pn = "642";
++			break;
++		case AT45DB1282:
++			pn = "1282";
++			break;
++		case AT45DB2562:
++			pn = "2562";
++			break;
++		case AT45DB5122:
++			pn = "5122";
++			break;
++		default:
++			pn = "????";
++			break;
++	}
++	dbg_print(pn);
++	msg_print(MSG_SPACE);
++	msg_print(MSG_DETECTED);
++	msg_print(MSG_NEWLINE);
++}
+ /*------------------------------------------------------------------------------*/
+ /* \fn    df_spi_init								*/
+ /* \brief Configure SPI								*/
+@@ -202,6 +260,42 @@ static char df_wait_ready(AT91PS_DF pDataFlash)
+ 
+ 	return FAILURE;
+ }
++
++void df_write(	AT91PS_DF pDf,
++	unsigned int addr,
++	int size, unsigned long offset)
++{
++	char rxBuffer[268];
++	int i, j;
++	i = offset;
++	if(offset == 0)
++		*((unsigned long *)(addr + 0x14)) = size;
++	while(size > 0) {
++		for(j = 0; j< ((size >268) ? 268 : size); j++)
++			rxBuffer[j] = *((unsigned char *)(addr +i+j));
++		df_page_write(pDf, rxBuffer, ((size <= AT91C_PAGE_SIZE(pDf)) ? size : AT91C_PAGE_SIZE(pDf)), i);
++		df_wait_ready(pDf);
++		i += AT91C_PAGE_SIZE(pDf);
++		size -= AT91C_PAGE_SIZE(pDf);
++	}
++#if 1
++#define LONG_VAL(addr) *((unsigned long *)(addr))
++
++	for(j=0; j < 0x1000;j+=32) {
++		df_continuous_read(pDf, (char *)rxBuffer, 32, j);
++		for(i = 0; i < 32; i+=4) {
++			if(!(i & 4)) dbg_print_hex(i+j);
++			if(LONG_VAL(0x200000+i+j) == LONG_VAL(&rxBuffer[i]))
++				msg_print(MSG_SPACE);
++			else
++				msg_print(MSG_EXCLAMATION);
++			dbg_print_hex(LONG_VAL(&rxBuffer[i]));
++			if(i & 4) msg_print(MSG_NEWLINE);
++		}
++	}
++#endif
++}
++
+ volatile	int loop;
+ /*------------------------------------------------------------------------------*/
+ /* \fn    df_read								*/
+@@ -226,14 +320,14 @@ static int df_read(
+ 			dbg_print(".");
+ 			if(--page_counter <= 0) {
+ 				page_counter = 32;
+-				dbg_print("\r\n");
++				msg_print(MSG_NEWLINE);
+ 			}
+ 			size -= SizeToRead;
+ 			addr += SizeToRead;
+ 			buffer += SizeToRead;
+ 		} else {
+ 			/* We got a timeout */
+-			dbg_print("Timeout while waiting for dataflash ready\n");
++			msg_df_print(MSG_TIMEOUT);
+ 			return FAILURE;
+ 		}
+ 	}
+@@ -246,17 +340,18 @@ static int df_read(
+ /*----------------------------------------------------------------------*/
+ static int df_download(AT91PS_DF pDf, unsigned int img_addr, unsigned int img_size, unsigned int img_dest)
+ {
+-	dbg_print(">Loading from Dataflash[");
+-	dbg_print_hex(img_addr);
+-	dbg_print("] to SDRAM[");
+-	dbg_print_hex(img_dest);
+-	dbg_print("]\r\n");
++	msg_print(MSG_LOADING);
++	msg_print(MSG_SPACE);
++	msg_print(MSG_FROM);
++	msg_print(MSG_DATAFLASH);
++	msg_print_num(img_addr);
+ 	/* read bytes in the dataflash */
+ 	if(df_read(pDf, img_addr,(unsigned char *)img_dest, img_size) == FAILURE)
+ 		return FAILURE;
+-	dbg_print("\r\n>Loading complete, [");
+-	dbg_print_hex(IMG_SIZE);
+-	dbg_print("] bytes\r\n");
++	msg_print(MSG_COMPLETE);
++	msg_print_num(img_size);
++	msg_print(MSG_BYTES);
++	msg_print(MSG_NEWLINE);
+ 	/* wait the dataflash ready status */
+ 	return df_wait_ready(pDf);
+ }
+@@ -288,7 +383,7 @@ static int df_init (AT91PS_DF pDf)
+ 	pDf->dfDescription.page_offset = 10;
+ 
+ 	dfcode = df_probe (pDf);
+-
++	msg_df_detect(dfcode);
+ 	switch (dfcode)
+ 	{
+ /*		case AT45DB011B:
+@@ -296,46 +391,41 @@ static int df_init (AT91PS_DF pDf)
+ 			pDf->dfDescription.pages_size = 264;
+ 			pDf->dfDescription.page_offset = 9;
+ 			break;
+-
++*/
+ 		case AT45DB021B:
+ 			pDf->dfDescription.pages_number = 1024;
+ 			pDf->dfDescription.pages_size = 264;
+ 			pDf->dfDescription.page_offset = 9;
+ 			break;
+-
++/*
+ 		case AT45DB041B:
+ 			pDf->dfDescription.pages_number = 2048;
+ 			pDf->dfDescription.pages_size = 264;
+ 			pDf->dfDescription.page_offset = 9;
+ 			break;
+-
++*/
+ 		case AT45DB081B:
+ 			pDf->dfDescription.pages_number = 4096;
+ 			pDf->dfDescription.pages_size = 264;
+ 			pDf->dfDescription.page_offset = 9;
+ 			break;
+-*/
+-		case AT45DB161B:
++/*		case AT45DB161B:
+ 			pDf->dfDescription.pages_number = 4096;
+ 			pDf->dfDescription.pages_size = 528;
+ 			pDf->dfDescription.page_offset = 10;
+-			dbg_print(">AT45DB161D detected\r\n");
+ 			break;
+ 
+ 		case AT45DB321B:
+ 			pDf->dfDescription.pages_number = 8192;
+ 			pDf->dfDescription.pages_size = 528;
+ 			pDf->dfDescription.page_offset = 10;
+-			dbg_print(">AT45DB321D detected\r\n");
+ 			break;
+ 
+ 		case AT45DB642:
+ 			pDf->dfDescription.pages_number = 8192;
+ 			pDf->dfDescription.pages_size = 1056;
+ 			pDf->dfDescription.page_offset = 11;
+-			dbg_print(">AT45DB642D detected\r\n");
+ 			break;
+-/*
+ 		case AT45DB1282:
+ 			pDf->dfDescription.pages_number = 16384;
+ 			pDf->dfDescription.pages_size = 1056;
+@@ -368,21 +458,22 @@ static int df_init (AT91PS_DF pDf)
+ /*------------------------------------------------------------------------------*/
+ static unsigned int df_is_boot_valid(unsigned char *buffer)
+ {
+-	int i = 3;
++    	return SUCCESS;
++}
+ 
+- 	/* Verify if the 28 first bytes of the sram correspond to ARM vectors
+-	   The sixth ARM vector contain the size of the code */
+-    	while(i < 28)
+-    	{
+-		if (i != 23)
+-		{
+-			if ((buffer[i] != 0xEA) && (buffer[i] != 0xE5) )
+-				return FAILURE;
+-		}
+-		i+=4;
+-    	}
++int burn_df(unsigned int pcs, unsigned int addr, unsigned int size, unsigned int offset)
++{
++    	AT91S_DF sDF;
++    	AT91PS_DF pDf = (AT91PS_DF)&sDF;
++    	pDf->bSemaphore = UNLOCKED;
+ 
+-    	return SUCCESS;
++    	df_spi_init(pcs, DF_CS_SETTINGS);
++
++    	if (df_init(pDf) == FAILURE)
++        	return FAILURE;
++	df_write(pDf, addr, size, offset);
++	
++	return SUCCESS;
+ }
+ 
+ /*------------------------------------------------------------------------------*/
+@@ -403,17 +494,13 @@ int load_df(unsigned int pcs, unsigned int img_addr, unsigned int img_size, unsi
+     	if (df_init(pDf) == FAILURE)
+         	return FAILURE;
+ 
+-#ifdef AT91SAM9260
+-	/* Test if a button has been pressed or not */
+-	/* Erase Page 0 to avoid infinite loop */
+-	df_recovery(pDf);
+-#endif
+-
+     	df_continuous_read(pDf, (char *)rxBuffer, 32, img_addr);
+ 	df_wait_ready(pDf);
+ 
+ 	if (df_is_boot_valid((unsigned char*)rxBuffer) == FAILURE) {
+-		dbg_print(">Invalid Boot Area...\n\r");
++		msg_print(MSG_INVALID);
++		msg_print(MSG_BOOT);
++		msg_print(MSG_NEWLINE);
+ 		return FAILURE;
+ 	}
+ 
+diff --git a/driver/debug.c b/driver/debug.c
+index e30e883..762f33e 100644
+--- a/driver/debug.c
++++ b/driver/debug.c
+@@ -106,3 +106,49 @@ void dbg_print_hex(unsigned int data)
+ }
+ 
+ 
++#ifdef CFG_DEBUG
++static char * messages[] = {
++	"detected",
++	"\r\n",
++	" ",
++	"!",
++	"dataflash",
++	"timeout",
++	"AT45",
++	"DB",
++	"invalid",
++	"boot",
++	"loading",
++	"from",
++	"code",
++	"complete",
++	"bytes",
++/*		case AT45DB011B:
++		case AT45DB021B:
++		case AT45DB041B:
++		case AT45DB081B:
++		case AT45DB161B:
++		case AT45DB321B:
++		case AT45DB642:
++		case AT45DB1282:
++		case AT45DB2562:
++		case AT45DB5122:
++*/
++};
++#endif
++
++void msg_print(int i)
++{
++#ifdef CFG_DEBUG
++	dbg_print(messages[i]);
++#endif
++}
++
++void msg_print_num(int n)
++{
++#ifdef CFG_DEBUG
++	dbg_print("[");
++	dbg_print_hex(n);
++	dbg_print("]");
++#endif
++}
+diff --git a/driver/driver.mk b/driver/driver.mk
+index 559d538..13d0e23 100644
+--- a/driver/driver.mk
++++ b/driver/driver.mk
+@@ -1,7 +1,7 @@
+ # Makefile for AT91-Bootstrap drivers directory
+ 
+ COBJS-y				+=	driver/debug.o
+-COBJS-y				+=	driver/gpio.o
++# COBJS-y				+=	driver/gpio.o
+ COBJS-y				+=	driver/pmc.o
+ COBJS-y				+=	driver/sdramc.o
+ COBJS-y				+=	driver/string.o
+diff --git a/driver/gpio.c b/driver/gpio.c
+index 9f17305..752b7c1 100644
+--- a/driver/gpio.c
++++ b/driver/gpio.c
+@@ -208,6 +208,7 @@ int pio_get_value(unsigned pin)
+ 	return (pdsr & mask) != 0;
+ }
+ 
++#if 0
+ /*------------------------------------------------------------------------------*/
+ /* \fn    pio_device_pio_setup							*/
+ /* \brief Configure PIO in periph mode according to the platform informations	*/
+@@ -248,3 +249,4 @@ int pio_setup (const struct pio_desc *pio_desc)
+         }
+         return pin;
+ }
++#endif
+\ No newline at end of file
+diff --git a/driver/nandflash.c b/driver/nandflash.c
+index b4e3e70..081fa69 100644
+--- a/driver/nandflash.c
++++ b/driver/nandflash.c
+@@ -126,6 +126,9 @@ static PSNandInitInfo AT91F_NandReadID(void)
+ 	NAND_DISABLE_CE();
+ 
+ 	uChipID = (bManufacturerID << 8) | bDeviceID;
++	dbg_print("NAND id:");
++	dbg_print_hex(uChipID);
++	dbg_print("\r\n");
+ 	
+ 	/* Search in NandFlash_InitInfo[] */
+ 	while (NandFlash_InitInfo[i].uNandID != 0)
+@@ -398,7 +401,7 @@ int load_nandflash(unsigned int img_addr, unsigned int img_size, unsigned int im
+ 	if (!pNandInitInfo)
+  	{
+ #ifdef CFG_DEBUG	
+-	   	dbg_print("\n\r-E- No NandFlash detected !!!\n\r");
++	   	dbg_print("\n\r-E- No NandFlash\n\r");
+ #endif
+ 		return -1;
+     	}
+diff --git a/driver/sdramc.c b/driver/sdramc.c
+index 3e5715b..9940f67 100644
+--- a/driver/sdramc.c
++++ b/driver/sdramc.c
+@@ -73,29 +73,10 @@ int sdram_init(unsigned int sdramc_cr, unsigned int sdramc_tr)
+ 
+ 	for (i =0; i< 10000;i++);
+ 
+-	write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 1st CBR
+-	writel(0x00000001, AT91C_SDRAM+4);						// Perform CBR
+-
+-	write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 2 CBR
+-	writel(0x00000002, AT91C_SDRAM+8);						// Perform CBR
+-
+-	write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 3 CBR
+-	writel(0x00000003, AT91C_SDRAM+0xc);					// Perform CBR
+-
+-	write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 4 CBR
+-	writel(0x00000004, AT91C_SDRAM+0x10);					// Perform CBR
+-
+-	write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 5 CBR
+-	writel(0x00000005, AT91C_SDRAM+0x14);					// Perform CBR
+-
+-	write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 6 CBR
+-	writel(0x00000006, AT91C_SDRAM+0x18);					// Perform CBR
+-
+-	write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 7 CBR
+-	writel(0x00000007, AT91C_SDRAM+0x1C);					// Perform CBR
+-
+-	write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 8 CBR
+-	writel(0x00000008, AT91C_SDRAM+0x20);					// Perform CBR
++	for (i = 0; i < 8; i++) {
++		write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);  // 8 x CBR
++		writel(0x00000001 + i, AT91C_SDRAM + 4 + 4 * i);						// Perform CBR
++	}
+ 
+ 	write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD);		// Set LMR operation
+ 	writel(0xcafedede, AT91C_SDRAM+0x24);					// Perform LMR burst=1, lat=2
+diff --git a/include/debug.h b/include/debug.h
+index 686294a..be7fe89 100644
+--- a/include/debug.h
++++ b/include/debug.h
+@@ -47,4 +47,22 @@ extern void dbg_init(unsigned int);
+ extern void dbg_print(const char *ptr);
+ extern void dbg_print_hex(unsigned int data);
+ 
++#define MSG_DETECTED 0
++#define MSG_NEWLINE 1
++#define MSG_SPACE 2
++#define MSG_EXCLAMATION 3
++#define MSG_DATAFLASH 4
++#define MSG_TIMEOUT 5
++#define MSG_AT45 6
++#define MSG_DB 7
++#define MSG_INVALID 8
++#define MSG_BOOT 9
++#define MSG_LOADING 10
++#define MSG_FROM 11
++#define MSG_CODE 12
++#define MSG_COMPLETE 13
++#define MSG_BYTES 14
++
++void msg_print(int i);
++void msg_print_num(int n);
+ #endif /*_DEBUG_H_*/
+diff --git a/include/nand_ids.h b/include/nand_ids.h
+index 5aa8753..c659b07 100644
+--- a/include/nand_ids.h
++++ b/include/nand_ids.h
+@@ -42,6 +42,7 @@
+ /* Supported NandFlash devices */
+ static struct SNandInitInfo NandFlash_InitInfo[] = {
+ 	{0xecda, 0x800, 0x20000, 0x800, 0x40, 0x0, "Samsung K9F2G08U0M 256Mb\0"},
++	{0xecaa, 0x800, 0x20000, 0x800, 0x40, 0x0, "Samsung K9F2G08U0A 256Mb\0"},
+ 	{0x2cca, 0x800, 0x20000, 0x800, 0x40, 0x1, "Micron MT29F2G16AAB 256Mb\0"},	
+ 	{0,}
+ };
+diff --git a/main.c b/main.c
+index ed750c2..e55e2fc 100644
+--- a/main.c
++++ b/main.c
+@@ -41,18 +41,149 @@
+ #include "include/flash.h"
+ #include "include/nandflash.h"
+ 
+-int test(void)
+-{
+-
+-}
+ /*------------------------------------------------------------------------------*/
+ /* Function Name       : main							*/
+ /* Object              : Main function						*/
+ /* Input Parameters    : none							*/
+ /* Output Parameters   : True							*/
+ /*------------------------------------------------------------------------------*/
++static unsigned long rand_next = 1;
++
++unsigned long stupid_rand(void)
++{
++	rand_next = rand_next * 1103515245 + 12345;
++	return (rand_next/131072) % 65536;
++}
++void stupid_srand(unsigned long seed)
++{
++	rand_next = seed;
++}
++
++unsigned long il, ij, k;
++unsigned char tbuf[128];
++void writeall()
++{
++    burn_df(AT91C_SPI_PCS_DATAFLASH, 0x200000, 0x1000, 0);
++    burn_df(AT91C_SPI_PCS_DATAFLASH, JUMP_ADDR, IMG_SIZE, IMG_ADDRESS);
++    while(1);
++}
++
++void dbg_cr(void)
++{
++	dbg_print("\r\n");
++}
++
++void dbg_printnum(char * s, unsigned long no)
++{
++	dbg_print(s);
++	dbg_print(" ");
++	dbg_print_hex(no);
++}
++
++void dbg_printnum_cr(char * s, unsigned long no)
++{
++	dbg_printnum(s, no);
++	dbg_cr();
++}
++void dbg_print_cr(char * s)
++{
++	dbg_print(s);
++	dbg_cr();
++}
++
++void test_pass(int pass, int mode, unsigned long start, unsigned long size, unsigned long step)
++{
++	unsigned long k, bad;
++	k = 0;
++	bad = 0;
++	stupid_srand(6);
++#if 0
++	if(pass == 7) {
++		unsigned long r1, j, l, *a1, *a2;
++		r1 = stupid_rand();
++		for(j = 0; (1 << j) < size; j++) {
++			a1 = start + j;
++			for(l = 1; l < size; l <<= 1) {
++				a2 = start + l;
++				if(j != l) {
++					*a1 = r1;
++					*a2 = r1 + 1;
++					for(k=0; k<100000; k++);
++					if(*a1 != r1 ||	*a2 != (r1 + 1) || *a1 == *a2) {
++							dbg_printnum("bad locations:", a2);
++							dbg_printnum_cr(" ", a1);
++							bad++;
++						}
++				}
++			}
++		}
++	}
++	else 
++#endif
++	for (ij = 0; ij < size; ij+=step) {
++		unsigned long wval = 0;
++		unsigned long rval;
++		unsigned long tmp;
++		unsigned long randval;
++		for(il=(start+ij); il<(start+step+ij);il+=4) {
++#if 1
++			randval = stupid_rand() & 0xffff;
++#endif
++			switch(pass)
++			{
++				case 0:
++					wval |= 0x1 << (k & 0x1f);
++					break;
++				case 1:
++					wval = (0x1 << (k & 0x1f)) | 1;
++					break;
++				case 2:
++					wval = 0x1 << (k & 0x1f);
++					break;
++				case 3:
++					wval = 0;
++					break;
++				case 4:
++					wval = 0xffffffff;
++					break;
++#if 1
++				case 5: {
++						wval = (randval << 16) + randval;
++					}
++					break;
++#endif
++			}
++			if(!(mode & 1)) {
++				*((unsigned long *)il) = wval;
++			}
++			else if(mode & 1) {
++				rval = (mode & 2) ? *((unsigned long *)il) & 0xffff : ((mode & 4) ? *((unsigned long *)il) & 0xffff0000 : *((unsigned long *)il));
++				tmp = wval;
++				wval = (mode & 2) ? wval & 0xffff: ((mode & 4) ? wval & 0xffff0000: wval);
++				if(wval != rval) {
++					dbg_print_hex(il);
++					dbg_printnum(": rd", rval);
++					dbg_printnum_cr("!= wr", wval);
++					bad++;
++				}
++				wval = tmp;
++			}
++			k++;
++			if(k > 95) {k = k & 95; if(pass == 0) wval = 0;}
++		}
++	}
++	if(mode & 1) {
++		dbg_printnum_cr("bad locations:", bad);
++	}
++	dbg_cr();
++}
++
+ int main(void)
+ {
++#undef LONG_TEST
++#ifdef LONG_TEST
++	int g, h, i;
++#endif
+ 
+ /* ================== 1st step: Hardware Initialization ================= */
+ 	/* Performs the hardware initialization */
+@@ -60,6 +191,27 @@ int main(void)
+ 	hw_init();
+ #endif
+ 
++#ifdef CFG_SDRAM
++#ifdef LONG_TEST
++	for(h = 0; h < 100; h++) {
++		dbg_printnum_cr("pass", h);
++		for(g = 0; g < 6; g++) {
++			dbg_printnum_cr("test", g);
++			test_pass(g, 0, 0x20000000, 0x2000000, 0x80);
++			for(i=0;i < 100000;i++);
++			dbg_print_cr("both chips");
++			test_pass(g, 1, 0x20000000, 0x2000000, 0x80);
++			dbg_print_cr("low chip");
++			test_pass(g, 3, 0x20000000, 0x2000000, 0x80);
++			dbg_print_cr("high chip");
++			test_pass(g, 5, 0x20000000, 0x2000000, 0x80);
++		}
++	}
++	dbg_print_cr("END");
++	while(1);
++#endif
++#endif
++
+ /* ==================== 2nd step: Load from media ==================== */
+ 	/* Load from Dataflash in RAM */
+ #ifdef CFG_DATAFLASH
+@@ -72,10 +224,10 @@ int main(void)
+ 
+ 	/* Load from Nandflash in RAM */
+ #ifdef CFG_NANDFLASH
+-	load_nandflash(IMG_ADDRESS, IMG_SIZE, JUMP_ADDR);
+-	dbg_print(">NANDflash ready\r\n");
++	//load_nandflash(IMG_ADDRESS, IMG_SIZE, JUMP_ADDR);
++	load_nandflash(IMG_ADDRESS, 128, tbuf);
+ #endif
+-
++#if 0
+ /* ==================== 3rd step:  Process the Image =================== */
+ 	/* Uncompress the image */
+ #ifdef GUNZIP
+@@ -95,5 +247,6 @@ int main(void)
+ 	dbg_print("]\r\n");
+ 	{ volatile unsigned int loop; for(loop = 200000; loop > 0; loop--);}
+ 	/* Jump to the Image Address */
++#endif
+ 	return JUMP_ADDR;
+ }
+-- 
+1.5.6.5
+
diff --git a/recipes/at91bootstrap/files/0002-Making-image-directly-flashable.patch b/recipes/at91bootstrap/files/0002-Making-image-directly-flashable.patch
new file mode 100644
index 0000000000..698baec60b
--- /dev/null
+++ b/recipes/at91bootstrap/files/0002-Making-image-directly-flashable.patch
@@ -0,0 +1,39 @@
+From 482b2b7601a17264129aa50e77ba2ad51b1d2217 Mon Sep 17 00:00:00 2001
+From: Sergey Lapin <slapin@slind.org>
+Date: Sat, 27 Sep 2008 01:28:19 +0400
+Subject: [PATCH] Making image directly flashable
+
+
+Signed-off-by: Sergey Lapin <slapin@ossfans.org>
+---
+ fixboot.py |   18 ++++++++++++++++++
+ 1 files changed, 18 insertions(+), 0 deletions(-)
+ create mode 100755 fixboot.py
+
+diff --git a/fixboot.py b/fixboot.py
+new file mode 100755
+index 0000000..e4c604e
+--- /dev/null
++++ b/fixboot.py
+@@ -0,0 +1,18 @@
++#!/usr/bin/env python
++
++import struct, sys
++
++#print sys.argv[1]
++
++fd = open(sys.argv[1], "r")
++
++line = fd.read()
++fd.close()
++
++# print len(line)
++
++vec = struct.pack("<I", len(line))
++
++fd = open(sys.argv[1]+".fixboot", "w")
++fd.write(line[0:20]+vec+line[24:])
++fd.close()
+-- 
+1.5.6.5
+
diff --git a/recipes/at91bootstrap/files/0003-AFEB9260-board-support.patch b/recipes/at91bootstrap/files/0003-AFEB9260-board-support.patch
new file mode 100644
index 0000000000..4201eb86f6
--- /dev/null
+++ b/recipes/at91bootstrap/files/0003-AFEB9260-board-support.patch
@@ -0,0 +1,665 @@
+From aad8fd3187b1d3549ea1cdcbcb7ddb4997da108c Mon Sep 17 00:00:00 2001
+From: Sergey Lapin <slapin@slind.org>
+Date: Sat, 27 Sep 2008 01:34:12 +0400
+Subject: [PATCH] AFEB9260 board support
+
+
+Signed-off-by: Sergey Lapin <slapin@ossfans.org>
+---
+ Makefile                              |   19 +++
+ board/afeb9260/afeb9260.c             |  240 +++++++++++++++++++++++++++++++++
+ board/afeb9260/afeb9260.mk            |    8 +
+ board/afeb9260/dataflash/afeb9260.h   |  127 +++++++++++++++++
+ board/afeb9260/nandflash/afeb9260ek.h |  151 +++++++++++++++++++++
+ board/afeb9260/pll.h                  |   35 +++++
+ include/part.h                        |   10 ++
+ 7 files changed, 590 insertions(+), 0 deletions(-)
+ create mode 100644 board/afeb9260/afeb9260.c
+ create mode 100644 board/afeb9260/afeb9260.mk
+ create mode 100644 board/afeb9260/dataflash/afeb9260.h
+ create mode 100644 board/afeb9260/nandflash/afeb9260ek.h
+ create mode 100644 board/afeb9260/pll.h
+
+diff --git a/Makefile b/Makefile
+index 475784e..805de99 100644
+--- a/Makefile
++++ b/Makefile
+@@ -142,6 +142,25 @@ at91sam9263ek_defconfig:	clean
+ 	echo	SPI_BOOT=SPI_BOOT_CS0		>>	.config
+ 	echo	SPI_CLK=$(CONFIG_SPI_CLK)	>>	.config
+ 
++afeb9260_defconfig:	clean
++	echo	BOARDNAME=afeb9260		>	.config
++	echo	BOARD=afeb9260			>>	.config
++	echo	PROJECT=$(MEMORY)		>>	.config
++	echo	CONFIG_$(CFG_MEMORY)=y		>>	.config
++	echo	SPI_MODE=$(CONFIG_SPI_MODE)	>>	.config
++	echo	SPI_BOOT=SPI_BOOT_CS1		>>	.config
++	echo	SPI_CLK=$(CONFIG_SPI_CLK)	>>	.config
++
++afeb9260-133_defconfig:	clean
++	echo	BOARDNAME=afeb9260-133		>	.config
++	echo	BOARD=afeb9260-133		>>	.config
++	echo	PROJECT=$(MEMORY)		>>	.config
++	echo	CONFIG_$(CFG_MEMORY)=y		>>	.config
++	echo	SPI_MODE=$(CONFIG_SPI_MODE)	>>	.config
++	echo	SPI_BOOT=SPI_BOOT_CS1		>>	.config
++	echo	SPI_CLK=$(CONFIG_SPI_CLK)	>>	.config
++
++
+ ../buildroot:
+ 	(cd .. ; svn co svn://uclibc.org/trunk/buildroot)
+ 
+diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c
+new file mode 100644
+index 0000000..81c0919
+--- /dev/null
++++ b/board/afeb9260/afeb9260.c
+@@ -0,0 +1,240 @@
++/* ----------------------------------------------------------------------------
++ *         ATMEL Microcontroller Software Support  -  ROUSSET  -
++ * ----------------------------------------------------------------------------
++ * Copyright (c) 2006, Atmel Corporation
++
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the disclaiimer below.
++ *
++ * - Redistributions in binary form must reproduce the above copyright notice,
++ * this list of conditions and the disclaimer below in the documentation and/or
++ * other materials provided with the distribution.
++ *
++ * Atmel's name may not be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * ----------------------------------------------------------------------------
++ * File Name           : at91sam9260ek.c
++ * Object              :
++ * Creation            : NLe Jul 13th 2006
++ * ODi Nov 9th         : dstp #3507 "Bad PIO descriptors in at91samxxxek.c"
++ *-----------------------------------------------------------------------------
++ */
++#include "../../include/part.h"
++#include "../../include/gpio.h"
++#include "../../include/pmc.h"
++#include "../../include/debug.h"
++#include "../../include/sdramc.h"
++#include "../../include/main.h"
++#ifdef CFG_NANDFLASH
++#include "../../include/nandflash.h"
++#endif
++#ifdef CFG_DATAFLASH
++#include "../../include/dataflash.h"
++#endif
++#ifdef CFG_FLASH
++#include "../../include/flash.h"
++#endif
++
++/* We init NAND regardless of whatever */
++/*------------------------------------------------------------------------------*/
++/* \fn    nandflash_hw_init							*/
++/* \brief NandFlash HW init							*/
++/*------------------------------------------------------------------------------*/
++void nandflash_hw_init(void)
++{
++	/* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */
++	writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM, AT91C_BASE_CCFG + CCFG_EBICSA);
++		    
++	/* Configure SMC CS3 */
++ 	writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
++  	writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
++	writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE)						, AT91C_BASE_SMC + SMC_CYCLE3);
++	writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | 
++  		AT91C_SMC_DBW_WIDTH_EIGTH_BITS | AT91C_SM_TDF)						, AT91C_BASE_SMC + SMC_CTRL3);
++
++	/* Configure the PIO controller */
++	writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC);
++
++	writel(1 << 13, AT91C_BASE_PIOC + PIO_IFDR(0));
++	writel(1 << 13, AT91C_BASE_PIOC + PIO_PPUER(0));
++	writel(1 << 13, AT91C_BASE_PIOC + PIO_ODR(0));
++	writel(1 << 14, AT91C_BASE_PIOC + PIO_CODR(0));
++	writel(1 << 14, AT91C_BASE_PIOC + PIO_MDDR(0));
++	writel(1 << 14, AT91C_BASE_PIOC + PIO_PPUDR(0));
++	writel(1 << 14, AT91C_BASE_PIOC + PIO_OER(0));
++	writel(3 << 13, AT91C_BASE_PIOC + PIO_IDR(0));
++	writel(3 << 13, AT91C_BASE_PIOC + PIO_PER(0));
++}
++
++
++#ifdef CFG_HW_INIT
++/*----------------------------------------------------------------------------*/
++/* \fn    hw_init							      */
++/* \brief This function performs very low level HW initialization	      */
++/* This function is invoked as soon as possible during the c_startup	      */
++/* The bss segment must be initialized					      */
++/*----------------------------------------------------------------------------*/
++void hw_init(void)
++{
++	/* Disable watchdog */
++	writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
++
++	/* At this stage the main oscillator is supposed to be enabled
++	 * PCK = MCK = MOSC */
++
++	/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
++	pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
++
++	/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */
++	pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
++
++	/* Configure PLLB */
++	pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
++
++	/* Configure the PIO controller */
++	writel(3 << 14, AT91C_BASE_PIOB + PIO_ASR(0));
++	writel(3 << 14, AT91C_BASE_PIOB + PIO_PDR(0));
++
++#ifdef CFG_DEBUG
++	/* Enable Debug messages on the DBGU */
++	dbg_init(BAUDRATE(MASTER_CLOCK, 115200));
++
++	dbg_print("AT91 bootstrap loading from 0x8400\n\r");
++#endif /* CFG_DEBUG */
++
++#ifdef CFG_SDRAM
++	/* Initialize the matrix */
++	writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_BASE_CCFG + CCFG_EBICSA);
++
++	/* Configure SDRAM Controller */
++
++#define HYNIX
++
++//#define MICRON
++#ifdef MICRON
++#define MICRON_REFRESH 1420 /* 15.625 us / 11 ns @ 180 Mhz*/
++	sdram_init(	AT91C_SDRAMC_NC_9  |
++				AT91C_SDRAMC_NR_12 |
++				AT91C_SDRAMC_CAS_2 |
++				AT91C_SDRAMC_NB_4_BANKS |
++				AT91C_SDRAMC_DBW_32_BITS |
++				AT91C_SDRAMC_TWR_2 | // 1 CLK+7ns
++				AT91C_SDRAMC_TRC_7 | // 60 ns
++				AT91C_SDRAMC_TRP_3 | // 15 ns
++				AT91C_SDRAMC_TRCD_3 | // 15 ns
++				AT91C_SDRAMC_TRAS_7 | // 37-120 ns
++				AT91C_SDRAMC_TXSR_7, /* 67ns */ /* Control Register */
++				/* 600 700 735 */ MICRON_REFRESH /* 740 1536*/ );	/* Refresh Timer Register */
++
++#endif
++/* 
++HY57V561620BT-H
++     *CAS lat		*tRCD		*tRAS		*tRC		*tRP		tAC	tOH
++133	2		2		6		8		2		5.4ns	2.7ns
++125	3		3		6		9		3		6ns	3ns
++100	2		2		5		7		2		6ns	3ns
++
++*/
++#ifdef HYNIX
++#if defined(PLLA_180MHz)
++/* CLK= 11ns */
++/* TWR = tDPL = 2 2CLK always */
++/* TRC = tRC = 65ns = 6 clk */
++/* TRP = tRP = 20ns = 2 clk */
++/* TRCD = tRCD = 20ns = 2 clk */
++/* TRAS = tRAS = 45ns = 5 clk */
++/* TXSR = tRRC = 65ns = 6 clk */
++
++	sdram_init(	AT91C_SDRAMC_NC_9  |
++				AT91C_SDRAMC_NR_13 |
++				AT91C_SDRAMC_CAS_2 |
++				AT91C_SDRAMC_NB_4_BANKS |
++				AT91C_SDRAMC_DBW_32_BITS |
++				AT91C_SDRAMC_TWR_2 |
++				AT91C_SDRAMC_TRC_6 | /* *7 */
++				AT91C_SDRAMC_TRP_2 |
++				AT91C_SDRAMC_TRCD_2 |
++				AT91C_SDRAMC_TRAS_5 | /* *5 */
++				AT91C_SDRAMC_TXSR_6, /* *8 */	/* Control Register */
++				710);	/* Refresh Timer Register */
++
++#elif defined(PLLA_120MHz)
++/* CLK= 16ns, MCLK=60MHz */
++/* TWR = tDPL = 2 2CLK always */
++/* TRC = tRC = 65ns = 4 clk */
++/* TRP = tRP = 20ns = 2 clk */
++/* TRCD = tRCD = 20ns = 2 clk */
++/* TRAS = tRAS = 45ns = 3 clk */
++/* TXSR = tRRC = 65ns = 4 clk */
++
++	sdram_init(	AT91C_SDRAMC_NC_9  |
++				AT91C_SDRAMC_NR_13 |
++				AT91C_SDRAMC_CAS_2 |
++				AT91C_SDRAMC_NB_4_BANKS |
++				AT91C_SDRAMC_DBW_32_BITS |
++				AT91C_SDRAMC_TWR_2 |
++				AT91C_SDRAMC_TRC_4 |
++				AT91C_SDRAMC_TRP_2 |
++				AT91C_SDRAMC_TRCD_2 |
++				AT91C_SDRAMC_TRAS_3 | /* *5 */
++				AT91C_SDRAMC_TXSR_4, /* *8 */	/* Control Register */
++				1032);	/* Refresh Timer Register */
++#else
++#error define PLLA180MHz
++#endif
++#endif /* HYNIX */
++#endif /* CFG_SDRAM */
++
++#ifdef	CFG_FLASH
++	flash_hw_init();
++#endif
++	nandflash_hw_init();
++}
++#endif /* CFG_HW_INIT */
++
++#ifdef CFG_SDRAM
++/*------------------------------------------------------------------------------*/
++/* \fn    sdramc_hw_init							*/
++/* \brief This function performs SDRAMC HW initialization			*/
++/*------------------------------------------------------------------------------*/
++void sdramc_hw_init(void)
++{
++	writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
++	writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
++
++}
++#endif /* CFG_SDRAM */
++
++#ifdef CFG_DATAFLASH
++
++/*------------------------------------------------------------------------------*/
++/* \fn    df_hw_init								*/
++/* \brief This function performs DataFlash HW initialization			*/
++/*------------------------------------------------------------------------------*/
++void df_hw_init(void)
++{
++	writel(0xf, 0xfffff444);
++	writel(0xf, 0xfffff460);
++	writel(0xf, 0xfffff470);
++	writel(0xf, 0xfffff404);
++	writel(1 << 11, AT91C_BASE_PIOC + PIO_BSR(0));
++	writel(1 << 11, AT91C_BASE_PIOC + PIO_PDR(0));
++}
++#endif /* CFG_DATAFLASH */
++
+diff --git a/board/afeb9260/afeb9260.mk b/board/afeb9260/afeb9260.mk
+new file mode 100644
+index 0000000..88c2f64
+--- /dev/null
++++ b/board/afeb9260/afeb9260.mk
+@@ -0,0 +1,8 @@
++# Target name (case sensitive!!!)
++TARGET=AFEB9260
++# Board name (case sensitive!!!)
++BOARD=afeb9260
++# Link Address and Top_of_Memory
++LINK_ADDR=0x200000
++TOP_OF_MEMORY=0x301000
++
+diff --git a/board/afeb9260/dataflash/afeb9260.h b/board/afeb9260/dataflash/afeb9260.h
+new file mode 100644
+index 0000000..8e60faa
+--- /dev/null
++++ b/board/afeb9260/dataflash/afeb9260.h
+@@ -0,0 +1,127 @@
++/* ----------------------------------------------------------------------------
++ *         ATMEL Microcontroller Software Support  -  ROUSSET  -
++ * ----------------------------------------------------------------------------
++ * Copyright (c) 2006, Atmel Corporation
++
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the disclaiimer below.
++ *
++ * - Redistributions in binary form must reproduce the above copyright notice,
++ * this list of conditions and the disclaimer below in the documentation and/or
++ * other materials provided with the distribution.
++ *
++ * Atmel's name may not be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * ----------------------------------------------------------------------------
++ * File Name           : at91sam9260ek.h
++ * Object              :
++ * Creation            : NLe Jul 13th 2006
++ *-----------------------------------------------------------------------------
++ */
++#ifndef _AFEB9260_H
++#define _AFEB9260_H
++#include	"spi.h"
++#include 	"pll.h"
++
++/* ******************************************************************* */
++/* DataFlash Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define AT91C_BASE_SPI	AT91C_BASE_SPI0
++#define AT91C_ID_SPI	AT91C_ID_SPI0
++
++/* SPI CLOCK */
++#define AT91C_SPI_CLK 		 5000000
++/* AC characteristics */
++/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */
++#define DATAFLASH_TCSS		(0x1a << 16)	/* 250ns min (tCSS) <=> 12/48000000 = 250ns */
++#define DATAFLASH_TCHS		(0x1 << 24)	/* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */
++
++#define DF_CS_SETTINGS 		((SPI_MODE) | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8))
++
++
++/* ******************************************************************* */
++/* BootStrap Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define MACH_TYPE       	0x44B		/* AT91SAM9260-EK */
++
++#define IMG_ADDRESS 		0x8400		/* Image Address in DataFlash */
++
++#if	defined(IMG_SIZE)
++#warning			"IMG_SIZE redefined"
++#else
++#define	IMG_SIZE		0x39000	/* Image Size in DataFlash    */
++#endif
++
++#if	defined(JUMP_ADDR)
++#warning			"JUMP_ADDR redefined"
++#else
++#define JUMP_ADDR		0x21F00000	/* Final Jump Address 	      */
++#endif
++
++/* ******************************************************************* */
++/* NandFlash Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define AT91C_SMARTMEDIA_BASE	0x40000000
++
++#define AT91_SMART_MEDIA_ALE    (1 << 21)	/* our ALE is AD21 */
++#define AT91_SMART_MEDIA_CLE    (1 << 22)	/* our CLE is AD22 */
++
++#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0)
++#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0)
++
++#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13))
++
++
++/* ******************************************************************** */
++/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/
++/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000.			*/
++/* Please refer to SMC section in AT91SAM9261 datasheet to learn how 	*/
++/* to generate these values. 						*/
++/* ******************************************************************** */
++
++#define AT91C_SM_NWE_SETUP	(2 << 0)
++#define AT91C_SM_NCS_WR_SETUP	(2 << 8)
++#define AT91C_SM_NRD_SETUP	(2 << 16)
++#define AT91C_SM_NCS_RD_SETUP	(2 << 24)
++  
++#define AT91C_SM_NWE_PULSE 	(4 << 0)
++#define AT91C_SM_NCS_WR_PULSE	(4 << 8)
++#define AT91C_SM_NRD_PULSE	(4 << 16)
++#define AT91C_SM_NCS_RD_PULSE	(4 << 24)
++  
++#define AT91C_SM_NWE_CYCLE 	(8 << 0)
++#define AT91C_SM_NRD_CYCLE	(8 << 16)
++
++#define AT91C_SM_TDF	        (2 << 16)
++
++
++
++/* ******************************************************************* */
++/* Application Settings                                                */
++/* ******************************************************************* */
++#define CFG_DEBUG
++#define CFG_DATAFLASH
++#define	CFG_SDRAM
++#define	CFG_HW_INIT
++
++
++#endif	/* _AT91SAM9260EK_H */
+diff --git a/board/afeb9260/nandflash/afeb9260ek.h b/board/afeb9260/nandflash/afeb9260ek.h
+new file mode 100644
+index 0000000..752ae0a
+--- /dev/null
++++ b/board/afeb9260/nandflash/afeb9260ek.h
+@@ -0,0 +1,151 @@
++/* ----------------------------------------------------------------------------
++ *         ATMEL Microcontroller Software Support  -  ROUSSET  -
++ * ----------------------------------------------------------------------------
++ * Copyright (c) 2006, Atmel Corporation
++
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the disclaimer below.
++ *
++ * - Redistributions in binary form must reproduce the above copyright notice,
++ * this list of conditions and the disclaimer below in the documentation and/or
++ * other materials provided with the distribution.
++ *
++ * Atmel's name may not be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * ----------------------------------------------------------------------------
++ * File Name           : at91sam9260ek.h
++ * Object              :
++ * Creation            : NLe Sep 28th 2006
++ *-----------------------------------------------------------------------------
++ */
++#ifndef _AFEB9260_H
++#define _AFEB9260_H
++#include	"spi.h"
++#include 	"pll.h"
++
++/* ******************************************************************* */
++/* DataFlash Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define AT91C_BASE_SPI	AT91C_BASE_SPI0
++#define AT91C_ID_SPI	AT91C_ID_SPI0
++
++/* SPI CLOCK */
++#define AT91C_SPI_CLK 		 5000000
++/* AC characteristics */
++/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */
++#define DATAFLASH_TCSS		(0x1a << 16)	/* 250ns min (tCSS) <=> 12/48000000 = 250ns */
++#define DATAFLASH_TCHS		(0x1 << 24)	/* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */
++
++#define DF_CS_SETTINGS 		((SPI_MODE) | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8))
++
++
++/* ******************************************************************* */
++/* NandFlash Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define AT91C_SMARTMEDIA_BASE	0x40000000
++
++#define AT91_SMART_MEDIA_ALE    (1 << 21)	/* our ALE is AD21 */
++#define AT91_SMART_MEDIA_CLE    (1 << 22)	/* our CLE is AD22 */
++
++#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0)
++#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0)
++
++#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13))
++
++
++/* ******************************************************************** */
++/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/
++/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000.			*/
++/* Please refer to SMC section in AT91SAM9261 datasheet to learn how 	*/
++/* to generate these values. 						*/
++/* ******************************************************************** */
++
++#define AT91C_SM_NWE_SETUP	(2 << 0)
++#define AT91C_SM_NCS_WR_SETUP	(2 << 8)
++#define AT91C_SM_NRD_SETUP	(2 << 16)
++#define AT91C_SM_NCS_RD_SETUP	(2 << 24)
++  
++#define AT91C_SM_NWE_PULSE 	(4 << 0)
++#define AT91C_SM_NCS_WR_PULSE	(4 << 8)
++#define AT91C_SM_NRD_PULSE	(4 << 16)
++#define AT91C_SM_NCS_RD_PULSE	(4 << 24)
++  
++#define AT91C_SM_NWE_CYCLE 	(8 << 0)
++#define AT91C_SM_NRD_CYCLE	(8 << 16)
++
++#define AT91C_SM_TDF	        (2 << 16)
++
++
++/* ******************************************************************** */
++/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/
++/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000.			*/
++/* Please refer to SMC section in AT91SAM9261 datasheet to learn how 	*/
++/* to generate these values. 						*/
++/* ******************************************************************** */
++/*#define AT91C_SM_NWE_SETUP	(0 << 0)
++#define AT91C_SM_NCS_WR_SETUP	(0 << 8)
++#define AT91C_SM_NRD_SETUP	(0 << 16)
++#define AT91C_SM_NCS_RD_SETUP	(0 << 24)
++  
++#define AT91C_SM_NWE_PULSE 	(2 << 0)
++#define AT91C_SM_NCS_WR_PULSE	(3 << 8)
++#define AT91C_SM_NRD_PULSE	(2 << 16)
++#define AT91C_SM_NCS_RD_PULSE	(3 << 24)
++  
++#define AT91C_SM_NWE_CYCLE 	(3 << 0)
++#define AT91C_SM_NRD_CYCLE	(3 << 16)
++
++#define AT91C_SM_TDF	        (1 << 16)
++*/
++
++/* ******************************************************************* */
++/* BootStrap Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define MACH_TYPE      		0x44B       	/* AT91SAM9260-EK */
++
++#define IMG_ADDRESS 		0x20000		/* Image Address in NandFlash */
++
++#if	defined(IMG_SIZE)
++#warning			"IMG_SIZE redefined"
++#else
++#define	IMG_SIZE		0x30000		/* Image Size in NandFlash    */
++#endif
++
++#if	defined(JUMP_ADDR)
++#warning			"JUMP_ADDR redefined"
++#else
++#define JUMP_ADDR		0x23F00000	/* Final Jump Address 	      */
++#endif
++
++/* ******************************************************************* */
++/* Application Settings                                                */
++/* ******************************************************************* */
++#define CFG_DEBUG
++#undef CFG_DATAFLASH
++
++#define CFG_NANDFLASH
++#undef	NANDFLASH_SMALL_BLOCKS	/* NANDFLASH_LARGE_BLOCKS used instead */
++
++#define CFG_HW_INIT
++#define CFG_SDRAM
++
++#endif	/* _AT91SAM9260EK_H */
+diff --git a/board/afeb9260/pll.h b/board/afeb9260/pll.h
+new file mode 100644
+index 0000000..6d20299
+--- /dev/null
++++ b/board/afeb9260/pll.h
+@@ -0,0 +1,35 @@
++/* ******************************************************************* */
++/* PMC Settings                                                        */
++/*                                                                     */
++/* The main oscillator is enabled as soon as possible in the c_startup */
++/* and MCK is switched on the main oscillator.                         */
++/* PLL initialization is done later in the hw_init() function          */
++/* ******************************************************************* */
++#define PLL_LOCK_TIMEOUT	1000000
++
++#define PLLA_180MHz
++
++#ifdef PLLA_200MHz
++#define PLLA_SETTINGS	0x2060BF09
++#define MASTER_CLOCK		(198656000/2)
++#endif
++
++#ifdef PLLA_180MHz
++#define PLLA_SETTINGS	0x2125BF1E /* 180MHz */
++#define MASTER_CLOCK		(179999198/2) /* 180MHz MCK=90MHz */
++#endif
++
++#ifdef PLLA_120MHz
++//#define PLLA_SETTINGS	0x2125BF2d /* 120MHz */
++//#define MASTER_CLOCK		(119999322) /* 120MHz MCK=60MHz*/
++#define PLLA_SETTINGS	0x2125BF2d /* 120MHz */
++#define MASTER_CLOCK		(119999465/2) /* 120MHz MCK=60MHz*/
++#endif
++
++#if !defined(PLLA_180MHz) && !defined(PLLA_120MHz)
++#error Define PLLA frequency
++#endif
++#define PLLB_SETTINGS	0x10483F0E
++
++/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */
++#define MCKR_SETTINGS	(AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2)
+diff --git a/include/part.h b/include/part.h
+index ec717d6..48e41e1 100644
+--- a/include/part.h
++++ b/include/part.h
+@@ -52,4 +52,14 @@
+ #include "at91sam9263ek.h"
+ #endif
+ 
++#ifdef AFEB9260
++#include "AT91SAM9260_inc.h"
++#include "afeb9260.h"
++#endif
++
++#ifdef AFEB9260_133
++#include "AT91SAM9260_inc.h"
++#include "afeb9260-133.h"
++#endif
++
+ #endif /* _PART_H */
+-- 
+1.5.6.5
+
diff --git a/recipes/at91bootstrap/files/0004-AFEB9260-133-board-support.patch b/recipes/at91bootstrap/files/0004-AFEB9260-133-board-support.patch
new file mode 100644
index 0000000000..c88801cc9e
--- /dev/null
+++ b/recipes/at91bootstrap/files/0004-AFEB9260-133-board-support.patch
@@ -0,0 +1,777 @@
+From ef96ec1464569eb42788076d27c9aa9376a3c396 Mon Sep 17 00:00:00 2001
+From: Sergey Lapin <slapin@slind.org>
+Date: Sat, 27 Sep 2008 01:34:49 +0400
+Subject: [PATCH] AFEB9260-133 board support
+
+
+Signed-off-by: Sergey Lapin <slapin@ossfans.org>
+---
+ board/afeb9260-133/afeb9260-133.c           |  403 +++++++++++++++++++++++++++
+ board/afeb9260-133/afeb9260-133.mk          |    8 +
+ board/afeb9260-133/dataflash/afeb9260-133.h |  127 +++++++++
+ board/afeb9260-133/nandflash/afeb9260-133.h |  151 ++++++++++
+ board/afeb9260-133/pll.h                    |   35 +++
+ 5 files changed, 724 insertions(+), 0 deletions(-)
+ create mode 100644 board/afeb9260-133/afeb9260-133.c
+ create mode 100644 board/afeb9260-133/afeb9260-133.mk
+ create mode 100644 board/afeb9260-133/dataflash/afeb9260-133.h
+ create mode 100644 board/afeb9260-133/nandflash/afeb9260-133.h
+ create mode 100644 board/afeb9260-133/pll.h
+
+diff --git a/board/afeb9260-133/afeb9260-133.c b/board/afeb9260-133/afeb9260-133.c
+new file mode 100644
+index 0000000..f54f7a7
+--- /dev/null
++++ b/board/afeb9260-133/afeb9260-133.c
+@@ -0,0 +1,403 @@
++/* ----------------------------------------------------------------------------
++ *         ATMEL Microcontroller Software Support  -  ROUSSET  -
++ * ----------------------------------------------------------------------------
++ * Copyright (c) 2006, Atmel Corporation
++
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the disclaiimer below.
++ *
++ * - Redistributions in binary form must reproduce the above copyright notice,
++ * this list of conditions and the disclaimer below in the documentation and/or
++ * other materials provided with the distribution.
++ *
++ * Atmel's name may not be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * ----------------------------------------------------------------------------
++ * File Name           : at91sam9260ek.c
++ * Object              :
++ * Creation            : NLe Jul 13th 2006
++ * ODi Nov 9th         : dstp #3507 "Bad PIO descriptors in at91samxxxek.c"
++ *-----------------------------------------------------------------------------
++ */
++#include "../../include/part.h"
++#include "../../include/gpio.h"
++#include "../../include/pmc.h"
++#include "../../include/debug.h"
++#include "../../include/sdramc.h"
++#include "../../include/main.h"
++#ifdef CFG_NANDFLASH
++#include "../../include/nandflash.h"
++#endif
++#ifdef CFG_DATAFLASH
++#include "../../include/dataflash.h"
++#endif
++#ifdef CFG_FLASH
++#include "../../include/flash.h"
++#endif
++static inline unsigned int get_cp15(void)
++{
++	unsigned int value;
++	__asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (value));
++	return value;
++}
++
++static inline void set_cp15(unsigned int value)
++{
++	__asm__("mcr p15, 0, %0, c1, c0, 0" : : "r" (value));
++}
++
++#ifdef CFG_HW_INIT
++/*----------------------------------------------------------------------------*/
++/* \fn    hw_init							      */
++/* \brief This function performs very low level HW initialization	      */
++/* This function is invoked as soon as possible during the c_startup	      */
++/* The bss segment must be initialized					      */
++/*----------------------------------------------------------------------------*/
++void hw_init(void)
++{
++	unsigned int cp15;
++	
++	/* Disable watchdog */
++	writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
++
++	/* At this stage the main oscillator is supposed to be enabled
++	 * PCK = MCK = MOSC */
++
++	/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
++	pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
++
++	/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */
++	pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
++
++	/* Configure PLLB */
++	pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
++
++	/* Configure CP15 */
++	/* Using procedure from u-boot for arm926ejs */
++	cp15 = get_cp15();
++	cp15 &= ~I_CACHE;
++	set_cp15(cp15);
++
++	/* Configure the PIO controller */
++	writel(3 << 14, AT91C_BASE_PIOB + PIO_ASR(0));
++	writel(3 << 14, AT91C_BASE_PIOB + PIO_PDR(0));
++
++#ifdef CFG_DEBUG
++	/* Enable Debug messages on the DBGU */
++	dbg_init(BAUDRATE(MASTER_CLOCK, 115200));
++	/* Configure CP15 */
++	/* Using procedure from u-boot for arm926ejs */
++#if 0
++	cp15 = get_cp15();
++	cp15 |= 0xC0000000;
++	set_cp15(cp15);
++#endif
++
++	dbg_print("AT91 bootstrap loading from @< 0x8400\n\r");
++#endif /* CFG_DEBUG */
++
++#ifdef CFG_SDRAM
++	/* Initialize the matrix */
++	writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_BASE_CCFG + CCFG_EBICSA);
++
++	/* Configure SDRAM Controller */
++
++#define HYNIX
++
++//#define MICRON
++#ifdef MICRON
++#define MICRON_REFRESH 1420 /* 15.625 us / 11 ns @ 180 Mhz*/
++	sdram_init(	AT91C_SDRAMC_NC_9  |
++				AT91C_SDRAMC_NR_12 |
++				AT91C_SDRAMC_CAS_2 |
++				AT91C_SDRAMC_NB_4_BANKS |
++				AT91C_SDRAMC_DBW_32_BITS |
++				AT91C_SDRAMC_TWR_2 | // 1 CLK+7ns
++				AT91C_SDRAMC_TRC_7 | // 60 ns
++				AT91C_SDRAMC_TRP_3 | // 15 ns
++				AT91C_SDRAMC_TRCD_3 | // 15 ns
++				AT91C_SDRAMC_TRAS_7 | // 37-120 ns
++				AT91C_SDRAMC_TXSR_7, /* 67ns */ /* Control Register */
++				/* 600 700 735 */ MICRON_REFRESH /* 740 1536*/ );	/* Refresh Timer Register */
++
++#endif
++/* 
++HY57V561620BT-H
++     *CAS lat		*tRCD		*tRAS		*tRC		*tRP		tAC	tOH
++133	2		2		6		8		2		5.4ns	2.7ns
++125	3		3		6		9		3		6ns	3ns
++100	2		2		5		7		2		6ns	3ns
++
++*/
++#ifdef HYNIX
++#if defined(PLLA_180MHz)
++/* CLK= 11ns */
++/* TWR = tDPL = 2 2CLK always */
++/* TRC = tRC = 65ns = 6 clk */
++/* TRP = tRP = 20ns = 2 clk */
++/* TRCD = tRCD = 20ns = 2 clk */
++/* TRAS = tRAS = 45ns = 5 clk */
++/* TXSR = tRRC = 65ns = 6 clk */
++
++	sdram_init(	AT91C_SDRAMC_NC_9  |
++				AT91C_SDRAMC_NR_13 |
++				AT91C_SDRAMC_CAS_2 |
++				AT91C_SDRAMC_NB_4_BANKS |
++				AT91C_SDRAMC_DBW_32_BITS |
++				AT91C_SDRAMC_TWR_2 |
++				AT91C_SDRAMC_TRC_6 | /* *7 */
++				AT91C_SDRAMC_TRP_2 |
++				AT91C_SDRAMC_TRCD_2 |
++				AT91C_SDRAMC_TRAS_5 | /* *5 */
++				AT91C_SDRAMC_TXSR_6, /* *8 */	/* Control Register */
++				710);	/* Refresh Timer Register */
++
++#elif defined(PLLA_120MHz)
++/* CLK= 16ns, MCLK=60MHz */
++/* TWR = tDPL = 2 2CLK always */
++/* TRC = tRC = 65ns = 4 clk */
++/* TRP = tRP = 20ns = 2 clk */
++/* TRCD = tRCD = 20ns = 2 clk */
++/* TRAS = tRAS = 45ns = 3 clk */
++/* TXSR = tRRC = 65ns = 4 clk */
++
++	sdram_init(	AT91C_SDRAMC_NC_9  |
++				AT91C_SDRAMC_NR_13 |
++				AT91C_SDRAMC_CAS_2 |
++				AT91C_SDRAMC_NB_4_BANKS |
++				AT91C_SDRAMC_DBW_32_BITS |
++				AT91C_SDRAMC_TWR_2 |
++				AT91C_SDRAMC_TRC_4 |
++				AT91C_SDRAMC_TRP_2 |
++				AT91C_SDRAMC_TRCD_2 |
++				AT91C_SDRAMC_TRAS_3 | /* *5 */
++				AT91C_SDRAMC_TXSR_4, /* *8 */	/* Control Register */
++				1032);	/* Refresh Timer Register */
++#else
++#error define PLLA180MHz
++#endif
++#endif /* HYNIX */
++#endif /* CFG_SDRAM */
++
++#ifdef	CFG_FLASH
++	flash_hw_init();
++#endif
++	nandflash_hw_init();
++	dbg_print("CP15=\r\n");
++	dbg_print_hex(get_cp15);
++}
++#endif /* CFG_HW_INIT */
++
++#ifdef CFG_SDRAM
++/*------------------------------------------------------------------------------*/
++/* \fn    sdramc_hw_init							*/
++/* \brief This function performs SDRAMC HW initialization			*/
++/*------------------------------------------------------------------------------*/
++void sdramc_hw_init(void)
++{
++	/* Configure PIOs */
++/*	const struct pio_desc sdramc_pio[] = {
++		{"D16", AT91C_PIN_PC(16), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D17", AT91C_PIN_PC(17), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D18", AT91C_PIN_PC(18), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D19", AT91C_PIN_PC(19), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D20", AT91C_PIN_PC(20), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D21", AT91C_PIN_PC(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D22", AT91C_PIN_PC(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D23", AT91C_PIN_PC(23), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D24", AT91C_PIN_PC(24), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D25", AT91C_PIN_PC(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D26", AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D27", AT91C_PIN_PC(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D28", AT91C_PIN_PC(28), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D29", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D30", AT91C_PIN_PC(30), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"D31", AT91C_PIN_PC(31), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++*/
++	/* Configure the SDRAMC PIO controller to output PCK0 */
++/*	pio_setup(sdramc_pio); */
++
++	writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
++	writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
++
++}
++#endif /* CFG_SDRAM */
++
++#ifdef CFG_DATAFLASH
++
++/*------------------------------------------------------------------------------*/
++/* \fn    df_recovery								*/
++/* \brief This function erases DataFlash Page 0 if BP4 is pressed 		*/
++/*        during boot sequence							*/
++/*------------------------------------------------------------------------------*/
++void df_recovery(AT91PS_DF pDf)
++{
++#if 0
++#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
++	/* Configure PIOs */
++	const struct pio_desc bp4_pio[] = {
++		{"BP4", AT91C_PIN_PA(31), 0, PIO_PULLUP, PIO_INPUT},
++		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	/* Configure the PIO controller */
++	writel((1 << AT91C_ID_PIOA), PMC_PCER + AT91C_BASE_PMC);
++	pio_setup(bp4_pio);
++	
++	/* If BP4 is pressed during Boot sequence */
++	/* Erase NandFlash block 0*/
++	if ( !pio_get_value(AT91C_PIN_PA(31)) )
++		df_page_erase(pDf, 0);
++#endif
++#endif
++}
++
++/*------------------------------------------------------------------------------*/
++/* \fn    df_hw_init								*/
++/* \brief This function performs DataFlash HW initialization			*/
++/*------------------------------------------------------------------------------*/
++void df_hw_init(void)
++{
++#if 0
++	/* Configure PIOs */
++	const struct pio_desc df_pio[] = {
++		{"MISO",  AT91C_PIN_PA(0), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"MOSI",  AT91C_PIN_PA(1), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"SPCK",  AT91C_PIN_PA(2), 0, PIO_DEFAULT, PIO_PERIPH_A},
++#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH)
++		{"NPCS0", AT91C_PIN_PA(3), 0, PIO_DEFAULT, PIO_PERIPH_A},
++#endif
++#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
++		{"NPCS1", AT91C_PIN_PC(11), 0, PIO_DEFAULT, PIO_PERIPH_B},
++#endif
++		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	/* Configure the PIO controller */
++	pio_setup(df_pio);
++#else
++	writel(0xf, 0xfffff444);
++	writel(0xf, 0xfffff460);
++	writel(0xf, 0xfffff470);
++	writel(0xf, 0xfffff404);
++	writel(1 << 11, AT91C_BASE_PIOC + PIO_BSR(0));
++	writel(1 << 11, AT91C_BASE_PIOC + PIO_PDR(0));
++#endif
++}
++#endif /* CFG_DATAFLASH */
++
++#ifdef CFG_FLASH
++
++/*------------------------------------------------------------------------------*/
++/* \fn    flash_hw_init								*/
++/* \brief This function performs Flash HW initialization			*/
++/*------------------------------------------------------------------------------*/
++void flash_hw_init(void)
++{
++	/* Configure PIOs */
++	const struct pio_desc flash_pio[] = {
++		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	/* Configure the PIO controller */
++	pio_setup(flash_pio);
++}
++
++#endif /* CFG_FLASH */
++
++#ifdef CFG_NANDFLASH
++/*------------------------------------------------------------------------------*/
++/* \fn    nand_recovery						*/
++/* \brief This function erases NandFlash Block 0 if BP4 is pressed 		*/
++/*        during boot sequence							*/
++/*------------------------------------------------------------------------------*/
++static void nand_recovery(void)
++{
++	/* Configure PIOs */
++	const struct pio_desc bp4_pio[] = {
++		{"BP4", AT91C_PIN_PA(31), 0, PIO_PULLUP, PIO_INPUT},
++		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	/* Configure the PIO controller */
++	writel((1 << AT91C_ID_PIOA), PMC_PCER + AT91C_BASE_PMC);
++	pio_setup(bp4_pio);
++	
++	/* If BP4 is pressed during Boot sequence */
++	/* Erase NandFlash block 0*/
++	if (!pio_get_value(AT91C_PIN_PA(31)) )
++		AT91F_NandEraseBlock0();
++}
++#endif
++/*------------------------------------------------------------------------------*/
++/* \fn    nandflash_hw_init							*/
++/* \brief NandFlash HW init							*/
++/*------------------------------------------------------------------------------*/
++void nandflash_hw_init(void)
++{
++#if 0
++	/* Configure PIOs */
++	const struct pio_desc nand_pio[] = {
++		{"RDY_BSY", AT91C_PIN_PC(13), 0, PIO_PULLUP, PIO_INPUT},
++		{"NANDCS",  AT91C_PIN_PC(14), 0, PIO_PULLUP, PIO_OUTPUT},
++		{(char *) 0, 0, 0,  PIO_DEFAULT, PIO_PERIPH_A},
++	};
++#endif
++	/* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */
++	writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM, AT91C_BASE_CCFG + CCFG_EBICSA);
++		    
++	/* Configure SMC CS3 */
++ 	writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
++  	writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
++	writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE)						, AT91C_BASE_SMC + SMC_CYCLE3);
++	writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | 
++  		AT91C_SMC_DBW_WIDTH_EIGTH_BITS | AT91C_SM_TDF)						, AT91C_BASE_SMC + SMC_CTRL3);
++
++	/* Configure the PIO controller */
++	writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC);
++
++	writel(1 << 13, AT91C_BASE_PIOC + PIO_IFDR(0));
++	writel(1 << 13, AT91C_BASE_PIOC + PIO_PPUER(0));
++	writel(1 << 13, AT91C_BASE_PIOC + PIO_ODR(0));
++	writel(1 << 14, AT91C_BASE_PIOC + PIO_CODR(0));
++	writel(1 << 14, AT91C_BASE_PIOC + PIO_MDDR(0));
++	writel(1 << 14, AT91C_BASE_PIOC + PIO_PPUDR(0));
++	writel(1 << 14, AT91C_BASE_PIOC + PIO_OER(0));
++	writel(3 << 13, AT91C_BASE_PIOC + PIO_IDR(0));
++	writel(3 << 13, AT91C_BASE_PIOC + PIO_PER(0));
++
++#if 0	
++	nand_recovery();
++#endif
++}
++
++
++#if 0
++/*------------------------------------------------------------------------------*/
++/* \fn    nandflash_cfg_16bits_dbw_init						*/
++/* \brief Configure SMC in 16 bits mode						*/
++/*------------------------------------------------------------------------------*/
++void nandflash_cfg_16bits_dbw_init(void)
++{
++	writel(readl(AT91C_BASE_SMC + SMC_CTRL3) | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS, AT91C_BASE_SMC + SMC_CTRL3);
++}
++
++#endif /* #ifdef CFG_NANDFLASH */
+diff --git a/board/afeb9260-133/afeb9260-133.mk b/board/afeb9260-133/afeb9260-133.mk
+new file mode 100644
+index 0000000..84e45d3
+--- /dev/null
++++ b/board/afeb9260-133/afeb9260-133.mk
+@@ -0,0 +1,8 @@
++# Target name (case sensitive!!!)
++TARGET=AFEB9260_133
++# Board name (case sensitive!!!)
++BOARD=afeb9260-133
++# Link Address and Top_of_Memory
++LINK_ADDR=0x200000
++TOP_OF_MEMORY=0x301000
++
+diff --git a/board/afeb9260-133/dataflash/afeb9260-133.h b/board/afeb9260-133/dataflash/afeb9260-133.h
+new file mode 100644
+index 0000000..2ebb020
+--- /dev/null
++++ b/board/afeb9260-133/dataflash/afeb9260-133.h
+@@ -0,0 +1,127 @@
++/* ----------------------------------------------------------------------------
++ *         ATMEL Microcontroller Software Support  -  ROUSSET  -
++ * ----------------------------------------------------------------------------
++ * Copyright (c) 2006, Atmel Corporation
++
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the disclaiimer below.
++ *
++ * - Redistributions in binary form must reproduce the above copyright notice,
++ * this list of conditions and the disclaimer below in the documentation and/or
++ * other materials provided with the distribution.
++ *
++ * Atmel's name may not be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * ----------------------------------------------------------------------------
++ * File Name           : at91sam9260ek.h
++ * Object              :
++ * Creation            : NLe Jul 13th 2006
++ *-----------------------------------------------------------------------------
++ */
++#ifndef _AFEB9260_133_H
++#define _AFEB9260_133_H
++#include	"spi.h"
++#include	"pll.h"
++
++/* ******************************************************************* */
++/* DataFlash Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define AT91C_BASE_SPI	AT91C_BASE_SPI0
++#define AT91C_ID_SPI	AT91C_ID_SPI0
++
++/* SPI CLOCK */
++#define AT91C_SPI_CLK 		 5000000
++/* AC characteristics */
++/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */
++#define DATAFLASH_TCSS		(0x1a << 16)	/* 250ns min (tCSS) <=> 12/48000000 = 250ns */
++#define DATAFLASH_TCHS		(0x1 << 24)	/* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */
++
++#define DF_CS_SETTINGS 		((SPI_MODE) | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8))
++
++
++/* ******************************************************************* */
++/* BootStrap Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define MACH_TYPE       	0x44B		/* AT91SAM9260-EK */
++
++#define IMG_ADDRESS 		0x8400		/* Image Address in DataFlash */
++
++#if	defined(IMG_SIZE)
++#warning			"IMG_SIZE redefined"
++#else
++#define	IMG_SIZE		0x39000	/* Image Size in DataFlash    */
++#endif
++
++#if	defined(JUMP_ADDR)
++#warning			"JUMP_ADDR redefined"
++#else
++#define JUMP_ADDR		0x21F00000	/* Final Jump Address 	      */
++#endif
++
++/* ******************************************************************* */
++/* NandFlash Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define AT91C_SMARTMEDIA_BASE	0x40000000
++
++#define AT91_SMART_MEDIA_ALE    (1 << 21)	/* our ALE is AD21 */
++#define AT91_SMART_MEDIA_CLE    (1 << 22)	/* our CLE is AD22 */
++
++#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0)
++#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0)
++
++#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13))
++
++
++/* ******************************************************************** */
++/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/
++/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000.			*/
++/* Please refer to SMC section in AT91SAM9261 datasheet to learn how 	*/
++/* to generate these values. 						*/
++/* ******************************************************************** */
++
++#define AT91C_SM_NWE_SETUP	(2 << 0)
++#define AT91C_SM_NCS_WR_SETUP	(2 << 8)
++#define AT91C_SM_NRD_SETUP	(2 << 16)
++#define AT91C_SM_NCS_RD_SETUP	(2 << 24)
++  
++#define AT91C_SM_NWE_PULSE 	(4 << 0)
++#define AT91C_SM_NCS_WR_PULSE	(4 << 8)
++#define AT91C_SM_NRD_PULSE	(4 << 16)
++#define AT91C_SM_NCS_RD_PULSE	(4 << 24)
++  
++#define AT91C_SM_NWE_CYCLE 	(8 << 0)
++#define AT91C_SM_NRD_CYCLE	(8 << 16)
++
++#define AT91C_SM_TDF	        (2 << 16)
++
++
++
++/* ******************************************************************* */
++/* Application Settings                                                */
++/* ******************************************************************* */
++#define CFG_DEBUG
++#define CFG_DATAFLASH
++#define	CFG_SDRAM
++#define	CFG_HW_INIT
++
++
++#endif	/* _AT91SAM9260EK_H */
+diff --git a/board/afeb9260-133/nandflash/afeb9260-133.h b/board/afeb9260-133/nandflash/afeb9260-133.h
+new file mode 100644
+index 0000000..414d30c
+--- /dev/null
++++ b/board/afeb9260-133/nandflash/afeb9260-133.h
+@@ -0,0 +1,151 @@
++/* ----------------------------------------------------------------------------
++ *         ATMEL Microcontroller Software Support  -  ROUSSET  -
++ * ----------------------------------------------------------------------------
++ * Copyright (c) 2006, Atmel Corporation
++
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the disclaimer below.
++ *
++ * - Redistributions in binary form must reproduce the above copyright notice,
++ * this list of conditions and the disclaimer below in the documentation and/or
++ * other materials provided with the distribution.
++ *
++ * Atmel's name may not be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * ----------------------------------------------------------------------------
++ * File Name           : at91sam9260ek.h
++ * Object              :
++ * Creation            : NLe Sep 28th 2006
++ *-----------------------------------------------------------------------------
++ */
++#ifndef _AFEB9260_133_H
++#define _AFEB9260_133_H
++#include	"spi.h"
++#include	"pll.h"
++
++/* ******************************************************************* */
++/* DataFlash Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define AT91C_BASE_SPI	AT91C_BASE_SPI0
++#define AT91C_ID_SPI	AT91C_ID_SPI0
++
++/* SPI CLOCK */
++#define AT91C_SPI_CLK 		 5000000
++/* AC characteristics */
++/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */
++#define DATAFLASH_TCSS		(0x1a << 16)	/* 250ns min (tCSS) <=> 12/48000000 = 250ns */
++#define DATAFLASH_TCHS		(0x1 << 24)	/* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */
++
++#define DF_CS_SETTINGS 		((SPI_MODE) | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8))
++
++
++/* ******************************************************************* */
++/* NandFlash Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define AT91C_SMARTMEDIA_BASE	0x40000000
++
++#define AT91_SMART_MEDIA_ALE    (1 << 21)	/* our ALE is AD21 */
++#define AT91_SMART_MEDIA_CLE    (1 << 22)	/* our CLE is AD22 */
++
++#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0)
++#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0)
++
++#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13))
++
++
++/* ******************************************************************** */
++/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/
++/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000.			*/
++/* Please refer to SMC section in AT91SAM9261 datasheet to learn how 	*/
++/* to generate these values. 						*/
++/* ******************************************************************** */
++
++#define AT91C_SM_NWE_SETUP	(2 << 0)
++#define AT91C_SM_NCS_WR_SETUP	(2 << 8)
++#define AT91C_SM_NRD_SETUP	(2 << 16)
++#define AT91C_SM_NCS_RD_SETUP	(2 << 24)
++  
++#define AT91C_SM_NWE_PULSE 	(4 << 0)
++#define AT91C_SM_NCS_WR_PULSE	(4 << 8)
++#define AT91C_SM_NRD_PULSE	(4 << 16)
++#define AT91C_SM_NCS_RD_PULSE	(4 << 24)
++  
++#define AT91C_SM_NWE_CYCLE 	(8 << 0)
++#define AT91C_SM_NRD_CYCLE	(8 << 16)
++
++#define AT91C_SM_TDF	        (2 << 16)
++
++
++/* ******************************************************************** */
++/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/
++/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000.			*/
++/* Please refer to SMC section in AT91SAM9261 datasheet to learn how 	*/
++/* to generate these values. 						*/
++/* ******************************************************************** */
++/*#define AT91C_SM_NWE_SETUP	(0 << 0)
++#define AT91C_SM_NCS_WR_SETUP	(0 << 8)
++#define AT91C_SM_NRD_SETUP	(0 << 16)
++#define AT91C_SM_NCS_RD_SETUP	(0 << 24)
++  
++#define AT91C_SM_NWE_PULSE 	(2 << 0)
++#define AT91C_SM_NCS_WR_PULSE	(3 << 8)
++#define AT91C_SM_NRD_PULSE	(2 << 16)
++#define AT91C_SM_NCS_RD_PULSE	(3 << 24)
++  
++#define AT91C_SM_NWE_CYCLE 	(3 << 0)
++#define AT91C_SM_NRD_CYCLE	(3 << 16)
++
++#define AT91C_SM_TDF	        (1 << 16)
++*/
++
++/* ******************************************************************* */
++/* BootStrap Settings                                                  */
++/*                                                                     */
++/* ******************************************************************* */
++#define MACH_TYPE      		0x44B       	/* AT91SAM9260-EK */
++
++#define IMG_ADDRESS 		0x20000		/* Image Address in NandFlash */
++
++#if	defined(IMG_SIZE)
++#warning			"IMG_SIZE redefined"
++#else
++#define	IMG_SIZE		0x30000		/* Image Size in NandFlash    */
++#endif
++
++#if	defined(JUMP_ADDR)
++#warning			"JUMP_ADDR redefined"
++#else
++#define JUMP_ADDR		0x23F00000	/* Final Jump Address 	      */
++#endif
++
++/* ******************************************************************* */
++/* Application Settings                                                */
++/* ******************************************************************* */
++#define CFG_DEBUG
++#undef CFG_DATAFLASH
++
++#define CFG_NANDFLASH
++#undef	NANDFLASH_SMALL_BLOCKS	/* NANDFLASH_LARGE_BLOCKS used instead */
++
++#define CFG_HW_INIT
++#define CFG_SDRAM
++
++#endif	/* _AT91SAM9260EK_H */
+diff --git a/board/afeb9260-133/pll.h b/board/afeb9260-133/pll.h
+new file mode 100644
+index 0000000..907aaa0
+--- /dev/null
++++ b/board/afeb9260-133/pll.h
+@@ -0,0 +1,35 @@
++/* ******************************************************************* */
++/* PMC Settings                                                        */
++/*                                                                     */
++/* The main oscillator is enabled as soon as possible in the c_startup */
++/* and MCK is switched on the main oscillator.                         */
++/* PLL initialization is done later in the hw_init() function          */
++/* ******************************************************************* */
++#define PLL_LOCK_TIMEOUT	1000000
++
++#define PLLA_120MHz
++
++#ifdef PLLA_200MHz
++#define PLLA_SETTINGS	0x2060BF09
++#define MASTER_CLOCK		(198656000/2)
++#endif
++
++#ifdef PLLA_180MHz
++#define PLLA_SETTINGS	0x2125BF1E /* 180MHz */
++#define MASTER_CLOCK		(179999198/2) /* 180MHz MCK=90MHz */
++#endif
++
++#ifdef PLLA_120MHz
++//#define PLLA_SETTINGS	0x2125BF2d /* 120MHz */
++//#define MASTER_CLOCK		(119999322) /* 120MHz MCK=60MHz*/
++#define PLLA_SETTINGS	0x2125BF2d /* 120MHz */
++#define MASTER_CLOCK		(119999465/2) /* 120MHz MCK=60MHz*/
++#endif
++
++#if !defined(PLLA_180MHz) && !defined(PLLA_120MHz)
++#error Define PLLA frequency
++#endif
++#define PLLB_SETTINGS	0x10483F0E
++
++/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */
++#define MCKR_SETTINGS	(AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2)
+-- 
+1.5.6.5
+