xserver-kdrive : commit missing patches

2 files changed, 3778 insertions, 0 deletions

diff --git a/packages/xorg-xserver/xserver-kdrive-1.3.0.0/build-glamo.patch b/packages/xorg-xserver/xserver-kdrive-1.3.0.0/build-glamo.patch
new file mode 100644
index 0000000000..f4757ce3c9
--- /dev/null
+++ b/packages/xorg-xserver/xserver-kdrive-1.3.0.0/build-glamo.patch
@@ -0,0 +1,76 @@
+diff --git a/configure.ac b/configure.ac
+index 76d33f0..2807c50 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -1824,6 +1824,7 @@ hw/kdrive/ati/Makefile
+ hw/kdrive/chips/Makefile
+ hw/kdrive/ephyr/Makefile
+ hw/kdrive/epson/Makefile
++hw/kdrive/glamo/Makefile
+ hw/kdrive/fake/Makefile
+ hw/kdrive/fbdev/Makefile
+ hw/kdrive/w100/Makefile
+diff --git a/hw/kdrive/Makefile.am b/hw/kdrive/Makefile.am
+index 8075a56..b97912d 100644
+--- a/hw/kdrive/Makefile.am
++++ b/hw/kdrive/Makefile.am
+@@ -4,7 +4,7 @@ VESA_SUBDIRS = vesa ati chips epson i810 mach64 mga neomagic nvidia pm2 r128 \
+ endif
+ 
+ if KDRIVEFBDEV
+-FBDEV_SUBDIRS = fbdev epson
++FBDEV_SUBDIRS = fbdev epson glamo
+ endif
+ 
+ if KDRIVEW100
+@@ -34,4 +34,4 @@ SUBDIRS =			\
+ 	fake
+ 
+ DIST_SUBDIRS = vesa ati chips epson i810 mach64 mga neomagic nvidia pm2 r128 \
+-               smi via fbdev sdl ephyr src linux fake sis300
++               smi via fbdev sdl ephyr src linux fake sis300 glamo
+diff --git a/hw/kdrive/glamo/Makefile.am b/hw/kdrive/glamo/Makefile.am
+index e8c48a4..ffb7a30 100644
+--- a/hw/kdrive/glamo/Makefile.am
++++ b/hw/kdrive/glamo/Makefile.am
+@@ -41,11 +41,14 @@ GLAMO_LIBS =				\
+ 
+ Xglamo_LDADD = \
+ 	$(GLAMO_LIBS)			\
+-	@KDRIVE_LIBS@
++	@KDRIVE_LIBS@			\
++	@XSERVER_LIBS@
+ 
+ Xglamo_DEPENDENCIES =	\
+ 	libglamo.a 			\
+-	@KDRIVE_LOCAL_LIBS@
++        $(FBDEV_LIBS)                   \
++        $(VESA_LIBS)                    \
++        $(DRI_LIBS)
+ 
+ relink:
+ 	rm -f $(bin_PROGRAMS) && make $(bin_PROGRAMS)
+diff --git a/hw/kdrive/glamo/glamo_stub.c b/hw/kdrive/glamo/glamo_stub.c
+index d772671..df43455 100644
+--- a/hw/kdrive/glamo/glamo_stub.c
++++ b/hw/kdrive/glamo/glamo_stub.c
+@@ -49,16 +49,10 @@ InitOutput(ScreenInfo *pScreenInfo, int argc, char **argv)
+ void
+ InitInput(int argc, char **argv)
+ {
+-	KdKeyboardInfo *ki;
+-
+-	KdAddKeyboardDriver(&LinuxKeyboardDriver);
+-	KdAddPointerDriver(&LinuxMouseDriver);
+-#ifdef TSLIB
+-	KdAddPointerDriver(&TsDriver);
++	KdInitInput (&LinuxEvdevMouseFuncs, &LinuxEvdevKeyboardFuncs);
++#ifdef TOUCHSCREEN
++	KdAddMouseDriver (&TsFuncs);
+ #endif
+-
+-	ki = KdParseKeyboard("keybd");
+-	KdAddKeyboard(ki);
+ }
+ 
+ void
diff --git a/packages/xorg-xserver/xserver-kdrive-1.3.0.0/smedia-glamo.patch b/packages/xorg-xserver/xserver-kdrive-1.3.0.0/smedia-glamo.patch
new file mode 100644
index 0000000000..4ad3573c95
--- /dev/null
+++ b/packages/xorg-xserver/xserver-kdrive-1.3.0.0/smedia-glamo.patch
@@ -0,0 +1,3702 @@
+Index: xserver/hw/kdrive/glamo/Makefile.am
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ xserver/hw/kdrive/glamo/Makefile.am	2007-09-25 19:32:10.000000000 +0800
+@@ -0,0 +1,51 @@
++if KDRIVEFBDEV
++FBDEV_INCLUDES =-I$(top_srcdir)/hw/kdrive/fbdev
++FBDEV_LIBS = $(top_builddir)/hw/kdrive/fbdev/libfbdev.a
++endif
++
++if KDRIVEVESA
++VESA_INCLUDES = -I$(top_srcdir)/hw/kdrive/vesa
++VESA_LIBS = $(top_builddir)/hw/kdrive/vesa/libvesa.a
++endif
++
++INCLUDES = 					\
++	@KDRIVE_INCS@				\
++	$(DRI_INCLUDES)				\
++	$(FBDEV_INCLUDES)			\
++	$(VESA_INCLUDES)			\
++	@KDRIVE_CFLAGS@
++
++bin_PROGRAMS = Xglamo
++
++noinst_LIBRARIES = libglamo.a
++
++libglamo_a_SOURCES = 	\
++	glamo_dma.c	\
++	glamo_dma.h	\
++	glamo_draw.c	\
++	glamo_draw.h	\
++	glamo.c		\
++	glamo.h		\
++	glamo-regs.h	\
++	glamo_video.c
++
++Xglamo_SOURCES = \
++	glamo_stub.c
++
++GLAMO_LIBS =				\
++	libglamo.a 			\
++	$(FBDEV_LIBS)			\
++	$(VESA_LIBS)			\
++	$(DRI_LIBS)			\
++	@KDRIVE_LIBS@
++
++Xglamo_LDADD = \
++	$(GLAMO_LIBS)			\
++	@KDRIVE_LIBS@
++
++Xglamo_DEPENDENCIES =	\
++	libglamo.a 			\
++	@KDRIVE_LOCAL_LIBS@
++
++relink:
++	rm -f $(bin_PROGRAMS) && make $(bin_PROGRAMS)
+Index: xserver/hw/kdrive/glamo/glamo-regs.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ xserver/hw/kdrive/glamo/glamo-regs.h	2007-09-25 19:00:20.000000000 +0800
+@@ -0,0 +1,685 @@
++#ifndef _GLAMO_REGS_H
++#define _GLAMO_REGS_H
++
++/* Smedia Glamo 336x/337x driver
++ *
++ * (C) 2007 by OpenMoko, Inc.
++ * Author: Harald Welte <laforge@openmoko.org>
++ * All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++enum glamo_regster_offsets {
++	GLAMO_REGOFS_GENERIC	= 0x0000,
++	GLAMO_REGOFS_HOSTBUS	= 0x0200,
++	GLAMO_REGOFS_MEMORY	= 0x0300,
++	GLAMO_REGOFS_VIDCAP	= 0x0400,
++	GLAMO_REGOFS_ISP	= 0x0500,
++	GLAMO_REGOFS_JPEG	= 0x0800,
++	GLAMO_REGOFS_MPEG	= 0x0c00,
++	GLAMO_REGOFS_LCD	= 0x1100,
++	GLAMO_REGOFS_MMC	= 0x1400,
++	GLAMO_REGOFS_MPROC0	= 0x1500,
++	GLAMO_REGOFS_MPROC1	= 0x1580,
++	GLAMO_REGOFS_CMDQUEUE	= 0x1600,
++	GLAMO_REGOFS_RISC	= 0x1680,
++	GLAMO_REGOFS_2D		= 0x1700,
++	GLAMO_REGOFS_3D		= 0x1b00,
++};
++
++
++enum glamo_register_generic {
++	GLAMO_REG_GCONF1	= 0x0000,
++	GLAMO_REG_GCONF2	= 0x0002,
++#define	GLAMO_REG_DEVICE_ID	GLAMO_REG_GCONF2
++	GLAMO_REG_GCONF3	= 0x0004,
++#define	GLAMO_REG_REVISION_ID	GLAMO_REG_GCONF3
++	GLAMO_REG_IRQ_GEN1	= 0x0006,
++#define GLAMO_REG_IRQ_ENABLE	GLAMO_REG_IRQ_GEN1
++	GLAMO_REG_IRQ_GEN2	= 0x0008,
++#define GLAMO_REG_IRQ_SET	GLAMO_REG_IRQ_GEN2
++	GLAMO_REG_IRQ_GEN3	= 0x000a,
++#define GLAMO_REG_IRQ_CLEAR	GLAMO_REG_IRQ_GEN3
++	GLAMO_REG_IRQ_GEN4	= 0x000c,
++#define GLAMO_REG_IRQ_STATUS	GLAMO_REG_IRQ_GEN4
++	GLAMO_REG_CLOCK_HOST	= 0x0010,
++	GLAMO_REG_CLOCK_MEMORY	= 0x0012,
++	GLAMO_REG_CLOCK_LCD	= 0x0014,
++	GLAMO_REG_CLOCK_MMC	= 0x0016,
++	GLAMO_REG_CLOCK_ISP	= 0x0018,
++	GLAMO_REG_CLOCK_JPEG	= 0x001a,
++	GLAMO_REG_CLOCK_3D	= 0x001c,
++	GLAMO_REG_CLOCK_2D	= 0x001e,
++	GLAMO_REG_CLOCK_RISC1	= 0x0020,	/* 3365 only? */
++	GLAMO_REG_CLOCK_RISC2	= 0x0022,	/* 3365 only? */
++	GLAMO_REG_CLOCK_MPEG	= 0x0024,
++	GLAMO_REG_CLOCK_MPROC	= 0x0026,
++
++	GLAMO_REG_CLOCK_GEN5_1	= 0x0030,
++	GLAMO_REG_CLOCK_GEN5_2	= 0x0032,
++	GLAMO_REG_CLOCK_GEN6	= 0x0034,
++	GLAMO_REG_CLOCK_GEN7	= 0x0036,
++	GLAMO_REG_CLOCK_GEN8	= 0x0038,
++	GLAMO_REG_CLOCK_GEN9	= 0x003a,
++	GLAMO_REG_CLOCK_GEN10	= 0x003c,
++	GLAMO_REG_CLOCK_GEN11	= 0x003e,
++	GLAMO_REG_PLL_GEN1	= 0x0040,
++	GLAMO_REG_PLL_GEN2	= 0x0042,
++	GLAMO_REG_PLL_GEN3	= 0x0044,
++	GLAMO_REG_PLL_GEN4	= 0x0046,
++	GLAMO_REG_PLL_GEN5	= 0x0048,
++	GLAMO_REG_GPIO_GEN1	= 0x0050,
++	GLAMO_REG_GPIO_GEN2	= 0x0052,
++	GLAMO_REG_GPIO_GEN3	= 0x0054,
++	GLAMO_REG_GPIO_GEN4	= 0x0056,
++	GLAMO_REG_GPIO_GEN5	= 0x0058,
++	GLAMO_REG_GPIO_GEN6	= 0x005a,
++	GLAMO_REG_GPIO_GEN7	= 0x005c,
++	GLAMO_REG_GPIO_GEN8	= 0x005e,
++	GLAMO_REG_GPIO_GEN9	= 0x0060,
++	GLAMO_REG_GPIO_GEN10	= 0x0062,
++	GLAMO_REG_DFT_GEN1	= 0x0070,
++	GLAMO_REG_DFT_GEN2	= 0x0072,
++	GLAMO_REG_DFT_GEN3	= 0x0074,
++	GLAMO_REG_DFT_GEN4	= 0x0076,
++
++	GLAMO_REG_DFT_GEN5	= 0x01e0,
++	GLAMO_REG_DFT_GEN6	= 0x01f0,
++};
++
++#define GLAMO_REG_HOSTBUS(x)	(GLAMO_REGOFS_HOSTBUS-2+(x*2))
++
++#define REG_MEM(x)		(GLAMO_REGOFS_MEMORY+(x))
++#define GLAMO_REG_MEM_TIMING(x)	(GLAMO_REG_MEM_TIMING1-2+(x*2))
++
++enum glamo_register_mem {
++	GLAMO_REG_MEM_TYPE	= REG_MEM(0x00),
++	GLAMO_REG_MEM_GEN	= REG_MEM(0x02),
++	GLAMO_REG_MEM_TIMING1	= REG_MEM(0x04),
++	GLAMO_REG_MEM_TIMING2	= REG_MEM(0x06),
++	GLAMO_REG_MEM_TIMING3	= REG_MEM(0x08),
++	GLAMO_REG_MEM_TIMING4	= REG_MEM(0x0a),
++	GLAMO_REG_MEM_TIMING5	= REG_MEM(0x0c),
++	GLAMO_REG_MEM_TIMING6	= REG_MEM(0x0e),
++	GLAMO_REG_MEM_TIMING7	= REG_MEM(0x10),
++	GLAMO_REG_MEM_TIMING8	= REG_MEM(0x12),
++	GLAMO_REG_MEM_TIMING9	= REG_MEM(0x14),
++	GLAMO_REG_MEM_TIMING10	= REG_MEM(0x16),
++	GLAMO_REG_MEM_TIMING11	= REG_MEM(0x18),
++	GLAMO_REG_MEM_POWER1	= REG_MEM(0x1a),
++	GLAMO_REG_MEM_POWER2	= REG_MEM(0x1c),
++	GLAMO_REG_MEM_LCD_BUF1	= REG_MEM(0x1e),
++	GLAMO_REG_MEM_LCD_BUF2	= REG_MEM(0x20),
++	GLAMO_REG_MEM_LCD_BUF3	= REG_MEM(0x22),
++	GLAMO_REG_MEM_LCD_BUF4	= REG_MEM(0x24),
++	GLAMO_REG_MEM_BIST1	= REG_MEM(0x26),
++	GLAMO_REG_MEM_BIST2	= REG_MEM(0x28),
++	GLAMO_REG_MEM_BIST3	= REG_MEM(0x2a),
++	GLAMO_REG_MEM_BIST4	= REG_MEM(0x2c),
++	GLAMO_REG_MEM_BIST5	= REG_MEM(0x2e),
++	GLAMO_REG_MEM_MAH1	= REG_MEM(0x30),
++	GLAMO_REG_MEM_MAH2	= REG_MEM(0x32),
++	GLAMO_REG_MEM_DRAM1	= REG_MEM(0x34),
++	GLAMO_REG_MEM_DRAM2	= REG_MEM(0x36),
++	GLAMO_REG_MEM_CRC	= REG_MEM(0x38),
++};
++
++#define GLAMO_MEM_TYPE_MASK	0x03
++
++enum glamo_reg_mem_dram1 {
++	GLAMO_MEM_DRAM1_EN_SDRAM_CLK	= (1 << 11),
++	GLAMO_MEM_DRAM1_SELF_REFRESH	= (1 << 12),
++};
++
++enum glamo_reg_mem_dram2 {
++	GLAMO_MEM_DRAM2_DEEP_PWRDOWN	= (1 << 12),
++};
++
++enum glamo_irq {
++	GLAMO_IRQ_HOSTBUS	= 0x0001,
++	GLAMO_IRQ_JPEG		= 0x0002,
++	GLAMO_IRQ_MPEG		= 0x0004,
++	GLAMO_IRQ_MPROC1	= 0x0008,
++	GLAMO_IRQ_MPROC0	= 0x0010,
++	GLAMO_IRQ_CMDQUEUE	= 0x0020,
++	GLAMO_IRQ_2D		= 0x0040,
++	GLAMO_IRQ_MMC		= 0x0080,
++	GLAMO_IRQ_RISC		= 0x0100,
++};
++
++enum glamo_reg_clock_host {
++	GLAMO_CLOCK_HOST_DG_BCLK	= 0x0001,
++	GLAMO_CLOCK_HOST_DG_M0CLK	= 0x0004,
++	GLAMO_CLOCK_HOST_RESET		= 0x1000,
++};
++
++enum glamo_reg_clock_mem {
++	GLAMO_CLOCK_MEM_DG_M1CLK	= 0x0001,
++	GLAMO_CLOCK_MEM_EN_M1CLK	= 0x0002,
++	GLAMO_CLOCK_MEM_DG_MOCACLK	= 0x0004,
++	GLAMO_CLOCK_MEM_EN_MOCACLK	= 0x0008,
++	GLAMO_CLOCK_MEM_RESET		= 0x1000,
++	GLAMO_CLOCK_MOCA_RESET		= 0x2000,
++};
++
++enum glamo_reg_clock_lcd {
++	GLAMO_CLOCK_LCD_DG_DCLK		= 0x0001,
++	GLAMO_CLOCK_LCD_EN_DCLK		= 0x0002,
++	GLAMO_CLOCK_LCD_DG_DMCLK	= 0x0004,
++	GLAMO_CLOCK_LCD_EN_DMCLK	= 0x0008,
++	//
++	GLAMO_CLOCK_LCD_EN_DHCLK	= 0x0020,
++	GLAMO_CLOCK_LCD_DG_M5CLK	= 0x0040,
++	GLAMO_CLOCK_LCD_EN_M5CLK	= 0x0080,
++	GLAMO_CLOCK_LCD_RESET		= 0x1000,
++};
++
++enum glamo_reg_clock_mmc {
++	GLAMO_CLOCK_MMC_DG_TCLK		= 0x0001,
++	GLAMO_CLOCK_MMC_EN_TCLK		= 0x0002,
++	GLAMO_CLOCK_MMC_DG_M9CLK	= 0x0004,
++	GLAMO_CLOCK_MMC_EN_M9CLK	= 0x0008,
++	GLAMO_CLOCK_MMC_RESET		= 0x1000,
++};
++
++enum glamo_reg_clock_isp {
++	GLAMO_CLOCK_ISP_DG_I1CLK	= 0x0001,
++	GLAMO_CLOCK_ISP_EN_I1CLK	= 0x0002,
++	GLAMO_CLOCK_ISP_DG_CCLK		= 0x0004,
++	GLAMO_CLOCK_ISP_EN_CCLK		= 0x0008,
++	//
++	GLAMO_CLOCK_ISP_EN_SCLK		= 0x0020,
++	GLAMO_CLOCK_ISP_DG_M2CLK	= 0x0040,
++	GLAMO_CLOCK_ISP_EN_M2CLK	= 0x0080,
++	GLAMO_CLOCK_ISP_DG_M15CLK	= 0x0100,
++	GLAMO_CLOCK_ISP_EN_M15CLK	= 0x0200,
++	GLAMO_CLOCK_ISP1_RESET		= 0x1000,
++	GLAMO_CLOCK_ISP2_RESET		= 0x2000,
++};
++
++enum glamo_reg_clock_jpeg {
++	GLAMO_CLOCK_JPEG_DG_JCLK	= 0x0001,
++	GLAMO_CLOCK_JPEG_EN_JCLK	= 0x0002,
++	GLAMO_CLOCK_JPEG_DG_M3CLK	= 0x0004,
++	GLAMO_CLOCK_JPEG_EN_M3CLK	= 0x0008,
++	GLAMO_CLOCK_JPEG_RESET		= 0x1000,
++};
++
++enum glamo_reg_clock_2d {
++	GLAMO_CLOCK_2D_DG_GCLK		= 0x0001,
++	GLAMO_CLOCK_2D_EN_GCLK		= 0x0002,
++	GLAMO_CLOCK_2D_DG_M7CLK		= 0x0004,
++	GLAMO_CLOCK_2D_EN_M7CLK		= 0x0008,
++	GLAMO_CLOCK_2D_DG_M6CLK		= 0x0010,
++	GLAMO_CLOCK_2D_EN_M6CLK		= 0x0020,
++	GLAMO_CLOCK_2D_RESET		= 0x1000,
++	GLAMO_CLOCK_2D_CQ_RESET		= 0x2000,
++};
++
++enum glamo_reg_clock_3d {
++	GLAMO_CLOCK_3D_DG_ECLK		= 0x0001,
++	GLAMO_CLOCK_3D_EN_ECLK		= 0x0002,
++	GLAMO_CLOCK_3D_DG_RCLK		= 0x0004,
++	GLAMO_CLOCK_3D_EN_RCLK		= 0x0008,
++	GLAMO_CLOCK_3D_DG_M8CLK		= 0x0010,
++	GLAMO_CLOCK_3D_EN_M8CLK		= 0x0020,
++	GLAMO_CLOCK_3D_BACK_RESET	= 0x1000,
++	GLAMO_CLOCK_3D_FRONT_RESET	= 0x2000,
++};
++
++enum glamo_reg_clock_mpeg {
++	GLAMO_CLOCK_MPEG_DG_X0CLK	= 0x0001,
++	GLAMO_CLOCK_MPEG_EN_X0CLK	= 0x0002,
++	GLAMO_CLOCK_MPEG_DG_X1CLK	= 0x0004,
++	GLAMO_CLOCK_MPEG_EN_X1CLK	= 0x0008,
++	GLAMO_CLOCK_MPEG_DG_X2CLK	= 0x0010,
++	GLAMO_CLOCK_MPEG_EN_X2CLK	= 0x0020,
++	GLAMO_CLOCK_MPEG_DG_X3CLK	= 0x0040,
++	GLAMO_CLOCK_MPEG_EN_X3CLK	= 0x0080,
++	GLAMO_CLOCK_MPEG_DG_X4CLK	= 0x0100,
++	GLAMO_CLOCK_MPEG_EN_X4CLK	= 0x0200,
++	GLAMO_CLOCK_MPEG_DG_X6CLK	= 0x0400,
++	GLAMO_CLOCK_MPEG_EN_X6CLK	= 0x0800,
++	GLAMO_CLOCK_MPEG_ENC_RESET	= 0x1000,
++	GLAMO_CLOCK_MPEG_DEC_RESET	= 0x2000,
++};
++
++enum glamo_reg_clock51 {
++	GLAMO_CLOCK_GEN51_EN_DIV_MCLK	= 0x0001,
++	GLAMO_CLOCK_GEN51_EN_DIV_SCLK	= 0x0002,
++	GLAMO_CLOCK_GEN51_EN_DIV_JCLK	= 0x0004,
++	GLAMO_CLOCK_GEN51_EN_DIV_DCLK	= 0x0008,
++	GLAMO_CLOCK_GEN51_EN_DIV_DMCLK	= 0x0010,
++	GLAMO_CLOCK_GEN51_EN_DIV_DHCLK	= 0x0020,
++	GLAMO_CLOCK_GEN51_EN_DIV_GCLK	= 0x0040,
++	GLAMO_CLOCK_GEN51_EN_DIV_TCLK	= 0x0080,
++	/* FIXME: higher bits */
++};
++
++enum glamo_reg_clock52 {
++	GLAMO_CLOCK_GEN52_EN_DIV_ACLK	= 0x0001,
++	GLAMO_CLOCK_GEN52_EN_DIV_AMCLK	= 0x0002,
++	GLAMO_CLOCK_GEN52_EN_DIV_OCLK	= 0x0004,
++	GLAMO_CLOCK_GEN52_EN_DIV_ZCLK	= 0x0008,
++	GLAMO_CLOCK_GEN52_EN_DIV_ICLK	= 0x0010,
++	/* FIXME: higher bits */
++};
++
++enum glamo_reg_hostbus2 {
++	GLAMO_HOSTBUS2_MMIO_EN_ISP	= 0x0001,
++	GLAMO_HOSTBUS2_MMIO_EN_JPEG	= 0x0002,
++	GLAMO_HOSTBUS2_MMIO_EN_MPEG	= 0x0004,
++	GLAMO_HOSTBUS2_MMIO_EN_LCD	= 0x0008,
++	GLAMO_HOSTBUS2_MMIO_EN_MMC	= 0x0010,
++	GLAMO_HOSTBUS2_MMIO_EN_MICROP0	= 0x0020,
++	GLAMO_HOSTBUS2_MMIO_EN_MICROP1	= 0x0040,
++	GLAMO_HOSTBUS2_MMIO_EN_CQ	= 0x0080,
++	GLAMO_HOSTBUS2_MMIO_EN_RISC	= 0x0100,
++	GLAMO_HOSTBUS2_MMIO_EN_2D	= 0x0200,
++	GLAMO_HOSTBUS2_MMIO_EN_3D	= 0x0400,
++};
++
++/* LCD Controller */
++
++#define REG_LCD(x)	(x)
++enum glamo_reg_lcd {
++	GLAMO_REG_LCD_MODE1		= REG_LCD(0x00),
++	GLAMO_REG_LCD_MODE2		= REG_LCD(0x02),
++	GLAMO_REG_LCD_MODE3		= REG_LCD(0x04),
++	GLAMO_REG_LCD_WIDTH		= REG_LCD(0x06),
++	GLAMO_REG_LCD_HEIGHT		= REG_LCD(0x08),
++	GLAMO_REG_LCD_POLARITY		= REG_LCD(0x0a),
++	GLAMO_REG_LCD_A_BASE1		= REG_LCD(0x0c),
++	GLAMO_REG_LCD_A_BASE2		= REG_LCD(0x0e),
++	GLAMO_REG_LCD_B_BASE1		= REG_LCD(0x10),
++	GLAMO_REG_LCD_B_BASE2		= REG_LCD(0x12),
++	GLAMO_REG_LCD_C_BASE1		= REG_LCD(0x14),
++	GLAMO_REG_LCD_C_BASE2		= REG_LCD(0x16),
++	GLAMO_REG_LCD_PITCH		= REG_LCD(0x18),
++	/* RES */
++	GLAMO_REG_LCD_HORIZ_TOTAL	= REG_LCD(0x1c),
++	/* RES */
++	GLAMO_REG_LCD_HORIZ_RETR_START	= REG_LCD(0x20),
++	/* RES */
++	GLAMO_REG_LCD_HORIZ_RETR_END	= REG_LCD(0x24),
++	/* RES */
++	GLAMO_REG_LCD_HORIZ_DISP_START	= REG_LCD(0x28),
++	/* RES */
++	GLAMO_REG_LCD_HORIZ_DISP_END	= REG_LCD(0x2c),
++	/* RES */
++	GLAMO_REG_LCD_VERT_TOTAL	= REG_LCD(0x30),
++	/* RES */
++	GLAMO_REG_LCD_VERT_RETR_START	= REG_LCD(0x34),
++	/* RES */
++	GLAMO_REG_LCD_VERT_RETR_END	= REG_LCD(0x38),
++	/* RES */
++	GLAMO_REG_LCD_VERT_DISP_START	= REG_LCD(0x3c),
++	/* RES */
++	GLAMO_REG_LCD_VERT_DISP_END	= REG_LCD(0x40),
++	/* RES */
++	GLAMO_REG_LCD_POL		= REG_LCD(0x44),
++	GLAMO_REG_LCD_DATA_START	= REG_LCD(0x46),
++	GLAMO_REG_LCD_FRATE_CONTRO	= REG_LCD(0x48),
++	GLAMO_REG_LCD_DATA_CMD_HDR	= REG_LCD(0x4a),
++	GLAMO_REG_LCD_SP_START		= REG_LCD(0x4c),
++	GLAMO_REG_LCD_SP_END		= REG_LCD(0x4e),
++	GLAMO_REG_LCD_CURSOR_BASE1	= REG_LCD(0x50),
++	GLAMO_REG_LCD_CURSOR_BASE2	= REG_LCD(0x52),
++	GLAMO_REG_LCD_CURSOR_PITCH	= REG_LCD(0x54),
++	GLAMO_REG_LCD_CURSOR_X_SIZE	= REG_LCD(0x56),
++	GLAMO_REG_LCD_CURSOR_Y_SIZE	= REG_LCD(0x58),
++	GLAMO_REG_LCD_CURSOR_X_POS	= REG_LCD(0x5a),
++	GLAMO_REG_LCD_CURSOR_Y_POS	= REG_LCD(0x5c),
++	GLAMO_REG_LCD_CURSOR_PRESET	= REG_LCD(0x5e),
++	GLAMO_REG_LCD_CURSOR_FG_COLOR	= REG_LCD(0x60),
++	/* RES */
++	GLAMO_REG_LCD_CURSOR_BG_COLOR	= REG_LCD(0x64),
++	/* RES */
++	GLAMO_REG_LCD_CURSOR_DST_COLOR	= REG_LCD(0x68),
++	/* RES */
++	GLAMO_REG_LCD_STATUS1		= REG_LCD(0x80),
++	GLAMO_REG_LCD_STATUS2		= REG_LCD(0x82),
++	GLAMO_REG_LCD_STATUS3		= REG_LCD(0x84),
++	GLAMO_REG_LCD_STATUS4		= REG_LCD(0x86),
++	/* RES */
++	GLAMO_REG_LCD_COMMAND1		= REG_LCD(0xa0),
++	GLAMO_REG_LCD_COMMAND2		= REG_LCD(0xa2),
++	/* RES */
++	GLAMO_REG_LCD_WFORM_DELAY1	= REG_LCD(0xb0),
++	GLAMO_REG_LCD_WFORM_DELAY2	= REG_LCD(0xb2),
++	/* RES */
++	GLAMO_REG_LCD_GAMMA_CORR	= REG_LCD(0x100),
++	/* RES */
++	GLAMO_REG_LCD_GAMMA_R_ENTRY01	= REG_LCD(0x110),
++	GLAMO_REG_LCD_GAMMA_R_ENTRY23	= REG_LCD(0x112),
++	GLAMO_REG_LCD_GAMMA_R_ENTRY45	= REG_LCD(0x114),
++	GLAMO_REG_LCD_GAMMA_R_ENTRY67	= REG_LCD(0x116),
++	GLAMO_REG_LCD_GAMMA_R_ENTRY8	= REG_LCD(0x118),
++	/* RES */
++	GLAMO_REG_LCD_GAMMA_G_ENTRY01	= REG_LCD(0x130),
++	GLAMO_REG_LCD_GAMMA_G_ENTRY23	= REG_LCD(0x132),
++	GLAMO_REG_LCD_GAMMA_G_ENTRY45	= REG_LCD(0x134),
++	GLAMO_REG_LCD_GAMMA_G_ENTRY67	= REG_LCD(0x136),
++	GLAMO_REG_LCD_GAMMA_G_ENTRY8	= REG_LCD(0x138),
++	/* RES */
++	GLAMO_REG_LCD_GAMMA_B_ENTRY01	= REG_LCD(0x150),
++	GLAMO_REG_LCD_GAMMA_B_ENTRY23	= REG_LCD(0x152),
++	GLAMO_REG_LCD_GAMMA_B_ENTRY45	= REG_LCD(0x154),
++	GLAMO_REG_LCD_GAMMA_B_ENTRY67	= REG_LCD(0x156),
++	GLAMO_REG_LCD_GAMMA_B_ENTRY8	= REG_LCD(0x158),
++	/* RES */
++	GLAMO_REG_LCD_SRAM_DRIVING1	= REG_LCD(0x160),
++	GLAMO_REG_LCD_SRAM_DRIVING2	= REG_LCD(0x162),
++	GLAMO_REG_LCD_SRAM_DRIVING3	= REG_LCD(0x164),
++};
++
++enum glamo_reg_lcd_mode1 {
++	GLAMO_LCD_MODE1_PWRSAVE		= 0x0001,
++	GLAMO_LCD_MODE1_PARTIAL_PRT	= 0x0002,
++	GLAMO_LCD_MODE1_HWFLIP		= 0x0004,
++	GLAMO_LCD_MODE1_LCD2		= 0x0008,
++	/* RES */
++	GLAMO_LCD_MODE1_PARTIAL_MODE	= 0x0020,
++	GLAMO_LCD_MODE1_CURSOR_DSTCOLOR	= 0x0040,
++	GLAMO_LCD_MODE1_PARTIAL_ENABLE	= 0x0080,
++	GLAMO_LCD_MODE1_TVCLK_IN_ENABLE	= 0x0100,
++	GLAMO_LCD_MODE1_HSYNC_HIGH_ACT	= 0x0200,
++	GLAMO_LCD_MODE1_VSYNC_HIGH_ACT	= 0x0400,
++	GLAMO_LCD_MODE1_HSYNC_FLIP	= 0x0800,
++	GLAMO_LCD_MODE1_GAMMA_COR_EN	= 0x1000,
++	GLAMO_LCD_MODE1_DITHER_EN	= 0x2000,
++	GLAMO_LCD_MODE1_CURSOR_EN	= 0x4000,
++	GLAMO_LCD_MODE1_ROTATE_EN	= 0x8000,
++};
++
++enum glamo_reg_lcd_mode2 {
++	GLAMO_LCD_MODE2_CRC_CHECK_EN	= 0x0001,
++	GLAMO_LCD_MODE2_DCMD_PER_LINE	= 0x0002,
++	GLAMO_LCD_MODE2_NOUSE_BDEF	= 0x0004,
++	GLAMO_LCD_MODE2_OUT_POS_MODE	= 0x0008,
++	GLAMO_LCD_MODE2_FRATE_CTRL_EN	= 0x0010,
++	GLAMO_LCD_MODE2_SINGLE_BUFFER	= 0x0020,
++	GLAMO_LCD_MODE2_SER_LSB_TO_MSB	= 0x0040,
++	/* FIXME */
++};
++
++enum glamo_reg_lcd_mode3 {
++	/* LCD color source data format */
++	GLAMO_LCD_SRC_RGB565		= 0x0000,
++	GLAMO_LCD_SRC_ARGB1555		= 0x4000,
++	GLAMO_LCD_SRC_ARGB4444		= 0x8000,
++	/* interface type */
++	GLAMO_LCD_MODE3_LCD		= 0x1000,
++	GLAMO_LCD_MODE3_RGB		= 0x0800,
++	GLAMO_LCD_MODE3_CPU		= 0x0000,
++	/* mode */
++	GLAMO_LCD_MODE3_RGB332		= 0x0000,
++	GLAMO_LCD_MODE3_RGB444		= 0x0100,
++	GLAMO_LCD_MODE3_RGB565		= 0x0200,
++	GLAMO_LCD_MODE3_RGB666		= 0x0300,
++	/* depth */
++	GLAMO_LCD_MODE3_6BITS		= 0x0000,
++	GLAMO_LCD_MODE3_8BITS		= 0x0010,
++	GLAMO_LCD_MODE3_9BITS		= 0x0020,
++	GLAMO_LCD_MODE3_16BITS		= 0x0030,
++	GLAMO_LCD_MODE3_18BITS		= 0x0040,
++};
++
++enum glamo_lcd_cmd_type {
++	GLAMO_LCD_CMD_TYPE_DISP		= 0x0000,
++	GLAMO_LCD_CMD_TYPE_PARALLEL	= 0x4000,
++	GLAMO_LCD_CMD_TYPE_SERIAL	= 0x8000,
++	GLAMO_LCD_CMD_TYPE_SERIAL_DIRECT= 0xc000,
++};
++#define GLAMO_LCD_CMD_TYPE_MASK		0xc000
++
++enum glamo_lcd_cmds {
++	GLAMO_LCD_CMD_DATA_DISP_FIRE	= 0x00,
++	GLAMO_LCD_CMD_DATA_DISP_SYNC	= 0x01,		/* RGB only */
++	/* switch to command mode, no display */
++	GLAMO_LCD_CMD_DATA_FIRE_NO_DISP	= 0x02,
++	/* display until VSYNC, switch to command */
++	GLAMO_LCD_CMD_DATA_FIRE_VSYNC	= 0x11,
++	/* display until HSYNC, switch to command */
++	GLAMO_LCD_CMD_DATA_FIRE_HSYNC	= 0x12,
++	/* display until VSYNC, 1 black frame, VSYNC, switch to command */
++	GLAMO_LCD_CMD_DATA_FIRE_VSYNC_B	= 0x13,
++	/* don't care about display and switch to command */
++	GLAMO_LCD_CMD_DATA_FIRE_FREE	= 0x14,		/* RGB only */
++	/* don't care about display, keep data display but disable data,
++	 * and switch to command */
++	GLAMO_LCD_CMD_DATA_FIRE_FREE_D	= 0x15,		/* RGB only */
++};
++
++enum glamo_core_revisions {
++	GLAMO_CORE_REV_A0		= 0x0000,
++	GLAMO_CORE_REV_A1		= 0x0001,
++	GLAMO_CORE_REV_A2		= 0x0002,
++	GLAMO_CORE_REV_A3		= 0x0003,
++};
++
++#define REG_ISP(x)		(GLAMO_REGOFS_ISP+(x))
++
++enum glamo_register_isp {
++	GLAMO_REG_ISP_EN1		= REG_ISP(0x00),
++	GLAMO_REG_ISP_EN2		= REG_ISP(0x02),
++	GLAMO_REG_ISP_EN3		= REG_ISP(0x04),
++	GLAMO_REG_ISP_EN4		= REG_ISP(0x06),
++	GLAMO_REG_ISP_CAP_0_ADDRL	= REG_ISP(0x08),
++	GLAMO_REG_ISP_CAP_0_ADDRH	= REG_ISP(0x0a),
++	GLAMO_REG_ISP_CAP_1_ADDRL	= REG_ISP(0x0c),
++	GLAMO_REG_ISP_CAP_1_ADDRH	= REG_ISP(0x0e),
++	GLAMO_REG_ISP_DEC_Y_ADDRL	= REG_ISP(0x10),
++	GLAMO_REG_ISP_DEC_Y_ADDRH	= REG_ISP(0x12),
++	GLAMO_REG_ISP_DEC_U_ADDRL	= REG_ISP(0x14),
++	GLAMO_REG_ISP_DEC_U_ADDRH	= REG_ISP(0x16),
++	GLAMO_REG_ISP_DEC_V_ADDRL	= REG_ISP(0x18),
++	GLAMO_REG_ISP_DEC_V_ADDRH	= REG_ISP(0x1a),
++	GLAMO_REG_ISP_CAP_SEG_HEIGHT	= REG_ISP(0x1c),
++	GLAMO_REG_ISP_CAP_PITCH		= REG_ISP(0x1e),
++	GLAMO_REG_ISP_CAP_HEIGHT	= REG_ISP(0x20),
++	GLAMO_REG_ISP_CAP_WIDTH		= REG_ISP(0x22),
++	GLAMO_REG_ISP_DEC_PITCH_Y	= REG_ISP(0x24),
++	GLAMO_REG_ISP_DEC_PITCH_UV	= REG_ISP(0x26),
++	GLAMO_REG_ISP_DEC_HEIGHT	= REG_ISP(0x28),
++	GLAMO_REG_ISP_DEC_WIDTH		= REG_ISP(0x2a),
++	GLAMO_REG_ISP_ONFLY_MODE1	= REG_ISP(0x2c),
++	GLAMO_REG_ISP_ONFLY_MODE2	= REG_ISP(0x2e),
++	GLAMO_REG_ISP_ONFLY_MODE3	= REG_ISP(0x30),
++	GLAMO_REG_ISP_ONFLY_MODE4	= REG_ISP(0x32),
++	GLAMO_REG_ISP_ONFLY_MODE5	= REG_ISP(0x34),
++	//
++	GLAMO_REG_ISP_YUV2RGB_11	= REG_ISP(0x50),
++	GLAMO_REG_ISP_YUV2RGB_21	= REG_ISP(0x52),
++	GLAMO_REG_ISP_YUV2RGB_32	= REG_ISP(0x54),
++	GLAMO_REG_ISP_YUV2RGB_33	= REG_ISP(0x56),
++	GLAMO_REG_ISP_YUV2RGB_RG	= REG_ISP(0x58),
++	GLAMO_REG_ISP_YUV2RGB_B		= REG_ISP(0x5a),
++	//
++	GLAMO_REG_ISP_PORT1_SCALEH	= REG_ISP(0x76),
++	GLAMO_REG_ISP_PORT1_SCALEV	= REG_ISP(0x78),
++	GLAMO_REG_ISP_PORT2_SCALEH	= REG_ISP(0x7a),
++	GLAMO_REG_ISP_PORT2_SCALEV	= REG_ISP(0x7c),
++	GLAMO_REG_ISP_DEC_SCALEH	= REG_ISP(0x7e),
++	GLAMO_REG_ISP_DEC_SCALEV	= REG_ISP(0x80),
++	GLAMO_REG_ISP_TURBO		= REG_ISP(0x82),
++	GLAMO_REG_ISP_PORT1_CAP_EN	= REG_ISP(0x84),
++	GLAMO_REG_ISP_PORT1_CAP_0_ADDRL	= REG_ISP(0x86),
++	GLAMO_REG_ISP_PORT1_CAP_0_ADDRH	= REG_ISP(0x88),
++	GLAMO_REG_ISP_PORT1_CAP_1_ADDRL	= REG_ISP(0x8a),
++	GLAMO_REG_ISP_PORT1_CAP_1_ADDRH	= REG_ISP(0x8c),
++	GLAMO_REG_ISP_PORT1_CAP_WIDTH	= REG_ISP(0x8e),
++	GLAMO_REG_ISP_PORT1_CAP_HEIGHT	= REG_ISP(0x90),
++	GLAMO_REG_ISP_PORT1_CAP_PITCH	= REG_ISP(0x92),
++	GLAMO_REG_ISP_PORT1_CAP_CLIP_L	= REG_ISP(0x94),
++	GLAMO_REG_ISP_PORT1_CAP_CLIP_R	= REG_ISP(0x96),
++	GLAMO_REG_ISP_PORT1_CAP_CLIP_T	= REG_ISP(0x98),
++	GLAMO_REG_ISP_PORT1_CAP_CLIP_B	= REG_ISP(0x9a),
++	GLAMO_REG_ISP_PORT1_DEC_EN	= REG_ISP(0x9c),
++	GLAMO_REG_ISP_PORT1_DEC_0_ADDRL	= REG_ISP(0x9e),
++	GLAMO_REG_ISP_PORT1_DEC_0_ADDRH	= REG_ISP(0xa0),
++	GLAMO_REG_ISP_PORT1_DEC_1_ADDRL	= REG_ISP(0xa2),
++	GLAMO_REG_ISP_PORT1_DEC_1_ADDRH	= REG_ISP(0xa4),
++	GLAMO_REG_ISP_PORT1_DEC_WIDTH	= REG_ISP(0xa6),
++	GLAMO_REG_ISP_PORT1_DEC_HEIGHT	= REG_ISP(0xa8),
++	GLAMO_REG_ISP_PORT1_DEC_PITCH	= REG_ISP(0xaa),
++	GLAMO_REG_ISP_PORT1_DEC_CLIP_L	= REG_ISP(0xac),
++	GLAMO_REG_ISP_PORT1_DEC_CLIP_R	= REG_ISP(0xae),
++	GLAMO_REG_ISP_PORT1_DEC_CLIP_T	= REG_ISP(0xb0),
++	GLAMO_REG_ISP_PORT1_DEC_CLIP_B	= REG_ISP(0xb2),
++	GLAMO_REG_ISP_PORT2_EN		= REG_ISP(0xb4),
++	GLAMO_REG_ISP_PORT2_0_Y_ADDRL	= REG_ISP(0xb6),
++	GLAMO_REG_ISP_PORT2_0_Y_ADDRH	= REG_ISP(0xb8),
++	GLAMO_REG_ISP_PORT2_0_U_ADDRL	= REG_ISP(0xba),
++	GLAMO_REG_ISP_PORT2_0_U_ADDRH	= REG_ISP(0xbc),
++	GLAMO_REG_ISP_PORT2_0_V_ADDRL	= REG_ISP(0xbe),
++	GLAMO_REG_ISP_PORT2_0_V_ADDRH	= REG_ISP(0xc0),
++	GLAMO_REG_ISP_PORT2_1_Y_ADDRL	= REG_ISP(0xc2),
++	GLAMO_REG_ISP_PORT2_1_Y_ADDRH	= REG_ISP(0xc4),
++	GLAMO_REG_ISP_PORT2_1_U_ADDRL	= REG_ISP(0xc6),
++	GLAMO_REG_ISP_PORT2_1_U_ADDRH	= REG_ISP(0xc8),
++	GLAMO_REG_ISP_PORT2_1_V_ADDRL	= REG_ISP(0xca),
++	GLAMO_REG_ISP_PORT2_1_V_ADDRH	= REG_ISP(0xcc),
++	GLAMO_REG_ISP_PORT2_2_Y_ADDRL	= REG_ISP(0xce),
++	GLAMO_REG_ISP_PORT2_2_Y_ADDRH	= REG_ISP(0xd0),
++	GLAMO_REG_ISP_PORT2_2_U_ADDRL	= REG_ISP(0xd2),
++	GLAMO_REG_ISP_PORT2_2_U_ADDRH	= REG_ISP(0xd4),
++	GLAMO_REG_ISP_PORT2_2_V_ADDRL	= REG_ISP(0xd6),
++	GLAMO_REG_ISP_PORT2_2_V_ADDRH	= REG_ISP(0xd8),
++	GLAMO_REG_ISP_PORT2_WIDTH	= REG_ISP(0xda),
++	GLAMO_REG_ISP_PORT2_HEIGHT	= REG_ISP(0xdc),
++	GLAMO_REG_ISP_PORT2_Y_PITCH	= REG_ISP(0xde),
++	GLAMO_REG_ISP_PORT2_UV_PITCH	= REG_ISP(0xe0),
++	//
++	GLAMO_REG_ISP_RGB2YUV_11_12	= REG_ISP(0xf6),
++	GLAMO_REG_ISP_RGB2YUV_13_21	= REG_ISP(0xf8),
++	GLAMO_REG_ISP_RGB2YUV_22_23	= REG_ISP(0xfa),
++	GLAMO_REG_ISP_RGB2YUV_31_32	= REG_ISP(0xfc),
++	GLAMO_REG_ISP_RGB2YUV_33	= REG_ISP(0xfe),
++	//
++	GLAMO_REG_ISP_PORT1_SCALEH_MATRIX	= REG_ISP(0x10c),
++	//
++	GLAMO_REG_ISP_PORT1_SCALEV_MATRIX	= REG_ISP(0x120),
++	//
++	GLAMO_REG_ISP_PORT2_SCALEH_MATRIX	= REG_ISP(0x134),
++	//
++	GLAMO_REG_ISP_PORT2_SCALEV_MATRIX	= REG_ISP(0x148),
++	//
++	GLAMO_REG_ISP_DEC_SCALEH_MATRIX		= REG_ISP(0x15c),
++	//
++	GLAMO_REG_ISP_DEC_SCALEV_MATRIX		= REG_ISP(0x170),
++	//
++	GLAMO_REG_ISP_STATUS			= REG_ISP(0x184),
++};
++
++enum glamo_reg_isp_en1 {
++	GLAMO_ISP_EN1_FIRE_ISP		= 0x0001,
++	GLAMO_ISP_EN1_FIRE_CAP		= 0x0002,
++	GLAMO_ISP_EN1_VIDEO_CONF	= 0x0004,
++	GLAMO_ISP_EN1_BAYER_SRC		= 0x0008,
++	//
++	GLAMO_ISP_EN1_YUV_PACK		= 0x0040,
++	GLAMO_ISP_EN1_PLANE_MODE	= 0x0080,
++	GLAMO_ISP_EN1_YUV_INPUT		= 0x0100,
++	GLAMO_ISP_EN1_YUV420		= 0x0200,
++	//
++};
++
++enum glamo_reg_isp_en3 {
++	//
++	GLAMO_ISP_EN3_SCALE_IMPROVE	= 0x0040,
++	GLAMO_ISP_EN3_PLANE_MODE	= 0x0080,
++	GLAMO_ISP_EN3_YUV_INPUT		= 0x0100,
++	GLAMO_ISP_EN3_YUV420		= 0x0200,
++	//
++};
++
++enum glamo_reg_isp_port1_en {
++	GLAMO_ISP_PORT1_EN_OUTPUT	= 0x0001,
++//	GLAMO_ISP_PORT1_EN_SCALE	= 0x0002,
++	GLAMO_ISP_PORT1_EN_CLIP		= 0x0004,
++	GLAMO_ISP_PORT1_EN_CLIP_OUT	= 0x0008,
++	GLAMO_ISP_PORT1_EN_DUAL_BUF	= 0x0010,
++};
++
++enum glamo_reg_isp_port2_en {
++	GLAMO_ISP_PORT2_EN_OUTPUT	= 0x0001,
++	GLAMO_ISP_PORT2_EN_SCALE	= 0x0002,
++	GLAMO_ISP_PORT2_EN_JPEG		= 0x0010,
++	GLAMO_ISP_PORT2_EN_MPEG		= 0x0020,
++	GLAMO_ISP_PORT2_EN_ENCODE	= 0x0040,
++	GLAMO_ISP_PORT2_EN_DECODE	= 0x0080,
++};
++
++#define REG_CQ(x)		(GLAMO_REGOFS_CMDQUEUE+(x))
++
++enum glamo_register_cq {
++	GLAMO_REG_CQ_BASE_ADDRL		= REG_CQ(0x00),
++	GLAMO_REG_CQ_BASE_ADDRH		= REG_CQ(0x02),
++	GLAMO_REG_CQ_LEN		= REG_CQ(0x04),
++	GLAMO_REG_CQ_WRITE_ADDRL	= REG_CQ(0x06),
++	GLAMO_REG_CQ_WRITE_ADDRH	= REG_CQ(0x08),
++	GLAMO_REG_CQ_FLIP		= REG_CQ(0x0a),
++	GLAMO_REG_CQ_CONTROL		= REG_CQ(0x0c),
++	GLAMO_REG_CQ_READ_ADDRL		= REG_CQ(0x0e),
++	GLAMO_REG_CQ_READ_ADDRH		= REG_CQ(0x10),
++	GLAMO_REG_CQ_STATUS		= REG_CQ(0x12),
++};
++
++#define REG_2D(x)		(GLAMO_REGOFS_2D+(x))
++
++enum glamo_register_2d {
++	GLAMO_REG_2D_SRC_ADDRL		= REG_2D(0x00),
++	GLAMO_REG_2D_SRC_ADDRH		= REG_2D(0x02),
++	GLAMO_REG_2D_SRC_PITCH		= REG_2D(0x04),
++	GLAMO_REG_2D_SRC_X		= REG_2D(0x06),
++	GLAMO_REG_2D_SRC_Y		= REG_2D(0x08),
++	GLAMO_REG_2D_DST_X		= REG_2D(0x0a),
++	GLAMO_REG_2D_DST_Y		= REG_2D(0x0c),
++	GLAMO_REG_2D_DST_ADDRL		= REG_2D(0x0e),
++	GLAMO_REG_2D_DST_ADDRH		= REG_2D(0x10),
++	GLAMO_REG_2D_DST_PITCH		= REG_2D(0x12),
++	GLAMO_REG_2D_DST_HEIGHT		= REG_2D(0x14),
++	GLAMO_REG_2D_RECT_WIDTH		= REG_2D(0x16),
++	GLAMO_REG_2D_RECT_HEIGHT	= REG_2D(0x18),
++	GLAMO_REG_2D_PAT_ADDRL		= REG_2D(0x1a),
++	GLAMO_REG_2D_PAT_ADDRH		= REG_2D(0x1c),
++	GLAMO_REG_2D_PAT_FG		= REG_2D(0x1e),
++	GLAMO_REG_2D_PAT_BG		= REG_2D(0x20),
++	GLAMO_REG_2D_SRC_FG		= REG_2D(0x22),
++	GLAMO_REG_2D_SRC_BG		= REG_2D(0x24),
++	GLAMO_REG_2D_MASK1		= REG_2D(0x26),
++	GLAMO_REG_2D_MASK2		= REG_2D(0x28),
++	GLAMO_REG_2D_MASK3		= REG_2D(0x2a),
++	GLAMO_REG_2D_MASK4		= REG_2D(0x2c),
++	GLAMO_REG_2D_ROT_X		= REG_2D(0x2e),
++	GLAMO_REG_2D_ROT_Y		= REG_2D(0x30),
++	GLAMO_REG_2D_LEFT_CLIP		= REG_2D(0x32),
++	GLAMO_REG_2D_TOP_CLIP		= REG_2D(0x34),
++	GLAMO_REG_2D_RIGHT_CLIP		= REG_2D(0x36),
++	GLAMO_REG_2D_BOTTOM_CLIP	= REG_2D(0x38),
++	GLAMO_REG_2D_COMMAND1		= REG_2D(0x3A),
++	GLAMO_REG_2D_COMMAND2		= REG_2D(0x3C),
++	GLAMO_REG_2D_COMMAND3		= REG_2D(0x3E),
++	GLAMO_REG_2D_SAFE		= REG_2D(0x40),
++	GLAMO_REG_2D_STATUS		= REG_2D(0x42),
++	GLAMO_REG_2D_ID1		= REG_2D(0x44),
++	GLAMO_REG_2D_ID2		= REG_2D(0x46),
++	GLAMO_REG_2D_ID3		= REG_2D(0x48),
++};
++
++#endif /* _GLAMO_REGS_H */
+Index: xserver/hw/kdrive/glamo/glamo.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ xserver/hw/kdrive/glamo/glamo.c	2007-09-26 17:44:47.000000000 +0800
+@@ -0,0 +1,498 @@
++/*
++ * Copyright © 2007 OpenMoko, Inc.
++ *
++ * This driver is based on Xati,
++ * Copyright © 2003 Eric Anholt
++ *
++ * Permission to use, copy, modify, distribute, and sell this software and its
++ * documentation for any purpose is hereby granted without fee, provided that
++ * the above copyright notice appear in all copies and that both that copyright
++ * notice and this permission notice appear in supporting documentation, and
++ * that the name of the copyright holders not be used in advertising or
++ * publicity pertaining to distribution of the software without specific,
++ * written prior permission.  The copyright holders make no representations
++ * about the suitability of this software for any purpose.  It is provided "as
++ * is" without express or implied warranty.
++ *
++ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
++ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
++ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
++ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
++ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
++ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
++ * OF THIS SOFTWARE.
++ */
++
++#ifdef HAVE_CONFIG_H
++#include <kdrive-config.h>
++#endif
++#include "glamo.h"
++#if defined(USE_DRI) && defined(GLXEXT)
++#include "glamo_sarea.h"
++#endif
++
++static Bool
++GLAMOCardInit(KdCardInfo *card)
++{
++	GLAMOCardInfo *glamoc;
++	Bool initialized = FALSE;
++
++	glamoc = xcalloc(sizeof(GLAMOCardInfo), 1);
++	if (glamoc == NULL)
++		return FALSE;
++
++#ifdef KDRIVEFBDEV
++	if (!initialized && fbdevInitialize(card, &glamoc->backend_priv.fbdev)) {
++		glamoc->use_fbdev = TRUE;
++		initialized = TRUE;
++		glamoc->backend_funcs.cardfini = fbdevCardFini;
++		glamoc->backend_funcs.scrfini = fbdevScreenFini;
++		glamoc->backend_funcs.initScreen = fbdevInitScreen;
++		glamoc->backend_funcs.finishInitScreen = fbdevFinishInitScreen;
++		glamoc->backend_funcs.createRes = fbdevCreateResources;
++		glamoc->backend_funcs.preserve = fbdevPreserve;
++		glamoc->backend_funcs.restore = fbdevRestore;
++		glamoc->backend_funcs.dpms = fbdevDPMS;
++		glamoc->backend_funcs.enable = fbdevEnable;
++		glamoc->backend_funcs.disable = fbdevDisable;
++		glamoc->backend_funcs.getColors = fbdevGetColors;
++		glamoc->backend_funcs.putColors = fbdevPutColors;
++#ifdef RANDR
++		glamoc->backend_funcs.randrSetConfig = fbdevRandRSetConfig;
++#endif
++	}
++#endif
++#ifdef KDRIVEVESA
++	if (!initialized && vesaInitialize(card, &glamoc->backend_priv.vesa)) {
++		glamoc->use_vesa = TRUE;
++		initialized = TRUE;
++		glamoc->backend_funcs.cardfini = vesaCardFini;
++		glamoc->backend_funcs.scrfini = vesaScreenFini;
++		glamoc->backend_funcs.initScreen = vesaInitScreen;
++		glamoc->backend_funcs.finishInitScreen = vesaFinishInitScreen;
++		glamoc->backend_funcs.createRes = vesaCreateResources;
++		glamoc->backend_funcs.preserve = vesaPreserve;
++		glamoc->backend_funcs.restore = vesaRestore;
++		glamoc->backend_funcs.dpms = vesaDPMS;
++		glamoc->backend_funcs.enable = vesaEnable;
++		glamoc->backend_funcs.disable = vesaDisable;
++		glamoc->backend_funcs.getColors = vesaGetColors;
++		glamoc->backend_funcs.putColors = vesaPutColors;
++#ifdef RANDR
++		glamoc->backend_funcs.randrSetConfig = vesaRandRSetConfig;
++#endif
++	}
++#endif
++
++	if (!initialized || !GLAMOMapReg(card, glamoc)) {
++		xfree(glamoc);
++		return FALSE;
++	}
++
++#ifdef USE_DRI
++	/* We demand identification by busid, not driver name */
++	glamoc->drmFd = drmOpen(NULL, glamoc->busid);
++	if (glamoc->drmFd < 0)
++		ErrorF("Failed to open DRM, DRI disabled.\n");
++#endif /* USE_DRI */
++
++	card->driver = glamoc;
++
++	glamoc->is_3362 = TRUE;
++	ErrorF("Using GLAMO 3362 card\n");
++
++	return TRUE;
++}
++
++static void
++GLAMOCardFini(KdCardInfo *card)
++{
++	GLAMOCardInfo *glamoc = (GLAMOCardInfo *)card->driver;
++
++	GLAMOUnmapReg(card, glamoc);
++	glamoc->backend_funcs.cardfini(card);
++}
++
++/*
++ * Once screen->off_screen_base is set, this function
++ * allocates the remaining memory appropriately
++ */
++
++static void
++GLAMOSetOffscreen (KdScreenInfo *screen)
++{
++	GLAMOCardInfo(screen);
++#if defined(USE_DRI) && defined(GLXEXT)
++	GLAMOScreenInfo *glamos = (GLAMOScreenInfo *)screen->driver;
++	int l;
++#endif
++	int screen_size;
++	char *mmio = glamoc->reg_base;
++
++	/* check (and adjust) pitch */
++	if (mmio)
++	{
++		int	byteStride = screen->fb[0].byteStride;
++		int	bitStride;
++		int	pixelStride;
++		int	bpp = screen->fb[0].bitsPerPixel;
++
++		/*
++		 * Ensure frame buffer is correctly aligned
++		 */
++		if (byteStride & 0x3f)
++		{
++			byteStride = (byteStride + 0x3f) & ~0x3f;
++			bitStride = byteStride * 8;
++			pixelStride = bitStride / bpp;
++
++			screen->fb[0].byteStride = byteStride;
++			screen->fb[0].pixelStride = pixelStride;
++		}
++	}
++
++	screen_size = screen->fb[0].byteStride * screen->height;
++
++	screen->off_screen_base = screen_size;
++
++#if defined(USE_DRI) && defined(GLXEXT)
++	/* Reserve a static area for the back buffer the same size as the
++	 * visible screen.  XXX: This would be better initialized in glamo_dri.c
++	 * when GLX is set up, but the offscreen memory manager's allocations
++	 * don't last through VT switches, while the kernel's understanding of
++	 * offscreen locations does.
++	 */
++	glamos->frontOffset = 0;
++	glamos->frontPitch = screen->fb[0].byteStride;
++
++	if (screen->off_screen_base + screen_size <= screen->memory_size) {
++		glamos->backOffset = screen->off_screen_base;
++		glamos->backPitch = screen->fb[0].byteStride;
++		screen->off_screen_base += screen_size;
++	}
++
++	/* Reserve the depth span for Rage 128 */
++	if (!glamoc->is_3362 && screen->off_screen_base +
++	    screen->fb[0].byteStride <= screen->memory_size) {
++		glamos->spanOffset = screen->off_screen_base;
++		screen->off_screen_base += screen->fb[0].byteStride;
++	}
++
++	/* Reserve the static depth buffer, which happens to be the same
++	 * bitsPerPixel as the screen.
++	 */
++	if (screen->off_screen_base + screen_size <= screen->memory_size) {
++		glamos->depthOffset = screen->off_screen_base;
++		glamos->depthPitch = screen->fb[0].byteStride;
++		screen->off_screen_base += screen_size;
++	}
++
++	/* Reserve approx. half of remaining offscreen memory for local
++	 * textures.  Round down to a whole number of texture regions.