gcc 4.2.1: add patches for maverick crunch on ep93xx (That's an FPU)

33 files changed, 3031 insertions, 2 deletions

diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-20000320.patch b/packages/gcc/gcc-4.2.1/arm-crunch-20000320.patch
new file mode 100644
index 0000000000..3fb0da7670
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-20000320.patch
@@ -0,0 +1,11 @@
+--- gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c.original	2007-06-07 16:33:44.000000000 +1000
++++ gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c	2007-06-07 16:34:05.000000000 +1000
+@@ -49,7 +49,7 @@
+     exit (0);
+   
+   c(0x3690000000000000ULL, 0x00000000U);
+-#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__)
++#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__) && ! (defined __MAVERICK__)
+   /* The ARM always stores FP numbers in big-wordian format,
+      even when running in little-byteian mode.  */
+   c(0x0000000136900000ULL, 0x00000001U);
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-32bit-disable.patch b/packages/gcc/gcc-4.2.1/arm-crunch-32bit-disable.patch
new file mode 100644
index 0000000000..88eaee322d
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-32bit-disable.patch
@@ -0,0 +1,85 @@
+--- gcc-4.1.2/gcc/config/arm/cirrus.md-integer	2007-06-15 09:01:37.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md	2007-06-15 09:04:45.000000000 +1000
+@@ -149,7 +149,7 @@
+ 	  (match_operand:SI          1 "cirrus_fp_register"  "0")
+ 	  (mult:SI (match_operand:SI 2 "cirrus_fp_register"  "v")
+ 		   (match_operand:SI 3 "cirrus_fp_register"  "v"))))]
+-  "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfmsc32%?\\t%V0, %V2, %V3"
+   [(set_attr "type" "mav_farith")
+    (set_attr "cirrus" "normal")]
+@@ -305,7 +305,7 @@
+   [(set (match_operand:SF           0 "cirrus_fp_register" "=v")
+  	(float:SF (match_operand:SI 1 "s_register_operand"  "r")))
+    (clobber (match_scratch:DF 2 "=v"))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
+   [(set_attr "length" "8")
+    (set_attr "cirrus" "move")]
+@@ -315,7 +315,7 @@
+   [(set (match_operand:DF           0 "cirrus_fp_register" "=v")
+ 	(float:DF (match_operand:SI 1 "s_register_operand" "r")))
+    (clobber (match_scratch:DF 2 "=v"))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
+   [(set_attr "length" "8")
+    (set_attr "cirrus" "move")]
+@@ -339,7 +339,7 @@
+   [(set (match_operand:SI         0 "s_register_operand" "=r")
+ 	(fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register"  "v"))))
+    (clobber (match_scratch:DF     2                      "=v"))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
+   [(set_attr "length" "8")
+    (set_attr "cirrus" "normal")]
+@@ -349,7 +349,7 @@
+   [(set (match_operand:SI         0 "s_register_operand" "=r")
+ 	(fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register"  "v"))))
+    (clobber (match_scratch:DF     2                      "=v"))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
+   [(set_attr "length" "8")
+    (set_attr "cirrus" "normal")]
+--- gcc-4.1.2/gcc/config/arm/arm.md-trunc	2007-06-15 10:56:13.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md	2007-06-15 11:01:22.000000000 +1000
+@@ -3130,7 +3130,7 @@
+ 	(float:SF (match_operand:SI 1 "s_register_operand" "")))]
+   "TARGET_ARM && TARGET_HARD_FLOAT"
+   "
+-  if (TARGET_MAVERICK)
++  if (TARGET_MAVERICK && 0)
+     {
+       emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
+       DONE;
+@@ -3142,7 +3142,7 @@
+ 	(float:DF (match_operand:SI 1 "s_register_operand" "")))]
+   "TARGET_ARM && TARGET_HARD_FLOAT"
+   "
+-  if (TARGET_MAVERICK)
++  if (TARGET_MAVERICK && 0)
+     {
+       emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
+       DONE;
+@@ -3154,7 +3154,7 @@
+ 	(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand"  ""))))]
+   "TARGET_ARM && TARGET_HARD_FLOAT"
+   "
+-  if (TARGET_MAVERICK)
++  if (TARGET_MAVERICK && 0)
+     {
+       if (!cirrus_fp_register (operands[0], SImode))
+         operands[0] = force_reg (SImode, operands[0]);
+@@ -3170,7 +3170,7 @@
+ 	(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand"  ""))))]
+   "TARGET_ARM && TARGET_HARD_FLOAT"
+   "
+-  if (TARGET_MAVERICK)
++  if (TARGET_MAVERICK && 0)
+     {
+       if (!cirrus_fp_register (operands[1], DFmode))
+         operands[1] = force_reg (DFmode, operands[0]);
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable-4.2.0.patch b/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable-4.2.0.patch
new file mode 100644
index 0000000000..60b17852bd
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable-4.2.0.patch
@@ -0,0 +1,169 @@
+--- gcc-4.1.2/gcc/config/arm/cirrus.md-integer	2007-06-15 09:01:37.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md	2007-06-15 09:04:45.000000000 +1000
+@@ -34,7 +34,7 @@
+   [(set (match_operand:DI          0 "cirrus_fp_register" "=v")
+ 	(plus:DI (match_operand:DI 1 "cirrus_fp_register"  "v")
+ 		 (match_operand:DI 2 "cirrus_fp_register"  "v")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfadd64%?\\t%V0, %V1, %V2"
+   [(set_attr "type" "mav_farith")
+    (set_attr "cirrus" "normal")]
+@@ -74,7 +74,7 @@
+   [(set (match_operand:DI           0 "cirrus_fp_register" "=v")
+ 	(minus:DI (match_operand:DI 1 "cirrus_fp_register"  "v")
+ 		  (match_operand:DI 2 "cirrus_fp_register"  "v")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfsub64%?\\t%V0, %V1, %V2"
+   [(set_attr "type" "mav_farith")
+    (set_attr "cirrus" "normal")]
+@@ -124,7 +124,7 @@
+   [(set (match_operand:DI          0 "cirrus_fp_register" "=v")
+ 	(mult:DI (match_operand:DI 2 "cirrus_fp_register"  "v")
+ 		 (match_operand:DI 1 "cirrus_fp_register"  "v")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfmul64%?\\t%V0, %V1, %V2"
+   [(set_attr "type" "mav_dmult")
+    (set_attr "cirrus" "normal")]
+@@ -206,7 +206,7 @@
+   [(set (match_operand:DI            0 "cirrus_fp_register" "=v")
+ 	(ashift:DI (match_operand:DI 1 "cirrus_fp_register"  "v")
+ 		   (match_operand:SI 2 "register_operand"    "r")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfrshl64%?\\t%V1, %V0, %s2"
+   [(set_attr "cirrus" "normal")]
+ )
+@@ -215,7 +215,7 @@
+   [(set (match_operand:DI            0 "cirrus_fp_register" "=v")
+ 	(ashift:DI (match_operand:DI 1 "cirrus_fp_register"  "v")
+ 		   (match_operand:SI 2 "cirrus_shift_const"  "")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfsh64%?\\t%V0, %V1, #%s2"
+   [(set_attr "cirrus" "normal")]
+ )
+@@ -224,7 +224,7 @@
+   [(set (match_operand:DI            0 "cirrus_fp_register" "=v")
+ 	(ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register"  "v")
+ 		     (match_operand:SI 2 "cirrus_shift_const"  "")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfsh64%?\\t%V0, %V1, #-%s2"
+   [(set_attr "cirrus" "normal")]
+ )
+@@ -232,7 +232,7 @@
+ (define_insn "*cirrus_absdi2"
+   [(set (match_operand:DI         0 "cirrus_fp_register" "=v")
+ 	(abs:DI (match_operand:DI 1 "cirrus_fp_register"  "v")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfabs64%?\\t%V0, %V1"
+   [(set_attr "cirrus" "normal")]
+ )
+@@ -238,11 +238,12 @@
+ )
+ 
+ ;; This doesn't really clobber ``cc''.  Fixme: aldyh.  
++;; maybe buggy?
+ (define_insn "*cirrus_negdi2"
+   [(set (match_operand:DI         0 "cirrus_fp_register" "=v")
+ 	(neg:DI (match_operand:DI 1 "cirrus_fp_register"  "v")))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfneg64%?\\t%V0, %V1"
+   [(set_attr "cirrus" "normal")]
+ )
+@@ -324,14 +324,14 @@
+ (define_insn "floatdisf2"
+   [(set (match_operand:SF           0 "cirrus_fp_register" "=v")
+ 	(float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfcvt64s%?\\t%V0, %V1"
+   [(set_attr "cirrus" "normal")])
+ 
+ (define_insn "floatdidf2"
+   [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
+ 	(float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfcvt64d%?\\t%V0, %V1"
+   [(set_attr "cirrus" "normal")])
+ 
+@@ -376,7 +376,7 @@
+ (define_insn "*cirrus_arm_movdi"
+   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
+ 	(match_operand:DI 1 "di_operand"              "rIK,mi,r,r,v,mi,v,v"))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "*
+   {
+   switch (which_alternative)
+--- gcc-4.1.2/gcc/config/arm/arm.md-64	2007-06-15 11:37:42.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md	2007-06-15 11:40:45.000000000 +1000
+@@ -357,7 +357,7 @@
+     (clobber (reg:CC CC_REGNUM))])]
+   "TARGET_EITHER"
+   "
+-  if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
++  if (TARGET_HARD_FLOAT && TARGET_MAVERICK && 0)
+     {
+       if (!cirrus_fp_register (operands[0], DImode))
+         operands[0] = force_reg (DImode, operands[0]);
+@@ -393,7 +393,7 @@
+ 	(plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
+ 		 (match_operand:DI 2 "s_register_operand" "r,  0")))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
++  "TARGET_ARM"
+   "#"
+   "TARGET_ARM && reload_completed"
+   [(parallel [(set (reg:CC_C CC_REGNUM)
+@@ -421,7 +421,7 @@
+ 		  (match_operand:SI 2 "s_register_operand" "r,r"))
+ 		 (match_operand:DI 1 "s_register_operand" "r,0")))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
++  "TARGET_ARM"
+   "#"
+   "TARGET_ARM && reload_completed"
+   [(parallel [(set (reg:CC_C CC_REGNUM)
+@@ -450,7 +450,7 @@
+ 		  (match_operand:SI 2 "s_register_operand" "r,r"))
+ 		 (match_operand:DI 1 "s_register_operand" "r,0")))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
++  "TARGET_ARM"
+   "#"
+   "TARGET_ARM && reload_completed"
+   [(parallel [(set (reg:CC_C CC_REGNUM)
+@@ -838,7 +838,7 @@
+   if (TARGET_HARD_FLOAT && TARGET_MAVERICK
+       && TARGET_ARM
+       && cirrus_fp_register (operands[0], DImode)
+-      && cirrus_fp_register (operands[1], DImode))
++      && cirrus_fp_register (operands[1], DImode) && 0)
+     {
+       emit_insn (gen_cirrus_subdi3 (operands[0], operands[1], operands[2]));
+       DONE;
+@@ -2599,7 +2599,7 @@
+            values to iwmmxt regs and back.  */
+         FAIL;
+     }
+-  else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK))
++  else if (!TARGET_REALLY_IWMMXT)
+     FAIL;
+   "
+ )
+@@ -4215,7 +4215,6 @@
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r")
+ 	(match_operand:DI 1 "general_operand"      "l, I,J,>,l,mi,l,*r"))]
+   "TARGET_THUMB
+-   && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
+    && (   register_operand (operands[0], DImode)
+        || register_operand (operands[1], DImode))"
+   "*
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable0.patch b/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable0.patch
new file mode 100644
index 0000000000..95abf68a60
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable0.patch
@@ -0,0 +1,47 @@
+diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md
+--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md	2006-09-28 03:10:22.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md	2007-05-15 09:53:21.000000000 +1000
+@@ -6865,10 +6877,12 @@
+ )
+ 
+ ;; Cirrus DI compare instruction
++;; This is disabled and left go through ARM core registers, because currently
++;; Crunch coprocessor does only signed comparison.
+ (define_expand "cmpdi"
+   [(match_operand:DI 0 "cirrus_fp_register" "")
+    (match_operand:DI 1 "cirrus_fp_register" "")]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0"
+   "{
+      arm_compare_op0 = operands[0];
+      arm_compare_op1 = operands[1];
+@@ -6879,7 +6893,7 @@
+   [(set (reg:CC CC_REGNUM)
+ 	(compare:CC (match_operand:DI 0 "cirrus_fp_register" "v")
+ 		    (match_operand:DI 1 "cirrus_fp_register" "v")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0"
+   "cfcmp64%?\\tr15, %V0, %V1"
+   [(set_attr "type"   "mav_farith")
+    (set_attr "cirrus" "compare")]
+@@ -10105,6 +10119,7 @@
+   [(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_PROLOGUE_USE)]
+   ""
+   "%@ %0 needed for prologue"
++  [(set_attr "length" "0")]
+ )
+ 
+ 
+diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md gcc-4.1.2/gcc/config/arm/cirrus.md
+--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md	2005-06-25 11:22:41.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md	2007-05-15 09:55:29.000000000 +1000
+@@ -348,7 +348,8 @@
+    (clobber (match_scratch:DF     2                      "=v"))]
+   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+   "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
+-  [(set_attr "length" "8")]
++  [(set_attr "length" "8")
++   (set_attr "cirrus" "normal")]
+ )
+ 
+ (define_insn "*cirrus_truncdfsf2"
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-and-or.patch b/packages/gcc/gcc-4.2.1/arm-crunch-and-or.patch
new file mode 100644
index 0000000000..24357d316e
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-and-or.patch
@@ -0,0 +1,67 @@
+--- gcc-4.1.2/gcc/config/arm/arm.md-original	2007-06-13 17:16:38.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md	2007-06-13 17:35:19.000000000 +1000
+@@ -8455,7 +8455,7 @@
+ 	(and:SI (match_operator:SI 1 "arm_comparison_operator"
+ 		 [(match_operand 3 "cc_register" "") (const_int 0)])
+ 		(match_operand:SI 2 "s_register_operand" "r")))]
+-  "TARGET_ARM"
++  "TARGET_ARM && !TARGET_MAVERICK"
+   "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
+   [(set_attr "conds" "use")
+    (set_attr "length" "8")]
+@@ -8466,7 +8466,7 @@
+ 	(ior:SI (match_operator:SI 2 "arm_comparison_operator"
+ 		 [(match_operand 3 "cc_register" "") (const_int 0)])
+ 		(match_operand:SI 1 "s_register_operand" "0,?r")))]
+-  "TARGET_ARM"
++  "TARGET_ARM && !TARGET_MAVERICK"
+   "@
+    orr%d2\\t%0, %1, #1
+    mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
+@@ -8734,7 +8734,8 @@
+    (clobber (reg:CC CC_REGNUM))]
+   "TARGET_ARM
+    && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y)
+-       != CCmode)"
++       != CCmode)
++   && !TARGET_MAVERICK"
+   "#"
+   "TARGET_ARM && reload_completed"
+   [(set (match_dup 7)
+@@ -8765,7 +8766,7 @@
+    (set (match_operand:SI 7 "s_register_operand" "=r")
+ 	(ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
+ 		(match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
+-  "TARGET_ARM"
++  "TARGET_ARM && !TARGET_MAVERICK"
+   "#"
+   "TARGET_ARM && reload_completed"
+   [(set (match_dup 0)
+@@ -8790,7 +8791,8 @@
+    (clobber (reg:CC CC_REGNUM))]
+   "TARGET_ARM
+    && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
+-       != CCmode)"
++       != CCmode)
++   && !TARGET_MAVERICK"
+   "#"
+   "TARGET_ARM && reload_completed
+    && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
+@@ -8823,7 +8825,7 @@
+    (set (match_operand:SI 7 "s_register_operand" "=r")
+ 	(and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
+ 		(match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
+-  "TARGET_ARM"
++  "TARGET_ARM && !TARGET_MAVERICK"
+   "#"
+   "TARGET_ARM && reload_completed"
+   [(set (match_dup 0)
+@@ -8850,7 +8852,7 @@
+ 		 [(match_operand:SI 4 "s_register_operand" "r,r,r")
+ 		  (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")])))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_ARM
++  "TARGET_ARM && !TARGET_MAVERICK
+    && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
+        == CCmode)"
+   "#"
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-cfcvt64-disable.patch b/packages/gcc/gcc-4.2.1/arm-crunch-cfcvt64-disable.patch
new file mode 100644
index 0000000000..f9280b18b5
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-cfcvt64-disable.patch
@@ -0,0 +1,19 @@
+--- gcc-4.2.0/gcc/config/arm/cirrus.md-original	2007-06-25 15:32:01.000000000 +1000
++++ gcc-4.2.0/gcc/config/arm/cirrus.md	2007-06-25 15:32:14.000000000 +1000
+@@ -325,14 +325,14 @@
+ (define_insn "floatdisf2"
+   [(set (match_operand:SF           0 "cirrus_fp_register" "=v")
+ 	(float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfcvt64s%?\\t%V0, %V1"
+   [(set_attr "cirrus" "normal")])
+ 
+ (define_insn "floatdidf2"
+   [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
+ 	(float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfcvt64d%?\\t%V0, %V1"
+   [(set_attr "cirrus" "normal")])
+ 
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-cfcvtds-disable.patch b/packages/gcc/gcc-4.2.1/arm-crunch-cfcvtds-disable.patch
new file mode 100644
index 0000000000..ec09ea16a1
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-cfcvtds-disable.patch
@@ -0,0 +1,32 @@
+--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt	2007-06-15 10:06:24.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md	2007-06-15 10:07:21.000000000 +1000
+@@ -355,11 +355,12 @@
+    (set_attr "cirrus" "normal")]
+ )
+ 
++; appears to be buggy - causes 20000320-1.c to fail in execute/ieee
+ (define_insn "*cirrus_truncdfsf2"
+   [(set (match_operand:SF  0 "cirrus_fp_register" "=v")
+         (float_truncate:SF
+          (match_operand:DF 1 "cirrus_fp_register" "v")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+   "cfcvtds%?\\t%V0, %V1"
+   [(set_attr "cirrus" "normal")]
+ )
+--- gcc-4.1.2/gcc/config/arm/arm.md-truncdfsf2	2007-06-15 10:25:43.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md	2007-06-15 10:27:01.000000000 +1000
+@@ -3181,11 +3181,12 @@
+ 
+ ;; Truncation insns
+ 
++;; Maverick Crunch truncdfsf2 is buggy - see cirrus.md
+ (define_expand "truncdfsf2"
+   [(set (match_operand:SF  0 "s_register_operand" "")
+ 	(float_truncate:SF
+  	 (match_operand:DF 1 "s_register_operand" "")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT"
++  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+   ""
+ )
+ 
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-cirrus-bugfixes.patch b/packages/gcc/gcc-4.2.1/arm-crunch-cirrus-bugfixes.patch
new file mode 100644
index 0000000000..cb0af8546d
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-cirrus-bugfixes.patch
@@ -0,0 +1,573 @@
+diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c gcc-4.1.2/gcc/config/arm/arm.c
+--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c	2007-05-09 16:32:29.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.c	2007-05-15 09:39:41.000000000 +1000
+@@ -4,6 +4,7 @@
+    Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
+    and Martin Simmons (@harleqn.co.uk).
+    More major hacks by Richard Earnshaw (rearnsha@arm.com).
++   Cirrus Crunch bugfixes by Vladimir Ivanov (vladit@nucleusys.com)
+ 
+    This file is part of GCC.
+ 
+@@ -131,9 +132,17 @@
+ static bool arm_xscale_rtx_costs (rtx, int, int, int *);
+ static bool arm_9e_rtx_costs (rtx, int, int, int *);
+ static int arm_address_cost (rtx);
+-static bool arm_memory_load_p (rtx);
++// static bool arm_memory_load_p (rtx);
+ static bool arm_cirrus_insn_p (rtx);
+-static void cirrus_reorg (rtx);
++// static void cirrus_reorg (rtx);
++static bool arm_mem_access_p (rtx);
++static bool cirrus_dest_regn_p (rtx, int);
++static rtx cirrus_prev_next_mach_insn (rtx, int *, int);
++static rtx cirrus_prev_mach_insn (rtx, int *);
++static rtx cirrus_next_mach_insn (rtx, int *);
++static void cirrus_reorg_branch (rtx);
++static void cirrus_reorg_bug1 (rtx);
++static void cirrus_reorg_bug10_12 (rtx);
+ static void arm_init_builtins (void);
+ static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
+ static void arm_init_iwmmxt_builtins (void);
+@@ -5399,41 +5412,6 @@
+               || TREE_CODE (valtype) == COMPLEX_TYPE));
+ }
+ 
+-/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
+-   Use by the Cirrus Maverick code which has to workaround
+-   a hardware bug triggered by such instructions.  */
+-static bool
+-arm_memory_load_p (rtx insn)
+-{
+-  rtx body, lhs, rhs;;
+-
+-  if (insn == NULL_RTX || GET_CODE (insn) != INSN)
+-    return false;
+-
+-  body = PATTERN (insn);
+-
+-  if (GET_CODE (body) != SET)
+-    return false;
+-
+-  lhs = XEXP (body, 0);
+-  rhs = XEXP (body, 1);
+-
+-  lhs = REG_OR_SUBREG_RTX (lhs);
+-
+-  /* If the destination is not a general purpose
+-     register we do not have to worry.  */
+-  if (GET_CODE (lhs) != REG
+-      || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
+-    return false;
+-
+-  /* As well as loads from memory we also have to react
+-     to loads of invalid constants which will be turned
+-     into loads from the minipool.  */
+-  return (GET_CODE (rhs) == MEM
+-	  || GET_CODE (rhs) == SYMBOL_REF
+-	  || note_invalid_constants (insn, -1, false));
+-}
+-
+ /* Return TRUE if INSN is a Cirrus instruction.  */
+ static bool
+ arm_cirrus_insn_p (rtx insn)
+@@ -5452,124 +5433,218 @@
+   return attr != CIRRUS_NOT;
+ }
+ 
+-/* Cirrus reorg for invalid instruction combinations.  */
+-static void
+-cirrus_reorg (rtx first)
++/* Return TRUE if ISN does memory access.  */
++static bool
++arm_mem_access_p (rtx insn)
+ {
+-  enum attr_cirrus attr;
+-  rtx body = PATTERN (first);
+-  rtx t;
+-  int nops;
++  enum attr_type attr;
+ 
+-  /* Any branch must be followed by 2 non Cirrus instructions.  */
+-  if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
+-    {
+-      nops = 0;
+-      t = next_nonnote_insn (first);
++  /* get_attr aborts on USE and CLOBBER.  */
++  if (!insn
++      || GET_CODE (insn) != INSN
++      || GET_CODE (PATTERN (insn)) == USE
++      || GET_CODE (PATTERN (insn)) == CLOBBER)
++    return 0;
+ 
+-      if (arm_cirrus_insn_p (t))
+-	++ nops;
++    attr = get_attr_type (insn);
+ 
+-      if (arm_cirrus_insn_p (next_nonnote_insn (t)))
+-	++ nops;
++  return attr == TYPE_LOAD_BYTE
++   || attr == TYPE_LOAD1   || attr == TYPE_LOAD2    || attr == TYPE_LOAD3 || attr == TYPE_LOAD4
++   || attr == TYPE_F_CVT
++   || attr == TYPE_F_MEM_R || attr == TYPE_R_MEM_F  || attr == TYPE_F_2_R || attr == TYPE_R_2_F
++   || attr == TYPE_F_LOAD	|| attr == TYPE_F_LOADS  || attr == TYPE_F_LOADD
++   || attr == TYPE_F_STORE || attr == TYPE_F_STORES || attr == TYPE_F_STORED
++   || attr == TYPE_STORE1  || attr == TYPE_STORE2   || attr == TYPE_STORE3  || attr == TYPE_STORE4;
++
++}
+ 
+-      while (nops --)
+-	emit_insn_after (gen_nop (), first);
++/* Return TRUE if destination is certain Cirrus register.  */
++static bool
++cirrus_dest_regn_p (rtx body, int regn)
++{
++  rtx lhs;
++  int reg;
++  lhs = XEXP (body, 0);
++  if (GET_CODE (lhs) != REG)
++    return 0;
+ 
+-      return;
+-    }
++  reg = REGNO (lhs);
++  if (REGNO_REG_CLASS (reg) != CIRRUS_REGS)
++    return 0;
+ 
+-  /* (float (blah)) is in parallel with a clobber.  */
+-  if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
+-    body = XVECEXP (body, 0, 0);
++  return reg == regn;
++}
++
++/* Get previous/next machine instruction during Cirrus workaround scans.
++   Assume worst case (for the purpose of Cirrus workarounds)
++   for JUMP / CALL instructions.  */
++static rtx
++cirrus_prev_next_mach_insn (rtx insn, int *len, int next)
++{
++  rtx t;
++  int l = 0;
+ 
+-  if (GET_CODE (body) == SET)
++  /* It seems that we can count only on INSN length.  */
++  for ( ; ; )
+     {
+-      rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
++      if (next)
++    	insn = NEXT_INSN (insn);
++      else
++    	insn = PREV_INSN (insn);
++      if (!insn)
++    	break;
+ 
+-      /* cfldrd, cfldr64, cfstrd, cfstr64 must
+-	 be followed by a non Cirrus insn.  */
+-      if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
+-	{
+-	  if (arm_cirrus_insn_p (next_nonnote_insn (first)))
+-	    emit_insn_after (gen_nop (), first);
++    if (GET_CODE (insn) == INSN)
++      {
++	    l = get_attr_length (insn) / 4;
++        if (l)
++	      break