merge of '1293c35f9186cb98ae4e1efe9e3cb8cc0e607def'

     and '799ba111ed9bf4dd2c65638fc75b6af788b54ab7'

9 files changed, 5972 insertions, 2 deletions

diff --git a/packages/linux/linux.inc b/packages/linux/linux.inc
index 3ee5e227f3..1e4e58b089 100644
--- a/packages/linux/linux.inc
+++ b/packages/linux/linux.inc
@@ -7,6 +7,7 @@ DEPENDS_kb9202 = "u-boot-mkimage-gta01-native"
 DEPENDS_at32stk1000 = "u-boot-mkimage-gta01-native" 
 DEPENDS_atngw100 = "u-boot-mkimage-gta01-native"
 DEPENDS_at91sam9263ek = "u-boot-mkimage-gta01-native"
+DEPENDS_sarge-at91 = "u-boot-mkimage-gta01-native"
 
 inherit kernel
 
@@ -16,6 +17,7 @@ KERNEL_IMAGETYPE_kb9202 = "uImage"
 KERNEL_IMAGETYPE_atngw100 = "uImage"
 KERNEL_IMAGETYPE_at32stk1000 = "uImage"
 KERNEL_IMAGETYPE_at91sam9263ek = "uImage"
+KERNEL_IMAGETYPE_sarge-at91 = "uImage"
 
 # Specify the commandline for you device here:
 
diff --git a/packages/linux/linux/sarge-at91/.mtn2git_empty b/packages/linux/linux/sarge-at91/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/linux/linux/sarge-at91/.mtn2git_empty
diff --git a/packages/linux/linux/sarge-at91/2.6.21-sarge-kernel.patch b/packages/linux/linux/sarge-at91/2.6.21-sarge-kernel.patch
new file mode 100644
index 0000000000..7b5f408c37
--- /dev/null
+++ b/packages/linux/linux/sarge-at91/2.6.21-sarge-kernel.patch
@@ -0,0 +1,238 @@
+diff -Nurp ../linux-2.6.21.4/arch/arm/boot/compressed/head-at91rm9200.S ./arch/arm/boot/compressed/head-at91rm9200.S
+--- ../linux-2.6.21.4/arch/arm/boot/compressed/head-at91rm9200.S	2007-06-12 22:29:12.000000000 +0200
++++ ./arch/arm/boot/compressed/head-at91rm9200.S	2007-06-12 02:57:07.000000000 +0200
+@@ -73,6 +73,12 @@
+ 		cmp	r7, r3
+ 		beq	99f
+ 
++                @ AT91RM9200
++                mov     r3,     #(MACH_TYPE_AT91RM9200 & 0xff)
++                orr     r3, r3, #(MACH_TYPE_AT91RM9200 & 0xff00)
++                cmp     r7, r3
++                beq     99f
++
+ 		@ Unknown board, use the AT91RM9200DK board
+ 		@ mov	r7, #MACH_TYPE_AT91RM9200
+ 		mov	r7,	#(MACH_TYPE_AT91RM9200DK & 0xff)
+diff -Nurp ../linux-2.6.21.4/arch/arm/mach-at91/board-sarge.c ./arch/arm/mach-at91/board-sarge.c
+--- ../linux-2.6.21.4/arch/arm/mach-at91/board-sarge.c	1970-01-01 01:00:00.000000000 +0100
++++ ./arch/arm/mach-at91/board-sarge.c	2007-06-12 02:57:07.000000000 +0200
+@@ -0,0 +1,190 @@
++/*
++ * linux/arch/arm/mach-at91/board-sarge.c
++ *
++ *  Copyright (C) 2007 BlackMesaEast staff
++ *
++ *	mcgregor@blackmesaeast.com.pl
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/spi/spi.h>
++#include <linux/mtd/physmap.h>
++
++#include <asm/hardware.h>
++#include <asm/setup.h>
++#include <asm/mach-types.h>
++#include <asm/irq.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/at91rm9200_mc.h>
++
++#include "generic.h"
++
++
++/*
++ * Serial port configuration.
++ *    0 .. 3 = USART0 .. USART3
++ *    4      = DBGU
++ */
++static struct at91_uart_config __initdata sarge_uart_config = {
++	.console_tty	= 0,				/* ttyS0 */
++	.nr_tty		= 5,
++	.tty_map	= { 4, 1, 0, 2, 3 }		/* ttyS0, ..., ttyS4 */
++};
++
++static void __init sarge_map_io(void)
++{
++	/* Initialize processor: 18.432 MHz crystal */
++	at91rm9200_initialize(18432000, AT91RM9200_PQFP);
++
++	/* Setup the serial ports and console */
++	at91_init_serial(&sarge_uart_config);
++}
++
++static void __init sarge_init_irq(void)
++{
++	at91rm9200_init_interrupts(NULL);
++}
++
++static struct at91_eth_data __initdata sarge_eth_data = {
++	.phy_irq_pin	= AT91_PIN_PB1,
++	.is_rmii	= 0,
++};
++
++static struct at91_usbh_data __initdata sarge_usbh_data = {
++	.ports		= 1,
++};
++
++static struct at91_udc_data __initdata sarge_udc_data = {
++	.vbus_pin	= AT91_PIN_PA20,
++	.pullup_pin	= AT91_PIN_PA21,
++};
++
++static struct at91_cf_data __initdata sarge_cf_data = {
++	.det_pin	= AT91_PIN_PB24,
++	.rst_pin	= AT91_PIN_PB23,
++	// .irq_pin	= ... not connected
++	// .vcc_pin	= ... always powered
++};
++
++static struct at91_mmc_data __initdata sarge_mmc_data = {
++	.det_pin	= AT91_PIN_PB0,
++	.slot_b		= 0,	
++	.wire4		= 1,	
++	.wp_pin		= AT91_PIN_PB2,
++};
++
++
++
++static struct spi_board_info sarge_spi_devices[] = {
++	{	/* DataFlash chip */
++		.modalias	= "mtd_dataflash",
++		.chip_select	= 0,
++		.max_speed_hz	= 15 * 1000 * 1000,
++	}
++};
++
++static struct mtd_partition __initdata sarge_nand_partition[] = {
++	{
++		.name	= "NAND Partition 1",
++		.offset	= 0,
++		.size	= MTDPART_SIZ_FULL,
++	},
++};
++
++static struct mtd_partition *nand_partitions(int size, int *num_partitions)
++{
++	*num_partitions = ARRAY_SIZE(sarge_nand_partition);
++	return sarge_nand_partition;
++}
++
++static struct at91_nand_data __initdata sarge_nand_data = {
++	.ale		= 22,
++	.cle		= 21,
++	.det_pin	= AT91_PIN_PB22,
++	.rdy_pin	= AT91_PIN_PB22,
++	// .enable_pin	= ... not there
++	.partition_info	= nand_partitions,
++};
++
++#define SARGE_FLASH_BASE	AT91_CHIPSELECT_0
++#define SARGE_FLASH_SIZE	0x200000
++
++static struct physmap_flash_data sarge_flash_data = {
++	.width		= 2,
++};
++
++static struct resource sarge_flash_resource = {
++	.start		= SARGE_FLASH_BASE,
++	.end		= SARGE_FLASH_BASE + SARGE_FLASH_SIZE - 1,
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct platform_device sarge_flash = {
++	.name		= "physmap-flash",
++	.id		= 0,
++	.dev		= {
++				.platform_data	= &sarge_flash_data,
++			},
++	.resource	= &sarge_flash_resource,
++	.num_resources	= 1,
++};
++
++static void __init sarge_board_init(void)
++{
++	/* Serial */
++	at91_add_device_serial();
++	/* Ethernet */
++	at91_add_device_eth(&sarge_eth_data);
++	/* USB Host */
++	at91_add_device_usbh(&sarge_usbh_data);
++	/* USB Device */
++	at91_add_device_udc(&sarge_udc_data);
++	at91_set_multi_drive(sarge_udc_data.pullup_pin, 1);	/* pullup_pin is connected to reset */
++	/* Compact Flash */
++	at91_add_device_cf(&sarge_cf_data);
++	/* I2C */
++	at91_add_device_i2c();
++	/* SPI */
++	at91_add_device_spi(sarge_spi_devices, ARRAY_SIZE(sarge_spi_devices));
++
++	/* MMC */
++	at91_add_device_mmc(0, &sarge_mmc_data);
++	/* NAND */
++	at91_add_device_nand(&sarge_nand_data);
++	/* NOR Flash */
++	platform_device_register(&sarge_flash);
++}
++MACHINE_START(AT91RM9200, "Sarge AT91RM9200 SBC")
++	/* Maintainer: mcgregor@blackmesaeast.com.pl */
++	.phys_io	= AT91_BASE_SYS,
++	.io_pg_offst	= (AT91_VA_BASE_SYS >> 18) & 0xfffc,
++	.boot_params	= AT91_SDRAM_BASE + 0x100,
++	.timer		= &at91rm9200_timer,
++	.map_io		= sarge_map_io,
++	.init_irq	= sarge_init_irq,
++	.init_machine	= sarge_board_init,
++MACHINE_END
+diff -Nurp ../linux-2.6.21.4/arch/arm/mach-at91/Kconfig ./arch/arm/mach-at91/Kconfig
+--- ../linux-2.6.21.4/arch/arm/mach-at91/Kconfig	2007-06-12 22:29:12.000000000 +0200
++++ ./arch/arm/mach-at91/Kconfig	2007-06-12 03:00:28.000000000 +0200
+@@ -90,6 +90,13 @@ config MACH_KAFA
+ 	help
+ 	  Select this if you are using Sperry-Sun's KAFA board.
+ 
++config MACH_SARGE
++        bool "Black Mesa East Sarge SBC"
++        depends on ARCH_AT91RM9200
++        help
++	  Select this if you are using BlackMesaEast Sarge PCB
++	  <http://blackmesaeast.com.pl>
++					    
+ config MACH_CHUB
+ 	bool "Promwad Chub board"
+ 	depends on ARCH_AT91RM9200
+diff -Nurp ../linux-2.6.21.4/arch/arm/mach-at91/Makefile ./arch/arm/mach-at91/Makefile
+--- ../linux-2.6.21.4/arch/arm/mach-at91/Makefile	2007-06-12 22:29:12.000000000 +0200
++++ ./arch/arm/mach-at91/Makefile	2007-06-12 03:00:47.000000000 +0200
+@@ -29,6 +29,7 @@ obj-$(CONFIG_MACH_KB9200)	+= board-kb920
+ obj-$(CONFIG_MACH_ATEB9200)	+= board-eb9200.o
+ obj-$(CONFIG_MACH_KAFA)		+= board-kafa.o
+ obj-$(CONFIG_MACH_CHUB)		+= board-chub.o
++obj-$(CONFIG_MACH_SARGE)	+= board-sarge.o
+ 
+ # AT91SAM9260 board-specific support
+ obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
diff --git a/packages/linux/linux/sarge-at91/2.6.21-sarge-mmc.patch b/packages/linux/linux/sarge-at91/2.6.21-sarge-mmc.patch
new file mode 100644
index 0000000000..01bbaeb73e
--- /dev/null
+++ b/packages/linux/linux/sarge-at91/2.6.21-sarge-mmc.patch
@@ -0,0 +1,87 @@
+diff -Nurp ../linux-2.6.21.4/drivers/mmc/at91_mci.c ./drivers/mmc/at91_mci.c
+--- ../linux-2.6.21.4/drivers/mmc/at91_mci.c	2007-06-12 22:29:12.000000000 +0200
++++ ./drivers/mmc/at91_mci.c	2007-06-12 03:52:55.000000000 +0200
+@@ -421,8 +421,11 @@ static unsigned int at91_mci_send_comman
+ 	if (cmd->opcode == MMC_STOP_TRANSMISSION)
+ 		cmdr |= AT91_MCI_TRCMD_STOP;
+ 
+-	if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
+-		cmdr |= AT91_MCI_OPDCMD;
++	//if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
++	//	cmdr |= AT91_MCI_OPDCMD;
++		
++	if (!(1/**machine_is_sarge*/) && host->bus_mode == MMC_BUSMODE_OPENDRAIN)
++	     cmdr |= AT91_MCI_OPDCMD;		
+ 
+ 	/*
+ 	 * Set the arguments and send the command
+@@ -739,7 +742,13 @@ static irqreturn_t at91_mci_irq(int irq,
+ 		at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
+ 		at91mci_completed_command(host);
+ 	} else
++//		at91_mci_write(host, AT91_MCI_IDR, int_status);
++	 {
++	    if (1 /*machine_is_sarge()*/)
++		at91_mci_write(host, AT91_MCI_IDR, (int_status & ~AT91_MCI_TXRDY) );
++	    else
+ 		at91_mci_write(host, AT91_MCI_IDR, int_status);
++	}		
+ 
+ 	return IRQ_HANDLED;
+ }
+diff -Nurp ../linux-2.6.21.4/drivers/mmc/mmc_block.c ./drivers/mmc/mmc_block.c
+--- ../linux-2.6.21.4/drivers/mmc/mmc_block.c	2007-06-07 23:27:31.000000000 +0200
++++ ./drivers/mmc/mmc_block.c	2007-06-12 04:19:36.000000000 +0200
+@@ -256,10 +256,24 @@ static int mmc_blk_issue_rq(struct mmc_q
+ 		 * this rule as they support querying the number of
+ 		 * successfully written sectors.
+ 		 */
+-		if (rq_data_dir(req) != READ &&
++//		if (rq_data_dir(req) != READ &&
++		    if ((1/**machine_is_sarge*/))
++		    {
++			if (rq_data_dir(req) != READ)
++			    brq.data.blocks = 1;
++		    }
++		    else if (rq_data_dir(req) != READ &&			
++
+ 		    !(card->host->caps & MMC_CAP_MULTIWRITE) &&
+ 		    !mmc_card_sd(card))
+ 			brq.data.blocks = 1;
++			
++			
++			
++			
++			
++			
++			
+ 
+ 		if (brq.data.blocks > 1) {
+ 			brq.data.flags |= MMC_DATA_MULTI;
+diff -Nurp ../linux-2.6.21.4/drivers/mmc/mmc.c ./drivers/mmc/mmc.c
+--- ../linux-2.6.21.4/drivers/mmc/mmc.c	2007-06-07 23:27:31.000000000 +0200
++++ ./drivers/mmc/mmc.c	2007-06-12 04:10:05.000000000 +0200
+@@ -1500,12 +1500,22 @@ static void mmc_setup(struct mmc_host *h
+ 	mmc_set_ios(host);
+ 
+ 	mmc_read_csds(host);
+-
++	/*
+ 	if (host->mode == MMC_MODE_SD) {
+ 		mmc_read_scrs(host);
+ 		mmc_read_switch_caps(host);
+ 	} else
+ 		mmc_process_ext_csds(host);
++	*/
++	
++	if (!(1/*machine_is_sarge*/))
++	{
++	    if (host->mode == MMC_MODE_SD) {
++		mmc_read_scrs(host);
++	    mmc_read_switch_caps(host);
++	    } else
++		mmc_process_ext_csds(host);
++	}	
+ }
+ 
+ 
diff --git a/packages/linux/linux/sarge-at91/2.6.21-sarge-phy.patch b/packages/linux/linux/sarge-at91/2.6.21-sarge-phy.patch
new file mode 100644
index 0000000000..25ce15eb94
--- /dev/null
+++ b/packages/linux/linux/sarge-at91/2.6.21-sarge-phy.patch
@@ -0,0 +1,400 @@
+diff -Nurp ../linux-2.6.21.4/drivers/net/arm/at91_ether.c ./drivers/net/arm/at91_ether.c
+--- ../linux-2.6.21.4/drivers/net/arm/at91_ether.c	2007-06-12 22:29:12.000000000 +0200
++++ ./drivers/net/arm/at91_ether.c	2007-06-12 03:11:16.000000000 +0200
+@@ -235,6 +235,11 @@ static irqreturn_t at91ether_phy_interru
+ 		if (!(phy & (1 << 7)))
+ 			goto done;
+ 	}
++	else if (lp->phy_type == MII_STE100P_ID) {	
++		read_phy(lp->phy_address, MII_STE100P_XCSIIS_REG, &phy); /* ack interrupt in STE100P PHY */
++		if (!(phy & 0x007F))
++		    goto done;
++	}
+ 
+ 	update_linkspeed(dev, 0);
+ 
+@@ -303,6 +308,11 @@ static void enable_phyirq(struct net_dev
+ 		dsintr = dsintr | 0x3;			/* set bits 0,1 */
+ 		write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
+ 	}
++	else if (lp->phy_type == MII_STE100P_ID) {	/* for STE100P PHY */
++		read_phy(lp->phy_address, MII_STE100P_XIE_REG, &dsintr);
++
++		dsintr |= 0x007F;
++	}
+ 
+ 	disable_mdi();
+ 	spin_unlock_irq(&lp->lock);
+@@ -359,6 +369,11 @@ static void disable_phyirq(struct net_de
+ 		dsintr = dsintr & ~0x3c;			/* clear bits 2..5 */
+ 		write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
+ 	}
++	else if (lp->phy_type == MII_STE100P_ID) {	/* for STE100P PHY */
++		read_phy(lp->phy_address, MII_STE100P_XIE_REG, &dsintr);
++		dsintr &= 0xFF80;
++		write_phy(lp->phy_address, MII_STE100P_XIE_REG, dsintr);
++	}
+ 
+ 	disable_mdi();
+ 	spin_unlock_irq(&lp->lock);
+@@ -1117,6 +1132,8 @@ static int __init at91ether_setup(unsign
+ 		printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
+ 	else if (phy_type == MII_LAN83C185_ID)
+ 		printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
++	else if (phy_type == MII_STE100P_ID)
++		printk(KERN_INFO "%s: STE100P PHY\n", dev->name);
+ 
+ 	return 0;
+ }
+@@ -1159,6 +1176,7 @@ static int __init at91ether_probe(struct
+ 			case MII_KS8721_ID:		/* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
+ 			case MII_T78Q21x3_ID:		/* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
+ 			case MII_LAN83C185_ID:		/* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
++ 			case MII_STE100P_ID:		/* STE100P: PHY_ID1 = 0x1C04, PHY_ID2 = 0x0000 */
+ 				detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
+ 				break;
+ 		}
+diff -Nurp ../linux-2.6.21.4/drivers/net/arm/at91_ether.h ./drivers/net/arm/at91_ether.h
+--- ../linux-2.6.21.4/drivers/net/arm/at91_ether.h	2007-06-12 22:29:12.000000000 +0200
++++ ./drivers/net/arm/at91_ether.h	2007-06-12 03:07:54.000000000 +0200
+@@ -29,6 +29,15 @@
+ #define MII_ISINTS_REG		19
+ #define MII_LEDCTRL_REG		20
+ 
++/* STE100P specific registers */
++#define MII_STE100P_XCSIIS_REG  0x11
++#define MII_STE100P_XIE_REG     0x12
++#define MII_XCR_REG             0x00
++#define MII_XCR_ISOLATE      0x0400
++
++/* STE100P PHY */
++#define MII_STE100P_ID  0x1c040010
++
+ /* Realtek RTL8201 PHY */
+ #define MII_RTL8201_ID		0x00008200
+ 
+diff -Nurp ../linux-2.6.21.4/drivers/net/phy/Kconfig ./drivers/net/phy/Kconfig
+--- ../linux-2.6.21.4/drivers/net/phy/Kconfig	2007-06-07 23:27:31.000000000 +0200
++++ ./drivers/net/phy/Kconfig	2007-06-12 03:12:16.000000000 +0200
+@@ -62,6 +62,12 @@ config BROADCOM_PHY
+ 	---help---
+ 	  Currently supports the BCM5411, BCM5421 and BCM5461 PHYs.
+ 
++config STE100P_PHY
++        tristate "Drivers for the STE100P PHY"
++        depends on PHYLIB
++        ---help---
++          Currently supports the ste100p
++	  
+ config FIXED_PHY
+ 	tristate "Drivers for PHY emulation on fixed speed/link"
+ 	depends on PHYLIB
+diff -Nurp ../linux-2.6.21.4/drivers/net/phy/Makefile ./drivers/net/phy/Makefile
+--- ../linux-2.6.21.4/drivers/net/phy/Makefile	2007-06-07 23:27:31.000000000 +0200
++++ ./drivers/net/phy/Makefile	2007-06-12 03:12:29.000000000 +0200
+@@ -12,3 +12,4 @@ obj-$(CONFIG_SMSC_PHY)		+= smsc.o
+ obj-$(CONFIG_VITESSE_PHY)	+= vitesse.o
+ obj-$(CONFIG_BROADCOM_PHY)	+= broadcom.o
+ obj-$(CONFIG_FIXED_PHY)		+= fixed.o
++obj-$(CONFIG_STE100P_PHY)       += ste100p.o
+diff -Nurp ../linux-2.6.21.4/drivers/net/phy/ste100p.c ./drivers/net/phy/ste100p.c
+--- ../linux-2.6.21.4/drivers/net/phy/ste100p.c	1970-01-01 01:00:00.000000000 +0100
++++ ./drivers/net/phy/ste100p.c	2007-06-12 02:52:31.000000000 +0200
+@@ -0,0 +1,297 @@
++/*
++ * drivers/net/phy/ste100p.c
++ *
++ * Driver for STE100P PHYs
++ *
++ * Author: Grzegorz Rajtar mcgregor@blackmesaeast.com.pl
++ *
++ * Copyright (c) 2007 Black Mesa East 
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/string.h>
++#include <linux/errno.h>
++#include <linux/unistd.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/spinlock.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/mii.h>
++#include <linux/ethtool.h>
++#include <linux/phy.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/uaccess.h>
++
++/* Control register and bitmasks*/
++#define MII_STE100P_XCR_REG 0x00
++#define MII_STE100P_XCR_RESET 		1 << 15
++#define MII_STE100P_XCR_LOOPBACK	1 << 14
++#define MII_STE100P_XCR_SPEED		1 << 13
++#define MII_STE100P_XCR_AN		1 << 12
++#define MII_STE100P_XCR_PWRDN		1 << 11
++#define MII_STE100P_XCR_ISOLATE		1 << 10
++#define MII_STE100P_XCR_RSTRT_AN	1 << 9
++#define MII_STE100P_XCR_FULL_DUP	1 << 8
++#define MII_STE100P_XCR_COLLEN		1 << 7
++
++
++/* Iinterrupt register and bitmasks */
++#define MII_STE100P_XIE_REG	0x12
++#define MII_STE100P_XIE_ANCE	1 << 6
++#define MII_STE100P_XIE_RFE	1 << 5
++#define MII_STE100P_XIE_LDE	1 << 4
++#define MII_STE100P_XIE_ANAE	1 << 3
++#define MII_STE100P_XIE_PDFE	1 << 2
++#define MII_STE100P_XIE_ANPE	1 << 1
++#define MII_STE100P_XIE_REFE	1
++#define MII_STE100P_XIE_ALL	\
++(MII_STE100P_XIE_ANCE | MII_STE100P_XIE_RFE | MII_STE100P_XIE_LDE | \
++ MII_STE100P_XIE_ANAE | MII_STE100P_XIE_PDFE | MII_STE100P_XIE_ANPE | MII_STE100P_XIE_REFE)
++
++/* Iinterrupt status register and bitmasks */
++#define MII_STE100P_XCSIIS_REG		0x11
++#define MII_STE100P_XCSIIS_SPEED	1 << 9
++#define MII_STE100P_XCSIIS_DUPLEX	1 << 8
++#define MII_STE100P_XCSIIS_PAUSE	1 << 7
++#define MII_STE100P_XCSIIS_ANC		1 << 6
++#define MII_STE100P_XCSIIS_RFD		1 << 5
++#define MII_STE100P_XCSIIS_LS		1 << 4
++#define MII_STE100P_XCSIIS_ANAR		1 << 3
++#define MII_STE100P_XCSIIS_PDF		1 << 2
++#define MII_STE100P_XCSIIS_ANPR		1 << 1
++#define MII_STE100P_XCSIIS_REF		1
++
++/* 100-TX register and bitmasks*/
++#define MII_STE100P_100CTR_REG		0x13
++#define MII_STE100P_100CTR_DISERR	1 << 13
++#define MII_STE100P_100CTR_ANC		1 << 12
++#define MII_STE100P_100CTR_ENRLB	1 << 9
++#define MII_STE100P_100CTR_ENDCR	1 << 8
++#define MII_STE100P_100CTR_ENRZI	1 << 7
++#define MII_STE100P_100CTR_EN4B5B	1 << 6
++#define MII_STE100P_100CTR_ISOTX	1 << 5
++#define MII_STE100P_100CTR_CMODE_MASK	0x001C
++#define MII_STE100P_100CTR_DISMLT	1 << 1
++#define MII_STE100P_100CTR_DISCRM	1
++
++/* Auto-negotiation register and bitmasks*/
++#define MII_STE100P_ANA_REG         0x04
++#define MII_STE100P_ANA_NXTPG          1 << 15 
++#define MII_STE100P_ANA_RF             1 << 13
++#define MII_STE100P_ANA_FC             1 << 10
++#define MII_STE100P_ANA_T4             1 << 9
++#define MII_STE100P_ANA_TXF            1 << 8
++#define MII_STE100P_ANA_TXH            1 << 7
++#define MII_STE100P_ANA_10F            1 << 6
++#define MII_STE100P_ANA_10H            1 << 5
++#define MII_STE100P_ANA_SF             0x0000
++#define MII_STE100P_ANA_SF_MASK        0x000F
++
++/* PHY chip ID regs */
++#define MII_STE100P_PID1_REG        0x02
++#define MII_STE100P_PID2_REG        0x03
++
++#define MII_STE100P_PHYID_VAL    0x1C040000
++#define MII_STE100P_PHYID_MASK   0xFFFF0000
++
++
++
++MODULE_DESCRIPTION("STE100P PHY driver");
++MODULE_AUTHOR("Grzegorz Rajtar <mcgregor@blackmesaeast.com.pl>");
++MODULE_LICENSE("GPL");
++
++static int ste100p_config_intr(struct phy_device *phydev)
++{
++	int temp;
++	temp = phy_read(phydev, MII_STE100P_XIE_REG);
++
++	if(PHY_INTERRUPT_ENABLED == phydev->interrupts )
++		temp |= MII_STE100P_XIE_ALL;
++	else
++	{
++		temp &= ~(MII_STE100P_XIE_ALL);
++		//clear interrupt status register
++		phy_read(phydev, MII_STE100P_XCSIIS_REG);
++	}
++
++	temp = phy_write(phydev, MII_STE100P_XIE_REG, temp);
++
++	return temp;
++}
++
++static int ste100p_config_aneg(struct phy_device *phydev)
++{
++	int err;
++
++	int temp = phy_read(phydev, MII_STE100P_XCR_REG);
++	int temp2;
++	
++	/* Isolate the PHY */
++
++	err = phy_write(phydev, MII_STE100P_XCR_REG, temp | MII_STE100P_XCR_ISOLATE);
++	
++	//read for isolate latch
++	temp = phy_read(phydev, MII_STE100P_XCR_REG);
++
++	if (err < 0)
++		return err;
++
++	/* Set the Auto_negotiation Advertisement Register */
++	/* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
++	err =  phy_write(phydev, MII_STE100P_ANA_REG,
++	    	MII_STE100P_ANA_NXTPG | MII_STE100P_ANA_TXF | MII_STE100P_ANA_TXH |
++		MII_STE100P_ANA_10F | MII_STE100P_ANA_10H | MII_STE100P_ANA_SF);
++
++	if (err < 0)
++	    return err;
++
++	err =  phy_write(phydev, MII_STE100P_XCR_REG, 
++		temp | MII_STE100P_XCR_AN /*| MII_STE100P_XCR_SPEED */ | MII_STE100P_XCR_FULL_DUP);
++
++	if (err < 0)
++	    return err;
++
++	/* Restart auto negotiation */
++
++	err = phy_write(phydev, MII_STE100P_XCR_REG,  
++	    (temp | MII_STE100P_XCR_AN | MII_STE100P_XCR_RSTRT_AN) & (~MII_STE100P_XCR_ISOLATE));
++
++	//read for isolate latch
++	phy_read(phydev, MII_STE100P_XCR_REG);
++
++	if (err < 0)
++		return err;
++
++	/* Configure the new settings */
++	err = genphy_config_aneg(phydev);
++
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++
++static int ste100p_config_init(struct phy_device *phydev)
++{
++	int err;
++	int temp;
++	int temp_xcr;	
++
++	/* Isolate the PHY */
++
++	temp_xcr = phy_read(phydev, MII_STE100P_XCR_REG);
++	
++	err = phy_write(phydev, MII_STE100P_XCR_REG, 
++	    ((temp_xcr |  MII_STE100P_XCR_ISOLATE) & (~MII_STE100P_XCR_AN)));
++
++	//read for isolate latch
++	temp_xcr = phy_read(phydev, MII_STE100P_XCR_REG);
++		
++	err = phy_write(phydev, MII_STE100P_XCR_REG,  
++	    temp_xcr &  (~MII_STE100P_XCR_ISOLATE));	
++
++	//read for isolate latch
++	phy_read(phydev, MII_STE100P_XCR_REG);
++	
++	if (err < 0)
++	    return err;
++
++	temp = phy_read(phydev, MII_STE100P_ANA_REG);
++	    
++	err = phy_write(phydev, MII_STE100P_ANA_REG, temp
++	    | MII_STE100P_ANA_FC | MII_STE100P_ANA_TXF 
++	    | MII_STE100P_ANA_TXH | MII_STE100P_ANA_10F | MII_STE100P_ANA_10H);
++	    
++	if (err < 0)
++	    return err;
++
++	/* Reconnect the PHY, and enable Autonegotiation */
++	err = phy_write(phydev,  MII_STE100P_XCR_REG, (temp_xcr | MII_STE100P_XCR_AN 
++		| MII_STE100P_XCR_RSTRT_AN) & (~MII_STE100P_XCR_ISOLATE));
++
++	//read for isolate latch
++	phy_read(phydev, MII_STE100P_XCR_REG);
++
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++
++static int ste100p_ack_interrupt(struct phy_device *phydev)
++{
++	int intmask = 1;
++	int rep = 0;
++
++	//clear multiple interrupts;
++	do
++	{
++	    intmask = phy_read(phydev, MII_STE100P_XCSIIS_REG);
++	    rep++;	    	    
++	} while ((intmask & MII_STE100P_XIE_ALL) != 0 && rep < 25);
++	
++	return  0;
++}
++
++
++static int ste100p_suspend(struct phy_device *phydev)
++{
++	int temp = phy_read(phydev, MII_STE100P_XCR_REG);
++	temp = phy_write(phydev, MII_STE100P_XCR_REG, temp | MII_STE100P_XCR_PWRDN);
++	//read for latch XCR REG
++	phy_read(phydev, MII_STE100P_XCR_REG);
++	return temp;
++}
++
++static int ste100p_resume(struct phy_device *phydev)
++{
++	int temp;
++	temp = phy_write(phydev, MII_STE100P_XCR_REG, temp & (~MII_STE100P_XCR_PWRDN));
++	//read for latch XCR REG	
++	phy_read(phydev, MII_STE100P_XCR_REG);
++	return temp;
++}
++
++static struct phy_driver ste100p_driver = {
++	.phy_id		= MII_STE100P_PHYID_VAL,
++	.name		= "STE100P",
++	.phy_id_mask	= MII_STE100P_PHYID_MASK,
++	.features	= PHY_BASIC_FEATURES,
++	.flags		= PHY_HAS_INTERRUPT,
++	.config_init	= &ste100p_config_init,
++	.config_intr	= &ste100p_config_intr,
++	.config_aneg	= &ste100p_config_aneg,
++	.suspend	= &ste100p_suspend,
++	.resume		= &ste100p_resume,
++	.ack_interrupt 	= &ste100p_ack_interrupt,
++	.read_status	= &genphy_read_status,
++	.driver 	= { .owner = THIS_MODULE,},
++};
++
++static int __init ste100p_init(void)
++{
++	return phy_driver_register(&ste100p_driver);
++}
++
++static void __exit ste100p_exit(void)
++{
++	phy_driver_unregister(&ste100p_driver);
++}
++
++module_init(ste100p_init);
++module_exit(ste100p_exit);
diff --git a/packages/linux/linux/sarge-at91/defconfig b/packages/linux/linux/sarge-at91/defconfig
new file mode 100644
index 0000000000..36d48a7b49
--- /dev/null
+++ b/packages/linux/linux/sarge-at91/defconfig
@@ -0,0 +1,1909 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.21.4
+# Wed Jun 13 02:03:51 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+
+#
+# AT91RM9200 Board Type
+#
+# CONFIG_MACH_ONEARM is not set
+# CONFIG_ARCH_AT91RM9200DK is not set
+# CONFIG_MACH_AT91RM9200EK is not set
+# CONFIG_MACH_CSB337 is not set
+# CONFIG_MACH_CSB637 is not set
+# CONFIG_MACH_CARMEVA is not set
+# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_KAFA is not set
+CONFIG_MACH_SARGE=y
+# CONFIG_MACH_CHUB is not set
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_ATMEL_TCLIB=y
+CONFIG_AT91_SLOW_CLOCK=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+
+#
+# PC-card bridges
+#
+CONFIG_AT91_CF=y
+
+#
+# Kernel Features
+#
+CONFIG_PREEMPT=y
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y