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authorKoen Kooi <koen@openembedded.org>2008-11-11 16:06:06 +0100
committerKoen Kooi <koen@openembedded.org>2008-11-11 16:06:06 +0100
commit022c55ed2377493c8774165d0fb2c124b91c3cc1 (patch)
tree845031f3471d5bb6271016f4d78303626b6f2a5a /packages
parente64327876b43fedcc8ef635ccc1a2f4f0f585791 (diff)
linux-omap git: update DSS2 patches and attempt to fix ASoC
Diffstat (limited to 'packages')
-rw-r--r--packages/linux/linux-omap/0003-DSS-Documentation-for-OMAP2-3-display-subsystem.patch6
-rw-r--r--packages/linux/linux-omap/0004-DSS-New-display-subsystem-driver-for-OMAP2-3.patch5169
-rw-r--r--packages/linux/linux-omap/0005-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch (renamed from packages/linux/linux-omap/0008-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch)51
-rw-r--r--packages/linux/linux-omap/0005-DSS-RFBI-support-for-OMAP2-3-DSS.patch1254
-rw-r--r--packages/linux/linux-omap/0006-DSS-Add-generic-DVI-panel.patch (renamed from packages/linux/linux-omap/0009-DSS-Add-generic-DVI-panel.patch)56
-rw-r--r--packages/linux/linux-omap/0006-DSS-TV-out-support-for-OMAP2-3-DSS.patch519
-rw-r--r--packages/linux/linux-omap/0007-DSS-DSI-support-for-OMAP2-3-DSS.patch3047
-rw-r--r--packages/linux/linux-omap/0007-DSS-support-for-Beagle-Board.patch (renamed from packages/linux/linux-omap/0010-DSS-support-for-Beagle-Board.patch)36
-rw-r--r--packages/linux/linux-omap/0008-DSS-BEAGLE-Enable-DSS-in-beagle-defconfig.patch453
-rw-r--r--packages/linux/linux-omap/0009-DSS-support-for-OMAP3-SDP-board.patch (renamed from packages/linux/linux-omap/0011-DSS-support-for-OMAP3-SDP-board.patch)64
-rw-r--r--packages/linux/linux-omap/beagleboard/defconfig10
-rw-r--r--packages/linux/linux-omap/fix-asoc.diff130
-rw-r--r--packages/linux/linux-omap_git.bb16
13 files changed, 5759 insertions, 5052 deletions
diff --git a/packages/linux/linux-omap/0003-DSS-Documentation-for-OMAP2-3-display-subsystem.patch b/packages/linux/linux-omap/0003-DSS-Documentation-for-OMAP2-3-display-subsystem.patch
index 59c15cee7d..4946bda5e7 100644
--- a/packages/linux/linux-omap/0003-DSS-Documentation-for-OMAP2-3-display-subsystem.patch
+++ b/packages/linux/linux-omap/0003-DSS-Documentation-for-OMAP2-3-display-subsystem.patch
@@ -1,4 +1,4 @@
-From 7a7fe8f7530bf5c7f3714acbe9a5ec8cf80c3d0c Mon Sep 17 00:00:00 2001
+From 58be9dfad433036ff46ed883c3bc77fca88079f7 Mon Sep 17 00:00:00 2001
From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Date: Tue, 4 Nov 2008 15:08:07 +0200
Subject: [PATCH] DSS: Documentation for OMAP2/3 display subsystem
@@ -11,7 +11,7 @@ Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
new file mode 100644
-index 0000000..b0cc980
+index 0000000..387bb73
--- /dev/null
+++ b/Documentation/arm/OMAP/DSS
@@ -0,0 +1,239 @@
@@ -41,7 +41,7 @@ index 0000000..b0cc980
+- Use CPU to update RFBI or DSI output
+- OMAP DISPC planes
+- RGB16, RGB24 packed, RGB24 unpacked
-+- YUV2, UYVY
++- YUV2, UYVY
+- Scaling
+- Adjusting DSS FCK to find a good pixel clock
+- Use DSI DPLL to create DSS FCK
diff --git a/packages/linux/linux-omap/0004-DSS-New-display-subsystem-driver-for-OMAP2-3.patch b/packages/linux/linux-omap/0004-DSS-New-display-subsystem-driver-for-OMAP2-3.patch
index febfc48c4d..509f34697a 100644
--- a/packages/linux/linux-omap/0004-DSS-New-display-subsystem-driver-for-OMAP2-3.patch
+++ b/packages/linux/linux-omap/0004-DSS-New-display-subsystem-driver-for-OMAP2-3.patch
@@ -1,32 +1,36 @@
-From 0cd726d12358cfe8d80fc0a309bb0c0732c716f0 Mon Sep 17 00:00:00 2001
+From 5a4331bf757fdec0ceb72bf40f7e46ce5c404e2d Mon Sep 17 00:00:00 2001
From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Tue, 4 Nov 2008 16:52:12 +0200
+Date: Tue, 11 Nov 2008 13:52:25 +0200
Subject: [PATCH] DSS: New display subsystem driver for OMAP2/3
-DSI, RFBI and VENC are separate patches
-
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
---
arch/arm/plat-omap/Kconfig | 2 +
arch/arm/plat-omap/Makefile | 2 +
- arch/arm/plat-omap/dss/Kconfig | 66 ++
+ arch/arm/plat-omap/dss/Kconfig | 66 +
arch/arm/plat-omap/dss/Makefile | 6 +
- arch/arm/plat-omap/dss/dispc.c | 1667 +++++++++++++++++++++++++++++
- arch/arm/plat-omap/dss/display.c | 781 ++++++++++++++
- arch/arm/plat-omap/dss/dpi.c | 303 ++++++
- arch/arm/plat-omap/dss/dss.c | 547 ++++++++++
- arch/arm/plat-omap/dss/dss.h | 240 +++++
- arch/arm/plat-omap/dss/sdi.c | 154 +++
- arch/arm/plat-omap/include/mach/display.h | 458 ++++++++
- 11 files changed, 4226 insertions(+), 0 deletions(-)
+ arch/arm/plat-omap/dss/dispc.c | 1720 ++++++++++++++++
+ arch/arm/plat-omap/dss/display.c | 775 ++++++++
+ arch/arm/plat-omap/dss/dpi.c | 323 +++
+ arch/arm/plat-omap/dss/dsi.c | 3022 +++++++++++++++++++++++++++++
+ arch/arm/plat-omap/dss/dss.c | 547 ++++++
+ arch/arm/plat-omap/dss/dss.h | 254 +++
+ arch/arm/plat-omap/dss/rfbi.c | 1234 ++++++++++++
+ arch/arm/plat-omap/dss/sdi.c | 157 ++
+ arch/arm/plat-omap/dss/venc.c | 515 +++++
+ arch/arm/plat-omap/include/mach/display.h | 458 +++++
+ 14 files changed, 9081 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-omap/dss/Kconfig
create mode 100644 arch/arm/plat-omap/dss/Makefile
create mode 100644 arch/arm/plat-omap/dss/dispc.c
create mode 100644 arch/arm/plat-omap/dss/display.c
create mode 100644 arch/arm/plat-omap/dss/dpi.c
+ create mode 100644 arch/arm/plat-omap/dss/dsi.c
create mode 100644 arch/arm/plat-omap/dss/dss.c
create mode 100644 arch/arm/plat-omap/dss/dss.h
+ create mode 100644 arch/arm/plat-omap/dss/rfbi.c
create mode 100644 arch/arm/plat-omap/dss/sdi.c
+ create mode 100644 arch/arm/plat-omap/dss/venc.c
create mode 100644 arch/arm/plat-omap/include/mach/display.h
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
@@ -54,7 +58,7 @@ index 1259846..2740497 100644
+obj-y += dss/
diff --git a/arch/arm/plat-omap/dss/Kconfig b/arch/arm/plat-omap/dss/Kconfig
new file mode 100644
-index 0000000..150cd24
+index 0000000..ef0b5d9
--- /dev/null
+++ b/arch/arm/plat-omap/dss/Kconfig
@@ -0,0 +1,66 @@
@@ -107,8 +111,8 @@ index 0000000..150cd24
+
+config OMAP2_DSS_MIN_FCK_PER_PCK
+ int "Minimum FCK/PCK ratio (for scaling)"
-+ range 1 32
-+ default 4
++ range 0 32
++ default 0
+ help
+ This can be used to adjust the minimum FCK/PCK ratio.
+
@@ -116,7 +120,7 @@ index 0000000..150cd24
+ n x PCK. Video plane scaling requires higher FCK than
+ normally.
+
-+ If this is set to 1, there's no extra constraint on the
++ If this is set to 0, there's no extra constraint on the
+ DISPC FCK. However, the FCK will at minimum be
+ 2xPCK (if active matrix) or 3xPCK (if passive matrix).
+
@@ -138,10 +142,10 @@ index 0000000..e98c6c1
+omap-dss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
diff --git a/arch/arm/plat-omap/dss/dispc.c b/arch/arm/plat-omap/dss/dispc.c
new file mode 100644
-index 0000000..8f5da2d
+index 0000000..6d06082
--- /dev/null
+++ b/arch/arm/plat-omap/dss/dispc.c
-@@ -0,0 +1,1667 @@
+@@ -0,0 +1,1720 @@
+/*
+ * linux/arch/arm/plat-omap/dss/dispc.c
+ *
@@ -255,8 +259,8 @@ index 0000000..8f5da2d
+ DISPC_IRQ_OCP_ERR | \
+ DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
+ DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
-+ DISPC_IRQ_SYNC_LOST)
-+/*DISPC_IRQ_SYNC_LOST_DIGIT*/
++ DISPC_IRQ_SYNC_LOST | \
++ DISPC_IRQ_SYNC_LOST_DIGIT)
+
+#define DISPC_MAX_NR_ISRS 8
+
@@ -1240,91 +1244,135 @@ index 0000000..8f5da2d
+ panel->acbi, panel->acb);
+}
+
-+unsigned long dispc_calc_clock_div(int is_tft, int pck, int *fck_div,
++void find_lck_pck_divs(int is_tft, unsigned long req_pck, unsigned long fck,
+ int *lck_div, int *pck_div)
+{
-+ unsigned long prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
-+ unsigned long pcd_min = is_tft ? 2 : 3;
-+ unsigned long best_pck = 0;
-+ int best_fd = 9, best_ld = 1, best_pd = 2;
-+ int fd, ld, pd;
++ int pcd_min = is_tft ? 2 : 3;
++ unsigned long best_pck;
++ int best_ld, cur_ld;
++ int best_pd, cur_pd;
+
-+ for (fd = 16; fd > 0; --fd) {
-+ unsigned long fck = prate / fd * 2;
-+
-+ if (fck > DISPC_MAX_FCK)
-+ continue;
++ best_pck = 0;
++ best_ld = 0;
++ best_pd = 0;
+
-+#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
-+ if (fck < pck * CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK)
-+ continue;
-+#endif
-+ for (ld = 1; ld <= 255; ++ld) {
-+ unsigned long lck = fck / ld;
++ for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
++ unsigned long lck = fck / cur_ld;
+
-+ for (pd = pcd_min; pd <= 255; ++pd) {
-+ int p = lck / pd;
++ for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
++ unsigned long pck = lck / cur_pd;
+
-+ if (abs(p - pck) < abs(best_pck - pck)) {
-+ best_pck = p;
-+ best_fd = fd;
-+ best_ld = ld;
-+ best_pd = pd;
-+ }
++ if (abs(pck - req_pck) < abs(best_pck - req_pck)) {
++ best_pck = pck;
++ best_ld = cur_ld;
++ best_pd = cur_pd;
+
-+ if (p == pck)
++ if (pck == req_pck)
+ goto found;
-+
-+ if (p < pck)
-+ break;
+ }
+
-+ if (lck / pcd_min < pck)
++ if (pck < req_pck)
+ break;
+ }
++
++ if (lck / pcd_min < req_pck)
++ break;
+ }
+
+found:
-+ *fck_div = best_fd;
+ *lck_div = best_ld;
+ *pck_div = best_pd;
-+
-+ return prate / best_fd * 2;
+}
+
-+void dispc_set_clock_div(int fck_div, int lck_div, int pck_div)
++int dispc_calc_clock_div(int is_tft, unsigned long req_pck,
++ struct dispc_clock_info *cinfo)
+{
-+ unsigned long prate;
++ unsigned long prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++ struct dispc_clock_info cur, best;
++ int match = 0;
++ int min_fck_per_pck;
++
++ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
++
++ if (min_fck_per_pck &&
++ req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
++ DSSERR("Requested pixel clock not possible with the current "
++ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
++ "the constraint off.\n");
++ min_fck_per_pck = 0;
++ }
+
-+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++retry:
++ memset(&cur, 0, sizeof(cur));
++ memset(&best, 0, sizeof(best));
+
-+ clk_set_rate(dispc.dpll4_m4_ck, prate / fck_div);
-+ dispc_set_lcd_divisor(lck_div, pck_div);
++ for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
++ cur.fck = prate / cur.fck_div * 2;
+
-+#ifdef DEBUG
-+ {
-+ unsigned long fck, lck, pck;
-+ fck = prate / fck_div * 2;
-+ lck = fck / lck_div;
-+ pck = lck / pck_div;
++ if (cur.fck > DISPC_MAX_FCK)
++ continue;
++
++ if (min_fck_per_pck &&
++ cur.fck < req_pck * min_fck_per_pck)
++ continue;
++
++ match = 1;
++
++ find_lck_pck_divs(is_tft, req_pck, cur.fck,
++ &cur.lck_div, &cur.pck_div);
++
++ cur.lck = cur.fck / cur.lck_div;
++ cur.pck = cur.lck / cur.pck_div;
+
-+ DSSDBG("dpll4_m4 = %ld\n", prate);
-+ DSSDBG("fck = %ld (%d)\n", fck, fck_div);
-+ DSSDBG("lck = %ld (%d)\n", lck, lck_div);
-+ DSSDBG("pck = %ld (%d)\n", pck, pck_div);
++ if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
++ best = cur;
++
++ if (cur.pck == req_pck)
++ goto found;
++ }
+ }
-+#endif
++
++found:
++ if (!match) {
++ if (min_fck_per_pck) {
++ DSSERR("Could not find suitable clock settings.\n"
++ "Turning FCK/PCK constraint off and"
++ "trying again.\n");
++ min_fck_per_pck = 0;
++ goto retry;
++ }
++
++ DSSERR("Could not find suitable clock settings.\n");
++
++ return -EINVAL;
++ }
++
++ if (cinfo)
++ *cinfo = best;
++
++ return 0;
+}
+
-+int dispc_pixel_clock_valid(int pixel_clock)
++int dispc_set_clock_div(struct dispc_clock_info *cinfo)
+{
-+ int fck_div, lck_div, pck_div;
-+ unsigned long fck;
++ unsigned long prate;
++ int r;
++
++ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++
++ r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
++
++ if (r)
++ return r;
++
++ dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
+
-+ fck = dispc_calc_clock_div(1, pixel_clock * 1000,
-+ &fck_div, &lck_div, &pck_div);
++ DSSDBG("dpll4_m4 = %ld\n", prate);
++ DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
++ DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
++ DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
+
-+ return fck > 0;
++ return 0;
+}
+
+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
@@ -1431,8 +1479,23 @@ index 0000000..8f5da2d
+ int i;
+ u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
+ static int errors;
++ u32 handledirqs = 0;
++
++#ifdef DEBUG
++ print_irq_status(irqstatus);
++#endif
+
-+ if (irqstatus & DISPC_IRQ_MASK_ERROR) {
++ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++ if (!registered_isr[i].isr)
++ continue;
++ if (registered_isr[i].mask & irqstatus) {
++ registered_isr[i].isr(registered_isr[i].arg,
++ irqstatus);
++ handledirqs |= registered_isr[i].mask;
++ }
++ }
++
++ if (irqstatus & ~handledirqs & DISPC_IRQ_MASK_ERROR) {
+ if (printk_ratelimit()) {
+ DSSERR("dispc irq error status %04x\n",
+ irqstatus);
@@ -1444,17 +1507,6 @@ index 0000000..8f5da2d
+ dispc_enable_digit_out(0);
+ }
+ }
-+#ifdef DEBUG
-+ print_irq_status(irqstatus);
-+#endif
-+
-+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
-+ if (!registered_isr[i].isr)
-+ continue;
-+ if (registered_isr[i].mask & irqstatus)
-+ registered_isr[i].isr(registered_isr[i].arg,
-+ irqstatus);
-+ }
+
+ /* ack the interrupt */
+ dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
@@ -1480,6 +1532,11 @@ index 0000000..8f5da2d
+{
+ memset(registered_isr, 0, sizeof(registered_isr));
+
++ /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
++ * so clear it */
++ dispc_write_reg(DISPC_IRQSTATUS,
++ dispc_read_reg(DISPC_IRQSTATUS));
++
+ /* We'll handle these always */
+ dispc_write_reg(DISPC_IRQENABLE, DISPC_IRQ_MASK_ERROR);
+}
@@ -1811,10 +1868,10 @@ index 0000000..8f5da2d
+
diff --git a/arch/arm/plat-omap/dss/display.c b/arch/arm/plat-omap/dss/display.c
new file mode 100644
-index 0000000..86f7d39
+index 0000000..4d7238f
--- /dev/null
+++ b/arch/arm/plat-omap/dss/display.c
-@@ -0,0 +1,781 @@
+@@ -0,0 +1,775 @@
+/*
+ * linux/arch/arm/plat-omap/dss/display.c
+ *
@@ -1843,7 +1900,6 @@ index 0000000..86f7d39
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/err.h>
-+#include <linux/delay.h>
+#include <linux/sysfs.h>
+#include <linux/clk.h>
+
@@ -2230,11 +2286,6 @@ index 0000000..86f7d39
+ dispc_enable_plane(ovl->id, 1);
+ }
+
-+ /* XXX if autoidle is enabled, we have to wait here a bit.
-+ * Otherwise if we issue GOLCD too soon after lcd enable,
-+ * we get sync lost. Why? */
-+ mdelay(100);
-+
+ dispc_go(mgr->id);
+
+ return 0;
@@ -2598,10 +2649,10 @@ index 0000000..86f7d39
+EXPORT_SYMBOL(omap_dss_unregister_panel);
diff --git a/arch/arm/plat-omap/dss/dpi.c b/arch/arm/plat-omap/dss/dpi.c
new file mode 100644
-index 0000000..d121b52
+index 0000000..2261288
--- /dev/null
+++ b/arch/arm/plat-omap/dss/dpi.c
-@@ -0,0 +1,303 @@
+@@ -0,0 +1,323 @@
+/*
+ * linux/arch/arm/plat-omap/dss/dpi.c
+ *
@@ -2674,23 +2725,32 @@ index 0000000..d121b52
+ }
+#else
+ {
-+ int fck_div;
-+ fck = dispc_calc_clock_div(is_tft,
-+ panel->timings.pixel_clock*1000,
-+ &fck_div, &lck_div, &pck_div);
++ struct dispc_clock_info cinfo;
++ dispc_calc_clock_div(is_tft, panel->timings.pixel_clock*1000,
++ &cinfo);
+
-+ if (fck == 0) {
-+ DSSERR("Requested pixel clock is not possible\n");
++ if (dispc_set_clock_div(&cinfo)) {
++ DSSERR("Failed to set DSS clocks\n");
+ return;
+ }
+
-+ dispc_set_clock_div(fck_div, lck_div, pck_div);
++ fck = cinfo.fck;
++ lck_div = cinfo.lck_div;
++ pck_div = cinfo.pck_div;
+ }
+#endif
+
+ pck = fck / lck_div / pck_div / 1000;
+
-+ panel->timings.pixel_clock = pck;
++ if (pck != panel->timings.pixel_clock) {
++ DSSWARN("Could not find exact pixel clock. Requested %d KHz, "
++ "got %lu KHz.\n",
++ panel->timings.pixel_clock,
++ pck);
++
++ panel->timings.pixel_clock = pck;
++ }
++
+ DSSDBG("fck %lu, lck_div %d, pck_div %d\n", fck, lck_div, pck_div);
+#ifdef DEBUG
+ {
@@ -2830,6 +2890,9 @@ index 0000000..d121b52
+static int dpi_check_timings(struct omap_display *display,
+ struct omap_video_timings *timings)
+{
++ int is_tft;
++ int r;
++
+ if (timings->hsw < 1 || timings->hsw > 64 ||
+ timings->hfp < 1 || timings->hfp > 256 ||
+ timings->hbp < 1 || timings->hbp > 256) {
@@ -2841,8 +2904,16 @@ index 0000000..d121b52
+ return -EINVAL;
+ }
+
-+ if (!dispc_pixel_clock_valid(timings->pixel_clock))
-+ return -EINVAL;
++
++ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++ r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000, 0);
++#else
++ r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000, 0);
++#endif
++ if (r)
++ return r;
+
+ return 0;
+}
@@ -2905,6 +2976,3034 @@ index 0000000..d121b52
+{
+}
+
+diff --git a/arch/arm/plat-omap/dss/dsi.c b/arch/arm/plat-omap/dss/dsi.c
+new file mode 100644
+index 0000000..980be39
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/dsi.c
+@@ -0,0 +1,3022 @@
++/*
++ * linux/arch/arm/plat-omap/dss/dsi.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DSI"
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/workqueue.h>
++#include <linux/mutex.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++
++#include "dss.h"
++
++/*#define VERBOSE*/
++/*#define VERBOSE_IRQ*/
++/*#define MEASURE_PERF*/
++
++#define DSI_BASE 0x4804FC00
++
++struct dsi_reg { u16 idx; };
++
++#define DSI_REG(idx) ((const struct dsi_reg) { idx })
++
++/* DSI Protocol Engine */
++
++#define DSI_REVISION DSI_REG(0x0000)
++#define DSI_SYSCONFIG DSI_REG(0x0010)
++#define DSI_SYSSTATUS DSI_REG(0x0014)
++#define DSI_IRQSTATUS DSI_REG(0x0018)
++#define DSI_IRQENABLE DSI_REG(0x001C)
++#define DSI_CTRL DSI_REG(0x0040)
++#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
++#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
++#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
++#define DSI_CLK_CTRL DSI_REG(0x0054)
++#define DSI_TIMING1 DSI_REG(0x0058)
++#define DSI_TIMING2 DSI_REG(0x005C)
++#define DSI_VM_TIMING1 DSI_REG(0x0060)
++#define DSI_VM_TIMING2 DSI_REG(0x0064)
++#define DSI_VM_TIMING3 DSI_REG(0x0068)
++#define DSI_CLK_TIMING DSI_REG(0x006C)
++#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
++#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
++#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
++#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
++#define DSI_VM_TIMING4 DSI_REG(0x0080)
++#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
++#define DSI_VM_TIMING5 DSI_REG(0x0088)
++#define DSI_VM_TIMING6 DSI_REG(0x008C)
++#define DSI_VM_TIMING7 DSI_REG(0x0090)
++#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
++#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
++#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
++#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
++#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
++#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
++#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
++#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
++
++/* DSIPHY_SCP */
++
++#define DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
++#define DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
++#define DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
++#define DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
++
++/* DSI_PLL_CTRL_SCP */
++
++#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
++#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
++#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
++#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
++#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
++
++#define REG_GET(idx, start, end) \
++ FLD_GET(dsi_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end) \
++ dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
++
++/* Global interrupts */
++#define DSI_IRQ_VC0 (1 << 0)
++#define DSI_IRQ_VC1 (1 << 1)
++#define DSI_IRQ_VC2 (1 << 2)
++#define DSI_IRQ_VC3 (1 << 3)
++#define DSI_IRQ_WAKEUP (1 << 4)
++#define DSI_IRQ_RESYNC (1 << 5)
++#define DSI_IRQ_PLL_LOCK (1 << 7)
++#define DSI_IRQ_PLL_UNLOCK (1 << 8)
++#define DSI_IRQ_PLL_RECALL (1 << 9)
++#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
++#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
++#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
++#define DSI_IRQ_TE_TRIGGER (1 << 16)
++#define DSI_IRQ_ACK_TRIGGER (1 << 17)
++#define DSI_IRQ_SYNC_LOST (1 << 18)
++#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
++#define DSI_IRQ_TA_TIMEOUT (1 << 20)
++#define DSI_IRQ_ERROR_MASK \
++ (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
++ DSI_IRQ_TA_TIMEOUT)
++#define DSI_IRQ_CHANNEL_MASK 0xf
++
++/* Virtual channel interrupts */
++#define DSI_VC_IRQ_CS (1 << 0)
++#define DSI_VC_IRQ_ECC_CORR (1 << 1)
++#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
++#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
++#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
++#define DSI_VC_IRQ_BTA (1 << 5)
++#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
++#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
++#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
++#define DSI_VC_IRQ_ERROR_MASK \
++ (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
++ DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
++ DSI_VC_IRQ_FIFO_TX_UDF)
++
++/* ComplexIO interrupts */
++#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
++#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
++#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
++#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
++#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
++#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
++#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
++#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
++#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
++#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
++#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
++#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
++
++#define DSI_DT_DCS_SHORT_WRITE_0 0x05
++#define DSI_DT_DCS_SHORT_WRITE_1 0x15
++#define DSI_DT_DCS_READ 0x06
++#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
++#define DSI_DT_NULL_PACKET 0x09
++#define DSI_DT_DCS_LONG_WRITE 0x39
++
++#define DSI_DT_RX_ACK_WITH_ERR 0x02
++#define DSI_DT_RX_DCS_LONG_READ 0x1c
++#define DSI_DT_RX_SHORT_READ_1 0x21
++#define DSI_DT_RX_SHORT_READ_2 0x22
++
++#define FINT_MAX 2100000
++#define FINT_MIN 750000
++#define REGN_MAX (1 << 7)
++#define REGM_MAX ((1 << 11) - 1)
++#define REGM3_MAX (1 << 4)
++#define REGM4_MAX (1 << 4)
++
++enum fifo_size {
++ DSI_FIFO_SIZE_0 = 0,
++ DSI_FIFO_SIZE_32 = 1,
++ DSI_FIFO_SIZE_64 = 2,
++ DSI_FIFO_SIZE_96 = 3,
++ DSI_FIFO_SIZE_128 = 4,
++};
++
++static struct
++{
++ void __iomem *base;
++
++ struct clk *dss_ick;
++ struct clk *dss1_fck;
++ struct clk *dss2_fck;
++
++ unsigned long dsi1_pll_fclk; /* Hz */
++ unsigned long dsi2_pll_fclk; /* Hz */
++ unsigned long dsiphy; /* Hz */
++ unsigned long ddr_clk; /* Hz */
++
++ struct {
++ enum fifo_size fifo_size;
++ int dest_per; /* destination peripheral 0-3 */
++ } vc[4];
++
++ struct mutex lock;
++
++ struct completion bta_completion;
++
++ spinlock_t update_lock;
++ int update_ongoing;
++ int update_syncers;
++ struct completion update_completion;
++ struct work_struct framedone_work;
++
++ enum omap_dss_update_mode update_mode;
++ int use_te;
++ int framedone_scheduled; /* helps to catch strange framedone bugs */
++
++ struct {
++ struct omap_display *display;
++ int x, y, w, h;
++ int bytespp;
++ } update_region;
++
++#ifdef MEASURE_PERF
++ ktime_t measure_time;
++ int measure_frames;
++#endif
++} dsi;
++
++
++static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
++{
++ __raw_writel(val, dsi.base + idx.idx);
++}
++
++static inline u32 dsi_read_reg(const struct dsi_reg idx)
++{
++ return __raw_readl(dsi.base + idx.idx);
++}
++
++static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
++ int value)
++{
++ int t = 1000;
++
++ while (REG_GET(idx, bitnum, bitnum) != value) {
++ if (--t == 0)
++ return !value;
++ }
++
++ return value;
++}
++
++
++#ifdef MEASURE_PERF
++static void start_measuring(void)
++{
++ dsi.measure_time = ktime_get();
++}
++
++static void end_measuring(const char *name)
++{
++ ktime_t t;
++ u32 total_bytes;
++ u32 us;
++ const int numframes = 100;
++
++ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
++ return;
++
++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
++ dsi.measure_frames++;
++ if (dsi.measure_frames < numframes)
++ return;
++ dsi.measure_frames = 0;
++ }
++
++ t = ktime_get();
++ t = ktime_sub(t, dsi.measure_time);
++ us = (u32)ktime_to_us(t);
++ if (us == 0)
++ us = 1;
++
++ total_bytes = dsi.update_region.w *
++ dsi.update_region.h *
++ dsi.update_region.bytespp;
++
++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
++ DSSINFO("%s update: %d frames in %u us, %u frames/sec\n",
++ name, numframes,
++ us,
++ 1000*1000 / us);
++ } else {
++ DSSINFO("%s update in %u us (%u Hz), %u bytes, %u kbytes/sec\n",
++ name,
++ us,
++ 1000*1000 / us,
++ total_bytes,
++ total_bytes * 1000 / us);
++ }
++}
++#else
++#define start_measuring()
++#define end_measuring(x)
++#endif
++
++
++
++
++static void print_irq_status(u32 status)
++{
++#ifndef VERBOSE_IRQ
++ if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
++ return;
++#endif
++ printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
++
++#define PIS(x) \
++ if (status & DSI_IRQ_##x) \
++ printk(#x " ");
++#ifdef VERBOSE_IRQ
++ PIS(VC0);
++ PIS(VC1);
++ PIS(VC2);
++ PIS(VC3);
++#endif
++ PIS(WAKEUP);
++ PIS(RESYNC);
++ PIS(PLL_LOCK);
++ PIS(PLL_UNLOCK);
++ PIS(PLL_RECALL);
++ PIS(COMPLEXIO_ERR);
++ PIS(HS_TX_TIMEOUT);
++ PIS(LP_RX_TIMEOUT);
++ PIS(TE_TRIGGER);
++ PIS(ACK_TRIGGER);
++ PIS(SYNC_LOST);
++ PIS(LDO_POWER_GOOD);
++ PIS(TA_TIMEOUT);
++#undef PIS
++
++ printk("\n");
++}
++
++static void print_irq_status_vc(int channel, u32 status)
++{
++#ifndef VERBOSE_IRQ
++ if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
++ return;
++#endif
++ printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
++
++#define PIS(x) \
++ if (status & DSI_VC_IRQ_##x) \
++ printk(#x " ");
++ PIS(CS);
++ PIS(ECC_CORR);
++#ifdef VERBOSE_IRQ
++ PIS(PACKET_SENT);
++#endif
++ PIS(FIFO_TX_OVF);
++ PIS(FIFO_RX_OVF);
++ PIS(BTA);
++ PIS(ECC_NO_CORR);
++ PIS(FIFO_TX_UDF);
++ PIS(PP_BUSY_CHANGE);
++#undef PIS
++ printk("\n");
++}
++
++static void print_irq_status_cio(u32 status)
++{
++ printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
++
++#define PIS(x) \
++ if (status & DSI_CIO_IRQ_##x) \
++ printk(#x " ");
++ PIS(ERRSYNCESC1);
++ PIS(ERRSYNCESC2);
++ PIS(ERRSYNCESC3);
++ PIS(ERRESC1);
++ PIS(ERRESC2);
++ PIS(ERRESC3);
++ PIS(ERRCONTROL1);
++ PIS(ERRCONTROL2);
++ PIS(ERRCONTROL3);
++ PIS(STATEULPS1);
++ PIS(STATEULPS2);
++ PIS(STATEULPS3);
++ PIS(ERRCONTENTIONLP0_1);
++ PIS(ERRCONTENTIONLP1_1);
++ PIS(ERRCONTENTIONLP0_2);
++ PIS(ERRCONTENTIONLP1_2);
++ PIS(ERRCONTENTIONLP0_3);
++ PIS(ERRCONTENTIONLP1_3);
++ PIS(ULPSACTIVENOT_ALL0);
++ PIS(ULPSACTIVENOT_ALL1);
++#undef PIS
++
++ printk("\n");
++}
++
++static int debug_irq;
++
++/* called from dss */
++void dsi_irq_handler(void)
++{
++ u32 irqstatus, vcstatus, ciostatus;
++ int i;
++
++ irqstatus = dsi_read_reg(DSI_IRQSTATUS);
++
++ if (irqstatus & DSI_IRQ_ERROR_MASK) {
++ DSSERR("DSI error, irqstatus %x\n", irqstatus);
++ print_irq_status(irqstatus);
++ } else if (debug_irq) {
++ print_irq_status(irqstatus);
++ }
++
++ for (i = 0; i < 4; ++i) {
++ if ((irqstatus & (1<<i)) == 0)
++ continue;
++
++ vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
++
++ if (vcstatus & DSI_VC_IRQ_BTA)
++ complete(&dsi.bta_completion);
++
++ if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
++ DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
++ i, vcstatus);
++ print_irq_status_vc(i, vcstatus);
++ } else if (debug_irq) {
++ print_irq_status_vc(i, vcstatus);
++ }
++
++ dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
++ }
++
++ if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
++ ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
++
++ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
++
++ DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
++ print_irq_status_cio(ciostatus);
++ }
++
++ dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
++}
++
++
++static void _dsi_initialize_irq(void)
++{
++ u32 l;
++ int i;
++
++ /* disable all interrupts */
++ dsi_write_reg(DSI_IRQENABLE, 0);
++ for (i = 0; i < 4; ++i)
++ dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
++ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
++
++ /* clear interrupt status */
++ l = dsi_read_reg(DSI_IRQSTATUS);
++ dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
++
++ for (i = 0; i < 4; ++i) {
++ l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
++ dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
++ }
++
++ l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
++ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
++
++ /* enable error irqs */
++ l = DSI_IRQ_ERROR_MASK;
++ dsi_write_reg(DSI_IRQENABLE, l);
++
++ l = DSI_VC_IRQ_ERROR_MASK;
++ for (i = 0; i < 4; ++i)
++ dsi_write_reg(DSI_VC_IRQENABLE(i), l);
++
++ /* XXX zonda responds incorrectly, causing control error:
++ Exit from LP-ESC mode to LP11 uses wrong transition states on the
++ data lines LP0 and LN0. */
++ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
++ -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
++}
++
++static void dsi_vc_enable_bta_irq(int channel)
++{
++ u32 l;
++
++ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
++ l |= DSI_VC_IRQ_BTA;
++ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
++}
++
++static void dsi_vc_disable_bta_irq(int channel)
++{
++ u32 l;
++
++ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
++ l &= ~DSI_VC_IRQ_BTA;
++ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
++}
++
++/* DSI func clock. this could also be DSI2_PLL_FCLK */
++static inline void enable_clocks(int enable)
++{
++ if (enable) {
++ clk_enable(dsi.dss_ick);
++ clk_enable(dsi.dss1_fck);
++ } else {
++ clk_disable(dsi.dss1_fck);
++ clk_disable(dsi.dss_ick);
++ }
++}
++
++/* source clock for DSI PLL. this could also be PCLKFREE */
++static inline void dsi_enable_pll_clock(int enable)
++{
++ if (enable)
++ clk_enable(dsi.dss2_fck);
++ else
++ clk_disable(dsi.dss2_fck);
++}
++
++#if 1
++
++#ifdef DEBUG
++static void _dsi_print_reset_status(void)
++{
++ u32 l;
++
++ /* A dummy read using the SCP interface to any DSIPHY register is
++ * required after DSIPHY reset to complete the reset of the DSI complex
++ * I/O. */
++ l = dsi_read_reg(DSIPHY_CFG5);
++
++ printk(KERN_DEBUG "DSI resets: ");
++
++ l = dsi_read_reg(DSI_PLL_STATUS);
++ printk("PLL (%d) ", FLD_GET(l, 0, 0));
++
++ l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
++ printk("CIO (%d) ", FLD_GET(l, 29, 29));
++
++ l = dsi_read_reg(DSIPHY_CFG5);
++ printk("PHY (%x, %d, %d, %d)\n",
++ FLD_GET(l, 28, 26),
++ FLD_GET(l, 29, 29),
++ FLD_GET(l, 30, 30),
++ FLD_GET(l, 31, 31));
++}
++#else
++#define _dsi_print_reset_status()
++#endif
++
++static int _dsi_reset(void)
++{
++ int r = 0;
++
++ /* Soft reset */
++ REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
++
++ if (wait_for_bit_change(DSI_SYSSTATUS, 0, 1) != 1) {
++ DSSERR("soft reset failed\n");
++ r = -ENODEV;
++ }
++
++ /* A dummy read using the SCP interface to any DSIPHY register is
++ * required after DSIPHY reset to complete the reset of the DSI complex
++ * I/O. */
++ dsi_read_reg(DSIPHY_CFG5);
++
++ _dsi_print_reset_status();
++
++ return r;
++}
++#endif
++
++static inline int dsi_if_enable(int enable)
++{
++ DSSDBG("dsi_if_enable(%d)\n", enable);
++
++ enable = enable ? 1 : 0;
++ REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
++
++ if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
++ DSSERR("Failed to set dsi_if_enable to %d\n", enable);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static unsigned long dsi_fclk_rate(void)
++{
++ unsigned long r;
++
++ if (dss_get_dsi_clk_source() == 0) {
++ /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
++ r = clk_get_rate(dsi.dss1_fck);
++ } else {
++ /* DSI FCLK source is DSI2_PLL_FCLK */
++ r = dsi.dsi2_pll_fclk;
++ }
++
++ return r;
++}
++
++static int dsi_set_lp_clk_divisor(void)
++{
++ int n;
++ unsigned long dsi_fclk;
++ unsigned long mhz;
++
++ /* LP_CLK_DIVISOR, DSI fclk/n, should be 20MHz - 32kHz */
++
++ dsi_fclk = dsi_fclk_rate();
++
++ for (n = 1; n < (1 << 13) - 1; ++n) {
++ mhz = dsi_fclk / n;
++ if (mhz <= 20*1000*1000)
++ break;
++ }
++
++ if (n == (1 << 13) - 1) {
++ DSSERR("DSI: Failed to find LP_CLK_DIVISOR\n");
++ return -EINVAL;
++ }
++
++ DSSDBG("LP_CLK_DIV %d, LP_CLK %ld\n", n, mhz);
++
++ REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0); /* LP_CLK_DIVISOR */
++ if (dsi_fclk > 30*1000*1000)
++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */
++
++ return 0;
++}
++
++
++enum dsi_pll_power_state {
++ DSI_PLL_POWER_OFF = 0x0,
++ DSI_PLL_POWER_ON_HSCLK = 0x1,
++ DSI_PLL_POWER_ON_ALL = 0x2,
++ DSI_PLL_POWER_ON_DIV = 0x3,
++};
++
++static int dsi_pll_power(enum dsi_pll_power_state state)
++{
++ int t = 0;
++
++ REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
++
++ /* PLL_PWR_STATUS */
++ while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
++ udelay(1);
++ if (t++ > 1000) {
++ DSSERR("DSI: Failed to set DSI PLL power mode to %d\n",
++ state);
++ return -ENODEV;
++ }
++ }
++
++ return 0;
++}
++
++int dsi_pll_calc_pck(int is_tft, unsigned long req_pck,
++ struct dsi_clock_info *cinfo)
++{
++ struct dsi_clock_info cur, best;
++ int min_fck_per_pck;
++ int match = 0;
++
++ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
++
++ if (min_fck_per_pck &&
++ req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
++ DSSERR("Requested pixel clock not possible with the current "
++ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
++ "the constraint off.\n");
++ min_fck_per_pck = 0;
++ }
++
++ DSSDBG("dsi_pll_calc\n");
++
++retry:
++ memset(&best, 0, sizeof(best));
++
++ memset(&cur, 0, sizeof(cur));
++ cur.clkin = clk_get_rate(dsi.dss2_fck);
++ cur.use_dss2_fck = 1;
++ cur.highfreq = 0;
++
++ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
++ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
++ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
++ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
++ if (cur.highfreq == 0)
++ cur.fint = cur.clkin / cur.regn;
++ else
++ cur.fint = cur.clkin / (2 * cur.regn);
++
++ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
++ continue;
++
++ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
++ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
++ unsigned long a, b;
++
++ a = 2 * cur.regm * (cur.clkin/1000);
++ b = cur.regn * (cur.highfreq + 1);
++ cur.dsiphy = a / b * 1000;
++
++ if (cur.dsiphy > 1800 * 1000 * 1000)
++ break;
++
++ /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
++ for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
++ ++cur.regm3) {
++ cur.dispc_fck = cur.dsiphy / cur.regm3;
++
++ /* this will narrow down the search a bit,
++ * but still give pixclocks below what was
++ * requested */
++ if (cur.dispc_fck < req_pck)
++ break;
++
++ if (cur.dispc_fck > DISPC_MAX_FCK)
++ continue;
++
++ if (min_fck_per_pck &&
++ cur.dispc_fck < req_pck * min_fck_per_pck)
++ continue;
++
++ match = 1;
++
++ find_lck_pck_divs(is_tft, req_pck,
++ cur.dispc_fck,
++ &cur.lck_div,
++ &cur.pck_div);
++
++ cur.lck = cur.dispc_fck / cur.lck_div;
++ cur.pck = cur.lck / cur.pck_div;
++
++ if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
++ best = cur;
++
++ if (cur.pck == req_pck)
++ goto found;
++ }
++ }
++ }
++ }
++found:
++ if (!match) {
++ if (min_fck_per_pck) {
++ DSSERR("Could not find suitable clock settings.\n"
++ "Turning FCK/PCK constraint off and"
++ "trying again.\n");
++ min_fck_per_pck = 0;
++ goto retry;
++ }
++
++ DSSERR("Could not find suitable clock settings.\n");
++
++ return -EINVAL;
++ }
++
++ /* DSI2_PLL_FCLK(MHz) = DSIPHY(MHz) / regm4 < 173MHz */
++ /* hardcoded 48MHz for now. what should it be? */
++ best.regm4 = best.dsiphy / 48000000;
++ if (best.regm4 > REGM4_MAX)
++ best.regm4 = REGM4_MAX;
++ best.dsi_fck = best.dsiphy / best.regm4;
++
++ if (cinfo)
++ *cinfo = best;
++
++ return 0;
++}
++
++static int dsi_pll_calc_datafreq(unsigned long datafreq,
++ struct dsi_clock_info *cinfo)
++{
++ struct dsi_clock_info cur, best;
++ const int use_dss2_fck = 1;
++
++ DSSDBG("dsi_pll_calc_datarate\n");
++
++ memset(&best, 0, sizeof(best));
++
++ memset(&cur, 0, sizeof(cur));
++ cur.use_dss2_fck = use_dss2_fck;
++ if (use_dss2_fck) {
++ cur.clkin = clk_get_rate(dsi.dss2_fck);
++ cur.highfreq = 0;
++ } else {
++ cur.clkin = dispc_pclk_rate();
++ if (cur.clkin < 32000000)
++ cur.highfreq = 0;
++ else
++ cur.highfreq = 1;
++ }
++
++ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
++ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
++ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
++ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
++ if (cur.highfreq == 0)
++ cur.fint = cur.clkin / cur.regn;
++ else
++ cur.fint = cur.clkin / (2 * cur.regn);
++
++ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
++ continue;
++
++ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
++ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
++ unsigned long a, b;
++
++ a = 2 * cur.regm * (cur.clkin/1000);
++ b = cur.regn * (cur.highfreq + 1);
++ cur.dsiphy = a / b * 1000;
++
++ if (cur.dsiphy > 1800 * 1000 * 1000)
++ break;
++
++ if (abs(cur.dsiphy - datafreq) <
++ abs(best.dsiphy - datafreq)) {
++ best = cur;
++ /* DSSDBG("best %ld\n", best.dsiphy); */
++ }
++
++ if (cur.dsiphy == datafreq)
++ goto found;
++ }
++ }
++found:
++ /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
++ /* hardcoded 48MHz for now. what should it be? */
++ best.regm3 = best.dsiphy / (48000000);
++ if (best.regm3 > REGM3_MAX)
++ best.regm3 = REGM3_MAX;
++ best.dispc_fck = best.dsiphy / best.regm3;
++
++ /* DSI2_PLL_FCLK(MHz) = DSIPHY(MHz) / regm4 < 173MHz */
++ /* hardcoded 48MHz for now. what should it be? */
++ best.regm4 = best.dsiphy / (48000000);
++ if (best.regm4 > REGM4_MAX)
++ best.regm4 = REGM4_MAX;
++ best.dsi_fck = best.dsiphy / best.regm4;
++
++ if (cinfo)
++ *cinfo = best;
++
++ return 0;
++}
++
++int dsi_pll_program(struct dsi_clock_info *cinfo)
++{
++ int r = 0;
++ u32 l;
++
++ DSSDBG("dsi_pll_program\n");
++
++ enable_clocks(1);
++
++ dsi.dsiphy = cinfo->dsiphy;
++ dsi.ddr_clk = dsi.dsiphy / 4;
++ dsi.dsi1_pll_fclk = cinfo->dispc_fck;
++ dsi.dsi2_pll_fclk = cinfo->dsi_fck;
++
++ DSSDBG("DSI Fint %ld\n", cinfo->fint);
++
++ DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
++ cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
++ cinfo->clkin,
++ cinfo->highfreq);
++
++ /* DSIPHY == CLKIN4DDR */
++ DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n",
++ cinfo->regm,
++ cinfo->regn,
++ cinfo->clkin,
++ cinfo->highfreq + 1,
++ cinfo->dsiphy);
++
++ DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
++ dsi.dsiphy / 1000 / 1000 / 2);
++
++ DSSDBG("Clock lane freq %ld Hz\n", dsi.ddr_clk);
++
++ DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
++ cinfo->regm3, cinfo->dispc_fck);
++ DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
++ cinfo->regm4, cinfo->dsi_fck);
++
++ REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
++
++ l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
++ l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
++ l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
++ l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
++ l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19); /* DSI_CLOCK_DIV */
++ l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23); /* DSIPROTO_CLOCK_DIV */
++ dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
++
++ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
++ l = FLD_MOD(l, 7, 4, 1); /* DSI_PLL_FREQSEL */
++ /* DSI_PLL_CLKSEL */
++ l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11);
++ l = FLD_MOD(l, cinfo->highfreq, 12, 12); /* DSI_PLL_HIGHFREQ */
++ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
++ l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
++ l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
++ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
++
++ REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
++
++ if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
++ DSSERR("dsi pll go bit not going down.\n");
++ r = -EIO;
++ goto err;
++ }
++
++ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
++ DSSERR("DSI: cannot lock PLL\n");
++ r = -EIO;
++ goto err;
++ }
++
++ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
++ l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
++ l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
++ l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
++ l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
++ l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
++ l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
++ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
++ l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
++ l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
++ l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
++ l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
++ l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
++ l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
++ l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
++ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
++
++ DSSDBG("PLL config done\n");
++err:
++ enable_clocks(0);
++
++ return r;
++}
++
++int dsi_pll_init(int enable_hsclk, int enable_hsdiv)
++{
++ int r = 0;
++ enum dsi_pll_power_state pwstate;
++ struct dispc_clock_info cinfo;
++
++ DSSDBG("PLL init\n");
++
++ enable_clocks(1);
++ dsi_enable_pll_clock(1);
++
++ /* configure dispc fck and pixel clock to something sane */
++ r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
++ if (r)
++ return r;
++
++ r = dispc_set_clock_div(&cinfo);
++ if (r)
++ return r;
++
++ /* PLL does not come out of reset without this... */
++ dispc_pck_free_enable(1);
++
++ if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
++ DSSERR("DSI: PLL not coming out of reset.\n");
++ r = -ENODEV;
++ goto err;
++ }
++
++ /* ... but if left on, we get problems when planes do not
++ * fill the whole display. No idea about this XXX */
++ dispc_pck_free_enable(0);
++
++ if (enable_hsclk && enable_hsdiv)
++ pwstate = DSI_PLL_POWER_ON_ALL;
++ else if (enable_hsclk)
++ pwstate = DSI_PLL_POWER_ON_HSCLK;
++ else if (enable_hsdiv)
++ pwstate = DSI_PLL_POWER_ON_DIV;
++ else
++ pwstate = DSI_PLL_POWER_OFF;
++
++ r = dsi_pll_power(pwstate);
++
++ if (r)
++ goto err;
++
++ enable_clocks(0);
++
++ DSSDBG("PLL init done\n");
++
++ return 0;
++err:
++ enable_clocks(0);
++ dsi_enable_pll_clock(0);
++ return r;
++}
++
++void dsi_pll_uninit(void)
++{
++ dsi_pll_power(DSI_PLL_POWER_OFF);
++ dsi_enable_pll_clock(0);
++ DSSDBG("PLL uninit done\n");
++}
++
++unsigned long dsi_get_dsi1_pll_rate(void)
++{
++ return dsi.dsi1_pll_fclk;
++}
++
++unsigned long dsi_get_dsi2_pll_rate(void)
++{
++ return dsi.dsi2_pll_fclk;
++}
++
++ssize_t dsi_print_clocks(char *buf, ssize_t size)
++{
++ ssize_t l = 0;
++ int clksel;
++
++ enable_clocks(1);
++
++ clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
++
++ l += snprintf(buf + l, size - l, "- dsi -\n");
++
++ l += snprintf(buf + l, size - l, "dsi fclk source = %s\n",
++ dss_get_dsi_clk_source() == 0 ?
++ "dss1_alwon_fclk" : "dsi2_pll_fclk");
++
++ l += snprintf(buf + l, size - l, "dsi pll source = %s\n",
++ clksel == 0 ?
++ "dss2_alwon_fclk" : "pclkfree");
++
++ l += snprintf(buf + l, size - l,
++ "DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n",
++ dsi.dsiphy, dsi.ddr_clk);
++
++ l += snprintf(buf + l, size - l,
++ "dsi1_pll_fck\t%lu (%s)\n"
++ "dsi2_pll_fck\t%lu (%s)\n",
++ dsi.dsi1_pll_fclk,
++ dss_get_dispc_clk_source() == 0 ? "off" : "on",
++ dsi.dsi2_pll_fclk,
++ dss_get_dsi_clk_source() == 0 ? "off" : "on");
++
++ enable_clocks(0);
++
++ return l;
++}
++
++
++enum dsi_complexio_power_state {
++ DSI_COMPLEXIO_POWER_OFF = 0x0,
++ DSI_COMPLEXIO_POWER_ON = 0x1,
++ DSI_COMPLEXIO_POWER_ULPS = 0x2,
++};
++
++static int dsi_complexio_power(enum dsi_complexio_power_state state)
++{
++ int t = 0;
++
++ /* PWR_CMD */
++ REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
++
++ /* PWR_STATUS */
++ while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
++ udelay(1);
++ if (t++ > 1000) {
++ DSSERR("DSI: failed to set complexio power state to "
++ "%d\n", state);
++ return -ENODEV;
++ }
++ }
++
++ return 0;
++}
++
++static void dsi_complexio_config(struct omap_display *display)
++{
++ u32 r;
++
++ int clk_lane = display->hw_config.u.dsi.clk_lane;
++ int data1_lane = display->hw_config.u.dsi.data1_lane;
++ int data2_lane = display->hw_config.u.dsi.data2_lane;
++ int clk_pol = display->hw_config.u.dsi.clk_pol;
++ int data1_pol = display->hw_config.u.dsi.data1_pol;
++ int data2_pol = display->hw_config.u.dsi.data2_pol;
++
++ r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
++ r = FLD_MOD(r, clk_lane, 2, 0);
++ r = FLD_MOD(r, clk_pol, 3, 3);
++ r = FLD_MOD(r, data1_lane, 6, 4);
++ r = FLD_MOD(r, data1_pol, 7, 7);
++ r = FLD_MOD(r, data2_lane, 10, 8);
++ r = FLD_MOD(r, data2_pol, 11, 11);
++ dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
++
++ /* The configuration of the DSI complex I/O (number of data lanes,
++ position, differential order) should not be changed while
++ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
++ the hardware to take into account a new configuration of the complex
++ I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
++ follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
++ then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
++ DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
++ DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
++ DSI complex I/O configuration is unknown. */
++
++ /*
++ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
++ REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
++ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
++ */
++}
++
++static inline int ns2ddr(int ns)
++{
++ /* convert time in ns to ddr ticks, rounding up */
++ return (ns * (dsi.ddr_clk/1000/1000) + 999) / 1000;
++}
++
++static void dsi_complexio_timings(void)
++{
++ u32 r;
++ u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
++ u32 tlpx_half, tclk_trail, tclk_zero;
++ u32 tclk_prepare;
++
++ /* calculate timings */
++
++ /* 1 * DDR_CLK = 2 * UI */
++
++ /* min 40ns + 4*UI max 85ns + 6*UI */
++ ths_prepare = ns2ddr(59) + 2;
++
++ /* min 145ns + 10*UI */
++ ths_prepare_ths_zero = ns2ddr(145) + 5;
++
++ /* min max(8*UI, 60ns+4*UI) */
++ ths_trail = max(4, ns2ddr(60) + 2);
++
++ /* min 100ns */
++ ths_exit = ns2ddr(100);
++
++ /* tlpx min 50n */
++ tlpx_half = ns2ddr(25);
++
++ /* min 60ns */
++ tclk_trail = ns2ddr(60);
++
++ /* min 38ns, max 95ns */
++ tclk_prepare = ns2ddr(38);
++
++ /* min tclk-prepare + tclk-zero = 300ns */
++ tclk_zero = ns2ddr(300 - 38);
++
++#ifdef VERBOSE
++ DSSDBG("ths_prepare %d, ths_prepare_ths_zero %d\n",
++ ths_prepare, ths_prepare_ths_zero);
++ DSSDBG("ths_trail %d, ths_exit %d\n", ths_trail, ths_exit);
++
++
++ DSSDBG("tlpx_half %d, tclk_trail %d, tclk_zero %d\n", tlpx_half,
++ tclk_trail, tclk_zero);
++ DSSDBG("tclk_prepare %d\n", tclk_prepare);
++#endif
++
++ /* program timings */
++
++ r = dsi_read_reg(DSIPHY_CFG0);
++ r = FLD_MOD(r, ths_prepare, 31, 24);
++ r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
++ r = FLD_MOD(r, ths_trail, 15, 8);
++ r = FLD_MOD(r, ths_exit, 7, 0);
++ dsi_write_reg(DSIPHY_CFG0, r);
++
++ r = dsi_read_reg(DSIPHY_CFG1);
++ r = FLD_MOD(r, tlpx_half, 22, 16);
++ r = FLD_MOD(r, tclk_trail, 15, 8);
++ r = FLD_MOD(r, tclk_zero, 7, 0);
++ dsi_write_reg(DSIPHY_CFG1, r);
++
++ r = dsi_read_reg(DSIPHY_CFG2);
++ r = FLD_MOD(r, tclk_prepare, 7, 0);
++ dsi_write_reg(DSIPHY_CFG2, r);
++}
++
++
++static int dsi_complexio_init(struct omap_display *display)
++{
++ int r = 0;
++
++ DSSDBG("dsi_complexio_init\n");
++
++ /* CIO_CLK_ICG, enable L3 clk to CIO */
++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
++
++ if (wait_for_bit_change(DSIPHY_CFG5, 30, 1) != 1) {
++ DSSERR("DSI: ComplexIO PHY not coming out of reset.\n");
++ r = -ENODEV;
++ goto err;
++ }
++
++ dsi_complexio_config(display);
++
++ r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
++
++ if (r)
++ goto err;
++
++ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
++ DSSERR("DSI: ComplexIO not coming out of reset.\n");
++ r = -ENODEV;
++ goto err;
++ }
++
++ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
++ DSSERR("DSI: ComplexIO LDO power down.\n");
++ r = -ENODEV;
++ goto err;
++ }
++
++ dsi_complexio_timings();
++
++ /*
++ The configuration of the DSI complex I/O (number of data lanes,
++ position, differential order) should not be changed while
++ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
++ hardware to recognize a new configuration of the complex I/O (done
++ in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
++ this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
++ reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
++ LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
++ bit to 1. If the sequence is not followed, the DSi complex I/O
++ configuration is undetermined.
++ */
++ dsi_if_enable(1);
++ dsi_if_enable(0);
++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
++ dsi_if_enable(1);
++ dsi_if_enable(0);
++
++ DSSDBG("CIO init done\n");
++err:
++ return r;
++}
++
++static void dsi_complexio_uninit(void)
++{
++ dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
++}
++
++
++
++static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
++ enum fifo_size size3, enum fifo_size size4)
++{
++ u32 r = 0;
++ int add = 0;
++ int i;
++
++ dsi.vc[0].fifo_size = size1;
++ dsi.vc[1].fifo_size = size2;
++ dsi.vc[2].fifo_size = size3;
++ dsi.vc[3].fifo_size = size4;
++
++ for (i = 0; i < 4; i++) {
++ u8 v;
++ int size = dsi.vc[i].fifo_size;
++
++ if (add + size > 4) {
++ DSSERR("DSI: Illegal FIFO configuration\n");
++ BUG();
++ }
++
++ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
++ r |= v << (8 * i);
++ /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
++ add += size;
++ }
++
++ dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
++}
++
++static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
++ enum fifo_size size3, enum fifo_size size4)
++{
++ u32 r = 0;
++ int add = 0;
++ int i;
++
++ dsi.vc[0].fifo_size = size1;
++ dsi.vc[1].fifo_size = size2;
++ dsi.vc[2].fifo_size = size3;
++ dsi.vc[3].fifo_size = size4;
++
++ for (i = 0; i < 4; i++) {
++ u8 v;
++ int size = dsi.vc[i].fifo_size;
++
++ if (add + size > 4) {
++ DSSERR("DSI: Illegal FIFO configuration\n");
++ BUG();
++ }
++
++ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
++ r |= v << (8 * i);
++ /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
++ add += size;
++ }
++
++ dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
++}
++
++static int dsi_force_tx_stop_mode_io(void)
++{
++ u32 r;
++
++ r = dsi_read_reg(DSI_TIMING1);
++ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
++ dsi_write_reg(DSI_TIMING1, r);
++
++ if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
++ DSSERR("TX_STOP bit not going down\n");
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static void dsi_vc_print_status(int channel)
++{
++ u32 r;
++
++ r = dsi_read_reg(DSI_VC_CTRL(channel));
++ DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
++ "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
++ channel,
++ FLD_GET(r, 5, 5),
++ FLD_GET(r, 6, 6),
++ FLD_GET(r, 15, 15),
++ FLD_GET(r, 16, 16),
++ FLD_GET(r, 20, 20));
++
++ r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
++ DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
++}
++
++static void dsi_vc_config(int channel)
++{
++ u32 r;
++
++ DSSDBG("dsi_vc_config %d\n", channel);
++
++ r = dsi_read_reg(DSI_VC_CTRL(channel));
++
++ r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
++ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
++ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
++ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
++ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
++ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
++ r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
++
++ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
++ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
++
++ dsi_write_reg(DSI_VC_CTRL(channel), r);
++}
++
++static void dsi_vc_config_vp(int channel)
++{
++ u32 r;
++
++ DSSDBG("dsi_vc_config_vp\n");
++
++ r = dsi_read_reg(DSI_VC_CTRL(channel));
++
++ r = FLD_MOD(r, 1, 1, 1); /* SOURCE, 1 = video port */
++ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
++ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
++ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
++ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
++ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
++ r = FLD_MOD(r, 1, 9, 9); /* MODE_SPEED, high speed on/off */
++
++ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
++ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
++
++ dsi_write_reg(DSI_VC_CTRL(channel), r);
++}
++
++
++static int dsi_vc_enable(int channel, int enable)
++{
++ DSSDBG("dsi_vc_enable channel %d, enable %d\n", channel, enable);
++
++ enable = enable ? 1 : 0;
++
++ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
++
++ if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
++ DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static void dsi_vc_enable_hs(int channel, int enable)
++{
++ DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
++
++ dsi_vc_enable(channel, 0);
++ dsi_if_enable(0);
++
++ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
++
++ dsi_vc_enable(channel, 1);
++ dsi_if_enable(1);
++
++ dsi_force_tx_stop_mode_io();
++}
++
++static void dsi_vc_flush_long_data(int channel)
++{
++ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
++ u32 val;
++ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++ DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
++ (val >> 0) & 0xff,
++ (val >> 8) & 0xff,
++ (val >> 16) & 0xff,
++ (val >> 24) & 0xff);
++ }
++}
++
++static u16 dsi_vc_flush_receive_data(int channel)
++{
++ /* RX_FIFO_NOT_EMPTY */
++ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
++ u32 val;
++ u8 dt;
++ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++ DSSDBG("\trawval %#08x\n", val);
++ dt = FLD_GET(val, 7, 0);
++ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
++ u16 err = FLD_GET(val, 23, 8);
++ DSSERR("\tACK with ERROR: %#x\n", err);
++ if (err & (1 << 9))
++ DSSERR("\t\tECC multibit\n");
++ if (err & (1 << 11))
++ DSSERR("\t\tData type not recognized\n");
++ if (err & (1 << 12))
++ DSSERR("\t\tInvalid VC ID\n");
++
++ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
++ DSSDBG("\tDCS short response, 1 byte: %#x\n",
++ FLD_GET(val, 23, 8));
++ return FLD_GET(val, 23, 8);
++ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
++ DSSDBG("\tDCS short response, 2 byte: %#x\n",
++ FLD_GET(val, 23, 8));
++ return FLD_GET(val, 23, 8);
++ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
++ DSSDBG("\tDCS long response, len %d\n",
++ FLD_GET(val, 23, 8));
++ dsi_vc_flush_long_data(channel);
++ } else {
++ DSSERR("\tunknown datatype\n");
++ }
++ }
++ return 0;
++}
++
++static int dsi_vc_send_bta(int channel)
++{
++ unsigned long tmo;
++
++ /*DSSDBG("dsi_vc_send_bta_sync %d\n", channel); */
++
++ if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
++ DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
++ dsi_vc_flush_receive_data(channel);
++ }
++
++ REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
++
++ tmo = jiffies + msecs_to_jiffies(10);
++ while (REG_GET(DSI_VC_CTRL(channel), 6, 6) == 1) {
++ if (time_after(jiffies, tmo)) {
++ DSSERR("Failed to send BTA\n");
++ return -EIO;
++ }
++ }
++
++ return 0;
++}
++
++static int dsi_vc_send_bta_sync(int channel)
++{
++ int r = 0;
++
++ init_completion(&dsi.bta_completion);
++
++ dsi_vc_enable_bta_irq(channel);
++
++ r = dsi_vc_send_bta(channel);
++ if (r)
++ goto err;
++
++ if (wait_for_completion_timeout(&dsi.bta_completion,
++ msecs_to_jiffies(500)) == 0) {
++ DSSERR("Failed to receive BTA\n");
++ r = -EIO;
++ goto err;
++ }
++err:
++ dsi_vc_disable_bta_irq(channel);
++
++ return r;
++}
++
++static inline void dsi_vc_write_long_header(int channel, u8 data_type,
++ u16 len, u8 ecc)
++{
++ u32 val;
++ u8 data_id;
++
++ /*data_id = data_type | channel << 6; */
++ data_id = data_type | dsi.vc[channel].dest_per << 6;
++
++ val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
++ FLD_VAL(ecc, 31, 24);
++
++ dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
++}
++
++static inline void dsi_vc_write_long_payload(int channel,
++ u8 b1, u8 b2, u8 b3, u8 b4)
++{
++ u32 val;
++
++ val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
++
++/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
++ b1, b2, b3, b4, val); */
++
++ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
++}
++
++static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
++ u8 ecc)
++{
++ /*u32 val; */
++ int i;
++ u8 *p;
++ int r = 0;
++ u8 b1, b2, b3, b4;
++
++ /*DSSDBG("dsi_vc_send_long, %d bytes\n", len); */
++
++ /* len + header */
++ if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
++ DSSERR("DSI: unable to send long packet: packet too long.\n");
++ return -EINVAL;
++ }
++
++ dsi_vc_write_long_header(channel, data_type, len, ecc);
++
++ /*dsi_vc_print_status(0); */
++
++ p = data;
++ for (i = 0; i < len >> 2; i++) {
++ /*DSSDBG("\tsending full packet %d\n", i); */
++ /*dsi_vc_print_status(0); */
++
++ b1 = *p++;
++ b2 = *p++;
++ b3 = *p++;
++ b4 = *p++;
++
++ dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
++ }
++
++ i = len % 4;
++ if (i) {
++ b1 = 0; b2 = 0; b3 = 0;
++
++ /*DSSDBG("\tsending remainder bytes %d\n", i); */
++
++ switch (i) {
++ case 3:
++ b1 = *p++;
++ b2 = *p++;
++ b3 = *p++;
++ break;
++ case 2:
++ b1 = *p++;
++ b2 = *p++;
++ break;
++ case 1:
++ b1 = *p++;
++ break;
++ }
++
++ dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
++ }
++
++ return r;
++}
++
++static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
++{
++ u32 r;
++ u8 data_id;
++/*
++ DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
++ channel,
++ data_type, data & 0xff, (data >> 8) & 0xff);
++*/
++ if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
++ DSSERR("ERROR FIFO FULL, aborting transfer\n");
++ return -EINVAL;
++ }
++
++ data_id = data_type | channel << 6;
++
++ r = (data_id << 0) | (data << 8) | (ecc << 24);
++
++ dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
++
++ return 0;
++}
++
++int dsi_vc_send_null(int channel)
++{
++ u8 nullpkg[] = {0, 0, 0, 0};
++ return dsi_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
++}
++EXPORT_SYMBOL(dsi_vc_send_null);
++
++int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
++{
++ int r;
++
++ BUG_ON(len == 0);
++
++ if (len == 1) {
++ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
++ data[0], 0);
++ } else if (len == 2) {
++ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
++ data[0] | (data[1] << 8), 0);
++ } else {
++ /* 0x39 = DCS Long Write */
++ r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
++ data, len, 0);
++ }
++
++ return r;
++}
++EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
++
++int dsi_vc_dcs_write(int channel, u8 *data, int len)
++{
++ int r;
++
++ r = dsi_vc_dcs_write_nosync(channel, data, len);
++ if (r)
++ return r;
++
++ /* Some devices need time to process the msg in low power mode.
++ This also makes the write synchronous, and checks that
++ the peripheral is still alive */
++ r = dsi_vc_send_bta_sync(channel);
++
++ return r;
++}
++EXPORT_SYMBOL(dsi_vc_dcs_write);
++
++int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
++{
++ u32 val;
++ u8 dt;
++ int debug = 0;
++
++ if (debug)
++ DSSDBG("dsi_vc_dcs_read\n");
++
++ dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
++
++ dsi_vc_send_bta_sync(channel);
++
++ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++ if (debug)
++ DSSDBG("\trawval %#08x\n", val);
++ dt = FLD_GET(val, 7, 0);
++ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
++ u16 err = FLD_GET(val, 23, 8);
++ DSSERR("\tACK with ERROR: %#x\n", err);
++ if (err & (1 << 9))
++ DSSERR("\t\tECC multibit\n");
++ if (err & (1 << 11))
++ DSSERR("\t\tData type not recognized\n");
++ if (err & (1 << 12))
++ DSSERR("\t\tInvalid VC ID\n");
++ return -1;
++
++ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
++ u8 data = FLD_GET(val, 15, 8);
++ if (debug)
++ DSSDBG("\tDCS short response, 1 byte: %#x\n", data);
++
++ if (buflen < 1)
++ return -1;
++
++ buf[0] = data;
++
++ return 1;
++ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
++ u16 data = FLD_GET(val, 23, 8);
++ if (debug)
++ DSSDBG("\tDCS short response, 2 byte: %#x\n", data);
++
++ if (buflen < 2)
++ return -1;
++
++ buf[0] = data & 0xff;
++ buf[1] = (data >> 8) & 0xff;
++
++ return 2;
++ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
++ int x;
++ int len = FLD_GET(val, 23, 8);
++ if (debug)
++ DSSDBG("\tDCS long response, len %d\n", len);
++
++ if (len > buflen)
++ return -1;
++
++ x = 0;
++ while (x < len) {
++ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++ if (debug)
++ DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 "
++ "%#02x\n",
++ (val >> 0) & 0xff,
++ (val >> 8) & 0xff,
++ (val >> 16) & 0xff,
++ (val >> 24) & 0xff);
++
++ if (x < len)
++ buf[x++] = (val >> 0) & 0xff;
++ if (x < len)
++ buf[x++] = (val >> 8) & 0xff;
++ if (x < len)
++ buf[x++] = (val >> 16) & 0xff;
++ if (x < len)
++ buf[x++] = (val >> 24) & 0xff;
++ }
++
++ return len;
++ } else {
++ DSSERR("\tunknown datatype\n");
++ return -1;
++ }
++}
++EXPORT_SYMBOL(dsi_vc_dcs_read);
++
++
++int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
++{
++ return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
++ len, 0);
++}
++EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
++
++
++static int dsi_set_lp_rx_timeout(int ns, int x4, int x16)
++{
++ u32 r;
++ unsigned long fck;
++ int ticks;
++
++ /* ticks in DSI_FCK */
++
++ fck = dsi_fclk_rate();
++ ticks = (fck / 1000 / 1000) * ns / 1000;
++
++ if (ticks > 0x1fff) {
++ DSSERR("LP_TX_TO too high\n");
++ return -EINVAL;
++ }
++
++ r = dsi_read_reg(DSI_TIMING2);
++ r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
++ r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
++ r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
++ r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
++ dsi_write_reg(DSI_TIMING2, r);
++
++ DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n",
++ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++ (fck / 1000 / 1000),
++ ticks);
++
++ return 0;
++}
++
++static int dsi_set_ta_timeout(int ns, int x8, int x16)
++{
++ u32 r;
++ unsigned long fck;
++ int ticks;
++
++ /* ticks in DSI_FCK */
++
++ fck = dsi_fclk_rate();
++ ticks = (fck / 1000 / 1000) * ns / 1000;
++
++ if (ticks > 0x1fff) {
++ DSSERR("TA_TO too high\n");
++ return -EINVAL;
++ }
++
++ r = dsi_read_reg(DSI_TIMING1);
++ r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
++ r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
++ r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
++ r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
++ dsi_write_reg(DSI_TIMING1, r);
++
++ DSSDBG("TA_TO %ld ns (%#x ticks)\n",
++ (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
++ (fck / 1000 / 1000),
++ ticks);
++
++ return 0;
++}
++
++static int dsi_set_stop_state_counter(int ns, int x4, int x16)
++{
++ u32 r;
++ unsigned long fck;
++ int ticks;
++
++ /* ticks in DSI_FCK */
++
++ fck = dsi_fclk_rate();
++ ticks = (fck / 1000 / 1000) * ns / 1000;
++
++ if (ticks > 0x1fff) {
++ DSSERR("STOP_STATE_COUNTER_IO too high\n");
++ return -EINVAL;
++ }
++
++ r = dsi_read_reg(DSI_TIMING1);
++ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
++ r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
++ r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
++ r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
++ dsi_write_reg(DSI_TIMING1, r);
++
++ DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n",
++ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++ (fck / 1000 / 1000),
++ ticks);
++
++ return 0;
++}
++
++static int dsi_set_hs_tx_timeout(int ns, int x4, int x16)
++{
++ u32 r;
++ unsigned long fck;
++ int ticks;
++
++ /* ticks in TxByteClkHS */
++
++ fck = dsi.ddr_clk / 4;
++ ticks = (fck / 1000 / 1000) * ns / 1000;
++
++ if (ticks > 0x1fff) {
++ DSSERR("HS_TX_TO too high\n");
++ return -EINVAL;
++ }
++
++ r = dsi_read_reg(DSI_TIMING2);
++ r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
++ r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
++ r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
++ r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
++ dsi_write_reg(DSI_TIMING2, r);
++
++ DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n",
++ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++ (fck / 1000 / 1000),
++ ticks);
++
++ return 0;
++}
++static int dsi_proto_config(struct omap_display *display)
++{
++ u32 r;
++ int buswidth = 0;
++
++ dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
++ DSI_FIFO_SIZE_0,
++ DSI_FIFO_SIZE_0,
++ DSI_FIFO_SIZE_0);
++
++ dsi_config_rx_fifo(DSI_FIFO_SIZE_128,
++ DSI_FIFO_SIZE_0,
++ DSI_FIFO_SIZE_0,
++ DSI_FIFO_SIZE_0);
++
++ /* XXX what values for the timeouts? */
++ dsi_set_stop_state_counter(1000, 0, 0);
++
++ dsi_set_ta_timeout(50000, 1, 1);
++
++ /* 3000ns * 16 */
++ dsi_set_lp_rx_timeout(3000, 0, 1);
++
++ /* 10000ns * 4 */
++ dsi_set_hs_tx_timeout(10000, 1, 0);
++
++ switch (display->bpp) {
++ case 16:
++ buswidth = 0;
++ break;
++ case 18:
++ buswidth = 1;
++ break;
++ case 24:
++ buswidth = 2;
++ break;
++ default:
++ BUG();
++ }
++
++ r = dsi_read_reg(DSI_CTRL);
++ r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
++ r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
++ r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
++ /* XXX what should the ratio be */
++ r = FLD_MOD(r, 0, 4, 4); /* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
++ r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
++ r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
++ r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
++ r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
++ r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
++ r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
++ r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
++
++ dsi_write_reg(DSI_CTRL, r);
++
++ /* we configure vc0 for L4 communication, and
++ * vc1 for dispc */
++ dsi_vc_config(0);
++ dsi_vc_config_vp(1);
++
++ /* set all vc targets to peripheral 0 */
++ dsi.vc[0].dest_per = 0;
++ dsi.vc[1].dest_per = 0;
++ dsi.vc[2].dest_per = 0;
++ dsi.vc[3].dest_per = 0;
++
++ return 0;
++}
++
++static void dsi_proto_timings(void)
++{
++ int tlpx_half, tclk_zero, tclk_prepare, tclk_trail;
++ int tclk_pre, tclk_post;
++ int ddr_clk_pre, ddr_clk_post;
++ u32 r;
++
++ r = dsi_read_reg(DSIPHY_CFG1);
++ tlpx_half = FLD_GET(r, 22, 16);
++ tclk_trail = FLD_GET(r, 15, 8);
++ tclk_zero = FLD_GET(r, 7, 0);
++
++ r = dsi_read_reg(DSIPHY_CFG2);
++ tclk_prepare = FLD_GET(r, 7, 0);
++
++ /* min 8*UI */
++ tclk_pre = 4;
++ /* min 60ns + 52*UI */
++ tclk_post = ns2ddr(60) + 26;
++
++ ddr_clk_pre = (tclk_pre + tlpx_half*2 + tclk_zero + tclk_prepare) / 4;
++ ddr_clk_post = (tclk_post + tclk_trail) / 4;
++
++ r = dsi_read_reg(DSI_CLK_TIMING);
++ r = FLD_MOD(r, ddr_clk_pre, 15, 8);
++ r = FLD_MOD(r, ddr_clk_post, 7, 0);
++ dsi_write_reg(DSI_CLK_TIMING, r);
++
++#ifdef VERBOSE
++ DSSDBG("ddr_clk_pre %d, ddr_clk_post %d\n",
++ ddr_clk_pre,
++ ddr_clk_post);
++#endif
++}
++
++
++#define DSI_DECL_VARS \
++ int __dsi_cb = 0; u32 __dsi_cv = 0;
++
++#define DSI_FLUSH(ch) \
++ if (__dsi_cb > 0) { \
++ /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
++ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
++ __dsi_cb = __dsi_cv = 0; \
++ }
++
++#define DSI_PUSH(ch, data) \
++ do { \
++ __dsi_cv |= (data) << (__dsi_cb * 8); \
++ /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
++ if (++__dsi_cb > 3) \
++ DSI_FLUSH(ch); \
++ } while (0)
++
++static int dsi_update_screen_l4(struct omap_display *display,
++ int x, int y, int w, int h)
++{
++ /* Note: supports only 24bit colors in 32bit container */
++ int first = 1;
++ int fifo_stalls = 0;
++ int max_dsi_packet_size;
++ int max_data_per_packet;
++ int max_pixels_per_packet;
++ int pixels_left;
++ int bytespp = 3;
++ int scr_width;
++ u32 *data;
++ int start_offset;
++ int horiz_inc;
++ int current_x;
++ struct omap_overlay *ovl;
++
++ debug_irq = 0;
++
++ DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
++ x, y, w, h);
++
++ ovl = &display->manager->overlays[0];
++
++ if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
++ return -EINVAL;
++
++ if (display->ctrl->bpp != 24)
++ return -EINVAL;
++
++ enable_clocks(1);
++
++ scr_width = ovl->info.screen_width;
++ data = ovl->info.vaddr;
++
++ start_offset = scr_width * y + x;
++ horiz_inc = scr_width - w;
++ current_x = x;
++
++ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
++ * in fifo */
++
++ /* When using CPU, max long packet size is TX buffer size */
++ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
++
++ /* we seem to get better perf if we divide the tx fifo to half,
++ and while the other half is being sent, we fill the other half
++ max_dsi_packet_size /= 2; */
++
++ max_data_per_packet = max_dsi_packet_size - 4 - 1;
++
++ max_pixels_per_packet = max_data_per_packet / bytespp;
++
++ DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
++
++ display->ctrl->setup_update(display, x, y, w, h);
++
++ pixels_left = w * h;
++
++ DSSDBG("total pixels %d\n", pixels_left);
++
++ data += start_offset;
++
++ dsi.update_region.x = x;
++ dsi.update_region.y = y;
++ dsi.update_region.w = w;
++ dsi.update_region.h = h;
++ dsi.update_region.bytespp = bytespp;
++
++ start_measuring();
++
++ while (pixels_left > 0) {
++ /* 0x2c = write_memory_start */
++ /* 0x3c = write_memory_continue */
++ u8 dcs_cmd = first ? 0x2c : 0x3c;
++ int pixels;
++ DSI_DECL_VARS;
++ first = 0;
++
++#if 1
++ /* using fifo not empty */
++ /* TX_FIFO_NOT_EMPTY */
++ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
++ udelay(1);
++ fifo_stalls++;
++ if (fifo_stalls > 0xfffff) {
++ DSSERR("fifo stalls overflow, pixels left %d\n",
++ pixels_left);
++ dsi_if_enable(0);
++ enable_clocks(0);
++ return -EIO;
++ }
++ }
++#elif 1
++ /* using fifo emptiness */
++ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
++ max_dsi_packet_size) {
++ fifo_stalls++;
++ if (fifo_stalls > 0xfffff) {
++ DSSERR("fifo stalls overflow, pixels left %d\n",
++ pixels_left);
++ dsi_if_enable(0);
++ enable_clocks(0);
++ return -EIO;
++ }
++ }
++#else
++ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
++ fifo_stalls++;
++ if (fifo_stalls > 0xfffff) {
++ DSSERR("fifo stalls overflow, pixels left %d\n",
++ pixels_left);
++ dsi_if_enable(0);
++ enable_clocks(0);
++ return -EIO;
++ }
++ }
++#endif
++ pixels = min(max_pixels_per_packet, pixels_left);
++
++ pixels_left -= pixels;
++
++ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
++ 1 + pixels * bytespp, 0);
++
++ DSI_PUSH(0, dcs_cmd);
++
++ while (pixels-- > 0) {
++ u32 pix = *data++;
++
++ DSI_PUSH(0, (pix >> 16) & 0xff);
++ DSI_PUSH(0, (pix >> 8) & 0xff);
++ DSI_PUSH(0, (pix >> 0) & 0xff);
++
++ current_x++;
++ if (current_x == x+w) {
++ current_x = x;
++ data += horiz_inc;
++ }
++ }
++
++ DSI_FLUSH(0);
++ }
++
++ end_measuring("L4");
++
++ enable_clocks(0);
++
++ return 0;
++}
++
++#if 0
++static void dsi_clear_screen_l4(struct omap_display *display,
++ int x, int y, int w, int h)
++{
++ int first = 1;
++ int fifo_stalls = 0;
++ int max_dsi_packet_size;
++ int max_data_per_packet;
++ int max_pixels_per_packet;
++ int pixels_left;
++ int bytespp = 3;
++ int pixnum;
++
++ debug_irq = 0;
++
++ DSSDBG("dsi_clear_screen_l4 (%d,%d %dx%d)\n",
++ x, y, w, h);
++
++ if (display->ctrl->bpp != 24)
++ return -EINVAL;
++
++ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp)
++ * bytes in fifo */
++
++ /* When using CPU, max long packet size is TX buffer size */
++ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
++
++ max_data_per_packet = max_dsi_packet_size - 4 - 1;
++
++ max_pixels_per_packet = max_data_per_packet / bytespp;
++
++ enable_clocks(1);
++
++ display->ctrl->setup_update(display, x, y, w, h);
++
++ pixels_left = w * h;
++
++ dsi.update_region.x = x;
++ dsi.update_region.y = y;
++ dsi.update_region.w = w;
++ dsi.update_region.h = h;
++ dsi.update_region.bytespp = bytespp;
++
++ start_measuring();
++
++ pixnum = 0;
++
++ while (pixels_left > 0) {
++ /* 0x2c = write_memory_start */
++ /* 0x3c = write_memory_continue */
++ u8 dcs_cmd = first ? 0x2c : 0x3c;
++ int pixels;
++ DSI_DECL_VARS;
++ first = 0;
++
++ /* TX_FIFO_NOT_EMPTY */
++ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
++ fifo_stalls++;
++ if (fifo_stalls > 0xfffff) {
++ DSSERR("fifo stalls overflow\n");
++ dsi_if_enable(0);
++ enable_clocks(0);
++ return;
++ }
++ }
++
++ pixels = min(max_pixels_per_packet, pixels_left);
++
++ pixels_left -= pixels;
++
++ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
++ 1 + pixels * bytespp, 0);
++
++ DSI_PUSH(0, dcs_cmd);
++
++ while (pixels-- > 0) {
++ u32 pix;
++
++ pix = 0x000000;
++
++ DSI_PUSH(0, (pix >> 16) & 0xff);
++ DSI_PUSH(0, (pix >> 8) & 0xff);
++ DSI_PUSH(0, (pix >> 0) & 0xff);
++ }
++
++ DSI_FLUSH(0);
++ }
++
++ enable_clocks(0);
++
++ end_measuring("L4 CLEAR");
++}
++#endif
++
++static int dsi_wait_for_framedone(void)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&dsi.update_lock, flags);
++ if (dsi.update_ongoing) {
++ long wait = msecs_to_jiffies(1000);
++ dsi.update_syncers++;
++ spin_unlock_irqrestore(&dsi.update_lock, flags);
++ wait = wait_for_completion_timeout(&dsi.update_completion,
++ wait);
++ if (wait == 0) {
++ DSSERR("timeout waiting sync\n");
++ return -ETIME;
++ }
++ } else {
++ spin_unlock_irqrestore(&dsi.update_lock, flags);
++ }
++
++ return 0;
++}
++
++static void dsi_setup_update_dispc(struct omap_display *display,
++ int x, int y, int w, int h)
++{
++ int bytespp = 3;
++
++ DSSDBG("dsi_setup_update_dispc(%d,%d %dx%d)\n",
++ x, y, w, h);
++
++ dsi.update_region.display = display;
++ dsi.update_region.x = x;
++ dsi.update_region.y = y;
++ dsi.update_region.w = w;
++ dsi.update_region.h = h;
++ dsi.update_region.bytespp = bytespp;
++
++ enable_clocks(1);
++
++ dispc_setup_partial_planes(display, &x, &y, &w, &h);
++
++ dispc_set_lcd_size(w, h);
++
++ enable_clocks(0);
++}
++
++static void dsi_update_screen_dispc(struct omap_display *display)
++{
++ int bytespp = 3;
++ int total_len;
++ int line_packet_len;
++ int x, y, w, h;
++ u32 l;
++
++ x = dsi.update_region.x;
++ y = dsi.update_region.y;
++ w = dsi.update_region.w;
++ h = dsi.update_region.h;
++
++ DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
++ x, y, w, h);
++
++ enable_clocks(1);
++
++ /* TODO: one packet could be longer, I think? Max is the line buffer */
++ line_packet_len = w * bytespp + 1; /* 1 byte for DCS cmd */
++ total_len = line_packet_len * h;
++
++ display->ctrl->setup_update(display, x, y, w, h);
++
++ if (0)
++ dsi_vc_print_status(1);
++
++ start_measuring();
++
++ l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
++ dsi_write_reg(DSI_VC_TE(1), l);
++
++ dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, line_packet_len, 0);
++
++ if (dsi.use_te)
++ l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
++ else
++ l = FLD_MOD(l, 1, 31, 31); /* TE_START */
++ dsi_write_reg(DSI_VC_TE(1), l);
++
++ dispc_enable_lcd_out(1);
++
++ if (dsi.use_te)
++ dsi_vc_send_bta(1);
++}
++
++static void framedone_callback(void *data, u32 mask)
++{
++ if (dsi.framedone_scheduled) {
++ DSSERR("Framedone already scheduled. Bogus FRAMEDONE IRQ?\n");
++ return;
++ }
++
++ dsi.framedone_scheduled = 1;
++
++ /* We get FRAMEDONE when DISPC has finished sending pixels and turns
++ * itself off. However, DSI still has the pixels in its buffers, and
++ * is sending the data. Thus we have to wait until we can do a new
++ * transfer or turn the clocks off. We do that in a separate work
++ * func. */
++ schedule_work(&dsi.framedone_work);
++}
++
++static void framedone_worker(struct work_struct *work)
++{
++ unsigned long flags;
++ u32 l;
++ unsigned long tmo;
++ int i = 0;
++
++ l = REG_GET(DSI_VC_TE(1), 23, 0); /* TE_SIZE */
++
++ /* There shouldn't be much stuff in DSI buffers, if any, so we'll
++ * just busyloop */
++ if (l > 0) {
++ tmo = jiffies + msecs_to_jiffies(50);
++ while (REG_GET(DSI_VC_TE(1), 23, 0) > 0) { /* TE_SIZE */
++ i++;
++ if (time_after(jiffies, tmo)) {
++ DSSERR("timeout waiting TE_SIZE to zero\n");
++ break;
++ }
++ cpu_relax();
++ }
++ }
++
++ if (REG_GET(DSI_VC_TE(1), 30, 30))
++ DSSERR("TE_EN not zero\n");
++
++ if (REG_GET(DSI_VC_TE(1), 31, 31))
++ DSSERR("TE_START not zero\n");
++
++ spin_lock_irqsave(&dsi.update_lock, flags);
++ if (dsi.update_ongoing == 0) {
++ spin_unlock_irqrestore(&dsi.update_lock, flags);
++ DSSERR("framedone irq without update request\n");
++ return;
++ }
++ spin_unlock_irqrestore(&dsi.update_lock, flags);
++
++ end_measuring("DISPC");
++
++ DSSDBG("FRAMEDONE\n");
++
++#if 0
++ if (l)
++ DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
++#else
++ if (l > 1024*3)
++ DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
++#endif
++
++ spin_lock_irqsave(&dsi.update_lock, flags);
++ dsi.update_ongoing = 0;
++ while (dsi.update_syncers > 0) {
++ complete(&dsi.update_completion);
++ --dsi.update_syncers;
++ }
++ spin_unlock_irqrestore(&dsi.update_lock, flags);
++
++#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
++ dispc_fake_vsync_irq();
++#endif
++ enable_clocks(0);
++
++ dsi.framedone_scheduled = 0;
++
++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
++ spin_lock_irqsave(&dsi.update_lock, flags);
++ dsi.update_ongoing = 1;
++ spin_unlock_irqrestore(&dsi.update_lock, flags);
++ dsi_update_screen_dispc(dsi.update_region.display);
++ }
++}
++
++static void dsi_start_auto_update(struct omap_display *display)
++{
++ unsigned long flags;
++ int bytespp = 3;
++
++ DSSDBG("starting auto update\n");
++
++ dsi.update_region.display = display;
++ dsi.update_region.x = 0;
++ dsi.update_region.y = 0;
++ dsi.update_region.w = display->x_res;
++ dsi.update_region.h = display->y_res;
++ dsi.update_region.bytespp = bytespp;
++
++ enable_clocks(1);
++
++ dispc_set_lcd_size(display->x_res, display->y_res);
++
++ spin_lock_irqsave(&dsi.update_lock, flags);
++ dsi.update_ongoing = 1;
++ spin_unlock_irqrestore(&dsi.update_lock, flags);
++ dsi_update_screen_dispc(display);
++}
++
++static void dsi_stop_auto_update(void)
++{
++ dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
++
++ DSSDBG("waiting for display to finish.\n");
++ dsi_wait_for_framedone();
++ DSSDBG("done waiting\n");
++ enable_clocks(0);
++
++ dsi.update_mode = OMAP_DSS_UPDATE_MANUAL;
++}
++
++static int dsi_set_update_mode(struct omap_display *display,
++ enum omap_dss_update_mode mode)
++{
++ if (mode == dsi.update_mode)
++ return 0;
++
++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++ dsi_stop_auto_update();
++ else if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
++ dsi_wait_for_framedone();
++
++ dsi.update_mode = mode;
++
++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++ dsi_start_auto_update(display);
++
++ return 0;
++}
++
++/* Display funcs */
++
++static int dsi_display_enable(struct omap_display *display)
++{
++ int r = 0;
++ struct dsi_clock_info cinfo;
++
++ DSSDBG("dsi_display_enable\n");
++
++ mutex_lock(&dsi.lock);
++
++ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
++ DSSERR("display already enabled\n");
++ r = -EINVAL;
++ goto err0;
++ }
++
++ enable_clocks(1);
++
++ r = omap_dispc_register_isr(framedone_callback, NULL,
++ DISPC_IRQ_FRAMEDONE);
++ if (r) {
++ DSSERR("can't get FRAMEDONE irq\n");
++ goto err1;
++ }
++
++ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
++
++ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
++ dispc_enable_fifohandcheck(1);
++ dispc_setup_plane_fifo(OMAP_DSS_GFX, 0);
++ dispc_setup_plane_fifo(OMAP_DSS_VIDEO1, 0);
++ dispc_setup_plane_fifo(OMAP_DSS_VIDEO2, 0);
++ dispc_set_tft_data_lines(display->bpp);
++
++ {
++ struct omap_video_timings timings = {
++ .hsw = 1,
++ .hfp = 1,
++ .hbp = 1,
++ .vsw = 1,
++ .vfp = 0,
++ .vbp = 0,
++ };
++
++ dispc_set_lcd_timings(&timings);
++ }
++
++ _dsi_print_reset_status();
++
++ r = dsi_pll_init(1, 0);
++ if (r)
++ goto err2;
++
++ /* XXX hardcoded for 300Mbp/lane for now */
++ r = dsi_pll_calc_datafreq(600 * 1000 * 1000, &cinfo);
++ if (r)
++ goto err3;
++
++ r = dsi_pll_program(&cinfo);
++ if (r)
++ goto err3;
++
++ DSSDBG("PLL OK\n");
++
++ r = dsi_complexio_init(display);
++ if (r)
++ goto err3;
++
++ _dsi_print_reset_status();
++
++ dsi_proto_timings();
++ dsi_set_lp_clk_divisor();
++
++ if (1)
++ _dsi_print_reset_status();
++
++ r = dsi_proto_config(display);
++ if (r)
++ goto err4;
++
++ /* enable interface */
++ dsi_vc_enable(0, 1);
++ dsi_vc_enable(1, 1);
++ dsi_if_enable(1);
++ dsi_force_tx_stop_mode_io();
++
++
++ if (display->ctrl && display->ctrl->enable) {
++ r = display->ctrl->enable(display);
++ if (r)
++ goto err5;
++ }
++
++ if (display->panel && display->panel->enable) {
++ r = display->panel->enable(display);
++ if (r)
++ goto err6;
++ }
++
++ if (dsi.use_te) {
++ r = display->ctrl->enable_te(display, 1);
++ if (r)
++ goto err7;
++ }
++
++ /* enable high-speed after initial config */
++ dsi_vc_enable_hs(0, 1);
++
++ display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++ dsi_start_auto_update(display);
++
++ enable_clocks(0);
++ mutex_unlock(&dsi.lock);
++
++ return 0;
++err7:
++ if (display->panel && display->panel->disable)
++ display->panel->disable(display);
++err6:
++ if (display->ctrl && display->ctrl->disable)
++ display->ctrl->disable(display);
++err5:
++ dsi_if_enable(0);
++err4:
++ dsi_complexio_uninit();
++err3:
++ dsi_pll_uninit();
++err2:
++ omap_dispc_unregister_isr(framedone_callback);
++err1:
++ enable_clocks(0);
++err0:
++ mutex_unlock(&dsi.lock);
++ DSSDBG("dsi_display_enable FAILED\n");
++ return r;
++}
++
++static void dsi_display_disable(struct omap_display *display)
++{
++ DSSDBG("dsi_display_disable\n");
++
++ mutex_lock(&dsi.lock);
++
++ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
++ goto end;
++
++ enable_clocks(1);
++
++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++ dsi_stop_auto_update();
++ else if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
++ dsi_wait_for_framedone();
++
++ display->state = OMAP_DSS_DISPLAY_DISABLED;
++
++ omap_dispc_unregister_isr(framedone_callback);
++
++ if (display->panel && display->panel->disable)
++ display->panel->disable(display);
++ if (display->ctrl && display->ctrl->disable)
++ display->ctrl->disable(display);
++
++ /* XXX sleep a bit to make sure all DSI buffers are sent.
++ * We should check it from somewhere, fifo fullness I guess */
++ msleep(200);
++
++ dsi_complexio_uninit();
++ dsi_pll_uninit();
++
++ enable_clocks(0);
++
++end:
++ mutex_unlock(&dsi.lock);
++}
++
++static int dsi_display_suspend(struct omap_display *display)
++{
++ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++ return -EINVAL;
++
++ if (display->panel->suspend)
++ display->panel->suspend(display);
++
++ if (display->ctrl->suspend)
++ display->ctrl->suspend(display);
++
++ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
++
++ return 0;
++}
++
++static int dsi_display_resume(struct omap_display *display)
++{
++ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
++ return -EINVAL;
++
++ if (display->panel->resume)
++ display->panel->resume(display);
++
++ if (display->ctrl->resume)
++ display->ctrl->resume(display);
++
++ display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++ return 0;
++}
++
++static void dsi_display_set_mode(struct omap_display *display,
++ int x_res, int y_res, int bpp)
++{
++ DSSDBG("dsi_display_set_mode %dx%d, %dbpp\n", x_res, y_res, bpp);
++}
++
++static int dsi_display_update(struct omap_display *display,
++ int x, int y, int w, int h)
++{
++ unsigned long flags;
++ int r = 0;
++
++ DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h);
++
++ if (w == 0 || h == 0)
++ return 0;
++
++ mutex_lock(&dsi.lock);
++
++ if (dsi.update_mode != OMAP_DSS_UPDATE_MANUAL)
++ goto end; /* XXX return error? */
++
++ spin_lock_irqsave(&dsi.update_lock, flags);
++
++ if (dsi.update_ongoing) {
++ spin_unlock_irqrestore(&dsi.update_lock, flags);
++ DSSERR("DSI is busy\n");
++ r = -EBUSY;
++ goto end;
++ }
++
++ dsi.update_ongoing = 1;
++
++ if (dsi.update_syncers > 0)
++ DSSERR("someone waiting for sync, and no update ongoing\n");
++
++ spin_unlock_irqrestore(&dsi.update_lock, flags);
++
++ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++ dsi_setup_update_dispc(display, x, y, w, h);
++ dsi_update_screen_dispc(display);
++ } else {
++ r = dsi_update_screen_l4(display, x, y, w, h);
++ if (r)
++ goto end;
++
++ spin_lock_irqsave(&dsi.update_lock, flags);
++ dsi.update_ongoing = 0;
++ while (dsi.update_syncers > 0) {
++ complete(&dsi.update_completion);
++ --dsi.update_syncers;
++ }
++ spin_unlock_irqrestore(&dsi.update_lock, flags);
++ }
++
++end:
++ mutex_unlock(&dsi.lock);
++ return r;
++}
++
++static int dsi_display_sync(struct omap_display *display)
++{
++ int r = 0;
++
++ DSSDBG("dsi_display_sync\n");
++
++ mutex_lock(&dsi.lock);
++
++ if (dsi.update_mode != OMAP_DSS_UPDATE_MANUAL)
++ goto end;
++
++ r = dsi_wait_for_framedone();
++
++end:
++ mutex_unlock(&dsi.lock);
++ return r;
++}
++
++static int dsi_display_set_update_mode(struct omap_display *display,
++ enum omap_dss_update_mode mode)
++{
++ int r;
++
++ DSSDBG("dsi_display_set_update_mode\n");
++
++ mutex_lock(&dsi.lock);
++
++ r = dsi_set_update_mode(display, mode);
++
++ mutex_unlock(&dsi.lock);
++
++ return r;
++}
++
++static enum omap_dss_update_mode dsi_display_get_update_mode(
++ struct omap_display *display)
++{
++ return dsi.update_mode;
++}
++
++static int dsi_display_enable_te(struct omap_display *display, int enable)
++{
++ enum omap_dss_update_mode mode;
++
++ DSSDBG("dsi_display_enable_te\n");
++
++ mutex_lock(&dsi.lock);
++
++ enable_clocks(1);
++
++ mode = dsi.update_mode;
++
++ /* XXX perhaps suspend or something would be better here */
++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++ dsi_stop_auto_update();
++ else if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
++ dsi_wait_for_framedone();
++
++ dsi.use_te = enable;
++ display->ctrl->enable_te(display, enable);
++ if (enable) {
++ /* disable LP_RX_TO, so that we can receive TE.
++ * Time to wait for TE is longer than the timer allows */
++ REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
++ } else {
++ REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
++ }
++
++ /* restore the old update mode */
++ dsi_set_update_mode(display, mode);
++
++ enable_clocks(0);
++
++ mutex_unlock(&dsi.lock);
++
++ return 0;
++}
++
++static int dsi_display_get_te(struct omap_display *display)
++{
++ return dsi.use_te;
++}
++
++static int dsi_display_run_test(struct omap_display *display, int test_num)
++{
++ enum omap_dss_update_mode mode;
++ int r = 0;
++
++ DSSDBG("dsi_display_run_test %d\n", test_num);
++
++ mutex_lock(&dsi.lock);
++
++ enable_clocks(1);
++
++ mode = dsi.update_mode;
++
++ /* XXX perhaps suspend or something would be better here */
++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++ dsi_stop_auto_update();
++ else if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
++ dsi_wait_for_framedone();
++
++ /* run test first in low speed mode */
++ dsi_vc_enable_hs(0, 0);
++
++ if (display->ctrl->run_test) {
++ r = display->ctrl->run_test(display, test_num);
++ if (r)
++ goto fail;
++ }
++
++ if (display->panel->run_test) {
++ r = display->panel->run_test(display, test_num);
++ if (r)
++ goto fail;
++ }
++
++ /* then in high speed */
++ dsi_vc_enable_hs(0, 1);
++
++ if (display->ctrl->run_test) {
++ r = display->ctrl->run_test(display, test_num);
++ if (r)
++ goto fail;
++ }
++
++ if (display->panel->run_test)
++ r = display->panel->run_test(display, test_num);
++
++fail:
++ dsi_vc_enable_hs(0, 1);
++
++ /* restore the old update mode */
++ dsi_set_update_mode(display, mode);
++
++ enable_clocks(0);
++
++ mutex_unlock(&dsi.lock);
++
++ return r;
++}
++
++void dsi_init_display(struct omap_display *display)
++{
++ DSSDBG("DSI init\n");
++
++ display->enable = dsi_display_enable;
++ display->disable = dsi_display_disable;
++ display->suspend = dsi_display_suspend;
++ display->resume = dsi_display_resume;
++ display->set_mode = dsi_display_set_mode;
++ display->update = dsi_display_update;
++ display->sync = dsi_display_sync;
++ display->set_update_mode = dsi_display_set_update_mode;
++ display->get_update_mode = dsi_display_get_update_mode;
++ display->enable_te = dsi_display_enable_te;
++ display->get_te = dsi_display_get_te;
++ display->run_test = dsi_display_run_test;
++
++ display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
++}
++
++int dsi_init(void)
++{
++ u32 rev;
++
++ init_completion(&dsi.bta_completion);
++ INIT_WORK(&dsi.framedone_work, framedone_worker);
++
++ init_completion(&dsi.update_completion);
++ spin_lock_init(&dsi.update_lock);
++ dsi.update_ongoing = 0;
++ dsi.update_syncers = 0;
++
++ mutex_init(&dsi.lock);
++
++ dsi.base = ioremap(DSI_BASE, SZ_1K);
++ if (!dsi.base) {
++ DSSERR("can't ioremap DSI\n");
++ return -ENOMEM;
++ }
++
++ dsi.dss_ick = get_dss_ick();
++ dsi.dss1_fck = get_dss1_fck();
++ dsi.dss2_fck = get_dss2_fck();
++
++ enable_clocks(1);
++
++ /* Autoidle */
++ REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
++
++ /* ENWAKEUP */
++ REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
++
++ /* SIDLEMODE smart-idle */
++ REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
++
++ if (0)
++ _dsi_reset();
++
++ _dsi_initialize_irq();
++
++ rev = dsi_read_reg(DSI_REVISION);
++ printk(KERN_INFO "OMAP DSI rev %d.%d\n",
++ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++ enable_clocks(0);
++
++ return 0;
++}
++
++void dsi_exit(void)
++{
++ iounmap(dsi.base);
++
++ DSSDBG("omap_dsi_exit\n");
++}
++
diff --git a/arch/arm/plat-omap/dss/dss.c b/arch/arm/plat-omap/dss/dss.c
new file mode 100644
index 0000000..da0364b
@@ -3460,10 +6559,10 @@ index 0000000..da0364b
+
diff --git a/arch/arm/plat-omap/dss/dss.h b/arch/arm/plat-omap/dss/dss.h
new file mode 100644
-index 0000000..4df7f67
+index 0000000..28929b9
--- /dev/null
+++ b/arch/arm/plat-omap/dss/dss.h
-@@ -0,0 +1,240 @@
+@@ -0,0 +1,254 @@
+/*
+ * linux/arch/arm/plat-omap/dss/dss.h
+ *
@@ -3555,6 +6654,41 @@ index 0000000..4df7f67
+ OMAP_DSS_PARALLELMODE_DSI,
+};
+
++struct dispc_clock_info {
++ /* rates that we get with dividers below */
++ unsigned long fck;
++ unsigned long lck;
++ unsigned long pck;
++
++ /* dividers */
++ int fck_div;
++ int lck_div;
++ int pck_div;
++};
++
++struct dsi_clock_info {
++ /* rates that we get with dividers below */
++ unsigned long fint;
++ unsigned long dsiphy;
++ unsigned long clkin; /* input clk for DSI PLL */
++ unsigned long dispc_fck; /* output clk, DSI1_PLL_FCLK */
++ unsigned long dsi_fck; /* output clk, DSI2_PLL_FCLK */
++ unsigned long lck;
++ unsigned long pck;
++
++ /* dividers */
++ int regn;
++ int regm;
++ int regm3;
++ int regm4;
++
++ int lck_div;
++ int pck_div;
++
++ int highfreq;
++ int use_dss2_fck;
++};
++
+int initialize_sysfs(struct device *dev);
+void uninitialize_sysfs(struct device *dev);
+void initialize_displays(struct omap_dss_platform_data *pdata);
@@ -3584,35 +6718,13 @@ index 0000000..4df7f67
+
+
+/* DSI */
-+struct dsi_clock_info {
-+ /* rates that we get with dividers below */
-+ unsigned long fint;
-+ unsigned long dsiphy;
-+ unsigned long clkin; /* input clk for DSI PLL */
-+ unsigned long dispc_fck; /* output clk, DSI1_PLL_FCLK */
-+ unsigned long dsi_fck; /* output clk, DSI2_PLL_FCLK */
-+ unsigned long pck; /* dispc pixel clock */
-+
-+ /* dividers */
-+ int regn;
-+ int regm;
-+ int regm3;
-+ int regm4;
-+
-+ int lck_div;
-+ int pck_div;
-+
-+ int highfreq;
-+ int use_dss2_fck;
-+};
-+
+int dsi_init(void);
+void dsi_exit(void);
+void dsi_init_display(struct omap_display *display);
+void dsi_irq_handler(void);
+unsigned long dsi_get_dsi1_pll_rate(void);
+unsigned long dsi_get_dsi2_pll_rate(void);
-+int dsi_pll_calc_pck(int is_tft, unsigned long pck,
++int dsi_pll_calc_pck(int is_tft, unsigned long req_pck,
+ struct dsi_clock_info *cinfo);
+int dsi_pll_program(struct dsi_clock_info *cinfo);
+int dsi_pll_init(int enable_hsclk, int enable_hsdiv);
@@ -3673,11 +6785,12 @@ index 0000000..4df7f67
+unsigned long dispc_fclk_rate(void);
+unsigned long dispc_pclk_rate(void);
+void dispc_set_pol_freq(struct omap_panel *panel);
-+unsigned long dispc_calc_clock_div(int is_tft, int pck, int *fck_div,
++void find_lck_pck_divs(int is_tft, unsigned long req_pck, unsigned long fck,
+ int *lck_div, int *pck_div);
-+void dispc_set_clock_div(int fck_div, int lck_div, int pck_div);
++int dispc_calc_clock_div(int is_tft, unsigned long req_pck,
++ struct dispc_clock_info *cinfo);
++int dispc_set_clock_div(struct dispc_clock_info *cinfo);
+void dispc_set_lcd_divisor(int lck_div, int pck_div);
-+int dispc_pixel_clock_valid(int pixel_clock);
+
+void dispc_setup_partial_planes(struct omap_display *display,
+ int *x, int *y, int *w, int *h);
@@ -3704,12 +6817,1252 @@ index 0000000..4df7f67
+void rfbi_init_display(struct omap_display *display);
+
+#endif
+diff --git a/arch/arm/plat-omap/dss/rfbi.c b/arch/arm/plat-omap/dss/rfbi.c
+new file mode 100644
+index 0000000..31ddd24
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/rfbi.c
+@@ -0,0 +1,1234 @@
++/*
++ * linux/arch/arm/plat-omap/dss/rfbi.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "RFBI"
++
++#include <linux/kernel.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/delay.h>
++#include <linux/kfifo.h>
++#include <linux/ktime.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include "dss.h"
++
++/*#define MEASURE_PERF*/
++
++#define RFBI_BASE 0x48050800
++
++struct rfbi_reg { u16 idx; };
++
++#define RFBI_REG(idx) ((const struct rfbi_reg) { idx })
++
++#define RFBI_REVISION RFBI_REG(0x0000)
++#define RFBI_SYSCONFIG RFBI_REG(0x0010)
++#define RFBI_SYSSTATUS RFBI_REG(0x0014)
++#define RFBI_CONTROL RFBI_REG(0x0040)
++#define RFBI_PIXEL_CNT RFBI_REG(0x0044)
++#define RFBI_LINE_NUMBER RFBI_REG(0x0048)
++#define RFBI_CMD RFBI_REG(0x004c)
++#define RFBI_PARAM RFBI_REG(0x0050)
++#define RFBI_DATA RFBI_REG(0x0054)
++#define RFBI_READ RFBI_REG(0x0058)
++#define RFBI_STATUS RFBI_REG(0x005c)
++
++#define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18)
++#define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18)
++#define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18)
++#define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18)
++#define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18)
++#define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18)
++
++#define RFBI_VSYNC_WIDTH RFBI_REG(0x0090)
++#define RFBI_HSYNC_WIDTH RFBI_REG(0x0094)
++
++#define RFBI_CMD_FIFO_LEN_BYTES (16 * sizeof(struct update_param))
++
++#define REG_FLD_MOD(idx, val, start, end) \
++ rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
++
++/* To work around an RFBI transfer rate limitation */
++#define OMAP_RFBI_RATE_LIMIT 1
++
++enum omap_rfbi_cycleformat {
++ OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
++ OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
++ OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
++ OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
++};
++
++enum omap_rfbi_datatype {
++ OMAP_DSS_RFBI_DATATYPE_12 = 0,
++ OMAP_DSS_RFBI_DATATYPE_16 = 1,
++ OMAP_DSS_RFBI_DATATYPE_18 = 2,
++ OMAP_DSS_RFBI_DATATYPE_24 = 3,
++};
++
++enum omap_rfbi_parallelmode {
++ OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
++ OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
++ OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
++ OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
++};
++
++enum update_cmd {
++ RFBI_CMD_UPDATE = 0,
++ RFBI_CMD_SYNC = 1,
++};
++
++static int rfbi_convert_timings(struct rfbi_timings *t);
++static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
++static void process_cmd_fifo(void);
++
++static struct {
++ void __iomem *base;
++
++ struct clk *dss_ick;
++ struct clk *dss1_fck;
++
++ unsigned long l4_khz;
++
++ enum omap_rfbi_datatype datatype;
++ enum omap_rfbi_parallelmode parallelmode;
++
++ enum omap_rfbi_te_mode te_mode;
++ int te_enabled;
++
++ void (*framedone_callback)(void *data);
++ void *framedone_callback_data;
++
++ struct omap_display *display[2];
++
++ struct kfifo *cmd_fifo;
++ spinlock_t cmd_lock;
++ struct completion cmd_done;
++ atomic_t cmd_fifo_full;
++ atomic_t cmd_pending;
++#ifdef MEASURE_PERF
++ ktime_t perf_time;
++#endif
++} rfbi;
++
++struct update_region {
++ u16 x;
++ u16 y;
++ u16 w;
++ u16 h;
++};
++
++struct update_param {
++ u8 rfbi_module;
++ u8 cmd;
++
++ union {
++ struct update_region r;
++ struct completion *sync;
++ } par;
++};
++
++static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
++{
++ __raw_writel(val, rfbi.base + idx.idx);
++}
++
++static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
++{
++ return __raw_readl(rfbi.base + idx.idx);
++}
++
++static void rfbi_enable_clocks(int enable)
++{
++ if (enable) {
++ clk_enable(rfbi.dss_ick);
++ clk_enable(rfbi.dss1_fck);
++ } else {
++ clk_disable(rfbi.dss1_fck);
++ clk_disable(rfbi.dss_ick);
++ }
++}
++
++void omap_rfbi_write_command(const void *buf, u32 len)
++{
++ rfbi_enable_clocks(1);
++ switch (rfbi.parallelmode) {
++ case OMAP_DSS_RFBI_PARALLELMODE_8:
++ {
++ const u8 *b = buf;
++ for (; len; len--)
++ rfbi_write_reg(RFBI_CMD, *b++);
++ break;
++ }
++
++ case OMAP_DSS_RFBI_PARALLELMODE_16:
++ {
++ const u16 *w = buf;
++ BUG_ON(len & 1);
++ for (; len; len -= 2)
++ rfbi_write_reg(RFBI_CMD, *w++);
++ break;
++ }
++
++ case OMAP_DSS_RFBI_PARALLELMODE_9:
++ case OMAP_DSS_RFBI_PARALLELMODE_12:
++ default:
++ BUG();
++ }
++ rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_command);
++
++void omap_rfbi_read_data(void *buf, u32 len)
++{
++ rfbi_enable_clocks(1);
++ switch (rfbi.parallelmode) {
++ case OMAP_DSS_RFBI_PARALLELMODE_8:
++ {
++ u8 *b = buf;
++ for (; len; len--) {
++ rfbi_write_reg(RFBI_READ, 0);
++ *b++ = rfbi_read_reg(RFBI_READ);
++ }
++ break;
++ }
++
++ case OMAP_DSS_RFBI_PARALLELMODE_16:
++ {
++ u16 *w = buf;
++ BUG_ON(len & ~1);
++ for (; len; len -= 2) {
++ rfbi_write_reg(RFBI_READ, 0);
++ *w++ = rfbi_read_reg(RFBI_READ);
++ }
++ break;
++ }
++
++ case OMAP_DSS_RFBI_PARALLELMODE_9:
++ case OMAP_DSS_RFBI_PARALLELMODE_12:
++ default:
++ BUG();
++ }
++ rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_read_data);
++
++void omap_rfbi_write_data(const void *buf, u32 len)
++{
++ rfbi_enable_clocks(1);
++ switch (rfbi.parallelmode) {
++ case OMAP_DSS_RFBI_PARALLELMODE_8:
++ {
++ const u8 *b = buf;
++ for (; len; len--)
++ rfbi_write_reg(RFBI_PARAM, *b++);
++ break;
++ }
++
++ case OMAP_DSS_RFBI_PARALLELMODE_16:
++ {
++ const u16 *w = buf;
++ BUG_ON(len & 1);
++ for (; len; len -= 2)
++ rfbi_write_reg(RFBI_PARAM, *w++);
++ break;
++ }
++
++ case OMAP_DSS_RFBI_PARALLELMODE_9:
++ case OMAP_DSS_RFBI_PARALLELMODE_12:
++ default:
++ BUG();
++
++ }
++ rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_data);
++
++void omap_rfbi_write_pixels(const void *buf, int scr_width, int x, int y,
++ int w, int h)
++{
++ int start_offset = scr_width * y + x;
++ int horiz_offset = scr_width - w;
++ int i;
++
++ rfbi_enable_clocks(1);
++
++ if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
++ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
++ const u16 *pd = buf;
++ pd += start_offset;
++
++ for (; h; --h) {
++ for (i = 0; i < w; ++i) {
++ const u8 *b = (const u8 *)pd;
++ rfbi_write_reg(RFBI_PARAM, *(b+1));
++ rfbi_write_reg(RFBI_PARAM, *(b+0));
++ ++pd;
++ }
++ pd += horiz_offset;
++ }
++ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
++ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
++ const u32 *pd = buf;
++ pd += start_offset;
++
++ for (; h; --h) {
++ for (i = 0; i < w; ++i) {
++ const u8 *b = (const u8 *)pd;
++ rfbi_write_reg(RFBI_PARAM, *(b+2));
++ rfbi_write_reg(RFBI_PARAM, *(b+1));
++ rfbi_write_reg(RFBI_PARAM, *(b+0));
++ ++pd;
++ }
++ pd += horiz_offset;
++ }
++ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
++ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
++ const u16 *pd = buf;
++ pd += start_offset;
++
++ for (; h; --h) {
++ for (i = 0; i < w; ++i) {
++ rfbi_write_reg(RFBI_PARAM, *pd);
++ ++pd;
++ }
++ pd += horiz_offset;
++ }
++ } else {
++ BUG();
++ }
++
++ rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_pixels);
++
++void rfbi_transfer_area(int width, int height,
++ void (callback)(void *data), void *data)
++{
++ u32 l;
++
++ /*BUG_ON(callback == 0);*/
++ BUG_ON(rfbi.framedone_callback != NULL);
++
++ DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
++
++ dispc_set_lcd_size(width, height);
++
++ dispc_enable_lcd_out(1);
++
++ rfbi.framedone_callback = callback;
++ rfbi.framedone_callback_data = data;
++
++ rfbi_enable_clocks(1);
++
++#ifdef MEASURE_PERF
++ rfbi.perf_time = ktime_get();
++#endif
++ rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
++
++ l = rfbi_read_reg(RFBI_CONTROL);
++ l = FLD_MOD(l, 1, 0, 0); /* enable */
++ if (!rfbi.te_enabled)
++ l = FLD_MOD(l, 1, 4, 4); /* ITE */
++
++ rfbi_write_reg(RFBI_CONTROL, l);
++}
++
++static void framedone_callback(void *data, u32 mask)
++{
++ void (*callback)(void *data);
++
++#ifdef MEASURE_PERF
++ {
++ ktime_t t = ktime_get();
++ t = ktime_sub(t, rfbi.perf_time);
++ DSSDBG("FRAMEDONE in %lld ns\n", ktime_to_ns(t));
++ }
++#else
++ DSSDBG("FRAMEDONE\n");
++#endif
++
++ REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
++
++ rfbi_enable_clocks(0);
++
++ callback = rfbi.framedone_callback;
++ rfbi.framedone_callback = NULL;
++
++ /*callback(rfbi.framedone_callback_data);*/
++
++ atomic_set(&rfbi.cmd_pending, 0);
++
++ process_cmd_fifo();
++}
++
++#if 1 /* VERBOSE */
++static void rfbi_print_timings(void)
++{
++ u32 l;
++ u32 time;
++
++ l = rfbi_read_reg(RFBI_CONFIG(0));
++ time = 1000000000 / rfbi.l4_khz;
++ if (l & (1 << 4))
++ time *= 2;
++
++ DSSDBG("Tick time %u ps\n", time);
++ l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
++ DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
++ "REONTIME %d, REOFFTIME %d\n",
++ l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
++ (l >> 20) & 0x0f, (l >> 24) & 0x3f);
++
++ l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
++ DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
++ "ACCESSTIME %d\n",
++ (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
++ (l >> 22) & 0x3f);
++}
++#else
++static void rfbi_print_timings(void) {}
++#endif
++
++
++
++
++static u32 extif_clk_period;
++
++static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
++{
++ int bus_tick = extif_clk_period * div;
++ return (ps + bus_tick - 1) / bus_tick * bus_tick;
++}
++
++static int calc_reg_timing(struct rfbi_timings *t, int div)
++{
++ t->clk_div = div;
++
++ t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
++
++ t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
++ t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
++ t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
++
++ t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
++ t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
++ t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
++
++ t->access_time = round_to_extif_ticks(t->access_time, div);
++ t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
++ t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
++
++ DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
++ t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
++ DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
++ t->we_on_time, t->we_off_time, t->re_cycle_time,
++ t->we_cycle_time);
++ DSSDBG("[reg]rdaccess %d cspulse %d\n",
++ t->access_time, t->cs_pulse_width);
++
++ return rfbi_convert_timings(t);
++}
++
++static int calc_extif_timings(struct rfbi_timings *t)
++{
++ u32 max_clk_div;
++ int div;
++
++ rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
++ for (div = 1; div <= max_clk_div; div++) {
++ if (calc_reg_timing(t, div) == 0)
++ break;
++ }
++
++ if (div <= max_clk_div)
++ return 0;
++
++ DSSERR("can't setup timings\n");
++ return -1;
++}
++
++
++void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
++{
++ int r;
++
++ if (!t->converted) {
++ r = calc_extif_timings(t);
++ if (r < 0)
++ DSSERR("Failed to calc timings\n");
++ }
++
++ BUG_ON(!t->converted);
++
++ rfbi_enable_clocks(1);
++ rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
++ rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
++
++ /* TIMEGRANULARITY */
++ REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
++ (t->tim[2] ? 1 : 0), 4, 4);
++
++ rfbi_print_timings();
++ rfbi_enable_clocks(0);
++}
++
++static int ps_to_rfbi_ticks(int time, int div)
++{
++ unsigned long tick_ps;
++ int ret;
++
++ /* Calculate in picosecs to yield more exact results */
++ tick_ps = 1000000000 / (rfbi.l4_khz) * div;
++
++ ret = (time + tick_ps - 1) / tick_ps;
++
++ return ret;
++}
++
++#ifdef OMAP_RFBI_RATE_LIMIT
++unsigned long rfbi_get_max_tx_rate(void)
++{
++ unsigned long l4_rate, dss1_rate;
++ int min_l4_ticks = 0;
++ int i;
++
++ /* According to TI this can't be calculated so make the
++ * adjustments for a couple of known frequencies and warn for
++ * others.
++ */
++ static const struct {
++ unsigned long l4_clk; /* HZ */
++ unsigned long dss1_clk; /* HZ */
++ unsigned long min_l4_ticks;
++ } ftab[] = {
++ { 55, 132, 7, }, /* 7.86 MPix/s */
++ { 110, 110, 12, }, /* 9.16 MPix/s */
++ { 110, 132, 10, }, /* 11 Mpix/s */
++ { 120, 120, 10, }, /* 12 Mpix/s */
++ { 133, 133, 10, }, /* 13.3 Mpix/s */
++ };
++
++ l4_rate = rfbi.l4_khz / 1000;
++ dss1_rate = clk_get_rate(rfbi.dss1_fck) / 1000000;
++
++ for (i = 0; i < ARRAY_SIZE(ftab); i++) {
++ /* Use a window instead of an exact match, to account
++ * for different DPLL multiplier / divider pairs.
++ */
++ if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
++ abs(ftab[i].dss1_clk - dss1_rate) < 3) {
++ min_l4_ticks = ftab[i].min_l4_ticks;
++ break;
++ }
++ }
++ if (i == ARRAY_SIZE(ftab)) {
++ /* Can't be sure, return anyway the maximum not
++ * rate-limited. This might cause a problem only for the
++ * tearing synchronisation.
++ */
++ DSSERR("can't determine maximum RFBI transfer rate\n");
++ return rfbi.l4_khz * 1000;
++ }
++ return rfbi.l4_khz * 1000 / min_l4_ticks;
++}
++#else
++int rfbi_get_max_tx_rate(void)
++{
++ return rfbi.l4_khz * 1000;
++}
++#endif
++
++static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
++{
++ *clk_period = 1000000000 / rfbi.l4_khz;
++ *max_clk_div = 2;
++}
++
++static int rfbi_convert_timings(struct rfbi_timings *t)
++{
++ u32 l;
++ int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
++ int actim, recyc, wecyc;
++ int div = t->clk_div;
++
++ if (div <= 0 || div > 2)
++ return -1;
++
++ /* Make sure that after conversion it still holds that:
++ * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
++ * csoff > cson, csoff >= max(weoff, reoff), actim > reon
++ */
++ weon = ps_to_rfbi_ticks(t->we_on_time, div);
++ weoff = ps_to_rfbi_ticks(t->we_off_time, div);
++ if (weoff <= weon)
++ weoff = weon + 1;
++ if (weon > 0x0f)
++ return -1;
++ if (weoff > 0x3f)
++ return -1;
++
++ reon = ps_to_rfbi_ticks(t->re_on_time, div);
++ reoff = ps_to_rfbi_ticks(t->re_off_time, div);
++ if (reoff <= reon)
++ reoff = reon + 1;
++ if (reon > 0x0f)
++ return -1;
++ if (reoff > 0x3f)
++ return -1;
++
++ cson = ps_to_rfbi_ticks(t->cs_on_time, div);
++ csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
++ if (csoff <= cson)
++ csoff = cson + 1;
++ if (csoff < max(weoff, reoff))
++ csoff = max(weoff, reoff);
++ if (cson > 0x0f)
++ return -1;
++ if (csoff > 0x3f)
++ return -1;
++
++ l = cson;
++ l |= csoff << 4;
++ l |= weon << 10;
++ l |= weoff << 14;
++ l |= reon << 20;
++ l |= reoff << 24;
++
++ t->tim[0] = l;
++
++ actim = ps_to_rfbi_ticks(t->access_time, div);
++ if (actim <= reon)
++ actim = reon + 1;
++ if (actim > 0x3f)
++ return -1;
++
++ wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
++ if (wecyc < weoff)
++ wecyc = weoff;
++ if (wecyc > 0x3f)
++ return -1;
++
++ recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
++ if (recyc < reoff)
++ recyc = reoff;
++ if (recyc > 0x3f)
++ return -1;
++
++ cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
++ if (cs_pulse > 0x3f)
++ return -1;
++
++ l = wecyc;
++ l |= recyc << 6;
++ l |= cs_pulse << 12;
++ l |= actim << 22;
++
++ t->tim[1] = l;
++
++ t->tim[2] = div - 1;
++
++ t->converted = 1;
++
++ return 0;
++}
++
++/* xxx FIX module selection missing */
++int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
++ unsigned hs_pulse_time, unsigned vs_pulse_time,
++ int hs_pol_inv, int vs_pol_inv, int extif_div)
++{
++ int hs, vs;
++ int min;
++ u32 l;
++
++ hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
++ vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
++ if (hs < 2)
++ return -EDOM;
++ if (mode == OMAP_DSS_RFBI_TE_MODE_2)
++ min = 2;
++ else /* OMAP_DSS_RFBI_TE_MODE_1 */
++ min = 4;
++ if (vs < min)
++ return -EDOM;
++ if (vs == hs)
++ return -EINVAL;
++ rfbi.te_mode = mode;
++ DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
++ mode, hs, vs, hs_pol_inv, vs_pol_inv);
++
++ rfbi_enable_clocks(1);
++ rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
++ rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
++
++ l = rfbi_read_reg(RFBI_CONFIG(0));
++ if (hs_pol_inv)
++ l &= ~(1 << 21);
++ else
++ l |= 1 << 21;
++ if (vs_pol_inv)
++ l &= ~(1 << 20);
++ else
++ l |= 1 << 20;
++ rfbi_enable_clocks(0);
++
++ return 0;
++}
++EXPORT_SYMBOL(omap_rfbi_setup_te);
++
++/* xxx FIX module selection missing */
++int omap_rfbi_enable_te(int enable, unsigned line)
++{
++ u32 l;
++
++ DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
++ if (line > (1 << 11) - 1)
++ return -EINVAL;
++
++ rfbi_enable_clocks(1);
++ l = rfbi_read_reg(RFBI_CONFIG(0));
++ l &= ~(0x3 << 2);
++ if (enable) {
++ rfbi.te_enabled = 1;
++ l |= rfbi.te_mode << 2;
++ } else
++ rfbi.te_enabled = 0;
++ rfbi_write_reg(RFBI_CONFIG(0), l);
++ rfbi_write_reg(RFBI_LINE_NUMBER, line);
++ rfbi_enable_clocks(0);
++
++ return 0;
++}
++EXPORT_SYMBOL(omap_rfbi_enable_te);
++
++#if 0
++static void rfbi_enable_config(int enable1, int enable2)
++{
++ u32 l;
++ int cs = 0;
++
++ if (enable1)
++ cs |= 1<<0;
++ if (enable2)
++ cs |= 1<<1;
++
++ rfbi_enable_clocks(1);
++
++ l = rfbi_read_reg(RFBI_CONTROL);
++
++ l = FLD_MOD(l, cs, 3, 2);
++ l = FLD_MOD(l, 0, 1, 1);
++
++ rfbi_write_reg(RFBI_CONTROL, l);
++
++
++ l = rfbi_read_reg(RFBI_CONFIG(0));
++ l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
++ /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
++ /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
++
++ l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
++ l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
++ l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
++
++ l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
++ rfbi_write_reg(RFBI_CONFIG(0), l);
++
++ rfbi_enable_clocks(0);
++}
++#endif
++
++int rfbi_configure(int rfbi_module, int bpp, int lines)
++{
++ u32 l;
++ int cycle1 = 0, cycle2 = 0, cycle3 = 0;
++ enum omap_rfbi_cycleformat cycleformat;
++ enum omap_rfbi_datatype datatype;
++ enum omap_rfbi_parallelmode parallelmode;
++
++ switch (bpp) {
++ case 12:
++ datatype = OMAP_DSS_RFBI_DATATYPE_12;
++ break;
++ case 16:
++ datatype = OMAP_DSS_RFBI_DATATYPE_16;
++ break;
++ case 18:
++ datatype = OMAP_DSS_RFBI_DATATYPE_18;
++ break;
++ case 24:
++ datatype = OMAP_DSS_RFBI_DATATYPE_24;
++ break;
++ default:
++ BUG();
++ return 1;
++ }
++ rfbi.datatype = datatype;
++
++ switch (lines) {
++ case 8:
++ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
++ break;
++ case 9:
++ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
++ break;
++ case 12:
++ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
++ break;
++ case 16:
++ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
++ break;
++ default:
++ BUG();
++ return 1;
++ }
++ rfbi.parallelmode = parallelmode;
++
++ if ((bpp % lines) == 0) {
++ switch (bpp / lines) {
++ case 1:
++ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
++ break;
++ case 2:
++ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
++ break;
++ case 3:
++ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
++ break;
++ default:
++ BUG();
++ return 1;
++ }
++ } else if ((2 * bpp % lines) == 0) {
++ if ((2 * bpp / lines) == 3)
++ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
++ else {
++ BUG();
++ return 1;
++ }
++ } else {
++ BUG();
++ return 1;
++ }
++
++ switch (cycleformat) {
++ case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
++ cycle1 = lines;
++ break;
++
++ case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
++ cycle1 = lines;
++ cycle2 = lines;
++ break;
++
++ case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
++ cycle1 = lines;
++ cycle2 = lines;
++ cycle3 = lines;
++ break;
++
++ case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
++ cycle1 = lines;
++ cycle2 = (lines / 2) | ((lines / 2) << 16);
++ cycle3 = (lines << 16);
++ break;
++ }
++
++ rfbi_enable_clocks(1);
++
++ REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
++
++ l = 0;
++ l |= FLD_VAL(parallelmode, 1, 0);
++ l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */
++ l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */
++ l |= FLD_VAL(datatype, 6, 5);
++ /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
++ l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */
++ l |= FLD_VAL(cycleformat, 10, 9);
++ l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */
++ l |= FLD_VAL(0, 16, 16); /* A0POLARITY */
++ l |= FLD_VAL(0, 17, 17); /* REPOLARITY */
++ l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */
++ l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */
++ l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */
++ l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */
++ rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
++
++ rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
++ rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
++ rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
++
++
++ l = rfbi_read_reg(RFBI_CONTROL);
++ l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
++ l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
++ rfbi_write_reg(RFBI_CONTROL, l);
++
++
++ DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
++ bpp, lines, cycle1, cycle2, cycle3);
++
++ rfbi_enable_clocks(0);
++
++ return 0;
++}
++
++static int rfbi_find_display(struct omap_display *disp)
++{
++ if (disp == rfbi.display[0])
++ return 0;
++
++ if (disp == rfbi.display[1])
++ return 1;
++
++ BUG();
++ return -1;
++}
++
++
++static void signal_fifo_waiters(void)
++{
++ if (atomic_read(&rfbi.cmd_fifo_full) > 0) {
++ /* DSSDBG("SIGNALING: Fifo not full for waiter!\n"); */
++ complete(&rfbi.cmd_done);
++ atomic_dec(&rfbi.cmd_fifo_full);
++ }
++}
++
++/* returns 1 for async op, and 0 for sync op */
++static int do_update(struct omap_display *display, struct update_region *upd)
++{
++ int x = upd->x;
++ int y = upd->y;
++ int w = upd->w;
++ int h = upd->h;
++
++ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++ /*display->ctrl->enable_te(display, 1); */
++
++ dispc_setup_partial_planes(display, &x, &y, &w, &h);
++
++ display->ctrl->setup_update(display, x, y, w, h);
++
++ rfbi_transfer_area(w, h, NULL, NULL);
++
++ return 1;
++ } else {
++ struct omap_overlay *ovl;
++ void *addr;
++ int scr_width;
++#ifdef MEASURE_PERF
++ ktime_t t1, t2;
++#endif
++ ovl = &display->manager->overlays[0];
++ scr_width = ovl->info.screen_width;
++ addr = ovl->info.vaddr;
++
++ display->ctrl->setup_update(display, x, y, w, h);
++
++#ifdef MEASURE_PERF
++ t1 = ktime_get();
++#endif
++ omap_rfbi_write_pixels(addr, scr_width,
++ x, y, w, h);
++#ifdef MEASURE_PERF
++ t2 = ktime_get();
++ t1 = ktime_sub(t2, t1);
++ DSSDBG("L4 FRAMEDONE in %lld ns\n",
++ ktime_to_ns(t1));
++#endif
++ return 0;
++ }
++}
++
++static void process_cmd_fifo(void)
++{
++ int len;
++ struct update_param p;
++ struct omap_display *display;
++ unsigned long flags;
++
++ if (atomic_inc_return(&rfbi.cmd_pending) != 1)
++ return;
++
++ while (true) {
++ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
++
++ len = __kfifo_get(rfbi.cmd_fifo, (unsigned char *)&p,
++ sizeof(struct update_param));
++ if (len == 0) {
++ DSSDBG("nothing more in fifo\n");
++ atomic_set(&rfbi.cmd_pending, 0);
++ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++ break;
++ }
++
++ /* DSSDBG("fifo full %d\n", rfbi.cmd_fifo_full.counter);*/
++
++ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++
++ BUG_ON(len != sizeof(struct update_param));
++ BUG_ON(p.rfbi_module > 1);
++
++ display = rfbi.display[p.rfbi_module];
++
++ if (p.cmd == RFBI_CMD_UPDATE) {
++ if (do_update(display, &p.par.r))
++ break; /* async op */
++ } else if (p.cmd == RFBI_CMD_SYNC) {
++ DSSDBG("Signaling SYNC done!\n");
++ complete(p.par.sync);
++ } else
++ BUG();
++ }
++
++ signal_fifo_waiters();
++}
++
++static void rfbi_push_cmd(struct update_param *p)
++{
++ int ret;
++
++ while (1) {
++ unsigned long flags;
++ int available;
++
++ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
++ available = RFBI_CMD_FIFO_LEN_BYTES -
++ __kfifo_len(rfbi.cmd_fifo);
++
++/* DSSDBG("%d bytes left in fifo\n", available); */
++ if (available < sizeof(struct update_param)) {
++ DSSDBG("Going to wait because FIFO FULL..\n");
++ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++ atomic_inc(&rfbi.cmd_fifo_full);
++ wait_for_completion(&rfbi.cmd_done);
++ /*DSSDBG("Woke up because fifo not full anymore\n");*/
++ continue;
++ }
++
++ ret = __kfifo_put(rfbi.cmd_fifo, (unsigned char *)p,
++ sizeof(struct update_param));
++/* DSSDBG("pushed %d bytes\n", ret);*/
++
++ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++
++ BUG_ON(ret != sizeof(struct update_param));
++
++ break;
++ }
++}
++
++static void rfbi_push_update(int rfbi_module, int x, int y, int w, int h)
++{
++ struct update_param p;
++
++ p.rfbi_module = rfbi_module;
++ p.cmd = RFBI_CMD_UPDATE;
++
++ p.par.r.x = x;
++ p.par.r.y = y;
++ p.par.r.w = w;
++ p.par.r.h = h;
++
++ DSSDBG("RFBI pushed %d,%d %dx%d\n", x, y, w, h);
++
++ rfbi_push_cmd(&p);
++
++ process_cmd_fifo();
++}
++
++static void rfbi_push_sync(int rfbi_module, struct completion *sync_comp)
++{
++ struct update_param p;
++
++ p.rfbi_module = rfbi_module;
++ p.cmd = RFBI_CMD_SYNC;
++ p.par.sync = sync_comp;
++
++ rfbi_push_cmd(&p);
++
++ DSSDBG("RFBI sync pushed to cmd fifo\n");
++
++ process_cmd_fifo();
++}
++
++int rfbi_init(void)
++{
++ u32 rev;
++ u32 l;
++
++ spin_lock_init(&rfbi.cmd_lock);
++ rfbi.cmd_fifo = kfifo_alloc(RFBI_CMD_FIFO_LEN_BYTES, GFP_KERNEL,
++ &rfbi.cmd_lock);
++ if (IS_ERR(rfbi.cmd_fifo))
++ return -ENOMEM;
++
++ init_completion(&rfbi.cmd_done);
++ atomic_set(&rfbi.cmd_fifo_full, 0);
++ atomic_set(&rfbi.cmd_pending, 0);
++
++ rfbi.base = ioremap(RFBI_BASE, SZ_256);
++ if (!rfbi.base) {
++ DSSERR("can't ioremap RFBI\n");
++ return -ENOMEM;
++ }
++
++ rfbi.dss_ick = get_dss_ick();
++ rfbi.dss1_fck = get_dss1_fck();
++
++ rfbi_enable_clocks(1);
++
++ msleep(10);
++
++ rfbi.l4_khz = clk_get_rate(rfbi.dss_ick) / 1000;
++
++ /* Enable autoidle and smart-idle */
++ l = rfbi_read_reg(RFBI_SYSCONFIG);
++ l |= (1 << 0) | (2 << 3);
++ rfbi_write_reg(RFBI_SYSCONFIG, l);
++
++ rev = rfbi_read_reg(RFBI_REVISION);
++ printk(KERN_INFO "OMAP RFBI rev %d.%d\n",
++ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++ rfbi_enable_clocks(0);
++
++ return 0;
++}
++
++void rfbi_exit(void)
++{
++ DSSDBG("rfbi_exit\n");
++
++ kfifo_free(rfbi.cmd_fifo);
++
++ iounmap(rfbi.base);
++}
++
++/* struct omap_display support */
++static void rfbi_display_set_mode(struct omap_display *display,
++ int x_res, int y_res, int bpp)
++{
++ display->bpp = bpp;
++
++ dispc_set_tft_data_lines(display->bpp);
++
++ if (rfbi_configure(display->hw_config.u.rfbi.channel,
++ display->bpp,
++ display->hw_config.u.rfbi.data_lines) != 0) {
++ DSSERR("can't configure rfbi\n");
++ }
++
++ display->ctrl->set_mode(display, x_res, y_res, bpp);
++}
++
++
++static int rfbi_display_update(struct omap_display *display,
++ int x, int y, int w, int h)
++{
++ int rfbi_module;
++
++ if (w == 0 || h == 0)
++ return 0;
++
++ rfbi_module = rfbi_find_display(display);
++
++ rfbi_push_update(rfbi_module, x, y, w, h);
++
++ return 0;
++}
++
++static int rfbi_display_sync(struct omap_display *display)
++{
++ struct completion sync_comp;
++ int rfbi_module;
++
++ rfbi_module = rfbi_find_display(display);
++
++ init_completion(&sync_comp);
++ rfbi_push_sync(rfbi_module, &sync_comp);
++ DSSDBG("Waiting for SYNC to happen...\n");
++ wait_for_completion(&sync_comp);
++ DSSDBG("Released from SYNC\n");
++ return 0;
++}
++
++static int rfbi_display_enable_te(struct omap_display *display, int enable)
++{
++ display->ctrl->enable_te(display, enable);
++ return 0;
++}
++
++static int rfbi_display_enable(struct omap_display *display)
++{
++ int r;
++
++ BUG_ON(display->panel == NULL || display->ctrl == NULL);
++
++ r = omap_dispc_register_isr(framedone_callback, NULL,
++ DISPC_IRQ_FRAMEDONE);
++ if (r) {
++ DSSERR("can't get FRAMEDONE irq\n");
++ return r;
++ }
++
++ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
++
++ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI);
++
++ /* FIX select 16bpp as default */
++ rfbi_configure(display->hw_config.u.rfbi.channel,
++ 16,
++ display->hw_config.u.rfbi.data_lines);
++
++ rfbi_set_timings(display->hw_config.u.rfbi.channel,
++ &display->ctrl->timings);
++
++ display->ctrl->enable(display);
++
++ return 0;
++}
++
++static void rfbi_display_disable(struct omap_display *display)
++{
++ display->ctrl->disable(display);
++ omap_dispc_unregister_isr(framedone_callback);
++}
++
++void rfbi_init_display(struct omap_display *display)
++{
++ display->enable = rfbi_display_enable;
++ display->disable = rfbi_display_disable;
++ display->set_mode = rfbi_display_set_mode;
++ display->update = rfbi_display_update;
++ display->sync = rfbi_display_sync;
++ display->enable_te = rfbi_display_enable_te;
++
++ rfbi.display[display->hw_config.u.rfbi.channel] = display;
++
++ display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
++}
diff --git a/arch/arm/plat-omap/dss/sdi.c b/arch/arm/plat-omap/dss/sdi.c
new file mode 100644
-index 0000000..3f114f2
+index 0000000..de19d47
--- /dev/null
+++ b/arch/arm/plat-omap/dss/sdi.c
-@@ -0,0 +1,154 @@
+@@ -0,0 +1,157 @@
+/*
+ * linux/arch/arm/plat-omap/dss/sdi.c
+ *
@@ -3749,7 +8102,8 @@ index 0000000..3f114f2
+
+static int sdi_display_enable(struct omap_display *display)
+{
-+ int fck_div, lck_div, pck_div;
++ struct dispc_clock_info cinfo;
++ int lck_div, pck_div;
+ unsigned long fck;
+
+ struct omap_panel *panel = display->panel;
@@ -3769,15 +8123,17 @@ index 0000000..3f114f2
+ dispc_set_lcd_timings(&panel->timings);
+ dispc_set_pol_freq(panel);
+
-+ fck = dispc_calc_clock_div(1, panel->timings.pixel_clock*1000,
-+ &fck_div, &lck_div, &pck_div);
++ dispc_calc_clock_div(1, panel->timings.pixel_clock * 1000,
++ &cinfo);
+
-+ if (fck == 0) {
-+ DSSERR("Requested pixel clock is not possible\n");
++ if (dispc_set_clock_div(&cinfo)) {
++ DSSERR("Failed to set DSS clocks\n");
+ return -EINVAL;
+ }
+
-+ dispc_set_clock_div(fck_div, lck_div, pck_div);
++ fck = cinfo.fck;
++ lck_div = cinfo.lck_div;
++ pck_div = cinfo.pck_div;
+
+ panel->timings.pixel_clock = fck / lck_div / pck_div / 1000;
+
@@ -3864,9 +8220,530 @@ index 0000000..3f114f2
+void sdi_exit(void)
+{
+}
+diff --git a/arch/arm/plat-omap/dss/venc.c b/arch/arm/plat-omap/dss/venc.c
+new file mode 100644
+index 0000000..2ed68b5
+--- /dev/null
++++ b/arch/arm/plat-omap/dss/venc.c
+@@ -0,0 +1,515 @@
++/*
++ * linux/arch/arm/plat-omap/dss/venc.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * VENC settings from TI's DSS driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "VENC"
++
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/mutex.h>
++#include <linux/completion.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++#include <mach/cpu.h>
++
++#include "dss.h"
++
++#define VENC_BASE 0x48050C00
++
++/* Venc registers */
++#define VENC_REV_ID 0x00
++#define VENC_STATUS 0x04
++#define VENC_F_CONTROL 0x08
++#define VENC_VIDOUT_CTRL 0x10
++#define VENC_SYNC_CTRL 0x14
++#define VENC_LLEN 0x1C
++#define VENC_FLENS 0x20
++#define VENC_HFLTR_CTRL 0x24
++#define VENC_CC_CARR_WSS_CARR 0x28
++#define VENC_C_PHASE 0x2C
++#define VENC_GAIN_U 0x30
++#define VENC_GAIN_V 0x34
++#define VENC_GAIN_Y 0x38
++#define VENC_BLACK_LEVEL 0x3C
++#define VENC_BLANK_LEVEL 0x40
++#define VENC_X_COLOR 0x44
++#define VENC_M_CONTROL 0x48
++#define VENC_BSTAMP_WSS_DATA 0x4C
++#define VENC_S_CARR 0x50
++#define VENC_LINE21 0x54
++#define VENC_LN_SEL 0x58
++#define VENC_L21__WC_CTL 0x5C
++#define VENC_HTRIGGER_VTRIGGER 0x60
++#define VENC_SAVID__EAVID 0x64
++#define VENC_FLEN__FAL 0x68
++#define VENC_LAL__PHASE_RESET 0x6C
++#define VENC_HS_INT_START_STOP_X 0x70
++#define VENC_HS_EXT_START_STOP_X 0x74
++#define VENC_VS_INT_START_X 0x78
++#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
++#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
++#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
++#define VENC_VS_EXT_STOP_Y 0x88
++#define VENC_AVID_START_STOP_X 0x90
++#define VENC_AVID_START_STOP_Y 0x94
++#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
++#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
++#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
++#define VENC_TVDETGP_INT_START_STOP_X 0xB0
++#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
++#define VENC_GEN_CTRL 0xB8
++#define VENC_OUTPUT_CONTROL 0xC4
++#define VENC_DAC_B__DAC_C 0xC8
++
++struct venc_config {
++ u32 f_control;
++ u32 vidout_ctrl;
++ u32 sync_ctrl;
++ u32 llen;
++ u32 flens;
++ u32 hfltr_ctrl;
++ u32 cc_carr_wss_carr;
++ u32 c_phase;
++ u32 gain_u;
++ u32 gain_v;
++ u32 gain_y;
++ u32 black_level;
++ u32 blank_level;
++ u32 x_color;
++ u32 m_control;
++ u32 bstamp_wss_data;
++ u32 s_carr;
++ u32 line21;
++ u32 ln_sel;
++ u32 l21__wc_ctl;
++ u32 htrigger_vtrigger;
++ u32 savid__eavid;
++ u32 flen__fal;
++ u32 lal__phase_reset;
++ u32 hs_int_start_stop_x;
++ u32 hs_ext_start_stop_x;
++ u32 vs_int_start_x;
++ u32 vs_int_stop_x__vs_int_start_y;
++ u32 vs_int_stop_y__vs_ext_start_x;
++ u32 vs_ext_stop_x__vs_ext_start_y;
++ u32 vs_ext_stop_y;
++ u32 avid_start_stop_x;
++ u32 avid_start_stop_y;
++ u32 fid_int_start_x__fid_int_start_y;
++ u32 fid_int_offset_y__fid_ext_start_x;
++ u32 fid_ext_start_y__fid_ext_offset_y;
++ u32 tvdetgp_int_start_stop_x;
++ u32 tvdetgp_int_start_stop_y;
++ u32 gen_ctrl;
++
++ int width;
++ int height;
++};
++
++/* from TRM */
++static const struct venc_config venc_config_pal_trm = {
++ .f_control = 0,
++ .vidout_ctrl = 1,
++ .sync_ctrl = 0x40,
++ .llen = 0x35F, /* 863 */
++ .flens = 0x270, /* 624 */
++ .hfltr_ctrl = 0,
++ .cc_carr_wss_carr = 0x2F7225ED,
++ .c_phase = 0,
++ .gain_u = 0x111,
++ .gain_v = 0x181,
++ .gain_y = 0x140,
++ .black_level = 0x3B,
++ .blank_level = 0x3B,
++ .x_color = 0x7,
++ .m_control = 0x2,
++ .bstamp_wss_data = 0x3F,
++ .s_carr = 0x2A098ACB,
++ .line21 = 0,
++ .ln_sel = 0x01290015,
++ .l21__wc_ctl = 0x0000F603,
++ .htrigger_vtrigger = 0,
++
++ .savid__eavid = 0x06A70108,
++ .flen__fal = 0x00180270,
++ .lal__phase_reset = 0x00180270,
++ .hs_int_start_stop_x = 0x00880358,
++ .hs_ext_start_stop_x = 0x000F035F,
++ .vs_int_start_x = 0x01A70000,
++ .vs_int_stop_x__vs_int_start_y = 0x000001A7,
++ .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
++ .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
++ .vs_ext_stop_y = 0x00000025,
++ .avid_start_stop_x = 0x03530083,
++ .avid_start_stop_y = 0x026C002E,
++ .fid_int_start_x__fid_int_start_y = 0x0001008A,
++ .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
++ .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
++
++ .tvdetgp_int_start_stop_x = 0x00140001,
++ .tvdetgp_int_start_stop_y = 0x00010001,
++ .gen_ctrl = 0x00FF0000,
++
++ .width = 720,
++ .height = 574, /* for some reason, this isn't 576 */
++};
++
++/* from TRM */
++static const struct venc_config venc_config_ntsc_trm = {
++ .f_control = 0,
++ .vidout_ctrl = 1,
++ .sync_ctrl = 0x8040,
++ .llen = 0x359,
++ .flens = 0x20C,
++ .hfltr_ctrl = 0,
++ .cc_carr_wss_carr = 0x043F2631,
++ .c_phase = 0,
++ .gain_u = 0x102,
++ .gain_v = 0x16C,
++ .gain_y = 0x12F,
++ .black_level = 0x43,
++ .blank_level = 0x38,
++ .x_color = 0x7,
++ .m_control = 0x1,
++ .bstamp_wss_data = 0x38,
++ .s_carr = 0x21F07C1F,
++ .line21 = 0,
++ .ln_sel = 0x01310011,
++ .l21__wc_ctl = 0x0000F003,
++ .htrigger_vtrigger = 0,
++
++ .savid__eavid = 0x069300F4,
++ .flen__fal = 0x0016020C,
++ .lal__phase_reset = 0x00060107,
++ .hs_int_start_stop_x = 0x008E0350,
++ .hs_ext_start_stop_x = 0x000F0359,
++ .vs_int_start_x = 0x01A00000,
++ .vs_int_stop_x__vs_int_start_y = 0x020701A0,
++ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
++ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
++ .vs_ext_stop_y = 0x00000006,
++ .avid_start_stop_x = 0x03480078,
++ .avid_start_stop_y = 0x02060024,
++ .fid_int_start_x__fid_int_start_y = 0x0001008A,
++ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
++ .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
++
++ .tvdetgp_int_start_stop_x = 0x00140001,
++ .tvdetgp_int_start_stop_y = 0x00010001,
++ .gen_ctrl = 0x00F90000,
++
++ .width = 720,
++ .height = 482,
++};
++
++static const struct venc_config venc_config_pal_bdghi = {
++ .f_control = 0,
++ .vidout_ctrl = 0,
++ .sync_ctrl = 0,
++ .hfltr_ctrl = 0,
++ .x_color = 0,
++ .line21 = 0,
++ .ln_sel = 21,
++ .htrigger_vtrigger = 0,
++ .tvdetgp_int_start_stop_x = 0x00140001,
++ .tvdetgp_int_start_stop_y = 0x00010001,
++ .gen_ctrl = 0x00FB0000,
++
++ .llen = 864-1,
++ .flens = 625-1,
++ .cc_carr_wss_carr = 0x2F7625ED,
++ .c_phase = 0xDF,
++ .gain_u = 0x111,
++ .gain_v = 0x181,
++ .gain_y = 0x140,
++ .black_level = 0x3e,
++ .blank_level = 0x3e,
++ .m_control = 0<<2 | 1<<1,
++ .bstamp_wss_data = 0x42,
++ .s_carr = 0x2a098acb,
++ .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
++ .savid__eavid = 0x06A70108,
++ .flen__fal = 23<<16 | 624<<0,
++ .lal__phase_reset = 2<<17 | 310<<0,
++ .hs_int_start_stop_x = 0x00920358,
++ .hs_ext_start_stop_x = 0x000F035F,
++ .vs_int_start_x = 0x1a7<<16,
++ .vs_int_stop_x__vs_int_start_y = 0x000601A7,
++ .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
++ .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
++ .vs_ext_stop_y = 0x05,
++ .avid_start_stop_x = 0x03530082,
++ .avid_start_stop_y = 0x0270002E,
++ .fid_int_start_x__fid_int_start_y = 0x0005008A,
++ .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
++ .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
++
++ .width = 720,
++ .height = 576,
++};
++
++static struct {
++ void __iomem *base;
++ struct clk *dss_54m_fck;
++ struct clk *dss_96m_fck;
++ struct clk *dss_ick;
++ struct clk *dss1_fck;
++ const struct venc_config *config;
++ struct mutex venc_lock;
++} venc;
++
++static struct omap_panel venc_panel = {
++ .name = "tv-out",
++ .x_res = 0,
++ .y_res = 0,
++ .bpp = 24,
++};
++
++static inline void venc_write_reg(int idx, u32 val)
++{
++ __raw_writel(val, venc.base + idx);
++}
++
++static inline u32 venc_read_reg(int idx)
++{
++ u32 l = __raw_readl(venc.base + idx);
++ return l;
++}
++
++static void venc_write_config(const struct venc_config *config)
++{
++ DSSDBG("write venc conf\n");
++
++ venc_write_reg(VENC_LLEN, config->llen);
++ venc_write_reg(VENC_FLENS, config->flens);
++ venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
++ venc_write_reg(VENC_C_PHASE, config->c_phase);
++ venc_write_reg(VENC_GAIN_U, config->gain_u);
++ venc_write_reg(VENC_GAIN_V, config->gain_v);
++ venc_write_reg(VENC_GAIN_Y, config->gain_y);
++ venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
++ venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
++ venc_write_reg(VENC_M_CONTROL, config->m_control);
++ venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
++ venc_write_reg(VENC_S_CARR, config->s_carr);
++ venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
++ venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
++ venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
++ venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
++ venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
++ venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
++ venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
++ venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
++ config->vs_int_stop_x__vs_int_start_y);
++ venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
++ config->vs_int_stop_y__vs_ext_start_x);
++ venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
++ config->vs_ext_stop_x__vs_ext_start_y);
++ venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
++ venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
++ venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
++ venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
++ config->fid_int_start_x__fid_int_start_y);
++ venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
++ config->fid_int_offset_y__fid_ext_start_x);
++ venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
++ config->fid_ext_start_y__fid_ext_offset_y);
++
++ venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
++ venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
++ venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
++ venc_write_reg(VENC_X_COLOR, config->x_color);
++ venc_write_reg(VENC_LINE21, config->line21);
++ venc_write_reg(VENC_LN_SEL, config->ln_sel);
++ venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
++ venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
++ config->tvdetgp_int_start_stop_x);
++ venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
++ config->tvdetgp_int_start_stop_y);
++ venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
++ venc_write_reg(VENC_F_CONTROL, config->f_control);
++ venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
++}
++
++static void venc_reset(void)
++{
++ int t = 1000;
++
++ venc_write_reg(VENC_F_CONTROL, venc_read_reg(VENC_F_CONTROL) | (1<<8));
++ while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
++ if (--t == 0) {
++ DSSERR("Failed to reset venc\n");
++ return;
++ }
++ }
++}
++
++static void venc_enable_clocks(int enable)
++{
++ if (enable) {
++ clk_enable(venc.dss_ick);
++ clk_enable(venc.dss1_fck);
++ clk_enable(venc.dss_54m_fck);
++ clk_enable(venc.dss_96m_fck);
++ } else {
++ clk_disable(venc.dss_96m_fck);
++ clk_disable(venc.dss_54m_fck);
++ clk_disable(venc.dss1_fck);
++ clk_disable(venc.dss_ick);
++ }
++}
++
++int venc_init(void)
++{
++ u8 rev_id;
++ int use_pal = 1; /* XXX */
++
++ mutex_init(&venc.venc_lock);
++
++ if (use_pal)
++ venc.config = &venc_config_pal_trm;
++ else
++ venc.config = &venc_config_ntsc_trm;
++
++ venc_panel.x_res = venc.config->width;
++ venc_panel.y_res = venc.config->height;
++
++ venc.base = ioremap(VENC_BASE, SZ_1K);
++ if (!venc.base) {
++ DSSERR("can't ioremap VENC\n");
++ return -ENOMEM;
++ }
++
++ venc.dss_ick = get_dss_ick();
++ venc.dss1_fck = get_dss1_fck();
++ venc.dss_54m_fck = get_tv_fck();
++ venc.dss_96m_fck = get_96m_fck();
++
++ /* enable clocks */
++ venc_enable_clocks(1);
++
++ /* configure venc */
++ venc_reset();
++ venc_write_config(venc.config);
++
++ rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
++ printk(KERN_INFO "OMAP VENC rev %d\n", rev_id);
++
++ venc_enable_clocks(0);
++
++ return 0;
++}
++
++void venc_exit(void)
++{
++ iounmap(venc.base);
++}
++
++static void venc_sync_lost_handler(void *arg, u32 mask)
++{
++ /* we just catch SYNC_LOST_DIGIT here so that
++ * dispc doesn't take it as an error */
++}
++
++static int venc_enable_display(struct omap_display *display)
++{
++ DSSDBG("venc_enable_display\n");
++
++ mutex_lock(&venc.venc_lock);
++
++ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
++ mutex_unlock(&venc.venc_lock);
++ return -EINVAL;
++ }
++
++ venc_enable_clocks(1);
++
++ dss_set_venc_output(display->hw_config.u.venc.type);
++ dss_set_dac_pwrdn_bgz(1);
++
++ if (display->hw_config.u.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) {
++ if (cpu_is_omap24xx())
++ venc_write_reg(VENC_OUTPUT_CONTROL, 0x2);
++ else
++ venc_write_reg(VENC_OUTPUT_CONTROL, 0xa);
++ } else { /* S-Video */
++ venc_write_reg(VENC_OUTPUT_CONTROL, 0xd);
++ }
++
++ venc_write_config(venc.config);
++
++ dispc_set_digit_size(venc.config->width, venc.config->height/2);
++
++ if (display->hw_config.panel_enable)
++ display->hw_config.panel_enable(display);
++
++ dispc_go(OMAP_DSS_CHANNEL_DIGIT);
++
++ omap_dispc_register_isr(venc_sync_lost_handler, 0,
++ DISPC_IRQ_SYNC_LOST_DIGIT);
++
++ dispc_enable_digit_out(1);
++
++ mdelay(20);
++
++ omap_dispc_unregister_isr(venc_sync_lost_handler);
++
++ display->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++ mutex_unlock(&venc.venc_lock);
++
++ return 0;
++}
++
++static void venc_disable_display(struct omap_display *display)
++{
++ DSSDBG("venc_disable_display\n");
++
++ mutex_lock(&venc.venc_lock);
++
++ if (display->state == OMAP_DSS_DISPLAY_DISABLED) {
++ mutex_unlock(&venc.venc_lock);
++ return;
++ }
++
++ venc_write_reg(VENC_OUTPUT_CONTROL, 0);
++ dss_set_dac_pwrdn_bgz(0);
++
++ dispc_enable_digit_out(0);
++
++ if (display->hw_config.panel_disable)
++ display->hw_config.panel_disable(display);
++
++ venc_enable_clocks(0);
++
++ display->state = OMAP_DSS_DISPLAY_DISABLED;
++
++ mutex_unlock(&venc.venc_lock);
++}
++
++void venc_init_display(struct omap_display *display)
++{
++ display->panel = &venc_panel;
++ display->enable = venc_enable_display;
++ display->disable = venc_disable_display;
++}
diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
new file mode 100644
-index 0000000..05e78de
+index 0000000..2e55fae
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/display.h
@@ -0,0 +1,458 @@
@@ -4259,7 +9136,7 @@ index 0000000..05e78de
+};
+
+struct omap_display {
-+ //atomic_t ref_count;
++ /*atomic_t ref_count;*/
+ int ref_count;
+
+ enum omap_display_type type;
diff --git a/packages/linux/linux-omap/0008-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch b/packages/linux/linux-omap/0005-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch
index 76cc5c793e..57a12c1a79 100644
--- a/packages/linux/linux-omap/0008-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch
+++ b/packages/linux/linux-omap/0005-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch
@@ -1,4 +1,4 @@
-From a993119097b63f30364ca17db4d039a401c44b4d Mon Sep 17 00:00:00 2001
+From 538201a6cc52913c8165644d8c5ee1dd2c2b2a95 Mon Sep 17 00:00:00 2001
From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Date: Tue, 4 Nov 2008 15:12:21 +0200
Subject: [PATCH] DSS: OMAPFB: fb driver for new display subsystem
@@ -13,10 +13,10 @@ Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
drivers/video/omap2/Kconfig | 29 +
drivers/video/omap2/Makefile | 2 +
drivers/video/omap2/omapfb-ioctl.c | 428 ++++++++++
- drivers/video/omap2/omapfb-main.c | 1247 ++++++++++++++++++++++++++++++
- drivers/video/omap2/omapfb-sysfs.c | 833 ++++++++++++++++++++
+ drivers/video/omap2/omapfb-main.c | 1276 ++++++++++++++++++++++++++++++
+ drivers/video/omap2/omapfb-sysfs.c | 833 +++++++++++++++++++
drivers/video/omap2/omapfb.h | 104 +++
- 11 files changed, 2663 insertions(+), 3 deletions(-)
+ 11 files changed, 2692 insertions(+), 3 deletions(-)
create mode 100644 drivers/video/omap2/Kconfig
create mode 100644 drivers/video/omap2/Makefile
create mode 100644 drivers/video/omap2/omapfb-ioctl.c
@@ -74,7 +74,7 @@ index 3746222..0ba1603 100644
return platform_device_register(&omap_fb_device);
}
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
-index a3c4408..e69c0b1 100644
+index 90d63c5..1e34304 100644
--- a/arch/arm/plat-omap/include/mach/omapfb.h
+++ b/arch/arm/plat-omap/include/mach/omapfb.h
@@ -90,6 +90,13 @@ enum omapfb_color_format {
@@ -116,7 +116,7 @@ index 248bddc..4d69355 100644
obj-$(CONFIG_FB_CARMINE) += carminefb.o
diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig
-index 5ebd591..8b6c675 100644
+index c355b59..541fab3 100644
--- a/drivers/video/omap/Kconfig
+++ b/drivers/video/omap/Kconfig
@@ -1,6 +1,7 @@
@@ -128,7 +128,7 @@ index 5ebd591..8b6c675 100644
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
-@@ -76,7 +77,7 @@ config FB_OMAP_BOOTLOADER_INIT
+@@ -80,7 +81,7 @@ config FB_OMAP_BOOTLOADER_INIT
config FB_OMAP_CONSISTENT_DMA_SIZE
int "Consistent DMA memory size (MB)"
@@ -616,10 +616,10 @@ index 0000000..1ceb6b9
+
diff --git a/drivers/video/omap2/omapfb-main.c b/drivers/video/omap2/omapfb-main.c
new file mode 100644
-index 0000000..7ef7080
+index 0000000..c0f1664
--- /dev/null
+++ b/drivers/video/omap2/omapfb-main.c
-@@ -0,0 +1,1247 @@
+@@ -0,0 +1,1276 @@
+/*
+ * linux/drivers/video/omap2/omapfb-main.c
+ *
@@ -828,6 +828,9 @@ index 0000000..7ef7080
+
+ fix->accel = FB_ACCEL_NONE;
+ fix->line_length = (var->xres_virtual * var->bits_per_pixel) >> 3;
++
++ fix->xpanstep = 1;
++ fix->ypanstep = 1;
+}
+
+/* check new var and possibly modify it to be ok */
@@ -1184,8 +1187,34 @@ index 0000000..7ef7080
+static int omapfb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *fbi)
+{
-+ DBG("pan_display(%d)\n", FB2OFB(fbi)->id);
-+ return 0;
++ struct omapfb_info *ofbi = FB2OFB(fbi);
++ struct omapfb2_device *fbdev = ofbi->fbdev;
++ int r = 0;
++
++ DBG("pan_display(%d)\n", ofbi->id);
++
++ omapfb_lock(fbdev);
++
++ if (var->xoffset != fbi->var.xoffset ||
++ var->yoffset != fbi->var.yoffset) {
++ struct fb_var_screeninfo new_var;
++
++ new_var = fbi->var;
++ new_var.xoffset = var->xoffset;
++ new_var.yoffset = var->yoffset;
++
++ r = check_fb_var(fbi, &new_var);
++
++ if (r == 0) {
++ fbi->var = new_var;
++ set_fb_fix(fbi);
++ r = omapfb_apply_changes(fbi, 0);
++ }
++ }
++
++ omapfb_unlock(fbdev);
++
++ return r;
+}
+
+static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
diff --git a/packages/linux/linux-omap/0005-DSS-RFBI-support-for-OMAP2-3-DSS.patch b/packages/linux/linux-omap/0005-DSS-RFBI-support-for-OMAP2-3-DSS.patch
deleted file mode 100644
index de376e6bd8..0000000000
--- a/packages/linux/linux-omap/0005-DSS-RFBI-support-for-OMAP2-3-DSS.patch
+++ /dev/null
@@ -1,1254 +0,0 @@
-From 029f985ead9e1ea4f5d26c5ee1a234c144d2b418 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Tue, 4 Nov 2008 16:53:02 +0200
-Subject: [PATCH] DSS: RFBI support for OMAP2/3 DSS
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- arch/arm/plat-omap/dss/rfbi.c | 1234 +++++++++++++++++++++++++++++++++++++++++
- 1 files changed, 1234 insertions(+), 0 deletions(-)
- create mode 100644 arch/arm/plat-omap/dss/rfbi.c
-
-diff --git a/arch/arm/plat-omap/dss/rfbi.c b/arch/arm/plat-omap/dss/rfbi.c
-new file mode 100644
-index 0000000..31ddd24
---- /dev/null
-+++ b/arch/arm/plat-omap/dss/rfbi.c
-@@ -0,0 +1,1234 @@
-+/*
-+ * linux/arch/arm/plat-omap/dss/rfbi.c
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "RFBI"
-+
-+#include <linux/kernel.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/vmalloc.h>
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/delay.h>
-+#include <linux/kfifo.h>
-+#include <linux/ktime.h>
-+
-+#include <mach/board.h>
-+#include <mach/display.h>
-+#include "dss.h"
-+
-+/*#define MEASURE_PERF*/
-+
-+#define RFBI_BASE 0x48050800
-+
-+struct rfbi_reg { u16 idx; };
-+
-+#define RFBI_REG(idx) ((const struct rfbi_reg) { idx })
-+
-+#define RFBI_REVISION RFBI_REG(0x0000)
-+#define RFBI_SYSCONFIG RFBI_REG(0x0010)
-+#define RFBI_SYSSTATUS RFBI_REG(0x0014)
-+#define RFBI_CONTROL RFBI_REG(0x0040)
-+#define RFBI_PIXEL_CNT RFBI_REG(0x0044)
-+#define RFBI_LINE_NUMBER RFBI_REG(0x0048)
-+#define RFBI_CMD RFBI_REG(0x004c)
-+#define RFBI_PARAM RFBI_REG(0x0050)
-+#define RFBI_DATA RFBI_REG(0x0054)
-+#define RFBI_READ RFBI_REG(0x0058)
-+#define RFBI_STATUS RFBI_REG(0x005c)
-+
-+#define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18)
-+#define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18)
-+#define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18)
-+#define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18)
-+#define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18)
-+#define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18)
-+
-+#define RFBI_VSYNC_WIDTH RFBI_REG(0x0090)
-+#define RFBI_HSYNC_WIDTH RFBI_REG(0x0094)
-+
-+#define RFBI_CMD_FIFO_LEN_BYTES (16 * sizeof(struct update_param))
-+
-+#define REG_FLD_MOD(idx, val, start, end) \
-+ rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
-+
-+/* To work around an RFBI transfer rate limitation */
-+#define OMAP_RFBI_RATE_LIMIT 1
-+
-+enum omap_rfbi_cycleformat {
-+ OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
-+ OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
-+ OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
-+ OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
-+};
-+
-+enum omap_rfbi_datatype {
-+ OMAP_DSS_RFBI_DATATYPE_12 = 0,
-+ OMAP_DSS_RFBI_DATATYPE_16 = 1,
-+ OMAP_DSS_RFBI_DATATYPE_18 = 2,
-+ OMAP_DSS_RFBI_DATATYPE_24 = 3,
-+};
-+
-+enum omap_rfbi_parallelmode {
-+ OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
-+ OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
-+ OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
-+ OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
-+};
-+
-+enum update_cmd {
-+ RFBI_CMD_UPDATE = 0,
-+ RFBI_CMD_SYNC = 1,
-+};
-+
-+static int rfbi_convert_timings(struct rfbi_timings *t);
-+static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
-+static void process_cmd_fifo(void);
-+
-+static struct {
-+ void __iomem *base;
-+
-+ struct clk *dss_ick;
-+ struct clk *dss1_fck;
-+
-+ unsigned long l4_khz;
-+
-+ enum omap_rfbi_datatype datatype;
-+ enum omap_rfbi_parallelmode parallelmode;
-+
-+ enum omap_rfbi_te_mode te_mode;
-+ int te_enabled;
-+
-+ void (*framedone_callback)(void *data);
-+ void *framedone_callback_data;
-+
-+ struct omap_display *display[2];
-+
-+ struct kfifo *cmd_fifo;
-+ spinlock_t cmd_lock;
-+ struct completion cmd_done;
-+ atomic_t cmd_fifo_full;
-+ atomic_t cmd_pending;
-+#ifdef MEASURE_PERF
-+ ktime_t perf_time;
-+#endif
-+} rfbi;
-+
-+struct update_region {
-+ u16 x;
-+ u16 y;
-+ u16 w;
-+ u16 h;
-+};
-+
-+struct update_param {
-+ u8 rfbi_module;
-+ u8 cmd;
-+
-+ union {
-+ struct update_region r;
-+ struct completion *sync;
-+ } par;
-+};
-+
-+static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
-+{
-+ __raw_writel(val, rfbi.base + idx.idx);
-+}
-+
-+static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
-+{
-+ return __raw_readl(rfbi.base + idx.idx);
-+}
-+
-+static void rfbi_enable_clocks(int enable)
-+{
-+ if (enable) {
-+ clk_enable(rfbi.dss_ick);
-+ clk_enable(rfbi.dss1_fck);
-+ } else {
-+ clk_disable(rfbi.dss1_fck);
-+ clk_disable(rfbi.dss_ick);
-+ }
-+}
-+
-+void omap_rfbi_write_command(const void *buf, u32 len)
-+{
-+ rfbi_enable_clocks(1);
-+ switch (rfbi.parallelmode) {
-+ case OMAP_DSS_RFBI_PARALLELMODE_8:
-+ {
-+ const u8 *b = buf;
-+ for (; len; len--)
-+ rfbi_write_reg(RFBI_CMD, *b++);
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_16:
-+ {
-+ const u16 *w = buf;
-+ BUG_ON(len & 1);
-+ for (; len; len -= 2)
-+ rfbi_write_reg(RFBI_CMD, *w++);
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_9:
-+ case OMAP_DSS_RFBI_PARALLELMODE_12:
-+ default:
-+ BUG();
-+ }
-+ rfbi_enable_clocks(0);
-+}
-+EXPORT_SYMBOL(omap_rfbi_write_command);
-+
-+void omap_rfbi_read_data(void *buf, u32 len)
-+{
-+ rfbi_enable_clocks(1);
-+ switch (rfbi.parallelmode) {
-+ case OMAP_DSS_RFBI_PARALLELMODE_8:
-+ {
-+ u8 *b = buf;
-+ for (; len; len--) {
-+ rfbi_write_reg(RFBI_READ, 0);
-+ *b++ = rfbi_read_reg(RFBI_READ);
-+ }
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_16:
-+ {
-+ u16 *w = buf;
-+ BUG_ON(len & ~1);
-+ for (; len; len -= 2) {
-+ rfbi_write_reg(RFBI_READ, 0);
-+ *w++ = rfbi_read_reg(RFBI_READ);
-+ }
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_9:
-+ case OMAP_DSS_RFBI_PARALLELMODE_12:
-+ default:
-+ BUG();
-+ }
-+ rfbi_enable_clocks(0);
-+}
-+EXPORT_SYMBOL(omap_rfbi_read_data);
-+
-+void omap_rfbi_write_data(const void *buf, u32 len)
-+{
-+ rfbi_enable_clocks(1);
-+ switch (rfbi.parallelmode) {
-+ case OMAP_DSS_RFBI_PARALLELMODE_8:
-+ {
-+ const u8 *b = buf;
-+ for (; len; len--)
-+ rfbi_write_reg(RFBI_PARAM, *b++);
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_16:
-+ {
-+ const u16 *w = buf;
-+ BUG_ON(len & 1);
-+ for (; len; len -= 2)
-+ rfbi_write_reg(RFBI_PARAM, *w++);
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_9:
-+ case OMAP_DSS_RFBI_PARALLELMODE_12:
-+ default:
-+ BUG();
-+
-+ }
-+ rfbi_enable_clocks(0);
-+}
-+EXPORT_SYMBOL(omap_rfbi_write_data);
-+
-+void omap_rfbi_write_pixels(const void *buf, int scr_width, int x, int y,
-+ int w, int h)
-+{
-+ int start_offset = scr_width * y + x;
-+ int horiz_offset = scr_width - w;
-+ int i;
-+
-+ rfbi_enable_clocks(1);
-+
-+ if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
-+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
-+ const u16 *pd = buf;
-+ pd += start_offset;
-+
-+ for (; h; --h) {
-+ for (i = 0; i < w; ++i) {
-+ const u8 *b = (const u8 *)pd;
-+ rfbi_write_reg(RFBI_PARAM, *(b+1));
-+ rfbi_write_reg(RFBI_PARAM, *(b+0));
-+ ++pd;
-+ }
-+ pd += horiz_offset;
-+ }
-+ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
-+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
-+ const u32 *pd = buf;
-+ pd += start_offset;
-+
-+ for (; h; --h) {
-+ for (i = 0; i < w; ++i) {
-+ const u8 *b = (const u8 *)pd;
-+ rfbi_write_reg(RFBI_PARAM, *(b+2));
-+ rfbi_write_reg(RFBI_PARAM, *(b+1));
-+ rfbi_write_reg(RFBI_PARAM, *(b+0));
-+ ++pd;
-+ }
-+ pd += horiz_offset;
-+ }
-+ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
-+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
-+ const u16 *pd = buf;
-+ pd += start_offset;
-+
-+ for (; h; --h) {
-+ for (i = 0; i < w; ++i) {
-+ rfbi_write_reg(RFBI_PARAM, *pd);
-+ ++pd;
-+ }
-+ pd += horiz_offset;
-+ }
-+ } else {
-+ BUG();
-+ }
-+
-+ rfbi_enable_clocks(0);
-+}
-+EXPORT_SYMBOL(omap_rfbi_write_pixels);
-+
-+void rfbi_transfer_area(int width, int height,
-+ void (callback)(void *data), void *data)
-+{
-+ u32 l;
-+
-+ /*BUG_ON(callback == 0);*/
-+ BUG_ON(rfbi.framedone_callback != NULL);
-+
-+ DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
-+
-+ dispc_set_lcd_size(width, height);
-+
-+ dispc_enable_lcd_out(1);
-+
-+ rfbi.framedone_callback = callback;
-+ rfbi.framedone_callback_data = data;
-+
-+ rfbi_enable_clocks(1);
-+
-+#ifdef MEASURE_PERF
-+ rfbi.perf_time = ktime_get();
-+#endif
-+ rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
-+
-+ l = rfbi_read_reg(RFBI_CONTROL);
-+ l = FLD_MOD(l, 1, 0, 0); /* enable */
-+ if (!rfbi.te_enabled)
-+ l = FLD_MOD(l, 1, 4, 4); /* ITE */
-+
-+ rfbi_write_reg(RFBI_CONTROL, l);
-+}
-+
-+static void framedone_callback(void *data, u32 mask)
-+{
-+ void (*callback)(void *data);
-+
-+#ifdef MEASURE_PERF
-+ {
-+ ktime_t t = ktime_get();
-+ t = ktime_sub(t, rfbi.perf_time);
-+ DSSDBG("FRAMEDONE in %lld ns\n", ktime_to_ns(t));
-+ }
-+#else
-+ DSSDBG("FRAMEDONE\n");
-+#endif
-+
-+ REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
-+
-+ rfbi_enable_clocks(0);
-+
-+ callback = rfbi.framedone_callback;
-+ rfbi.framedone_callback = NULL;
-+
-+ /*callback(rfbi.framedone_callback_data);*/
-+
-+ atomic_set(&rfbi.cmd_pending, 0);
-+
-+ process_cmd_fifo();
-+}
-+
-+#if 1 /* VERBOSE */
-+static void rfbi_print_timings(void)
-+{
-+ u32 l;
-+ u32 time;
-+
-+ l = rfbi_read_reg(RFBI_CONFIG(0));
-+ time = 1000000000 / rfbi.l4_khz;
-+ if (l & (1 << 4))
-+ time *= 2;
-+
-+ DSSDBG("Tick time %u ps\n", time);
-+ l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
-+ DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
-+ "REONTIME %d, REOFFTIME %d\n",
-+ l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
-+ (l >> 20) & 0x0f, (l >> 24) & 0x3f);
-+
-+ l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
-+ DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
-+ "ACCESSTIME %d\n",
-+ (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
-+ (l >> 22) & 0x3f);
-+}
-+#else
-+static void rfbi_print_timings(void) {}
-+#endif
-+
-+
-+
-+
-+static u32 extif_clk_period;
-+
-+static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
-+{
-+ int bus_tick = extif_clk_period * div;
-+ return (ps + bus_tick - 1) / bus_tick * bus_tick;
-+}
-+
-+static int calc_reg_timing(struct rfbi_timings *t, int div)
-+{
-+ t->clk_div = div;
-+
-+ t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
-+
-+ t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
-+ t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
-+ t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
-+
-+ t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
-+ t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
-+ t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
-+
-+ t->access_time = round_to_extif_ticks(t->access_time, div);
-+ t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
-+ t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
-+
-+ DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
-+ t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
-+ DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
-+ t->we_on_time, t->we_off_time, t->re_cycle_time,
-+ t->we_cycle_time);
-+ DSSDBG("[reg]rdaccess %d cspulse %d\n",
-+ t->access_time, t->cs_pulse_width);
-+
-+ return rfbi_convert_timings(t);
-+}
-+
-+static int calc_extif_timings(struct rfbi_timings *t)
-+{
-+ u32 max_clk_div;
-+ int div;
-+
-+ rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
-+ for (div = 1; div <= max_clk_div; div++) {
-+ if (calc_reg_timing(t, div) == 0)
-+ break;
-+ }
-+
-+ if (div <= max_clk_div)
-+ return 0;
-+
-+ DSSERR("can't setup timings\n");
-+ return -1;
-+}
-+
-+
-+void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
-+{
-+ int r;
-+
-+ if (!t->converted) {
-+ r = calc_extif_timings(t);
-+ if (r < 0)
-+ DSSERR("Failed to calc timings\n");
-+ }
-+
-+ BUG_ON(!t->converted);
-+
-+ rfbi_enable_clocks(1);
-+ rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
-+ rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
-+
-+ /* TIMEGRANULARITY */
-+ REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
-+ (t->tim[2] ? 1 : 0), 4, 4);
-+
-+ rfbi_print_timings();
-+ rfbi_enable_clocks(0);
-+}
-+
-+static int ps_to_rfbi_ticks(int time, int div)
-+{
-+ unsigned long tick_ps;
-+ int ret;
-+
-+ /* Calculate in picosecs to yield more exact results */
-+ tick_ps = 1000000000 / (rfbi.l4_khz) * div;
-+
-+ ret = (time + tick_ps - 1) / tick_ps;
-+
-+ return ret;
-+}
-+
-+#ifdef OMAP_RFBI_RATE_LIMIT
-+unsigned long rfbi_get_max_tx_rate(void)
-+{
-+ unsigned long l4_rate, dss1_rate;
-+ int min_l4_ticks = 0;
-+ int i;
-+
-+ /* According to TI this can't be calculated so make the
-+ * adjustments for a couple of known frequencies and warn for
-+ * others.
-+ */
-+ static const struct {
-+ unsigned long l4_clk; /* HZ */
-+ unsigned long dss1_clk; /* HZ */
-+ unsigned long min_l4_ticks;
-+ } ftab[] = {
-+ { 55, 132, 7, }, /* 7.86 MPix/s */
-+ { 110, 110, 12, }, /* 9.16 MPix/s */
-+ { 110, 132, 10, }, /* 11 Mpix/s */
-+ { 120, 120, 10, }, /* 12 Mpix/s */
-+ { 133, 133, 10, }, /* 13.3 Mpix/s */
-+ };
-+
-+ l4_rate = rfbi.l4_khz / 1000;
-+ dss1_rate = clk_get_rate(rfbi.dss1_fck) / 1000000;
-+
-+ for (i = 0; i < ARRAY_SIZE(ftab); i++) {
-+ /* Use a window instead of an exact match, to account
-+ * for different DPLL multiplier / divider pairs.
-+ */
-+ if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
-+ abs(ftab[i].dss1_clk - dss1_rate) < 3) {
-+ min_l4_ticks = ftab[i].min_l4_ticks;
-+ break;
-+ }
-+ }
-+ if (i == ARRAY_SIZE(ftab)) {
-+ /* Can't be sure, return anyway the maximum not
-+ * rate-limited. This might cause a problem only for the
-+ * tearing synchronisation.
-+ */
-+ DSSERR("can't determine maximum RFBI transfer rate\n");
-+ return rfbi.l4_khz * 1000;
-+ }
-+ return rfbi.l4_khz * 1000 / min_l4_ticks;
-+}
-+#else
-+int rfbi_get_max_tx_rate(void)
-+{
-+ return rfbi.l4_khz * 1000;
-+}
-+#endif
-+
-+static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
-+{
-+ *clk_period = 1000000000 / rfbi.l4_khz;
-+ *max_clk_div = 2;
-+}
-+
-+static int rfbi_convert_timings(struct rfbi_timings *t)
-+{
-+ u32 l;
-+ int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
-+ int actim, recyc, wecyc;
-+ int div = t->clk_div;
-+
-+ if (div <= 0 || div > 2)
-+ return -1;
-+
-+ /* Make sure that after conversion it still holds that:
-+ * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
-+ * csoff > cson, csoff >= max(weoff, reoff), actim > reon
-+ */
-+ weon = ps_to_rfbi_ticks(t->we_on_time, div);
-+ weoff = ps_to_rfbi_ticks(t->we_off_time, div);
-+ if (weoff <= weon)
-+ weoff = weon + 1;
-+ if (weon > 0x0f)
-+ return -1;
-+ if (weoff > 0x3f)
-+ return -1;
-+
-+ reon = ps_to_rfbi_ticks(t->re_on_time, div);
-+ reoff = ps_to_rfbi_ticks(t->re_off_time, div);
-+ if (reoff <= reon)
-+ reoff = reon + 1;
-+ if (reon > 0x0f)
-+ return -1;
-+ if (reoff > 0x3f)
-+ return -1;
-+
-+ cson = ps_to_rfbi_ticks(t->cs_on_time, div);
-+ csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
-+ if (csoff <= cson)
-+ csoff = cson + 1;
-+ if (csoff < max(weoff, reoff))
-+ csoff = max(weoff, reoff);
-+ if (cson > 0x0f)
-+ return -1;
-+ if (csoff > 0x3f)
-+ return -1;
-+
-+ l = cson;
-+ l |= csoff << 4;
-+ l |= weon << 10;
-+ l |= weoff << 14;
-+ l |= reon << 20;
-+ l |= reoff << 24;
-+
-+ t->tim[0] = l;
-+
-+ actim = ps_to_rfbi_ticks(t->access_time, div);
-+ if (actim <= reon)
-+ actim = reon + 1;
-+ if (actim > 0x3f)
-+ return -1;
-+
-+ wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
-+ if (wecyc < weoff)
-+ wecyc = weoff;
-+ if (wecyc > 0x3f)
-+ return -1;
-+
-+ recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
-+ if (recyc < reoff)
-+ recyc = reoff;
-+ if (recyc > 0x3f)
-+ return -1;
-+
-+ cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
-+ if (cs_pulse > 0x3f)
-+ return -1;
-+
-+ l = wecyc;
-+ l |= recyc << 6;
-+ l |= cs_pulse << 12;
-+ l |= actim << 22;
-+
-+ t->tim[1] = l;
-+
-+ t->tim[2] = div - 1;
-+
-+ t->converted = 1;
-+
-+ return 0;
-+}
-+
-+/* xxx FIX module selection missing */
-+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
-+ unsigned hs_pulse_time, unsigned vs_pulse_time,
-+ int hs_pol_inv, int vs_pol_inv, int extif_div)
-+{
-+ int hs, vs;
-+ int min;
-+ u32 l;
-+
-+ hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
-+ vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
-+ if (hs < 2)
-+ return -EDOM;
-+ if (mode == OMAP_DSS_RFBI_TE_MODE_2)
-+ min = 2;
-+ else /* OMAP_DSS_RFBI_TE_MODE_1 */
-+ min = 4;
-+ if (vs < min)
-+ return -EDOM;
-+ if (vs == hs)
-+ return -EINVAL;
-+ rfbi.te_mode = mode;
-+ DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
-+ mode, hs, vs, hs_pol_inv, vs_pol_inv);
-+
-+ rfbi_enable_clocks(1);
-+ rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
-+ rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
-+
-+ l = rfbi_read_reg(RFBI_CONFIG(0));
-+ if (hs_pol_inv)
-+ l &= ~(1 << 21);
-+ else
-+ l |= 1 << 21;
-+ if (vs_pol_inv)
-+ l &= ~(1 << 20);
-+ else
-+ l |= 1 << 20;
-+ rfbi_enable_clocks(0);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(omap_rfbi_setup_te);
-+
-+/* xxx FIX module selection missing */
-+int omap_rfbi_enable_te(int enable, unsigned line)
-+{
-+ u32 l;
-+
-+ DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
-+ if (line > (1 << 11) - 1)
-+ return -EINVAL;
-+
-+ rfbi_enable_clocks(1);
-+ l = rfbi_read_reg(RFBI_CONFIG(0));
-+ l &= ~(0x3 << 2);
-+ if (enable) {
-+ rfbi.te_enabled = 1;
-+ l |= rfbi.te_mode << 2;
-+ } else
-+ rfbi.te_enabled = 0;
-+ rfbi_write_reg(RFBI_CONFIG(0), l);
-+ rfbi_write_reg(RFBI_LINE_NUMBER, line);
-+ rfbi_enable_clocks(0);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(omap_rfbi_enable_te);
-+
-+#if 0
-+static void rfbi_enable_config(int enable1, int enable2)
-+{
-+ u32 l;
-+ int cs = 0;
-+
-+ if (enable1)
-+ cs |= 1<<0;
-+ if (enable2)
-+ cs |= 1<<1;
-+
-+ rfbi_enable_clocks(1);
-+
-+ l = rfbi_read_reg(RFBI_CONTROL);
-+
-+ l = FLD_MOD(l, cs, 3, 2);
-+ l = FLD_MOD(l, 0, 1, 1);
-+
-+ rfbi_write_reg(RFBI_CONTROL, l);
-+
-+
-+ l = rfbi_read_reg(RFBI_CONFIG(0));
-+ l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
-+ /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
-+ /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
-+
-+ l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
-+ l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
-+ l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
-+
-+ l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
-+ rfbi_write_reg(RFBI_CONFIG(0), l);
-+
-+ rfbi_enable_clocks(0);
-+}
-+#endif
-+
-+int rfbi_configure(int rfbi_module, int bpp, int lines)
-+{
-+ u32 l;
-+ int cycle1 = 0, cycle2 = 0, cycle3 = 0;
-+ enum omap_rfbi_cycleformat cycleformat;
-+ enum omap_rfbi_datatype datatype;
-+ enum omap_rfbi_parallelmode parallelmode;
-+
-+ switch (bpp) {
-+ case 12:
-+ datatype = OMAP_DSS_RFBI_DATATYPE_12;
-+ break;
-+ case 16:
-+ datatype = OMAP_DSS_RFBI_DATATYPE_16;
-+ break;
-+ case 18:
-+ datatype = OMAP_DSS_RFBI_DATATYPE_18;
-+ break;
-+ case 24:
-+ datatype = OMAP_DSS_RFBI_DATATYPE_24;
-+ break;
-+ default:
-+ BUG();
-+ return 1;
-+ }
-+ rfbi.datatype = datatype;
-+
-+ switch (lines) {
-+ case 8:
-+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
-+ break;
-+ case 9:
-+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
-+ break;
-+ case 12:
-+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
-+ break;
-+ case 16:
-+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
-+ break;
-+ default:
-+ BUG();
-+ return 1;
-+ }
-+ rfbi.parallelmode = parallelmode;
-+
-+ if ((bpp % lines) == 0) {
-+ switch (bpp / lines) {
-+ case 1:
-+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
-+ break;
-+ case 2:
-+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
-+ break;
-+ case 3:
-+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
-+ break;
-+ default:
-+ BUG();
-+ return 1;
-+ }
-+ } else if ((2 * bpp % lines) == 0) {
-+ if ((2 * bpp / lines) == 3)
-+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
-+ else {
-+ BUG();
-+ return 1;
-+ }
-+ } else {
-+ BUG();
-+ return 1;
-+ }
-+
-+ switch (cycleformat) {
-+ case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
-+ cycle1 = lines;
-+ break;
-+
-+ case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
-+ cycle1 = lines;
-+ cycle2 = lines;
-+ break;
-+
-+ case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
-+ cycle1 = lines;
-+ cycle2 = lines;
-+ cycle3 = lines;
-+ break;
-+
-+ case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
-+ cycle1 = lines;
-+ cycle2 = (lines / 2) | ((lines / 2) << 16);
-+ cycle3 = (lines << 16);
-+ break;
-+ }
-+
-+ rfbi_enable_clocks(1);
-+
-+ REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
-+
-+ l = 0;
-+ l |= FLD_VAL(parallelmode, 1, 0);
-+ l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */
-+ l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */
-+ l |= FLD_VAL(datatype, 6, 5);
-+ /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
-+ l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */
-+ l |= FLD_VAL(cycleformat, 10, 9);
-+ l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */
-+ l |= FLD_VAL(0, 16, 16); /* A0POLARITY */
-+ l |= FLD_VAL(0, 17, 17); /* REPOLARITY */
-+ l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */
-+ l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */
-+ l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */
-+ l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */
-+ rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
-+
-+ rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
-+ rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
-+ rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
-+
-+
-+ l = rfbi_read_reg(RFBI_CONTROL);
-+ l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
-+ l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
-+ rfbi_write_reg(RFBI_CONTROL, l);
-+
-+
-+ DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
-+ bpp, lines, cycle1, cycle2, cycle3);
-+
-+ rfbi_enable_clocks(0);
-+
-+ return 0;
-+}
-+
-+static int rfbi_find_display(struct omap_display *disp)
-+{
-+ if (disp == rfbi.display[0])
-+ return 0;
-+
-+ if (disp == rfbi.display[1])
-+ return 1;
-+
-+ BUG();
-+ return -1;
-+}
-+
-+
-+static void signal_fifo_waiters(void)
-+{
-+ if (atomic_read(&rfbi.cmd_fifo_full) > 0) {
-+ /* DSSDBG("SIGNALING: Fifo not full for waiter!\n"); */
-+ complete(&rfbi.cmd_done);
-+ atomic_dec(&rfbi.cmd_fifo_full);
-+ }
-+}
-+
-+/* returns 1 for async op, and 0 for sync op */
-+static int do_update(struct omap_display *display, struct update_region *upd)
-+{
-+ int x = upd->x;
-+ int y = upd->y;
-+ int w = upd->w;
-+ int h = upd->h;
-+
-+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
-+ /*display->ctrl->enable_te(display, 1); */
-+
-+ dispc_setup_partial_planes(display, &x, &y, &w, &h);
-+
-+ display->ctrl->setup_update(display, x, y, w, h);
-+
-+ rfbi_transfer_area(w, h, NULL, NULL);
-+
-+ return 1;
-+ } else {
-+ struct omap_overlay *ovl;
-+ void *addr;
-+ int scr_width;
-+#ifdef MEASURE_PERF
-+ ktime_t t1, t2;
-+#endif
-+ ovl = &display->manager->overlays[0];
-+ scr_width = ovl->info.screen_width;
-+ addr = ovl->info.vaddr;
-+
-+ display->ctrl->setup_update(display, x, y, w, h);
-+
-+#ifdef MEASURE_PERF
-+ t1 = ktime_get();
-+#endif
-+ omap_rfbi_write_pixels(addr, scr_width,
-+ x, y, w, h);
-+#ifdef MEASURE_PERF
-+ t2 = ktime_get();
-+ t1 = ktime_sub(t2, t1);
-+ DSSDBG("L4 FRAMEDONE in %lld ns\n",
-+ ktime_to_ns(t1));
-+#endif
-+ return 0;
-+ }
-+}
-+
-+static void process_cmd_fifo(void)
-+{
-+ int len;
-+ struct update_param p;
-+ struct omap_display *display;
-+ unsigned long flags;
-+
-+ if (atomic_inc_return(&rfbi.cmd_pending) != 1)
-+ return;
-+
-+ while (true) {
-+ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
-+
-+ len = __kfifo_get(rfbi.cmd_fifo, (unsigned char *)&p,
-+ sizeof(struct update_param));
-+ if (len == 0) {
-+ DSSDBG("nothing more in fifo\n");
-+ atomic_set(&rfbi.cmd_pending, 0);
-+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
-+ break;
-+ }
-+
-+ /* DSSDBG("fifo full %d\n", rfbi.cmd_fifo_full.counter);*/
-+
-+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
-+
-+ BUG_ON(len != sizeof(struct update_param));
-+ BUG_ON(p.rfbi_module > 1);
-+
-+ display = rfbi.display[p.rfbi_module];
-+
-+ if (p.cmd == RFBI_CMD_UPDATE) {
-+ if (do_update(display, &p.par.r))
-+ break; /* async op */
-+ } else if (p.cmd == RFBI_CMD_SYNC) {
-+ DSSDBG("Signaling SYNC done!\n");
-+ complete(p.par.sync);
-+ } else
-+ BUG();
-+ }
-+
-+ signal_fifo_waiters();
-+}
-+
-+static void rfbi_push_cmd(struct update_param *p)
-+{
-+ int ret;
-+
-+ while (1) {
-+ unsigned long flags;
-+ int available;
-+
-+ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
-+ available = RFBI_CMD_FIFO_LEN_BYTES -
-+ __kfifo_len(rfbi.cmd_fifo);
-+
-+/* DSSDBG("%d bytes left in fifo\n", available); */
-+ if (available < sizeof(struct update_param)) {
-+ DSSDBG("Going to wait because FIFO FULL..\n");
-+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
-+ atomic_inc(&rfbi.cmd_fifo_full);
-+ wait_for_completion(&rfbi.cmd_done);
-+ /*DSSDBG("Woke up because fifo not full anymore\n");*/
-+ continue;
-+ }
-+
-+ ret = __kfifo_put(rfbi.cmd_fifo, (unsigned char *)p,
-+ sizeof(struct update_param));
-+/* DSSDBG("pushed %d bytes\n", ret);*/
-+
-+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
-+
-+ BUG_ON(ret != sizeof(struct update_param));
-+
-+ break;
-+ }
-+}
-+
-+static void rfbi_push_update(int rfbi_module, int x, int y, int w, int h)
-+{
-+ struct update_param p;
-+
-+ p.rfbi_module = rfbi_module;
-+ p.cmd = RFBI_CMD_UPDATE;
-+
-+ p.par.r.x = x;
-+ p.par.r.y = y;
-+ p.par.r.w = w;
-+ p.par.r.h = h;
-+
-+ DSSDBG("RFBI pushed %d,%d %dx%d\n", x, y, w, h);
-+
-+ rfbi_push_cmd(&p);
-+
-+ process_cmd_fifo();
-+}
-+
-+static void rfbi_push_sync(int rfbi_module, struct completion *sync_comp)
-+{
-+ struct update_param p;
-+
-+ p.rfbi_module = rfbi_module;
-+ p.cmd = RFBI_CMD_SYNC;
-+ p.par.sync = sync_comp;
-+
-+ rfbi_push_cmd(&p);
-+
-+ DSSDBG("RFBI sync pushed to cmd fifo\n");
-+
-+ process_cmd_fifo();
-+}
-+
-+int rfbi_init(void)
-+{
-+ u32 rev;
-+ u32 l;
-+
-+ spin_lock_init(&rfbi.cmd_lock);
-+ rfbi.cmd_fifo = kfifo_alloc(RFBI_CMD_FIFO_LEN_BYTES, GFP_KERNEL,
-+ &rfbi.cmd_lock);
-+ if (IS_ERR(rfbi.cmd_fifo))
-+ return -ENOMEM;
-+
-+ init_completion(&rfbi.cmd_done);
-+ atomic_set(&rfbi.cmd_fifo_full, 0);
-+ atomic_set(&rfbi.cmd_pending, 0);
-+
-+ rfbi.base = ioremap(RFBI_BASE, SZ_256);
-+ if (!rfbi.base) {
-+ DSSERR("can't ioremap RFBI\n");
-+ return -ENOMEM;
-+ }
-+
-+ rfbi.dss_ick = get_dss_ick();
-+ rfbi.dss1_fck = get_dss1_fck();
-+
-+ rfbi_enable_clocks(1);
-+
-+ msleep(10);
-+
-+ rfbi.l4_khz = clk_get_rate(rfbi.dss_ick) / 1000;
-+
-+ /* Enable autoidle and smart-idle */
-+ l = rfbi_read_reg(RFBI_SYSCONFIG);
-+ l |= (1 << 0) | (2 << 3);
-+ rfbi_write_reg(RFBI_SYSCONFIG, l);
-+
-+ rev = rfbi_read_reg(RFBI_REVISION);
-+ printk(KERN_INFO "OMAP RFBI rev %d.%d\n",
-+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
-+
-+ rfbi_enable_clocks(0);
-+
-+ return 0;
-+}
-+
-+void rfbi_exit(void)
-+{
-+ DSSDBG("rfbi_exit\n");
-+
-+ kfifo_free(rfbi.cmd_fifo);
-+
-+ iounmap(rfbi.base);
-+}
-+
-+/* struct omap_display support */
-+static void rfbi_display_set_mode(struct omap_display *display,
-+ int x_res, int y_res, int bpp)
-+{
-+ display->bpp = bpp;
-+
-+ dispc_set_tft_data_lines(display->bpp);
-+
-+ if (rfbi_configure(display->hw_config.u.rfbi.channel,
-+ display->bpp,
-+ display->hw_config.u.rfbi.data_lines) != 0) {
-+ DSSERR("can't configure rfbi\n");
-+ }
-+
-+ display->ctrl->set_mode(display, x_res, y_res, bpp);
-+}
-+
-+
-+static int rfbi_display_update(struct omap_display *display,
-+ int x, int y, int w, int h)
-+{
-+ int rfbi_module;
-+
-+ if (w == 0 || h == 0)
-+ return 0;
-+
-+ rfbi_module = rfbi_find_display(display);
-+
-+ rfbi_push_update(rfbi_module, x, y, w, h);
-+
-+ return 0;
-+}
-+
-+static int rfbi_display_sync(struct omap_display *display)
-+{
-+ struct completion sync_comp;
-+ int rfbi_module;
-+
-+ rfbi_module = rfbi_find_display(display);
-+
-+ init_completion(&sync_comp);
-+ rfbi_push_sync(rfbi_module, &sync_comp);
-+ DSSDBG("Waiting for SYNC to happen...\n");
-+ wait_for_completion(&sync_comp);
-+ DSSDBG("Released from SYNC\n");
-+ return 0;
-+}
-+
-+static int rfbi_display_enable_te(struct omap_display *display, int enable)
-+{
-+ display->ctrl->enable_te(display, enable);
-+ return 0;
-+}
-+
-+static int rfbi_display_enable(struct omap_display *display)
-+{
-+ int r;
-+
-+ BUG_ON(display->panel == NULL || display->ctrl == NULL);
-+
-+ r = omap_dispc_register_isr(framedone_callback, NULL,
-+ DISPC_IRQ_FRAMEDONE);
-+ if (r) {
-+ DSSERR("can't get FRAMEDONE irq\n");
-+ return r;
-+ }
-+
-+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
-+
-+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI);
-+
-+ /* FIX select 16bpp as default */
-+ rfbi_configure(display->hw_config.u.rfbi.channel,
-+ 16,
-+ display->hw_config.u.rfbi.data_lines);
-+
-+ rfbi_set_timings(display->hw_config.u.rfbi.channel,
-+ &display->ctrl->timings);
-+
-+ display->ctrl->enable(display);
-+
-+ return 0;
-+}
-+
-+static void rfbi_display_disable(struct omap_display *display)
-+{
-+ display->ctrl->disable(display);
-+ omap_dispc_unregister_isr(framedone_callback);
-+}
-+
-+void rfbi_init_display(struct omap_display *display)
-+{
-+ display->enable = rfbi_display_enable;
-+ display->disable = rfbi_display_disable;
-+ display->set_mode = rfbi_display_set_mode;
-+ display->update = rfbi_display_update;
-+ display->sync = rfbi_display_sync;
-+ display->enable_te = rfbi_display_enable_te;
-+
-+ rfbi.display[display->hw_config.u.rfbi.channel] = display;
-+
-+ display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
-+}
---
-1.5.6.3
-
diff --git a/packages/linux/linux-omap/0009-DSS-Add-generic-DVI-panel.patch b/packages/linux/linux-omap/0006-DSS-Add-generic-DVI-panel.patch
index 26a7999abe..790cada121 100644
--- a/packages/linux/linux-omap/0009-DSS-Add-generic-DVI-panel.patch
+++ b/packages/linux/linux-omap/0006-DSS-Add-generic-DVI-panel.patch
@@ -1,6 +1,6 @@
-From e62e58fbb6adfb288da56c949bdb6211c695a263 Mon Sep 17 00:00:00 2001
+From 36e83ecf4db86b61cec3bc9817d658d3ef218967 Mon Sep 17 00:00:00 2001
From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Mon, 20 Oct 2008 13:12:33 +0300
+Date: Tue, 11 Nov 2008 13:52:56 +0200
Subject: [PATCH] DSS: Add generic DVI panel
For some reason we can't allocate enough mem for 1280x1024x24bpp, even if
@@ -8,20 +8,18 @@ there should be enough continuous mem. So 1280x1024 mode defaults to
16bpp for now.
You also need DSI PLL to generate pix clock for 1280x1024.
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
---
- drivers/video/omap2/Kconfig | 20 +++++++
+ drivers/video/omap2/Kconfig | 23 ++++++
drivers/video/omap2/Makefile | 2 +
- drivers/video/omap2/panel-dvi.c | 121 +++++++++++++++++++++++++++++++++++++++
- 3 files changed, 143 insertions(+), 0 deletions(-)
+ drivers/video/omap2/panel-dvi.c | 150 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 175 insertions(+), 0 deletions(-)
create mode 100644 drivers/video/omap2/panel-dvi.c
diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
-index 4b72479..4584e1b 100644
+index 4b72479..996f047 100644
--- a/drivers/video/omap2/Kconfig
+++ b/drivers/video/omap2/Kconfig
-@@ -24,6 +24,26 @@ config FB_OMAP2_FORCE_AUTO_UPDATE
+@@ -24,6 +24,29 @@ config FB_OMAP2_FORCE_AUTO_UPDATE
menu "OMAP2/3 Display Device Drivers"
depends on OMAP2_DSS
@@ -35,6 +33,9 @@ index 4b72479..4584e1b 100644
+ depends on PANEL_DVI
+ default PANEL_DVI_HIGHRES
+
++config PANEL_DVI_LOWLOWRES
++ bool "640 x 480 @ 60"
++
+config PANEL_DVI_LOWRES
+ bool "800 x 600 @ 60"
+
@@ -59,10 +60,10 @@ index 51c2e00..7c75340 100644
+obj-$(CONFIG_PANEL_DVI) += panel-dvi.o
diff --git a/drivers/video/omap2/panel-dvi.c b/drivers/video/omap2/panel-dvi.c
new file mode 100644
-index 0000000..2d053df
+index 0000000..541f588
--- /dev/null
+++ b/drivers/video/omap2/panel-dvi.c
-@@ -0,0 +1,121 @@
+@@ -0,0 +1,150 @@
+/*
+ * DVI panel support
+ *
@@ -108,6 +109,17 @@ index 0000000..2d053df
+ display->hw_config.panel_disable(display);
+}
+
++static int dvi_panel_suspend(struct omap_display *display)
++{
++ dvi_panel_disable(display);
++ return 0;
++}
++
++static int dvi_panel_resume(struct omap_display *display)
++{
++ return dvi_panel_enable(display);
++}
++
+static struct omap_panel dvi_panel = {
+ .owner = THIS_MODULE,
+ .name = "panel-dvi",
@@ -115,11 +127,29 @@ index 0000000..2d053df
+ /*.remove = dvi_cleanup, */
+ .enable = dvi_panel_enable,
+ .disable = dvi_panel_disable,
++ .suspend = dvi_panel_suspend,
++ .resume = dvi_panel_resume,
+ /*.set_mode = dvi_set_mode, */
+
-+#if defined(CONFIG_PANEL_DVI_LOWRES)
++#if defined(CONFIG_PANEL_DVI_LOWLOWRES)
++ .timings = {
++ /* 640 x 480 @ 60 hz reduced blanking vesa
++ * (dunno if these are correct) */
++ .pixel_clock = 23500,
++ .hfp = 48,
++ .hsw = 32,
++ .hbp = 80,
++ .vfp = 3,
++ .vsw = 4,
++ .vbp = 11,
++ },
++
++ .x_res = 640,
++ .y_res = 480,
++ .bpp = 24,
++#elif defined(CONFIG_PANEL_DVI_LOWRES)
+ .timings = {
-+ /* 800 x 600 @ 60 Hz Reduced blanking VESA CVT 0.48M3-R */
++ /* 800 x 600 @ 60 hz reduced blanking vesa cvt 0.48m3-r */
+ .pixel_clock = 35500,
+ .hfp = 48,
+ .hsw = 32,
diff --git a/packages/linux/linux-omap/0006-DSS-TV-out-support-for-OMAP2-3-DSS.patch b/packages/linux/linux-omap/0006-DSS-TV-out-support-for-OMAP2-3-DSS.patch
deleted file mode 100644
index 0a28867e98..0000000000
--- a/packages/linux/linux-omap/0006-DSS-TV-out-support-for-OMAP2-3-DSS.patch
+++ /dev/null
@@ -1,519 +0,0 @@
-From fc7030b395c21d051de16719751efc75e954c590 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Tue, 4 Nov 2008 16:53:54 +0200
-Subject: [PATCH] DSS: TV-out support for OMAP2/3 DSS
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- arch/arm/plat-omap/dss/venc.c | 499 +++++++++++++++++++++++++++++++++++++++++
- 1 files changed, 499 insertions(+), 0 deletions(-)
- create mode 100644 arch/arm/plat-omap/dss/venc.c
-
-diff --git a/arch/arm/plat-omap/dss/venc.c b/arch/arm/plat-omap/dss/venc.c
-new file mode 100644
-index 0000000..a9739ad
---- /dev/null
-+++ b/arch/arm/plat-omap/dss/venc.c
-@@ -0,0 +1,499 @@
-+/*
-+ * linux/arch/arm/plat-omap/dss/venc.c
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * VENC settings from TI's DSS driver
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "VENC"
-+
-+#include <linux/kernel.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+
-+#include <linux/semaphore.h>
-+#include <mach/board.h>
-+#include <mach/gpio.h>
-+#include <mach/display.h>
-+#include <mach/cpu.h>
-+
-+#include "dss.h"
-+
-+#define VENC_BASE 0x48050C00
-+
-+/* Venc registers */
-+#define VENC_REV_ID 0x00
-+#define VENC_STATUS 0x04
-+#define VENC_F_CONTROL 0x08
-+#define VENC_VIDOUT_CTRL 0x10
-+#define VENC_SYNC_CTRL 0x14
-+#define VENC_LLEN 0x1C
-+#define VENC_FLENS 0x20
-+#define VENC_HFLTR_CTRL 0x24
-+#define VENC_CC_CARR_WSS_CARR 0x28
-+#define VENC_C_PHASE 0x2C
-+#define VENC_GAIN_U 0x30
-+#define VENC_GAIN_V 0x34
-+#define VENC_GAIN_Y 0x38
-+#define VENC_BLACK_LEVEL 0x3C
-+#define VENC_BLANK_LEVEL 0x40
-+#define VENC_X_COLOR 0x44
-+#define VENC_M_CONTROL 0x48
-+#define VENC_BSTAMP_WSS_DATA 0x4C
-+#define VENC_S_CARR 0x50
-+#define VENC_LINE21 0x54
-+#define VENC_LN_SEL 0x58
-+#define VENC_L21__WC_CTL 0x5C
-+#define VENC_HTRIGGER_VTRIGGER 0x60
-+#define VENC_SAVID__EAVID 0x64
-+#define VENC_FLEN__FAL 0x68
-+#define VENC_LAL__PHASE_RESET 0x6C
-+#define VENC_HS_INT_START_STOP_X 0x70
-+#define VENC_HS_EXT_START_STOP_X 0x74
-+#define VENC_VS_INT_START_X 0x78
-+#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
-+#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
-+#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
-+#define VENC_VS_EXT_STOP_Y 0x88
-+#define VENC_AVID_START_STOP_X 0x90
-+#define VENC_AVID_START_STOP_Y 0x94
-+#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
-+#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
-+#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
-+#define VENC_TVDETGP_INT_START_STOP_X 0xB0
-+#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
-+#define VENC_GEN_CTRL 0xB8
-+#define VENC_OUTPUT_CONTROL 0xC4
-+#define VENC_DAC_B__DAC_C 0xC8
-+
-+static DECLARE_MUTEX(venc_lock);
-+
-+struct venc_config {
-+ u32 f_control;
-+ u32 vidout_ctrl;
-+ u32 sync_ctrl;
-+ u32 llen;
-+ u32 flens;
-+ u32 hfltr_ctrl;
-+ u32 cc_carr_wss_carr;
-+ u32 c_phase;
-+ u32 gain_u;
-+ u32 gain_v;
-+ u32 gain_y;
-+ u32 black_level;
-+ u32 blank_level;
-+ u32 x_color;
-+ u32 m_control;
-+ u32 bstamp_wss_data;
-+ u32 s_carr;
-+ u32 line21;
-+ u32 ln_sel;
-+ u32 l21__wc_ctl;
-+ u32 htrigger_vtrigger;
-+ u32 savid__eavid;
-+ u32 flen__fal;
-+ u32 lal__phase_reset;
-+ u32 hs_int_start_stop_x;
-+ u32 hs_ext_start_stop_x;
-+ u32 vs_int_start_x;
-+ u32 vs_int_stop_x__vs_int_start_y;
-+ u32 vs_int_stop_y__vs_ext_start_x;
-+ u32 vs_ext_stop_x__vs_ext_start_y;
-+ u32 vs_ext_stop_y;
-+ u32 avid_start_stop_x;
-+ u32 avid_start_stop_y;
-+ u32 fid_int_start_x__fid_int_start_y;
-+ u32 fid_int_offset_y__fid_ext_start_x;
-+ u32 fid_ext_start_y__fid_ext_offset_y;
-+ u32 tvdetgp_int_start_stop_x;
-+ u32 tvdetgp_int_start_stop_y;
-+ u32 gen_ctrl;
-+
-+ int width;
-+ int height;
-+};
-+
-+/* from TRM */
-+static const struct venc_config venc_config_pal_trm = {
-+ .f_control = 0,
-+ .vidout_ctrl = 1,
-+ .sync_ctrl = 0x40,
-+ .llen = 0x35F, /* 863 */
-+ .flens = 0x270, /* 624 */
-+ .hfltr_ctrl = 0,
-+ .cc_carr_wss_carr = 0x2F7225ED,
-+ .c_phase = 0,
-+ .gain_u = 0x111,
-+ .gain_v = 0x181,
-+ .gain_y = 0x140,
-+ .black_level = 0x3B,
-+ .blank_level = 0x3B,
-+ .x_color = 0x7,
-+ .m_control = 0x2,
-+ .bstamp_wss_data = 0x3F,
-+ .s_carr = 0x2A098ACB,
-+ .line21 = 0,
-+ .ln_sel = 0x01290015,
-+ .l21__wc_ctl = 0x0000F603,
-+ .htrigger_vtrigger = 0,
-+
-+ .savid__eavid = 0x06A70108,
-+ .flen__fal = 0x00180270,
-+ .lal__phase_reset = 0x00180270,
-+ .hs_int_start_stop_x = 0x00880358,
-+ .hs_ext_start_stop_x = 0x000F035F,
-+ .vs_int_start_x = 0x01A70000,
-+ .vs_int_stop_x__vs_int_start_y = 0x000001A7,
-+ .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
-+ .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
-+ .vs_ext_stop_y = 0x00000025,
-+ .avid_start_stop_x = 0x03530083,
-+ .avid_start_stop_y = 0x026C002E,
-+ .fid_int_start_x__fid_int_start_y = 0x0001008A,
-+ .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
-+ .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
-+
-+ .tvdetgp_int_start_stop_x = 0x00140001,
-+ .tvdetgp_int_start_stop_y = 0x00010001,
-+ .gen_ctrl = 0x00FF0000,
-+
-+ .width = 720,
-+ .height = 574, /* for some reason, this isn't 576 */
-+};
-+
-+/* from TRM */
-+static const struct venc_config venc_config_ntsc_trm = {
-+ .f_control = 0,
-+ .vidout_ctrl = 1,
-+ .sync_ctrl = 0x8040,
-+ .llen = 0x359,
-+ .flens = 0x20C,
-+ .hfltr_ctrl = 0,
-+ .cc_carr_wss_carr = 0x043F2631,
-+ .c_phase = 0,
-+ .gain_u = 0x102,
-+ .gain_v = 0x16C,
-+ .gain_y = 0x12F,
-+ .black_level = 0x43,
-+ .blank_level = 0x38,
-+ .x_color = 0x7,
-+ .m_control = 0x1,
-+ .bstamp_wss_data = 0x38,
-+ .s_carr = 0x21F07C1F,
-+ .line21 = 0,
-+ .ln_sel = 0x01310011,
-+ .l21__wc_ctl = 0x0000F003,
-+ .htrigger_vtrigger = 0,
-+
-+ .savid__eavid = 0x069300F4,
-+ .flen__fal = 0x0016020C,
-+ .lal__phase_reset = 0x00060107,
-+ .hs_int_start_stop_x = 0x008E0350,
-+ .hs_ext_start_stop_x = 0x000F0359,
-+ .vs_int_start_x = 0x01A00000,
-+ .vs_int_stop_x__vs_int_start_y = 0x020701A0,
-+ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
-+ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
-+ .vs_ext_stop_y = 0x00000006,
-+ .avid_start_stop_x = 0x03480078,
-+ .avid_start_stop_y = 0x02060024,
-+ .fid_int_start_x__fid_int_start_y = 0x0001008A,
-+ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
-+ .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
-+
-+ .tvdetgp_int_start_stop_x = 0x00140001,
-+ .tvdetgp_int_start_stop_y = 0x00010001,
-+ .gen_ctrl = 0x00F90000,
-+
-+ .width = 720,
-+ .height = 482,
-+};
-+
-+static const struct venc_config venc_config_pal_bdghi = {
-+ .f_control = 0,
-+ .vidout_ctrl = 0,
-+ .sync_ctrl = 0,
-+ .hfltr_ctrl = 0,
-+ .x_color = 0,
-+ .line21 = 0,
-+ .ln_sel = 21,
-+ .htrigger_vtrigger = 0,
-+ .tvdetgp_int_start_stop_x = 0x00140001,
-+ .tvdetgp_int_start_stop_y = 0x00010001,
-+ .gen_ctrl = 0x00FB0000,
-+
-+ .llen = 864-1,
-+ .flens = 625-1,
-+ .cc_carr_wss_carr = 0x2F7625ED,
-+ .c_phase = 0xDF,
-+ .gain_u = 0x111,
-+ .gain_v = 0x181,
-+ .gain_y = 0x140,
-+ .black_level = 0x3e,
-+ .blank_level = 0x3e,
-+ .m_control = 0<<2 | 1<<1,
-+ .bstamp_wss_data = 0x42,
-+ .s_carr = 0x2a098acb,
-+ .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
-+ .savid__eavid = 0x06A70108,
-+ .flen__fal = 23<<16 | 624<<0,
-+ .lal__phase_reset = 2<<17 | 310<<0,
-+ .hs_int_start_stop_x = 0x00920358,
-+ .hs_ext_start_stop_x = 0x000F035F,
-+ .vs_int_start_x = 0x1a7<<16,
-+ .vs_int_stop_x__vs_int_start_y = 0x000601A7,
-+ .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
-+ .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
-+ .vs_ext_stop_y = 0x05,
-+ .avid_start_stop_x = 0x03530082,
-+ .avid_start_stop_y = 0x0270002E,
-+ .fid_int_start_x__fid_int_start_y = 0x0005008A,
-+ .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
-+ .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
-+
-+ .width = 720,
-+ .height = 576,
-+};
-+
-+static struct {
-+ void __iomem *base;
-+ struct clk *dss_54m_fck;
-+ struct clk *dss_96m_fck;
-+ struct clk *dss_ick;
-+ struct clk *dss1_fck;
-+ const struct venc_config *config;
-+} venc;
-+
-+static struct omap_panel venc_panel = {
-+ .name = "tv-out",
-+ .x_res = 0,
-+ .y_res = 0,
-+ .bpp = 24,
-+};
-+
-+static inline void venc_write_reg(int idx, u32 val)
-+{
-+ __raw_writel(val, venc.base + idx);
-+}
-+
-+static inline u32 venc_read_reg(int idx)
-+{
-+ u32 l = __raw_readl(venc.base + idx);
-+ return l;
-+}
-+
-+static void venc_write_config(const struct venc_config *config)
-+{
-+ DSSDBG("write venc conf\n");
-+
-+ venc_write_reg(VENC_LLEN, config->llen);
-+ venc_write_reg(VENC_FLENS, config->flens);
-+ venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
-+ venc_write_reg(VENC_C_PHASE, config->c_phase);
-+ venc_write_reg(VENC_GAIN_U, config->gain_u);
-+ venc_write_reg(VENC_GAIN_V, config->gain_v);
-+ venc_write_reg(VENC_GAIN_Y, config->gain_y);
-+ venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
-+ venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
-+ venc_write_reg(VENC_M_CONTROL, config->m_control);
-+ venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
-+ venc_write_reg(VENC_S_CARR, config->s_carr);
-+ venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
-+ venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
-+ venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
-+ venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
-+ venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
-+ venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
-+ venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
-+ venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
-+ config->vs_int_stop_x__vs_int_start_y);
-+ venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
-+ config->vs_int_stop_y__vs_ext_start_x);
-+ venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
-+ config->vs_ext_stop_x__vs_ext_start_y);
-+ venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
-+ venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
-+ venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
-+ venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
-+ config->fid_int_start_x__fid_int_start_y);
-+ venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
-+ config->fid_int_offset_y__fid_ext_start_x);
-+ venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
-+ config->fid_ext_start_y__fid_ext_offset_y);
-+
-+ venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
-+ venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
-+ venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
-+ venc_write_reg(VENC_X_COLOR, config->x_color);
-+ venc_write_reg(VENC_LINE21, config->line21);
-+ venc_write_reg(VENC_LN_SEL, config->ln_sel);
-+ venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
-+ venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
-+ config->tvdetgp_int_start_stop_x);
-+ venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
-+ config->tvdetgp_int_start_stop_y);
-+ venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
-+ venc_write_reg(VENC_F_CONTROL, config->f_control);
-+ venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
-+}
-+
-+static void venc_reset(void)
-+{
-+ int t = 1000;
-+
-+ venc_write_reg(VENC_F_CONTROL, venc_read_reg(VENC_F_CONTROL) | (1<<8));
-+ while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
-+ if (--t == 0) {
-+ DSSERR("Failed to reset venc\n");
-+ return;
-+ }
-+ }
-+}
-+
-+static void venc_enable_clocks(int enable)
-+{
-+ if (enable) {
-+ clk_enable(venc.dss_ick);
-+ clk_enable(venc.dss1_fck);
-+ clk_enable(venc.dss_54m_fck);
-+ clk_enable(venc.dss_96m_fck);
-+ } else {
-+ clk_disable(venc.dss_96m_fck);
-+ clk_disable(venc.dss_54m_fck);
-+ clk_disable(venc.dss1_fck);
-+ clk_disable(venc.dss_ick);
-+ }
-+}
-+
-+int venc_init(void)
-+{
-+ u8 rev_id;
-+ int use_pal = 1; /* XXX */
-+
-+ if (use_pal)
-+ venc.config = &venc_config_pal_trm;
-+ else
-+ venc.config = &venc_config_ntsc_trm;
-+
-+ venc_panel.x_res = venc.config->width;
-+ venc_panel.y_res = venc.config->height;
-+
-+ venc.base = ioremap(VENC_BASE, SZ_1K);
-+ if (!venc.base) {
-+ DSSERR("can't ioremap VENC\n");
-+ return -ENOMEM;
-+ }
-+
-+ venc.dss_ick = get_dss_ick();
-+ venc.dss1_fck = get_dss1_fck();
-+ venc.dss_54m_fck = get_tv_fck();
-+ venc.dss_96m_fck = get_96m_fck();
-+
-+ /* enable clocks */
-+ venc_enable_clocks(1);
-+
-+ /* configure venc */
-+ venc_reset();
-+ venc_write_config(venc.config);
-+
-+ rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
-+ printk(KERN_INFO "OMAP VENC rev %d\n", rev_id);
-+
-+ venc_enable_clocks(0);
-+
-+ return 0;
-+}
-+
-+void venc_exit(void)
-+{
-+ iounmap(venc.base);
-+}
-+
-+static int venc_enable_display(struct omap_display *display)
-+{
-+ DSSDBG("venc_enable_display\n");
-+
-+ down(&venc_lock);
-+
-+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
-+ up(&venc_lock);
-+ return -EINVAL;
-+ }
-+
-+ venc_enable_clocks(1);
-+
-+ dss_set_venc_output(display->hw_config.u.venc.type);
-+ dss_set_dac_pwrdn_bgz(1);
-+
-+ venc_write_config(venc.config);
-+
-+ if (display->hw_config.u.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) {
-+ if (cpu_is_omap24xx())
-+ venc_write_reg(VENC_OUTPUT_CONTROL, 0x2);
-+ else
-+ venc_write_reg(VENC_OUTPUT_CONTROL, 0xa);
-+ } else { /* S-Video */
-+ venc_write_reg(VENC_OUTPUT_CONTROL, 0xd);
-+ }
-+
-+ dispc_set_digit_size(venc.config->width, venc.config->height/2);
-+
-+ if (display->hw_config.panel_enable)
-+ display->hw_config.panel_enable(display);
-+
-+ dispc_enable_digit_out(1);
-+
-+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
-+
-+ up(&venc_lock);
-+
-+ return 0;
-+}
-+
-+static void venc_disable_display(struct omap_display *display)
-+{
-+ DSSDBG("venc_disable_display\n");
-+
-+ down(&venc_lock);
-+
-+ if (display->state == OMAP_DSS_DISPLAY_DISABLED) {
-+ up(&venc_lock);
-+ return;
-+ }
-+
-+ venc_write_reg(VENC_OUTPUT_CONTROL, 0);
-+ dss_set_dac_pwrdn_bgz(0);
-+
-+ dispc_enable_digit_out(0);
-+
-+ if (display->hw_config.panel_disable)
-+ display->hw_config.panel_disable(display);
-+
-+ venc_enable_clocks(0);
-+
-+ display->state = OMAP_DSS_DISPLAY_DISABLED;
-+
-+ up(&venc_lock);
-+}
-+
-+void venc_init_display(struct omap_display *display)
-+{
-+ display->panel = &venc_panel;
-+ display->enable = venc_enable_display;
-+ display->disable = venc_disable_display;
-+}
---
-1.5.6.3
-
diff --git a/packages/linux/linux-omap/0007-DSS-DSI-support-for-OMAP2-3-DSS.patch b/packages/linux/linux-omap/0007-DSS-DSI-support-for-OMAP2-3-DSS.patch
deleted file mode 100644
index e1c92b289a..0000000000
--- a/packages/linux/linux-omap/0007-DSS-DSI-support-for-OMAP2-3-DSS.patch
+++ /dev/null
@@ -1,3047 +0,0 @@
-From 421c7dc28a0b9b2ee0c8514045a8ee1af7b002de Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Tue, 4 Nov 2008 15:18:25 +0200
-Subject: [PATCH] DSS: DSI support for OMAP2/3 DSS
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- arch/arm/plat-omap/dss/dsi.c | 3027 ++++++++++++++++++++++++++++++++++++++++++
- 1 files changed, 3027 insertions(+), 0 deletions(-)
- create mode 100644 arch/arm/plat-omap/dss/dsi.c
-
-diff --git a/arch/arm/plat-omap/dss/dsi.c b/arch/arm/plat-omap/dss/dsi.c
-new file mode 100644
-index 0000000..47e5628
---- /dev/null
-+++ b/arch/arm/plat-omap/dss/dsi.c
-@@ -0,0 +1,3027 @@
-+/*
-+ * linux/arch/arm/plat-omap/dss/dsi.c
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "DSI"
-+
-+#include <linux/kernel.h>
-+#include <linux/io.h>
-+#include <linux/clk.h>
-+#include <linux/device.h>
-+#include <linux/err.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/workqueue.h>
-+#include <linux/mutex.h>
-+
-+#include <mach/board.h>
-+#include <mach/display.h>
-+
-+#include "dss.h"
-+
-+/*#define VERBOSE*/
-+/*#define VERBOSE_IRQ*/
-+/*#define MEASURE_PERF*/
-+
-+#define DSI_BASE 0x4804FC00
-+
-+struct dsi_reg { u16 idx; };
-+
-+#define DSI_REG(idx) ((const struct dsi_reg) { idx })
-+
-+/* DSI Protocol Engine */
-+
-+#define DSI_REVISION DSI_REG(0x0000)
-+#define DSI_SYSCONFIG DSI_REG(0x0010)
-+#define DSI_SYSSTATUS DSI_REG(0x0014)
-+#define DSI_IRQSTATUS DSI_REG(0x0018)
-+#define DSI_IRQENABLE DSI_REG(0x001C)
-+#define DSI_CTRL DSI_REG(0x0040)
-+#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
-+#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
-+#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
-+#define DSI_CLK_CTRL DSI_REG(0x0054)
-+#define DSI_TIMING1 DSI_REG(0x0058)
-+#define DSI_TIMING2 DSI_REG(0x005C)
-+#define DSI_VM_TIMING1 DSI_REG(0x0060)
-+#define DSI_VM_TIMING2 DSI_REG(0x0064)
-+#define DSI_VM_TIMING3 DSI_REG(0x0068)
-+#define DSI_CLK_TIMING DSI_REG(0x006C)
-+#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
-+#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
-+#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
-+#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
-+#define DSI_VM_TIMING4 DSI_REG(0x0080)
-+#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
-+#define DSI_VM_TIMING5 DSI_REG(0x0088)
-+#define DSI_VM_TIMING6 DSI_REG(0x008C)
-+#define DSI_VM_TIMING7 DSI_REG(0x0090)
-+#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
-+#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
-+#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
-+#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
-+#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
-+#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
-+#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
-+#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
-+
-+/* DSIPHY_SCP */
-+
-+#define DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
-+#define DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
-+#define DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
-+#define DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
-+
-+/* DSI_PLL_CTRL_SCP */
-+
-+#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
-+#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
-+#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
-+#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
-+#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
-+
-+#define REG_GET(idx, start, end) \
-+ FLD_GET(dsi_read_reg(idx), start, end)
-+
-+#define REG_FLD_MOD(idx, val, start, end) \
-+ dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
-+
-+/* Global interrupts */
-+#define DSI_IRQ_VC0 (1 << 0)
-+#define DSI_IRQ_VC1 (1 << 1)
-+#define DSI_IRQ_VC2 (1 << 2)
-+#define DSI_IRQ_VC3 (1 << 3)
-+#define DSI_IRQ_WAKEUP (1 << 4)
-+#define DSI_IRQ_RESYNC (1 << 5)
-+#define DSI_IRQ_PLL_LOCK (1 << 7)
-+#define DSI_IRQ_PLL_UNLOCK (1 << 8)
-+#define DSI_IRQ_PLL_RECALL (1 << 9)
-+#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
-+#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
-+#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
-+#define DSI_IRQ_TE_TRIGGER (1 << 16)
-+#define DSI_IRQ_ACK_TRIGGER (1 << 17)
-+#define DSI_IRQ_SYNC_LOST (1 << 18)
-+#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
-+#define DSI_IRQ_TA_TIMEOUT (1 << 20)
-+#define DSI_IRQ_ERROR_MASK \
-+ (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
-+ DSI_IRQ_TA_TIMEOUT)
-+#define DSI_IRQ_CHANNEL_MASK 0xf
-+
-+/* Virtual channel interrupts */
-+#define DSI_VC_IRQ_CS (1 << 0)
-+#define DSI_VC_IRQ_ECC_CORR (1 << 1)
-+#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
-+#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
-+#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
-+#define DSI_VC_IRQ_BTA (1 << 5)
-+#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
-+#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
-+#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
-+#define DSI_VC_IRQ_ERROR_MASK \
-+ (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
-+ DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
-+ DSI_VC_IRQ_FIFO_TX_UDF)
-+
-+/* ComplexIO interrupts */
-+#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
-+#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
-+#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
-+#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
-+#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
-+#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
-+#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
-+#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
-+#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
-+#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
-+#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
-+#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
-+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
-+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
-+
-+#define DSI_DT_DCS_SHORT_WRITE_0 0x05
-+#define DSI_DT_DCS_SHORT_WRITE_1 0x15
-+#define DSI_DT_DCS_READ 0x06
-+#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
-+#define DSI_DT_NULL_PACKET 0x09
-+#define DSI_DT_DCS_LONG_WRITE 0x39
-+
-+#define DSI_DT_RX_ACK_WITH_ERR 0x02
-+#define DSI_DT_RX_DCS_LONG_READ 0x1c
-+#define DSI_DT_RX_SHORT_READ_1 0x21
-+#define DSI_DT_RX_SHORT_READ_2 0x22
-+
-+#define FINT_MAX 2100000
-+#define FINT_MIN 750000
-+#define REGN_MAX (1 << 7)
-+#define REGM_MAX ((1 << 11) - 1)
-+#define REGM3_MAX (1 << 4)
-+#define REGM4_MAX (1 << 4)
-+
-+enum fifo_size {
-+ DSI_FIFO_SIZE_0 = 0,
-+ DSI_FIFO_SIZE_32 = 1,
-+ DSI_FIFO_SIZE_64 = 2,
-+ DSI_FIFO_SIZE_96 = 3,
-+ DSI_FIFO_SIZE_128 = 4,
-+};
-+
-+static struct
-+{
-+ void __iomem *base;
-+
-+ struct clk *dss_ick;
-+ struct clk *dss1_fck;
-+ struct clk *dss2_fck;
-+
-+ unsigned long dsi1_pll_fclk; /* Hz */
-+ unsigned long dsi2_pll_fclk; /* Hz */
-+ unsigned long dsiphy; /* Hz */
-+ unsigned long ddr_clk; /* Hz */
-+
-+ struct {
-+ enum fifo_size fifo_size;
-+ int dest_per; /* destination peripheral 0-3 */
-+ } vc[4];
-+
-+ struct mutex lock;
-+
-+ struct completion bta_completion;
-+
-+ spinlock_t update_lock;
-+ int update_ongoing;
-+ int update_syncers;
-+ struct completion update_completion;
-+ struct work_struct framedone_work;
-+
-+ enum omap_dss_update_mode update_mode;
-+ int use_te;
-+ int framedone_scheduled; /* helps to catch strange framedone bugs */
-+
-+ struct {
-+ struct omap_display *display;
-+ int x, y, w, h;
-+ int bytespp;
-+ } update_region;
-+
-+#ifdef MEASURE_PERF
-+ ktime_t measure_time;
-+ int measure_frames;
-+#endif
-+} dsi;
-+
-+
-+static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
-+{
-+ __raw_writel(val, dsi.base + idx.idx);
-+}
-+
-+static inline u32 dsi_read_reg(const struct dsi_reg idx)
-+{
-+ return __raw_readl(dsi.base + idx.idx);
-+}
-+
-+static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
-+ int value)
-+{
-+ int t = 1000;
-+
-+ while (REG_GET(idx, bitnum, bitnum) != value) {
-+ if (--t == 0)
-+ return !value;
-+ }
-+
-+ return value;
-+}
-+
-+
-+#ifdef MEASURE_PERF
-+static void start_measuring(void)
-+{
-+ dsi.measure_time = ktime_get();
-+}
-+
-+static void end_measuring(const char *name)
-+{
-+ ktime_t t;
-+ u32 total_bytes;
-+ u32 us;
-+ const int numframes = 100;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
-+ return;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
-+ dsi.measure_frames++;
-+ if (dsi.measure_frames < numframes)
-+ return;
-+ dsi.measure_frames = 0;
-+ }
-+
-+ t = ktime_get();
-+ t = ktime_sub(t, dsi.measure_time);
-+ us = (u32)ktime_to_us(t);
-+ if (us == 0)
-+ us = 1;
-+
-+ total_bytes = dsi.update_region.w *
-+ dsi.update_region.h *
-+ dsi.update_region.bytespp;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
-+ DSSINFO("%s update: %d frames in %u us, %u frames/sec\n",
-+ name, numframes,
-+ us,
-+ 1000*1000 / us);
-+ } else {
-+ DSSINFO("%s update in %u us (%u Hz), %u bytes, %u kbytes/sec\n",
-+ name,
-+ us,
-+ 1000*1000 / us,
-+ total_bytes,
-+ total_bytes * 1000 / us);
-+ }
-+}
-+#else
-+#define start_measuring()
-+#define end_measuring(x)
-+#endif
-+
-+
-+
-+
-+static void print_irq_status(u32 status)
-+{
-+#ifndef VERBOSE_IRQ
-+ if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
-+ return;
-+#endif
-+ printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
-+
-+#define PIS(x) \
-+ if (status & DSI_IRQ_##x) \
-+ printk(#x " ");
-+#ifdef VERBOSE_IRQ
-+ PIS(VC0);
-+ PIS(VC1);
-+ PIS(VC2);
-+ PIS(VC3);
-+#endif
-+ PIS(WAKEUP);
-+ PIS(RESYNC);
-+ PIS(PLL_LOCK);
-+ PIS(PLL_UNLOCK);
-+ PIS(PLL_RECALL);
-+ PIS(COMPLEXIO_ERR);
-+ PIS(HS_TX_TIMEOUT);
-+ PIS(LP_RX_TIMEOUT);
-+ PIS(TE_TRIGGER);
-+ PIS(ACK_TRIGGER);
-+ PIS(SYNC_LOST);
-+ PIS(LDO_POWER_GOOD);
-+ PIS(TA_TIMEOUT);
-+#undef PIS
-+
-+ printk("\n");
-+}
-+
-+static void print_irq_status_vc(int channel, u32 status)
-+{
-+#ifndef VERBOSE_IRQ
-+ if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
-+ return;
-+#endif
-+ printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
-+
-+#define PIS(x) \
-+ if (status & DSI_VC_IRQ_##x) \
-+ printk(#x " ");
-+ PIS(CS);
-+ PIS(ECC_CORR);
-+#ifdef VERBOSE_IRQ
-+ PIS(PACKET_SENT);
-+#endif
-+ PIS(FIFO_TX_OVF);
-+ PIS(FIFO_RX_OVF);
-+ PIS(BTA);
-+ PIS(ECC_NO_CORR);
-+ PIS(FIFO_TX_UDF);
-+ PIS(PP_BUSY_CHANGE);
-+#undef PIS
-+ printk("\n");
-+}
-+
-+static void print_irq_status_cio(u32 status)
-+{
-+ printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
-+
-+#define PIS(x) \
-+ if (status & DSI_CIO_IRQ_##x) \
-+ printk(#x " ");
-+ PIS(ERRSYNCESC1);
-+ PIS(ERRSYNCESC2);
-+ PIS(ERRSYNCESC3);
-+ PIS(ERRESC1);
-+ PIS(ERRESC2);
-+ PIS(ERRESC3);
-+ PIS(ERRCONTROL1);
-+ PIS(ERRCONTROL2);
-+ PIS(ERRCONTROL3);
-+ PIS(STATEULPS1);
-+ PIS(STATEULPS2);
-+ PIS(STATEULPS3);
-+ PIS(ERRCONTENTIONLP0_1);
-+ PIS(ERRCONTENTIONLP1_1);
-+ PIS(ERRCONTENTIONLP0_2);
-+ PIS(ERRCONTENTIONLP1_2);
-+ PIS(ERRCONTENTIONLP0_3);
-+ PIS(ERRCONTENTIONLP1_3);
-+ PIS(ULPSACTIVENOT_ALL0);
-+ PIS(ULPSACTIVENOT_ALL1);
-+#undef PIS
-+
-+ printk("\n");
-+}
-+
-+static int debug_irq;
-+
-+/* called from dss */
-+void dsi_irq_handler(void)
-+{
-+ u32 irqstatus, vcstatus, ciostatus;
-+ int i;
-+
-+ irqstatus = dsi_read_reg(DSI_IRQSTATUS);
-+
-+ if (irqstatus & DSI_IRQ_ERROR_MASK) {
-+ DSSERR("DSI error, irqstatus %x\n", irqstatus);
-+ print_irq_status(irqstatus);
-+ } else if (debug_irq) {
-+ print_irq_status(irqstatus);
-+ }
-+
-+ for (i = 0; i < 4; ++i) {
-+ if ((irqstatus & (1<<i)) == 0)
-+ continue;
-+
-+ vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
-+
-+ if (vcstatus & DSI_VC_IRQ_BTA)
-+ complete(&dsi.bta_completion);
-+
-+ if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
-+ DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
-+ i, vcstatus);
-+ print_irq_status_vc(i, vcstatus);
-+ } else if (debug_irq) {
-+ print_irq_status_vc(i, vcstatus);
-+ }
-+
-+ dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
-+ }
-+
-+ if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
-+ ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
-+
-+ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
-+
-+ DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
-+ print_irq_status_cio(ciostatus);
-+ }
-+
-+ dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
-+}
-+
-+
-+static void _dsi_initialize_irq(void)
-+{
-+ u32 l;
-+ int i;
-+
-+ /* disable all interrupts */
-+ dsi_write_reg(DSI_IRQENABLE, 0);
-+ for (i = 0; i < 4; ++i)
-+ dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
-+ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
-+
-+ /* clear interrupt status */
-+ l = dsi_read_reg(DSI_IRQSTATUS);
-+ dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
-+
-+ for (i = 0; i < 4; ++i) {
-+ l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
-+ dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
-+ }
-+
-+ l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
-+ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
-+
-+ /* enable error irqs */
-+ l = DSI_IRQ_ERROR_MASK;
-+ dsi_write_reg(DSI_IRQENABLE, l);
-+
-+ l = DSI_VC_IRQ_ERROR_MASK;
-+ for (i = 0; i < 4; ++i)
-+ dsi_write_reg(DSI_VC_IRQENABLE(i), l);
-+
-+ /* XXX zonda responds incorrectly, causing control error:
-+ Exit from LP-ESC mode to LP11 uses wrong transition states on the
-+ data lines LP0 and LN0. */
-+ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
-+ -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
-+}
-+
-+static void dsi_vc_enable_bta_irq(int channel)
-+{
-+ u32 l;
-+
-+ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
-+ l |= DSI_VC_IRQ_BTA;
-+ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
-+}
-+
-+static void dsi_vc_disable_bta_irq(int channel)
-+{
-+ u32 l;
-+
-+ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
-+ l &= ~DSI_VC_IRQ_BTA;
-+ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
-+}
-+
-+/* DSI func clock. this could also be DSI2_PLL_FCLK */
-+static inline void enable_clocks(int enable)
-+{
-+ if (enable) {
-+ clk_enable(dsi.dss_ick);
-+ clk_enable(dsi.dss1_fck);
-+ } else {
-+ clk_disable(dsi.dss1_fck);
-+ clk_disable(dsi.dss_ick);
-+ }
-+}
-+
-+/* source clock for DSI PLL. this could also be PCLKFREE */
-+static inline void dsi_enable_pll_clock(int enable)
-+{
-+ if (enable)
-+ clk_enable(dsi.dss2_fck);
-+ else
-+ clk_disable(dsi.dss2_fck);
-+}
-+
-+#if 1
-+
-+#ifdef DEBUG
-+static void _dsi_print_reset_status(void)
-+{
-+ u32 l;
-+
-+ /* A dummy read using the SCP interface to any DSIPHY register is
-+ * required after DSIPHY reset to complete the reset of the DSI complex
-+ * I/O. */
-+ l = dsi_read_reg(DSIPHY_CFG5);
-+
-+ printk(KERN_DEBUG "DSI resets: ");
-+
-+ l = dsi_read_reg(DSI_PLL_STATUS);
-+ printk("PLL (%d) ", FLD_GET(l, 0, 0));
-+
-+ l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
-+ printk("CIO (%d) ", FLD_GET(l, 29, 29));
-+
-+ l = dsi_read_reg(DSIPHY_CFG5);
-+ printk("PHY (%x, %d, %d, %d)\n",
-+ FLD_GET(l, 28, 26),
-+ FLD_GET(l, 29, 29),
-+ FLD_GET(l, 30, 30),
-+ FLD_GET(l, 31, 31));
-+}
-+#else
-+#define _dsi_print_reset_status()
-+#endif
-+
-+static int _dsi_reset(void)
-+{
-+ int r = 0;
-+
-+ /* Soft reset */
-+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
-+
-+ if (wait_for_bit_change(DSI_SYSSTATUS, 0, 1) != 1) {
-+ DSSERR("soft reset failed\n");
-+ r = -ENODEV;
-+ }
-+
-+ /* A dummy read using the SCP interface to any DSIPHY register is
-+ * required after DSIPHY reset to complete the reset of the DSI complex
-+ * I/O. */
-+ dsi_read_reg(DSIPHY_CFG5);
-+
-+ _dsi_print_reset_status();
-+
-+ return r;
-+}
-+#endif
-+
-+static inline int dsi_if_enable(int enable)
-+{
-+ DSSDBG("dsi_if_enable(%d)\n", enable);
-+
-+ enable = enable ? 1 : 0;
-+ REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
-+
-+ if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
-+ DSSERR("Failed to set dsi_if_enable to %d\n", enable);
-+ return -EIO;
-+ }
-+
-+ return 0;
-+}
-+
-+static unsigned long dsi_fclk_rate(void)
-+{
-+ unsigned long r;
-+
-+ if (dss_get_dsi_clk_source() == 0) {
-+ /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
-+ r = clk_get_rate(dsi.dss1_fck);
-+ } else {
-+ /* DSI FCLK source is DSI2_PLL_FCLK */
-+ r = dsi.dsi2_pll_fclk;
-+ }
-+
-+ return r;
-+}
-+
-+static int dsi_set_lp_clk_divisor(void)
-+{
-+ int n;
-+ unsigned long dsi_fclk;
-+ unsigned long mhz;
-+
-+ /* LP_CLK_DIVISOR, DSI fclk/n, should be 20MHz - 32kHz */
-+
-+ dsi_fclk = dsi_fclk_rate();
-+
-+ for (n = 1; n < (1 << 13) - 1; ++n) {
-+ mhz = dsi_fclk / n;
-+ if (mhz <= 20*1000*1000)
-+ break;
-+ }
-+
-+ if (n == (1 << 13) - 1) {
-+ DSSERR("DSI: Failed to find LP_CLK_DIVISOR\n");
-+ return -EINVAL;
-+ }
-+
-+ DSSDBG("LP_CLK_DIV %d, LP_CLK %ld\n", n, mhz);
-+
-+ REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0); /* LP_CLK_DIVISOR */
-+ if (dsi_fclk > 30*1000*1000)
-+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */
-+
-+ return 0;
-+}
-+
-+
-+enum dsi_pll_power_state {
-+ DSI_PLL_POWER_OFF = 0x0,
-+ DSI_PLL_POWER_ON_HSCLK = 0x1,
-+ DSI_PLL_POWER_ON_ALL = 0x2,
-+ DSI_PLL_POWER_ON_DIV = 0x3,
-+};
-+
-+static int dsi_pll_power(enum dsi_pll_power_state state)
-+{
-+ int t = 0;
-+
-+ REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
-+
-+ /* PLL_PWR_STATUS */
-+ while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
-+ udelay(1);
-+ if (t++ > 1000) {
-+ DSSERR("DSI: Failed to set DSI PLL power mode to %d\n",
-+ state);
-+ return -ENODEV;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+/* return 1 for exact match */
-+static int iterate_dispc_divs(int is_tft, unsigned long pck,
-+ struct dsi_clock_info *cur, struct dsi_clock_info *best)
-+{
-+ int pcd_min = is_tft ? 2 : 3;
-+
-+ for (cur->lck_div = 1; cur->lck_div <= 255; ++cur->lck_div) {
-+ unsigned long lck = cur->dispc_fck / cur->lck_div;
-+
-+ for (cur->pck_div = pcd_min; cur->pck_div <= 255;
-+ ++cur->pck_div) {
-+
-+ cur->pck = lck / cur->pck_div;
-+
-+ if (abs(cur->pck - pck) < abs(best->pck - pck)) {
-+ *best = *cur;
-+ /*
-+ DSSDBG("best match fck %ld, pck %ld, regn %d, "
-+ "regm %d, regm3 %d, ld %d, pd %d\n",
-+ best->dispc_fck,
-+ best->pck,
-+ best->regn, best->regm,
-+ best->regm3,
-+ best->lck_div, best->pck_div);
-+ */
-+ }
-+
-+ if (cur->pck == pck)
-+ return 1;
-+
-+ if (cur->pck < pck)
-+ break;
-+ }
-+
-+ if (lck / pcd_min < cur->pck)
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+int dsi_pll_calc_pck(int is_tft, unsigned long pck,
-+ struct dsi_clock_info *cinfo)
-+{
-+ struct dsi_clock_info cur, best;
-+
-+ DSSDBG("dsi_pll_calc\n");
-+
-+ memset(&best, 0, sizeof(best));
-+
-+ memset(&cur, 0, sizeof(cur));
-+ cur.clkin = clk_get_rate(dsi.dss2_fck);
-+ cur.use_dss2_fck = 1;
-+ cur.highfreq = 0;
-+
-+ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
-+ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
-+ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
-+ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
-+ if (cur.highfreq == 0)
-+ cur.fint = cur.clkin / cur.regn;
-+ else
-+ cur.fint = cur.clkin / (2 * cur.regn);
-+
-+ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
-+ continue;
-+
-+ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
-+ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
-+ unsigned long a, b;
-+
-+ a = 2 * cur.regm * (cur.clkin/1000);
-+ b = cur.regn * (cur.highfreq + 1);
-+ cur.dsiphy = a / b * 1000;
-+
-+ if (cur.dsiphy > 1800 * 1000 * 1000)
-+ break;
-+
-+ /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
-+ for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
-+ ++cur.regm3) {
-+ int r;
-+
-+ cur.dispc_fck = cur.dsiphy / cur.regm3;
-+
-+ /* this will narrow down the search a bit,
-+ * but still give pixclocks below what was
-+ * requested */
-+ if (cur.dispc_fck < pck)
-+ break;
-+
-+ if (cur.dispc_fck > DISPC_MAX_FCK)
-+ continue;
-+
-+#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
-+ if (cur.dispc_fck <
-+ pck * CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK)
-+ continue;
-+#endif
-+ r = iterate_dispc_divs(is_tft, pck,
-+ &cur, &best);
-+ if (r == 1)
-+ goto found;
-+
-+ }
-+ }
-+ }
-+found:
-+
-+ /* DSI2_PLL_FCLK(MHz) = DSIPHY(MHz) / regm4 < 173MHz */
-+ /* hardcoded 48MHz for now. what should it be? */
-+ best.regm4 = best.dsiphy / (48000000);
-+ if (best.regm4 > REGM4_MAX)
-+ best.regm4 = REGM4_MAX;
-+ best.dsi_fck = best.dsiphy / best.regm4;
-+
-+ *cinfo = best;
-+
-+ return 0;
-+}
-+
-+static int dsi_pll_calc_datafreq(unsigned long datafreq,
-+ struct dsi_clock_info *cinfo)
-+{
-+ struct dsi_clock_info cur, best;
-+ const int use_dss2_fck = 1;
-+
-+ DSSDBG("dsi_pll_calc_datarate\n");
-+
-+ memset(&best, 0, sizeof(best));
-+
-+ memset(&cur, 0, sizeof(cur));
-+ cur.use_dss2_fck = use_dss2_fck;
-+ if (use_dss2_fck) {
-+ cur.clkin = clk_get_rate(dsi.dss2_fck);
-+ cur.highfreq = 0;
-+ } else {
-+ cur.clkin = dispc_pclk_rate();
-+ if (cur.clkin < 32000000)
-+ cur.highfreq = 0;
-+ else
-+ cur.highfreq = 1;
-+ }
-+
-+ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
-+ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
-+ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
-+ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
-+ if (cur.highfreq == 0)
-+ cur.fint = cur.clkin / cur.regn;
-+ else
-+ cur.fint = cur.clkin / (2 * cur.regn);
-+
-+ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
-+ continue;
-+
-+ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
-+ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
-+ unsigned long a, b;
-+
-+ a = 2 * cur.regm * (cur.clkin/1000);
-+ b = cur.regn * (cur.highfreq + 1);
-+ cur.dsiphy = a / b * 1000;
-+
-+ if (cur.dsiphy > 1800 * 1000 * 1000)
-+ break;
-+
-+ if (abs(cur.dsiphy - datafreq) <
-+ abs(best.dsiphy - datafreq)) {
-+ best = cur;
-+ /* DSSDBG("best %ld\n", best.dsiphy); */
-+ }
-+
-+ if (cur.dsiphy == datafreq)
-+ goto found;
-+ }
-+ }
-+found:
-+ /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
-+ /* hardcoded 48MHz for now. what should it be? */
-+ best.regm3 = best.dsiphy / (48000000);
-+ if (best.regm3 > REGM3_MAX)
-+ best.regm3 = REGM3_MAX;
-+ best.dispc_fck = best.dsiphy / best.regm3;
-+
-+ /* DSI2_PLL_FCLK(MHz) = DSIPHY(MHz) / regm4 < 173MHz */
-+ /* hardcoded 48MHz for now. what should it be? */
-+ best.regm4 = best.dsiphy / (48000000);
-+ if (best.regm4 > REGM4_MAX)
-+ best.regm4 = REGM4_MAX;
-+ best.dsi_fck = best.dsiphy / best.regm4;
-+
-+ *cinfo = best;
-+
-+ return 0;
-+}
-+
-+int dsi_pll_program(struct dsi_clock_info *cinfo)
-+{
-+ int r = 0;
-+ u32 l;
-+
-+ DSSDBG("dsi_pll_program\n");
-+
-+ enable_clocks(1);
-+
-+ dsi.dsiphy = cinfo->dsiphy;
-+ dsi.ddr_clk = dsi.dsiphy / 4;
-+ dsi.dsi1_pll_fclk = cinfo->dispc_fck;
-+ dsi.dsi2_pll_fclk = cinfo->dsi_fck;
-+
-+ DSSDBG("DSI Fint %ld\n", cinfo->fint);
-+
-+ DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
-+ cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
-+ cinfo->clkin,
-+ cinfo->highfreq);
-+
-+ /* DSIPHY == CLKIN4DDR */
-+ DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n",
-+ cinfo->regm,
-+ cinfo->regn,
-+ cinfo->clkin,
-+ cinfo->highfreq + 1,
-+ cinfo->dsiphy);
-+
-+ DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
-+ dsi.dsiphy / 1000 / 1000 / 2);
-+
-+ DSSDBG("Clock lane freq %ld Hz\n", dsi.ddr_clk);
-+
-+ DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
-+ cinfo->regm3, cinfo->dispc_fck);
-+ DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
-+ cinfo->regm4, cinfo->dsi_fck);
-+
-+ REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
-+
-+ l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
-+ l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
-+ l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
-+ l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
-+ l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19); /* DSI_CLOCK_DIV */
-+ l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23); /* DSIPROTO_CLOCK_DIV */
-+ dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
-+
-+ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
-+ l = FLD_MOD(l, 7, 4, 1); /* DSI_PLL_FREQSEL */
-+ /* DSI_PLL_CLKSEL */
-+ l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11);
-+ l = FLD_MOD(l, cinfo->highfreq, 12, 12); /* DSI_PLL_HIGHFREQ */
-+ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
-+ l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
-+ l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
-+ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
-+
-+ REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
-+
-+ if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
-+ DSSERR("dsi pll go bit not going down.\n");
-+ r = -EIO;
-+ goto err;
-+ }
-+
-+ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
-+ DSSERR("DSI: cannot lock PLL\n");
-+ r = -EIO;
-+ goto err;
-+ }
-+
-+ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
-+ l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
-+ l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
-+ l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
-+ l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
-+ l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
-+ l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
-+ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
-+ l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
-+ l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
-+ l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
-+ l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
-+ l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
-+ l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
-+ l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
-+ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
-+
-+ DSSDBG("PLL config done\n");
-+err:
-+ enable_clocks(0);
-+
-+ return r;
-+}
-+
-+int dsi_pll_init(int enable_hsclk, int enable_hsdiv)
-+{
-+ int r = 0;
-+ int fck_div, lck_div, pck_div;
-+ unsigned long fck;
-+ enum dsi_pll_power_state pwstate;
-+
-+ DSSDBG("PLL init\n");
-+
-+ enable_clocks(1);
-+ dsi_enable_pll_clock(1);
-+
-+ /* configure dispc fck and pixel clock to something sane */
-+ fck = dispc_calc_clock_div(1, 48 * 1000 * 1000,
-+ &fck_div, &lck_div, &pck_div);
-+ if (fck == 0)
-+ return -EINVAL;
-+
-+ dispc_set_clock_div(fck_div, lck_div, pck_div);
-+
-+ /* PLL does not come out of reset without this... */
-+ dispc_pck_free_enable(1);
-+
-+ if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
-+ DSSERR("DSI: PLL not coming out of reset.\n");
-+ r = -ENODEV;
-+ goto err;
-+ }
-+
-+ /* ... but if left on, we get problems when planes do not
-+ * fill the whole display. No idea about this XXX */
-+ dispc_pck_free_enable(0);
-+
-+ if (enable_hsclk && enable_hsdiv)
-+ pwstate = DSI_PLL_POWER_ON_ALL;
-+ else if (enable_hsclk)
-+ pwstate = DSI_PLL_POWER_ON_HSCLK;
-+ else if (enable_hsdiv)
-+ pwstate = DSI_PLL_POWER_ON_DIV;
-+ else
-+ pwstate = DSI_PLL_POWER_OFF;
-+
-+ r = dsi_pll_power(pwstate);
-+
-+ if (r)
-+ goto err;
-+
-+ enable_clocks(0);
-+
-+ DSSDBG("PLL init done\n");
-+
-+ return 0;
-+err:
-+ enable_clocks(0);
-+ dsi_enable_pll_clock(0);
-+ return r;
-+}
-+
-+void dsi_pll_uninit(void)
-+{
-+ dsi_pll_power(DSI_PLL_POWER_OFF);
-+ dsi_enable_pll_clock(0);
-+ DSSDBG("PLL uninit done\n");
-+}
-+
-+unsigned long dsi_get_dsi1_pll_rate(void)
-+{
-+ return dsi.dsi1_pll_fclk;
-+}
-+
-+unsigned long dsi_get_dsi2_pll_rate(void)
-+{
-+ return dsi.dsi2_pll_fclk;
-+}
-+
-+ssize_t dsi_print_clocks(char *buf, ssize_t size)
-+{
-+ ssize_t l = 0;
-+ int clksel;
-+
-+ enable_clocks(1);
-+
-+ clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
-+
-+ l += snprintf(buf + l, size - l, "- dsi -\n");
-+
-+ l += snprintf(buf + l, size - l, "dsi fclk source = %s\n",
-+ dss_get_dsi_clk_source() == 0 ?
-+ "dss1_alwon_fclk" : "dsi2_pll_fclk");
-+
-+ l += snprintf(buf + l, size - l, "dsi pll source = %s\n",
-+ clksel == 0 ?
-+ "dss2_alwon_fclk" : "pclkfree");
-+
-+ l += snprintf(buf + l, size - l,
-+ "DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n",
-+ dsi.dsiphy, dsi.ddr_clk);
-+
-+ l += snprintf(buf + l, size - l,
-+ "dsi1_pll_fck\t%lu (%s)\n"
-+ "dsi2_pll_fck\t%lu (%s)\n",
-+ dsi.dsi1_pll_fclk,
-+ dss_get_dispc_clk_source() == 0 ? "off" : "on",
-+ dsi.dsi2_pll_fclk,
-+ dss_get_dsi_clk_source() == 0 ? "off" : "on");
-+
-+ enable_clocks(0);
-+
-+ return l;
-+}
-+
-+
-+enum dsi_complexio_power_state {
-+ DSI_COMPLEXIO_POWER_OFF = 0x0,
-+ DSI_COMPLEXIO_POWER_ON = 0x1,
-+ DSI_COMPLEXIO_POWER_ULPS = 0x2,
-+};
-+
-+static int dsi_complexio_power(enum dsi_complexio_power_state state)
-+{
-+ int t = 0;
-+
-+ /* PWR_CMD */
-+ REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
-+
-+ /* PWR_STATUS */
-+ while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
-+ udelay(1);
-+ if (t++ > 1000) {
-+ DSSERR("DSI: failed to set complexio power state to "
-+ "%d\n", state);
-+ return -ENODEV;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void dsi_complexio_config(struct omap_display *display)
-+{
-+ u32 r;
-+
-+ int clk_lane = display->hw_config.u.dsi.clk_lane;
-+ int data1_lane = display->hw_config.u.dsi.data1_lane;
-+ int data2_lane = display->hw_config.u.dsi.data2_lane;
-+ int clk_pol = display->hw_config.u.dsi.clk_pol;
-+ int data1_pol = display->hw_config.u.dsi.data1_pol;
-+ int data2_pol = display->hw_config.u.dsi.data2_pol;
-+
-+ r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
-+ r = FLD_MOD(r, clk_lane, 2, 0);
-+ r = FLD_MOD(r, clk_pol, 3, 3);
-+ r = FLD_MOD(r, data1_lane, 6, 4);
-+ r = FLD_MOD(r, data1_pol, 7, 7);
-+ r = FLD_MOD(r, data2_lane, 10, 8);
-+ r = FLD_MOD(r, data2_pol, 11, 11);
-+ dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
-+
-+ /* The configuration of the DSI complex I/O (number of data lanes,
-+ position, differential order) should not be changed while
-+ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
-+ the hardware to take into account a new configuration of the complex
-+ I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
-+ follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
-+ then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
-+ DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
-+ DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
-+ DSI complex I/O configuration is unknown. */
-+
-+ /*
-+ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
-+ REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
-+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
-+ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
-+ */
-+}
-+
-+static inline int ns2ddr(int ns)
-+{
-+ /* convert time in ns to ddr ticks, rounding up */
-+ return (ns * (dsi.ddr_clk/1000/1000) + 999) / 1000;
-+}
-+
-+static void dsi_complexio_timings(void)
-+{
-+ u32 r;
-+ u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
-+ u32 tlpx_half, tclk_trail, tclk_zero;
-+ u32 tclk_prepare;
-+
-+ /* calculate timings */
-+
-+ /* 1 * DDR_CLK = 2 * UI */
-+
-+ /* min 40ns + 4*UI max 85ns + 6*UI */
-+ ths_prepare = ns2ddr(59) + 2;
-+
-+ /* min 145ns + 10*UI */
-+ ths_prepare_ths_zero = ns2ddr(145) + 5;
-+
-+ /* min max(8*UI, 60ns+4*UI) */
-+ ths_trail = max(4, ns2ddr(60) + 2);
-+
-+ /* min 100ns */
-+ ths_exit = ns2ddr(100);
-+
-+ /* tlpx min 50n */
-+ tlpx_half = ns2ddr(25);
-+
-+ /* min 60ns */
-+ tclk_trail = ns2ddr(60);
-+
-+ /* min 38ns, max 95ns */
-+ tclk_prepare = ns2ddr(38);
-+
-+ /* min tclk-prepare + tclk-zero = 300ns */
-+ tclk_zero = ns2ddr(300 - 38);
-+
-+#ifdef VERBOSE
-+ DSSDBG("ths_prepare %d, ths_prepare_ths_zero %d\n",
-+ ths_prepare, ths_prepare_ths_zero);
-+ DSSDBG("ths_trail %d, ths_exit %d\n", ths_trail, ths_exit);
-+
-+
-+ DSSDBG("tlpx_half %d, tclk_trail %d, tclk_zero %d\n", tlpx_half,
-+ tclk_trail, tclk_zero);
-+ DSSDBG("tclk_prepare %d\n", tclk_prepare);
-+#endif
-+
-+ /* program timings */
-+
-+ r = dsi_read_reg(DSIPHY_CFG0);
-+ r = FLD_MOD(r, ths_prepare, 31, 24);
-+ r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
-+ r = FLD_MOD(r, ths_trail, 15, 8);
-+ r = FLD_MOD(r, ths_exit, 7, 0);
-+ dsi_write_reg(DSIPHY_CFG0, r);
-+
-+ r = dsi_read_reg(DSIPHY_CFG1);
-+ r = FLD_MOD(r, tlpx_half, 22, 16);
-+ r = FLD_MOD(r, tclk_trail, 15, 8);
-+ r = FLD_MOD(r, tclk_zero, 7, 0);
-+ dsi_write_reg(DSIPHY_CFG1, r);
-+
-+ r = dsi_read_reg(DSIPHY_CFG2);
-+ r = FLD_MOD(r, tclk_prepare, 7, 0);
-+ dsi_write_reg(DSIPHY_CFG2, r);
-+}
-+
-+
-+static int dsi_complexio_init(struct omap_display *display)
-+{
-+ int r = 0;
-+
-+ DSSDBG("dsi_complexio_init\n");
-+
-+ /* CIO_CLK_ICG, enable L3 clk to CIO */
-+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
-+
-+ if (wait_for_bit_change(DSIPHY_CFG5, 30, 1) != 1) {
-+ DSSERR("DSI: ComplexIO PHY not coming out of reset.\n");
-+ r = -ENODEV;
-+ goto err;
-+ }
-+
-+ dsi_complexio_config(display);
-+
-+ r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
-+
-+ if (r)
-+ goto err;
-+
-+ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
-+ DSSERR("DSI: ComplexIO not coming out of reset.\n");
-+ r = -ENODEV;
-+ goto err;
-+ }
-+
-+ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
-+ DSSERR("DSI: ComplexIO LDO power down.\n");
-+ r = -ENODEV;
-+ goto err;
-+ }
-+
-+ dsi_complexio_timings();
-+
-+ /*
-+ The configuration of the DSI complex I/O (number of data lanes,
-+ position, differential order) should not be changed while
-+ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
-+ hardware to recognize a new configuration of the complex I/O (done
-+ in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
-+ this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
-+ reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
-+ LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
-+ bit to 1. If the sequence is not followed, the DSi complex I/O
-+ configuration is undetermined.
-+ */
-+ dsi_if_enable(1);
-+ dsi_if_enable(0);
-+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
-+ dsi_if_enable(1);
-+ dsi_if_enable(0);
-+
-+ DSSDBG("CIO init done\n");
-+err:
-+ return r;
-+}
-+
-+static void dsi_complexio_uninit(void)
-+{
-+ dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
-+}
-+
-+
-+
-+static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
-+ enum fifo_size size3, enum fifo_size size4)
-+{
-+ u32 r = 0;
-+ int add = 0;
-+ int i;
-+
-+ dsi.vc[0].fifo_size = size1;
-+ dsi.vc[1].fifo_size = size2;
-+ dsi.vc[2].fifo_size = size3;
-+ dsi.vc[3].fifo_size = size4;
-+
-+ for (i = 0; i < 4; i++) {
-+ u8 v;
-+ int size = dsi.vc[i].fifo_size;
-+
-+ if (add + size > 4) {
-+ DSSERR("DSI: Illegal FIFO configuration\n");
-+ BUG();
-+ }
-+
-+ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
-+ r |= v << (8 * i);
-+ /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
-+ add += size;
-+ }
-+
-+ dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
-+}
-+
-+static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
-+ enum fifo_size size3, enum fifo_size size4)
-+{
-+ u32 r = 0;
-+ int add = 0;
-+ int i;
-+
-+ dsi.vc[0].fifo_size = size1;
-+ dsi.vc[1].fifo_size = size2;
-+ dsi.vc[2].fifo_size = size3;
-+ dsi.vc[3].fifo_size = size4;
-+
-+ for (i = 0; i < 4; i++) {
-+ u8 v;
-+ int size = dsi.vc[i].fifo_size;
-+
-+ if (add + size > 4) {
-+ DSSERR("DSI: Illegal FIFO configuration\n");
-+ BUG();
-+ }
-+
-+ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
-+ r |= v << (8 * i);
-+ /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
-+ add += size;
-+ }
-+
-+ dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
-+}
-+
-+static int dsi_force_tx_stop_mode_io(void)
-+{
-+ u32 r;
-+
-+ r = dsi_read_reg(DSI_TIMING1);
-+ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
-+ dsi_write_reg(DSI_TIMING1, r);
-+
-+ if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
-+ DSSERR("TX_STOP bit not going down\n");
-+ return -EIO;
-+ }
-+
-+ return 0;
-+}
-+
-+static void dsi_vc_print_status(int channel)
-+{
-+ u32 r;
-+
-+ r = dsi_read_reg(DSI_VC_CTRL(channel));
-+ DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
-+ "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
-+ channel,
-+ FLD_GET(r, 5, 5),
-+ FLD_GET(r, 6, 6),
-+ FLD_GET(r, 15, 15),
-+ FLD_GET(r, 16, 16),
-+ FLD_GET(r, 20, 20));
-+
-+ r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
-+ DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
-+}
-+
-+static void dsi_vc_config(int channel)
-+{
-+ u32 r;
-+
-+ DSSDBG("dsi_vc_config %d\n", channel);
-+
-+ r = dsi_read_reg(DSI_VC_CTRL(channel));
-+
-+ r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
-+ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
-+ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
-+ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
-+ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
-+ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
-+ r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
-+
-+ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
-+ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
-+
-+ dsi_write_reg(DSI_VC_CTRL(channel), r);
-+}
-+
-+static void dsi_vc_config_vp(int channel)
-+{
-+ u32 r;
-+
-+ DSSDBG("dsi_vc_config_vp\n");
-+
-+ r = dsi_read_reg(DSI_VC_CTRL(channel));
-+
-+ r = FLD_MOD(r, 1, 1, 1); /* SOURCE, 1 = video port */
-+ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
-+ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
-+ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
-+ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
-+ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
-+ r = FLD_MOD(r, 1, 9, 9); /* MODE_SPEED, high speed on/off */
-+
-+ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
-+ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
-+
-+ dsi_write_reg(DSI_VC_CTRL(channel), r);
-+}
-+
-+
-+static int dsi_vc_enable(int channel, int enable)
-+{
-+ DSSDBG("dsi_vc_enable channel %d, enable %d\n", channel, enable);
-+
-+ enable = enable ? 1 : 0;
-+
-+ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
-+
-+ if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
-+ DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
-+ return -EIO;
-+ }
-+
-+ return 0;
-+}
-+
-+static void dsi_vc_enable_hs(int channel, int enable)
-+{
-+ DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
-+
-+ dsi_vc_enable(channel, 0);
-+ dsi_if_enable(0);
-+
-+ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
-+
-+ dsi_vc_enable(channel, 1);
-+ dsi_if_enable(1);
-+
-+ dsi_force_tx_stop_mode_io();
-+}
-+
-+static void dsi_vc_flush_long_data(int channel)
-+{
-+ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
-+ u32 val;
-+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
-+ DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
-+ (val >> 0) & 0xff,
-+ (val >> 8) & 0xff,
-+ (val >> 16) & 0xff,
-+ (val >> 24) & 0xff);
-+ }
-+}
-+
-+static u16 dsi_vc_flush_receive_data(int channel)
-+{
-+ /* RX_FIFO_NOT_EMPTY */
-+ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
-+ u32 val;
-+ u8 dt;
-+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
-+ DSSDBG("\trawval %#08x\n", val);
-+ dt = FLD_GET(val, 7, 0);
-+ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
-+ u16 err = FLD_GET(val, 23, 8);
-+ DSSERR("\tACK with ERROR: %#x\n", err);
-+ if (err & (1 << 9))
-+ DSSERR("\t\tECC multibit\n");
-+ if (err & (1 << 11))
-+ DSSERR("\t\tData type not recognized\n");
-+ if (err & (1 << 12))
-+ DSSERR("\t\tInvalid VC ID\n");
-+
-+ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
-+ DSSDBG("\tDCS short response, 1 byte: %#x\n",
-+ FLD_GET(val, 23, 8));
-+ return FLD_GET(val, 23, 8);
-+ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
-+ DSSDBG("\tDCS short response, 2 byte: %#x\n",
-+ FLD_GET(val, 23, 8));
-+ return FLD_GET(val, 23, 8);
-+ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
-+ DSSDBG("\tDCS long response, len %d\n",
-+ FLD_GET(val, 23, 8));
-+ dsi_vc_flush_long_data(channel);
-+ } else {
-+ DSSERR("\tunknown datatype\n");
-+ }
-+ }
-+ return 0;
-+}
-+
-+static int dsi_vc_send_bta(int channel)
-+{
-+ unsigned long tmo;
-+
-+ /*DSSDBG("dsi_vc_send_bta_sync %d\n", channel); */
-+
-+ if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
-+ DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
-+ dsi_vc_flush_receive_data(channel);
-+ }
-+
-+ REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
-+
-+ tmo = jiffies + msecs_to_jiffies(10);
-+ while (REG_GET(DSI_VC_CTRL(channel), 6, 6) == 1) {
-+ if (time_after(jiffies, tmo)) {
-+ DSSERR("Failed to send BTA\n");
-+ return -EIO;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int dsi_vc_send_bta_sync(int channel)
-+{
-+ int r = 0;
-+
-+ init_completion(&dsi.bta_completion);
-+
-+ dsi_vc_enable_bta_irq(channel);
-+
-+ r = dsi_vc_send_bta(channel);
-+ if (r)
-+ goto err;
-+
-+ if (wait_for_completion_timeout(&dsi.bta_completion,
-+ msecs_to_jiffies(500)) == 0) {
-+ DSSERR("Failed to receive BTA\n");
-+ r = -EIO;
-+ goto err;
-+ }
-+err:
-+ dsi_vc_disable_bta_irq(channel);
-+
-+ return r;
-+}
-+
-+static inline void dsi_vc_write_long_header(int channel, u8 data_type,
-+ u16 len, u8 ecc)
-+{
-+ u32 val;
-+ u8 data_id;
-+
-+ /*data_id = data_type | channel << 6; */
-+ data_id = data_type | dsi.vc[channel].dest_per << 6;
-+
-+ val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
-+ FLD_VAL(ecc, 31, 24);
-+
-+ dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
-+}
-+
-+static inline void dsi_vc_write_long_payload(int channel,
-+ u8 b1, u8 b2, u8 b3, u8 b4)
-+{
-+ u32 val;
-+
-+ val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
-+
-+/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
-+ b1, b2, b3, b4, val); */
-+
-+ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
-+}
-+
-+static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
-+ u8 ecc)
-+{
-+ /*u32 val; */
-+ int i;
-+ u8 *p;
-+ int r = 0;
-+ u8 b1, b2, b3, b4;
-+
-+ /*DSSDBG("dsi_vc_send_long, %d bytes\n", len); */
-+
-+ /* len + header */
-+ if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
-+ DSSERR("DSI: unable to send long packet: packet too long.\n");
-+ return -EINVAL;
-+ }
-+
-+ dsi_vc_write_long_header(channel, data_type, len, ecc);
-+
-+ /*dsi_vc_print_status(0); */
-+
-+ p = data;
-+ for (i = 0; i < len >> 2; i++) {
-+ /*DSSDBG("\tsending full packet %d\n", i); */
-+ /*dsi_vc_print_status(0); */
-+
-+ b1 = *p++;
-+ b2 = *p++;
-+ b3 = *p++;
-+ b4 = *p++;
-+
-+ dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
-+ }
-+
-+ i = len % 4;
-+ if (i) {
-+ b1 = 0; b2 = 0; b3 = 0;
-+
-+ /*DSSDBG("\tsending remainder bytes %d\n", i); */
-+
-+ switch (i) {
-+ case 3:
-+ b1 = *p++;
-+ b2 = *p++;
-+ b3 = *p++;
-+ break;
-+ case 2:
-+ b1 = *p++;
-+ b2 = *p++;
-+ break;
-+ case 1:
-+ b1 = *p++;
-+ break;
-+ }
-+
-+ dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
-+ }
-+
-+ return r;
-+}
-+
-+static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
-+{
-+ u32 r;
-+ u8 data_id;
-+/*
-+ DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
-+ channel,
-+ data_type, data & 0xff, (data >> 8) & 0xff);
-+*/
-+ if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
-+ DSSERR("ERROR FIFO FULL, aborting transfer\n");
-+ return -EINVAL;
-+ }
-+
-+ data_id = data_type | channel << 6;
-+
-+ r = (data_id << 0) | (data << 8) | (ecc << 24);
-+
-+ dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
-+
-+ return 0;
-+}
-+
-+int dsi_vc_send_null(int channel)
-+{
-+ u8 nullpkg[] = {0, 0, 0, 0};
-+ return dsi_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
-+}
-+EXPORT_SYMBOL(dsi_vc_send_null);
-+
-+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
-+{
-+ int r;
-+
-+ BUG_ON(len == 0);
-+
-+ if (len == 1) {
-+ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
-+ data[0], 0);
-+ } else if (len == 2) {
-+ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
-+ data[0] | (data[1] << 8), 0);
-+ } else {
-+ /* 0x39 = DCS Long Write */
-+ r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
-+ data, len, 0);
-+ }
-+
-+ return r;
-+}
-+EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
-+
-+int dsi_vc_dcs_write(int channel, u8 *data, int len)
-+{
-+ int r;
-+
-+ r = dsi_vc_dcs_write_nosync(channel, data, len);
-+ if (r)
-+ return r;
-+
-+ /* Some devices need time to process the msg in low power mode.
-+ This also makes the write synchronous, and checks that
-+ the peripheral is still alive */
-+ r = dsi_vc_send_bta_sync(channel);
-+
-+ return r;
-+}
-+EXPORT_SYMBOL(dsi_vc_dcs_write);
-+
-+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
-+{
-+ u32 val;
-+ u8 dt;
-+ int debug = 0;
-+
-+ if (debug)
-+ DSSDBG("dsi_vc_dcs_read\n");
-+
-+ dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
-+
-+ dsi_vc_send_bta_sync(channel);
-+
-+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
-+ if (debug)
-+ DSSDBG("\trawval %#08x\n", val);
-+ dt = FLD_GET(val, 7, 0);
-+ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
-+ u16 err = FLD_GET(val, 23, 8);
-+ DSSERR("\tACK with ERROR: %#x\n", err);
-+ if (err & (1 << 9))
-+ DSSERR("\t\tECC multibit\n");
-+ if (err & (1 << 11))
-+ DSSERR("\t\tData type not recognized\n");
-+ if (err & (1 << 12))
-+ DSSERR("\t\tInvalid VC ID\n");
-+ return -1;
-+
-+ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
-+ u8 data = FLD_GET(val, 15, 8);
-+ if (debug)
-+ DSSDBG("\tDCS short response, 1 byte: %#x\n", data);
-+
-+ if (buflen < 1)
-+ return -1;
-+
-+ buf[0] = data;
-+
-+ return 1;
-+ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
-+ u16 data = FLD_GET(val, 23, 8);
-+ if (debug)
-+ DSSDBG("\tDCS short response, 2 byte: %#x\n", data);
-+
-+ if (buflen < 2)
-+ return -1;
-+
-+ buf[0] = data & 0xff;
-+ buf[1] = (data >> 8) & 0xff;
-+
-+ return 2;
-+ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
-+ int x;
-+ int len = FLD_GET(val, 23, 8);
-+ if (debug)
-+ DSSDBG("\tDCS long response, len %d\n", len);
-+
-+ if (len > buflen)
-+ return -1;
-+
-+ x = 0;
-+ while (x < len) {
-+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
-+ if (debug)
-+ DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 "
-+ "%#02x\n",
-+ (val >> 0) & 0xff,
-+ (val >> 8) & 0xff,
-+ (val >> 16) & 0xff,
-+ (val >> 24) & 0xff);
-+
-+ if (x < len)
-+ buf[x++] = (val >> 0) & 0xff;
-+ if (x < len)
-+ buf[x++] = (val >> 8) & 0xff;
-+ if (x < len)
-+ buf[x++] = (val >> 16) & 0xff;
-+ if (x < len)
-+ buf[x++] = (val >> 24) & 0xff;
-+ }
-+
-+ return len;
-+ } else {
-+ DSSERR("\tunknown datatype\n");
-+ return -1;
-+ }
-+}
-+EXPORT_SYMBOL(dsi_vc_dcs_read);
-+
-+
-+int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
-+{
-+ return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
-+ len, 0);
-+}
-+EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
-+
-+
-+static int dsi_set_lp_rx_timeout(int ns, int x4, int x16)
-+{
-+ u32 r;
-+ unsigned long fck;
-+ int ticks;
-+
-+ /* ticks in DSI_FCK */
-+
-+ fck = dsi_fclk_rate();
-+ ticks = (fck / 1000 / 1000) * ns / 1000;
-+
-+ if (ticks > 0x1fff) {
-+ DSSERR("LP_TX_TO too high\n");
-+ return -EINVAL;
-+ }
-+
-+ r = dsi_read_reg(DSI_TIMING2);
-+ r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
-+ r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
-+ r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
-+ r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
-+ dsi_write_reg(DSI_TIMING2, r);
-+
-+ DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n",
-+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
-+ (fck / 1000 / 1000),
-+ ticks);
-+
-+ return 0;
-+}
-+
-+static int dsi_set_ta_timeout(int ns, int x8, int x16)
-+{
-+ u32 r;
-+ unsigned long fck;
-+ int ticks;
-+
-+ /* ticks in DSI_FCK */
-+
-+ fck = dsi_fclk_rate();
-+ ticks = (fck / 1000 / 1000) * ns / 1000;
-+
-+ if (ticks > 0x1fff) {
-+ DSSERR("TA_TO too high\n");
-+ return -EINVAL;
-+ }
-+
-+ r = dsi_read_reg(DSI_TIMING1);
-+ r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
-+ r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
-+ r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
-+ r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
-+ dsi_write_reg(DSI_TIMING1, r);
-+
-+ DSSDBG("TA_TO %ld ns (%#x ticks)\n",
-+ (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
-+ (fck / 1000 / 1000),
-+ ticks);
-+
-+ return 0;
-+}
-+
-+static int dsi_set_stop_state_counter(int ns, int x4, int x16)
-+{
-+ u32 r;
-+ unsigned long fck;
-+ int ticks;
-+
-+ /* ticks in DSI_FCK */
-+
-+ fck = dsi_fclk_rate();
-+ ticks = (fck / 1000 / 1000) * ns / 1000;
-+
-+ if (ticks > 0x1fff) {
-+ DSSERR("STOP_STATE_COUNTER_IO too high\n");
-+ return -EINVAL;
-+ }
-+
-+ r = dsi_read_reg(DSI_TIMING1);
-+ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
-+ r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
-+ r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
-+ r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
-+ dsi_write_reg(DSI_TIMING1, r);
-+
-+ DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n",
-+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
-+ (fck / 1000 / 1000),
-+ ticks);
-+
-+ return 0;
-+}
-+
-+static int dsi_set_hs_tx_timeout(int ns, int x4, int x16)
-+{
-+ u32 r;
-+ unsigned long fck;
-+ int ticks;
-+
-+ /* ticks in TxByteClkHS */
-+
-+ fck = dsi.ddr_clk / 4;
-+ ticks = (fck / 1000 / 1000) * ns / 1000;
-+
-+ if (ticks > 0x1fff) {
-+ DSSERR("HS_TX_TO too high\n");
-+ return -EINVAL;
-+ }
-+
-+ r = dsi_read_reg(DSI_TIMING2);
-+ r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
-+ r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
-+ r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
-+ r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
-+ dsi_write_reg(DSI_TIMING2, r);
-+
-+ DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n",
-+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
-+ (fck / 1000 / 1000),
-+ ticks);
-+
-+ return 0;
-+}
-+static int dsi_proto_config(struct omap_display *display)
-+{
-+ u32 r;
-+ int buswidth = 0;
-+
-+ dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
-+ DSI_FIFO_SIZE_0,
-+ DSI_FIFO_SIZE_0,
-+ DSI_FIFO_SIZE_0);
-+
-+ dsi_config_rx_fifo(DSI_FIFO_SIZE_128,
-+ DSI_FIFO_SIZE_0,
-+ DSI_FIFO_SIZE_0,
-+ DSI_FIFO_SIZE_0);
-+
-+ /* XXX what values for the timeouts? */
-+ dsi_set_stop_state_counter(1000, 0, 0);
-+
-+ dsi_set_ta_timeout(50000, 1, 1);
-+
-+ /* 3000ns * 16 */
-+ dsi_set_lp_rx_timeout(3000, 0, 1);
-+
-+ /* 10000ns * 4 */
-+ dsi_set_hs_tx_timeout(10000, 1, 0);
-+
-+ switch (display->bpp) {
-+ case 16:
-+ buswidth = 0;
-+ break;
-+ case 18:
-+ buswidth = 1;
-+ break;
-+ case 24:
-+ buswidth = 2;
-+ break;
-+ default:
-+ BUG();
-+ }
-+
-+ r = dsi_read_reg(DSI_CTRL);
-+ r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
-+ r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
-+ r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
-+ /* XXX what should the ratio be */
-+ r = FLD_MOD(r, 0, 4, 4); /* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
-+ r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
-+ r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
-+ r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
-+ r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
-+ r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
-+ r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
-+ r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
-+
-+ dsi_write_reg(DSI_CTRL, r);
-+
-+ /* we configure vc0 for L4 communication, and
-+ * vc1 for dispc */
-+ dsi_vc_config(0);
-+ dsi_vc_config_vp(1);
-+
-+ /* set all vc targets to peripheral 0 */
-+ dsi.vc[0].dest_per = 0;
-+ dsi.vc[1].dest_per = 0;
-+ dsi.vc[2].dest_per = 0;
-+ dsi.vc[3].dest_per = 0;
-+
-+ return 0;
-+}
-+
-+static void dsi_proto_timings(void)
-+{
-+ int tlpx_half, tclk_zero, tclk_prepare, tclk_trail;
-+ int tclk_pre, tclk_post;
-+ int ddr_clk_pre, ddr_clk_post;
-+ u32 r;
-+
-+ r = dsi_read_reg(DSIPHY_CFG1);
-+ tlpx_half = FLD_GET(r, 22, 16);
-+ tclk_trail = FLD_GET(r, 15, 8);
-+ tclk_zero = FLD_GET(r, 7, 0);
-+
-+ r = dsi_read_reg(DSIPHY_CFG2);
-+ tclk_prepare = FLD_GET(r, 7, 0);
-+
-+ /* min 8*UI */
-+ tclk_pre = 4;
-+ /* min 60ns + 52*UI */
-+ tclk_post = ns2ddr(60) + 26;
-+
-+ ddr_clk_pre = (tclk_pre + tlpx_half*2 + tclk_zero + tclk_prepare) / 4;
-+ ddr_clk_post = (tclk_post + tclk_trail) / 4;
-+
-+ r = dsi_read_reg(DSI_CLK_TIMING);
-+ r = FLD_MOD(r, ddr_clk_pre, 15, 8);
-+ r = FLD_MOD(r, ddr_clk_post, 7, 0);
-+ dsi_write_reg(DSI_CLK_TIMING, r);
-+
-+#ifdef VERBOSE
-+ DSSDBG("ddr_clk_pre %d, ddr_clk_post %d\n",
-+ ddr_clk_pre,
-+ ddr_clk_post);
-+#endif
-+}
-+
-+
-+#define DSI_DECL_VARS \
-+ int __dsi_cb = 0; u32 __dsi_cv = 0;
-+
-+#define DSI_FLUSH(ch) \
-+ if (__dsi_cb > 0) { \
-+ /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
-+ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
-+ __dsi_cb = __dsi_cv = 0; \
-+ }
-+
-+#define DSI_PUSH(ch, data) \
-+ do { \
-+ __dsi_cv |= (data) << (__dsi_cb * 8); \
-+ /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
-+ if (++__dsi_cb > 3) \
-+ DSI_FLUSH(ch); \
-+ } while (0)
-+
-+static int dsi_update_screen_l4(struct omap_display *display,
-+ int x, int y, int w, int h)
-+{
-+ /* Note: supports only 24bit colors in 32bit container */
-+ int first = 1;
-+ int fifo_stalls = 0;
-+ int max_dsi_packet_size;
-+ int max_data_per_packet;
-+ int max_pixels_per_packet;
-+ int pixels_left;
-+ int bytespp = 3;
-+ int scr_width;
-+ u32 *data;
-+ int start_offset;
-+ int horiz_inc;
-+ int current_x;
-+ struct omap_overlay *ovl;
-+
-+ debug_irq = 0;
-+
-+ DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
-+ x, y, w, h);
-+
-+ ovl = &display->manager->overlays[0];
-+
-+ if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
-+ return -EINVAL;
-+
-+ if (display->ctrl->bpp != 24)
-+ return -EINVAL;
-+
-+ enable_clocks(1);
-+
-+ scr_width = ovl->info.screen_width;
-+ data = ovl->info.vaddr;
-+
-+ start_offset = scr_width * y + x;
-+ horiz_inc = scr_width - w;
-+ current_x = x;
-+
-+ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
-+ * in fifo */
-+
-+ /* When using CPU, max long packet size is TX buffer size */
-+ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
-+
-+ /* we seem to get better perf if we divide the tx fifo to half,
-+ and while the other half is being sent, we fill the other half
-+ max_dsi_packet_size /= 2; */
-+
-+ max_data_per_packet = max_dsi_packet_size - 4 - 1;
-+
-+ max_pixels_per_packet = max_data_per_packet / bytespp;
-+
-+ DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
-+
-+ display->ctrl->setup_update(display, x, y, w, h);
-+
-+ pixels_left = w * h;
-+
-+ DSSDBG("total pixels %d\n", pixels_left);
-+
-+ data += start_offset;
-+
-+ dsi.update_region.x = x;
-+ dsi.update_region.y = y;
-+ dsi.update_region.w = w;
-+ dsi.update_region.h = h;
-+ dsi.update_region.bytespp = bytespp;
-+
-+ start_measuring();
-+
-+ while (pixels_left > 0) {
-+ /* 0x2c = write_memory_start */
-+ /* 0x3c = write_memory_continue */
-+ u8 dcs_cmd = first ? 0x2c : 0x3c;
-+ int pixels;
-+ DSI_DECL_VARS;
-+ first = 0;
-+
-+#if 1
-+ /* using fifo not empty */
-+ /* TX_FIFO_NOT_EMPTY */
-+ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
-+ udelay(1);
-+ fifo_stalls++;
-+ if (fifo_stalls > 0xfffff) {
-+ DSSERR("fifo stalls overflow, pixels left %d\n",
-+ pixels_left);
-+ dsi_if_enable(0);
-+ enable_clocks(0);
-+ return -EIO;
-+ }
-+ }
-+#elif 1
-+ /* using fifo emptiness */
-+ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
-+ max_dsi_packet_size) {
-+ fifo_stalls++;
-+ if (fifo_stalls > 0xfffff) {
-+ DSSERR("fifo stalls overflow, pixels left %d\n",
-+ pixels_left);
-+ dsi_if_enable(0);
-+ enable_clocks(0);
-+ return -EIO;
-+ }
-+ }
-+#else
-+ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
-+ fifo_stalls++;
-+ if (fifo_stalls > 0xfffff) {
-+ DSSERR("fifo stalls overflow, pixels left %d\n",
-+ pixels_left);
-+ dsi_if_enable(0);
-+ enable_clocks(0);
-+ return -EIO;
-+ }
-+ }
-+#endif
-+ pixels = min(max_pixels_per_packet, pixels_left);
-+
-+ pixels_left -= pixels;
-+
-+ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
-+ 1 + pixels * bytespp, 0);
-+
-+ DSI_PUSH(0, dcs_cmd);
-+
-+ while (pixels-- > 0) {
-+ u32 pix = *data++;
-+
-+ DSI_PUSH(0, (pix >> 16) & 0xff);
-+ DSI_PUSH(0, (pix >> 8) & 0xff);
-+ DSI_PUSH(0, (pix >> 0) & 0xff);
-+
-+ current_x++;
-+ if (current_x == x+w) {
-+ current_x = x;
-+ data += horiz_inc;
-+ }
-+ }
-+
-+ DSI_FLUSH(0);
-+ }
-+
-+ end_measuring("L4");
-+
-+ enable_clocks(0);
-+
-+ return 0;
-+}
-+
-+#if 0
-+static void dsi_clear_screen_l4(struct omap_display *display,
-+ int x, int y, int w, int h)
-+{
-+ int first = 1;
-+ int fifo_stalls = 0;
-+ int max_dsi_packet_size;
-+ int max_data_per_packet;
-+ int max_pixels_per_packet;
-+ int pixels_left;
-+ int bytespp = 3;
-+ int pixnum;
-+
-+ debug_irq = 0;
-+
-+ DSSDBG("dsi_clear_screen_l4 (%d,%d %dx%d)\n",
-+ x, y, w, h);
-+
-+ if (display->ctrl->bpp != 24)
-+ return -EINVAL;
-+
-+ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp)
-+ * bytes in fifo */
-+
-+ /* When using CPU, max long packet size is TX buffer size */
-+ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
-+
-+ max_data_per_packet = max_dsi_packet_size - 4 - 1;
-+
-+ max_pixels_per_packet = max_data_per_packet / bytespp;
-+
-+ enable_clocks(1);
-+
-+ display->ctrl->setup_update(display, x, y, w, h);
-+
-+ pixels_left = w * h;
-+
-+ dsi.update_region.x = x;
-+ dsi.update_region.y = y;
-+ dsi.update_region.w = w;
-+ dsi.update_region.h = h;
-+ dsi.update_region.bytespp = bytespp;
-+
-+ start_measuring();
-+
-+ pixnum = 0;
-+
-+ while (pixels_left > 0) {
-+ /* 0x2c = write_memory_start */
-+ /* 0x3c = write_memory_continue */
-+ u8 dcs_cmd = first ? 0x2c : 0x3c;
-+ int pixels;
-+ DSI_DECL_VARS;
-+ first = 0;
-+
-+ /* TX_FIFO_NOT_EMPTY */
-+ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
-+ fifo_stalls++;
-+ if (fifo_stalls > 0xfffff) {
-+ DSSERR("fifo stalls overflow\n");
-+ dsi_if_enable(0);
-+ enable_clocks(0);
-+ return;
-+ }
-+ }
-+
-+ pixels = min(max_pixels_per_packet, pixels_left);
-+
-+ pixels_left -= pixels;
-+
-+ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
-+ 1 + pixels * bytespp, 0);
-+
-+ DSI_PUSH(0, dcs_cmd);
-+
-+ while (pixels-- > 0) {
-+ u32 pix;
-+
-+ pix = 0x000000;
-+
-+ DSI_PUSH(0, (pix >> 16) & 0xff);
-+ DSI_PUSH(0, (pix >> 8) & 0xff);
-+ DSI_PUSH(0, (pix >> 0) & 0xff);
-+ }
-+
-+ DSI_FLUSH(0);
-+ }
-+
-+ enable_clocks(0);
-+
-+ end_measuring("L4 CLEAR");
-+}
-+#endif
-+
-+static int dsi_wait_for_framedone(void)
-+{
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&dsi.update_lock, flags);
-+ if (dsi.update_ongoing) {
-+ long wait = msecs_to_jiffies(1000);
-+ dsi.update_syncers++;
-+ spin_unlock_irqrestore(&dsi.update_lock, flags);
-+ wait = wait_for_completion_timeout(&dsi.update_completion,
-+ wait);
-+ if (wait == 0) {
-+ DSSERR("timeout waiting sync\n");
-+ return -ETIME;
-+ }
-+ } else {
-+ spin_unlock_irqrestore(&dsi.update_lock, flags);
-+ }
-+
-+ return 0;
-+}
-+
-+static void dsi_setup_update_dispc(struct omap_display *display,
-+ int x, int y, int w, int h)
-+{
-+ int bytespp = 3;
-+
-+ DSSDBG("dsi_setup_update_dispc(%d,%d %dx%d)\n",
-+ x, y, w, h);
-+
-+ dsi.update_region.display = display;
-+ dsi.update_region.x = x;
-+ dsi.update_region.y = y;
-+ dsi.update_region.w = w;
-+ dsi.update_region.h = h;
-+ dsi.update_region.bytespp = bytespp;
-+
-+ enable_clocks(1);
-+
-+ dispc_setup_partial_planes(display, &x, &y, &w, &h);
-+
-+ dispc_set_lcd_size(w, h);
-+
-+ enable_clocks(0);
-+}
-+
-+static void dsi_update_screen_dispc(struct omap_display *display)
-+{
-+ int bytespp = 3;
-+ int total_len;
-+ int line_packet_len;
-+ int x, y, w, h;
-+ u32 l;
-+
-+ x = dsi.update_region.x;
-+ y = dsi.update_region.y;
-+ w = dsi.update_region.w;
-+ h = dsi.update_region.h;
-+
-+ DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
-+ x, y, w, h);
-+
-+ enable_clocks(1);
-+
-+ /* TODO: one packet could be longer, I think? Max is the line buffer */
-+ line_packet_len = w * bytespp + 1; /* 1 byte for DCS cmd */
-+ total_len = line_packet_len * h;
-+
-+ display->ctrl->setup_update(display, x, y, w, h);
-+
-+ if (0)
-+ dsi_vc_print_status(1);
-+
-+ start_measuring();
-+
-+ l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
-+ dsi_write_reg(DSI_VC_TE(1), l);
-+
-+ dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, line_packet_len, 0);
-+
-+ if (dsi.use_te)
-+ l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
-+ else
-+ l = FLD_MOD(l, 1, 31, 31); /* TE_START */
-+ dsi_write_reg(DSI_VC_TE(1), l);
-+
-+ dispc_enable_lcd_out(1);
-+
-+ if (dsi.use_te)
-+ dsi_vc_send_bta(1);
-+}
-+
-+static void framedone_callback(void *data, u32 mask)
-+{
-+ if (dsi.framedone_scheduled) {
-+ DSSERR("Framedone already scheduled. Bogus FRAMEDONE IRQ?\n");
-+ return;
-+ }
-+
-+ dsi.framedone_scheduled = 1;
-+
-+ /* We get FRAMEDONE when DISPC has finished sending pixels and turns
-+ * itself off. However, DSI still has the pixels in its buffers, and
-+ * is sending the data. Thus we have to wait until we can do a new
-+ * transfer or turn the clocks off. We do that in a separate work
-+ * func. */
-+ schedule_work(&dsi.framedone_work);
-+}
-+
-+static void framedone_worker(struct work_struct *work)
-+{
-+ unsigned long flags;
-+ u32 l;
-+ unsigned long tmo;
-+ int i = 0;
-+
-+ l = REG_GET(DSI_VC_TE(1), 23, 0); /* TE_SIZE */
-+
-+ /* There shouldn't be much stuff in DSI buffers, if any, so we'll
-+ * just busyloop */
-+ if (l > 0) {
-+ tmo = jiffies + msecs_to_jiffies(50);
-+ while (REG_GET(DSI_VC_TE(1), 23, 0) > 0) { /* TE_SIZE */
-+ i++;
-+ if (time_after(jiffies, tmo)) {
-+ DSSERR("timeout waiting TE_SIZE to zero\n");
-+ break;
-+ }
-+ cpu_relax();
-+ }
-+ }
-+
-+ if (REG_GET(DSI_VC_TE(1), 30, 30))
-+ DSSERR("TE_EN not zero\n");
-+
-+ if (REG_GET(DSI_VC_TE(1), 31, 31))
-+ DSSERR("TE_START not zero\n");
-+
-+ spin_lock_irqsave(&dsi.update_lock, flags);
-+ if (dsi.update_ongoing == 0) {
-+ spin_unlock_irqrestore(&dsi.update_lock, flags);
-+ DSSERR("framedone irq without update request\n");
-+ return;
-+ }
-+ spin_unlock_irqrestore(&dsi.update_lock, flags);
-+
-+ end_measuring("DISPC");
-+
-+ DSSDBG("FRAMEDONE\n");
-+
-+#if 0
-+ if (l)
-+ DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
-+#else
-+ if (l > 1024*3)
-+ DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
-+#endif
-+
-+ spin_lock_irqsave(&dsi.update_lock, flags);
-+ dsi.update_ongoing = 0;
-+ while (dsi.update_syncers > 0) {
-+ complete(&dsi.update_completion);
-+ --dsi.update_syncers;
-+ }
-+ spin_unlock_irqrestore(&dsi.update_lock, flags);
-+
-+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
-+ dispc_fake_vsync_irq();
-+#endif
-+ enable_clocks(0);
-+
-+ dsi.framedone_scheduled = 0;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
-+ spin_lock_irqsave(&dsi.update_lock, flags);
-+ dsi.update_ongoing = 1;
-+ spin_unlock_irqrestore(&dsi.update_lock, flags);
-+ dsi_update_screen_dispc(dsi.update_region.display);
-+ }
-+}
-+
-+static void dsi_start_auto_update(struct omap_display *display)
-+{
-+ unsigned long flags;
-+ int bytespp = 3;
-+
-+ DSSDBG("starting auto update\n");
-+
-+ dsi.update_region.display = display;
-+ dsi.update_region.x = 0;
-+ dsi.update_region.y = 0;
-+ dsi.update_region.w = display->x_res;
-+ dsi.update_region.h = display->y_res;
-+ dsi.update_region.bytespp = bytespp;
-+
-+ enable_clocks(1);
-+
-+ dispc_set_lcd_size(display->x_res, display->y_res);
-+
-+ spin_lock_irqsave(&dsi.update_lock, flags);
-+ dsi.update_ongoing = 1;
-+ spin_unlock_irqrestore(&dsi.update_lock, flags);
-+ dsi_update_screen_dispc(display);
-+}
-+
-+static void dsi_stop_auto_update(void)
-+{
-+ dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
-+
-+ DSSDBG("waiting for display to finish.\n");
-+ dsi_wait_for_framedone();
-+ DSSDBG("done waiting\n");
-+ enable_clocks(0);
-+
-+ dsi.update_mode = OMAP_DSS_UPDATE_MANUAL;
-+}
-+
-+static int dsi_set_update_mode(struct omap_display *display,
-+ enum omap_dss_update_mode mode)
-+{
-+ if (mode == dsi.update_mode)
-+ return 0;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
-+ dsi_stop_auto_update();
-+ else if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
-+ dsi_wait_for_framedone();
-+
-+ dsi.update_mode = mode;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
-+ dsi_start_auto_update(display);
-+
-+ return 0;
-+}
-+
-+/* Display funcs */
-+
-+static int dsi_display_enable(struct omap_display *display)
-+{
-+ int r = 0;
-+ struct dsi_clock_info cinfo;
-+
-+ DSSDBG("dsi_display_enable\n");
-+
-+ mutex_lock(&dsi.lock);
-+
-+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
-+ DSSERR("display already enabled\n");
-+ r = -EINVAL;
-+ goto err0;
-+ }
-+
-+ enable_clocks(1);
-+
-+ r = omap_dispc_register_isr(framedone_callback, NULL,
-+ DISPC_IRQ_FRAMEDONE);
-+ if (r) {
-+ DSSERR("can't get FRAMEDONE irq\n");
-+ goto err1;
-+ }
-+
-+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
-+
-+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
-+ dispc_enable_fifohandcheck(1);
-+ dispc_setup_plane_fifo(OMAP_DSS_GFX, 0);
-+ dispc_setup_plane_fifo(OMAP_DSS_VIDEO1, 0);
-+ dispc_setup_plane_fifo(OMAP_DSS_VIDEO2, 0);
-+ dispc_set_tft_data_lines(display->bpp);
-+
-+ {
-+ struct omap_video_timings timings = {
-+ .hsw = 1,
-+ .hfp = 1,
-+ .hbp = 1,
-+ .vsw = 1,
-+ .vfp = 0,
-+ .vbp = 0,
-+ };
-+
-+ dispc_set_lcd_timings(&timings);
-+ }
-+
-+ _dsi_print_reset_status();
-+
-+ r = dsi_pll_init(1, 0);
-+ if (r)
-+ goto err2;
-+
-+ /* XXX hardcoded for 300Mbp/lane for now */
-+ r = dsi_pll_calc_datafreq(600 * 1000 * 1000, &cinfo);
-+ if (r)
-+ goto err3;
-+
-+ r = dsi_pll_program(&cinfo);
-+ if (r)
-+ goto err3;
-+
-+ DSSDBG("PLL OK\n");
-+
-+ r = dsi_complexio_init(display);
-+ if (r)
-+ goto err3;
-+
-+ _dsi_print_reset_status();
-+
-+ dsi_proto_timings();
-+ dsi_set_lp_clk_divisor();
-+
-+ if (1)
-+ _dsi_print_reset_status();
-+
-+ r = dsi_proto_config(display);
-+ if (r)
-+ goto err4;
-+
-+ /* enable interface */
-+ dsi_vc_enable(0, 1);
-+ dsi_vc_enable(1, 1);
-+ dsi_if_enable(1);
-+ dsi_force_tx_stop_mode_io();
-+
-+
-+ if (display->ctrl && display->ctrl->enable) {
-+ r = display->ctrl->enable(display);
-+ if (r)
-+ goto err5;
-+ }
-+
-+ if (display->panel && display->panel->enable) {
-+ r = display->panel->enable(display);
-+ if (r)
-+ goto err6;
-+ }
-+
-+ if (dsi.use_te) {
-+ r = display->ctrl->enable_te(display, 1);
-+ if (r)
-+ goto err7;
-+ }
-+
-+ /* enable high-speed after initial config */
-+ dsi_vc_enable_hs(0, 1);
-+
-+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
-+ dsi_start_auto_update(display);
-+
-+ enable_clocks(0);
-+ mutex_unlock(&dsi.lock);
-+
-+ return 0;
-+err7:
-+ if (display->panel && display->panel->disable)
-+ display->panel->disable(display);
-+err6:
-+ if (display->ctrl && display->ctrl->disable)
-+ display->ctrl->disable(display);
-+err5:
-+ dsi_if_enable(0);
-+err4:
-+ dsi_complexio_uninit();
-+err3:
-+ dsi_pll_uninit();
-+err2:
-+ omap_dispc_unregister_isr(framedone_callback);
-+err1:
-+ enable_clocks(0);
-+err0:
-+ mutex_unlock(&dsi.lock);
-+ DSSDBG("dsi_display_enable FAILED\n");
-+ return r;
-+}
-+
-+static void dsi_display_disable(struct omap_display *display)
-+{
-+ DSSDBG("dsi_display_disable\n");
-+
-+ mutex_lock(&dsi.lock);
-+
-+ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
-+ goto end;
-+
-+ enable_clocks(1);
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
-+ dsi_stop_auto_update();
-+ else if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
-+ dsi_wait_for_framedone();
-+
-+ display->state = OMAP_DSS_DISPLAY_DISABLED;
-+
-+ omap_dispc_unregister_isr(framedone_callback);
-+
-+ if (display->panel && display->panel->disable)
-+ display->panel->disable(display);
-+ if (display->ctrl && display->ctrl->disable)
-+ display->ctrl->disable(display);
-+
-+ /* XXX sleep a bit to make sure all DSI buffers are sent.
-+ * We should check it from somewhere, fifo fullness I guess */
-+ msleep(200);
-+
-+ dsi_complexio_uninit();
-+ dsi_pll_uninit();
-+
-+ enable_clocks(0);
-+
-+end:
-+ mutex_unlock(&dsi.lock);
-+}
-+
-+static int dsi_display_suspend(struct omap_display *display)
-+{
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
-+ return -EINVAL;
-+
-+ if (display->panel->suspend)
-+ display->panel->suspend(display);
-+
-+ if (display->ctrl->suspend)
-+ display->ctrl->suspend(display);
-+
-+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
-+
-+ return 0;
-+}
-+
-+static int dsi_display_resume(struct omap_display *display)
-+{
-+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
-+ return -EINVAL;
-+
-+ if (display->panel->resume)
-+ display->panel->resume(display);
-+
-+ if (display->ctrl->resume)
-+ display->ctrl->resume(display);
-+
-+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
-+
-+ return 0;
-+}
-+
-+static void dsi_display_set_mode(struct omap_display *display,
-+ int x_res, int y_res, int bpp)
-+{
-+ DSSDBG("dsi_display_set_mode %dx%d, %dbpp\n", x_res, y_res, bpp);
-+}
-+
-+static int dsi_display_update(struct omap_display *display,
-+ int x, int y, int w, int h)
-+{
-+ unsigned long flags;
-+ int r = 0;
-+
-+ DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h);
-+
-+ if (w == 0 || h == 0)
-+ return 0;
-+
-+ mutex_lock(&dsi.lock);
-+
-+ if (dsi.update_mode != OMAP_DSS_UPDATE_MANUAL)
-+ goto end; /* XXX return error? */
-+
-+ spin_lock_irqsave(&dsi.update_lock, flags);
-+
-+ if (dsi.update_ongoing) {
-+ spin_unlock_irqrestore(&dsi.update_lock, flags);
-+ DSSERR("DSI is busy\n");
-+ r = -EBUSY;
-+ goto end;
-+ }
-+
-+ dsi.update_ongoing = 1;
-+
-+ if (dsi.update_syncers > 0)
-+ DSSERR("someone waiting for sync, and no update ongoing\n");
-+
-+ spin_unlock_irqrestore(&dsi.update_lock, flags);
-+
-+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
-+ dsi_setup_update_dispc(display, x, y, w, h);
-+ dsi_update_screen_dispc(display);
-+ } else {
-+ r = dsi_update_screen_l4(display, x, y, w, h);
-+ if (r)
-+ goto end;
-+
-+ spin_lock_irqsave(&dsi.update_lock, flags);
-+ dsi.update_ongoing = 0;
-+ while (dsi.update_syncers > 0) {
-+ complete(&dsi.update_completion);
-+ --dsi.update_syncers;
-+ }
-+ spin_unlock_irqrestore(&dsi.update_lock, flags);
-+ }
-+
-+end:
-+ mutex_unlock(&dsi.lock);
-+ return r;
-+}
-+
-+static int dsi_display_sync(struct omap_display *display)
-+{
-+ int r = 0;
-+
-+ DSSDBG("dsi_display_sync\n");
-+
-+ mutex_lock(&dsi.lock);
-+
-+ if (dsi.update_mode != OMAP_DSS_UPDATE_MANUAL)
-+ goto end;
-+
-+ r = dsi_wait_for_framedone();
-+
-+end:
-+ mutex_unlock(&dsi.lock);
-+ return r;
-+}
-+
-+static int dsi_display_set_update_mode(struct omap_display *display,
-+ enum omap_dss_update_mode mode)
-+{
-+ int r;
-+
-+ DSSDBG("dsi_display_set_update_mode\n");
-+
-+ mutex_lock(&dsi.lock);
-+
-+ r = dsi_set_update_mode(display, mode);
-+
-+ mutex_unlock(&dsi.lock);
-+
-+ return r;
-+}
-+
-+static enum omap_dss_update_mode dsi_display_get_update_mode(
-+ struct omap_display *display)
-+{
-+ return dsi.update_mode;
-+}
-+
-+static int dsi_display_enable_te(struct omap_display *display, int enable)
-+{
-+ enum omap_dss_update_mode mode;
-+
-+ DSSDBG("dsi_display_enable_te\n");
-+
-+ mutex_lock(&dsi.lock);
-+
-+ enable_clocks(1);
-+
-+ mode = dsi.update_mode;
-+
-+ /* XXX perhaps suspend or something would be better here */
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
-+ dsi_stop_auto_update();
-+ else if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
-+ dsi_wait_for_framedone();
-+
-+ dsi.use_te = enable;
-+ display->ctrl->enable_te(display, enable);
-+ if (enable) {
-+ /* disable LP_RX_TO, so that we can receive TE.
-+ * Time to wait for TE is longer than the timer allows */
-+ REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
-+ } else {
-+ REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
-+ }
-+
-+ /* restore the old update mode */
-+ dsi_set_update_mode(display, mode);
-+
-+ enable_clocks(0);
-+
-+ mutex_unlock(&dsi.lock);
-+
-+ return 0;
-+}
-+
-+static int dsi_display_get_te(struct omap_display *display)
-+{
-+ return dsi.use_te;
-+}
-+
-+static int dsi_display_run_test(struct omap_display *display, int test_num)
-+{
-+ enum omap_dss_update_mode mode;
-+ int r = 0;
-+
-+ DSSDBG("dsi_display_run_test %d\n", test_num);
-+
-+ mutex_lock(&dsi.lock);
-+
-+ enable_clocks(1);
-+
-+ mode = dsi.update_mode;
-+
-+ /* XXX perhaps suspend or something would be better here */
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
-+ dsi_stop_auto_update();
-+ else if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
-+ dsi_wait_for_framedone();
-+
-+ /* run test first in low speed mode */
-+ dsi_vc_enable_hs(0, 0);
-+
-+ if (display->ctrl->run_test) {
-+ r = display->ctrl->run_test(display, test_num);
-+ if (r)
-+ goto fail;
-+ }
-+
-+ if (display->panel->run_test) {
-+ r = display->panel->run_test(display, test_num);
-+ if (r)
-+ goto fail;
-+ }
-+
-+ /* then in high speed */
-+ dsi_vc_enable_hs(0, 1);
-+
-+ if (display->ctrl->run_test) {
-+ r = display->ctrl->run_test(display, test_num);
-+ if (r)
-+ goto fail;
-+ }
-+
-+ if (display->panel->run_test)
-+ r = display->panel->run_test(display, test_num);
-+
-+fail:
-+ dsi_vc_enable_hs(0, 1);
-+
-+ /* restore the old update mode */
-+ dsi_set_update_mode(display, mode);
-+
-+ enable_clocks(0);
-+
-+ mutex_unlock(&dsi.lock);
-+
-+ return r;
-+}
-+
-+void dsi_init_display(struct omap_display *display)
-+{
-+ DSSDBG("DSI init\n");
-+
-+ display->enable = dsi_display_enable;
-+ display->disable = dsi_display_disable;
-+ display->suspend = dsi_display_suspend;
-+ display->resume = dsi_display_resume;
-+ display->set_mode = dsi_display_set_mode;
-+ display->update = dsi_display_update;
-+ display->sync = dsi_display_sync;
-+ display->set_update_mode = dsi_display_set_update_mode;
-+ display->get_update_mode = dsi_display_get_update_mode;
-+ display->enable_te = dsi_display_enable_te;
-+ display->get_te = dsi_display_get_te;
-+ display->run_test = dsi_display_run_test;
-+
-+ display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
-+}
-+
-+int dsi_init(void)
-+{
-+ u32 rev;
-+
-+ init_completion(&dsi.bta_completion);
-+ INIT_WORK(&dsi.framedone_work, framedone_worker);
-+
-+ init_completion(&dsi.update_completion);
-+ spin_lock_init(&dsi.update_lock);
-+ dsi.update_ongoing = 0;
-+ dsi.update_syncers = 0;
-+
-+ mutex_init(&dsi.lock);
-+
-+ dsi.base = ioremap(DSI_BASE, SZ_1K);
-+ if (!dsi.base) {
-+ DSSERR("can't ioremap DSI\n");
-+ return -ENOMEM;
-+ }
-+
-+ dsi.dss_ick = get_dss_ick();
-+ dsi.dss1_fck = get_dss1_fck();
-+ dsi.dss2_fck = get_dss2_fck();
-+
-+ enable_clocks(1);
-+
-+ /* Autoidle */
-+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
-+
-+ /* ENWAKEUP */
-+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
-+
-+ /* SIDLEMODE smart-idle */
-+ REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
-+
-+ if (0)
-+ _dsi_reset();
-+
-+ _dsi_initialize_irq();
-+
-+ rev = dsi_read_reg(DSI_REVISION);
-+ printk(KERN_INFO "OMAP DSI rev %d.%d\n",
-+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
-+
-+ enable_clocks(0);
-+
-+ return 0;
-+}
-+
-+void dsi_exit(void)
-+{
-+ iounmap(dsi.base);
-+
-+ DSSDBG("omap_dsi_exit\n");
-+}
-+
---
-1.5.6.3
-
diff --git a/packages/linux/linux-omap/0010-DSS-support-for-Beagle-Board.patch b/packages/linux/linux-omap/0007-DSS-support-for-Beagle-Board.patch
index ee93a32dde..145695cd8a 100644
--- a/packages/linux/linux-omap/0010-DSS-support-for-Beagle-Board.patch
+++ b/packages/linux/linux-omap/0007-DSS-support-for-Beagle-Board.patch
@@ -1,15 +1,15 @@
-From 25b99d79100db8142de061954704fdabd76672d2 Mon Sep 17 00:00:00 2001
+From c5e43b2e4bc191feaab30e364c462a47aa3cc0a3 Mon Sep 17 00:00:00 2001
From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Date: Mon, 29 Sep 2008 17:03:36 +0300
Subject: [PATCH] DSS: support for Beagle Board
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
---
- arch/arm/mach-omap2/board-omap3beagle.c | 121 +++++++++++++++++++++++++++----
- 1 files changed, 108 insertions(+), 13 deletions(-)
+ arch/arm/mach-omap2/board-omap3beagle.c | 123 +++++++++++++++++++++++++++----
+ 1 files changed, 107 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
-index ce6c7b4..a6fe63d 100644
+index c1de795..cd0c776 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -42,6 +42,8 @@
@@ -20,8 +20,8 @@ index ce6c7b4..a6fe63d 100644
+#include <mach/display.h>
#include "twl4030-generic-scripts.h"
-
-@@ -186,15 +188,6 @@ static void __init omap3_beagle_init_irq(void)
+ #include "mmc-twl4030.h"
+@@ -200,15 +202,6 @@ static void __init omap3_beagle_init_irq(void)
omap_gpio_init();
}
@@ -37,7 +37,7 @@ index ce6c7b4..a6fe63d 100644
static struct gpio_led gpio_leds[] = {
{
.name = "beagleboard::usr0",
-@@ -248,13 +241,114 @@ static struct platform_device keys_gpio = {
+@@ -262,13 +255,113 @@ static struct platform_device keys_gpio = {
},
};
@@ -68,7 +68,7 @@ index ce6c7b4..a6fe63d 100644
+};
+
+
-+static int panel_enable_tv(struct omap_display *display)
++static int beagle_panel_enable_tv(struct omap_display *display)
+{
+#define ENABLE_VDAC_DEDICATED 0x03
+#define ENABLE_VDAC_DEV_GRP 0x20
@@ -82,7 +82,7 @@ index ce6c7b4..a6fe63d 100644
+ return 0;
+}
+
-+static void panel_disable_tv(struct omap_display *display)
++static void beagle_panel_disable_tv(struct omap_display *display)
+{
+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
+ TWL4030_VDAC_DEDICATED);
@@ -94,8 +94,8 @@ index ce6c7b4..a6fe63d 100644
+ .type = OMAP_DISPLAY_TYPE_VENC,
+ .name = "tv",
+ .u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
-+ .panel_enable = panel_enable_tv,
-+ .panel_disable = panel_disable_tv,
++ .panel_enable = beagle_panel_enable_tv,
++ .panel_disable = beagle_panel_disable_tv,
+};
+
+static struct omap_dss_platform_data beagle_dss_data = {
@@ -118,10 +118,9 @@ index ce6c7b4..a6fe63d 100644
+{
+ int r;
+
-+ r = gpio_request(beagle_display_data_dvi.panel_reset_gpio, "DVI reset GPIO");
-+ if(r < 0) {
++ r = gpio_request(beagle_display_data_dvi.panel_reset_gpio, "DVI reset");
++ if (r < 0)
+ printk(KERN_ERR "Unable to get DVI reset GPIO\n");
-+ }
+}
+
+static struct omap_fbmem_config beagle_fbmem0_config = {
@@ -154,7 +153,7 @@ index ce6c7b4..a6fe63d 100644
&leds_gpio,
&keys_gpio,
};
-@@ -302,8 +396,6 @@ static void __init omap3_beagle_init(void)
+@@ -316,22 +409,20 @@ static void __init omap3_beagle_init(void)
omap3_beagle_i2c_init();
platform_add_devices(omap3_beagle_devices,
ARRAY_SIZE(omap3_beagle_devices));
@@ -162,8 +161,11 @@ index ce6c7b4..a6fe63d 100644
- omap_board_config_size = ARRAY_SIZE(omap3_beagle_config);
omap_serial_init();
- omap_cfg_reg(AH8_34XX_GPIO29);
-@@ -319,10 +411,13 @@ static void __init omap3_beagle_init(void)
+ omap_cfg_reg(J25_34XX_GPIO170);
+- gpio_request(170, "DVI_nPD");
+- /* REVISIT leave DVI powered down until it's needed ... */
+- gpio_direction_output(170, true);
+
usb_musb_init();
usb_ehci_init();
omap3beagle_flash_init();
diff --git a/packages/linux/linux-omap/0008-DSS-BEAGLE-Enable-DSS-in-beagle-defconfig.patch b/packages/linux/linux-omap/0008-DSS-BEAGLE-Enable-DSS-in-beagle-defconfig.patch
new file mode 100644
index 0000000000..f88abaacd4
--- /dev/null
+++ b/packages/linux/linux-omap/0008-DSS-BEAGLE-Enable-DSS-in-beagle-defconfig.patch
@@ -0,0 +1,453 @@
+From 54f114db20a45e99389bec9c3c630c76f3e6c043 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Fri, 7 Nov 2008 16:54:01 +0200
+Subject: [PATCH] DSS: BEAGLE: Enable DSS in beagle defconfig
+
+---
+ arch/arm/configs/omap3_beagle_defconfig | 143 ++++++++++++++++++++++---------
+ 1 files changed, 103 insertions(+), 40 deletions(-)
+
+diff --git a/arch/arm/configs/omap3_beagle_defconfig b/arch/arm/configs/omap3_beagle_defconfig
+index df67296..5036233 100644
+--- a/arch/arm/configs/omap3_beagle_defconfig
++++ b/arch/arm/configs/omap3_beagle_defconfig
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.27-omap1
+-# Fri Oct 17 14:05:39 2008
++# Linux kernel version: 2.6.28-rc3-omap1
++# Tue Nov 11 14:30:05 2008
+ #
+ CONFIG_ARM=y
+ CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+@@ -22,8 +22,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
+ # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
+-CONFIG_ARCH_SUPPORTS_AOUT=y
+-CONFIG_ZONE_DMA=y
+ CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+ CONFIG_VECTORS_BASE=0xffff0000
+ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+@@ -79,6 +77,7 @@ CONFIG_SIGNALFD=y
+ CONFIG_TIMERFD=y
+ CONFIG_EVENTFD=y
+ CONFIG_SHMEM=y
++CONFIG_AIO=y
+ CONFIG_VM_EVENT_COUNTERS=y
+ CONFIG_SLAB=y
+ # CONFIG_SLUB is not set
+@@ -87,15 +86,9 @@ CONFIG_SLAB=y
+ # CONFIG_MARKERS is not set
+ CONFIG_HAVE_OPROFILE=y
+ # CONFIG_KPROBES is not set
+-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+-# CONFIG_HAVE_IOREMAP_PROT is not set
+ CONFIG_HAVE_KPROBES=y
+ CONFIG_HAVE_KRETPROBES=y
+-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+-# CONFIG_HAVE_DMA_ATTRS is not set
+-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+ CONFIG_HAVE_CLK=y
+-CONFIG_PROC_PAGE_MONITOR=y
+ CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+ CONFIG_SLABINFO=y
+ CONFIG_RT_MUTEXES=y
+@@ -128,6 +121,7 @@ CONFIG_DEFAULT_AS=y
+ # CONFIG_DEFAULT_NOOP is not set
+ CONFIG_DEFAULT_IOSCHED="anticipatory"
+ CONFIG_CLASSIC_RCU=y
++# CONFIG_FREEZER is not set
+
+ #
+ # System Type
+@@ -168,7 +162,7 @@ CONFIG_CLASSIC_RCU=y
+ # CONFIG_ARCH_LH7A40X is not set
+ # CONFIG_ARCH_DAVINCI is not set
+ CONFIG_ARCH_OMAP=y
+-# CONFIG_ARCH_MSM7X00A is not set
++# CONFIG_ARCH_MSM is not set
+
+ #
+ # TI OMAP Implementations
+@@ -200,17 +194,27 @@ CONFIG_OMAP_DM_TIMER=y
+ # CONFIG_OMAP_LL_DEBUG_UART1 is not set
+ # CONFIG_OMAP_LL_DEBUG_UART2 is not set
+ CONFIG_OMAP_LL_DEBUG_UART3=y
++CONFIG_OMAP2_DSS=y
++# CONFIG_OMAP2_DSS_DEBUG is not set
++# CONFIG_OMAP2_DSS_RFBI is not set
++CONFIG_OMAP2_DSS_VENC=y
++# CONFIG_OMAP2_DSS_SDI is not set
++# CONFIG_OMAP2_DSS_DSI is not set
++# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
++CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
+ CONFIG_ARCH_OMAP34XX=y
+ CONFIG_ARCH_OMAP3430=y
+
+ #
+ # OMAP Board Type
+ #
++# CONFIG_MACH_NOKIA_DFL61 is not set
+ # CONFIG_MACH_OMAP_LDP is not set
+ # CONFIG_MACH_OMAP_3430SDP is not set
+ # CONFIG_MACH_OMAP3EVM is not set
+ CONFIG_MACH_OMAP3_BEAGLE=y
+ # CONFIG_MACH_OVERO is not set
++# CONFIG_MACH_OMAP3_PANDORA is not set
+ CONFIG_OMAP_TICK_GPTIMER=12
+
+ #
+@@ -263,26 +267,30 @@ CONFIG_TICK_ONESHOT=y
+ CONFIG_NO_HZ=y
+ CONFIG_HIGH_RES_TIMERS=y
+ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
+ # CONFIG_PREEMPT is not set
+ CONFIG_HZ=128
+ CONFIG_AEABI=y
+ CONFIG_OABI_COMPAT=y
+ CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+ CONFIG_SELECT_MEMORY_MODEL=y
+ CONFIG_FLATMEM_MANUAL=y
+ # CONFIG_DISCONTIGMEM_MANUAL is not set
+ # CONFIG_SPARSEMEM_MANUAL is not set
+ CONFIG_FLATMEM=y
+ CONFIG_FLAT_NODE_MEM_MAP=y
+-# CONFIG_SPARSEMEM_STATIC is not set
+-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+ CONFIG_PAGEFLAGS_EXTENDED=y
+ CONFIG_SPLIT_PTLOCK_CPUS=4
+ # CONFIG_RESOURCES_64BIT is not set
+-CONFIG_ZONE_DMA_FLAG=1
+-CONFIG_BOUNCE=y
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
+ CONFIG_VIRT_TO_BUS=y
++CONFIG_UNEVICTABLE_LRU=y
+ # CONFIG_LEDS is not set
+ CONFIG_ALIGNMENT_TRAP=y
+
+@@ -296,9 +304,10 @@ CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.16
+ # CONFIG_KEXEC is not set
+
+ #
+-# CPU Frequency scaling
++# CPU Power Management
+ #
+ # CONFIG_CPU_FREQ is not set
++# CONFIG_CPU_IDLE is not set
+
+ #
+ # Floating point emulation
+@@ -318,6 +327,8 @@ CONFIG_VFPv3=y
+ # Userspace binary formats
+ #
+ CONFIG_BINFMT_ELF=y
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_HAVE_AOUT=y
+ # CONFIG_BINFMT_AOUT is not set
+ CONFIG_BINFMT_MISC=y
+
+@@ -379,6 +390,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
+ # CONFIG_TIPC is not set
+ # CONFIG_ATM is not set
+ # CONFIG_BRIDGE is not set
++# CONFIG_NET_DSA is not set
+ # CONFIG_VLAN_8021Q is not set
+ # CONFIG_DECNET is not set
+ # CONFIG_LLC2 is not set
+@@ -399,11 +411,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
+ # CONFIG_IRDA is not set
+ # CONFIG_BT is not set
+ # CONFIG_AF_RXRPC is not set
+-
+-#
+-# Wireless
+-#
++# CONFIG_PHONET is not set
++CONFIG_WIRELESS=y
+ # CONFIG_CFG80211 is not set
++CONFIG_WIRELESS_OLD_REGULATORY=y
+ # CONFIG_WIRELESS_EXT is not set
+ # CONFIG_MAC80211 is not set
+ # CONFIG_IEEE80211 is not set
+@@ -490,6 +501,7 @@ CONFIG_MTD_NAND=y
+ # CONFIG_MTD_NAND_VERIFY_WRITE is not set
+ # CONFIG_MTD_NAND_ECC_SMC is not set
+ # CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_GPIO is not set
+ CONFIG_MTD_NAND_OMAP2=y
+ CONFIG_MTD_NAND_IDS=y
+ # CONFIG_MTD_NAND_DISKONCHIP is not set
+@@ -743,6 +755,8 @@ CONFIG_GPIO_TWL4030=y
+ # CONFIG_W1 is not set
+ # CONFIG_POWER_SUPPLY is not set
+ # CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_THERMAL_HWMON is not set
+ # CONFIG_WATCHDOG is not set
+
+ #
+@@ -760,10 +774,14 @@ CONFIG_SSB_POSSIBLE=y
+ # CONFIG_HTC_EGPIO is not set
+ # CONFIG_HTC_PASIC3 is not set
+ CONFIG_TWL4030_CORE=y
++# CONFIG_TWL4030_POWER is not set
+ # CONFIG_MFD_TMIO is not set
+ # CONFIG_MFD_T7L66XB is not set
+ # CONFIG_MFD_TC6387XB is not set
+ # CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM8350_I2C is not set
+
+ #
+ # Multimedia devices
+@@ -790,6 +808,7 @@ CONFIG_DAB=y
+ CONFIG_FB=y
+ # CONFIG_FIRMWARE_EDID is not set
+ # CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+ CONFIG_FB_CFB_FILLRECT=y
+ CONFIG_FB_CFB_COPYAREA=y
+ CONFIG_FB_CFB_IMAGEBLIT=y
+@@ -810,10 +829,22 @@ CONFIG_FB_CFB_IMAGEBLIT=y
+ #
+ # CONFIG_FB_S1D13XXX is not set
+ # CONFIG_FB_VIRTUAL is not set
+-CONFIG_FB_OMAP=y
+-# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+-# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+-CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=4
++# CONFIG_FB_METRONOME is not set
++CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=14
++CONFIG_FB_OMAP2=y
++# CONFIG_FB_OMAP2_DEBUG is not set
++# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
++
++#
++# OMAP2/3 Display Device Drivers
++#
++CONFIG_PANEL_DVI=y
++# CONFIG_PANEL_DVI_LOWLOWRES is not set
++# CONFIG_PANEL_DVI_LOWRES is not set
++CONFIG_PANEL_DVI_HIGHRES=y
++# CONFIG_PANEL_DVI_VERYHIGHRES is not set
++# CONFIG_PANEL_SDP3430 is not set
++# CONFIG_PANEL_NEVADA is not set
+ # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+ #
+@@ -862,6 +893,8 @@ CONFIG_USB_OTG=y
+ # CONFIG_USB_OTG_WHITELIST is not set
+ # CONFIG_USB_OTG_BLACKLIST_HUB is not set
+ CONFIG_USB_MON=y
++# CONFIG_USB_WUSB is not set
++# CONFIG_USB_WUSB_CBAF is not set
+
+ #
+ # USB Host Controller Drivers
+@@ -873,6 +906,7 @@ CONFIG_USB_MON=y
+ # CONFIG_USB_OHCI_HCD is not set
+ # CONFIG_USB_SL811_HCD is not set
+ # CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HWA_HCD is not set
+ CONFIG_USB_MUSB_HDRC=y
+ CONFIG_USB_MUSB_SOC=y
+
+@@ -895,6 +929,7 @@ CONFIG_USB_INVENTRA_DMA=y
+ # CONFIG_USB_ACM is not set
+ # CONFIG_USB_PRINTER is not set
+ # CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
+
+ #
+ # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+@@ -923,6 +958,7 @@ CONFIG_USB_INVENTRA_DMA=y
+ # CONFIG_USB_EMI62 is not set
+ # CONFIG_USB_EMI26 is not set
+ # CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
+ # CONFIG_USB_RIO500 is not set
+ # CONFIG_USB_LEGOTOWER is not set
+ # CONFIG_USB_LCD is not set
+@@ -939,22 +975,25 @@ CONFIG_USB_INVENTRA_DMA=y
+ # CONFIG_USB_IOWARRIOR is not set
+ # CONFIG_USB_TEST is not set
+ # CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_VST is not set
+ CONFIG_USB_GADGET=y
+ # CONFIG_USB_GADGET_DEBUG is not set
+ # CONFIG_USB_GADGET_DEBUG_FILES is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
+ CONFIG_USB_GADGET_SELECTED=y
+-# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_AT91 is not set
+ # CONFIG_USB_GADGET_ATMEL_USBA is not set
+ # CONFIG_USB_GADGET_FSL_USB2 is not set
+-# CONFIG_USB_GADGET_NET2280 is not set
+-# CONFIG_USB_GADGET_PXA25X is not set
+-# CONFIG_USB_GADGET_M66592 is not set
+-# CONFIG_USB_GADGET_PXA27X is not set
+-# CONFIG_USB_GADGET_GOKU is not set
+ # CONFIG_USB_GADGET_LH7A40X is not set
+ # CONFIG_USB_GADGET_OMAP is not set
++# CONFIG_USB_GADGET_PXA25X is not set
++# CONFIG_USB_GADGET_PXA27X is not set
+ # CONFIG_USB_GADGET_S3C2410 is not set
+-# CONFIG_USB_GADGET_AT91 is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_FSL_QE is not set
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_GOKU is not set
+ # CONFIG_USB_GADGET_DUMMY_HCD is not set
+ CONFIG_USB_GADGET_DUALSPEED=y
+ # CONFIG_USB_ZERO is not set
+@@ -971,7 +1010,7 @@ CONFIG_MMC=y
+ # CONFIG_MMC_UNSAFE_RESUME is not set
+
+ #
+-# MMC/SD Card Drivers
++# MMC/SD/SDIO Card Drivers
+ #
+ CONFIG_MMC_BLOCK=y
+ CONFIG_MMC_BLOCK_BOUNCE=y
+@@ -979,10 +1018,12 @@ CONFIG_MMC_BLOCK_BOUNCE=y
+ # CONFIG_MMC_TEST is not set
+
+ #
+-# MMC/SD Host Controller Drivers
++# MMC/SD/SDIO Host Controller Drivers
+ #
+ # CONFIG_MMC_SDHCI is not set
+ CONFIG_MMC_OMAP_HS=y
++# CONFIG_MEMSTICK is not set
++# CONFIG_ACCESSIBILITY is not set
+ # CONFIG_NEW_LEDS is not set
+ CONFIG_RTC_LIB=y
+ CONFIG_RTC_CLASS=y
+@@ -1024,12 +1065,15 @@ CONFIG_RTC_DRV_TWL4030=y
+ # Platform RTC drivers
+ #
+ # CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
+ # CONFIG_RTC_DRV_DS1511 is not set
+ # CONFIG_RTC_DRV_DS1553 is not set
+ # CONFIG_RTC_DRV_DS1742 is not set
+ # CONFIG_RTC_DRV_STK17TA8 is not set
+ # CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
+ # CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
+ # CONFIG_RTC_DRV_V3020 is not set
+
+ #
+@@ -1059,11 +1103,12 @@ CONFIG_EXT2_FS=y
+ # CONFIG_EXT2_FS_XIP is not set
+ CONFIG_EXT3_FS=y
+ # CONFIG_EXT3_FS_XATTR is not set
+-# CONFIG_EXT4DEV_FS is not set
++# CONFIG_EXT4_FS is not set
+ CONFIG_JBD=y
+ # CONFIG_REISERFS_FS is not set
+ # CONFIG_JFS_FS is not set
+ # CONFIG_FS_POSIX_ACL is not set
++CONFIG_FILE_LOCKING=y
+ # CONFIG_XFS_FS is not set
+ # CONFIG_OCFS2_FS is not set
+ CONFIG_DNOTIFY=y
+@@ -1100,6 +1145,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+ #
+ CONFIG_PROC_FS=y
+ CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
+ CONFIG_SYSFS=y
+ CONFIG_TMPFS=y
+ # CONFIG_TMPFS_POSIX_ACL is not set
+@@ -1148,6 +1194,7 @@ CONFIG_LOCKD_V4=y
+ CONFIG_NFS_COMMON=y
+ CONFIG_SUNRPC=y
+ CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_REGISTER_V4 is not set
+ CONFIG_RPCSEC_GSS_KRB5=y
+ # CONFIG_RPCSEC_GSS_SPKM3 is not set
+ # CONFIG_SMB_FS is not set
+@@ -1260,15 +1307,23 @@ CONFIG_DEBUG_INFO=y
+ CONFIG_FRAME_POINTER=y
+ # CONFIG_BOOT_PRINTK_DELAY is not set
+ # CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+ # CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+ # CONFIG_FAULT_INJECTION is not set
+ # CONFIG_LATENCYTOP is not set
+-CONFIG_HAVE_FTRACE=y
+-CONFIG_HAVE_DYNAMIC_FTRACE=y
+-# CONFIG_FTRACE is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++
++#
++# Tracers
++#
++# CONFIG_FUNCTION_TRACER is not set
+ # CONFIG_IRQSOFF_TRACER is not set
+ # CONFIG_SCHED_TRACER is not set
+ # CONFIG_CONTEXT_SWITCH_TRACER is not set
++# CONFIG_BOOT_TRACER is not set
++# CONFIG_STACK_TRACER is not set
++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+ # CONFIG_SAMPLES is not set
+ CONFIG_HAVE_ARCH_KGDB=y
+ # CONFIG_KGDB is not set
+@@ -1282,14 +1337,19 @@ CONFIG_HAVE_ARCH_KGDB=y
+ #
+ # CONFIG_KEYS is not set
+ # CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
+ # CONFIG_SECURITY_FILE_CAPABILITIES is not set
+ CONFIG_CRYPTO=y
+
+ #
+ # Crypto core or helper
+ #
++# CONFIG_CRYPTO_FIPS is not set
+ CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_AEAD=y
+ CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_RNG=y
+ CONFIG_CRYPTO_MANAGER=y
+ # CONFIG_CRYPTO_GF128MUL is not set
+ # CONFIG_CRYPTO_NULL is not set
+@@ -1362,14 +1422,17 @@ CONFIG_CRYPTO_DES=y
+ #
+ # CONFIG_CRYPTO_DEFLATE is not set
+ # CONFIG_CRYPTO_LZO is not set
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
+ CONFIG_CRYPTO_HW=y
+
+ #
+ # Library routines
+ #
+ CONFIG_BITREVERSE=y
+-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+ CONFIG_CRC_CCITT=y
+ # CONFIG_CRC16 is not set
+ # CONFIG_CRC_T10DIF is not set
+--
+1.5.6.3
+
diff --git a/packages/linux/linux-omap/0011-DSS-support-for-OMAP3-SDP-board.patch b/packages/linux/linux-omap/0009-DSS-support-for-OMAP3-SDP-board.patch
index 1e23a192b1..4c22a89929 100644
--- a/packages/linux/linux-omap/0011-DSS-support-for-OMAP3-SDP-board.patch
+++ b/packages/linux/linux-omap/0009-DSS-support-for-OMAP3-SDP-board.patch
@@ -1,4 +1,4 @@
-From 69302d06679f25f940f5ee3cb8c51c1becf46e52 Mon Sep 17 00:00:00 2001
+From b51518d69d562d275afc830373710417e507c613 Mon Sep 17 00:00:00 2001
From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Date: Mon, 20 Oct 2008 13:13:15 +0300
Subject: [PATCH] DSS: support for OMAP3 SDP board
@@ -13,7 +13,7 @@ Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
create mode 100644 drivers/video/omap2/panel-sdp3430.c
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
-index 8773698..b910bc6 100644
+index 7ee85e9..f226a55 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -40,6 +40,8 @@
@@ -25,7 +25,7 @@ index 8773698..b910bc6 100644
#include <asm/io.h>
#include <asm/delay.h>
-@@ -239,14 +241,224 @@ static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
+@@ -240,14 +242,224 @@ static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
},
};
@@ -71,20 +71,20 @@ index 8773698..b910bc6 100644
+static int lcd_enabled;
+static int dvi_enabled;
+
-+static void __init display_init(void)
++static void __init sdp3430_display_init(void)
+{
+ int r;
+
+ enable_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO;
+ backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
+
-+ r = gpio_request(enable_gpio, "OMAP SDP LCD Reset GPIO");
++ r = gpio_request(enable_gpio, "LCD reset");
+ if (r) {
+ printk(KERN_ERR "failed to get LCD reset GPIO\n");
+ goto err0;
+ }
+
-+ r = gpio_request(backlight_gpio, "OMAP SDP LCD Backlight GPIO");
++ r = gpio_request(backlight_gpio, "LCD Backlight");
+ if (r) {
+ printk(KERN_ERR "failed to get LCD backlight GPIO\n");
+ goto err1;
@@ -101,7 +101,7 @@ index 8773698..b910bc6 100644
+}
+
+
-+static int panel_enable_lcd(struct omap_display *display)
++static int sdp3430_panel_enable_lcd(struct omap_display *display)
+{
+ u8 ded_val, ded_reg;
+ u8 grp_val, grp_reg;
@@ -136,7 +136,7 @@ index 8773698..b910bc6 100644
+ return 0;
+}
+
-+static void panel_disable_lcd(struct omap_display *display)
++static void sdp3430_panel_disable_lcd(struct omap_display *display)
+{
+ lcd_enabled = 0;
+
@@ -150,16 +150,16 @@ index 8773698..b910bc6 100644
+ }
+}
+
-+static struct omap_display_data sdp_display_data = {
++static struct omap_display_data sdp3430_display_data = {
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .name = "lcd",
+ .panel_name = "panel-sdp3430",
+ .u.dpi.data_lines = 16,
-+ .panel_enable = panel_enable_lcd,
-+ .panel_disable = panel_disable_lcd,
++ .panel_enable = sdp3430_panel_enable_lcd,
++ .panel_disable = sdp3430_panel_disable_lcd,
+};
+
-+static int panel_enable_dvi(struct omap_display *display)
++static int sdp3430_panel_enable_dvi(struct omap_display *display)
+{
+ if (lcd_enabled) {
+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
@@ -178,7 +178,7 @@ index 8773698..b910bc6 100644
+ return 0;
+}
+
-+static void panel_disable_dvi(struct omap_display *display)
++static void sdp3430_panel_disable_dvi(struct omap_display *display)
+{
+ dvi_enabled = 0;
+
@@ -190,16 +190,16 @@ index 8773698..b910bc6 100644
+}
+
+
-+static struct omap_display_data sdp_display_data_dvi = {
++static struct omap_display_data sdp3430_display_data_dvi = {
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .name = "dvi",
+ .panel_name = "panel-dvi",
+ .u.dpi.data_lines = 24,
-+ .panel_enable = panel_enable_dvi,
-+ .panel_disable = panel_disable_dvi,
++ .panel_enable = sdp3430_panel_enable_dvi,
++ .panel_disable = sdp3430_panel_disable_dvi,
+};
+
-+static int panel_enable_tv(struct omap_display *display)
++static int sdp3430_panel_enable_tv(struct omap_display *display)
+{
+#define ENABLE_VDAC_DEDICATED 0x03
+#define ENABLE_VDAC_DEV_GRP 0x20
@@ -213,7 +213,7 @@ index 8773698..b910bc6 100644
+ return 0;
+}
+
-+static void panel_disable_tv(struct omap_display *display)
++static void sdp3430_panel_disable_tv(struct omap_display *display)
+{
+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
+ TWL4030_VDAC_DEDICATED);
@@ -221,20 +221,20 @@ index 8773698..b910bc6 100644
+ TWL4030_VDAC_DEV_GRP);
+}
+
-+static struct omap_display_data sdp_display_data_tv = {
++static struct omap_display_data sdp3430_display_data_tv = {
+ .type = OMAP_DISPLAY_TYPE_VENC,
+ .name = "tv",
+ .u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
-+ .panel_enable = panel_enable_tv,
-+ .panel_disable = panel_disable_tv,
++ .panel_enable = sdp3430_panel_enable_tv,
++ .panel_disable = sdp3430_panel_disable_tv,
+};
+
+static struct omap_dss_platform_data sdp3430_dss_data = {
+ .num_displays = 3,
+ .displays = {
-+ &sdp_display_data,
-+ &sdp_display_data_dvi,
-+ &sdp_display_data_tv,
++ &sdp3430_display_data,
++ &sdp3430_display_data_dvi,
++ &sdp3430_display_data_tv,
+ }
+};
+
@@ -254,7 +254,7 @@ index 8773698..b910bc6 100644
};
static inline void __init sdp3430_init_smc91x(void)
-@@ -293,13 +505,11 @@ static struct omap_uart_config sdp3430_uart_config __initdata = {
+@@ -294,13 +506,11 @@ static struct omap_uart_config sdp3430_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
@@ -271,20 +271,20 @@ index 8773698..b910bc6 100644
};
static int sdp3430_batt_table[] = {
-@@ -450,8 +660,6 @@ static void __init omap_3430sdp_init(void)
+@@ -467,8 +677,6 @@ static void __init omap_3430sdp_init(void)
{
omap3430_i2c_init();
platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
- omap_board_config = sdp3430_config;
- omap_board_config_size = ARRAY_SIZE(sdp3430_config);
- if (system_rev > OMAP3430_REV_ES1_0)
+ if (omap_rev() > OMAP3430_REV_ES1_0)
ts_gpio = OMAP34XX_TS_GPIO_IRQ_SDPV2;
else
-@@ -466,10 +674,14 @@ static void __init omap_3430sdp_init(void)
+@@ -483,10 +691,14 @@ static void __init omap_3430sdp_init(void)
usb_musb_init();
usb_ehci_init();
- hsmmc_init();
-+ display_init();
+ hsmmc_init(mmc);
++ sdp3430_display_init();
}
static void __init omap_3430sdp_map_io(void)
@@ -296,10 +296,10 @@ index 8773698..b910bc6 100644
omap2_map_common_io();
}
diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
-index 4584e1b..95691ad 100644
+index 996f047..f4e450d 100644
--- a/drivers/video/omap2/Kconfig
+++ b/drivers/video/omap2/Kconfig
-@@ -45,5 +45,10 @@ config PANEL_DVI_VERYHIGHRES
+@@ -48,5 +48,10 @@ config PANEL_DVI_VERYHIGHRES
endchoice
diff --git a/packages/linux/linux-omap/beagleboard/defconfig b/packages/linux/linux-omap/beagleboard/defconfig
index 56dea7e122..22c29fb23c 100644
--- a/packages/linux/linux-omap/beagleboard/defconfig
+++ b/packages/linux/linux-omap/beagleboard/defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28-rc3-omap1
-# Sat Nov 8 08:59:05 2008
+# Tue Nov 11 15:45:33 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -203,7 +203,8 @@ CONFIG_OMAP2_DSS_DEBUG=y
# CONFIG_OMAP2_DSS_RFBI is not set
CONFIG_OMAP2_DSS_VENC=y
# CONFIG_OMAP2_DSS_SDI is not set
-# CONFIG_OMAP2_DSS_DSI is not set
+CONFIG_OMAP2_DSS_DSI=y
+CONFIG_OMAP2_DSS_USE_DSI_PLL=y
# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4
CONFIG_ARCH_OMAP34XX=y
@@ -1322,9 +1323,11 @@ CONFIG_FB_OMAP2_DEBUG=y
# OMAP2/3 Display Device Drivers
#
CONFIG_PANEL_DVI=y
+# CONFIG_PANEL_DVI_LOWLOWRES is not set
# CONFIG_PANEL_DVI_LOWRES is not set
CONFIG_PANEL_DVI_HIGHRES=y
# CONFIG_PANEL_DVI_VERYHIGHRES is not set
+# CONFIG_PANEL_SDP3430 is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
@@ -1384,7 +1387,10 @@ CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_SOC=y
CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y
# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_TWL4030=y
# CONFIG_SOUND_PRIME is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
diff --git a/packages/linux/linux-omap/fix-asoc.diff b/packages/linux/linux-omap/fix-asoc.diff
new file mode 100644
index 0000000000..4948e932fb
--- /dev/null
+++ b/packages/linux/linux-omap/fix-asoc.diff
@@ -0,0 +1,130 @@
+From linux-omap-owner@vger.kernel.org Mon Nov 10 23:48:17 2008
+Date: Mon, 10 Nov 2008 14:36:32 -0800
+From: "Steve Sakoman" <sakoman@gmail.com>
+To: "Philip Balister" <philip@balister.org>
+Subject: Re: ASOC and the Beagle
+Cc: "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
+ "Tony Lindgren" <tony@atomide.com>
+
+On Mon, Nov 10, 2008 at 12:38 PM, Steve Sakoman <sakoman@gmail.com> wrote:
+> On Mon, Nov 10, 2008 at 7:10 AM, Philip Balister <philip@balister.org> wrote:
+>> A few weeks ago kernels built from git would detect the sound hardware and
+>> actually work.
+>>
+>> Yesterday I build a kernel and the sound hardware is no longer detected. Is
+>> there an easy way to fix this?
+>>
+>> Sorry I'm so vague, I don't have all the revision data handy ....
+>
+> I just noticed this too.
+>
+> It seems that the Kconfig for soc/omap got damaged in the merge.
+>
+> The fix is simple, patch below.
+
+Next time I should build test before posting :-)
+
+Turns out that the Makefile for soc/omap and the Kconfig and Makefile
+for soc/codec also got screwed up in the merge, so those need to be
+fixed.
+
+The complete fix is:
+
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index 38a0e3b..5df7402 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -10,6 +10,7 @@ config SND_SOC_ALL_CODECS
+ select SND_SOC_TLV320AIC23
+ select SND_SOC_TLV320AIC26
+ select SND_SOC_TLV320AIC3X
++ select SND_SOC_TWL4030
+ select SND_SOC_UDA1380
+ select SND_SOC_WM8510
+ select SND_SOC_WM8580
+@@ -75,6 +76,10 @@ config SND_SOC_TLV320AIC3X
+ tristate
+ depends on I2C
+
++config SND_SOC_TWL4030
++ tristate
++ depends on TWL4030_CORE
++
+ config SND_SOC_UDA1380
+ tristate
+
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index 90f0a58..3b9b58a 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -7,6 +7,7 @@ snd-soc-ssm2602-objs := ssm2602.o
+ snd-soc-tlv320aic23-objs := tlv320aic23.o
+ snd-soc-tlv320aic26-objs := tlv320aic26.o
+ snd-soc-tlv320aic3x-objs := tlv320aic3x.o
++snd-soc-twl4030-objs := twl4030.o
+ snd-soc-uda1380-objs := uda1380.o
+ snd-soc-wm8510-objs := wm8510.o
+ snd-soc-wm8580-objs := wm8580.o
+@@ -29,6 +30,7 @@ obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o
+ obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o
+ obj-$(CONFIG_SND_SOC_TLV320AIC26) += snd-soc-tlv320aic26.o
+ obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o
++obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o
+ obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o
+ obj-$(CONFIG_SND_SOC_WM8510) += snd-soc-wm8510.o
+ obj-$(CONFIG_SND_SOC_WM8580) += snd-soc-wm8580.o
+diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
+index 8b7766b..0daeee4 100644
+--- a/sound/soc/omap/Kconfig
++++ b/sound/soc/omap/Kconfig
+@@ -14,6 +14,14 @@ config SND_OMAP_SOC_N810
+ help
+ Say Y if you want to add support for SoC audio on Nokia N810.
+
++config SND_OMAP_SOC_OMAP3_BEAGLE
++ tristate "SoC Audio support for OMAP3 Beagle"
++ depends on SND_OMAP_SOC && MACH_OMAP3_BEAGLE
++ select SND_OMAP_SOC_MCBSP
++ select SND_SOC_TWL4030
++ help
++ Say Y if you want to add support for SoC audio on the Beagleboard.
++
+ config SND_OMAP_SOC_OSK5912
+ tristate "SoC Audio support for omap osk5912"
+ depends on SND_OMAP_SOC && MACH_OMAP_OSK
+@@ -21,3 +29,13 @@ config SND_OMAP_SOC_OSK5912
+ select SND_SOC_TLV320AIC23
+ help
+ Say Y if you want to add support for SoC audio on osk5912.
++
++config SND_OMAP_SOC_OVERO
++ tristate "SoC Audio support for Gumstix Overo"
++ depends on SND_OMAP_SOC && MACH_OVERO
++ select SND_OMAP_SOC_MCBSP
++ select SND_SOC_TWL4030
++ help
++ Say Y if you want to add support for SoC audio on the Gumstix Overo.
++
++
+diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
+index e09d1f2..4bae404 100644
+--- a/sound/soc/omap/Makefile
++++ b/sound/soc/omap/Makefile
+@@ -7,7 +7,12 @@ obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o
+
+ # OMAP Machine Support
+ snd-soc-n810-objs := n810.o
++snd-soc-omap3beagle-objs := omap3beagle.o
+ snd-soc-osk5912-objs := osk5912.o
++snd-soc-overo-objs := overo.o
+
+ obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o
++obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o
+ obj-$(CONFIG_SND_OMAP_SOC_OSK5912) += snd-soc-osk5912.o
++obj-$(CONFIG_SND_OMAP_SOC_OVERO) += snd-soc-overo.o
++
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at http://vger.kernel.org/majordomo-info.html
+
diff --git a/packages/linux/linux-omap_git.bb b/packages/linux/linux-omap_git.bb
index 66029225c4..109dcdffd8 100644
--- a/packages/linux/linux-omap_git.bb
+++ b/packages/linux/linux-omap_git.bb
@@ -6,11 +6,11 @@ KERNEL_IMAGETYPE = "uImage"
COMPATIBLE_MACHINE = "omap5912osk|omap1710h3|omap2430sdp|omap2420h4|beagleboard|omap3evm"
-SRCREV = "f7429fd378a29cf6947c2613e0fd6e6e36165167"
+SRCREV = "444fcab6e8f8bad4ffc50feb91516c246d91e901"
PV = "2.6.27+2.6.28-rc3+${PR}+gitr${SRCREV}"
#PV = "2.6.27+${PR}+gitr${SRCREV}"
-PR = "r1"
+PR = "r2"
SRC_URI = "git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git;protocol=git \
file://defconfig"
@@ -36,12 +36,12 @@ SRC_URI_append = " \
file://0001-Implement-downsampling-with-debugs.patch;patch=1 \
file://0003-DSS-Documentation-for-OMAP2-3-display-subsystem.patch;patch=1 \
file://0004-DSS-New-display-subsystem-driver-for-OMAP2-3.patch;patch=1 \
- file://0005-DSS-RFBI-support-for-OMAP2-3-DSS.patch;patch=1 \
- file://0006-DSS-TV-out-support-for-OMAP2-3-DSS.patch;patch=1 \
- file://0007-DSS-DSI-support-for-OMAP2-3-DSS.patch;patch=1 \
- file://0008-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch;patch=1 \
- file://0009-DSS-Add-generic-DVI-panel.patch;patch=1 \
- file://0010-DSS-support-for-Beagle-Board.patch;patch=1 \
+ file://0005-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch;patch=1 \
+ file://0006-DSS-Add-generic-DVI-panel.patch;patch=1 \
+ file://0007-DSS-support-for-Beagle-Board.patch;patch=1 \
+ file://0008-DSS-BEAGLE-Enable-DSS-in-beagle-defconfig.patch;patch=1 \
+ file://0009-DSS-support-for-OMAP3-SDP-board.patch;patch=1 \
+ file://fix-asoc.diff;patch=1 \
"
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 04:47:47 +0000