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authorPaul Sokolovsky <pmiscml@gmail.com>2007-06-14 04:51:44 +0000
committerPaul Sokolovsky <pmiscml@gmail.com>2007-06-14 04:51:44 +0000
commit998f6f792ea953caf0ca7ab8b7fbe858d68a510f (patch)
tree90754e0b123fbf58fc099648a68eae3dda0f8004 /packages/uboot/u-boot-mkimage-gta01-native/uboot-neo1973-resume.patch
parent60dfd703b4c5180533ec14102c276fc4fb70a5a3 (diff)
parent1d4ca5c243ec65cf27ec1d4d908163da029e6fcc (diff)
merge of '443650a5c3bfafa4e922391b71d87087c6b6f355'
and 'a59cc92c385b66015a1eb53d505bf4f139187778'
Diffstat (limited to 'packages/uboot/u-boot-mkimage-gta01-native/uboot-neo1973-resume.patch')
-rw-r--r--packages/uboot/u-boot-mkimage-gta01-native/uboot-neo1973-resume.patch113
1 files changed, 113 insertions, 0 deletions
diff --git a/packages/uboot/u-boot-mkimage-gta01-native/uboot-neo1973-resume.patch b/packages/uboot/u-boot-mkimage-gta01-native/uboot-neo1973-resume.patch
new file mode 100644
index 0000000000..19d912620d
--- /dev/null
+++ b/packages/uboot/u-boot-mkimage-gta01-native/uboot-neo1973-resume.patch
@@ -0,0 +1,113 @@
+Resume support for low-level uboot code, Version 5
+
+Signed-off-by: Ben Dooks <ben-linux@fluff.org>
+
+Index: u-boot/cpu/arm920t/start.S
+===================================================================
+--- u-boot.orig/cpu/arm920t/start.S 2007-02-28 03:51:24.000000000 +0100
++++ u-boot/cpu/arm920t/start.S 2007-03-01 02:43:47.000000000 +0100
+@@ -158,18 +158,68 @@
+ str r1, [r0]
+ # endif
+
++ /* default FCLK is 202 MHz ! */
++#define LOCKTIME 0x4c000000
++#define UPLLCON 0x4c000008
++//#define MPLLCFG ((0x90 << 12) + (0x2 << 4) + 0x2)
++#define MPLLCFG ((0x90 << 12) + (0x7 << 4) + 0x0)
++#define UPLLCFG ((0x78 << 12) + (0x2 << 4) + 0x3)
++ ldr r0, =LOCKTIME
++ mov r1, #0xffffff
++ str r1, [r0]
++
++ ldr r0, =UPLLCON
++ ldr r1, =UPLLCFG
++ str r1, [r0]
++
++ /* Page 7-19, seven nops between UPLL and MPLL */
++ nop
++ nop
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ ldr r1, =MPLLCFG
++ str r1, [r0, #-4] /* MPLLCON */
++
+ /* FCLK:HCLK:PCLK = 1:2:4 */
+- /* default FCLK is 120 MHz ! */
+ ldr r0, =CLKDIVN
+ mov r1, #3
+ str r1, [r0]
++
++#if 1
++ /* enable uart */
++ ldr r0, =0x4c00000c /* clkcon */
++ ldr r1, =0x7fff0 /* all clocks on */
++ str r1, [r0]
++
++ /* gpio UART0 init */
++ ldr r0, =0x56000070
++ mov r1, #0xaa
++ str r1, [r0]
++
++ /* init uart */
++ ldr r0, =0x50000000
++ mov r1, #0x03
++ str r1, [r0]
++ ldr r1, =0x245
++ str r1, [r0, #0x04]
++ mov r1, #0x01
++ str r1, [r0, #0x08]
++ mov r1, #0x00
++ str r1, [r0, #0x0c]
++ mov r1, #0x1a
++ str r1, [r0, #0x28]
++#endif
++
+ #endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
+
+ #ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ #ifndef CONFIG_LL_INIT_NAND_ONLY
+ bl cpu_init_crit
+ #endif
+-#endif
+
+ #ifndef CONFIG_SKIP_RELOCATE_UBOOT
+ adr r0, _start /* r0 <- current position of code */
+@@ -202,9 +252,33 @@
+
+ #ifdef CONFIG_S3C2410_NAND_BOOT
+ nand_load:
++ /* take sdram out of power down */
++ ldr r0, =0x56000080 /* misccr */
++ ldr r1, [ r0 ]
++ bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE)
++ str r1, [ r0 ]
++
++ /* ensure signals stabalise */
++ mov r1, #128
++1: subs r1, r1, #1
++ bpl 1b
++
+ #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
+ bl cpu_init_crit
+ #endif
++#if defined(CONFIG_S3C2410)
++ /* ensure some refresh has happened */
++ ldr r1, =0xfffff
++1: subs r1, r1, #1
++ bpl 1b
++
++ /* test for resume */
++ ldr r1, =0x560000B4 /* gstatus2 */
++ ldr r0, [ r1 ]
++ tst r0, #0x02 /* is this resume from power down */
++ ldrne pc, [r1, #4] /* gstatus3 */
++#endif /* CONFIG_S3C2410 */
++#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+ /* mov r10, lr */
+