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authorKoen Kooi <koen@openembedded.org>2008-06-24 19:47:17 +0000
committerKoen Kooi <koen@openembedded.org>2008-06-24 19:47:17 +0000
commit561ae8afba41ca0d712713acd11e1865f2f208df (patch)
treea3368f61d72609324a3b232a64e16c3dc0c19dff /packages/linux
parent372d39e40ebabb739e1e4d727b8a9253569c8c43 (diff)
linux-omap2 git: add DPLL patches for beagleboard
Diffstat (limited to 'packages/linux')
-rw-r--r--packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch114
-rw-r--r--packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch95
-rw-r--r--packages/linux/linux-omap2_git.bb4
3 files changed, 212 insertions, 1 deletions
diff --git a/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch b/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch
new file mode 100644
index 0000000000..25e5aad9c9
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch
@@ -0,0 +1,114 @@
+From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008
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+Date: Tue, 24 Jun 2008 01:12:35 -0600 (MDT)
+From: Paul Walmsley <paul@pwsan.com>
+To: linux-omap@vger.kernel.org
+Subject: [PATCH] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4
+Message-ID: <alpine.DEB.1.00.0806240111320.9741@utopia.booyaka.com>
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+
+
+OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and
+DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this
+into the OMAP3 clock framework.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+
+ arch/arm/mach-omap2/clock34xx.h | 20 ++++++++++++++++----
+ 1 files changed, 16 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
+index b4dceea..9605744 100644
+--- a/arch/arm/mach-omap2/clock34xx.h
++++ b/arch/arm/mach-omap2/clock34xx.h
+@@ -1029,8 +1029,15 @@ static struct clk corex2_fck = {
+
+ /* DPLL power domain clock controls */
+
+-static const struct clksel div2_core_clksel[] = {
+- { .parent = &core_ck, .rates = div2_rates },
++static const struct clksel_rate div4_rates[] = {
++ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
++ { .div = 2, .val = 2, .flags = RATE_IN_343X },
++ { .div = 4, .val = 4, .flags = RATE_IN_343X },
++ { .div = 0 }
++};
++
++static const struct clksel div4_core_clksel[] = {
++ { .parent = &core_ck, .rates = div4_rates },
+ { .parent = NULL }
+ };
+
+@@ -1044,7 +1051,7 @@ static struct clk dpll1_fck = {
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
+- .clksel = div2_core_clksel,
++ .clksel = div4_core_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+@@ -1119,7 +1126,7 @@ static struct clk dpll2_fck = {
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
+- .clksel = div2_core_clksel,
++ .clksel = div4_core_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+@@ -1155,6 +1162,11 @@ static struct clk iva2_ck = {
+
+ /* Common interface clocks */
+
++static const struct clksel div2_core_clksel[] = {
++ { .parent = &core_ck, .rates = div2_rates },
++ { .parent = NULL }
++};
++
+ static struct clk l3_ick = {
+ .name = "l3_ick",
+ .parent = &core_ck,
+--
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+the body of a message to majordomo@vger.kernel.org
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+
diff --git a/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch b/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch
new file mode 100644
index 0000000000..2e0dfd9f13
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch
@@ -0,0 +1,95 @@
+From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008
+Received: from localhost
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+Date: Tue, 24 Jun 2008 01:11:21 -0600 (MDT)
+From: Paul Walmsley <paul@pwsan.com>
+To: linux-omap@vger.kernel.org
+Subject: [PATCH] OMAP3 clock: fix DPLL jitter correction and rate
+ programming
+Message-ID: <alpine.DEB.1.00.0806240109440.9741@utopia.booyaka.com>
+User-Agent: Alpine 1.00 (DEB 882 2007-12-20)
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+
+
+Fix DPLL jitter correction programming. Previously,
+omap3_noncore_dpll_program() stored the FREQSEL jitter correction
+parameter to the wrong register. This caused jitter correction to be set
+incorrectly and also caused the DPLL divider to be programmed incorrectly.
+
+Also, fix DPLL divider programming. An off-by-one error existed in
+omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher
+divider than intended.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+
+ arch/arm/mach-omap2/clock34xx.c | 13 ++++++++-----
+ 1 files changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
+index 408b51a..8fdf8f3 100644
+--- a/arch/arm/mach-omap2/clock34xx.c
++++ b/arch/arm/mach-omap2/clock34xx.c
+@@ -346,14 +346,17 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
+ /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
+ _omap3_noncore_dpll_bypass(clk);
+
++ /* Set jitter correction */
++ v = __raw_readl(dd->control_reg);
++ v &= ~dd->freqsel_mask;
++ v |= freqsel << __ffs(dd->freqsel_mask);
++ __raw_writel(v, dd->control_reg);
++
++ /* Set DPLL multiplier, divider */
+ v = __raw_readl(dd->mult_div1_reg);
+ v &= ~(dd->mult_mask | dd->div1_mask);
+-
+- /* Set mult (M), div1 (N), freqsel */
+ v |= m << __ffs(dd->mult_mask);
+- v |= n << __ffs(dd->div1_mask);
+- v |= freqsel << __ffs(dd->freqsel_mask);
+-
++ v |= (n - 1) << __ffs(dd->div1_mask);
+ __raw_writel(v, dd->mult_div1_reg);
+
+ /* We let the clock framework set the other output dividers later */
+--
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+
diff --git a/packages/linux/linux-omap2_git.bb b/packages/linux/linux-omap2_git.bb
index 8c83d8f6ca..29cfb35bdb 100644
--- a/packages/linux/linux-omap2_git.bb
+++ b/packages/linux/linux-omap2_git.bb
@@ -5,7 +5,7 @@ FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/linux-omap2-git/${MA
SRCREV = "6604ac6c8a14d583a463159f3a1601427dab7e05"
PV = "2.6.25+2.6.26-rc7+${PR}+git${SRCREV}"
-PR = "r29"
+PR = "r30"
SRC_URI = "git://source.mvista.com/git/linux-omap-2.6.git;protocol=git \
@@ -20,6 +20,8 @@ SRC_URI_append_beagleboard = " file://no-harry-potter.diff;patch=1 \
file://fix-dispc-clocks.patch;patch=1 \
file://soc.patch;patch=1 \
file://16bpp.patch;patch=1 \
+ file://omap3-dppl-divider.patch;patch=1 \
+ file://omap3-jitter.patch;patch=1 \
"
SRC_URI_append_omap3evm = " file://no-harry-potter.diff;patch=1 \