linux-omap2 : Remove patches that are now available from kernel git repository,

3 files changed, 0 insertions, 2281 deletions

diff --git a/packages/linux/linux-omap2-git/beagleboard/0001-ARM-OMAP-SmartReflex-driver.patch b/packages/linux/linux-omap2-git/beagleboard/0001-ARM-OMAP-SmartReflex-driver.patch
deleted file mode 100644
index 550a4f58be..0000000000
--- a/packages/linux/linux-omap2-git/beagleboard/0001-ARM-OMAP-SmartReflex-driver.patch
+++ /dev/null
@@ -1,1002 +0,0 @@
-From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
-To: linux-omap@vger.kernel.org
-Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
-Subject: [PATCH 1/3] ARM: OMAP: SmartReflex driver, reference source and header files
-Date: 	Mon,  2 Jun 2008 14:30:12 +0300
-
-The following patch set integrates TI's SmartReflex driver. SmartReflex is a
-module that adjusts OMAP3 VDD1 and VDD2 operating voltages around the nominal
-values of current operating point depending on silicon characteristics and
-operating conditions.
-
-The driver creates two sysfs entries into /sys/power/ named "sr_vdd1_autocomp"
-and "sr_vdd2_autocomp" which can be used to activate SmartReflex modules 1 and
-2.
-
-Use the following commands to enable SmartReflex:
-
-echo -n 1 > /sys/power/sr_vdd1_autocomp
-echo -n 1 > /sys/power/sr_vdd2_autocomp
-
-To disable:
-
-echo -n 0 > /sys/power/sr_vdd1_autocomp
-echo -n 0 > /sys/power/sr_vdd2_autocomp
-
-This particular patch adds the TI reference source and header files for
-SmartReflex. Only modifications include minor styling to pass checkpatch.pl
-test.
-
-Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
----
- arch/arm/mach-omap2/smartreflex.c |  815 +++++++++++++++++++++++++++++++++++++
- arch/arm/mach-omap2/smartreflex.h |  136 ++++++
- 2 files changed, 951 insertions(+), 0 deletions(-)
- create mode 100644 arch/arm/mach-omap2/smartreflex.c
- create mode 100644 arch/arm/mach-omap2/smartreflex.h
-
-diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
-new file mode 100644
-index 0000000..dae7460
---- /dev/null
-+++ b/arch/arm/mach-omap2/smartreflex.c
-@@ -0,0 +1,815 @@
-+/*
-+ * linux/arch/arm/mach-omap3/smartreflex.c
-+ *
-+ * OMAP34XX SmartReflex Voltage Control
-+ *
-+ * Copyright (C) 2007 Texas Instruments, Inc.
-+ * Lesly A M <x0080970@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/clk.h>
-+#include <linux/sysfs.h>
-+
-+#include <asm/arch/prcm.h>
-+#include <asm/arch/power_companion.h>
-+#include <linux/io.h>
-+
-+#include "prcm-regs.h"
-+#include "smartreflex.h"
-+
-+
-+/* #define DEBUG_SR 1 */
-+#ifdef DEBUG_SR
-+#  define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__ ,\
-+									## args)
-+#else
-+#  define DPRINTK(fmt, args...)
-+#endif
-+
-+struct omap_sr{
-+	int srid;
-+	int is_sr_reset;
-+	int is_autocomp_active;
-+	struct clk *fck;
-+	u32 req_opp_no;
-+	u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue;
-+	u32 senp_mod, senn_mod;
-+	u32 srbase_addr;
-+	u32 vpbase_addr;
-+};
-+
-+static struct omap_sr sr1 = {
-+	.srid = SR1,
-+	.is_sr_reset = 1,
-+	.is_autocomp_active = 0,
-+	.srbase_addr = OMAP34XX_SR1_BASE,
-+};
-+
-+static struct omap_sr sr2 = {
-+	.srid = SR2,
-+	.is_sr_reset = 1,
-+	.is_autocomp_active = 0,
-+	.srbase_addr = OMAP34XX_SR2_BASE,
-+};
-+
-+static inline void sr_write_reg(struct omap_sr *sr, int offset, u32 value)
-+{
-+	omap_writel(value, sr->srbase_addr + offset);
-+}
-+
-+static inline void sr_modify_reg(struct omap_sr *sr, int offset, u32 mask,
-+								u32 value)
-+{
-+	u32 reg_val;
-+
-+	reg_val = omap_readl(sr->srbase_addr + offset);
-+	reg_val &= ~mask;
-+	reg_val |= value;
-+
-+	omap_writel(reg_val, sr->srbase_addr + offset);
-+}
-+
-+static inline u32 sr_read_reg(struct omap_sr *sr, int offset)
-+{
-+	return omap_readl(sr->srbase_addr + offset);
-+}
-+
-+
-+#ifndef USE_EFUSE_VALUES
-+static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
-+{
-+	u32 gn, rn, mul;
-+
-+	for (gn = 0; gn < GAIN_MAXLIMIT; gn++) {
-+		mul = 1 << (gn + 8);
-+		rn = mul / sensor;
-+		if (rn < R_MAXLIMIT) {
-+			*sengain = gn;
-+			*rnsen = rn;
-+		}
-+	}
-+}
-+#endif
-+
-+static int sr_clk_enable(struct omap_sr *sr)
-+{
-+	if (clk_enable(sr->fck) != 0) {
-+		printk(KERN_ERR "Could not enable sr%d_fck\n", sr->srid);
-+		goto clk_enable_err;
-+	}
-+
-+	/* set fclk- active , iclk- idle */
-+	sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
-+						SR_CLKACTIVITY_IOFF_FON);
-+
-+	return 0;
-+
-+clk_enable_err:
-+	return -1;
-+}
-+
-+static int sr_clk_disable(struct omap_sr *sr)
-+{
-+	/* set fclk, iclk- idle */
-+	sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
-+						SR_CLKACTIVITY_IOFF_FOFF);
-+
-+	clk_disable(sr->fck);
-+	sr->is_sr_reset = 1;
-+
-+	return 0;
-+}
-+
-+static void sr_set_nvalues(struct omap_sr *sr)
-+{
-+#ifdef USE_EFUSE_VALUES
-+	u32 n1, n2;
-+#else
-+	u32 senpval, sennval;
-+	u32 senpgain, senngain;
-+	u32 rnsenp, rnsenn;
-+#endif
-+
-+	if (sr->srid == SR1) {
-+#ifdef USE_EFUSE_VALUES
-+		/* Read values for VDD1 from EFUSE */
-+#else
-+		/* since E-Fuse Values are not available, calculating the
-+		 * reciprocal of the SenN and SenP values for SR1
-+		 */
-+		sr->senp_mod = 0x03;        /* SenN-M5 enabled */
-+		sr->senn_mod = 0x03;
-+
-+		/* for OPP5 */
-+		senpval = 0x848 + 0x330;
-+		sennval = 0xacd + 0x330;
-+
-+		cal_reciprocal(senpval, &senpgain, &rnsenp);
-+		cal_reciprocal(sennval, &senngain, &rnsenn);
-+
-+		sr->opp5_nvalue =
-+				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
-+				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
-+				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
-+				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
-+
-+		/* for OPP4 */
-+		senpval = 0x727 + 0x2a0;
-+		sennval = 0x964 + 0x2a0;
-+
-+		cal_reciprocal(senpval, &senpgain, &rnsenp);
-+		cal_reciprocal(sennval, &senngain, &rnsenn);
-+
-+		sr->opp4_nvalue =
-+				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
-+				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
-+				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
-+				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
-+
-+		/* for OPP3 */
-+		senpval = 0x655 + 0x200;
-+		sennval = 0x85b + 0x200;
-+
-+		cal_reciprocal(senpval, &senpgain, &rnsenp);
-+		cal_reciprocal(sennval, &senngain, &rnsenn);
-+
-+		sr->opp3_nvalue =
-+				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
-+				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
-+				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
-+				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
-+
-+		/* for OPP2 */
-+		senpval = 0x3be + 0x1a0;
-+		sennval = 0x506 + 0x1a0;
-+
-+		cal_reciprocal(senpval, &senpgain, &rnsenp);
-+		cal_reciprocal(sennval, &senngain, &rnsenn);
-+
-+		sr->opp2_nvalue =
-+				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
-+				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
-+				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
-+				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
-+
-+		/* for OPP1 */
-+		senpval = 0x28c + 0x100;
-+		sennval = 0x373 + 0x100;
-+
-+		cal_reciprocal(senpval, &senpgain, &rnsenp);
-+		cal_reciprocal(sennval, &senngain, &rnsenn);
-+
-+		sr->opp1_nvalue =
-+				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
-+				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
-+				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
-+				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
-+
-+		sr_clk_enable(sr);
-+		sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue);
-+		sr_clk_disable(sr);
-+
-+#endif
-+	} else if (sr->srid == SR2) {
-+#ifdef USE_EFUSE_VALUES
-+		/* Read values for VDD2 from EFUSE */
-+#else
-+		/* since E-Fuse Values are not available, calculating the
-+		 * reciprocal of the SenN and SenP values for SR2
-+		 */
-+		sr->senp_mod = 0x03;
-+		sr->senn_mod = 0x03;
-+
-+		/* for OPP3 */
-+		senpval = 0x579 + 0x200;
-+		sennval = 0x76f + 0x200;
-+
-+		cal_reciprocal(senpval, &senpgain, &rnsenp);
-+		cal_reciprocal(sennval, &senngain, &rnsenn);
-+
-+		sr->opp3_nvalue =
-+				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
-+				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
-+				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
-+				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
-+
-+		/* for OPP2 */
-+		senpval = 0x390 + 0x1c0;
-+		sennval = 0x4f5 + 0x1c0;
-+
-+		cal_reciprocal(senpval, &senpgain, &rnsenp);
-+		cal_reciprocal(sennval, &senngain, &rnsenn);
-+
-+		sr->opp2_nvalue =
-+				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
-+				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
-+				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
-+				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
-+
-+		/* for OPP1 */
-+		senpval = 0x25d;
-+		sennval = 0x359;
-+
-+		cal_reciprocal(senpval, &senpgain, &rnsenp);
-+		cal_reciprocal(sennval, &senngain, &rnsenn);
-+
-+		sr->opp1_nvalue =
-+				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
-+				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
-+				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
-+				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
-+
-+#endif
-+	}
-+
-+}
-+
-+static void sr_configure_vp(int srid)
-+{
-+	u32 vpconfig;
-+
-+	if (srid == SR1) {
-+		vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN
-+			| PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN;
-+
-+		PRM_VP1_CONFIG = vpconfig;
-+		PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
-+						PRM_VP1_VSTEPMIN_VSTEPMIN;
-+
-+		PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
-+						PRM_VP1_VSTEPMAX_VSTEPMAX;
-+
-+		PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX |
-+			PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT;
-+
-+		PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD;
-+		PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD;
-+
-+	} else if (srid == SR2) {
-+		vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN
-+			| PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN;
-+
-+		PRM_VP2_CONFIG = vpconfig;
-+		PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
-+						PRM_VP2_VSTEPMIN_VSTEPMIN;
-+
-+		PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
-+						PRM_VP2_VSTEPMAX_VSTEPMAX;
-+
-+		PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX |
-+			PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT;
-+
-+		PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD;
-+		PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD;
-+
-+	}
-+}
-+
-+static void sr_configure_vc(void)
-+{
-+	PRM_VC_SMPS_SA =
-+		(R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) |
-+		(R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT);
-+
-+	PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) |
-+				(R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT);
-+
-+	PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) |
-+			(PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
-+			(PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) |
-+			(PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT);
-+
-+	PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) |
-+			(PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
-+			(PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) |
-+			(PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT);
-+
-+	PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1;
-+
-+	PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN
-+							| PRM_VC_I2C_CFG_SREN;
-+
-+	/* Setup voltctrl and other setup times */
-+#ifdef CONFIG_SYSOFFMODE
-+	PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET;
-+	PRM_CLKSETUP = PRM_CLKSETUP_DURATION;
-+	PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) |
-+			(PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET);
-+	PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION;
-+	PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION;
-+#else
-+	PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET;
-+#endif
-+
-+}
-+
-+
-+static void sr_configure(struct omap_sr *sr)
-+{
-+	u32 sys_clk, sr_clk_length = 0;
-+	u32 sr_config;
-+	u32 senp_en , senn_en;
-+
-+	senp_en = sr->senp_mod;
-+	senn_en = sr->senn_mod;
-+
-+	sys_clk = prcm_get_system_clock_speed();
-+
-+	switch (sys_clk) {
-+	case 12000:
-+		sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
-+		break;
-+	case 13000:
-+		sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
-+		break;
-+	case 19200:
-+		sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
-+		break;
-+	case 26000:
-+		sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
-+		break;
-+	case 38400:
-+		sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
-+		break;
-+	default :
-+		printk(KERN_ERR "Invalid sysclk value\n");
-+		break;
-+	}
-+
-+	DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk);
-+	if (sr->srid == SR1) {
-+		sr_config = SR1_SRCONFIG_ACCUMDATA |
-+			(sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-+			SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
-+			SRCONFIG_MINMAXAVG_EN |
-+			(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
-+			(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
-+			SRCONFIG_DELAYCTRL;
-+
-+		sr_write_reg(sr, SRCONFIG, sr_config);
-+
-+		sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
-+					SR1_AVGWEIGHT_SENNAVGWEIGHT);
-+
-+		sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
-+			SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
-+			(SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT));
-+
-+	} else if (sr->srid == SR2) {
-+		sr_config = SR2_SRCONFIG_ACCUMDATA |
-+			(sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-+			SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
-+			SRCONFIG_MINMAXAVG_EN |
-+			(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
-+			(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
-+			SRCONFIG_DELAYCTRL;
-+
-+		sr_write_reg(sr, SRCONFIG, sr_config);
-+
-+		sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
-+					SR2_AVGWEIGHT_SENNAVGWEIGHT);
-+
-+		sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
-+			SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
-+			(SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
-+
-+	}
-+	sr->is_sr_reset = 0;
-+}
-+
-+static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
-+{
-+	u32 nvalue_reciprocal, current_nvalue;
-+
-+	sr->req_opp_no = target_opp_no;
-+
-+	if (sr->srid == SR1) {
-+		switch (target_opp_no) {
-+		case 5:
-+			nvalue_reciprocal = sr->opp5_nvalue;
-+			break;
-+		case 4:
-+			nvalue_reciprocal = sr->opp4_nvalue;
-+			break;
-+		case 3:
-+			nvalue_reciprocal = sr->opp3_nvalue;
-+			break;
-+		case 2:
-+			nvalue_reciprocal = sr->opp2_nvalue;
-+			break;
-+		case 1:
-+			nvalue_reciprocal = sr->opp1_nvalue;
-+			break;
-+		default:
-+			nvalue_reciprocal = sr->opp3_nvalue;
-+			break;
-+		}
-+	} else {
-+		switch (target_opp_no) {
-+		case 3:
-+			nvalue_reciprocal = sr->opp3_nvalue;
-+			break;
-+		case 2:
-+			nvalue_reciprocal = sr->opp2_nvalue;
-+			break;
-+		case 1:
-+			nvalue_reciprocal = sr->opp1_nvalue;
-+			break;
-+		default:
-+			nvalue_reciprocal = sr->opp3_nvalue;
-+			break;
-+		}
-+	}
-+
-+	current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL);
-+
-+	if (current_nvalue == nvalue_reciprocal) {
-+		DPRINTK("System is already at the desired voltage level\n");
-+		return;
-+	}
-+
-+	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
-+
-+	/* Enable the interrupt */
-+	sr_modify_reg(sr, ERRCONFIG,
-+			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
-+			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
-+
-+	if (sr->srid == SR1) {
-+		/* Enable VP1 */
-+		PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE;
-+	} else if (sr->srid == SR2) {
-+		/* Enable VP2 */
-+		PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE;
-+	}
-+
-+	/* SRCONFIG - enable SR */
-+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
-+
-+}
-+
-+static void sr_disable(struct omap_sr *sr)
-+{
-+	sr->is_sr_reset = 1;
-+
-+	/* SRCONFIG - disable SR */
-+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);
-+
-+	if (sr->srid == SR1) {
-+		/* Enable VP1 */
-+		PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
-+	} else if (sr->srid == SR2) {
-+		/* Enable VP2 */
-+		PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
-+	}
-+}
-+
-+
-+void sr_start_vddautocomap(int srid, u32 target_opp_no)
-+{
-+	struct omap_sr *sr = NULL;
-+
-+	if (srid == SR1)
-+		sr = &sr1;
-+	else if (srid == SR2)
-+		sr = &sr2;
-+
-+	if (sr->is_sr_reset == 1) {
-+		sr_clk_enable(sr);
-+		sr_configure(sr);
-+	}
-+
-+	if (sr->is_autocomp_active == 1)
-+		DPRINTK(KERN_WARNING "SR%d: VDD autocomp is already active\n",
-+									srid);
-+
-+	sr->is_autocomp_active = 1;
-+	sr_enable(sr, target_opp_no);
-+}
-+EXPORT_SYMBOL(sr_start_vddautocomap);
-+
-+int sr_stop_vddautocomap(int srid)
-+{
-+	struct omap_sr *sr = NULL;
-+
-+	if (srid == SR1)
-+		sr = &sr1;
-+	else if (srid == SR2)
-+		sr = &sr2;
-+
-+	if (sr->is_autocomp_active == 1) {
-+		sr_disable(sr);
-+		sr_clk_disable(sr);
-+		sr->is_autocomp_active = 0;
-+		return SR_TRUE;
-+	} else {
-+		DPRINTK(KERN_WARNING "SR%d: VDD autocomp is not active\n",
-+								srid);
-+		return SR_FALSE;
-+	}
-+
-+}
-+EXPORT_SYMBOL(sr_stop_vddautocomap);
-+
-+void enable_smartreflex(int srid)
-+{
-+	u32 target_opp_no = 0;
-+	struct omap_sr *sr = NULL;
-+
-+	if (srid == SR1)
-+		sr = &sr1;
-+	else if (srid == SR2)
-+		sr = &sr2;
-+
-+	if (sr->is_autocomp_active == 1) {
-+		if (sr->is_sr_reset == 1) {
-+			if (srid == SR1) {
-+				/* Enable SR clks */
-+				CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
-+				target_opp_no = get_opp_no(current_vdd1_opp);
-+
-+			} else if (srid == SR2) {
-+				/* Enable SR clks */
-+				CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
-+				target_opp_no = get_opp_no(current_vdd2_opp);
-+			}
-+
-+			sr_configure(sr);
-+
-+			sr_enable(sr, target_opp_no);
-+		}
-+	}
-+}
-+
-+void disable_smartreflex(int srid)
-+{
-+	struct omap_sr *sr = NULL;
-+
-+	if (srid == SR1)
-+		sr = &sr1;
-+	else if (srid == SR2)
-+		sr = &sr2;
-+
-+	if (sr->is_autocomp_active == 1) {
-+		if (srid == SR1) {
-+			/* Enable SR clk */
-+			CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
-+
-+		} else if (srid == SR2) {
-+			/* Enable SR clk */
-+			CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
-+		}
-+
-+		if (sr->is_sr_reset == 0) {
-+
-+			sr->is_sr_reset = 1;
-+			/* SRCONFIG - disable SR */
-+			sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
-+							~SRCONFIG_SRENABLE);
-+
-+			if (sr->srid == SR1) {
-+				/* Disable SR clk */
-+				CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE;
-+				/* Enable VP1 */
-+				PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
-+
-+			} else if (sr->srid == SR2) {
-+				/* Disable SR clk */
-+				CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE;
-+				/* Enable VP2 */
-+				PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
-+			}
-+		}
-+	}
-+}
-+
-+
-+/* Voltage Scaling using SR VCBYPASS */
-+int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
-+{
-+	int ret;
-+	int sr_status = 0;
-+	u32 vdd, target_opp_no;
-+	u32 vc_bypass_value;
-+	u32 reg_addr = 0;
-+	u32 loop_cnt = 0, retries_cnt = 0;
-+
-+	vdd = get_vdd(target_opp);
-+	target_opp_no = get_opp_no(target_opp);
-+
-+	if (vdd == PRCM_VDD1) {
-+		sr_status = sr_stop_vddautocomap(SR1);
-+
-+		PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) |
-+						(vsel << PRM_VC_CMD_ON_SHIFT);
-+		reg_addr = R_VDD1_SR_CONTROL;
-+
-+	} else if (vdd == PRCM_VDD2) {
-+		sr_status = sr_stop_vddautocomap(SR2);
-+
-+		PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) |
-+						(vsel << PRM_VC_CMD_ON_SHIFT);
-+		reg_addr = R_VDD2_SR_CONTROL;
-+	}
-+
-+	vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) |
-+			(reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) |
-+			(R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT);
-+
-+	PRM_VC_BYPASS_VAL = vc_bypass_value;
-+
-+	PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID;
-+
-+	DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL);
-+	DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU);
-+
-+	while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) {
-+		ret = loop_wait(&loop_cnt, &retries_cnt, 10);
-+		if (ret != PRCM_PASS) {
-+			printk(KERN_INFO "Loop count exceeded in check SR I2C"
-+								"write\n");
-+			return ret;
-+		}
-+	}
-+
-+	omap_udelay(T2_SMPS_UPDATE_DELAY);
-+
-+	if (sr_status) {
-+		if (vdd == PRCM_VDD1)
-+			sr_start_vddautocomap(SR1, target_opp_no);
-+		else if (vdd == PRCM_VDD2)
-+			sr_start_vddautocomap(SR2, target_opp_no);
-+	}
-+
-+	return SR_PASS;
-+}
-+
-+/* Sysfs interface to select SR VDD1 auto compensation */
-+static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf)
-+{
-+	return sprintf(buf, "%d\n", sr1.is_autocomp_active);
-+}
-+
-+static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
-+				const char *buf, size_t n)
-+{
-+	u32 current_vdd1opp_no;
-+	unsigned short value;
-+
-+	if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
-+		printk(KERN_ERR "sr_vdd1_autocomp: Invalid value\n");
-+		return -EINVAL;
-+	}
-+
-+	current_vdd1opp_no = get_opp_no(current_vdd1_opp);
-+
-+	if (value == 0)
-+		sr_stop_vddautocomap(SR1);
-+	else
-+		sr_start_vddautocomap(SR1, current_vdd1opp_no);
-+
-+	return n;
-+}
-+
-+static struct subsys_attribute sr_vdd1_autocomp = {
-+	.attr = {
-+	.name = __stringify(sr_vdd1_autocomp),
-+	.mode = 0644,
-+	},
-+	.show = omap_sr_vdd1_autocomp_show,
-+	.store = omap_sr_vdd1_autocomp_store,
-+};
-+
-+/* Sysfs interface to select SR VDD2 auto compensation */
-+static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf)
-+{
-+	return sprintf(buf, "%d\n", sr2.is_autocomp_active);
-+}
-+
-+static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
-+				const char *buf, size_t n)
-+{
-+	u32 current_vdd2opp_no;
-+	unsigned short value;
-+
-+	if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
-+		printk(KERN_ERR "sr_vdd2_autocomp: Invalid value\n");
-+		return -EINVAL;
-+	}
-+
-+	current_vdd2opp_no = get_opp_no(current_vdd2_opp);
-+
-+	if (value == 0)
-+		sr_stop_vddautocomap(SR2);
-+	else
-+		sr_start_vddautocomap(SR2, current_vdd2opp_no);
-+
-+	return n;
-+}
-+
-+static struct subsys_attribute sr_vdd2_autocomp = {
-+	.attr = {
-+	.name = __stringify(sr_vdd2_autocomp),
-+	.mode = 0644,
-+	},
-+	.show = omap_sr_vdd2_autocomp_show,
-+	.store = omap_sr_vdd2_autocomp_store,
-+};
-+
-+
-+
-+static int __init omap3_sr_init(void)
-+{
-+	int ret = 0;
-+	u8 RdReg;
-+
-+#ifdef CONFIG_ARCH_OMAP34XX
-+	sr1.fck = clk_get(NULL, "sr1_fck");
-+	if (IS_ERR(sr1.fck))
-+		printk(KERN_ERR "Could not get sr1_fck\n");
-+
-+	sr2.fck = clk_get(NULL, "sr2_fck");
-+	if (IS_ERR(sr2.fck))
-+		printk(KERN_ERR "Could not get sr2_fck\n");
-+#endif /* #ifdef CONFIG_ARCH_OMAP34XX */
-+
-+	/* Call the VPConfig, VCConfig, set N Values. */
-+	sr_set_nvalues(&sr1);
-+	sr_configure_vp(SR1);
-+
-+	sr_set_nvalues(&sr2);
-+	sr_configure_vp(SR2);
-+
-+	sr_configure_vc();
-+
-+	/* Enable SR on T2 */
-+	ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG);
-+	RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
-+	ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG);
-+
-+
-+	printk(KERN_INFO "SmartReflex driver initialized\n");
-+
-+	ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp);
-+	if (ret)
-+		printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
-+
-+	ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp);
-+	if (ret)
-+		printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
-+
-+	return 0;
-+}
-+
-+arch_initcall(omap3_sr_init);
-diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
-new file mode 100644
-index 0000000..62907ef
---- /dev/null
-+++ b/arch/arm/mach-omap2/smartreflex.h
-@@ -0,0 +1,136 @@
-+/*
-+ * linux/arch/arm/mach-omap3/smartreflex.h
-+ *
-+ * Copyright (C) 2007 Texas Instruments, Inc.
-+ * Lesly A M <x0080970@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+
-+/* SR Modules */
-+#define SR1		1
-+#define SR2		2
-+
-+#define SR_FAIL		1
-+#define SR_PASS		0
-+
-+#define SR_TRUE		1
-+#define SR_FALSE	0
-+
-+#define GAIN_MAXLIMIT	16
-+#define R_MAXLIMIT	256
-+
-+#define SR1_CLK_ENABLE	(0x1 << 6)
-+#define SR2_CLK_ENABLE	(0x1 << 7)
-+
-+/* PRM_VP1_CONFIG */
-+#define PRM_VP1_CONFIG_ERROROFFSET	(0x00 << 24)
-+#define PRM_VP1_CONFIG_ERRORGAIN	(0x20 << 16)
-+
-+#define PRM_VP1_CONFIG_INITVOLTAGE	(0x30 << 8) /* 1.2 volt */
-+#define PRM_VP1_CONFIG_TIMEOUTEN	(0x1 << 3)
-+#define PRM_VP1_CONFIG_INITVDD		(0x1 << 2)
-+#define PRM_VP1_CONFIG_FORCEUPDATE	(0x1 << 1)
-+#define PRM_VP1_CONFIG_VPENABLE		(0x1 << 0)
-+
-+/* PRM_VP1_VSTEPMIN */
-+#define PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN	(0x01F4 << 8)
-+#define PRM_VP1_VSTEPMIN_VSTEPMIN		(0x01 << 0)
-+
-+/* PRM_VP1_VSTEPMAX */
-+#define PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX	(0x01F4 << 8)
-+#define PRM_VP1_VSTEPMAX_VSTEPMAX		(0x04 << 0)
-+
-+/* PRM_VP1_VLIMITTO */
-+#define PRM_VP1_VLIMITTO_VDDMAX		(0x3C << 24)
-+#define PRM_VP1_VLIMITTO_VDDMIN		(0x0 << 16)
-+#define PRM_VP1_VLIMITTO_TIMEOUT	(0xFFFF << 0)
-+
-+/* PRM_VP2_CONFIG */
-+#define PRM_VP2_CONFIG_ERROROFFSET	(0x00 << 24)
-+#define PRM_VP2_CONFIG_ERRORGAIN	(0x20 << 16)
-+
-+#define PRM_VP2_CONFIG_INITVOLTAGE	(0x30 << 8) /* 1.2 volt */
-+#define PRM_VP2_CONFIG_TIMEOUTEN	(0x1 << 3)
-+#define PRM_VP2_CONFIG_INITVDD		(0x1 << 2)
-+#define PRM_VP2_CONFIG_FORCEUPDATE	(0x1 << 1)
-+#define PRM_VP2_CONFIG_VPENABLE		(0x1 << 0)
-+
-+/* PRM_VP2_VSTEPMIN */
-+#define PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN	(0x01F4 << 8)
-+#define PRM_VP2_VSTEPMIN_VSTEPMIN		(0x01 << 0)
-+
-+/* PRM_VP2_VSTEPMAX */
-+#define PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX	(0x01F4 << 8)
-+#define PRM_VP2_VSTEPMAX_VSTEPMAX		(0x04 << 0)
-+
-+/* PRM_VP2_VLIMITTO */
-+#define PRM_VP2_VLIMITTO_VDDMAX		(0x2C << 24)
-+#define PRM_VP2_VLIMITTO_VDDMIN		(0x0 << 16)
-+#define PRM_VP2_VLIMITTO_TIMEOUT	(0xFFFF << 0)
-+
-+/* SRCONFIG */
-+#define SR1_SRCONFIG_ACCUMDATA		(0x1F4 << 22)
-+#define SR2_SRCONFIG_ACCUMDATA		(0x1F4 << 22)
-+
-+#define SRCLKLENGTH_12MHZ_SYSCLK	0x3C
-+#define SRCLKLENGTH_13MHZ_SYSCLK	0x41
-+#define SRCLKLENGTH_19MHZ_SYSCLK	0x60
-+#define SRCLKLENGTH_26MHZ_SYSCLK	0x82
-+#define SRCLKLENGTH_38MHZ_SYSCLK	0xC0
-+
-+#define SRCONFIG_SRCLKLENGTH_SHIFT	12
-+#define SRCONFIG_SENNENABLE_SHIFT	5
-+#define SRCONFIG_SENPENABLE_SHIFT	3
-+
-+#define SRCONFIG_SRENABLE		(0x01 << 11)
-+#define SRCONFIG_SENENABLE		(0x01 << 10)
-+#define SRCONFIG_ERRGEN_EN		(0x01 << 9)
-+#define SRCONFIG_MINMAXAVG_EN		(0x01 << 8)
-+
-+#define SRCONFIG_DELAYCTRL		(0x01 << 2)
-+#define SRCONFIG_CLKCTRL		(0x00 << 0)
-+
-+/* AVGWEIGHT */
-+#define SR1_AVGWEIGHT_SENPAVGWEIGHT	(0x03 << 2)
-+#define SR1_AVGWEIGHT_SENNAVGWEIGHT	(0x03 << 0)
-+
-+#define SR2_AVGWEIGHT_SENPAVGWEIGHT	(0x01 << 2)
-+#define SR2_AVGWEIGHT_SENNAVGWEIGHT	(0x01 << 0)
-+
-+/* NVALUERECIPROCAL */
-+#define NVALUERECIPROCAL_SENPGAIN_SHIFT	20
-+#define NVALUERECIPROCAL_SENNGAIN_SHIFT	16
-+#define NVALUERECIPROCAL_RNSENP_SHIFT	8
-+#define NVALUERECIPROCAL_RNSENN_SHIFT	0
-+
-+/* ERRCONFIG */
-+#define SR_CLKACTIVITY_MASK		(0x03 << 20)
-+#define SR_ERRWEIGHT_MASK		(0x07 << 16)
-+#define SR_ERRMAXLIMIT_MASK		(0xFF << 8)
-+#define SR_ERRMINLIMIT_MASK		(0xFF << 0)
-+
-+#define SR_CLKACTIVITY_IOFF_FOFF	(0x00 << 20)
-+#define SR_CLKACTIVITY_IOFF_FON		(0x02 << 20)
-+
-+#define ERRCONFIG_VPBOUNDINTEN		(0x1 << 31)
-+#define ERRCONFIG_VPBOUNDINTST		(0x1 << 30)
-+
-+#define SR1_ERRWEIGHT			(0x07 << 16)
-+#define SR1_ERRMAXLIMIT			(0x02 << 8)
-+#define SR1_ERRMINLIMIT			(0xFA << 0)
-+
-+#define SR2_ERRWEIGHT			(0x07 << 16)
-+#define SR2_ERRMAXLIMIT			(0x02 << 8)
-+#define SR2_ERRMINLIMIT			(0xF9 << 0)
-+
-+extern u32 current_vdd1_opp;
-+extern u32 current_vdd2_opp;
-+extern struct kset power_subsys;
-+
-+extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
-+extern void omap_udelay(u32 udelay);
-+
--- 
-1.5.4.3
diff --git a/packages/linux/linux-omap2-git/beagleboard/0002-ARM-OMAP-SmartReflex-driver.patch b/packages/linux/linux-omap2-git/beagleboard/0002-ARM-OMAP-SmartReflex-driver.patch
deleted file mode 100644
index 8e609395a0..0000000000
--- a/packages/linux/linux-omap2-git/beagleboard/0002-ARM-OMAP-SmartReflex-driver.patch
+++ /dev/null
@@ -1,278 +0,0 @@
-From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
-To: linux-omap@vger.kernel.org
-Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
-Subject: [PATCH 2/3] ARM: OMAP: SmartReflex driver: added required register and bit definitions.
-Date: 	Fri,  6 Jun 2008 12:49:48 +0300
-
-Added new register and bit definitions to enable Smartreflex driver integration.
-Also PRM_VC_SMPS_SA bit definitions' naming was changed to match the naming of
-other similar bit definitions.
-
-Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
----
- arch/arm/mach-omap2/prm-regbits-34xx.h |   27 ++++++--
- arch/arm/mach-omap2/smartreflex.h      |  124 ++++++++++++++++++++++++++++++-
- include/asm-arm/arch-omap/control.h    |   19 +++++
- include/asm-arm/arch-omap/omap34xx.h   |    2 +
- 4 files changed, 163 insertions(+), 9 deletions(-)
-
-diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
-index c6a7940..f82b5a7 100644
---- a/arch/arm/mach-omap2/prm-regbits-34xx.h
-+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
-@@ -435,10 +435,10 @@
- /* PM_PWSTST_EMU specific bits */
- 
- /* PRM_VC_SMPS_SA */
--#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT		16
--#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK		(0x7f << 16)
--#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT		0
--#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK		(0x7f << 0)
-+#define OMAP3430_SMPS_SA1_SHIFT				16
-+#define OMAP3430_SMPS_SA1_MASK				(0x7f << 16)
-+#define OMAP3430_SMPS_SA0_SHIFT				0
-+#define OMAP3430_SMPS_SA0_MASK				(0x7f << 0)
- 
- /* PRM_VC_SMPS_VOL_RA */
- #define OMAP3430_VOLRA1_SHIFT				16
-@@ -452,7 +452,7 @@
- #define OMAP3430_CMDRA0_SHIFT				0
- #define OMAP3430_CMDRA0_MASK				(0xff << 0)
- 
--/* PRM_VC_CMD_VAL_0 specific bits */
-+/* PRM_VC_CMD_VAL */
- #define OMAP3430_VC_CMD_ON_SHIFT			24
- #define OMAP3430_VC_CMD_ON_MASK				(0xFF << 24)
- #define OMAP3430_VC_CMD_ONLP_SHIFT			16
-@@ -462,7 +462,17 @@
- #define OMAP3430_VC_CMD_OFF_SHIFT			0
- #define OMAP3430_VC_CMD_OFF_MASK			(0xFF << 0)
- 
-+/* PRM_VC_CMD_VAL_0 specific bits */
-+#define OMAP3430_VC_CMD_VAL0_ON				(0x3 << 4)
-+#define OMAP3430_VC_CMD_VAL0_ONLP			(0x3 << 3)
-+#define OMAP3430_VC_CMD_VAL0_RET			(0x3 << 3)
-+#define OMAP3430_VC_CMD_VAL0_OFF			(0x3 << 3)
-+
- /* PRM_VC_CMD_VAL_1 specific bits */
-+#define OMAP3430_VC_CMD_VAL1_ON				(0xB << 2)
-+#define OMAP3430_VC_CMD_VAL1_ONLP			(0x3 << 3)
-+#define OMAP3430_VC_CMD_VAL1_RET			(0x3 << 3)
-+#define OMAP3430_VC_CMD_VAL1_OFF			(0x3 << 3)
- 
- /* PRM_VC_CH_CONF */
- #define OMAP3430_CMD1					(1 << 20)
-@@ -521,6 +531,13 @@
- #define OMAP3430_AUTO_RET				(1 << 1)
- #define OMAP3430_AUTO_SLEEP				(1 << 0)
- 
-+/* Constants to define setup durations */
-+#define OMAP3430_CLKSETUP_DURATION			0xff
-+#define OMAP3430_VOLTSETUP_TIME2			0xfff
-+#define OMAP3430_VOLTSETUP_TIME1			0xfff
-+#define OMAP3430_VOLTOFFSET_DURATION			0xff
-+#define OMAP3430_VOLTSETUP2_DURATION			0xff
-+
- /* PRM_SRAM_PCHARGE */
- #define OMAP3430_PCHARGE_TIME_SHIFT			0
- #define OMAP3430_PCHARGE_TIME_MASK			(0xff << 0)
-diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
-index 62907ef..2091a15 100644
---- a/arch/arm/mach-omap2/smartreflex.h
-+++ b/arch/arm/mach-omap2/smartreflex.h
-@@ -1,5 +1,10 @@
-+#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
-+#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
- /*
-- * linux/arch/arm/mach-omap3/smartreflex.h
-+ * linux/arch/arm/mach-omap2/smartreflex.h
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Kalle Jokiniemi
-  *
-  * Copyright (C) 2007 Texas Instruments, Inc.
-  * Lesly A M <x0080970@ti.com>
-@@ -9,6 +14,21 @@
-  * published by the Free Software Foundation.
-  */
- 
-+#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
-+#define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
-+#define PHY_TO_OFF_PM_INT(p)		(p - 0x2e)
-+
-+/* SMART REFLEX REG ADDRESS OFFSET */
-+#define SRCONFIG	0x00
-+#define SRSTATUS	0x04
-+#define SENVAL		0x08
-+#define SENMIN		0x0C
-+#define SENMAX		0x10
-+#define SENAVG		0x14
-+#define AVGWEIGHT	0x18
-+#define NVALUERECIPROCAL	0x1C
-+#define SENERROR	0x20
-+#define ERRCONFIG	0x24
- 
- /* SR Modules */
- #define SR1		1
-@@ -127,10 +147,106 @@
- #define SR2_ERRMAXLIMIT			(0x02 << 8)
- #define SR2_ERRMINLIMIT			(0xF9 << 0)
- 
-+/* T2 SMART REFLEX */
-+#define R_SRI2C_SLAVE_ADDR		0x12
-+#define R_VDD1_SR_CONTROL		0x00
-+#define R_VDD2_SR_CONTROL		0x01
-+#define T2_SMPS_UPDATE_DELAY		360	/* In uSec */
-+
-+/* Vmode control */
-+#define R_DCDC_GLOBAL_CFG	PHY_TO_OFF_PM_RECIEVER(0x61)
-+
-+#define R_VDD1_VSEL		PHY_TO_OFF_PM_RECIEVER(0xb9)
-+#define R_VDD1_VMODE_CFG	PHY_TO_OFF_PM_RECIEVER(0xba)
-+#define R_VDD1_VFLOOR		PHY_TO_OFF_PM_RECIEVER(0xbb)
-+#define R_VDD1_VROOF		PHY_TO_OFF_PM_RECIEVER(0xbc)
-+#define R_VDD1_STEP		PHY_TO_OFF_PM_RECIEVER(0xbd)
-+
-+#define R_VDD2_VSEL		PHY_TO_OFF_PM_RECIEVER(0xc7)
-+#define R_VDD2_VMODE_CFG	PHY_TO_OFF_PM_RECIEVER(0xc8)
-+#define R_VDD2_VFLOOR		PHY_TO_OFF_PM_RECIEVER(0xc9)
-+#define R_VDD2_VROOF		PHY_TO_OFF_PM_RECIEVER(0xca)
-+#define R_VDD2_STEP		PHY_TO_OFF_PM_RECIEVER(0xcb)
-+
-+/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */
-+#define DCDC_GLOBAL_CFG_ENABLE_SRFLX	0x08
-+
-+/* VDDs*/
-+#define PRCM_VDD1	1
-+#define PRCM_VDD2	2
-+#define PRCM_MAX_SYSC_REGS 30
-+
-+/* XXX: These should be removed/moved from here once we have a working DVFS
-+   implementation in place */
-+#define AT_3430		1	/*3430 ES 1.0 */
-+#define AT_3430_ES2	2	/*3430 ES 2.0 */
-+
-+#define ID_OPP			0xE2 	/*OPP*/
-+
-+/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */
-+#define OMAP_TYPE_SHIFT		28
-+#define OMAP_TYPE_MASK		0xF
-+/* OPP ID: bits: 0-4 for OPP number */
-+#define OPP_NO_POS		0
-+#define OPP_NO_MASK		0x1F
-+/* OPP ID: bits: 5-6 for VDD */
-+#define VDD_NO_POS		5
-+#define VDD_NO_MASK		0x3
-+/* Other IDs: bits 20-27 for ID type */
-+/* These IDs have bits 25,26,27 as 1 */
-+#define OTHER_ID_TYPE_SHIFT		20
-+#define OTHER_ID_TYPE_MASK		0xFF
-+
-+#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT)
-+#define ID_OPP_NO(X)	 ((X & OPP_NO_MASK) << OPP_NO_POS)
-+#define ID_VDD(X)	 ((X & VDD_NO_MASK) << VDD_NO_POS)
-+#define OMAP(X)		 ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK)
-+#define get_opp_no(X)	 ((X >> OPP_NO_POS) & OPP_NO_MASK)
-+#define get_vdd(X)	 ((X >> VDD_NO_POS) & VDD_NO_MASK)
-+
-+/* VDD1 OPPs */
-+#define PRCM_VDD1_OPP1		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
-+					ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1))
-+#define PRCM_VDD1_OPP2		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
-+					ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2))
-+#define PRCM_VDD1_OPP3		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
-+					ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3))
-+#define PRCM_VDD1_OPP4		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
-+					ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4))
-+#define PRCM_VDD1_OPP5		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
-+					ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5))
-+#define PRCM_NO_VDD1_OPPS	5
-+
-+
-+/* VDD2 OPPs */
-+#define PRCM_VDD2_OPP1		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
-+					ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1))
-+#define PRCM_VDD2_OPP2		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
-+					ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2))
-+#define PRCM_VDD2_OPP3		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
-+					ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3))
-+#define PRCM_NO_VDD2_OPPS	3
-+/* XXX: end remove/move */
-+
-+
-+/* XXX: find more appropriate place for these once DVFS is in place */
- extern u32 current_vdd1_opp;
- extern u32 current_vdd2_opp;
--extern struct kset power_subsys;
- 
--extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
--extern void omap_udelay(u32 udelay);
-+/*
-+ * Smartreflex module enable/disable interface.
-+ * NOTE: if smartreflex is not enabled from sysfs, these functions will not
-+ * do anything.
-+ */
-+#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
-+void enable_smartreflex(int srid);
-+void disable_smartreflex(int srid);
-+#else
-+static inline void enable_smartreflex(int srid) {}
-+static inline void disable_smartreflex(int srid) {}
-+#endif
-+
-+
-+#endif
-+
- 
-diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
-index 12bc22a..6e64fe7 100644
---- a/include/asm-arm/arch-omap/control.h
-+++ b/include/asm-arm/arch-omap/control.h
-@@ -138,6 +138,15 @@
- #define OMAP343X_CONTROL_TEST_KEY_11	(OMAP2_CONTROL_GENERAL + 0x00f4)
- #define OMAP343X_CONTROL_TEST_KEY_12	(OMAP2_CONTROL_GENERAL + 0x00f8)
- #define OMAP343X_CONTROL_TEST_KEY_13	(OMAP2_CONTROL_GENERAL + 0x00fc)
-+#define OMAP343X_CONTROL_FUSE_OPP1_VDD1	(OMAP2_CONTROL_GENERAL + 0x0110)
-+#define OMAP343X_CONTROL_FUSE_OPP2_VDD1	(OMAP2_CONTROL_GENERAL + 0x0114)
-+#define OMAP343X_CONTROL_FUSE_OPP3_VDD1	(OMAP2_CONTROL_GENERAL + 0x0118)
-+#define OMAP343X_CONTROL_FUSE_OPP4_VDD1	(OMAP2_CONTROL_GENERAL + 0x011c)
-+#define OMAP343X_CONTROL_FUSE_OPP5_VDD1	(OMAP2_CONTROL_GENERAL + 0x0120)
-+#define OMAP343X_CONTROL_FUSE_OPP1_VDD2	(OMAP2_CONTROL_GENERAL + 0x0124)
-+#define OMAP343X_CONTROL_FUSE_OPP2_VDD2	(OMAP2_CONTROL_GENERAL + 0x0128)
-+#define OMAP343X_CONTROL_FUSE_OPP3_VDD2	(OMAP2_CONTROL_GENERAL + 0x012c)
-+#define OMAP343X_CONTROL_FUSE_SR	(OMAP2_CONTROL_GENERAL + 0x0130)
- #define OMAP343X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
- #define OMAP343X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
- #define OMAP343X_CONTROL_TEMP_SENSOR	(OMAP2_CONTROL_GENERAL + 0x02b4)
-@@ -172,6 +181,16 @@
- #define OMAP2_SYSBOOT_1_MASK		(1 << 1)
- #define OMAP2_SYSBOOT_0_MASK		(1 << 0)
- 
-+/* CONTROL_FUSE_SR bits */
-+#define OMAP343X_SR2_SENNENABLE_MASK	(0x3 << 10)
-+#define OMAP343X_SR2_SENNENABLE_SHIFT	10
-+#define OMAP343X_SR2_SENPENABLE_MASK	(0x3 << 8)
-+#define OMAP343X_SR2_SENPENABLE_SHIFT	8
-+#define OMAP343X_SR1_SENNENABLE_MASK	(0x3 << 2)
-+#define OMAP343X_SR1_SENNENABLE_SHIFT	2
-+#define OMAP343X_SR1_SENPENABLE_MASK	(0x3 << 0)
-+#define OMAP343X_SR1_SENPENABLE_SHIFT	0
-+
- #ifndef __ASSEMBLY__
- #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
- extern void __iomem *omap_ctrl_base_get(void);
-diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
-index 6a0459a..3667fd6 100644
---- a/include/asm-arm/arch-omap/omap34xx.h
-+++ b/include/asm-arm/arch-omap/omap34xx.h
-@@ -54,6 +54,8 @@
- #define OMAP34XX_HSUSB_OTG_BASE	(L4_34XX_BASE + 0xAB000)
- #define OMAP34XX_HSUSB_HOST_BASE	(L4_34XX_BASE + 0x64000)
- #define OMAP34XX_USBTLL_BASE	(L4_34XX_BASE + 0x62000)
-+#define OMAP34XX_SR1_BASE	0x480C9000
-+#define OMAP34XX_SR2_BASE	0x480CB000
- 
- 
- #if defined(CONFIG_ARCH_OMAP3430)
--- 
-1.5.4.3
diff --git a/packages/linux/linux-omap2-git/beagleboard/0003-ARM-OMAP-SmartReflex-driver.patch b/packages/linux/linux-omap2-git/beagleboard/0003-ARM-OMAP-SmartReflex-driver.patch
deleted file mode 100644
index 40d5790367..0000000000
--- a/packages/linux/linux-omap2-git/beagleboard/0003-ARM-OMAP-SmartReflex-driver.patch
+++ /dev/null
@@ -1,1001 +0,0 @@
-From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
-To: linux-omap@vger.kernel.org
-Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
-Subject: [PATCH 3/3] ARM: OMAP: SmartReflex driver: integration to linux-omap
-Date: 	Fri,  6 Jun 2008 12:49:49 +0300
-Message-Id: <1212745789-13926-3-git-send-email-ext-kalle.jokiniemi@nokia.com>
-
-- Changed register accesses to use prm_{read,write}_mod_reg and
-  prm_{set,clear,rmw}_mod_reg_bits() functions instread of
-  "REG_X = REG_Y" type accesses.
-
-- Changed direct register clock enables/disables to clockframework calls.
-
-- replaced cpu-related #ifdefs with if (cpu_is_xxxx()) calls.
-
-- Added E-fuse support: Use silicon characteristics parameters from E-fuse
-
-- added smartreflex_disable/enable calls to pm34xx.c suspend function.
-
-- Added "SmartReflex support" entry into Kconfig under "System type->TI OMAP
-  Implementations". It depends on ARCH_OMAP34XX and TWL4030_CORE.
-
-- Added "SmartReflex testing support" Kconfig option for using hard coded
-  software parameters instead of E-fuse parameters.
-
-Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
----
- arch/arm/mach-omap2/Makefile      |    3 +
- arch/arm/mach-omap2/pm34xx.c      |    9 +
- arch/arm/mach-omap2/smartreflex.c |  531 +++++++++++++++++++++++--------------
- arch/arm/mach-omap2/smartreflex.h |    9 +-
- arch/arm/plat-omap/Kconfig        |   31 +++
- 5 files changed, 385 insertions(+), 198 deletions(-)
-
-diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
-index 50c6657..f645b6e 100644
---- a/arch/arm/mach-omap2/Makefile
-+++ b/arch/arm/mach-omap2/Makefile
-@@ -25,6 +25,9 @@ obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o
- obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
- endif
- 
-+# SmartReflex driver
-+obj-$(CONFIG_OMAP_SMARTREFLEX)		+= smartreflex.o
-+
- # Clock framework
- obj-$(CONFIG_ARCH_OMAP2)		+= clock24xx.o
- obj-$(CONFIG_ARCH_OMAP3)		+= clock34xx.o
-diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
-index 7e775cc..3da4f47 100644
---- a/arch/arm/mach-omap2/pm34xx.c
-+++ b/arch/arm/mach-omap2/pm34xx.c
-@@ -36,6 +36,7 @@
- 
- #include "prm.h"
- #include "pm.h"
-+#include "smartreflex.h"
- 
- struct power_state {
- 	struct powerdomain *pwrdm;
-@@ -256,6 +257,10 @@ static int omap3_pm_suspend(void)
- 	struct power_state *pwrst;
- 	int state, ret = 0;
- 
-+	/* XXX Disable smartreflex before entering suspend */
-+	disable_smartreflex(SR1);
-+	disable_smartreflex(SR2);
-+
- 	/* Read current next_pwrsts */
- 	list_for_each_entry(pwrst, &pwrst_list, node)
- 		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
-@@ -287,6 +292,10 @@ restore:
- 		printk(KERN_INFO "Successfully put all powerdomains "
- 		       "to target state\n");
- 
-+	/* XXX Enable smartreflex after suspend */
-+	enable_smartreflex(SR1);
-+	enable_smartreflex(SR2);
-+
- 	return ret;
- }
- 
-diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
-index dae7460..0b10a5d 100644
---- a/arch/arm/mach-omap2/smartreflex.c
-+++ b/arch/arm/mach-omap2/smartreflex.c
-@@ -3,6 +3,9 @@
-  *
-  * OMAP34XX SmartReflex Voltage Control
-  *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Kalle Jokiniemi
-+ *
-  * Copyright (C) 2007 Texas Instruments, Inc.
-  * Lesly A M <x0080970@ti.com>
-  *
-@@ -20,13 +23,16 @@
- #include <linux/err.h>
- #include <linux/clk.h>
- #include <linux/sysfs.h>
--
--#include <asm/arch/prcm.h>
--#include <asm/arch/power_companion.h>
-+#include <linux/kobject.h>
-+#include <linux/i2c/twl4030.h>
- #include <linux/io.h>
- 
--#include "prcm-regs.h"
-+#include <asm/arch/omap34xx.h>
-+#include <asm/arch/control.h>
-+
-+#include "prm.h"
- #include "smartreflex.h"
-+#include "prm-regbits-34xx.h"
- 
- 
- /* #define DEBUG_SR 1 */
-@@ -37,11 +43,16 @@
- #  define DPRINTK(fmt, args...)
- #endif
- 
-+/* XXX: These should be relocated where-ever the OPP implementation will be */
-+u32 current_vdd1_opp;
-+u32 current_vdd2_opp;
-+
- struct omap_sr{
- 	int srid;
- 	int is_sr_reset;
- 	int is_autocomp_active;
- 	struct clk *fck;
-+	u32 clk_length;
- 	u32 req_opp_no;
- 	u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue;
- 	u32 senp_mod, senn_mod;
-@@ -53,6 +64,7 @@ static struct omap_sr sr1 = {
- 	.srid = SR1,
- 	.is_sr_reset = 1,
- 	.is_autocomp_active = 0,
-+	.clk_length = 0,
- 	.srbase_addr = OMAP34XX_SR1_BASE,
- };
- 
-@@ -60,6 +72,7 @@ static struct omap_sr sr2 = {
- 	.srid = SR2,
- 	.is_sr_reset = 1,
- 	.is_autocomp_active = 0,
-+	.clk_length = 0,
- 	.srbase_addr = OMAP34XX_SR2_BASE,
- };
- 
-@@ -85,8 +98,6 @@ static inline u32 sr_read_reg(struct omap_sr *sr, int offset)
- 	return omap_readl(sr->srbase_addr + offset);
- }
- 
--
--#ifndef USE_EFUSE_VALUES
- static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
- {
- 	u32 gn, rn, mul;
-@@ -100,7 +111,21 @@ static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
- 		}
- 	}
- }
--#endif
-+
-+static void sr_clk_get(struct omap_sr *sr)
-+{
-+	if (sr->srid == SR1) {
-+		sr->fck = clk_get(NULL, "sr1_fck");
-+		if (IS_ERR(sr->fck))
-+			printk(KERN_ERR "Could not get sr1_fck\n");
-+
-+	} else if (sr->srid == SR2) {
-+		sr->fck = clk_get(NULL, "sr2_fck");
-+		if (IS_ERR(sr->fck))
-+			printk(KERN_ERR "Could not get sr2_fck\n");
-+
-+	}
-+}
- 
- static int sr_clk_enable(struct omap_sr *sr)
- {
-@@ -131,22 +156,86 @@ static int sr_clk_disable(struct omap_sr *sr)
- 	return 0;
- }
- 
--static void sr_set_nvalues(struct omap_sr *sr)
-+static void sr_set_clk_length(struct omap_sr *sr)
-+{
-+	struct clk *osc_sys_ck;
-+	u32 sys_clk = 0;
-+
-+	osc_sys_ck = clk_get(NULL, "osc_sys_ck");
-+	sys_clk = clk_get_rate(osc_sys_ck);
-+	clk_put(osc_sys_ck);
-+
-+	switch (sys_clk) {
-+	case 12000000:
-+		sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
-+		break;
-+	case 13000000:
-+		sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
-+		break;
-+	case 19200000:
-+		sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
-+		break;
-+	case 26000000:
-+		sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
-+		break;
-+	case 38400000:
-+		sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
-+		break;
-+	default :
-+		printk(KERN_ERR "Invalid sysclk value: %d\n", sys_clk);
-+		break;
-+	}
-+}
-+
-+static void sr_set_efuse_nvalues(struct omap_sr *sr)
-+{
-+	if (sr->srid == SR1) {
-+		sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
-+					OMAP343X_SR1_SENNENABLE_MASK) >>
-+					OMAP343X_SR1_SENNENABLE_SHIFT;
-+
-+		sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
-+					OMAP343X_SR1_SENPENABLE_MASK) >>
-+					OMAP343X_SR1_SENPENABLE_SHIFT;
-+
-+		sr->opp5_nvalue = omap_ctrl_readl(
-+					OMAP343X_CONTROL_FUSE_OPP5_VDD1);
-+		sr->opp4_nvalue = omap_ctrl_readl(
-+					OMAP343X_CONTROL_FUSE_OPP4_VDD1);
-+		sr->opp3_nvalue = omap_ctrl_readl(
-+					OMAP343X_CONTROL_FUSE_OPP3_VDD1);
-+		sr->opp2_nvalue = omap_ctrl_readl(
-+					OMAP343X_CONTROL_FUSE_OPP2_VDD1);
-+		sr->opp1_nvalue = omap_ctrl_readl(
-+					OMAP343X_CONTROL_FUSE_OPP1_VDD1);
-+	} else if (sr->srid == SR2) {
-+		sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
-+					OMAP343X_SR2_SENNENABLE_MASK) >>
-+					OMAP343X_SR2_SENNENABLE_SHIFT;
-+
-+		sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
-+					OMAP343X_SR2_SENPENABLE_MASK) >>
-+					OMAP343X_SR2_SENPENABLE_SHIFT;
-+
-+		sr->opp3_nvalue = omap_ctrl_readl(
-+					OMAP343X_CONTROL_FUSE_OPP3_VDD2);
-+		sr->opp2_nvalue = omap_ctrl_readl(
-+					OMAP343X_CONTROL_FUSE_OPP2_VDD2);
-+		sr->opp1_nvalue = omap_ctrl_readl(
-+					OMAP343X_CONTROL_FUSE_OPP1_VDD2);
-+	}
-+}
-+
-+/* Hard coded nvalues for testing purposes, may cause device to hang! */
-+static void sr_set_testing_nvalues(struct omap_sr *sr)
- {
--#ifdef USE_EFUSE_VALUES
--	u32 n1, n2;
--#else
- 	u32 senpval, sennval;
- 	u32 senpgain, senngain;
- 	u32 rnsenp, rnsenn;
--#endif
- 
- 	if (sr->srid == SR1) {
--#ifdef USE_EFUSE_VALUES
--		/* Read values for VDD1 from EFUSE */
--#else
--		/* since E-Fuse Values are not available, calculating the
--		 * reciprocal of the SenN and SenP values for SR1
-+		/* Calculating the reciprocal of the SenN and SenP values
-+		 * for SR1
- 		 */
- 		sr->senp_mod = 0x03;        /* SenN-M5 enabled */
- 		sr->senn_mod = 0x03;
-@@ -216,15 +305,16 @@ static void sr_set_nvalues(struct omap_sr *sr)
- 				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
- 				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
- 
-+		/* XXX The clocks are enabled in the startup and NVALUE is
-+		 * set also there. Disabling this for now, but this could
-+		 * be related to dynamic sleep during boot */
-+#if 0
- 		sr_clk_enable(sr);
- 		sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue);
- 		sr_clk_disable(sr);
--
- #endif
-+
- 	} else if (sr->srid == SR2) {
--#ifdef USE_EFUSE_VALUES
--		/* Read values for VDD2 from EFUSE */
--#else
- 		/* since E-Fuse Values are not available, calculating the
- 		 * reciprocal of the SenN and SenP values for SR2
- 		 */
-@@ -269,134 +359,163 @@ static void sr_set_nvalues(struct omap_sr *sr)
- 				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
- 				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
- 				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
--
--#endif
- 	}
- 
- }
- 
-+static void sr_set_nvalues(struct omap_sr *sr)
-+{
-+	if (SR_TESTING_NVALUES)
-+		sr_set_testing_nvalues(sr);
-+	else
-+		sr_set_efuse_nvalues(sr);
-+}
-+
- static void sr_configure_vp(int srid)
- {
- 	u32 vpconfig;
- 
- 	if (srid == SR1) {
- 		vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN
--			| PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN;
--
--		PRM_VP1_CONFIG = vpconfig;
--		PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
--						PRM_VP1_VSTEPMIN_VSTEPMIN;
--
--		PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
--						PRM_VP1_VSTEPMAX_VSTEPMAX;
--
--		PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX |
--			PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT;
--
--		PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD;
--		PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD;
-+					| PRM_VP1_CONFIG_INITVOLTAGE
-+					| PRM_VP1_CONFIG_TIMEOUTEN;
-+
-+		prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP1_CONFIG_OFFSET);
-+		prm_write_mod_reg(PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
-+					PRM_VP1_VSTEPMIN_VSTEPMIN,
-+					OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP1_VSTEPMIN_OFFSET);
-+
-+		prm_write_mod_reg(PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
-+					PRM_VP1_VSTEPMAX_VSTEPMAX,
-+					OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP1_VSTEPMAX_OFFSET);
-+
-+		prm_write_mod_reg(PRM_VP1_VLIMITTO_VDDMAX |
-+					PRM_VP1_VLIMITTO_VDDMIN |
-+					PRM_VP1_VLIMITTO_TIMEOUT,
-+					OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP1_VLIMITTO_OFFSET);
-+
-+		/* Trigger initVDD value copy to voltage processor */
-+		prm_set_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP1_CONFIG_OFFSET);
-+		/* Clear initVDD copy trigger bit */
-+		prm_clear_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP1_CONFIG_OFFSET);
- 
- 	} else if (srid == SR2) {
- 		vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN
--			| PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN;
--
--		PRM_VP2_CONFIG = vpconfig;
--		PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
--						PRM_VP2_VSTEPMIN_VSTEPMIN;
--
--		PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
--						PRM_VP2_VSTEPMAX_VSTEPMAX;
--
--		PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX |
--			PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT;
--
--		PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD;
--		PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD;
-+					| PRM_VP2_CONFIG_INITVOLTAGE
-+					| PRM_VP2_CONFIG_TIMEOUTEN;
-+
-+		prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP2_CONFIG_OFFSET);
-+		prm_write_mod_reg(PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
-+					PRM_VP2_VSTEPMIN_VSTEPMIN,
-+					OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP2_VSTEPMIN_OFFSET);
-+
-+		prm_write_mod_reg(PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
-+					PRM_VP2_VSTEPMAX_VSTEPMAX,
-+					OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP2_VSTEPMAX_OFFSET);
-+
-+		prm_write_mod_reg(PRM_VP2_VLIMITTO_VDDMAX |
-+					PRM_VP2_VLIMITTO_VDDMIN |
-+					PRM_VP2_VLIMITTO_TIMEOUT,
-+					OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP2_VLIMITTO_OFFSET);
-+
-+		/* Trigger initVDD value copy to voltage processor */
-+		prm_set_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP2_CONFIG_OFFSET);
-+		/* Reset initVDD copy trigger bit */
-+		prm_clear_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP2_CONFIG_OFFSET);
- 
- 	}
- }
- 
- static void sr_configure_vc(void)
- {
--	PRM_VC_SMPS_SA =
--		(R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) |
--		(R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT);
--
--	PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) |
--				(R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT);
--
--	PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) |
--			(PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
--			(PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) |
--			(PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT);
--
--	PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) |
--			(PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
--			(PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) |
--			(PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT);
--
--	PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1;
--
--	PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN
--							| PRM_VC_I2C_CFG_SREN;
-+	prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) |
-+			(R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT),
-+			OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
-+
-+	prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) |
-+			(R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
-+			OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
-+
-+	prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON <<
-+		OMAP3430_VC_CMD_ON_SHIFT) |
-+		(OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
-+		(OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) |
-+		(OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
-+		OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
-+
-+	prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON <<
-+		OMAP3430_VC_CMD_ON_SHIFT) |
-+		(OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
-+		(OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) |
-+		(OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
-+		OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
-+
-+	prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
-+				OMAP3430_GR_MOD,
-+				OMAP3_PRM_VC_CH_CONF_OFFSET);
-+
-+	prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
-+				OMAP3430_GR_MOD,
-+				OMAP3_PRM_VC_I2C_CFG_OFFSET);
- 
- 	/* Setup voltctrl and other setup times */
-+	/* XXX CONFIG_SYSOFFMODE has not been implemented yet */
- #ifdef CONFIG_SYSOFFMODE
--	PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET;
--	PRM_CLKSETUP = PRM_CLKSETUP_DURATION;
--	PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) |
--			(PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET);
--	PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION;
--	PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION;
-+	prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET,
-+			OMAP3430_GR_MOD,
-+			OMAP3_PRM_VOLTCTRL_OFFSET);
-+
-+	prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
-+			OMAP3_PRM_CLKSETUP_OFFSET);
-+	prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 <<
-+			OMAP3430_VOLTSETUP_TIME2_OFFSET) |
-+			(OMAP3430_VOLTSETUP_TIME1 <<
-+			OMAP3430_VOLTSETUP_TIME1_OFFSET),
-+			OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
-+
-+	prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
-+			OMAP3_PRM_VOLTOFFSET_OFFSET);
-+	prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
-+			OMAP3_PRM_VOLTSETUP2_OFFSET);
- #else
--	PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET;
-+	prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
-+			OMAP3_PRM_VOLTCTRL_OFFSET);
- #endif
- 
- }
- 
--
- static void sr_configure(struct omap_sr *sr)
- {
--	u32 sys_clk, sr_clk_length = 0;
- 	u32 sr_config;
- 	u32 senp_en , senn_en;
- 
-+	if (sr->clk_length == 0)
-+		sr_set_clk_length(sr);
-+
- 	senp_en = sr->senp_mod;
- 	senn_en = sr->senn_mod;
--
--	sys_clk = prcm_get_system_clock_speed();
--
--	switch (sys_clk) {
--	case 12000:
--		sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
--		break;
--	case 13000:
--		sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
--		break;
--	case 19200:
--		sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
--		break;
--	case 26000:
--		sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
--		break;
--	case 38400:
--		sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
--		break;
--	default :
--		printk(KERN_ERR "Invalid sysclk value\n");
--		break;
--	}
--
--	DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk);
- 	if (sr->srid == SR1) {
- 		sr_config = SR1_SRCONFIG_ACCUMDATA |
--			(sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-+			(sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
- 			SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
- 			SRCONFIG_MINMAXAVG_EN |
- 			(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
- 			(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
- 			SRCONFIG_DELAYCTRL;
--
-+		DPRINTK(KERN_DEBUG "setting SRCONFIG1 to 0x%08lx\n",
-+						(unsigned long int) sr_config);
- 		sr_write_reg(sr, SRCONFIG, sr_config);
- 
- 		sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
-@@ -408,18 +527,18 @@ static void sr_configure(struct omap_sr *sr)
- 
- 	} else if (sr->srid == SR2) {
- 		sr_config = SR2_SRCONFIG_ACCUMDATA |
--			(sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-+			(sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
- 			SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
- 			SRCONFIG_MINMAXAVG_EN |
- 			(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
- 			(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
- 			SRCONFIG_DELAYCTRL;
- 
-+		DPRINTK(KERN_DEBUG "setting SRCONFIG2 to 0x%08lx\n",
-+						(unsigned long int) sr_config);
- 		sr_write_reg(sr, SRCONFIG, sr_config);
--
- 		sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
- 					SR2_AVGWEIGHT_SENNAVGWEIGHT);
--
- 		sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
- 			SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
- 			(SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
-@@ -428,9 +547,9 @@ static void sr_configure(struct omap_sr *sr)
- 	sr->is_sr_reset = 0;
- }
- 
--static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
-+static int sr_enable(struct omap_sr *sr, u32 target_opp_no)
- {
--	u32 nvalue_reciprocal, current_nvalue;
-+	u32 nvalue_reciprocal;
- 
- 	sr->req_opp_no = target_opp_no;
- 
-@@ -472,11 +591,10 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
- 		}
- 	}
- 
--	current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL);
--
--	if (current_nvalue == nvalue_reciprocal) {
--		DPRINTK("System is already at the desired voltage level\n");
--		return;
-+	if (nvalue_reciprocal == 0) {
-+		printk(KERN_NOTICE "OPP%d doesn't support SmartReflex\n",
-+								target_opp_no);
-+		return SR_FALSE;
- 	}
- 
- 	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
-@@ -485,18 +603,19 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
- 	sr_modify_reg(sr, ERRCONFIG,
- 			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
- 			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
--
- 	if (sr->srid == SR1) {
- 		/* Enable VP1 */
--		PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE;
-+		prm_set_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD,
-+				OMAP3_PRM_VP1_CONFIG_OFFSET);
- 	} else if (sr->srid == SR2) {
- 		/* Enable VP2 */
--		PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE;
-+		prm_set_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD,
-+				OMAP3_PRM_VP2_CONFIG_OFFSET);
- 	}
- 
- 	/* SRCONFIG - enable SR */
- 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
--
-+	return SR_TRUE;
- }
- 
- static void sr_disable(struct omap_sr *sr)
-@@ -507,11 +626,13 @@ static void sr_disable(struct omap_sr *sr)
- 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);
- 
- 	if (sr->srid == SR1) {
--		/* Enable VP1 */
--		PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
-+		/* Disable VP1 */
-+		prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP1_CONFIG_OFFSET);
- 	} else if (sr->srid == SR2) {
--		/* Enable VP2 */
--		PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
-+		/* Disable VP2 */
-+		prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD,
-+					OMAP3_PRM_VP2_CONFIG_OFFSET);
- 	}
- }
- 
-@@ -535,7 +656,12 @@ void sr_start_vddautocomap(int srid, u32 target_opp_no)
- 									srid);
- 
- 	sr->is_autocomp_active = 1;
--	sr_enable(sr, target_opp_no);
-+	if (!sr_enable(sr, target_opp_no)) {
-+		printk(KERN_WARNING "SR%d: VDD autocomp not activated\n", srid);
-+		sr->is_autocomp_active = 0;
-+		if (sr->is_sr_reset == 1)
-+			sr_clk_disable(sr);
-+	}
- }
- EXPORT_SYMBOL(sr_start_vddautocomap);
- 
-@@ -574,20 +700,18 @@ void enable_smartreflex(int srid)
- 
- 	if (sr->is_autocomp_active == 1) {
- 		if (sr->is_sr_reset == 1) {
--			if (srid == SR1) {
--				/* Enable SR clks */
--				CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
--				target_opp_no = get_opp_no(current_vdd1_opp);
-+			/* Enable SR clks */
-+			sr_clk_enable(sr);
- 
--			} else if (srid == SR2) {
--				/* Enable SR clks */
--				CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
-+			if (srid == SR1)
-+				target_opp_no = get_opp_no(current_vdd1_opp);
-+			else if (srid == SR2)
- 				target_opp_no = get_opp_no(current_vdd2_opp);
--			}
- 
- 			sr_configure(sr);
- 
--			sr_enable(sr, target_opp_no);
-+			if (!sr_enable(sr, target_opp_no))
-+				sr_clk_disable(sr);
- 		}
- 	}
- }
-@@ -602,15 +726,6 @@ void disable_smartreflex(int srid)
- 		sr = &sr2;
- 
- 	if (sr->is_autocomp_active == 1) {
--		if (srid == SR1) {
--			/* Enable SR clk */
--			CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
--
--		} else if (srid == SR2) {
--			/* Enable SR clk */
--			CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
--		}
--
- 		if (sr->is_sr_reset == 0) {
- 
- 			sr->is_sr_reset = 1;
-@@ -618,17 +733,18 @@ void disable_smartreflex(int srid)
- 			sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
- 							~SRCONFIG_SRENABLE);
- 
-+			/* Disable SR clk */
-+			sr_clk_disable(sr);
- 			if (sr->srid == SR1) {
--				/* Disable SR clk */
--				CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE;
--				/* Enable VP1 */
--				PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
--
-+				/* Disable VP1 */
-+				prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE,
-+						OMAP3430_GR_MOD,
-+						OMAP3_PRM_VP1_CONFIG_OFFSET);
- 			} else if (sr->srid == SR2) {
--				/* Disable SR clk */
--				CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE;
--				/* Enable VP2 */
--				PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
-+				/* Disable VP2 */
-+				prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE,
-+						OMAP3430_GR_MOD,
-+						OMAP3_PRM_VP2_CONFIG_OFFSET);
- 			}
- 		}
- 	}
-@@ -638,7 +754,6 @@ void disable_smartreflex(int srid)
- /* Voltage Scaling using SR VCBYPASS */
- int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
- {
--	int ret;
- 	int sr_status = 0;
- 	u32 vdd, target_opp_no;
- 	u32 vc_bypass_value;
-@@ -651,39 +766,53 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
- 	if (vdd == PRCM_VDD1) {
- 		sr_status = sr_stop_vddautocomap(SR1);
- 
--		PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) |
--						(vsel << PRM_VC_CMD_ON_SHIFT);
-+		prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
-+					(vsel << OMAP3430_VC_CMD_ON_SHIFT),
-+					OMAP3430_GR_MOD,
-+					OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
- 		reg_addr = R_VDD1_SR_CONTROL;
- 
- 	} else if (vdd == PRCM_VDD2) {
- 		sr_status = sr_stop_vddautocomap(SR2);
- 
--		PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) |
--						(vsel << PRM_VC_CMD_ON_SHIFT);
-+		prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
-+					(vsel << OMAP3430_VC_CMD_ON_SHIFT),
-+					OMAP3430_GR_MOD,
-+					OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
- 		reg_addr = R_VDD2_SR_CONTROL;
- 	}
- 
--	vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) |
--			(reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) |
--			(R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT);
-+	vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) |
-+			(reg_addr << OMAP3430_REGADDR_SHIFT) |
-+			(R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT);
- 
--	PRM_VC_BYPASS_VAL = vc_bypass_value;
-+	prm_write_mod_reg(vc_bypass_value, OMAP3430_GR_MOD,
-+			OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
- 
--	PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID;
-+	vc_bypass_value = prm_set_mod_reg_bits(OMAP3430_VALID, OMAP3430_GR_MOD,
-+					OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
- 
--	DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL);
--	DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU);
-+	DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, vc_bypass_value);
-+	DPRINTK("PRM_IRQST_MPU %X\n", prm_read_mod_reg(OCP_MOD,
-+					OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
- 
--	while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) {
--		ret = loop_wait(&loop_cnt, &retries_cnt, 10);
--		if (ret != PRCM_PASS) {
-+	while ((vc_bypass_value & OMAP3430_VALID) != 0x0) {
-+		loop_cnt++;
-+		if (retries_cnt > 10) {
- 			printk(KERN_INFO "Loop count exceeded in check SR I2C"
- 								"write\n");
--			return ret;
-+			return SR_FAIL;
-+		}
-+		if (loop_cnt > 50) {
-+			retries_cnt++;
-+			loop_cnt = 0;
-+			udelay(10);
- 		}
-+		vc_bypass_value = prm_read_mod_reg(OMAP3430_GR_MOD,
-+					OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
- 	}
- 
--	omap_udelay(T2_SMPS_UPDATE_DELAY);
-+	udelay(T2_SMPS_UPDATE_DELAY);
- 
- 	if (sr_status) {
- 		if (vdd == PRCM_VDD1)
-@@ -696,13 +825,15 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
- }
- 
- /* Sysfs interface to select SR VDD1 auto compensation */
--static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf)
-+static ssize_t omap_sr_vdd1_autocomp_show(struct kobject *kobj,
-+					struct kobj_attribute *attr, char *buf)
- {
- 	return sprintf(buf, "%d\n", sr1.is_autocomp_active);
- }
- 
--static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
--				const char *buf, size_t n)
-+static ssize_t omap_sr_vdd1_autocomp_store(struct kobject *kobj,
-+					struct kobj_attribute *attr,
-+					const char *buf, size_t n)
- {
- 	u32 current_vdd1opp_no;
- 	unsigned short value;
-@@ -722,7 +853,7 @@ static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
- 	return n;
- }
- 
--static struct subsys_attribute sr_vdd1_autocomp = {
-+static struct kobj_attribute sr_vdd1_autocomp = {
- 	.attr = {
- 	.name = __stringify(sr_vdd1_autocomp),
- 	.mode = 0644,
-@@ -732,13 +863,15 @@ static struct subsys_attribute sr_vdd1_autocomp = {
- };
- 
- /* Sysfs interface to select SR VDD2 auto compensation */
--static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf)
-+static ssize_t omap_sr_vdd2_autocomp_show(struct kobject *kobj,
-+					struct kobj_attribute *attr, char *buf)
- {
- 	return sprintf(buf, "%d\n", sr2.is_autocomp_active);
- }
- 
--static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
--				const char *buf, size_t n)
-+static ssize_t omap_sr_vdd2_autocomp_store(struct kobject *kobj,
-+					struct kobj_attribute *attr,
-+					const char *buf, size_t n)
- {
- 	u32 current_vdd2opp_no;
- 	unsigned short value;
-@@ -758,7 +891,7 @@ static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
- 	return n;
- }
- 
--static struct subsys_attribute sr_vdd2_autocomp = {
-+static struct kobj_attribute sr_vdd2_autocomp = {
- 	.attr = {
- 	.name = __stringify(sr_vdd2_autocomp),
- 	.mode = 0644,
-@@ -774,15 +907,19 @@ static int __init omap3_sr_init(void)
- 	int ret = 0;
- 	u8 RdReg;
- 
--#ifdef CONFIG_ARCH_OMAP34XX
--	sr1.fck = clk_get(NULL, "sr1_fck");
--	if (IS_ERR(sr1.fck))
--		printk(KERN_ERR "Could not get sr1_fck\n");
--
--	sr2.fck = clk_get(NULL, "sr2_fck");
--	if (IS_ERR(sr2.fck))
--		printk(KERN_ERR "Could not get sr2_fck\n");
--#endif /* #ifdef CONFIG_ARCH_OMAP34XX */
-+	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
-+		current_vdd1_opp = PRCM_VDD1_OPP3;
-+		current_vdd2_opp = PRCM_VDD2_OPP3;
-+	} else {
-+		current_vdd1_opp = PRCM_VDD1_OPP1;
-+		current_vdd2_opp = PRCM_VDD1_OPP1;
-+	}
-+	if (cpu_is_omap34xx()) {
-+		sr_clk_get(&sr1);
-+		sr_clk_get(&sr2);
-+	}
-+	sr_set_clk_length(&sr1);
-+	sr_set_clk_length(&sr2);
- 
- 	/* Call the VPConfig, VCConfig, set N Values. */
- 	sr_set_nvalues(&sr1);
-@@ -794,22 +931,24 @@ static int __init omap3_sr_init(void)
- 	sr_configure_vc();
- 
- 	/* Enable SR on T2 */
--	ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG);
--	RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
--	ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG);
-+	ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &RdReg,
-+					R_DCDC_GLOBAL_CFG);
- 
-+	RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
-+	ret |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, RdReg,
-+					R_DCDC_GLOBAL_CFG);
- 
- 	printk(KERN_INFO "SmartReflex driver initialized\n");
- 
--	ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp);
-+	ret = sysfs_create_file(power_kobj, &sr_vdd1_autocomp.attr);
- 	if (ret)
--		printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
-+		printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);
- 
--	ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp);
-+	ret = sysfs_create_file(power_kobj, &sr_vdd2_autocomp.attr);
- 	if (ret)
--		printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
-+		printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);
- 
- 	return 0;
- }
- 
--arch_initcall(omap3_sr_init);
-+late_initcall(omap3_sr_init);
-diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
-index 2091a15..194429e 100644
---- a/arch/arm/mach-omap2/smartreflex.h
-+++ b/arch/arm/mach-omap2/smartreflex.h
-@@ -233,12 +233,18 @@
- extern u32 current_vdd1_opp;
- extern u32 current_vdd2_opp;
- 
-+#ifdef CONFIG_OMAP_SMARTREFLEX_TESTING
-+#define SR_TESTING_NVALUES 	1
-+#else
-+#define SR_TESTING_NVALUES 	0
-+#endif
-+
- /*
-  * Smartreflex module enable/disable interface.
-  * NOTE: if smartreflex is not enabled from sysfs, these functions will not
-  * do anything.
-  */
--#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
-+#ifdef CONFIG_OMAP_SMARTREFLEX
- void enable_smartreflex(int srid);
- void disable_smartreflex(int srid);
- #else
-@@ -246,7 +252,6 @@ static inline void enable_smartreflex(int srid) {}
- static inline void disable_smartreflex(int srid) {}
- #endif
- 
--
- #endif
- 
- 
-diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
-index b085b07..960c13f 100644
---- a/arch/arm/plat-omap/Kconfig
-+++ b/arch/arm/plat-omap/Kconfig
-@@ -56,6 +56,37 @@ config OMAP_DEBUG_CLOCKDOMAIN
- 	  for every clockdomain register write.  However, the
- 	  extra detail costs some memory.
- 
-+config OMAP_SMARTREFLEX
-+	bool "SmartReflex support"
-+	depends on ARCH_OMAP34XX && TWL4030_CORE
-+	help
-+	  Say Y if you want to enable SmartReflex.
-+
-+	  SmartReflex can perform continuous dynamic voltage
-+	  scaling around the nominal operating point voltage
-+	  according to silicon characteristics and operating
-+	  conditions. Enabling SmartReflex reduces power
-+	  consumption.
-+
-+	  Please note, that by default SmartReflex is only
-+	  initialized. To enable the automatic voltage
-+	  compensation for VDD1 and VDD2, user must write 1 to
-+	  /sys/power/sr_vddX_autocomp, where X is 1 or 2.
-+
-+config OMAP_SMARTREFLEX_TESTING
-+	bool "Smartreflex testing support"
-+	depends on OMAP_SMARTREFLEX
-+	default n
-+	help
-+	  Say Y if you want to enable SmartReflex testing with SW hardcoded
-+	  NVALUES intead of E-fuse NVALUES set in factory silicon testing.
-+
-+	  In some devices the E-fuse values have not been set, even though
-+	  SmartReflex modules are included. Using these hardcoded values set
-+	  in software, one can test the SmartReflex features without E-fuse.
-+
-+	  WARNING: Enabling this option may cause your device to hang!
-+
- config OMAP_RESET_CLOCKS
- 	bool "Reset unused clocks during boot"
- 	depends on ARCH_OMAP
--- 
-1.5.4.3