nas100d-kernel: Latest 2.6.15-rc1 patches added.

3 files changed, 179 insertions, 17 deletions

diff --git a/packages/linux/nas100d-kernel/2.6.15/60-nas100d-ide.patch b/packages/linux/nas100d-kernel/2.6.15/60-nas100d-ide.patch
index 9f5d164356..afd7d9c750 100644
--- a/packages/linux/nas100d-kernel/2.6.15/60-nas100d-ide.patch
+++ b/packages/linux/nas100d-kernel/2.6.15/60-nas100d-ide.patch
@@ -1,17 +1,18 @@
- drivers/ide/pci/aec62xx.c |   51 +++++++++++++++++++++++++++++++++++++++++++---
- drivers/ide/setup-pci.c   |   12 +++++++++-
- 2 files changed, 59 insertions(+), 4 deletions(-)
+ drivers/ide/pci/aec62xx.c |   67 +++++++++++++++++++++++++++++++++++++++++++---
+ drivers/ide/setup-pci.c   |   12 +++++++-
+ 2 files changed, 75 insertions(+), 4 deletions(-)
 
---- linux-nas100d.orig/drivers/ide/pci/aec62xx.c	2005-11-12 15:38:03.000000000 +0100
-+++ linux-nas100d/drivers/ide/pci/aec62xx.c	2005-11-13 01:45:26.000000000 +0100
-@@ -145,6 +145,15 @@ static int aec6210_tune_chipset (ide_dri
+--- linux-nas100d.orig/drivers/ide/pci/aec62xx.c	2005-11-21 20:49:50.000000000 +0100
++++ linux-nas100d/drivers/ide/pci/aec62xx.c	2005-11-21 22:15:21.000000000 +0100
+@@ -145,6 +145,16 @@ static int aec6210_tune_chipset (ide_dri
  	unsigned long flags;
  
  	local_irq_save(flags);
 +
 +#ifdef CONFIG_MACH_NAS100D
 +	printk(KERN_INFO "aec62xx: nas100d tuning\n");
-+	pci_write_config_byte(hwif->pci_dev, PCI_LATENCY_TIMER, 0x90);
++	pci_write_config_word(hwif->pci_dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER);
++	pci_write_config_byte(hwif->pci_dev, PCI_LATENCY_TIMER, 0x80);
 +	/* Enable burst mode & force 2 ports enable  */
 +	pci_read_config_byte(hwif->pci_dev, 0x4a, &tmp0);
 +	pci_write_config_byte(hwif->pci_dev, 0x4a, tmp0 | 0x80);
@@ -20,7 +21,25 @@
  	/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
  	pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
  	tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
-@@ -263,7 +272,7 @@ static int aec62xx_irq_timeout (ide_driv
+@@ -206,9 +216,17 @@ static int config_chipset_for_dma (ide_d
+ {
+ 	u8 speed = ide_dma_speed(drive, aec62xx_ratemask(drive));	
+ 
++#ifdef CONFIG_MACH_NAS100D
++	ide_hwif_t *hwif= HWIF(drive);
++	u8 unit		= (drive->select.b.unit & 0x01);
++#endif
+ 	if (!(speed))
+ 		return 0;
+ 
++#ifdef CONFIG_MACH_NAS100D
++	outb((inb(hwif->dma_base+2) & ~(1<<(5+unit))), hwif->dma_base+2);
++#endif
++
+ 	(void) aec62xx_tune_chipset(drive, speed);
+ 	return ide_dma_enable(drive);
+ }
+@@ -263,7 +281,7 @@ static int aec62xx_irq_timeout (ide_driv
  		case PCI_DEVICE_ID_ARTOP_ATP865:
  		case PCI_DEVICE_ID_ARTOP_ATP865R:
  			printk(" AEC62XX time out ");
@@ -29,7 +48,7 @@
  			{
  				int i = 0;
  				u8 reg49h = 0;
-@@ -277,7 +286,7 @@ static int aec62xx_irq_timeout (ide_driv
+@@ -277,7 +295,7 @@ static int aec62xx_irq_timeout (ide_driv
  		default:
  			break;
  	}
@@ -38,7 +57,7 @@
  	{
  		ide_hwif_t *hwif	= HWIF(drive);
  		struct pci_dev *dev	= hwif->pci_dev;
-@@ -299,6 +308,14 @@ static unsigned int __devinit init_chips
+@@ -299,6 +317,14 @@ static unsigned int __devinit init_chips
  {
  	int bus_speed = system_bus_clock();
  
@@ -53,7 +72,7 @@
  	if (dev->resource[PCI_ROM_RESOURCE].start) {
  		pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
  		printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
-@@ -312,12 +329,35 @@ static unsigned int __devinit init_chips
+@@ -312,12 +338,35 @@ static unsigned int __devinit init_chips
  	return dev->irq;
  }
  
@@ -89,7 +108,7 @@
  	if (hwif->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
  		hwif->serialized = hwif->channel;
  		hwif->no_dsc = 1;
-@@ -360,7 +400,7 @@ static void __devinit init_dma_aec62xx(i
+@@ -360,11 +409,18 @@ static void __devinit init_dma_aec62xx(i
  	} else {
  		u8 ata66	= 0;
  		pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
@@ -98,7 +117,18 @@
  			hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
  	}
  
-@@ -427,6 +467,9 @@ static ide_pci_device_t aec62xx_chipsets
+ 	ide_setup_dma(hwif, dmabase, 8);
++#ifdef CONFIG_MACH_NAS100D
++	{
++		u8 dma_stat = hwif->INB(hwif->dma_status);
++		dma_stat |= (1 << 4);
++		hwif->OUTB(dma_stat, hwif->dma_status);
++	}
++#endif
+ }
+ 
+ static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
+@@ -427,6 +483,9 @@ static ide_pci_device_t aec62xx_chipsets
  		.init_dma	= init_dma_aec62xx,
  		.channels	= 2,
  		.autodma	= AUTODMA,
@@ -108,7 +138,7 @@
  		.bootable	= OFF_BOARD,
  	},{	/* 4 */
  		.name		= "AEC6X80R",
-@@ -454,6 +497,8 @@ static int __devinit aec62xx_init_one(st
+@@ -454,6 +513,8 @@ static int __devinit aec62xx_init_one(st
  {
  	ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
  
@@ -117,8 +147,8 @@
  	return d->init_setup(dev, d);
  }
  
---- linux-nas100d.orig/drivers/ide/setup-pci.c	2005-11-12 15:38:03.000000000 +0100
-+++ linux-nas100d/drivers/ide/setup-pci.c	2005-11-13 01:36:30.000000000 +0100
+--- linux-nas100d.orig/drivers/ide/setup-pci.c	2005-11-21 20:49:50.000000000 +0100
++++ linux-nas100d/drivers/ide/setup-pci.c	2005-11-21 22:01:22.000000000 +0100
 @@ -602,10 +602,20 @@ void ide_pci_setup_ports(struct pci_dev 
  		if ((d->flags & IDEPCI_FLAG_FORCE_PDC) &&
  		    (secondpdc++==1) && (port==1))
diff --git a/packages/linux/nas100d-kernel/2.6.15/90-ixp4xx-nslu2.patch b/packages/linux/nas100d-kernel/2.6.15/90-ixp4xx-nslu2.patch
new file mode 100644
index 0000000000..c106f7c957
--- /dev/null
+++ b/packages/linux/nas100d-kernel/2.6.15/90-ixp4xx-nslu2.patch
@@ -0,0 +1,132 @@
+ixp4xx updates:
+  - Handle reads that don't start on a half-word boundary.
+  - Make it work when CPU is in little-endian mode.
+    
+Signed-off-by: John Bowler <jbowler@acm.org>
+Signed-off-by: Alessandro Zummo <a.zummo@towertech.it>
+Signed-off-by: David Vrabel <dvrabel@arcom.com>
+
+Index: linux-2.6-working/drivers/mtd/maps/ixp4xx.c
+===================================================================
+--- linux-2.6-working.orig/drivers/mtd/maps/ixp4xx.c	2005-11-16 15:19:34.000000000 +0000
++++ linux-2.6-working/drivers/mtd/maps/ixp4xx.c	2005-11-16 16:06:54.000000000 +0000
+@@ -34,10 +34,55 @@
+ 
+ #include <linux/reboot.h>
+ 
++/*
++ * Read/write a 16 bit word from flash address 'addr'.
++ *
++ * When the cpu is in little-endian mode it swizzles the address lines
++ * ('address coherency') so we need to undo the swizzling to ensure commands
++ * and the like end up on the correct flash address.
++ *
++ * To further complicate matters, due to the way the expansion bus controller
++ * handles 32 bit reads, the byte stream ABCD is stored on the flash as:
++ *     D15    D0
++ *     +---+---+
++ *     | A | B | 0
++ *     +---+---+
++ *     | C | D | 2
++ *     +---+---+
++ * This means that on LE systems each 16 bit word must be swapped. Note that
++ * this requires CONFIG_MTD_CFI_BE_BYTE_SWAP to be enabled to 'unswap' the CFI
++ * data and other flash commands which are always in D7-D0.
++ */
+ #ifndef __ARMEB__
++#ifndef CONFIG_MTD_CFI_BE_BYTE_SWAP
++#  error CONFIG_MTD_CFI_BE_BYTE_SWAP required
++#endif
++
++static inline u16 flash_read16(void __iomem *addr)
++{
++	return be16_to_cpu(__raw_readw((void __iomem *)((unsigned long)addr ^ 0x2)));
++}
++
++static inline void flash_write16(u16 d, void __iomem *addr)
++{
++	__raw_writew(cpu_to_be16(d), (void __iomem *)((unsigned long)addr ^ 0x2));
++}
++
+ #define	BYTE0(h)	((h) & 0xFF)
+ #define	BYTE1(h)	(((h) >> 8) & 0xFF)
++
+ #else
++
++static inline u16 flash_read16(const void __iomem *addr)
++{
++	return __raw_readw(addr);
++}
++
++static inline void flash_write16(u16 d, void __iomem *addr)
++{
++	__raw_writew(d, addr);
++}
++
+ #define	BYTE0(h)	(((h) >> 8) & 0xFF)
+ #define	BYTE1(h)	((h) & 0xFF)
+ #endif
+@@ -45,7 +90,7 @@
+ static map_word ixp4xx_read16(struct map_info *map, unsigned long ofs)
+ {
+ 	map_word val;
+-	val.x[0] = le16_to_cpu(readw(map->virt + ofs));
++	val.x[0] = flash_read16(map->virt + ofs);
+ 	return val;
+ }
+ 
+@@ -57,19 +102,28 @@
+ static void ixp4xx_copy_from(struct map_info *map, void *to,
+ 			     unsigned long from, ssize_t len)
+ {
+-	int i;
+ 	u8 *dest = (u8 *) to;
+ 	void __iomem *src = map->virt + from;
+-	u16 data;
+ 
+-	for (i = 0; i < (len / 2); i++) {
+-		data = le16_to_cpu(readw(src + 2*i));
+-		dest[i * 2] = BYTE0(data);
+-		dest[i * 2 + 1] = BYTE1(data);
++	if (len <= 0)
++		return;
++
++	if (from & 1) {
++		*dest++ = BYTE1(flash_read16(src));
++                src++;
++		--len;
+ 	}
+ 
+-	if (len & 1)
+-		dest[len - 1] = BYTE0(le16_to_cpu(readw(src + 2*i)));
++	while (len >= 2) {
++		u16 data = flash_read16(src);
++		*dest++ = BYTE0(data);
++		*dest++ = BYTE1(data);
++		src += 2;
++		len -= 2;
++        }
++
++	if (len > 0)
++		*dest++ = BYTE0(flash_read16(src));
+ }
+ 
+ /*
+@@ -79,7 +133,7 @@
+ static void ixp4xx_probe_write16(struct map_info *map, map_word d, unsigned long adr)
+ {
+ 	if (!(adr & 1))
+-		writew(cpu_to_le16(d.x[0]), map->virt + adr);
++		flash_write16(d.x[0], map->virt + adr);
+ }
+ 
+ /*
+@@ -87,7 +141,7 @@
+  */
+ static void ixp4xx_write16(struct map_info *map, map_word d, unsigned long adr)
+ {
+-	writew(cpu_to_le16(d.x[0]), map->virt + adr);
++	flash_write16(d.x[0], map->virt + adr);
+ }
+ 
+ struct ixp4xx_flash_info {
diff --git a/packages/linux/nas100d-kernel/2.6.15/defconfig b/packages/linux/nas100d-kernel/2.6.15/defconfig
index 939a5d437e..f0d28ccd2b 100644
--- a/packages/linux/nas100d-kernel/2.6.15/defconfig
+++ b/packages/linux/nas100d-kernel/2.6.15/defconfig
@@ -966,7 +966,7 @@ CONFIG_I2C_DEBUG_CORE=n
 CONFIG_I2C_DEBUG_ALGO=n
 CONFIG_I2C_DEBUG_BUS=n
 CONFIG_I2C_DEBUG_CHIP=y
-CONFIG_RTC_PCF8563_I2C=m
+CONFIG_RTC_PCF8563_I2C=y
 
 #
 # Hardware Monitoring support