summaryrefslogtreecommitdiff
path: root/packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch
diff options
context:
space:
mode:
authorKoen Kooi <koen@openembedded.org>2007-09-10 03:35:48 +0000
committerKoen Kooi <koen@openembedded.org>2007-09-10 03:35:48 +0000
commit4dab2a3bd62003416bbc7557d42dd40d0fb81cfe (patch)
tree7ad4efd42e590f9c29c746e93f1a8beb954034f3 /packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch
parent92f78925abb02d4ba25c95a83c49172006c9cc5d (diff)
linux-ezx: update to svn r2050
Diffstat (limited to 'packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch')
-rw-r--r--packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch54
1 files changed, 23 insertions, 31 deletions
diff --git a/packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch b/packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch
index 35417344e0..afb5d9c005 100644
--- a/packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch
+++ b/packages/linux/linux-ezx-2.6.21/patches/a780-pcap.patch
@@ -1,7 +1,7 @@
Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c
===================================================================
---- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-06-28 22:44:12.000000000 -0300
-+++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-06-28 22:45:00.000000000 -0300
+--- linux-2.6.21.orig/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 22:33:03.000000000 -0300
++++ linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c 2007-08-31 23:01:17.000000000 -0300
@@ -20,6 +20,7 @@
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxafb.h>
@@ -10,7 +10,7 @@ Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c
#include "generic.h"
-@@ -49,7 +50,85 @@
+@@ -49,7 +50,77 @@
.pxafb_lcd_power = &ezx_lcd_power,
};
@@ -18,49 +18,41 @@ Index: linux-2.6.21/arch/arm/mach-pxa/ezx-a780.c
+static int __init a780_pcap_init(void)
+{
+ /* initialize PCAP registers */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1CTRL, 1);
-+// ezx_pcap_vibrator_level(PCAP_VIBRATOR_VOLTAGE_LEVEL3);
-+
+ /* set SW1 sleep to keep SW1 1.3v in sync mode */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE10, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE11, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE10, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE11, 0);
+
+ /* SW1 active in sync mode */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE00, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE01, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE00, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW1_MODE01, 0);
+
+ /* at SW1 -core voltage to 1.30V */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW10_DVS, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW11_DVS, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW12_DVS, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW13_DVS, 0);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW10_DVS, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW11_DVS, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW12_DVS, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_SW13_DVS, 0);
+
+ /* when STANDY2 PIN ACTIVE (high) set V3-- sram V8 -- pll off */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_LOWPWR, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_LOWPWR, 0);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V3_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V3_LOWPWR, 0);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V8_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V8_LOWPWR, 0);
+
+ /*
+ * when STANDY2 PIN ACTIVE (high) set V4-- lcd only for e680 V6 ---
+ * camera for e680
+ */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_LOWPWR, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_LOWPWR, 0);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V4_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V4_LOWPWR, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V6_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_VREG2_V6_LOWPWR, 0);
+
+ /* set Vc to low power mode when AP sleep */
-+// SSP_PCAP_bit_set( SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VC_STBY);
-+
-+ /* set VAUX2 to voltage 2.775V and low power mode when AP sleep */
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_1, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_0, 0);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_STBY, 1);
-+ ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_LOWPWR, 1);
-+// ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN, 1);
++// SSP_PCAP_bit_set(PCAP_BIT_LOWPWR_CTRL_VC_STBY);
+
-+// PGSR(GPIO34_TXENB) |= GPIO_bit(GPIO34_TXENB);
++ /* set VAUX2 to low power mode when AP sleep */
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_VAUX2_STBY, 1);
++ ezx_pcap_bit_set(PCAP_BIT_LOWPWR_VAUX2_LOWPWR, 1);
+
+ return 0;
+}