linux-2.6.26: cleanup backport of Freescale NAND controller

1 files changed, 0 insertions, 107 deletions

diff --git a/packages/linux/linux-2.6.26/boc01/003-081124-nand.patch b/packages/linux/linux-2.6.26/boc01/003-081124-nand.patch
deleted file mode 100644
index 885bad2715..0000000000
--- a/packages/linux/linux-2.6.26/boc01/003-081124-nand.patch
+++ /dev/null
@@ -1,107 +0,0 @@
-diff -Nru linux-2.6.26/drivers/mtd/nand/fsl_elbc_nand.c linux-2.6.26.modified/drivers/mtd/nand/fsl_elbc_nand.c
---- linux-2.6.26/drivers/mtd/nand/fsl_elbc_nand.c	2008-07-13 23:51:29.000000000 +0200
-+++ linux-2.6.26.modified/drivers/mtd/nand/fsl_elbc_nand.c	2008-10-24 13:43:30.000000000 +0200
-@@ -89,7 +89,7 @@
- 	.eccbytes = 3,
- 	.eccpos = {6, 7, 8},
- 	.oobfree = { {0, 5}, {9, 7} },
--	.oobavail = 12,
-+//	.oobavail = 12,
- };
- 
- /* Small Page FLASH with FMR[ECCM] = 1 */
-@@ -97,7 +97,7 @@
- 	.eccbytes = 3,
- 	.eccpos = {8, 9, 10},
- 	.oobfree = { {0, 5}, {6, 2}, {11, 5} },
--	.oobavail = 12,
-+	//.oobavail = 12,
- };
- 
- /* Large Page FLASH with FMR[ECCM] = 0 */
-@@ -105,7 +105,7 @@
- 	.eccbytes = 12,
- 	.eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
- 	.oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
--	.oobavail = 48,
-+	//.oobavail = 48,
- };
- 
- /* Large Page FLASH with FMR[ECCM] = 1 */
-@@ -113,7 +113,48 @@
- 	.eccbytes = 12,
- 	.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
- 	.oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
--	.oobavail = 48,
-+//	.oobavail = 48,
-+};
-+/*
-+ * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
-+ * 1, so we have to adjust bad block pattern. This pattern should be used for
-+ * x8 chips only. So far hardware does not support x16 chips anyway.
-+ */
-+static u8 scan_ff_pattern[] = { 0xff, };
-+
-+static struct nand_bbt_descr largepage_memorybased = {
-+	.options = 0,
-+	.offs = 0,
-+	.len = 1,
-+	.pattern = scan_ff_pattern,
-+};
-+
-+/*
-+ * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
-+ * interfere with ECC positions, that's why we implement our own descriptors.
-+ * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
-+ */
-+static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
-+static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
-+
-+static struct nand_bbt_descr bbt_main_descr = {
-+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
-+		   NAND_BBT_2BIT | NAND_BBT_VERSION,
-+	.offs =	11,
-+	.len = 4,
-+	.veroffs = 15,
-+	.maxblocks = 4,
-+	.pattern = bbt_pattern,
-+};
-+
-+static struct nand_bbt_descr bbt_mirror_descr = {
-+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
-+		   NAND_BBT_2BIT | NAND_BBT_VERSION,
-+	.offs =	11,
-+	.len = 4,
-+	.veroffs = 15,
-+	.maxblocks = 4,
-+	.pattern = mirror_pattern,
- };
- 
- /*=================================*/
-@@ -687,8 +728,9 @@
- 			chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
- 			                   &fsl_elbc_oob_lp_eccm1 :
- 			                   &fsl_elbc_oob_lp_eccm0;
--			mtd->ecclayout = chip->ecc.layout;
--			mtd->oobavail = chip->ecc.layout->oobavail;
-+			//mtd->ecclayout = chip->ecc.layout;
-+			//mtd->oobavail = chip->ecc.layout->oobavail;
-+			chip->badblock_pattern = &largepage_memorybased;
- 		}
- 	} else {
- 		dev_err(ctrl->dev,
-@@ -752,8 +794,12 @@
- 	chip->cmdfunc = fsl_elbc_cmdfunc;
- 	chip->waitfunc = fsl_elbc_wait;
- 
-+	chip->bbt_td = &bbt_main_descr;
-+	chip->bbt_md = &bbt_mirror_descr;
-+
- 	/* set up nand options */
--	chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
-+	//chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
-+	chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT;
- 
- 	chip->controller = &ctrl->controller;
- 	chip->priv = priv;
-