diff options
| author | Denys Dmytriyenko <denis@denix.org> | 2009-03-17 14:32:59 -0400 |
|---|---|---|
| committer | Denys Dmytriyenko <denis@denix.org> | 2009-03-17 14:32:59 -0400 |
| commit | 709c4d66e0b107ca606941b988bad717c0b45d9b (patch) | |
| tree | 37ee08b1eb308f3b2b6426d5793545c38396b838 /packages/linux/linux-2.6.23/mpc8313e-rdb | |
| parent | fa6cd5a3b993f16c27de4ff82b42684516d433ba (diff) | |
rename packages/ to recipes/ per earlier agreement
See links below for more details:
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21326
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21816
Signed-off-by: Denys Dmytriyenko <denis@denix.org>
Acked-by: Mike Westerhof <mwester@dls.net>
Acked-by: Philip Balister <philip@balister.org>
Acked-by: Khem Raj <raj.khem@gmail.com>
Acked-by: Marcin Juszkiewicz <hrw@openembedded.org>
Acked-by: Koen Kooi <koen@openembedded.org>
Acked-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
Diffstat (limited to 'packages/linux/linux-2.6.23/mpc8313e-rdb')
4 files changed, 0 insertions, 3919 deletions
diff --git a/packages/linux/linux-2.6.23/mpc8313e-rdb/defconfig b/packages/linux/linux-2.6.23/mpc8313e-rdb/defconfig deleted file mode 100644 index d842308fc9..0000000000 --- a/packages/linux/linux-2.6.23/mpc8313e-rdb/defconfig +++ /dev/null @@ -1,1870 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.23 -# Mon Dec 17 17:18:08 2007 -# -# CONFIG_PPC64 is not set - -# -# Processor support -# -CONFIG_6xx=y -# CONFIG_PPC_85xx is not set -# CONFIG_PPC_8xx is not set -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_E200 is not set -CONFIG_83xx=y -CONFIG_PPC_FPU=y -CONFIG_PPC_STD_MMU=y -CONFIG_PPC_STD_MMU_32=y -# CONFIG_PPC_MM_SLICES is not set -# CONFIG_SMP is not set -CONFIG_PPC32=y -CONFIG_PPC_MERGE=y -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_IRQ_PER_CPU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_ARCH_HAS_ILOG2_U32=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -# CONFIG_ARCH_NO_VIRT_TO_BUS is not set -CONFIG_PPC=y -CONFIG_EARLY_PRINTK=y -CONFIG_GENERIC_NVRAM=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_PPC_OF=y -CONFIG_OF=y -CONFIG_PPC_UDBG_16550=y -# CONFIG_GENERIC_TBSYNC is not set -CONFIG_AUDIT_ARCH=y -CONFIG_GENERIC_BUG=y -CONFIG_DEFAULT_UIMAGE=y -# CONFIG_PPC_DCR_NATIVE is not set -# CONFIG_PPC_DCR_MMIO is not set -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED=y -# CONFIG_RELAY is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -# CONFIG_KALLSYMS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_ANON_INODES=y -# CONFIG_EPOLL is not set -CONFIG_SIGNALFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set -# CONFIG_BLK_DEV_BSG is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Platform support -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_EMBEDDED6xx is not set -# CONFIG_PPC_82xx is not set -CONFIG_PPC_83xx=y -# CONFIG_PPC_86xx is not set -# CONFIG_PPC_MPC52xx is not set -# CONFIG_PPC_MPC5200 is not set -# CONFIG_PPC_CELL is not set -# CONFIG_PPC_CELL_NATIVE is not set -# CONFIG_PQ2ADS is not set -CONFIG_MPC8313_RDB=y -# CONFIG_MPC832x_MDS is not set -# CONFIG_MPC832x_RDB is not set -# CONFIG_MPC834x_MDS is not set -# CONFIG_MPC834x_ITX is not set -# CONFIG_MPC836x_MDS is not set -CONFIG_PPC_MPC831x=y -# CONFIG_MPIC is not set -# CONFIG_MPIC_WEIRD is not set -# CONFIG_PPC_I8259 is not set -# CONFIG_PPC_RTAS is not set -# CONFIG_MMIO_NVRAM is not set -# CONFIG_PPC_MPC106 is not set -# CONFIG_PPC_970_NAP is not set -# CONFIG_PPC_INDIRECT_IO is not set -# CONFIG_GENERIC_IOMAP is not set -# CONFIG_CPU_FREQ is not set -# CONFIG_CPM2 is not set -# CONFIG_FSL_ULI1575 is not set - -# -# Kernel options -# -# CONFIG_HIGHMEM is not set -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y -CONFIG_VIRT_TO_BUS=y -CONFIG_PROC_DEVICETREE=y -# CONFIG_CMDLINE_BOOL is not set -# CONFIG_PM is not set -CONFIG_SUSPEND_UP_POSSIBLE=y -CONFIG_HIBERNATION_UP_POSSIBLE=y -CONFIG_SECCOMP=y -CONFIG_WANT_DEVICE_TREE=y -CONFIG_DEVICE_TREE="" -CONFIG_ISA_DMA_API=y - -# -# Bus options -# -CONFIG_ZONE_DMA=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PPC_INDIRECT_PCI=y -CONFIG_FSL_SOC=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_SYSCALL=y -# CONFIG_PCIEPORTBUS is not set -CONFIG_ARCH_SUPPORTS_MSI=y -# CONFIG_PCI_MSI is not set - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set -# CONFIG_HOTPLUG_PCI is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00800000 - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_ASK_IP_FIB_HASH=y -# CONFIG_IP_FIB_TRIE is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -# CONFIG_NET_IPGRE_BROADCAST is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_TUNNEL=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_TUNNEL=m -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_BRIDGE_NETFILTER=y - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK_ENABLED=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -# CONFIG_NF_CONNTRACK_EVENTS is not set -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CT_PROTO_UDPLITE=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PROTO_GRE=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_TFTP=m -CONFIG_NF_NAT_AMANDA=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_NF_NAT_SIP=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# IPv6: Netfilter Configuration (EXPERIMENTAL) -# -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_OWNER=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_RAW=m - -# -# Bridge: Netfilter Configuration -# -# CONFIG_BRIDGE_NF_EBTABLES is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -# CONFIG_ATM_CLIP_NO_ICMP is not set -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -# CONFIG_ATM_BR2684_IPFILTER is not set -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=m -# CONFIG_DECNET is not set -CONFIG_LLC=m -CONFIG_LLC2=m -CONFIG_IPX=m -# CONFIG_IPX_INTERN is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -CONFIG_WAN_ROUTER=m - -# -# QoS and/or fair queueing -# -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_FIFO=y - -# -# Queueing/Scheduling -# -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RR=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_INGRESS=m - -# -# Classification -# -CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_STACK=32 -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=m -CONFIG_NET_ACT_GACT=m -CONFIG_GACT_PROB=y -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_IPT=m -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_SIMP=m -# CONFIG_NET_CLS_POLICE is not set -CONFIG_NET_CLS_IND=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -# CONFIG_BT_CMTP is not set -CONFIG_BT_HIDP=m - -# -# Bluetooth device drivers -# -CONFIG_BT_HCIUSB=m -CONFIG_BT_HCIUSB_SCO=y -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIVHCI=m -# CONFIG_AF_RXRPC is not set -CONFIG_FIB_RULES=y - -# -# Wireless -# -CONFIG_CFG80211=y -CONFIG_WIRELESS_EXT=y -CONFIG_MAC80211=m -# CONFIG_MAC80211_LEDS is not set -# CONFIG_MAC80211_DEBUG is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_RFKILL=m -CONFIG_RFKILL_INPUT=m -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CFI_AMDSTD=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0xfe000000 -CONFIG_MTD_PHYSMAP_LEN=0x0800000 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2 -# CONFIG_MTD_PHYSMAP_OF is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_CAFE is not set -CONFIG_MTD_NAND_FSL_ELBC=y -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ONENAND is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -CONFIG_OF_DEVICE=y -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=32768 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -# CONFIG_CDROM_PKTCDVD is not set -CONFIG_ATA_OVER_ETH=m -CONFIG_MISC_DEVICES=y -# CONFIG_PHANTOM is not set -CONFIG_EEPROM_93CX6=m -# CONFIG_SGI_IOC4 is not set -# CONFIG_TIFM_CORE is not set -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=m -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=m -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -CONFIG_SCSI_SPI_ATTRS=m -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_FIREWIRE is not set -# CONFIG_IEEE1394 is not set -# CONFIG_I2O is not set -# CONFIG_MACINTOSH_DRIVERS is not set -CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set -# CONFIG_IFB is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ARCNET is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -CONFIG_CICADA_PHY=y -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_NET_ETHERNET is not set -CONFIG_NETDEV_1000=y -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -CONFIG_GIANFAR=y -CONFIG_GFAR_NAPI=y -# CONFIG_QLA3XXX is not set -# CONFIG_ATL1 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_TR is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -CONFIG_IPW2100=m -CONFIG_IPW2100_MONITOR=y -# CONFIG_IPW2100_DEBUG is not set -CONFIG_IPW2200=m -CONFIG_IPW2200_MONITOR=y -CONFIG_IPW2200_RADIOTAP=y -CONFIG_IPW2200_PROMISCUOUS=y -CONFIG_IPW2200_QOS=y -# CONFIG_IPW2200_DEBUG is not set -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -# CONFIG_LIBERTAS_DEBUG is not set -CONFIG_AIRO=m -CONFIG_HERMES=m -CONFIG_PLX_HERMES=m -CONFIG_TMD_HERMES=m -CONFIG_NORTEL_HERMES=m -CONFIG_PCI_HERMES=m -CONFIG_ATMEL=m -CONFIG_PCI_ATMEL=m -CONFIG_PRISM54=m -CONFIG_USB_ZD1201=m -CONFIG_RTL8187=m -CONFIG_HOSTAP=m -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -CONFIG_HOSTAP_PLX=m -CONFIG_HOSTAP_PCI=m -CONFIG_BCM43XX=m -CONFIG_BCM43XX_DEBUG=y -CONFIG_BCM43XX_DMA=y -CONFIG_BCM43XX_PIO=y -CONFIG_BCM43XX_DMA_AND_PIO_MODE=y -# CONFIG_BCM43XX_DMA_MODE is not set -# CONFIG_BCM43XX_PIO_MODE is not set -CONFIG_ZD1211RW=m -# CONFIG_ZD1211RW_DEBUG is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET_MII is not set -# CONFIG_USB_USBNET is not set -# CONFIG_WAN is not set -CONFIG_ATM_DRIVERS=y -# CONFIG_ATM_DUMMY is not set -# CONFIG_ATM_TCP is not set -# CONFIG_ATM_LANAI is not set -# CONFIG_ATM_ENI is not set -# CONFIG_ATM_FIRESTREAM is not set -# CONFIG_ATM_ZATM is not set -# CONFIG_ATM_NICSTAR is not set -# CONFIG_ATM_IDT77252 is not set -# CONFIG_ATM_AMBASSADOR is not set -# CONFIG_ATM_HORIZON is not set -# CONFIG_ATM_IA is not set -# CONFIG_ATM_FORE200E_MAYBE is not set -# CONFIG_ATM_HE is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -CONFIG_PPPOATM=m -CONFIG_PPPOL2TP=m -# CONFIG_SLIP is not set -CONFIG_SLHC=m -# CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -CONFIG_ISDN=m -CONFIG_ISDN_I4L=m -# CONFIG_ISDN_PPP is not set -# CONFIG_ISDN_AUDIO is not set - -# -# ISDN feature submodules -# -CONFIG_ISDN_DRV_LOOP=m -CONFIG_ISDN_DIVERSION=m - -# -# ISDN4Linux hardware drivers -# - -# -# Passive cards -# -CONFIG_ISDN_DRV_HISAX=m - -# -# D-channel protocol features -# -CONFIG_HISAX_EURO=y -CONFIG_DE_AOC=y -# CONFIG_HISAX_NO_SENDCOMPLETE is not set -# CONFIG_HISAX_NO_LLC is not set -# CONFIG_HISAX_NO_KEYPAD is not set -CONFIG_HISAX_1TR6=y -CONFIG_HISAX_NI1=y -CONFIG_HISAX_MAX_CARDS=8 - -# -# HiSax supported cards -# -CONFIG_HISAX_16_3=y -CONFIG_HISAX_S0BOX=y -CONFIG_HISAX_FRITZPCI=y -CONFIG_HISAX_AVM_A1_PCMCIA=y -CONFIG_HISAX_ELSA=y -CONFIG_HISAX_DIEHLDIVA=y -CONFIG_HISAX_SEDLBAUER=y -CONFIG_HISAX_NICCY=y -CONFIG_HISAX_BKM_A4T=y -CONFIG_HISAX_SCT_QUADRO=y -CONFIG_HISAX_GAZEL=y -CONFIG_HISAX_W6692=y -CONFIG_HISAX_HFC_SX=y -# CONFIG_HISAX_DEBUG is not set - -# -# HiSax PCMCIA card service modules -# - -# -# HiSax sub driver modules -# -CONFIG_HISAX_ST5481=m -CONFIG_HISAX_HFCUSB=m -CONFIG_HISAX_HFC4S8S=m -CONFIG_HISAX_FRITZ_PCIPNP=m -CONFIG_HISAX_HDLC=y - -# -# Active cards -# -CONFIG_HYSDN=m -CONFIG_HYSDN_CAPI=y -CONFIG_ISDN_DRV_GIGASET=m -CONFIG_GIGASET_BASE=m -CONFIG_GIGASET_M105=m -CONFIG_GIGASET_M101=m -# CONFIG_GIGASET_DEBUG is not set -CONFIG_GIGASET_UNDOCREQ=y -CONFIG_ISDN_CAPI=m -CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y -CONFIG_CAPI_TRACE=y -# CONFIG_ISDN_CAPI_MIDDLEWARE is not set -CONFIG_ISDN_CAPI_CAPI20=m -# CONFIG_ISDN_CAPI_CAPIDRV is not set - -# -# CAPI hardware drivers -# -CONFIG_CAPI_AVM=y -CONFIG_ISDN_DRV_AVMB1_B1PCI=m -# CONFIG_ISDN_DRV_AVMB1_B1PCIV4 is not set -CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m -CONFIG_ISDN_DRV_AVMB1_T1PCI=m -CONFIG_ISDN_DRV_AVMB1_C4=m -CONFIG_CAPI_EICON=y -CONFIG_ISDN_DIVAS=m -CONFIG_ISDN_DIVAS_BRIPCI=y -CONFIG_ISDN_DIVAS_PRIPCI=y -CONFIG_ISDN_DIVAS_DIVACAPI=m -CONFIG_ISDN_DIVAS_USERIDI=m -CONFIG_ISDN_DIVAS_MAINT=m -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_UARTLITE is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -# CONFIG_SERIAL_OF_PLATFORM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_IPMI_HANDLER is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_83xx_WDT=y - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_HW_RANDOM=y -# CONFIG_NVRAM is not set -# CONFIG_GEN_RTC is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_DEVPORT=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y - -# -# I2C Algorithms -# -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set - -# -# I2C Hardware Bus support -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set -# CONFIG_I2C_PIIX4 is not set -CONFIG_I2C_MPC=y -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_TINY_USB is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set -# CONFIG_I2C_VOODOO3 is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_M41T00 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set - -# -# SPI support -# -CONFIG_SPI=y -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BITBANG=y -CONFIG_SPI_MPC83xx=y - -# -# SPI Protocol Masters -# -CONFIG_SPI_AT25=m -CONFIG_SPI_SPIDEV=m -CONFIG_SPI_TLE62X0=m -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ABITUGURU is not set -# CONFIG_SENSORS_ABITUGURU3 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -CONFIG_SENSORS_LM75=m -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_SM501 is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -CONFIG_DAB=y -# CONFIG_USB_DABUSB is not set - -# -# Graphics support -# -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_FB is not set -# CONFIG_FB_IBM_GXT4500 is not set - -# -# Sound -# -CONFIG_SOUND=m - -# -# Advanced Linux Sound Architecture -# -CONFIG_SND=m -CONFIG_SND_TIMER=m -CONFIG_SND_PCM=m -CONFIG_SND_HWDEP=m -CONFIG_SND_RAWMIDI=m -# CONFIG_SND_SEQUENCER is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_PCM_OSS_PLUGINS=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set - -# -# Generic devices -# -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set - -# -# PCI devices -# -# CONFIG_SND_AD1889 is not set -# CONFIG_SND_ALS300 is not set -# CONFIG_SND_ALS4000 is not set -# CONFIG_SND_ALI5451 is not set -# CONFIG_SND_ATIIXP is not set -# CONFIG_SND_ATIIXP_MODEM is not set -# CONFIG_SND_AU8810 is not set -# CONFIG_SND_AU8820 is not set -# CONFIG_SND_AU8830 is not set -# CONFIG_SND_AZT3328 is not set -# CONFIG_SND_BT87X is not set -# CONFIG_SND_CA0106 is not set -# CONFIG_SND_CMIPCI is not set -# CONFIG_SND_CS4281 is not set -# CONFIG_SND_CS46XX is not set -# CONFIG_SND_CS5530 is not set -# CONFIG_SND_DARLA20 is not set -# CONFIG_SND_GINA20 is not set -# CONFIG_SND_LAYLA20 is not set -# CONFIG_SND_DARLA24 is not set -# CONFIG_SND_GINA24 is not set -# CONFIG_SND_LAYLA24 is not set -# CONFIG_SND_MONA is not set -# CONFIG_SND_MIA is not set -# CONFIG_SND_ECHO3G is not set -# CONFIG_SND_INDIGO is not set -# CONFIG_SND_INDIGOIO is not set -# CONFIG_SND_INDIGODJ is not set -# CONFIG_SND_EMU10K1 is not set -# CONFIG_SND_EMU10K1X is not set -# CONFIG_SND_ENS1370 is not set -# CONFIG_SND_ENS1371 is not set -# CONFIG_SND_ES1938 is not set -# CONFIG_SND_ES1968 is not set -# CONFIG_SND_FM801 is not set -# CONFIG_SND_HDA_INTEL is not set -# CONFIG_SND_HDSP is not set -# CONFIG_SND_HDSPM is not set -# CONFIG_SND_ICE1712 is not set -# CONFIG_SND_ICE1724 is not set -# CONFIG_SND_INTEL8X0 is not set -# CONFIG_SND_INTEL8X0M is not set -# CONFIG_SND_KORG1212 is not set -# CONFIG_SND_MAESTRO3 is not set -# CONFIG_SND_MIXART is not set -# CONFIG_SND_NM256 is not set -# CONFIG_SND_PCXHR is not set -# CONFIG_SND_RIPTIDE is not set -# CONFIG_SND_RME32 is not set -# CONFIG_SND_RME96 is not set -# CONFIG_SND_RME9652 is not set -# CONFIG_SND_SONICVIBES is not set -# CONFIG_SND_TRIDENT is not set -# CONFIG_SND_VIA82XX is not set -# CONFIG_SND_VIA82XX_MODEM is not set -# CONFIG_SND_VX222 is not set -# CONFIG_SND_YMFPCI is not set - -# -# ALSA PowerMac devices -# - -# -# ALSA PowerPC devices -# - -# -# USB devices -# -CONFIG_SND_USB_AUDIO=m -# CONFIG_SND_USB_USX2Y is not set -# CONFIG_SND_USB_CAIAQ is not set - -# -# System on Chip audio support -# -# CONFIG_SND_SOC is not set - -# -# SoC Audio support for SuperH -# - -# -# Open Sound System -# -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set - -# -# USB Input Devices -# -# CONFIG_USB_HID is not set - -# -# USB HID Boot Protocol drivers -# -# CONFIG_USB_KBD is not set -# CONFIG_USB_MOUSE is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set - -# -# USB Host Controller Drivers -# -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_SPLIT_ISO=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -# CONFIG_USB_EHCI_TT_NEWSCHED is not set -CONFIG_USB_EHCI_FSL=y -# CONFIG_USB_ISP116X_HCD is not set -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PPC_OF=y -CONFIG_USB_OHCI_HCD_PPC_OF_BE=y -# CONFIG_USB_OHCI_HCD_PPC_OF_LE is not set -CONFIG_USB_OHCI_HCD_PCI=y -CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y -CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_UHCI_HCD=y -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# may also be needed; see USB_STORAGE Help for more information -# -CONFIG_USB_STORAGE=m -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -CONFIG_USB_MON=y - -# -# USB port drivers -# - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGET is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set - -# -# USB DSL modem support -# -# CONFIG_USB_ATM is not set - -# -# USB Gadget Support -# -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -CONFIG_USB_GADGET_NET2280=y -CONFIG_USB_NET2280=y -# CONFIG_USB_GADGET_PXA2XX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -CONFIG_USB_ETH=y -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -CONFIG_MMC=m -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD Card Drivers -# -CONFIG_MMC_BLOCK=m -CONFIG_MMC_BLOCK_BOUNCE=y - -# -# MMC/SD Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_WBSD is not set -# CONFIG_MMC_TIFM_SD is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y - -# -# LED drivers -# -CONFIG_LEDS_MPC8313E_RDB=y - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_CPU_ACTIVITY=m -# CONFIG_INFINIBAND is not set -# CONFIG_EDAC is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -CONFIG_RTC_INTF_DEV_UIE_EMUL=y -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_DRV_DS1307=y -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_MAX6902 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# - -# -# DMA Engine support -# -CONFIG_DMA_ENGINE=y - -# -# DMA Clients -# -CONFIG_NET_DMA=y - -# -# DMA Devices -# -CONFIG_INTEL_IOATDMA=y - -# -# Userspace I/O -# -CONFIG_UIO=m -CONFIG_UIO_CIF=m - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -CONFIG_AUTOFS4_FS=y -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -CONFIG_NTFS_FS=m -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -CONFIG_CRAMFS=y -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=m -# CONFIG_NFSD_V3 is not set -CONFIG_NFSD_TCP=y -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=m -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_BIND34 is not set -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=m -# CONFIG_SMB_NLS_DEFAULT is not set -CONFIG_CIFS=m -# CONFIG_CIFS_STATS is not set -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_XATTR is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_EXPERIMENTAL is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -CONFIG_LDM_PARTITION=y -# CONFIG_LDM_DEBUG is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set - -# -# Native Language Support -# -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -CONFIG_NLS_CODEPAGE_932=y -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -CONFIG_NLS_ISO8859_8=y -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Distributed Lock Manager -# -# CONFIG_DLM is not set -# CONFIG_UCC_SLOW is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_CRC_CCITT=m -CONFIG_CRC16=m -CONFIG_CRC_ITU_T=m -CONFIG_CRC32=y -CONFIG_CRC7=m -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y - -# -# Instrumentation Support -# -CONFIG_PROFILING=y -CONFIG_OPROFILE=m - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_PPC_EARLY_DEBUG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ABLKCIPHER=m -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_HASH=m -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_HW=y diff --git a/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc8313e-rdb-leds.patch b/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc8313e-rdb-leds.patch deleted file mode 100644 index 1116ce3998..0000000000 --- a/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc8313e-rdb-leds.patch +++ /dev/null @@ -1,202 +0,0 @@ -diff -urN linux-2.6.23.orig/drivers/leds/Kconfig linux-2.6.23/drivers/leds/Kconfig ---- linux-2.6.23.orig/drivers/leds/Kconfig 2007-10-09 22:31:38.000000000 +0200 -+++ linux-2.6.23/drivers/leds/Kconfig 2007-12-14 15:32:37.000000000 +0100 -@@ -101,6 +101,12 @@ - outputs. To be useful the particular board must have LEDs - and they must be connected to the GPIO lines. - -+config LEDS_MPC8313E_RDB -+ tristate "LED Support for MPC8313E-RDB LEDs" -+ depends on LEDS_CLASS && PPC_83xx -+ help -+ This option enables support for the LEDs on MPC8313E-RDB board. -+ - comment "LED Triggers" - - config LEDS_TRIGGERS -diff -urN linux-2.6.23.orig/drivers/leds/leds-mpc8313e-rdb.c linux-2.6.23/drivers/leds/leds-mpc8313e-rdb.c ---- linux-2.6.23.orig/drivers/leds/leds-mpc8313e-rdb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.23/drivers/leds/leds-mpc8313e-rdb.c 2007-12-14 15:32:55.000000000 +0100 -@@ -0,0 +1,171 @@ -+/* -+ * drivers/leds/leds-mpc8313e-rdb.c -+ * Copyright (C) 2007 Jeremy Laine <jeremy.laine@bolloretelecom.eu> -+ * Copyright (C) 2007 Leon Woestenberg <leon@sidebranch.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive for -+ * more details. -+ * -+ * MPC8313E-RDB LEDs driver -+ * -+ */ -+ -+#include <linux/module.h> -+#include <linux/platform_device.h> -+#include <linux/ioport.h> -+#include <linux/leds.h> -+#include <linux/err.h> -+#include <asm/io.h> -+ -+#define LEDS_BASE 0xfa000000 -+#define LEDS_SIZE 0x2 -+ -+static struct platform_device *leds_pdev = NULL; -+static struct resource *led_mem = NULL; -+static void *led_io = NULL; -+static u8 led_state = 0xff; -+ -+struct mpc8313_led { -+ struct led_classdev cdev; -+ u8 bitmask; -+}; -+ -+static void mpc8313leds_set(struct led_classdev *led_cdev, enum led_brightness value) -+{ -+ struct mpc8313_led *led_dev = container_of(led_cdev, struct mpc8313_led, cdev); -+ if (value) -+ led_state &= ~led_dev->bitmask; -+ else -+ led_state |= led_dev->bitmask; -+ iowrite8(led_state, led_io); -+} -+ -+static struct mpc8313_led mpc8313_leds[] = { -+ { -+ .cdev = { -+ .name = "mpc8313:led0", -+ .brightness_set = mpc8313leds_set, -+ }, -+ .bitmask = 1, -+ }, -+ { -+ .cdev = { -+ .name = "mpc8313:led1", -+ .brightness_set = mpc8313leds_set, -+ }, -+ .bitmask = 2, -+ }, -+ { -+ .cdev = { -+ .name = "mpc8313:led2", -+ .brightness_set = mpc8313leds_set, -+ }, -+ .bitmask = 4, -+ }, -+ { -+ .cdev = { -+ .name = "mpc8313:led3", -+ .brightness_set = mpc8313leds_set, -+ }, -+ .bitmask = 8, -+ }, -+ { -+ .cdev = { -+ .name = "mpc8313:led4", -+ .brightness_set = mpc8313leds_set, -+ }, -+ .bitmask = 16, -+ }, -+ { -+ .cdev = { -+ .name = "mpc8313:led5", -+ .brightness_set = mpc8313leds_set, -+ }, -+ .bitmask = 32, -+ }, -+ { -+ .cdev = { -+ .name = "mpc8313:led6", -+ .brightness_set = mpc8313leds_set, -+ }, -+ .bitmask = 64, -+ }, -+ { -+ .cdev = { -+ .name = "mpc8313:led7", -+ .brightness_set = mpc8313leds_set, -+ }, -+ .bitmask = 128, -+ }, -+}; -+ -+static int mpc8313leds_probe(struct platform_device *pdev) -+{ -+ int i; -+ int ret; -+ -+ for (i = ret = 0; ret >= 0 && i < ARRAY_SIZE(mpc8313_leds); i++) { -+ ret = led_classdev_register(&pdev->dev, -+ &mpc8313_leds[i].cdev); -+ } -+ -+ if (ret < 0 && i > 1) { -+ for (i = i - 2; i >= 0; i--) -+ led_classdev_unregister(&mpc8313_leds[i].cdev); -+ } -+ -+ return ret; -+} -+ -+static int mpc8313leds_remove(struct platform_device *pdev) -+{ -+ int i; -+ -+ for (i = ARRAY_SIZE(mpc8313_leds) - 1; i >= 0; i--) -+ led_classdev_unregister(&mpc8313_leds[i].cdev); -+ -+ return 0; -+} -+ -+static struct platform_driver mpc8313leds_driver = { -+ .driver = { -+ .name = "mpc8313-leds", -+ .owner = THIS_MODULE, -+ }, -+ .probe = mpc8313leds_probe, -+ .remove = mpc8313leds_remove, -+}; -+ -+static int __init mpc8313leds_init(void) -+{ -+ if (!(led_mem = request_mem_region(LEDS_BASE, LEDS_SIZE, "mpc8313-leds"))) -+ return -ENOMEM; -+ if (!(led_io = ioremap(LEDS_BASE, LEDS_SIZE))) -+ { -+ release_mem_region(LEDS_BASE, LEDS_SIZE); -+ led_mem = NULL; -+ return -ENOMEM; -+ } -+ iowrite8(led_state, led_io); -+ -+ leds_pdev = platform_device_register_simple("mpc8313-leds", -1, NULL, 0); -+ -+ return platform_driver_register(&mpc8313leds_driver); -+} -+ -+static void __exit mpc8313leds_exit(void) -+{ -+ if (led_mem) release_mem_region(LEDS_BASE, LEDS_SIZE); -+ led_mem = NULL; -+ platform_driver_unregister(&mpc8313leds_driver); -+ -+ platform_device_unregister(leds_pdev); -+} -+ -+module_init(mpc8313leds_init); -+module_exit(mpc8313leds_exit); -+ -+MODULE_AUTHOR("Jeremy Laine <jeremy.laine@bolloretelecom.eu>"); -+MODULE_DESCRIPTION("MPC8313E-RDB LED driver"); -+MODULE_LICENSE("GPL"); -diff -urN linux-2.6.23.orig/drivers/leds/Makefile linux-2.6.23/drivers/leds/Makefile ---- linux-2.6.23.orig/drivers/leds/Makefile 2007-10-09 22:31:38.000000000 +0200 -+++ linux-2.6.23/drivers/leds/Makefile 2007-12-14 15:32:37.000000000 +0100 -@@ -17,6 +17,7 @@ - obj-$(CONFIG_LEDS_H1940) += leds-h1940.o - obj-$(CONFIG_LEDS_COBALT) += leds-cobalt.o - obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o -+obj-$(CONFIG_LEDS_MPC8313E_RDB) += leds-mpc8313e-rdb.o - - # LED Triggers - obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o diff --git a/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc8313e-rdb-rtc.patch b/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc8313e-rdb-rtc.patch deleted file mode 100644 index 4177a3d4a9..0000000000 --- a/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc8313e-rdb-rtc.patch +++ /dev/null @@ -1,40 +0,0 @@ -diff -urN linux-2.6.23.orig/arch/powerpc/boot/dts/mpc8313erdb.dts linux-2.6.23/arch/powerpc/boot/dts/mpc8313erdb.dts ---- linux-2.6.23.orig/arch/powerpc/boot/dts/mpc8313erdb.dts 2007-10-09 22:31:38.000000000 +0200 -+++ linux-2.6.23/arch/powerpc/boot/dts/mpc8313erdb.dts 2007-12-01 13:16:55.000000000 +0100 -@@ -54,12 +54,20 @@ - }; - - i2c@3000 { -+ #address-cells = <1>; -+ #size-cells = <0>; - device_type = "i2c"; - compatible = "fsl-i2c"; - reg = <3000 100>; - interrupts = <e 8>; - interrupt-parent = < &ipic >; - dfsrr; -+ -+ rtc@68 { -+ device_type = "rtc"; -+ compatible = "dallas,ds1339"; -+ reg = <68>; -+ }; - }; - - i2c@3100 { -diff -urN linux-2.6.23.orig/arch/powerpc/sysdev/fsl_soc.c linux-2.6.23/arch/powerpc/sysdev/fsl_soc.c ---- linux-2.6.23.orig/arch/powerpc/sysdev/fsl_soc.c 2007-10-09 22:31:38.000000000 +0200 -+++ linux-2.6.23/arch/powerpc/sysdev/fsl_soc.c 2007-12-01 13:08:30.000000000 +0100 -@@ -319,6 +319,12 @@ - {"ricoh,rs5c372b", "rtc-rs5c372", "rs5c372b",}, - {"ricoh,rv5c386", "rtc-rs5c372", "rv5c386",}, - {"ricoh,rv5c387a", "rtc-rs5c372", "rv5c387a",}, -+ {"dallas,ds1307", "rtc-ds1307", "ds1307",}, -+ {"dallas,ds1337", "rtc-ds1307", "ds1337",}, -+ {"dallas,ds1338", "rtc-ds1307", "ds1338",}, -+ {"dallas,ds1339", "rtc-ds1307", "ds1339",}, -+ {"dallas,ds1340", "rtc-ds1307", "ds1340",}, -+ {"stm,m41t00", "rtc-ds1307", "m41t00"}, - }; - - static int __init of_find_i2c_driver(struct device_node *node, struct i2c_board_info *info) diff --git a/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc831x-nand.patch b/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc831x-nand.patch deleted file mode 100644 index efff29bca1..0000000000 --- a/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc831x-nand.patch +++ /dev/null @@ -1,1807 +0,0 @@ -diff -urN linux-2.6.23.orig/arch/powerpc/boot/dts/mpc8313erdb.dts linux-2.6.23/arch/powerpc/boot/dts/mpc8313erdb.dts ---- linux-2.6.23.orig/arch/powerpc/boot/dts/mpc8313erdb.dts 2007-10-09 22:31:38.000000000 +0200 -+++ linux-2.6.23/arch/powerpc/boot/dts/mpc8313erdb.dts 2007-11-28 20:36:57.000000000 +0100 -@@ -37,6 +37,12 @@ - device_type = "memory"; - reg = <00000000 08000000>; // 128MB at 0 - }; -+ -+ nand0 { -+ device_type = "nand"; -+ compatible = "fsl-nand"; -+ reg = <e2800000 00000200>; -+ }; - - soc8313@e0000000 { - #address-cells = <1>; -@@ -210,5 +216,15 @@ - built-in; - device_type = "ipic"; - }; -+ -+ elbc@5000 { -+ device_type = "elbc"; -+ compatible = "fsl-elbc"; -+ reg = <5000 1000>; -+ interrupts = <4d 8>; -+ interrupt-parent = < &ipic >; -+ allow-direct-device-sleep; -+ }; -+ - }; - }; -diff -urN linux-2.6.23.orig/arch/powerpc/sysdev/fsl_soc.c linux-2.6.23/arch/powerpc/sysdev/fsl_soc.c ---- linux-2.6.23.orig/arch/powerpc/sysdev/fsl_soc.c 2007-10-09 22:31:38.000000000 +0200 -+++ linux-2.6.23/arch/powerpc/sysdev/fsl_soc.c 2007-11-28 20:36:39.000000000 +0100 -@@ -6,6 +6,12 @@ - * 2006 (c) MontaVista Software, Inc. - * Vitaly Bordug <vbordug@ru.mvista.com> - * -+ * Change log: -+ * Copyright (C) 2006 Freescale Semiconductor, Inc. -+ * 2006: Lo Wilson (r43300@freescale.com) -+ * Added support for Enhanced Local Bus Controller -+ * Added support for USB UTMI mode on-chip PHY -+ * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your -@@ -27,6 +33,8 @@ - #include <linux/fsl_devices.h> - #include <linux/fs_enet_pd.h> - #include <linux/fs_uart_pd.h> -+#include <linux/mtd/nand.h> -+#include <linux/mtd/fsl_elbc.h> - - #include <asm/system.h> - #include <asm/atomic.h> -@@ -648,6 +656,75 @@ - - arch_initcall(fsl_usb_of_init); - -+static int __init fsl_elbc_of_init(void) -+{ -+ struct device_node *np; -+ unsigned int i; -+ struct platform_device *elbc_dev = NULL; -+ struct platform_device *nand_dev = NULL; -+ int ret; -+ -+ /* find and register the enhanced local bus controller */ -+ for (np = NULL, i = 0; -+ (np = of_find_compatible_node(np, "elbc", "fsl-elbc")) != NULL; -+ i++) { -+ struct resource r[2]; -+ -+ memset(&r, 0, sizeof(r)); -+ -+ ret = of_address_to_resource(np, 0, &r[0]); -+ if (ret) -+ goto err; -+ -+ r[1].start = r[1].end = irq_of_parse_and_map(np, 0); -+ r[1].flags = IORESOURCE_IRQ; -+ -+ elbc_dev = -+ platform_device_register_simple("fsl-elbc", i, r, 2); -+ if (IS_ERR(elbc_dev)) { -+ ret = PTR_ERR(elbc_dev); -+ goto err; -+ } -+ } -+ -+ /* find and register NAND memories if the eLBC was found */ -+ for (np = NULL, i = 0; -+ elbc_dev && -+ (np = of_find_compatible_node(np, "nand", "fsl-nand")) != NULL; -+ i++) { -+ struct resource r; -+ struct platform_fsl_nand_chip chip_data; -+ -+ memset(&r, 0, sizeof(r)); -+ memset(&chip_data, 0, sizeof(chip_data)); -+ -+ ret = of_address_to_resource(np, 0, &r); -+ if (ret) -+ goto err; -+ -+ nand_dev = -+ platform_device_register_simple("fsl-nand", i, &r, 1); -+ if (IS_ERR(nand_dev)) { -+ ret = PTR_ERR(nand_dev); -+ goto err; -+ } -+ -+ chip_data.name = get_property(np, "name", NULL); -+ chip_data.partitions_str = get_property(np, "partitions", NULL); -+ -+ ret = platform_device_add_data(nand_dev, &chip_data, -+ sizeof(struct platform_fsl_nand_chip)); -+ if (ret) -+ goto err; -+ } -+ return 0; -+ -+err: -+ return ret; -+} -+ -+arch_initcall(fsl_elbc_of_init); -+ - #ifdef CONFIG_CPM2 - - extern void init_scc_ioports(struct fs_uart_platform_info*); -diff -urN linux-2.6.23.orig/drivers/mtd/nand/fsl_elbc.c linux-2.6.23/drivers/mtd/nand/fsl_elbc.c ---- linux-2.6.23.orig/drivers/mtd/nand/fsl_elbc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.23/drivers/mtd/nand/fsl_elbc.c 2007-11-28 20:36:39.000000000 +0100 -@@ -0,0 +1,1325 @@ -+/* linux/drivers/mtd/nand/fsl_elbc.c -+ * -+ * Copyright (C) 2006 Freescale Semiconductor, Inc. -+ * -+ * Freescale Enhanced Local Bus Controller NAND driver -+ * -+ * Author: Nick Spence <Nick.Spence@freescale.com> -+ * Maintainer: Tony Li <Tony.Li@freescale.com> -+ * -+ * Changelog: -+ * 2006-12 Tony Li <Tony.Li@freescale.com> -+ * Adopt to MPC8313ERDB board -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+*/ -+ -+//#ifdef CONFIG_MTD_NAND_DEBUG -+//#define DEBUG -+//#endif -+//#define DEBUG -+ -+#include <linux/module.h> -+#include <linux/types.h> -+#include <linux/init.h> -+#include <linux/kernel.h> -+#include <linux/string.h> -+#include <linux/ioport.h> -+#include <linux/platform_device.h> -+#include <linux/delay.h> -+#include <linux/err.h> -+#include <linux/slab.h> -+#include <linux/interrupt.h> -+#include <linux/device.h> -+#include <linux/fsl_devices.h> -+ -+#include <linux/mtd/mtd.h> -+#include <linux/mtd/nand.h> -+#include <linux/mtd/nand_ecc.h> -+#include <linux/mtd/partitions.h> -+ -+#include <asm/io.h> -+#include <asm/mpc83xx.h> -+#include <linux/mtd/fsl_elbc.h> -+ -+#define PFX "fsl-elbc: " -+ -+#undef CFG_FCM_DEBUG -+#define CFG_FCM_DEBUG_LVL 3 -+#ifdef CFG_FCM_DEBUG -+static int fcm_debug_level = CFG_FCM_DEBUG_LVL; -+#define FCM_DEBUG(n, args...) \ -+ do { \ -+ if (n <= fcm_debug_level) \ -+ printk(args); \ -+ } while(0) -+#else /* CONFIG_FCM_DEBUG */ -+#define FCM_DEBUG(n, args...) do { } while(0) -+#endif -+ -+#define FCM_SIZE (8 * 1024) -+ -+#define MAX_BANKS (8) -+ -+/* use interrupt instead of busy waiting TODO */ -+#define FCM_USE_INTERRUPT -+ -+#define MIN(x, y) ((x < y) ? x : y) -+ -+#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ -+ -+#define FCM_TIMEOUT_MSECS 100 /* Maximum number of mSecs to wait for FCM */ -+ -+ -+ -+struct fsl_elbc_ctrl; -+ -+/* mtd information per set */ -+ -+struct fsl_elbc_mtd { -+ struct mtd_info mtd; -+ struct nand_chip chip; -+ struct platform_fsl_nand_chip pl_chip; -+ struct fsl_elbc_ctrl *ctrl; -+ -+ struct device *device; -+// int nr_chips; /* Number of chips in set */ -+// int nr_partitions; /* Number of partitions or 0 */ -+ char *name; /* Name of set (optional) */ -+ int *nr_map; /* Physical chip num (option)*/ -+// struct mtd_partition *partitions; /* MTD partition list (option*/ -+// struct nand_ecclayout *ecclayout; -+ unsigned int options; -+ struct resource *area; -+ int bank; /* Chip select bank number */ -+ unsigned int pbase; /* Chip select base physical address */ -+ unsigned int vbase; /* Chip select base virtual address */ -+ int pgs; /* NAND page size (0=512, 1=2048) */ -+ unsigned int fmr; /* FCM Flash Mode Register value */ -+}; -+ -+/* overview of the fsl elbc controller */ -+ -+struct fsl_elbc_ctrl { -+ struct nand_hw_control controller; -+ struct fsl_elbc_mtd *nmtd[MAX_BANKS]; -+ -+ /* device info */ -+ atomic_t childs_active; -+ struct device *device; -+ struct resource *area; -+ lbus83xx_t *regs; -+ int irq; -+ wait_queue_head_t irq_wait; -+ unsigned int irq_status; /* status read from LTESR by irq handler */ -+ u_char *addr; /* Address of assigned FCM buffer */ -+ unsigned int page; /* Last page written to / read from */ -+ unsigned int read_bytes; /* Number of bytes read during command */ -+ unsigned int index; /* Pointer to next byte to 'read' */ -+ unsigned int status; /* status read from LTESR after last op */ -+ int oobbuf; /* Pointer to OOB block */ -+ unsigned int mdr; /* UPM/FCM Data Register value */ -+ unsigned int use_mdr; /* Non zero if the MDR is to be set */ -+}; -+ -+struct fsl_elbc_ctrl elbc_ctrl; -+ -+/* These map to the positions used by the FCM hardware ECC generator */ -+ -+/* Small Page FLASH with FMR[ECCM] = 0 */ -+static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { /* TODO */ -+//TODO .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ -+ .eccbytes = 3, -+ .eccpos = {6, 7, 8}, -+ .oobfree = { {0, 5}, {9, 7} } -+}; -+ -+/* Small Page FLASH with FMR[ECCM] = 1 */ -+static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { /* TODO */ -+//TODO .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ -+ .eccbytes = 3, -+ .eccpos = {8, 9, 10}, -+ .oobfree = { {0, 5}, {6, 2}, {11, 5} } -+}; -+ -+/* Large Page FLASH with FMR[ECCM] = 0 */ -+static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = { -+//TODO .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ -+ .eccbytes = 12, -+ .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, -+ .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} } -+}; -+ -+/* Large Page FLASH with FMR[ECCM] = 1 */ -+static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { -+//TODO .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ -+ .eccbytes = 12, -+ .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, -+ .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} } -+}; -+ -+/*=================================*/ -+ -+/* -+ * Set up the FCM hardware block and page address fields, and the fcm -+ * structure addr field to point to the correct FCM buffer in memory -+ */ -+static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) -+{ -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_mtd *nmtd = chip->priv; -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ volatile lbus83xx_t *lbc = ctrl->regs; -+ int buf_num; -+ -+ ctrl->page = page_addr; -+ -+ lbc->fbar = page_addr >> (chip->phys_erase_shift - chip->page_shift); -+ if (nmtd->pgs) { -+ lbc->fpar = ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | -+ ( oob ? FPAR_LP_MS : 0) | -+ column; -+ buf_num = (page_addr & 1) << 2; -+ } else { -+ lbc->fpar = ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | -+ ( oob ? FPAR_SP_MS : 0) | -+ column; -+ buf_num = page_addr & 7; -+ } -+ ctrl->addr = (unsigned char*)(nmtd->vbase + (buf_num * 1024)); -+ -+ /* for OOB data point to the second half of the buffer */ -+ if (oob) { -+ ctrl->addr += (nmtd->pgs ? 2048 : 512); -+ } -+ FCM_DEBUG(2,"set_addr: bank=%d, ctrl->addr=0x%p (0x%08x)\n", buf_num, ctrl->addr, nmtd->vbase); -+} -+ -+/* -+ * execute FCM command and wait for it to complete -+ */ -+static int fsl_elbc_run_command(struct mtd_info *mtd) -+{ -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_mtd *nmtd = chip->priv; -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ volatile lbus83xx_t *lbc = ctrl->regs; -+ /* Setup the FMR[OP] to execute without write protection */ -+ lbc->fmr = nmtd->fmr | 3; -+ if (ctrl->use_mdr) -+ lbc->mdr = ctrl->mdr; -+ -+ FCM_DEBUG(5,"fsl_elbc_run_command: fmr= %08X fir= %08X fcr= %08X\n", -+ lbc->fmr, lbc->fir, lbc->fcr); -+ FCM_DEBUG(5,"fsl_elbc_run_command: fbar=%08X fpar=%08X fbcr=%08X bank=%d\n", -+ lbc->fbar, lbc->fpar, lbc->fbcr, nmtd->bank); -+ -+ /* clear event registers */ -+ lbc->lteatr = 0; -+ lbc->ltesr |= (LTESR_FCT | LTESR_PAR | LTESR_CC); -+ -+ /* execute special operation */ -+ lbc->lsor = nmtd->bank; -+ -+ /* wait for FCM complete flag or timeout */ -+/* TODO */ -+#ifdef FCM_USE_INTERRUPT -+ ctrl->status = ctrl->irq_status = 0; -+ wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, FCM_TIMEOUT_MSECS * HZ/1000); -+ ctrl->status = ctrl->irq_status; -+#else -+ { -+ unsigned long timeout; -+ unsigned long now; -+ now = jiffies_to_msecs(jiffies); -+ timeout = now + FCM_TIMEOUT_MSECS; -+ while (time_before(now, timeout)) { -+ ctrl->status = lbc->ltesr & (LTESR_FCT | LTESR_PAR | LTESR_CC); -+ if (ctrl->status) -+ break; -+ now = jiffies_to_msecs(jiffies); -+ } -+ } -+#endif -+ -+ /* store mdr value in case it was needed */ -+ if (ctrl->use_mdr) -+ ctrl->mdr = lbc->mdr; -+ -+ ctrl->use_mdr = 0; -+ -+ FCM_DEBUG(5,"fsl_elbc_run_command: stat=%08X mdr= %08X fmr= %08X\n", -+ ctrl->status, ctrl->mdr, lbc->fmr); -+ -+ /* returns 0 on success otherwise non-zero) */ -+ return (ctrl->status == LTESR_CC ? 0 : EFAULT); -+} -+ -+/* cmdfunc send commands to the FCM */ -+static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned command, -+ int column, int page_addr) -+{ -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_mtd *nmtd = chip->priv; -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ volatile lbus83xx_t *lbc = ctrl->regs; -+ -+ ctrl->use_mdr = 0; -+ -+ /* clear the read buffer */ -+ ctrl->read_bytes = 0; -+ if (command != NAND_CMD_PAGEPROG) { -+ ctrl->index = 0; -+ ctrl->oobbuf = -1; -+ } -+ -+ switch (command) { -+ /* READ0 and READ1 read the entire buffer to use hardware ECC */ -+ case NAND_CMD_READ1: -+ FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_READ1, page_addr:" -+ " 0x%x, column: 0x%x.\n", page_addr, column); -+ ctrl->index = column + 256; -+ goto read0; -+ case NAND_CMD_READ0: -+ FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" -+ " 0x%x, column: 0x%x.\n", page_addr, column); -+ ctrl->index = column; -+read0: -+ if (nmtd->pgs) { -+ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | -+ (FIR_OP_CA << FIR_OP1_SHIFT) | -+ (FIR_OP_PA << FIR_OP2_SHIFT) | -+ (FIR_OP_CW1 << FIR_OP3_SHIFT) | -+ (FIR_OP_RBW << FIR_OP4_SHIFT); -+ } else { -+ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | -+ (FIR_OP_CA << FIR_OP1_SHIFT) | -+ (FIR_OP_PA << FIR_OP2_SHIFT) | -+ (FIR_OP_RBW << FIR_OP3_SHIFT); -+ } -+ lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | -+ (NAND_CMD_READSTART << FCR_CMD1_SHIFT); -+ lbc->fbcr = 0; /* read entire page to enable ECC */ -+ set_addr(mtd, 0, page_addr, 0); -+ ctrl->read_bytes = mtd->writesize + mtd->oobsize; -+ goto write_cmd2; -+ /* READOOB read only the OOB becasue no ECC is performed */ -+ case NAND_CMD_READOOB: -+ FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" -+ " 0x%x, column: 0x%x.\n", page_addr, column); -+ if (nmtd->pgs) { -+ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | -+ (FIR_OP_CA << FIR_OP1_SHIFT) | -+ (FIR_OP_PA << FIR_OP2_SHIFT) | -+ (FIR_OP_CW1 << FIR_OP3_SHIFT) | -+ (FIR_OP_RBW << FIR_OP4_SHIFT); -+ lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | -+ (NAND_CMD_READSTART << FCR_CMD1_SHIFT); -+ } else { -+ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | -+ (FIR_OP_CA << FIR_OP1_SHIFT) | -+ (FIR_OP_PA << FIR_OP2_SHIFT) | -+ (FIR_OP_RBW << FIR_OP3_SHIFT); -+ lbc->fcr = (NAND_CMD_READOOB << FCR_CMD0_SHIFT); -+ } -+ lbc->fbcr = mtd->oobsize - column; -+ set_addr(mtd, column, page_addr, 1); -+ ctrl->read_bytes = mtd->oobsize; -+ ctrl->index = column; -+ goto write_cmd2; -+ /* READID must read all 5 possible bytes while CEB is active */ -+ case NAND_CMD_READID: -+ FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); -+ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | -+ (FIR_OP_UA << FIR_OP1_SHIFT) | -+ (FIR_OP_RBW << FIR_OP2_SHIFT); -+ lbc->fcr = (NAND_CMD_READID << FCR_CMD0_SHIFT); -+ lbc->fbcr = 5; /* 5 bytes for manuf, device and exts */ -+ ctrl->use_mdr = 1; -+ ctrl->mdr = 0; -+ goto write_cmd0; -+ /* ERASE1 stores the block and page address */ -+ case NAND_CMD_ERASE1: -+ FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_ERASE1, page_addr:" -+ " 0x%x.\n", page_addr); -+ set_addr(mtd, 0, page_addr, 0); -+ goto end; -+ /* ERASE2 uses the block and page address from ERASE1 */ -+ case NAND_CMD_ERASE2: -+ FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); -+ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | -+ (FIR_OP_PA << FIR_OP1_SHIFT) | -+ (FIR_OP_CM1 << FIR_OP2_SHIFT); -+ lbc->fcr = (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | -+ (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT); -+ lbc->fbcr = 0; -+ goto write_cmd1; -+ /* SEQIN sets up the addr buffer and all registers except the length */ -+ case NAND_CMD_SEQIN: -+ FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr:" -+ " 0x%x, column: 0x%x.\n", page_addr, column); -+ if (column == 0) { -+ lbc->fbcr = 0; /* write entire page to enable ECC */ -+ } else { -+ lbc->fbcr = 1; /* mark as partial page so no HW ECC */ -+ } -+ if (nmtd->pgs) { -+ /* always use READ0 for large page devices */ -+ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | -+ (FIR_OP_CA << FIR_OP1_SHIFT) | -+ (FIR_OP_PA << FIR_OP2_SHIFT) | -+ (FIR_OP_WB << FIR_OP3_SHIFT) | -+ (FIR_OP_CW1 << FIR_OP4_SHIFT); -+ lbc->fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) | -+ (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT); -+ set_addr(mtd, column, page_addr, 0); -+ } else { -+ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | -+ (FIR_OP_CM2 << FIR_OP1_SHIFT) | -+ (FIR_OP_CA << FIR_OP2_SHIFT) | -+ (FIR_OP_PA << FIR_OP3_SHIFT) | -+ (FIR_OP_WB << FIR_OP4_SHIFT) | -+ (FIR_OP_CW1 << FIR_OP5_SHIFT); -+ if (column >= mtd->writesize) { -+ /* OOB area --> READOOB */ -+ column -= mtd->writesize; -+ lbc->fcr = (NAND_CMD_READOOB << FCR_CMD0_SHIFT) -+ | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT) -+ | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); -+ set_addr(mtd, column, page_addr, 1); -+ } else if (column < 256) { -+ /* First 256 bytes --> READ0 */ -+ lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) -+ | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT) -+ | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); -+ set_addr(mtd, column, page_addr, 0); -+ } else { -+ /* Second 256 bytes --> READ1 */ -+ column -= 256; -+ lbc->fcr = (NAND_CMD_READ1 << FCR_CMD0_SHIFT) -+ | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT) -+ | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); -+ set_addr(mtd, column, page_addr, 0); -+ } -+ } -+ goto end; -+ /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ -+ case NAND_CMD_PAGEPROG: -+ FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG" -+ " writing %d bytes.\n",ctrl->index); -+ /* if the write did not start at 0 or is not a full page */ -+ /* then set the exact length, otherwise use a full page */ -+ /* write so the HW generates the ECC. */ -+ if (lbc->fbcr || -+ (ctrl->index != (mtd->writesize + mtd->oobsize))) -+ lbc->fbcr = ctrl->index; -+ goto write_cmd2; -+ /* CMD_STATUS must read the status byte while CEB is active */ -+ /* Note - it does not wait for the ready line */ -+ case NAND_CMD_STATUS: -+ FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_STATUS.\n"); -+ lbc->fir = (FIR_OP_CM0 << FIR_OP0_SHIFT) | -+ (FIR_OP_RBW << FIR_OP1_SHIFT); -+ lbc->fcr = (NAND_CMD_STATUS << FCR_CMD0_SHIFT); -+ lbc->fbcr = 1; -+ goto write_cmd0; -+ /* RESET without waiting for the ready line */ -+ case NAND_CMD_RESET: -+ FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); -+ lbc->fir = (FIR_OP_CM0 << FIR_OP0_SHIFT); -+ lbc->fcr = (NAND_CMD_RESET << FCR_CMD0_SHIFT); -+ lbc->fbcr = 0; -+ goto write_cmd0; -+ default: -+ printk("fsl_elbc_cmdfunc: error, unsupported command.\n"); -+ goto end; -+ } -+ -+ /* Short cuts fall through to save code */ -+ write_cmd0: -+ set_addr(mtd, 0, 0, 0); -+ write_cmd1: -+ ctrl->read_bytes = lbc->fbcr; -+ write_cmd2: -+ fsl_elbc_run_command(mtd); -+ -+#ifdef CONFIG_MTD_NAND_VERIFY_WRITE -+ /* if we wrote a page then read back the oob to get the ECC */ -+ if ((command == NAND_CMD_PAGEPROG) && -+ (chip->ecc.mode > NAND_ECC_SOFT) && -+ (lbc->fbcr == 0) && -+ (ctrl->oobbuf != 0) && -+ (ctrl->oobbuf != -1)) { -+ int i; -+ uint *oob_config; -+ unsigned char *oob_buf; -+ -+ i = ctrl->page; -+ oob_buf = (unsigned char*) ctrl->oobbuf; -+ oob_config = chip->ecc.layout->eccpos; -+ -+ /* wait for the write to complete and check it passed */ -+ if (!(chip->waitfunc(mtd, chip) & 0x01)) { -+ /* read back the OOB */ -+ fsl_elbc_cmdfunc(mtd, NAND_CMD_READOOB, 0, i); -+ /* if it succeeded then copy the ECC bytes */ -+ if (ctrl->status == LTESR_CC) { -+ for (i=0; i < chip->ecc.layout->eccbytes; i++) { -+ oob_buf[oob_config[i]] = -+ ctrl->addr[oob_config[i]]; -+ } -+ } -+ } -+ } -+#endif -+ -+ end: -+ return; -+} -+ -+/* select chip */ -+ -+static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) -+{ -+} -+ -+/* fsl_elbc_cmd_ctrl -+ * -+ * Issue command and address cycles to the chip -+*/ -+ -+static void fsl_elbc_cmd_ctrl(struct mtd_info *mtd, int dat, -+ unsigned int ctrl) -+{ -+} -+ -+/* fsl_elbc_dev_ready() -+ * -+ * returns 0 if the nand is busy, 1 if it is ready -+*/ -+ -+static int fsl_elbc_dev_ready(struct mtd_info *mtd) -+{ -+ return 0; -+} -+ -+/* -+ * FCM does not support 16 bit data busses -+ */ -+static u16 fsl_elbc_read_word(struct mtd_info *mtd) -+{ -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_ctrl *ctrl = (struct fsl_elbc_ctrl *) chip->controller; -+ -+ dev_err(ctrl->device, "fsl_elbc_read_word: UNIMPLEMENTED.\n"); -+ return 0; -+} -+ -+/* -+ * Write buf to the FCM Controller Data Buffer -+ */ -+static void fsl_elbc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -+{ -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_mtd *nmtd = chip->priv; -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ -+ FCM_DEBUG(3,"fsl_elbc_write_buf: writing %d bytes starting with 0x%lx" -+ " at %d.\n", len, *((unsigned long*) buf), ctrl->index); -+ -+ /* If armed catch the address of the OOB buffer so that it can be */ -+ /* updated with the real signature after the program comletes */ -+ if (!ctrl->oobbuf) -+ ctrl->oobbuf = (int) buf; -+ -+ /* copy the data into the FCM hardware buffer and update the index */ -+ memcpy(&(ctrl->addr[ctrl->index]), buf, len); -+ ctrl->index += len; -+ return; -+} -+ -+ -+/* -+ * read a byte from either the FCM hardware buffer if it has any data left -+ * otherwise issue a command to read a single byte. -+ */ -+static u_char fsl_elbc_read_byte(struct mtd_info *mtd) -+{ -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_mtd *nmtd = chip->priv; -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ volatile lbus83xx_t *lbc = ctrl->regs; -+ unsigned char byte; -+ -+ /* If there are still bytes in the FCM then use the next byte */ -+ if(ctrl->index < ctrl->read_bytes) { -+ byte = ctrl->addr[(ctrl->index)++]; -+ FCM_DEBUG(4,"fsl_elbc_read_byte: byte %u (%02X): %d of %d.\n", -+ byte, byte, ctrl->index-1, ctrl->read_bytes); -+ } else { -+ /* otherwise issue a command to read 1 byte */ -+ lbc->fir = (FIR_OP_RSW << FIR_OP0_SHIFT); -+ ctrl->use_mdr = 1; -+ ctrl->read_bytes = 0; -+ ctrl->index = 0; -+ ctrl->read_bytes = 0; -+ ctrl->index = 0; -+ byte = fsl_elbc_run_command(mtd) ? ERR_BYTE : ctrl->mdr & 0xff; -+ FCM_DEBUG(4,"fsl_elbc_read_byte: byte %u (%02X) from bus.\n", -+ byte, byte); -+ } -+ -+ return byte; -+} -+ -+/* -+ * Read from the FCM Controller Data Buffer -+ */ -+static void fsl_elbc_read_buf(struct mtd_info *mtd, u_char* buf, int len) -+{ -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_mtd *nmtd = chip->priv; -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ int i; -+ int rest; -+ unsigned long old_status; -+ -+ FCM_DEBUG(3,"fsl_elbc_read_buf: reading %d bytes.\n", len); -+ -+ /* see how much is still in the FCM buffer */ -+ i = min((unsigned int)len, (ctrl->read_bytes - ctrl->index)); -+ rest = len - i; -+ len = i; -+ -+ /* copying bytes even if there was an error so that the oob works */ -+ memcpy(buf, &(ctrl->addr[(ctrl->index)]), len); -+ ctrl->index += len; -+ -+ /* If more data is needed then issue another block read */ -+ if (rest) { -+ FCM_DEBUG(3,"fsl_elbc_read_buf: getting %d more bytes.\n", -+ rest); -+ -+ buf += len; -+ -+ /* keep last status in case it was an error */ -+ old_status = ctrl->status; -+ -+ /* read full next page to use HW ECC if enabled */ -+ fsl_elbc_cmdfunc(mtd, NAND_CMD_READ0, 0, ctrl->page + 1); -+ -+ /* preserve the worst status code */ -+ if (ctrl->status == LTESR_CC) -+ ctrl->status = old_status; -+ -+ fsl_elbc_read_buf(mtd, buf, rest); -+ } -+ return; -+} -+ -+ -+/* -+ * Verify buffer against the FCM Controller Data Buffer -+ */ -+static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -+{ -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_mtd *nmtd = chip->priv; -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ int i; -+ int rest; -+ -+ FCM_DEBUG(3,"fsl_elbc_verify_buf: checking %d bytes starting with 0x%02lx.\n", -+ len, *((unsigned long*) buf)); -+ -+ /* If last read failed then return error bytes */ -+ if (ctrl->status != LTESR_CC) { -+ return EFAULT; -+ } -+ -+ /* see how much is still in the FCM buffer */ -+ i = min((unsigned int)len, (ctrl->read_bytes - ctrl->index)); -+ rest = len - i; -+ len = i; -+ -+ if (memcmp(buf, &(ctrl->addr[(ctrl->index)]), len)) { -+ return EFAULT; -+ } -+ -+ ctrl->index += len; -+ if (rest) { -+ FCM_DEBUG(3,"fsl_elbc_verify_buf: getting %d more bytes.\n", rest); -+ buf += len; -+ -+ /* read full next page to use HW ECC if enabled */ -+ fsl_elbc_cmdfunc(mtd, NAND_CMD_READ0, 0, ctrl->page + 1); -+ -+ return fsl_elbc_verify_buf(mtd, buf, rest); -+ } -+ return 0; -+} -+ -+/* this function is called after Program and Erase Operations to -+ * check for success or failure */ -+static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *this) -+{ -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_mtd *nmtd = chip->priv; -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ volatile lbus83xx_t *lbc = ctrl->regs; -+ -+ if (ctrl->status != LTESR_CC) { -+ return(0x1); /* Status Read error */ -+ } -+ -+ /* Use READ_STATUS command, but wait for the device to be ready */ -+ ctrl->use_mdr = 0; -+ ctrl->oobbuf = -1; -+ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | -+ (FIR_OP_RBW << FIR_OP1_SHIFT); -+ lbc->fcr = (NAND_CMD_STATUS << FCR_CMD0_SHIFT); -+ set_addr(mtd, 0, 0, 0); -+ lbc->fbcr = 1; -+ ctrl->index = 0; -+ ctrl->read_bytes = lbc->fbcr; -+ fsl_elbc_run_command(mtd); -+ if (ctrl->status != LTESR_CC) { -+ return(0x1); /* Status Read error */ -+ } -+ return chip->read_byte(mtd); -+} -+ -+/* ECC handling functions */ -+ -+/* -+ * fsl_elbc_enable_hwecc - start ECC generation -+ */ -+static void fsl_elbc_enable_hwecc(struct mtd_info *mtd, int mode) -+{ -+ return; -+} -+ -+/* -+ * fsl_elbc_calculate_ecc - Calculate the ECC bytes -+ * This is done by hardware during the write process, so we use this -+ * to arm the oob buf capture on the next write_buf() call. The ECC bytes -+ * only need to be captured if CONFIG_MTD_NAND_VERIFY_WRITE is defined which -+ * reads back the pages and checks they match the data and oob buffers. -+ */ -+static int fsl_elbc_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) -+{ -+#ifdef CONFIG_MTD_NAND_VERIFY_WRITE -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_mtd *nmtd = chip->priv; -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ -+ /* arm capture of oob buf ptr on next write_buf */ -+ ctrl->oobbuf = 0; -+#endif -+ return 0; -+} -+ -+/* -+ * fsl_elbc_correct_data - Detect and correct bit error(s) -+ * The detection and correction is done automatically by the hardware, -+ * if the complete page was read. If the status code is okay then there -+ * was no error, otherwise we return an error code indicating an uncorrectable -+ * error. -+ */ -+static int fsl_elbc_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) -+{ -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_mtd *nmtd = chip->priv; -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ -+ /* No errors */ -+ if (ctrl->status == LTESR_CC) -+ return 0; -+ -+ return -1; /* uncorrectable error */ -+} -+ -+/*************************************************************************/ -+/* Chip setup and control functions */ -+/*************************************************************************/ -+ -+/* -+ * Dummy scan_bbt to complete setup of the FMR based on NAND size -+ */ -+static int fsl_elbc_chip_init_tail (struct mtd_info *mtd) -+{ -+ struct nand_chip *chip = mtd->priv; -+ struct fsl_elbc_mtd *nmtd = chip->priv; -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ volatile lbus83xx_t *lbc = ctrl->regs; -+ unsigned int i; -+ unsigned int al; -+ -+ /* calculate FMR Address Length field */ -+ al = 0; -+ for (i = chip->pagemask >> 16; i ; i >>= 8) { -+ al++; -+ } -+ -+ /* add to ECCM mode set in fsl_elbc_init */ -+ nmtd->fmr |= 12 << FMR_CWTO_SHIFT | /* Timeout > 12 mSecs */ -+ al << FMR_AL_SHIFT; -+ -+ FCM_DEBUG(1,"fsl_elbc_init: nand->options = %08X\n", chip->options); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->numchips = %10d\n", chip->numchips); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->chipsize = %10ld\n", chip->chipsize); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->pagemask = %10X\n", chip->pagemask); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->chip_delay = %8d\n", chip->chip_delay); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->badblockpos = %7d\n", chip->badblockpos); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->chip_shift = %8d\n", chip->chip_shift); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->page_shift = %8d\n", chip->page_shift); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->phys_erase_shift = %2d\n", -+ chip->phys_erase_shift); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->ecclayout= %10p\n", chip->ecclayout); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->eccmode = %10d\n", chip->ecc.mode ); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->eccsteps = %10d\n", chip->ecc.steps); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->eccsize = %10d\n", chip->ecc.size ); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->eccbytes = %10d\n", chip->ecc.bytes); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->ecctotal = %10d\n", chip->ecc.total); -+ FCM_DEBUG(1,"fsl_elbc_init: nand->ecclayout= %10p\n", chip->ecc.layout); -+ FCM_DEBUG(1,"fsl_elbc_init: mtd->flags = %08X\n", mtd->flags); -+ FCM_DEBUG(1,"fsl_elbc_init: mtd->size = %10d\n", mtd->size); -+ FCM_DEBUG(1,"fsl_elbc_init: mtd->erasesize = %10d\n", mtd->erasesize); -+ FCM_DEBUG(1,"fsl_elbc_init: mtd->writesize = %10d\n", mtd->writesize); -+ FCM_DEBUG(1,"fsl_elbc_init: mtd->oobsize = %10d\n", mtd->oobsize); -+ FCM_DEBUG(1,"fsl_elbc_init: mtd->ecctype = %10d\n", mtd->ecctype); -+ FCM_DEBUG(1,"fsl_elbc_init: mtd->eccsize = %10d\n", mtd->eccsize); -+ -+ /* adjust Option Register and ECC to match Flash page size */ -+ if (mtd->writesize == 512) -+ lbc->bank[nmtd->bank].or &= ~(OR_FCM_PGS); -+ else if (mtd->writesize == 2048) { -+ lbc->bank[nmtd->bank].or |= OR_FCM_PGS; -+ /* adjust ecc setup if needed */ -+ if ( (lbc->bank[nmtd->bank].br & BR_DECC) == BR_DECC_CHK_GEN) { -+ chip->ecc.size = 2048; -+ chip->ecc.steps = 1; -+//TODO chip->ecc.bytes += 9; -+//TODO chip->ecc.total += 9; -+ chip->ecc.layout = (nmtd->fmr & FMR_ECCM) ? -+ &fsl_elbc_oob_lp_eccm1 : &fsl_elbc_oob_lp_eccm0; -+ mtd->ecclayout = chip->ecc.layout; -+ } -+ } -+ else { -+ printk("fsl_elbc_init: page size %d is not supported\n", -+ mtd->writesize); -+ return -1; -+ } -+ nmtd->pgs = (lbc->bank[nmtd->bank].or>>OR_FCM_PGS_SHIFT) & 1; -+ -+ /* fix up the oobavail size in case the layout was changed */ -+ chip->ecc.layout->oobavail = 0; -+ for (i = 0; chip->ecc.layout->oobfree[i].length; i++) -+ chip->ecc.layout->oobavail += -+ chip->ecc.layout->oobfree[i].length; -+ -+ /* return to the default bbt_scan_routine */ -+ chip->scan_bbt = nand_default_bbt; -+ -+ /* restore complete options including the real SKIP_BBTSCAN setting */ -+ chip->options = nmtd->options; -+ -+ /* Check, if we should skip the bad block table scan */ -+ if (chip->options & NAND_SKIP_BBTSCAN) -+ return 0; -+ -+ return chip->scan_bbt(mtd); -+} -+/* fsl_elbc_chip_init -+ * -+ * init a single instance of an chip -+*/ -+ -+static int fsl_elbc_chip_init(struct fsl_elbc_mtd *nmtd) -+{ -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ volatile lbus83xx_t *lbc = ctrl->regs; -+ struct nand_chip *chip = &nmtd->chip; -+ -+ FCM_DEBUG(1,"eLBC Set Information for bank %d\n", nmtd->bank); -+ FCM_DEBUG(1," name = %s\n", -+ nmtd->pl_chip.name ? nmtd->pl_chip.name : "(NULL)"); -+ FCM_DEBUG(1," nr_chips = %d\n", nmtd->pl_chip.nr_chips); -+ FCM_DEBUG(1," partitions = %s\n", -+ nmtd->pl_chip.partitions_str ? -+ nmtd->pl_chip.partitions_str : "(NULL)"); -+ dev_dbg(nmtd->device,"eLBC Set Information for bank %d\n", nmtd->bank); -+ dev_dbg(nmtd->device," name = %s\n", -+ nmtd->name ? nmtd->name : "(NULL)"); -+ dev_dbg(nmtd->device," nr_chips = %d\n", nmtd->pl_chip.nr_chips); -+ dev_dbg(nmtd->device," partitions = %s\n", -+ nmtd->pl_chip.partitions_str ? -+ nmtd->pl_chip.partitions_str : "(NULL)"); -+ -+ /* Fill in fsl_elbc_mtd structure */ -+ nmtd->name = (char *) nmtd->pl_chip.name; -+ nmtd->mtd.name = nmtd->name; -+ nmtd->mtd.priv = chip; -+ nmtd->mtd.owner = THIS_MODULE; -+ nmtd->pgs = (lbc->bank[nmtd->bank].or>>OR_FCM_PGS_SHIFT) & 1; -+// TODO nmtd->fmr = FMR_ECCM; /* rest filled in later */ -+ nmtd->fmr = 0; /* rest filled in later */ -+ -+ /* fill in nand_chip structure */ -+ /* set physical base address from the Base Register */ -+ chip->IO_ADDR_W = (void __iomem*) (nmtd->pbase); -+ chip->IO_ADDR_R = chip->IO_ADDR_W; -+ -+ /* set up function call table */ -+// chip->hwcontrol = fsl_elbc_hwcontrol; -+ chip->read_byte = fsl_elbc_read_byte; -+ chip->read_word = fsl_elbc_read_word; -+ chip->write_buf = fsl_elbc_write_buf; -+ chip->read_buf = fsl_elbc_read_buf; -+ chip->verify_buf = fsl_elbc_verify_buf; -+ chip->select_chip = fsl_elbc_select_chip; -+// TODO chip->block_bad -+// TODO chip->block_markbad -+ chip->cmd_ctrl = fsl_elbc_cmd_ctrl; -+ chip->dev_ready = fsl_elbc_dev_ready; -+ chip->cmdfunc = fsl_elbc_cmdfunc; -+ chip->waitfunc = fsl_elbc_wait; -+ chip->scan_bbt = fsl_elbc_chip_init_tail; -+// TODO chip->errstat -+ -+ /* set up nand options */ -+ chip->options = NAND_NO_READRDY; -+ chip->chip_delay = 1; -+ -+ chip->controller = &ctrl->controller; -+ chip->priv = nmtd; -+ -+ /* If CS Base Register selects full hardware ECC then use it */ -+ if ( (lbc->bank[nmtd->bank].br & BR_DECC) == BR_DECC_CHK_GEN) { -+ chip->ecc.mode = NAND_ECC_HW; -+ chip->ecc.calculate = fsl_elbc_calculate_ecc; -+ chip->ecc.correct = fsl_elbc_correct_data; -+ chip->ecc.hwctl = fsl_elbc_enable_hwecc; -+ /* put in small page settings and adjust later if needed */ -+ chip->ecc.layout = (nmtd->fmr & FMR_ECCM) ? -+ &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0; -+ chip->ecc.size = 512; -+ chip->ecc.bytes = 3; -+ } else { -+ /* otherwise fall back to default software ECC */ -+ chip->ecc.mode = NAND_ECC_SOFT; -+ } -+ -+ /* force BBT scan to get to custom scan_bbt for final settings */ -+ nmtd->options = chip->options; -+ chip-> options &= ~(NAND_SKIP_BBTSCAN); -+ -+ return 0; -+} -+ -+ -+ -+static int fsl_elbc_chip_remove(struct platform_device *pdev) -+{ -+ struct fsl_elbc_mtd *nmtd = platform_get_drvdata(pdev); -+ struct fsl_elbc_ctrl *ctrl = nmtd->ctrl; -+ -+ nand_release(&nmtd->mtd); -+ -+ if (nmtd->vbase != 0) { -+ iounmap((void __iomem*)nmtd->vbase); -+ nmtd->vbase = 0; -+ } -+ -+/* TODO -+ if (nmtd->area != NULL) { -+ release_resource(nmtd->area); -+ kfree(nmtd->area); -+ nmtd->area = NULL; -+ } -+*/ -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ ctrl->nmtd[nmtd->bank] = NULL; -+ atomic_dec(&ctrl->childs_active); -+ -+ kfree(nmtd); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_MTD_PARTITIONS -+const char *part_probes[] = { "cmdlinepart", NULL }; -+#endif -+ -+static int fsl_elbc_chip_probe(struct platform_device *pdev) -+{ -+ struct platform_fsl_nand_chip *pnc = pdev->dev.platform_data; -+ struct fsl_elbc_ctrl *ctrl = &elbc_ctrl; -+ volatile lbus83xx_t *lbc = ctrl->regs; -+ struct fsl_elbc_mtd *nmtd; -+ struct resource *res; -+ int err = 0; -+ int size; -+ int bank; -+ int mtd_parts_nb = 0; -+ struct mtd_partition *mtd_parts = 0; -+ -+ dev_dbg(&pdev->dev, "fsl_elbc_chip_probe(%p)\n", pdev); -+ -+ /* check that the platform data structure was supplied */ -+ if (pnc == NULL) { -+ dev_err(&pdev->dev,"Device needs a platform data structure\n"); -+ return -ENOENT; -+ } -+ -+ /* check that the device has a name */ -+ if (pnc->name == NULL) { -+ dev_err(&pdev->dev,"Device requires a name\n"); -+ return -ENOENT; -+ } -+ /* get, allocate and map the memory resource */ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (res == NULL) { -+ dev_err(&pdev->dev,"failed to get memory region resource\n"); -+ return -ENOENT; -+ } -+ /* find which chip select it is connected to */ -+ for (bank=0; bank < MAX_BANKS; bank++) { -+ if ( (lbc->bank[bank].br & BR_V) && -+ ((lbc->bank[bank].br & BR_MSEL) == BR_MS_FCM) && -+ ((lbc->bank[bank].br & lbc->bank[bank].or & BR_BA) == -+ res->start) ) { -+ break; -+ } -+ } -+ -+ if (bank >= MAX_BANKS) { -+ dev_err(&pdev->dev,"address did not match any chip selects\n"); -+ return -ENOENT; -+ } -+ -+ nmtd = kmalloc (sizeof(*nmtd), GFP_KERNEL); -+ if (!nmtd) { -+ dev_err(ctrl->device, "no memory for nand chip structure\n"); -+ return -ENOMEM; -+ } -+ memset(nmtd, 0, sizeof(*nmtd)); -+ -+ platform_set_drvdata(pdev, nmtd); -+ -+ atomic_inc(&ctrl->childs_active); -+ if (pnc) -+ memcpy(&(nmtd->pl_chip), pnc, sizeof(*pnc)); -+ ctrl->nmtd[bank] = nmtd; -+ nmtd->bank = bank; -+ nmtd->ctrl = ctrl; -+ nmtd->device = &pdev->dev; -+ -+ size = ( res->end - res->start ) + 1; -+/* TODO - already requested by the elbc instance ????? -+ ctrl->area = request_mem_region(res->start, size, pdev->name); -+ if (ctrl->area == NULL) { -+ dev_err(&pdev->dev, "failed to get memory region\n"); -+ err = -ENOENT; -+ goto exit_error; -+ } -+*/ -+ nmtd->pbase = res->start; -+ nmtd->vbase = (unsigned int) ioremap(nmtd->pbase, FCM_SIZE); -+ if (nmtd->vbase == 0) { -+ dev_err(ctrl->device, "failed to ioremap() memory region\n"); -+ err = -EIO; -+ goto exit_error; -+ } -+ -+ err = fsl_elbc_chip_init(nmtd); -+ if (err != 0) -+ goto exit_error; -+ -+ err = nand_scan(&nmtd->mtd, -+ nmtd->pl_chip.nr_chips ? nmtd->pl_chip.nr_chips : 1 ); -+ if (err != 0) -+ goto exit_error; -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ /* check for command line partition information */ -+ if (!(nmtd->pl_chip.options & FSL_ELBC_NO_CMDLINE_PARTITIONS)) -+ mtd_parts_nb = parse_mtd_partitions( -+ &nmtd->mtd, -+ part_probes, -+ &mtd_parts, -+ 0); -+#if 0 -+ /* otherwise try local partition string */ -+ if (mtd_parts_nb <= 0 && nmtd->pl_chip.partitions_str) -+ mtd_parts_nb = parse_mtd_string_partitions( -+ &nmtd->mtd, -+ part_probes, -+ &mtd_parts, -+ 0, -+ nmtd->pl_chip.partitions_str); -+#endif -+ if (mtd_parts_nb > 0) -+ err = add_mtd_partitions(&nmtd->mtd, -+ mtd_parts, -+ mtd_parts_nb); -+ else -+#endif -+ err = add_mtd_device(&nmtd->mtd); -+ -+ if (err == 0) -+ return 0; -+ -+ exit_error: -+ fsl_elbc_chip_remove(pdev); -+ -+ if (err == 0) -+ err = -EINVAL; -+ return err; -+} -+ -+ -+/**************************************************************************/ -+/* Controller setup and control functions */ -+/**************************************************************************/ -+ -+static int fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl, -+ struct platform_device *pdev) -+{ -+ volatile lbus83xx_t *lbc= (lbus83xx_t*) ctrl->regs; -+ -+ /* Enable only FCM detection of timeouts, ECC errors and completion */ -+ lbc->ltedr = ~(LTESR_FCT | LTESR_PAR | LTESR_CC); -+ -+ /* clear event registers */ -+ lbc->lteatr = 0; -+ lbc->ltesr |= (LTESR_FCT | LTESR_PAR | LTESR_CC); -+ -+ /* Enable interrupts for any detected events */ -+ lbc->lteir = ~0; -+ -+ ctrl->read_bytes = 0; -+ ctrl->index = 0; -+ ctrl->addr = (unsigned char*) (NULL); -+ ctrl->oobbuf = -1; -+ -+ return 0; -+} -+ -+static int fsl_elbc_ctrl_remove(struct platform_device *pdev) -+{ -+ struct fsl_elbc_ctrl *ctrl = platform_get_drvdata(pdev); -+ -+ if (atomic_read(&ctrl->childs_active)) -+ return -EBUSY; -+ -+ if (ctrl->regs != NULL) { -+ iounmap(ctrl->regs); -+ ctrl->regs = NULL; -+ } -+ -+/* TODO -+ if (ctrl->area != NULL) { -+ release_resource(ctrl->area); -+ kfree(ctrl->area); -+ ctrl->area = NULL; -+ } -+*/ -+ if (ctrl->irq) { -+ free_irq(ctrl->irq, pdev); -+ ctrl->irq = 0; -+ } -+ -+ platform_set_drvdata(pdev, NULL); -+ memset(ctrl, 0, sizeof(*ctrl)); -+ -+ return 0; -+} -+ -+ -+/* interrupt handler code */ -+ -+static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *param) -+{ -+ struct fsl_elbc_ctrl *ctrl = platform_get_drvdata((struct platform_device*)param); -+ volatile lbus83xx_t *lbc= (lbus83xx_t*) ctrl->regs; -+ -+ ctrl->irq_status = lbc->ltesr & (LTESR_FCT | LTESR_PAR | LTESR_CC); -+ if (ctrl->irq_status) -+ wake_up(&ctrl->irq_wait); -+ -+ /* clear event registers */ -+ lbc->lteatr = 0; -+ lbc->ltesr |= ctrl->irq_status; -+ -+ return IRQ_HANDLED; -+} -+ -+ -+/* fsl_elbc_ctrl_probe -+ * -+ * called by device layer when it finds a device matching -+ * one our driver can handled. This code allocates all of -+ * the resources needed for the controller only. The -+ * resources for the NAND banks themselves are allocated -+ * in the chip probe function. -+*/ -+ -+static int fsl_elbc_ctrl_probe(struct platform_device *pdev) -+{ -+ struct fsl_elbc_ctrl *ctrl; -+ struct resource *res; -+ int err = 0; -+ int size; -+ int ret; -+ -+ dev_dbg(&pdev->dev, "fsl_elbc_ctrl_probe(%p)\n", pdev); -+ ctrl = &elbc_ctrl; -+ -+ memset(ctrl, 0, sizeof(*ctrl)); -+ platform_set_drvdata(pdev, ctrl); -+ -+ spin_lock_init(&ctrl->controller.lock); -+ init_waitqueue_head(&ctrl->controller.wq); -+ init_waitqueue_head(&ctrl->irq_wait); -+ -+ /* get, allocate and map the memory resource */ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (res == NULL) { -+ dev_err(&pdev->dev,"failed to get memory region resouce\n"); -+ err = -ENOENT; -+ goto exit_error; -+ } -+ -+ size = ( res->end - res->start ) + 1; -+/* TODO - already requested by the elbc instance ????? -+ ctrl->area = request_mem_region(res->start, size, pdev->name); -+ if (ctrl->area == NULL) { -+ dev_err(&pdev->dev, "failed to get memory region\n"); -+ err = -ENOENT; -+ goto exit_error; -+ } -+*/ -+ ctrl->regs = ioremap(res->start, size); -+ if (ctrl->regs == 0) { -+ dev_err(&pdev->dev, "failed to ioremap() region\n"); -+ err = -EIO; -+ goto exit_error; -+ } -+ -+ /* get and allocate the irq resource */ -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (res == NULL) { -+ dev_err(&pdev->dev, "failed to get irq resource\n"); -+ err = -ENOENT; -+ goto exit_error; -+ } -+ -+ ret = request_irq(res->start, fsl_elbc_ctrl_irq, 0, pdev->name, pdev); -+ if (ret != 0) { -+ dev_err(&pdev->dev, "failed to install irq (%d)\n", ret); -+ err = -EIO; -+ goto exit_error; -+ } -+ -+ ctrl->irq = res->start; -+ ctrl->device = &pdev->dev; -+ dev_dbg(&pdev->dev, "mapped registers at %p\n", ctrl->regs); -+ -+ /* initialise the hardware */ -+ -+ err = fsl_elbc_ctrl_init(ctrl, pdev); -+ if (err == 0) -+ return 0; -+ -+ exit_error: -+ fsl_elbc_ctrl_remove(pdev); -+ -+ if (err == 0) -+ err = -EINVAL; -+ return err; -+} -+ -+/* PM Support */ -+#ifdef CONFIG_PM -+ -+static int fsl_elbc_ctrl_suspend(struct platform_device *dev, pm_message_t pm) -+{ -+ return 0; -+} -+ -+static int fsl_elbc_ctrl_resume(struct platform_device *dev) -+{ -+ return 0; -+} -+ -+#else -+#define fsl_elbc_ctrl_suspend NULL -+#define fsl_elbc_ctrl_resume NULL -+#endif -+ -+/*************************************************************************/ -+/* device driver registration */ -+/*************************************************************************/ -+ -+ -+static struct platform_driver fsl_elbc_ctrl_driver = { -+ .probe = fsl_elbc_ctrl_probe, -+ .remove = fsl_elbc_ctrl_remove, -+ .suspend = fsl_elbc_ctrl_suspend, -+ .resume = fsl_elbc_ctrl_resume, -+ .driver = { -+ .name = "fsl-elbc", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static struct platform_driver fsl_elbc_chip_driver = { -+ .probe = fsl_elbc_chip_probe, -+ .remove = fsl_elbc_chip_remove, -+ .driver = { -+ .name = "fsl-nand", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init fsl_elbc_init(void) -+{ -+ int ret; -+ -+ printk("Freescale eLBC NAND Driver (C) 2006 Freescale\n"); -+ -+ ret = platform_driver_register(&fsl_elbc_ctrl_driver); -+ if (!ret) -+ ret = platform_driver_register(&fsl_elbc_chip_driver); -+ -+ return ret; -+} -+ -+static void __exit fsl_elbc_exit(void) -+{ -+ platform_driver_unregister(&fsl_elbc_chip_driver); -+ platform_driver_unregister(&fsl_elbc_ctrl_driver); -+} -+ -+module_init(fsl_elbc_init); -+module_exit(fsl_elbc_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Nick Spence"); -+MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver"); -diff -urN linux-2.6.23.orig/drivers/mtd/nand/Kconfig linux-2.6.23/drivers/mtd/nand/Kconfig ---- linux-2.6.23.orig/drivers/mtd/nand/Kconfig 2007-10-09 22:31:38.000000000 +0200 -+++ linux-2.6.23/drivers/mtd/nand/Kconfig 2007-11-28 20:36:39.000000000 +0100 -@@ -265,6 +265,14 @@ - depends on MTD_NAND && MACH_ARMCORE - - -+config MTD_NAND_FSL_ELBC -+ tristate "NAND support for MPC831x" -+ depends on MTD_NAND && PPC_MPC831x -+ help -+ The MPC831x includes a NAND FLASH Controller Module with built-in hardware -+ ECC capabilities. Enabling this This option will enable you to use these to -+ control external NAND device. -+ - config MTD_NAND_NANDSIM - tristate "Support for NAND Flash Simulator" - depends on MTD_PARTITIONS -diff -urN linux-2.6.23.orig/drivers/mtd/nand/Makefile linux-2.6.23/drivers/mtd/nand/Makefile ---- linux-2.6.23.orig/drivers/mtd/nand/Makefile 2007-10-09 22:31:38.000000000 +0200 -+++ linux-2.6.23/drivers/mtd/nand/Makefile 2007-11-28 20:36:39.000000000 +0100 -@@ -27,5 +27,6 @@ - obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o - obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o -+obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc.o - - nand-objs := nand_base.o nand_bbt.o -diff -urN linux-2.6.23.orig/include/linux/mtd/fsl_elbc.h linux-2.6.23/include/linux/mtd/fsl_elbc.h ---- linux-2.6.23.orig/include/linux/mtd/fsl_elbc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.23/include/linux/mtd/fsl_elbc.h 2007-11-28 20:36:39.000000000 +0100 -@@ -0,0 +1,313 @@ -+/* -+ * (C) Copyright 2004-2006 Freescale Semiconductor, Inc. -+ * -+ * Freescale Enhanced Local Bus Controller Internal Memory Map -+ * -+ * History : -+ * 20061010 : Extracted fomr immap_83xx.h -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ * -+ */ -+#ifdef __KERNEL__ -+#ifndef __FSL_ELBC__ -+#define __FSL_ELBC__ -+ -+/* -+ * Local Bus Controller Registers -+ */ -+typedef struct lbus_bank{ -+ u32 br; /**< Base Register */ -+#define BR0 0x5000 -+#define BR1 0x5008 -+#define BR2 0x5010 -+#define BR3 0x5018 -+#define BR4 0x5020 -+#define BR5 0x5028 -+#define BR6 0x5030 -+#define BR7 0x5038 -+ -+#define BR_BA 0xFFFF8000 -+#define BR_BA_SHIFT 15 -+#define BR_PS 0x00001800 -+#define BR_PS_SHIFT 11 -+#define BR_PS_8 0x00000800 /* Port Size 8 bit */ -+#define BR_PS_16 0x00001000 /* Port Size 16 bit */ -+#define BR_PS_32 0x00001800 /* Port Size 32 bit */ -+#define BR_DECC 0x00000600 -+#define BR_DECC_SHIFT 9 -+#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */ -+#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */ -+#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */ -+#define BR_WP 0x00000100 -+#define BR_WP_SHIFT 8 -+#define BR_MSEL 0x000000E0 -+#define BR_MSEL_SHIFT 5 -+#define BR_MS_GPCM 0x00000000 /* GPCM */ -+#define BR_MS_FCM 0x00000020 /* FCM */ -+#define BR_MS_SDRAM 0x00000060 /* SDRAM */ -+#define BR_MS_UPMA 0x00000080 /* UPMA */ -+#define BR_MS_UPMB 0x000000A0 /* UPMB */ -+#define BR_MS_UPMC 0x000000C0 /* UPMC */ -+#define BR_V 0x00000001 -+#define BR_V_SHIFT 0 -+#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) -+ -+ u32 or; /**< Base Register */ -+#define OR0 0x5004 -+#define OR1 0x500C -+#define OR2 0x5014 -+#define OR3 0x501C -+#define OR4 0x5024 -+#define OR5 0x502C -+#define OR6 0x5034 -+#define OR7 0x503C -+ -+#define OR_GPCM_AM 0xFFFF8000 -+#define OR_GPCM_AM_SHIFT 15 -+#define OR_GPCM_BCTLD 0x00001000 -+#define OR_GPCM_BCTLD_SHIFT 12 -+#define OR_GPCM_CSNT 0x00000800 -+#define OR_GPCM_CSNT_SHIFT 11 -+#define OR_GPCM_ACS 0x00000600 -+#define OR_GPCM_ACS_SHIFT 9 -+#define OR_GPCM_ACS_0b10 0x00000400 -+#define OR_GPCM_ACS_0b11 0x00000600 -+#define OR_GPCM_XACS 0x00000100 -+#define OR_GPCM_XACS_SHIFT 8 -+#define OR_GPCM_SCY 0x000000F0 -+#define OR_GPCM_SCY_SHIFT 4 -+#define OR_GPCM_SCY_1 0x00000010 -+#define OR_GPCM_SCY_2 0x00000020 -+#define OR_GPCM_SCY_3 0x00000030 -+#define OR_GPCM_SCY_4 0x00000040 -+#define OR_GPCM_SCY_5 0x00000050 -+#define OR_GPCM_SCY_6 0x00000060 -+#define OR_GPCM_SCY_7 0x00000070 -+#define OR_GPCM_SCY_8 0x00000080 -+#define OR_GPCM_SCY_9 0x00000090 -+#define OR_GPCM_SCY_10 0x000000a0 -+#define OR_GPCM_SCY_11 0x000000b0 -+#define OR_GPCM_SCY_12 0x000000c0 -+#define OR_GPCM_SCY_13 0x000000d0 -+#define OR_GPCM_SCY_14 0x000000e0 -+#define OR_GPCM_SCY_15 0x000000f0 -+#define OR_GPCM_SETA 0x00000008 -+#define OR_GPCM_SETA_SHIFT 3 -+#define OR_GPCM_TRLX 0x00000004 -+#define OR_GPCM_TRLX_SHIFT 2 -+#define OR_GPCM_EHTR 0x00000002 -+#define OR_GPCM_EHTR_SHIFT 1 -+#define OR_GPCM_EAD 0x00000001 -+#define OR_GPCM_EAD_SHIFT 0 -+ -+#define OR_UPM_AM 0xFFFF8000 -+#define OR_UPM_AM_SHIFT 15 -+#define OR_UPM_XAM 0x00006000 -+#define OR_UPM_XAM_SHIFT 13 -+#define OR_UPM_BCTLD 0x00001000 -+#define OR_UPM_BCTLD_SHIFT 12 -+#define OR_UPM_BI 0x00000100 -+#define OR_UPM_BI_SHIFT 8 -+#define OR_UPM_TRLX 0x00000004 -+#define OR_UPM_TRLX_SHIFT 2 -+#define OR_UPM_EHTR 0x00000002 -+#define OR_UPM_EHTR_SHIFT 1 -+#define OR_UPM_EAD 0x00000001 -+#define OR_UPM_EAD_SHIFT 0 -+ -+#define OR_SDRAM_AM 0xFFFF8000 -+#define OR_SDRAM_AM_SHIFT 15 -+#define OR_SDRAM_XAM 0x00006000 -+#define OR_SDRAM_XAM_SHIFT 13 -+#define OR_SDRAM_COLS 0x00001C00 -+#define OR_SDRAM_COLS_SHIFT 10 -+#define OR_SDRAM_ROWS 0x000001C0 -+#define OR_SDRAM_ROWS_SHIFT 6 -+#define OR_SDRAM_PMSEL 0x00000020 -+#define OR_SDRAM_PMSEL_SHIFT 5 -+#define OR_SDRAM_EAD 0x00000001 -+#define OR_SDRAM_EAD_SHIFT 0 -+ -+#define OR_FCM_AM 0xFFFF8000 -+#define OR_FCM_AM_SHIFT 15 -+#define OR_FCM_BCTLD 0x00001000 -+#define OR_FCM_BCTLD_SHIFT 12 -+#define OR_FCM_PGS 0x00000400 -+#define OR_FCM_PGS_SHIFT 10 -+#define OR_FCM_CSCT 0x00000200 -+#define OR_FCM_CSCT_SHIFT 9 -+#define OR_FCM_CST 0x00000100 -+#define OR_FCM_CST_SHIFT 8 -+#define OR_FCM_CHT 0x00000080 -+#define OR_FCM_CHT_SHIFT 7 -+#define OR_FCM_SCY 0x00000070 -+#define OR_FCM_SCY_SHIFT 4 -+#define OR_FCM_SCY_1 0x00000010 -+#define OR_FCM_SCY_2 0x00000020 -+#define OR_FCM_SCY_3 0x00000030 -+#define OR_FCM_SCY_4 0x00000040 -+#define OR_FCM_SCY_5 0x00000050 -+#define OR_FCM_SCY_6 0x00000060 -+#define OR_FCM_SCY_7 0x00000070 -+#define OR_FCM_RST 0x00000008 -+#define OR_FCM_RST_SHIFT 3 -+#define OR_FCM_TRLX 0x00000004 -+#define OR_FCM_TRLX_SHIFT 2 -+#define OR_FCM_EHTR 0x00000002 -+#define OR_FCM_EHTR_SHIFT 1 -+} lbus_bank_t; -+ -+typedef struct lbus83xx { -+ lbus_bank_t bank[8]; -+ u8 res0[0x28]; -+ u32 mar; /**< UPM Address Register */ -+ u8 res1[0x4]; -+ u32 mamr; /**< UPMA Mode Register */ -+ u32 mbmr; /**< UPMB Mode Register */ -+ u32 mcmr; /**< UPMC Mode Register */ -+ u8 res2[0x8]; -+ u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ -+ u32 mdr; /**< UPM Data Register */ -+ u8 res3[0x4]; -+ u32 lsor; /**< Special Operation Initiation Register */ -+ u32 lsdmr; /**< SDRAM Mode Register */ -+ u8 res4[0x8]; -+ u32 lurt; /**< UPM Refresh Timer */ -+ u32 lsrt; /**< SDRAM Refresh Timer */ -+ u8 res5[0x8]; -+ u32 ltesr; /**< Transfer Error Status Register */ -+#define LTESR_BM 0x80000000 -+#define LTESR_FCT 0x40000000 -+#define LTESR_PAR 0x20000000 -+#define LTESR_WP 0x04000000 -+#define LTESR_ATMW 0x00800000 -+#define LTESR_ATMR 0x00400000 -+#define LTESR_CS 0x00080000 -+#define LTESR_CC 0x00000001 -+ u32 ltedr; /**< Transfer Error Disable Register */ -+ u32 lteir; /**< Transfer Error Interrupt Register */ -+ u32 lteatr; /**< Transfer Error Attributes Register */ -+ u32 ltear; /**< Transfer Error Address Register */ -+ u8 res6[0xC]; -+ u32 lbcr; /**< Configuration Register */ -+#define LBCR_LDIS 0x80000000 -+#define LBCR_LDIS_SHIFT 31 -+#define LBCR_BCTLC 0x00C00000 -+#define LBCR_BCTLC_SHIFT 22 -+#define LBCR_AHD 0x00200000 -+#define LBCR_LPBSE 0x00020000 -+#define LBCR_LPBSE_SHIFT 17 -+#define LBCR_EPAR 0x00010000 -+#define LBCR_EPAR_SHIFT 16 -+#define LBCR_BMT 0x0000FF00 -+#define LBCR_BMT_SHIFT 8 -+#define LBCR_INIT 0x00040000 -+ u32 lcrr; /**< Clock Ratio Register */ -+#define LCRR_DBYP 0x80000000 -+#define LCRR_DBYP_SHIFT 31 -+#define LCRR_BUFCMDC 0x30000000 -+#define LCRR_BUFCMDC_SHIFT 28 -+#define LCRR_ECL 0x03000000 -+#define LCRR_ECL_SHIFT 24 -+#define LCRR_EADC 0x00030000 -+#define LCRR_EADC_SHIFT 16 -+#define LCRR_CLKDIV 0x0000000F -+#define LCRR_CLKDIV_SHIFT 0 -+ u8 res7[0x8]; -+ u32 fmr; /**< Flash Mode Register */ -+#define FMR_CWTO 0x0000F000 -+#define FMR_CWTO_SHIFT 12 -+#define FMR_BOOT 0x00000800 -+#define FMR_ECCM 0x00000100 -+#define FMR_AL 0x00000030 -+#define FMR_AL_SHIFT 4 -+#define FMR_OP 0x00000003 -+#define FMR_OP_SHIFT 0 -+ u32 fir; /**< Flash Instruction Register */ -+#define FIR_OP0 0xF0000000 -+#define FIR_OP0_SHIFT 28 -+#define FIR_OP1 0x0F000000 -+#define FIR_OP1_SHIFT 24 -+#define FIR_OP2 0x00F00000 -+#define FIR_OP2_SHIFT 20 -+#define FIR_OP3 0x000F0000 -+#define FIR_OP3_SHIFT 16 -+#define FIR_OP4 0x0000F000 -+#define FIR_OP4_SHIFT 12 -+#define FIR_OP5 0x00000F00 -+#define FIR_OP5_SHIFT 8 -+#define FIR_OP6 0x000000F0 -+#define FIR_OP6_SHIFT 4 -+#define FIR_OP7 0x0000000F -+#define FIR_OP7_SHIFT 0 -+#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ -+#define FIR_OP_CA 0x1 /* Issue current column address */ -+#define FIR_OP_PA 0x2 /* Issue current block+page address */ -+#define FIR_OP_UA 0x3 /* Issue user defined address */ -+#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ -+#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ -+#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ -+#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ -+#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ -+#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ -+#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ -+#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ -+#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ -+#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ -+#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ -+#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */ -+ u32 fcr; /**< Flash Command Register */ -+#define FCR_CMD0 0xFF000000 -+#define FCR_CMD0_SHIFT 24 -+#define FCR_CMD1 0x00FF0000 -+#define FCR_CMD1_SHIFT 16 -+#define FCR_CMD2 0x0000FF00 -+#define FCR_CMD2_SHIFT 8 -+#define FCR_CMD3 0x000000FF -+#define FCR_CMD3_SHIFT 0 -+ u32 fbar; /**< Flash Block Address Register */ -+#define FBAR_BLK 0x00FFFFFF -+ u32 fpar; /**< Flash Page Address Register */ -+#define FPAR_SP_PI 0x00007C00 -+#define FPAR_SP_PI_SHIFT 10 -+#define FPAR_SP_MS 0x00000200 -+#define FPAR_SP_CI 0x000001FF -+#define FPAR_SP_CI_SHIFT 0 -+#define FPAR_LP_PI 0x0003F000 -+#define FPAR_LP_PI_SHIFT 12 -+#define FPAR_LP_MS 0x00000800 -+#define FPAR_LP_CI 0x000007FF -+#define FPAR_LP_CI_SHIFT 0 -+ u32 fbcr; /**< Flash Byte Count Register */ -+#define FBCR_BC 0x00000FFF -+ u8 res11[0x8]; -+ u8 res8[0xF00]; -+} lbus83xx_t; -+ -+struct platform_fsl_nand_chip { -+ const char *name; -+ int nr_chips; -+ const char *partitions_str; -+ unsigned int options; -+}; -+ -+/* Setting this option prevents the command line from being parsed -+ * for MTD partitions. */ -+#define FSL_ELBC_NO_CMDLINE_PARTITIONS 0x10000000 -+ -+#endif /* __FSL_ELBC__ */ -+#endif /* __KERNEL__ */ |