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authorKoen Kooi <koen@openembedded.org>2007-08-30 14:50:58 +0000
committerKoen Kooi <koen@openembedded.org>2007-08-30 14:50:58 +0000
commitb026cba70e6ddba33680f90c2693738b7c19a9b7 (patch)
tree9018106d6778cb88386c852940d617e0c5d99152 /packages/gcc
parent634f80151cba377aedff02a302f44eaa5b52af7c (diff)
gcc 4.2.1: add patches for maverick crunch on ep93xx (That's an FPU)
Diffstat (limited to 'packages/gcc')
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-20000320.patch11
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-32bit-disable.patch85
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable-4.2.0.patch169
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable0.patch47
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-and-or.patch67
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-cfcvt64-disable.patch19
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-cfcvtds-disable.patch32
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-cirrus-bugfixes.patch573
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-compare-geu.patch48
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-compare-unordered.patch98
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-compare-unordered.patch-z-eq98
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-compare.patch400
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-compare.patch-z-eq400
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-dominance.patch12
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-eabi-ieee754-div.patch139
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-eabi-ieee754.patch100
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-eabi.patch64
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-floatsi-disable-single.patch38
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-floatsi-disable.patch61
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-floatunsidf.patch37
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-fp_consts.patch13
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-neg.patch30
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-neg2.patch25
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-offset.patch20
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-predicates.patch20
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-predicates2.patch10
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-predicates3.patch116
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-saveregs.patch153
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-scc.patch38
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-truncsi-disable-new.patch33
-rw-r--r--packages/gcc/gcc-4.2.1/arm-crunch-truncsi-disable.patch56
-rw-r--r--packages/gcc/gcc-cross_4.2.1.bb2
-rw-r--r--packages/gcc/gcc_4.2.1.bb19
33 files changed, 3031 insertions, 2 deletions
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-20000320.patch b/packages/gcc/gcc-4.2.1/arm-crunch-20000320.patch
new file mode 100644
index 0000000000..3fb0da7670
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-20000320.patch
@@ -0,0 +1,11 @@
+--- gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c.original 2007-06-07 16:33:44.000000000 +1000
++++ gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c 2007-06-07 16:34:05.000000000 +1000
+@@ -49,7 +49,7 @@
+ exit (0);
+
+ c(0x3690000000000000ULL, 0x00000000U);
+-#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__)
++#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__) && ! (defined __MAVERICK__)
+ /* The ARM always stores FP numbers in big-wordian format,
+ even when running in little-byteian mode. */
+ c(0x0000000136900000ULL, 0x00000001U);
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-32bit-disable.patch b/packages/gcc/gcc-4.2.1/arm-crunch-32bit-disable.patch
new file mode 100644
index 0000000000..88eaee322d
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-32bit-disable.patch
@@ -0,0 +1,85 @@
+--- gcc-4.1.2/gcc/config/arm/cirrus.md-integer 2007-06-15 09:01:37.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 09:04:45.000000000 +1000
+@@ -149,7 +149,7 @@
+ (match_operand:SI 1 "cirrus_fp_register" "0")
+ (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
+ (match_operand:SI 3 "cirrus_fp_register" "v"))))]
+- "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfmsc32%?\\t%V0, %V2, %V3"
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
+@@ -305,7 +305,7 @@
+ [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
+ (float:SF (match_operand:SI 1 "s_register_operand" "r")))
+ (clobber (match_scratch:DF 2 "=v"))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
+ [(set_attr "length" "8")
+ (set_attr "cirrus" "move")]
+@@ -315,7 +315,7 @@
+ [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
+ (float:DF (match_operand:SI 1 "s_register_operand" "r")))
+ (clobber (match_scratch:DF 2 "=v"))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
+ [(set_attr "length" "8")
+ (set_attr "cirrus" "move")]
+@@ -339,7 +339,7 @@
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v"))))
+ (clobber (match_scratch:DF 2 "=v"))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
+ [(set_attr "length" "8")
+ (set_attr "cirrus" "normal")]
+@@ -349,7 +349,7 @@
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v"))))
+ (clobber (match_scratch:DF 2 "=v"))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
+ [(set_attr "length" "8")
+ (set_attr "cirrus" "normal")]
+--- gcc-4.1.2/gcc/config/arm/arm.md-trunc 2007-06-15 10:56:13.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 11:01:22.000000000 +1000
+@@ -3130,7 +3130,7 @@
+ (float:SF (match_operand:SI 1 "s_register_operand" "")))]
+ "TARGET_ARM && TARGET_HARD_FLOAT"
+ "
+- if (TARGET_MAVERICK)
++ if (TARGET_MAVERICK && 0)
+ {
+ emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
+ DONE;
+@@ -3142,7 +3142,7 @@
+ (float:DF (match_operand:SI 1 "s_register_operand" "")))]
+ "TARGET_ARM && TARGET_HARD_FLOAT"
+ "
+- if (TARGET_MAVERICK)
++ if (TARGET_MAVERICK && 0)
+ {
+ emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
+ DONE;
+@@ -3154,7 +3154,7 @@
+ (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))]
+ "TARGET_ARM && TARGET_HARD_FLOAT"
+ "
+- if (TARGET_MAVERICK)
++ if (TARGET_MAVERICK && 0)
+ {
+ if (!cirrus_fp_register (operands[0], SImode))
+ operands[0] = force_reg (SImode, operands[0]);
+@@ -3170,7 +3170,7 @@
+ (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))]
+ "TARGET_ARM && TARGET_HARD_FLOAT"
+ "
+- if (TARGET_MAVERICK)
++ if (TARGET_MAVERICK && 0)
+ {
+ if (!cirrus_fp_register (operands[1], DFmode))
+ operands[1] = force_reg (DFmode, operands[0]);
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable-4.2.0.patch b/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable-4.2.0.patch
new file mode 100644
index 0000000000..60b17852bd
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable-4.2.0.patch
@@ -0,0 +1,169 @@
+--- gcc-4.1.2/gcc/config/arm/cirrus.md-integer 2007-06-15 09:01:37.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 09:04:45.000000000 +1000
+@@ -34,7 +34,7 @@
+ [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
+ (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
+ (match_operand:DI 2 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfadd64%?\\t%V0, %V1, %V2"
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
+@@ -74,7 +74,7 @@
+ [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
+ (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
+ (match_operand:DI 2 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfsub64%?\\t%V0, %V1, %V2"
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "normal")]
+@@ -124,7 +124,7 @@
+ [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
+ (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v")
+ (match_operand:DI 1 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfmul64%?\\t%V0, %V1, %V2"
+ [(set_attr "type" "mav_dmult")
+ (set_attr "cirrus" "normal")]
+@@ -206,7 +206,7 @@
+ [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
+ (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
+ (match_operand:SI 2 "register_operand" "r")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfrshl64%?\\t%V1, %V0, %s2"
+ [(set_attr "cirrus" "normal")]
+ )
+@@ -215,7 +215,7 @@
+ [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
+ (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
+ (match_operand:SI 2 "cirrus_shift_const" "")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfsh64%?\\t%V0, %V1, #%s2"
+ [(set_attr "cirrus" "normal")]
+ )
+@@ -224,7 +224,7 @@
+ [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
+ (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v")
+ (match_operand:SI 2 "cirrus_shift_const" "")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfsh64%?\\t%V0, %V1, #-%s2"
+ [(set_attr "cirrus" "normal")]
+ )
+@@ -232,7 +232,7 @@
+ (define_insn "*cirrus_absdi2"
+ [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
+ (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfabs64%?\\t%V0, %V1"
+ [(set_attr "cirrus" "normal")]
+ )
+@@ -238,11 +238,12 @@
+ )
+
+ ;; This doesn't really clobber ``cc''. Fixme: aldyh.
++;; maybe buggy?
+ (define_insn "*cirrus_negdi2"
+ [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
+ (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v")))
+ (clobber (reg:CC CC_REGNUM))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfneg64%?\\t%V0, %V1"
+ [(set_attr "cirrus" "normal")]
+ )
+@@ -324,14 +324,14 @@
+ (define_insn "floatdisf2"
+ [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
+ (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfcvt64s%?\\t%V0, %V1"
+ [(set_attr "cirrus" "normal")])
+
+ (define_insn "floatdidf2"
+ [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
+ (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfcvt64d%?\\t%V0, %V1"
+ [(set_attr "cirrus" "normal")])
+
+@@ -376,7 +376,7 @@
+ (define_insn "*cirrus_arm_movdi"
+ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
+ (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "*
+ {
+ switch (which_alternative)
+--- gcc-4.1.2/gcc/config/arm/arm.md-64 2007-06-15 11:37:42.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 11:40:45.000000000 +1000
+@@ -357,7 +357,7 @@
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_EITHER"
+ "
+- if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK && 0)
+ {
+ if (!cirrus_fp_register (operands[0], DImode))
+ operands[0] = force_reg (DImode, operands[0]);
+@@ -393,7 +393,7 @@
+ (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
+ (match_operand:DI 2 "s_register_operand" "r, 0")))
+ (clobber (reg:CC CC_REGNUM))]
+- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
++ "TARGET_ARM"
+ "#"
+ "TARGET_ARM && reload_completed"
+ [(parallel [(set (reg:CC_C CC_REGNUM)
+@@ -421,7 +421,7 @@
+ (match_operand:SI 2 "s_register_operand" "r,r"))
+ (match_operand:DI 1 "s_register_operand" "r,0")))
+ (clobber (reg:CC CC_REGNUM))]
+- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
++ "TARGET_ARM"
+ "#"
+ "TARGET_ARM && reload_completed"
+ [(parallel [(set (reg:CC_C CC_REGNUM)
+@@ -450,7 +450,7 @@
+ (match_operand:SI 2 "s_register_operand" "r,r"))
+ (match_operand:DI 1 "s_register_operand" "r,0")))
+ (clobber (reg:CC CC_REGNUM))]
+- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
++ "TARGET_ARM"
+ "#"
+ "TARGET_ARM && reload_completed"
+ [(parallel [(set (reg:CC_C CC_REGNUM)
+@@ -838,7 +838,7 @@
+ if (TARGET_HARD_FLOAT && TARGET_MAVERICK
+ && TARGET_ARM
+ && cirrus_fp_register (operands[0], DImode)
+- && cirrus_fp_register (operands[1], DImode))
++ && cirrus_fp_register (operands[1], DImode) && 0)
+ {
+ emit_insn (gen_cirrus_subdi3 (operands[0], operands[1], operands[2]));
+ DONE;
+@@ -2599,7 +2599,7 @@
+ values to iwmmxt regs and back. */
+ FAIL;
+ }
+- else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK))
++ else if (!TARGET_REALLY_IWMMXT)
+ FAIL;
+ "
+ )
+@@ -4215,7 +4215,6 @@
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r")
+ (match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))]
+ "TARGET_THUMB
+- && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
+ && ( register_operand (operands[0], DImode)
+ || register_operand (operands[1], DImode))"
+ "*
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable0.patch b/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable0.patch
new file mode 100644
index 0000000000..95abf68a60
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-64bit-disable0.patch
@@ -0,0 +1,47 @@
+diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md
+--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md 2006-09-28 03:10:22.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-15 09:53:21.000000000 +1000
+@@ -6865,10 +6877,12 @@
+ )
+
+ ;; Cirrus DI compare instruction
++;; This is disabled and left go through ARM core registers, because currently
++;; Crunch coprocessor does only signed comparison.
+ (define_expand "cmpdi"
+ [(match_operand:DI 0 "cirrus_fp_register" "")
+ (match_operand:DI 1 "cirrus_fp_register" "")]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0"
+ "{
+ arm_compare_op0 = operands[0];
+ arm_compare_op1 = operands[1];
+@@ -6879,7 +6893,7 @@
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_operand:DI 0 "cirrus_fp_register" "v")
+ (match_operand:DI 1 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0"
+ "cfcmp64%?\\tr15, %V0, %V1"
+ [(set_attr "type" "mav_farith")
+ (set_attr "cirrus" "compare")]
+@@ -10105,6 +10119,7 @@
+ [(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_PROLOGUE_USE)]
+ ""
+ "%@ %0 needed for prologue"
++ [(set_attr "length" "0")]
+ )
+
+
+diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md gcc-4.1.2/gcc/config/arm/cirrus.md
+--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md 2005-06-25 11:22:41.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-05-15 09:55:29.000000000 +1000
+@@ -348,7 +348,8 @@
+ (clobber (match_scratch:DF 2 "=v"))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
+- [(set_attr "length" "8")]
++ [(set_attr "length" "8")
++ (set_attr "cirrus" "normal")]
+ )
+
+ (define_insn "*cirrus_truncdfsf2"
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-and-or.patch b/packages/gcc/gcc-4.2.1/arm-crunch-and-or.patch
new file mode 100644
index 0000000000..24357d316e
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-and-or.patch
@@ -0,0 +1,67 @@
+--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-13 17:16:38.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-13 17:35:19.000000000 +1000
+@@ -8455,7 +8455,7 @@
+ (and:SI (match_operator:SI 1 "arm_comparison_operator"
+ [(match_operand 3 "cc_register" "") (const_int 0)])
+ (match_operand:SI 2 "s_register_operand" "r")))]
+- "TARGET_ARM"
++ "TARGET_ARM && !TARGET_MAVERICK"
+ "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
+ [(set_attr "conds" "use")
+ (set_attr "length" "8")]
+@@ -8466,7 +8466,7 @@
+ (ior:SI (match_operator:SI 2 "arm_comparison_operator"
+ [(match_operand 3 "cc_register" "") (const_int 0)])
+ (match_operand:SI 1 "s_register_operand" "0,?r")))]
+- "TARGET_ARM"
++ "TARGET_ARM && !TARGET_MAVERICK"
+ "@
+ orr%d2\\t%0, %1, #1
+ mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
+@@ -8734,7 +8734,8 @@
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_ARM
+ && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y)
+- != CCmode)"
++ != CCmode)
++ && !TARGET_MAVERICK"
+ "#"
+ "TARGET_ARM && reload_completed"
+ [(set (match_dup 7)
+@@ -8765,7 +8766,7 @@
+ (set (match_operand:SI 7 "s_register_operand" "=r")
+ (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
+ (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
+- "TARGET_ARM"
++ "TARGET_ARM && !TARGET_MAVERICK"
+ "#"
+ "TARGET_ARM && reload_completed"
+ [(set (match_dup 0)
+@@ -8790,7 +8791,8 @@
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_ARM
+ && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
+- != CCmode)"
++ != CCmode)
++ && !TARGET_MAVERICK"
+ "#"
+ "TARGET_ARM && reload_completed
+ && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
+@@ -8823,7 +8825,7 @@
+ (set (match_operand:SI 7 "s_register_operand" "=r")
+ (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
+ (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
+- "TARGET_ARM"
++ "TARGET_ARM && !TARGET_MAVERICK"
+ "#"
+ "TARGET_ARM && reload_completed"
+ [(set (match_dup 0)
+@@ -8850,7 +8852,7 @@
+ [(match_operand:SI 4 "s_register_operand" "r,r,r")
+ (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")])))
+ (clobber (reg:CC CC_REGNUM))]
+- "TARGET_ARM
++ "TARGET_ARM && !TARGET_MAVERICK
+ && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
+ == CCmode)"
+ "#"
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-cfcvt64-disable.patch b/packages/gcc/gcc-4.2.1/arm-crunch-cfcvt64-disable.patch
new file mode 100644
index 0000000000..f9280b18b5
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-cfcvt64-disable.patch
@@ -0,0 +1,19 @@
+--- gcc-4.2.0/gcc/config/arm/cirrus.md-original 2007-06-25 15:32:01.000000000 +1000
++++ gcc-4.2.0/gcc/config/arm/cirrus.md 2007-06-25 15:32:14.000000000 +1000
+@@ -325,14 +325,14 @@
+ (define_insn "floatdisf2"
+ [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
+ (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfcvt64s%?\\t%V0, %V1"
+ [(set_attr "cirrus" "normal")])
+
+ (define_insn "floatdidf2"
+ [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
+ (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfcvt64d%?\\t%V0, %V1"
+ [(set_attr "cirrus" "normal")])
+
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-cfcvtds-disable.patch b/packages/gcc/gcc-4.2.1/arm-crunch-cfcvtds-disable.patch
new file mode 100644
index 0000000000..ec09ea16a1
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-cfcvtds-disable.patch
@@ -0,0 +1,32 @@
+--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-15 10:06:24.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 10:07:21.000000000 +1000
+@@ -355,11 +355,12 @@
+ (set_attr "cirrus" "normal")]
+ )
+
++; appears to be buggy - causes 20000320-1.c to fail in execute/ieee
+ (define_insn "*cirrus_truncdfsf2"
+ [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
+ (float_truncate:SF
+ (match_operand:DF 1 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfcvtds%?\\t%V0, %V1"
+ [(set_attr "cirrus" "normal")]
+ )
+--- gcc-4.1.2/gcc/config/arm/arm.md-truncdfsf2 2007-06-15 10:25:43.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 10:27:01.000000000 +1000
+@@ -3181,11 +3181,12 @@
+
+ ;; Truncation insns
+
++;; Maverick Crunch truncdfsf2 is buggy - see cirrus.md
+ (define_expand "truncdfsf2"
+ [(set (match_operand:SF 0 "s_register_operand" "")
+ (float_truncate:SF
+ (match_operand:DF 1 "s_register_operand" "")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ ""
+ )
+
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-cirrus-bugfixes.patch b/packages/gcc/gcc-4.2.1/arm-crunch-cirrus-bugfixes.patch
new file mode 100644
index 0000000000..cb0af8546d
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-cirrus-bugfixes.patch
@@ -0,0 +1,573 @@
+diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c gcc-4.1.2/gcc/config/arm/arm.c
+--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c 2007-05-09 16:32:29.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-15 09:39:41.000000000 +1000
+@@ -4,6 +4,7 @@
+ Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
+ and Martin Simmons (@harleqn.co.uk).
+ More major hacks by Richard Earnshaw (rearnsha@arm.com).
++ Cirrus Crunch bugfixes by Vladimir Ivanov (vladit@nucleusys.com)
+
+ This file is part of GCC.
+
+@@ -131,9 +132,17 @@
+ static bool arm_xscale_rtx_costs (rtx, int, int, int *);
+ static bool arm_9e_rtx_costs (rtx, int, int, int *);
+ static int arm_address_cost (rtx);
+-static bool arm_memory_load_p (rtx);
++// static bool arm_memory_load_p (rtx);
+ static bool arm_cirrus_insn_p (rtx);
+-static void cirrus_reorg (rtx);
++// static void cirrus_reorg (rtx);
++static bool arm_mem_access_p (rtx);
++static bool cirrus_dest_regn_p (rtx, int);
++static rtx cirrus_prev_next_mach_insn (rtx, int *, int);
++static rtx cirrus_prev_mach_insn (rtx, int *);
++static rtx cirrus_next_mach_insn (rtx, int *);
++static void cirrus_reorg_branch (rtx);
++static void cirrus_reorg_bug1 (rtx);
++static void cirrus_reorg_bug10_12 (rtx);
+ static void arm_init_builtins (void);
+ static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
+ static void arm_init_iwmmxt_builtins (void);
+@@ -5399,41 +5412,6 @@
+ || TREE_CODE (valtype) == COMPLEX_TYPE));
+ }
+
+-/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
+- Use by the Cirrus Maverick code which has to workaround
+- a hardware bug triggered by such instructions. */
+-static bool
+-arm_memory_load_p (rtx insn)
+-{
+- rtx body, lhs, rhs;;
+-
+- if (insn == NULL_RTX || GET_CODE (insn) != INSN)
+- return false;
+-
+- body = PATTERN (insn);
+-
+- if (GET_CODE (body) != SET)
+- return false;
+-
+- lhs = XEXP (body, 0);
+- rhs = XEXP (body, 1);
+-
+- lhs = REG_OR_SUBREG_RTX (lhs);
+-
+- /* If the destination is not a general purpose
+- register we do not have to worry. */
+- if (GET_CODE (lhs) != REG
+- || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
+- return false;
+-
+- /* As well as loads from memory we also have to react
+- to loads of invalid constants which will be turned
+- into loads from the minipool. */
+- return (GET_CODE (rhs) == MEM
+- || GET_CODE (rhs) == SYMBOL_REF
+- || note_invalid_constants (insn, -1, false));
+-}
+-
+ /* Return TRUE if INSN is a Cirrus instruction. */
+ static bool
+ arm_cirrus_insn_p (rtx insn)
+@@ -5452,124 +5433,218 @@
+ return attr != CIRRUS_NOT;
+ }
+
+-/* Cirrus reorg for invalid instruction combinations. */
+-static void
+-cirrus_reorg (rtx first)
++/* Return TRUE if ISN does memory access. */
++static bool
++arm_mem_access_p (rtx insn)
+ {
+- enum attr_cirrus attr;
+- rtx body = PATTERN (first);
+- rtx t;
+- int nops;
++ enum attr_type attr;
+
+- /* Any branch must be followed by 2 non Cirrus instructions. */
+- if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
+- {
+- nops = 0;
+- t = next_nonnote_insn (first);
++ /* get_attr aborts on USE and CLOBBER. */
++ if (!insn
++ || GET_CODE (insn) != INSN
++ || GET_CODE (PATTERN (insn)) == USE
++ || GET_CODE (PATTERN (insn)) == CLOBBER)
++ return 0;
+
+- if (arm_cirrus_insn_p (t))
+- ++ nops;
++ attr = get_attr_type (insn);
+
+- if (arm_cirrus_insn_p (next_nonnote_insn (t)))
+- ++ nops;
++ return attr == TYPE_LOAD_BYTE
++ || attr == TYPE_LOAD1 || attr == TYPE_LOAD2 || attr == TYPE_LOAD3 || attr == TYPE_LOAD4
++ || attr == TYPE_F_CVT
++ || attr == TYPE_F_MEM_R || attr == TYPE_R_MEM_F || attr == TYPE_F_2_R || attr == TYPE_R_2_F
++ || attr == TYPE_F_LOAD || attr == TYPE_F_LOADS || attr == TYPE_F_LOADD
++ || attr == TYPE_F_STORE || attr == TYPE_F_STORES || attr == TYPE_F_STORED
++ || attr == TYPE_STORE1 || attr == TYPE_STORE2 || attr == TYPE_STORE3 || attr == TYPE_STORE4;
++
++}
+
+- while (nops --)
+- emit_insn_after (gen_nop (), first);
++/* Return TRUE if destination is certain Cirrus register. */
++static bool
++cirrus_dest_regn_p (rtx body, int regn)
++{
++ rtx lhs;
++ int reg;
++ lhs = XEXP (body, 0);
++ if (GET_CODE (lhs) != REG)
++ return 0;
+
+- return;
+- }
++ reg = REGNO (lhs);
++ if (REGNO_REG_CLASS (reg) != CIRRUS_REGS)
++ return 0;
+
+- /* (float (blah)) is in parallel with a clobber. */
+- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
+- body = XVECEXP (body, 0, 0);
++ return reg == regn;
++}
++
++/* Get previous/next machine instruction during Cirrus workaround scans.
++ Assume worst case (for the purpose of Cirrus workarounds)
++ for JUMP / CALL instructions. */
++static rtx
++cirrus_prev_next_mach_insn (rtx insn, int *len, int next)
++{
++ rtx t;
++ int l = 0;
+
+- if (GET_CODE (body) == SET)
++ /* It seems that we can count only on INSN length. */
++ for ( ; ; )
+ {
+- rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
++ if (next)
++ insn = NEXT_INSN (insn);
++ else
++ insn = PREV_INSN (insn);
++ if (!insn)
++ break;
+
+- /* cfldrd, cfldr64, cfstrd, cfstr64 must
+- be followed by a non Cirrus insn. */
+- if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
+- {
+- if (arm_cirrus_insn_p (next_nonnote_insn (first)))
+- emit_insn_after (gen_nop (), first);
++ if (GET_CODE (insn) == INSN)
++ {
++ l = get_attr_length (insn) / 4;
++ if (l)
++ break;
++ }
++ else if (GET_CODE (insn) == JUMP_INSN)
++ {
++ l = 1;
++ t = is_jump_table (insn);
++ if (t)
++ l += get_jump_table_size (t) / 4;
++ break;
++ }
++ else if (GET_CODE (insn) == CALL_INSN)
++ {
++ l = 1;
++ break;
++ }
++ }
+
+- return;
+- }
+- else if (arm_memory_load_p (first))
+- {
+- unsigned int arm_regno;
++ if (len)
++ *len = l;
+
+- /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
+- ldr/cfmv64hr combination where the Rd field is the same
+- in both instructions must be split with a non Cirrus
+- insn. Example:
+-
+- ldr r0, blah
+- nop
+- cfmvsr mvf0, r0. */
+-
+- /* Get Arm register number for ldr insn. */
+- if (GET_CODE (lhs) == REG)
+- arm_regno = REGNO (lhs);
+- else
+- {
+- gcc_assert (GET_CODE (rhs) == REG);
+- arm_regno = REGNO (rhs);
+- }
++ return insn;
++}
+
+- /* Next insn. */
+- first = next_nonnote_insn (first);
++static rtx
++cirrus_prev_mach_insn (rtx insn, int *len)
++{
++ return cirrus_prev_next_mach_insn (insn, len, 0);
++}
+
+- if (! arm_cirrus_insn_p (first))
+- return;
++static rtx
++cirrus_next_mach_insn (rtx insn, int *len)
++{
++ return cirrus_prev_next_mach_insn (insn, len, 1);
++}
+
+- body = PATTERN (first);
++/* Cirrus reorg for branch slots. */
++static void
++cirrus_reorg_branch (rtx insn)
++{
++ rtx t;
++ int nops, l;
+
+- /* (float (blah)) is in parallel with a clobber. */
+- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
+- body = XVECEXP (body, 0, 0);
+-
+- if (GET_CODE (body) == FLOAT)
+- body = XEXP (body, 0);
+-
+- if (get_attr_cirrus (first) == CIRRUS_MOVE
+- && GET_CODE (XEXP (body, 1)) == REG
+- && arm_regno == REGNO (XEXP (body, 1)))
+- emit_insn_after (gen_nop (), first);
++ /* TODO: handle jump-tables. */
++ t = is_jump_table (insn);
++ if (t)
++ return;
++
++ /* Any branch must be followed by 2 non Cirrus instructions. */
++ t = insn;
++ for (nops = 2; nops > 0; )
++ {
++ if (!cirrus_next_mach_insn (t, 0))
++ {
++ insn = t;
++ break;
++ }
++ t = cirrus_next_mach_insn (t, &l);
++ if (arm_cirrus_insn_p (t))
++ break;
++ nops -= l;
+
+- return;
+- }
+ }
+
+- /* get_attr cannot accept USE or CLOBBER. */
+- if (!first
+- || GET_CODE (first) != INSN
+- || GET_CODE (PATTERN (first)) == USE
+- || GET_CODE (PATTERN (first)) == CLOBBER)
+- return;
++ while (nops-- > 0)
++ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
++}
+
+- attr = get_attr_cirrus (first);
++/* Cirrus reorg for bug #1 (cirrus + cfcmpxx). */
++static void
++cirrus_reorg_bug1 (rtx insn)
++{
++ rtx body = PATTERN (insn), body2;
++ rtx t;
++ int i, nops, l;
++ enum attr_cirrus attr;
+
+- /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
+- must be followed by a non-coprocessor instruction. */
+- if (attr == CIRRUS_COMPARE)
++ /* Check if destination or clobber is Cirrus register. */
++ if (GET_CODE (body) == PARALLEL)
+ {
+- nops = 0;
+-
+- t = next_nonnote_insn (first);
++ for (i = 0; i < XVECLEN (body, 0); i++)
++ {
++ body2 = XVECEXP (body, 0, i);
++ if (GET_CODE (body2) == SET)
++ {
++ if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM))
++ {
++ nops = 5;
++ goto fix;
++ }
++ }
++ else if (GET_CODE (body2) == CLOBBER)
++ {
++ if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM))
++ {
++ nops = 4;
++ goto fix;
++ }
++ }
++ }
++ }
++ else if (GET_CODE (body) == SET)
++ {
++ if (cirrus_dest_regn_p (body, LAST_CIRRUS_FP_REGNUM))
++ {
++ nops = 5;
++ goto fix;
++ }
++ }
++ return;
+
+- if (arm_cirrus_insn_p (t))
+- ++ nops;
++fix:
++ t = insn;
++ for ( ; nops > 0; )
++ {
++ t = cirrus_next_mach_insn (t, &l);
++ if (!t)
++ break;
++ if (GET_CODE (t) == JUMP_INSN
++ || GET_CODE (t) == CALL_INSN)
++ {
++ nops -= l;
++ break;
++ }
++ else if (arm_cirrus_insn_p (t))
++ {
++ attr = get_attr_cirrus (t);
++ if (attr == CIRRUS_COMPARE)
++ break;
++ }
++ nops -= l;
++ }
+
+- if (arm_cirrus_insn_p (next_nonnote_insn (t)))
+- ++ nops;
++ while (nops-- > 0)
++ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
++}
+
+- while (nops --)
+- emit_insn_after (gen_nop (), first);
++/* Cirrus reorg for bugs #10 and #12 (data aborts). */
++static void
++cirrus_reorg_bug10_12 (rtx insn)
++{
++ rtx t;
+
+- return;
+- }
++ t = cirrus_next_mach_insn (insn, 0);
++ if (arm_cirrus_insn_p (t))
++ if (TARGET_CIRRUS_D0 ||
++ get_attr_cirrus (t) == CIRRUS_DOUBLE)
++ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
+ }
+
+ /* Return TRUE if X references a SYMBOL_REF. */
+@@ -7727,7 +7796,7 @@
+ {
+ Mnode * mp;
+ Mnode * nmp;
+- int align64 = 0;
++ int align64 = 0, stuffnop = 0;
+
+ if (ARM_DOUBLEWORD_ALIGN)
+ for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
+@@ -7742,8 +7811,27 @@
+ ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
+ INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
+
++ /* Check if branch before minipool is already stuffed with nops. */
++ if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1)
++ {
++ rtx t;
++
++ t = prev_active_insn (scan);
++ if (GET_CODE (t) != INSN
++ || PATTERN (t) != const0_rtx)
++ stuffnop = 1;
++ }
+ scan = emit_label_after (gen_label_rtx (), scan);
+ scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
++ /* Last instruction was branch, so put two non-Cirrus opcodes. */
++ if (stuffnop)
++ {
++#if TARGET_CIRRUS /* This is doubling up on nops, so I don't think this is a good idea */
++ emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
++ emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
++#endif
++ }
++
+ scan = emit_label_after (minipool_vector_label, scan);
+
+ for (mp = minipool_vector_head; mp != NULL; mp = nmp)
+@@ -8151,15 +8239,38 @@
+ gcc_assert (GET_CODE (insn) == NOTE);
+ minipool_pad = 0;
+
++#if TARGET_CIRRUS /* I think this is a double-up */
++ /* Scan all the insn and fix Cirrus issues. */
++ if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1)
++ {
++ rtx t, s;
++
++ for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0))
++ if (arm_mem_access_p (t))
++ cirrus_reorg_bug10_12 (t);
++
++ if (TARGET_CIRRUS_D0)
++ for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0))
++ if (arm_cirrus_insn_p (t))
++ cirrus_reorg_bug1 (t);
++
++ /* Find last insn. */
++ for (t = insn; ; t = s)
++ {
++ s = cirrus_next_mach_insn (t, 0);
++ if (!s)
++ break;
++ }
++ /* Scan backward and fix branches. - WARNING: appears to cause "bad immediate value for offset" problems! */
++ for ( ; t; t = cirrus_prev_mach_insn (t, 0))
++ if (GET_CODE (t) == JUMP_INSN
++ || GET_CODE (t) == CALL_INSN)
++ cirrus_reorg_branch (t);
++ }
++#endif
+ /* Scan all the insns and record the operands that will need fixing. */
+ for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
+ {
+- if (TARGET_CIRRUS_FIX_INVALID_INSNS
+- && (arm_cirrus_insn_p (insn)
+- || GET_CODE (insn) == JUMP_INSN
+- || arm_memory_load_p (insn)))
+- cirrus_reorg (insn);
+-
+ if (GET_CODE (insn) == BARRIER)
+ push_minipool_barrier (insn, address);
+ else if (INSN_P (insn))
+@@ -11755,16 +11910,10 @@
+ || get_attr_conds (this_insn) != CONDS_NOCOND)
+ fail = TRUE;
+
+- /* A conditional cirrus instruction must be followed by
+- a non Cirrus instruction. However, since we
+- conditionalize instructions in this function and by
+- the time we get here we can't add instructions
+- (nops), because shorten_branches() has already been
+- called, we will disable conditionalizing Cirrus
+- instructions to be safe. */
+- if (GET_CODE (scanbody) != USE
+- && GET_CODE (scanbody) != CLOBBER
+- && get_attr_cirrus (this_insn) != CIRRUS_NOT)
++ /* To avoid erratic behaviour, we avoid conditional Cirrus
++ instructions when doing workarounds. */
++ if (arm_cirrus_insn_p(this_insn)
++ && (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1))
+ fail = TRUE;
+ break;
+
+diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.h gcc-4.1.2/gcc/config/arm/arm.h
+--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.h 2005-11-05 01:02:51.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.h 2007-05-15 10:15:05.000000000 +1000
+@@ -5,6 +5,7 @@
+ and Martin Simmons (@harleqn.co.uk).
+ More major hacks by Richard Earnshaw (rearnsha@arm.com)
+ Minor hacks by Nick Clifton (nickc@cygnus.com)
++ Cirrus Crunch fixes by Vladimir Ivanov (vladitx@nucleusys.com)
+
+ This file is part of GCC.
+
+@@ -140,7 +141,9 @@
+ %{msoft-float:%{mhard-float: \
+ %e-msoft-float and -mhard_float may not be used together}} \
+ %{mbig-endian:%{mlittle-endian: \
+- %e-mbig-endian and -mlittle-endian may not be used together}}"
++ %e-mbig-endian and -mlittle-endian may not be used together}} \
++%{mfix-crunch-d0:%{mfix-crunch-d1: \
++ %e-mfix-crunch-d0 and -mfix-crunch-d1 may not be used together}}"
+
+ #ifndef CC1_SPEC
+ #define CC1_SPEC ""
+@@ -179,6 +182,9 @@
+ #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
+ #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
+ #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
++#define TARGET_CIRRUS (arm_arch_cirrus)
++#define TARGET_CIRRUS_D0 0 /* (target_flags & ARM_FLAG_CIRRUS_D0) */
++#define TARGET_CIRRUS_D1 1 /* (target_flags & ARM_FLAG_CIRRUS_D1) */
+ #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
+ #define TARGET_IWMMXT (arm_arch_iwmmxt)
+ #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
+diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.opt gcc-4.1.2/gcc/config/arm/arm.opt
+--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.opt 2005-11-05 01:02:51.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.opt 2007-05-15 10:09:31.000000000 +1000
+@@ -68,6 +68,14 @@
+ Target Report Mask(CIRRUS_FIX_INVALID_INSNS)
+ Cirrus: Place NOPs to avoid invalid instruction combinations
+
++fix-crunch-d0
++Target Report Mask(ARM_FLAG_CIRRUS_D0)
++Cirrus: workarounds for Crunch coprocessor revision D0
++
++fix-crunch-d1
++Target Report Mask(ARM_FLAG_CIRRUS_D1)
++Cirrus: workarounds for Crunch coprocessor revision D1
++
+ mcpu=
+ Target RejectNegative Joined
+ Specify the name of the target CPU
+diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/doc/invoke.texi gcc-4.1.2/gcc/doc/invoke.texi
+--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/doc/invoke.texi 2006-09-26 07:21:58.000000000 +1000
++++ gcc-4.1.2/gcc/doc/invoke.texi 2007-05-15 10:07:04.000000000 +1000
+@@ -408,7 +408,7 @@
+ -msingle-pic-base -mno-single-pic-base @gol
+ -mpic-register=@var{reg} @gol
+ -mnop-fun-dllimport @gol
+--mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol
++-mfix-crunch-d0 -mfix-crunch-d1 @gol
+ -mpoke-function-name @gol
+ -mthumb -marm @gol
+ -mtpcs-frame -mtpcs-leaf-frame @gol
+@@ -7435,17 +7435,12 @@
+ Specify the register to be used for PIC addressing. The default is R10
+ unless stack-checking is enabled, when R9 is used.
+
+-@item -mcirrus-fix-invalid-insns
+-@opindex mcirrus-fix-invalid-insns
+-@opindex mno-cirrus-fix-invalid-insns
+-Insert NOPs into the instruction stream to in order to work around
+-problems with invalid Maverick instruction combinations. This option
+-is only valid if the @option{-mcpu=ep9312} option has been used to
+-enable generation of instructions for the Cirrus Maverick floating
+-point co-processor. This option is not enabled by default, since the
+-problem is only present in older Maverick implementations. The default
+-can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
+-switch.
++@item -mfix-crunch-d0
++@itemx -mfix-crunch-d1
++@opindex mfix-crunch-d0
++@opindex mfix-crunch-d1
++Enable workarounds for the Cirrus MaverickCrunch coprocessor revisions
++D0 and D1 respectively.
+
+ @item -mpoke-function-name
+ @opindex mpoke-function-name
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-compare-geu.patch b/packages/gcc/gcc-4.2.1/arm-crunch-compare-geu.patch
new file mode 100644
index 0000000000..3d27cc1d9d
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-compare-geu.patch
@@ -0,0 +1,48 @@
+--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-08 06:39:41.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-08 06:41:00.000000000 +1000
+@@ -7125,6 +7125,22 @@
+ (set_attr "length" "8")]
+ )
+
++; Special pattern to match GEU for MAVERICK.
++(define_insn "*arm_bgeu"
++ [(set (pc)
++ (if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0))
++ (label_ref (match_operand 0 "" ""))
++ (pc)))]
++ "TARGET_ARM && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE)
++ return \"beq\\t%l0\;bvs\\t%l0\"; else return \"bge\\t%l0\;nop\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "8")]
++)
++
+ ; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0.
+ (define_insn "*arm_bunlt"
+ [(set (pc)
+@@ -7240,6 +7256,22 @@
+ (set_attr "length" "8")]
+ )
+
++; Special pattern to match reversed GEU for MAVERICK.
++(define_insn "*arm_bgeu_reversed"
++ [(set (pc)
++ (if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0))
++ (pc)
++ (label_ref (match_operand 0 "" ""))))]
++ "TARGET_ARM && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "12")]
++)
++
+ ; Special pattern to match reversed UNLT for MAVERICK.
+ (define_insn "*arm_bunlt_reversed"
+ [(set (pc)
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-compare-unordered.patch b/packages/gcc/gcc-4.2.1/arm-crunch-compare-unordered.patch
new file mode 100644
index 0000000000..c4fcdb3746
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-compare-unordered.patch
@@ -0,0 +1,98 @@
+--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-07 14:45:22.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-07 15:13:58.000000000 +1000
+@@ -7001,16 +7001,16 @@
+ (if_then_else (unordered (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0,
+ arm_compare_op1);"
+ )
+
+ (define_expand "bordered"
+ [(set (pc)
+ (if_then_else (ordered (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0,
+ arm_compare_op1);"
+@@ -7141,6 +7141,38 @@
+ (set_attr "length" "8")]
+ )
+
++; Special pattern to match UNORDERED for MAVERICK - UGLY since we need to test for Z=0 && N=0.
++(define_insn "*arm_bunordered"
++ [(set (pc)
++ (if_then_else (unordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
++ (label_ref (match_operand 0 "" ""))
++ (pc)))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "12")]
++)
++
++; Special pattern to match ORDERED for MAVERICK.
++(define_insn "*arm_bordered"
++ [(set (pc)
++ (if_then_else (ordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
++ (label_ref (match_operand 0 "" ""))
++ (pc)))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"beq\\t%l0\;bmi\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "8")]
++)
++
+ (define_insn "*arm_cond_branch"
+ [(set (pc)
+ (if_then_else (match_operator 1 "arm_comparison_operator"
+@@ -7224,6 +7256,37 @@
+ (set_attr "length" "8")]
+ )
+
++; Special pattern to match reversed UNORDERED for MAVERICK.
++(define_insn "*arm_bunordered_reversed"
++ [(set (pc)
++ (if_then_else (unordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
++ (pc)
++ (label_ref (match_operand 0 "" ""))))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"beq\\t%l0\;bmi\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "8")]
++)
++
++; Special pattern to match reversed ORDERED for MAVERICK - UGLY since we need to test for Z=0 && N=0.
++(define_insn "*arm_bordered_reversed"
++ [(set (pc)
++ (if_then_else (ordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
++ (pc)
++ (label_ref (match_operand 0 "" ""))))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "12")]
++)
+
+ (define_insn "*arm_cond_branch_reversed"
+ [(set (pc)
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-compare-unordered.patch-z-eq b/packages/gcc/gcc-4.2.1/arm-crunch-compare-unordered.patch-z-eq
new file mode 100644
index 0000000000..715fb95086
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-compare-unordered.patch-z-eq
@@ -0,0 +1,98 @@
+--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-07 14:45:22.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-07 15:13:58.000000000 +1000
+@@ -7001,16 +7001,16 @@
+ (if_then_else (unordered (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0,
+ arm_compare_op1);"
+ )
+
+ (define_expand "bordered"
+ [(set (pc)
+ (if_then_else (ordered (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0,
+ arm_compare_op1);"
+@@ -7141,6 +7141,38 @@
+ (set_attr "length" "8")]
+ )
+
++; Special pattern to match UNORDERED for MAVERICK - UGLY since we need to test for C=0 && N=0
++(define_insn "*arm_bunordered"
++ [(set (pc)
++ (if_then_else (unordered (match_operand 1 "cc_register" "") (const_int 0))
++ (label_ref (match_operand 0 "" ""))
++ (pc)))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"bcs\\t.+12\;bmi\\t.+8\;b\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "12")]
++)
++
++; Special pattern to match ORDERED for MAVERICK.
++(define_insn "*arm_bordered"
++ [(set (pc)
++ (if_then_else (ordered (match_operand 1 "cc_register" "") (const_int 0))
++ (label_ref (match_operand 0 "" ""))
++ (pc)))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"bcs\\t%l0\;bmi\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "8")]
++)
++
+ (define_insn "*arm_cond_branch"
+ [(set (pc)
+ (if_then_else (match_operator 1 "arm_comparison_operator"
+@@ -7224,6 +7256,37 @@
+ (set_attr "length" "8")]
+ )
+
++; Special pattern to match reversed UNORDERED for MAVERICK.
++(define_insn "*arm_bunordered_reversed"
++ [(set (pc)
++ (if_then_else (unordered (match_operand 1 "cc_register" "") (const_int 0))
++ (pc)
++ (label_ref (match_operand 0 "" ""))))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"bcs\\t%l0\;bmi\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "8")]
++)
++
++; Special pattern to match reversed ORDERED for MAVERICK - UGLY since we need to test for C=0 && N=0
++(define_insn "*arm_bordered_reversed"
++ [(set (pc)
++ (if_then_else (ordered (match_operand 1 "cc_register" "") (const_int 0))
++ (pc)
++ (label_ref (match_operand 0 "" ""))))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"bcs\\t.+12\;bmi\\t.+8\;b\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "12")]
++)
+
+ (define_insn "*arm_cond_branch_reversed"
+ [(set (pc)
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-compare.patch b/packages/gcc/gcc-4.2.1/arm-crunch-compare.patch
new file mode 100644
index 0000000000..ccbb4854c3
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-compare.patch
@@ -0,0 +1,400 @@
+diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c
+--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000
+@@ -11427,26 +11427,53 @@
+ /* These encodings assume that AC=1 in the FPA system control
+ byte. This allows us to handle all cases except UNEQ and
+ LTGT. */
+- switch (comp_code)
+- {
+- case GE: return ARM_GE;
+- case GT: return ARM_GT;
+- case LE: return ARM_LS;
+- case LT: return ARM_MI;
+- case NE: return ARM_NE;
+- case EQ: return ARM_EQ;
+- case ORDERED: return ARM_VC;
+- case UNORDERED: return ARM_VS;
+- case UNLT: return ARM_LT;
+- case UNLE: return ARM_LE;
+- case UNGT: return ARM_HI;
+- case UNGE: return ARM_PL;
+- /* UNEQ and LTGT do not have a representation. */
+- case UNEQ: /* Fall through. */
+- case LTGT: /* Fall through. */
+- default: gcc_unreachable ();
+- }
+-
++ if (!TARGET_MAVERICK)
++ {
++ switch (comp_code)
++ {
++ case GE: return ARM_GE;
++ case GT: return ARM_GT;
++ case LE: return ARM_LS;
++ case LT: return ARM_MI;
++ case NE: return ARM_NE;
++ case EQ: return ARM_EQ;
++ case ORDERED: return ARM_VC;
++ case UNORDERED: return ARM_VS;
++ case UNLT: return ARM_LT;
++ case UNLE: return ARM_LE;
++ case UNGT: return ARM_HI;
++ case UNGE: return ARM_PL;
++ /* UNEQ and LTGT do not have a representation. */
++ case UNEQ: /* Fall through. */
++ case LTGT: /* Fall through. */
++ default: gcc_unreachable ();
++ }
++ }
++ else
++ {
++ /* CIRRUS */
++ switch (comp_code)
++ {
++#if 1
++ case GT: return ARM_VS;
++ case LE: return ARM_LE;
++ case LT: return ARM_LT;
++ case NE: return ARM_NE;
++ case EQ: return ARM_EQ;
++ case UNLE: return ARM_VC;
++ case UNGT: return ARM_GT;
++ case UNGE: return ARM_GE;
++ case UNEQ: return ARM_PL;
++ case LTGT: return ARM_MI;
++ /* These do not have a representation. */
++ case GE: /* Fall through. -UNGE wrong atm */
++ case UNLT: /* Fall through. -LT wrong atm */
++ case ORDERED: /* Fall through. -AL wrong atm */
++ case UNORDERED: /* Fall through. -AL wrong atm */
++#endif
++ default: gcc_unreachable ();
++ }
++ }
+ case CC_SWPmode:
+ switch (comp_code)
+ {
+diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md
+--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000
+@@ -6952,10 +6952,11 @@
+ "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
+ )
+
++;broken on cirrus
+ (define_expand "bge"
+ [(set (pc)
+ (if_then_else (ge (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM"
++ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
+ "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
+@@ -6988,6 +6989,7 @@
+ "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
+ )
+
++; broken on cirrus?
+ (define_expand "bgeu"
+ [(set (pc)
+ (if_then_else (geu (match_dup 1) (const_int 0))
+@@ -7031,14 +7033,15 @@
+ (if_then_else (ungt (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);"
+ )
+
+-(define_expand "bunlt"
++; broken for cirrus
++(define_expand "bunlt"
+ [(set (pc)
+ (if_then_else (unlt (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);"
+@@ -7049,7 +7052,7 @@
+ (if_then_else (unge (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);"
+ )
+
+@@ -7058,7 +7061,7 @@
+ (if_then_else (unle (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);"
+ )
+
+@@ -7069,7 +7072,7 @@
+ (if_then_else (uneq (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);"
+ )
+
+@@ -7078,7 +7081,7 @@
+ (if_then_else (ltgt (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);"
+ )
+
+@@ -7086,7 +7089,7 @@
+ ;; Patterns to match conditional branch insns.
+ ;;
+
+-; Special pattern to match UNEQ.
++; Special pattern to match UNEQ for FPA and VFP.
+ (define_insn "*arm_buneq"
+ [(set (pc)
+ (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
+@@ -7102,7 +7105,7 @@
+ (set_attr "length" "8")]
+ )
+
+-; Special pattern to match LTGT.
++; Special pattern to match LTGT for FPA and VFP.
+ (define_insn "*arm_bltgt"
+ [(set (pc)
+ (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
+@@ -7118,6 +7121,38 @@
+ (set_attr "length" "8")]
+ )
+
++; Special pattern to match GE for MAVERICK.
++(define_insn "*arm_bge"
++ [(set (pc)
++ (if_then_else (ge (match_operand:CCFP 1 "cc_register" "") (const_int 0))
++ (label_ref (match_operand 0 "" ""))
++ (pc)))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"beq\\t%l0\;bvs\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "8")]
++)
++
++; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0.
++(define_insn "*arm_bunlt"
++ [(set (pc)
++ (if_then_else (unlt (match_operand:CCFP 1 "cc_register" "") (const_int 0))
++ (label_ref (match_operand 0 "" ""))
++ (pc)))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "12")]
++)
++
+ (define_insn "*arm_cond_branch"
+ [(set (pc)
+ (if_then_else (match_operator 1 "arm_comparison_operator"
+@@ -7137,7 +7172,7 @@
+ (set_attr "type" "branch")]
+ )
+
+-; Special pattern to match reversed UNEQ.
++; Special pattern to match reversed UNEQ for FPA and VFP.
+ (define_insn "*arm_buneq_reversed"
+ [(set (pc)
+ (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
+@@ -7153,7 +7188,7 @@
+ (set_attr "length" "8")]
+ )
+
+-; Special pattern to match reversed LTGT.
++; Special pattern to match reversed LTGT for FPA and VFP.
+ (define_insn "*arm_bltgt_reversed"
+ [(set (pc)
+ (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
+@@ -7169,6 +7204,39 @@
+ (set_attr "length" "8")]
+ )
+
++; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0.
++(define_insn "*arm_bge_reversed"
++ [(set (pc)
++ (if_then_else (ge (match_operand:CCFP 1 "cc_register" "") (const_int 0))
++ (pc)
++ (label_ref (match_operand 0 "" ""))))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "12")]
++)
++
++; Special pattern to match reversed UNLT for MAVERICK.
++(define_insn "*arm_bunlt_reversed"
++ [(set (pc)
++ (if_then_else (unlt (match_operand:CCFP 1 "cc_register" "") (const_int 0))
++ (pc)
++ (label_ref (match_operand 0 "" ""))))]
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"beq\\t%l0\;bvs\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "8")]
++)
++
++
+ (define_insn "*arm_cond_branch_reversed"
+ [(set (pc)
+ (if_then_else (match_operator 1 "arm_comparison_operator"
+@@ -7220,8 +7288,9 @@
+ "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
+ )
+
++;; broken for cirrus - definitely
+ (define_expand "sge"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (ge:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM"
++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
+@@ -7227,6 +7296,14 @@
+ "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
+ )
+
++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK
++; (define_expand "sge"
++; [(set (match_operand:SI 0 "s_register_operand" "")
++; (ge:SI (match_dup 1) (const_int 0)))]
++; "TARGET_ARM && (TARGET_MAVERICK)"
++; "gcc_unreachable ();"
++; )
++
+ (define_expand "slt"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (lt:SI (match_dup 1) (const_int 0)))]
+@@ -7248,6 +7325,7 @@
+ "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
+ )
+
++;; broken for cirrus - maybe
+ (define_expand "sgeu"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (geu:SI (match_dup 1) (const_int 0)))]
+@@ -7255,6 +7333,14 @@
+ "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);"
+ )
+
++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK?
++; (define_expand "sgeu"
++; [(set (match_operand:SI 0 "s_register_operand" "")
++; (ge:SI (match_dup 1) (const_int 0)))]
++; "TARGET_ARM && (TARGET_MAVERICK)"
++; "gcc_unreachable ();"
++; )
++
+ (define_expand "sltu"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (ltu:SI (match_dup 1) (const_int 0)))]
+@@ -7281,7 +7367,7 @@
+ (define_expand "sungt"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (ungt:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0,
+ arm_compare_op1);"
+ )
+@@ -7289,23 +7375,32 @@
+ (define_expand "sunge"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (unge:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0,
+ arm_compare_op1);"
+ )
+
++; broken for cirrus
+ (define_expand "sunlt"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (unlt:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0,
+ arm_compare_op1);"
+ )
+
++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK
++; (define_expand "sunlt"
++; [(set (match_operand:SI 0 "s_register_operand" "")
++; (unlt:SI (match_dup 1) (const_int 0)))]
++; "TARGET_ARM && (TARGET_MAVERICK)"
++; "gcc_unreachable ();"
++; )
++
+ (define_expand "sunle"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (unle:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0,
+ arm_compare_op1);"
+ )
+@@ -7371,7 +7466,7 @@
+ enum rtx_code code = GET_CODE (operands[1]);
+ rtx ccreg;
+
+- if (code == UNEQ || code == LTGT)
++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED)))
+ FAIL;
+
+ ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
+@@ -7390,7 +7485,8 @@
+ enum rtx_code code = GET_CODE (operands[1]);
+ rtx ccreg;
+
+- if (code == UNEQ || code == LTGT)
++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED)))
++
+ FAIL;
+
+ /* When compiling for SOFT_FLOAT, ensure both arms are in registers.
+@@ -7409,13 +7505,13 @@
+ (if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
+ (match_operand:DF 2 "s_register_operand" "")
+ (match_operand:DF 3 "arm_float_add_operand" "")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "
+ {
+ enum rtx_code code = GET_CODE (operands[1]);
+ rtx ccreg;
+
+- if (code == UNEQ || code == LTGT)
++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED)))
+ FAIL;
+
+ ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-compare.patch-z-eq b/packages/gcc/gcc-4.2.1/arm-crunch-compare.patch-z-eq
new file mode 100644
index 0000000000..bc40411be4
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-compare.patch-z-eq
@@ -0,0 +1,400 @@
+diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c
+--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000
+@@ -11427,26 +11427,53 @@
+ /* These encodings assume that AC=1 in the FPA system control
+ byte. This allows us to handle all cases except UNEQ and
+ LTGT. */
+- switch (comp_code)
+- {
+- case GE: return ARM_GE;
+- case GT: return ARM_GT;
+- case LE: return ARM_LS;
+- case LT: return ARM_MI;
+- case NE: return ARM_NE;
+- case EQ: return ARM_EQ;
+- case ORDERED: return ARM_VC;
+- case UNORDERED: return ARM_VS;
+- case UNLT: return ARM_LT;
+- case UNLE: return ARM_LE;
+- case UNGT: return ARM_HI;
+- case UNGE: return ARM_PL;
+- /* UNEQ and LTGT do not have a representation. */
+- case UNEQ: /* Fall through. */
+- case LTGT: /* Fall through. */
+- default: gcc_unreachable ();
+- }
+-
++ if (!TARGET_MAVERICK)
++ {
++ switch (comp_code)
++ {
++ case GE: return ARM_GE;
++ case GT: return ARM_GT;
++ case LE: return ARM_LS;
++ case LT: return ARM_MI;
++ case NE: return ARM_NE;
++ case EQ: return ARM_EQ;
++ case ORDERED: return ARM_VC;
++ case UNORDERED: return ARM_VS;
++ case UNLT: return ARM_LT;
++ case UNLE: return ARM_LE;
++ case UNGT: return ARM_HI;
++ case UNGE: return ARM_PL;
++ /* UNEQ and LTGT do not have a representation. */
++ case UNEQ: /* Fall through. */
++ case LTGT: /* Fall through. */
++ default: gcc_unreachable ();
++ }
++ }
++ else
++ {
++ /* CIRRUS */
++ switch (comp_code)
++ {
++#if 1
++ case GT: return ARM_VS;
++ case LE: return ARM_LE;
++ case LT: return ARM_LT;
++ case NE: return ARM_NE;
++ case EQ: return ARM_EQ;
++ case UNLE: return ARM_VC;
++ case UNGT: return ARM_GT;
++ case UNGE: return ARM_GE;
++ case UNEQ: return ARM_PL;
++ case LTGT: return ARM_MI;
++ /* These do not have a representation. */
++ case GE: /* Fall through. -UNGE wrong atm */
++ case UNLT: /* Fall through. -LT wrong atm */
++ case ORDERED: /* Fall through. -AL wrong atm */
++ case UNORDERED: /* Fall through. -AL wrong atm */
++#endif
++ default: gcc_unreachable ();
++ }
++ }
+ case CC_SWPmode:
+ switch (comp_code)
+ {
+diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md
+--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000
+@@ -6952,10 +6952,11 @@
+ "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
+ )
+
++;broken on cirrus
+ (define_expand "bge"
+ [(set (pc)
+ (if_then_else (ge (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM"
++ "TARGET_ARM"
+ "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
+@@ -6988,6 +6989,7 @@
+ "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
+ )
+
++; broken on cirrus?
+ (define_expand "bgeu"
+ [(set (pc)
+ (if_then_else (geu (match_dup 1) (const_int 0))
+@@ -7031,14 +7033,15 @@
+ (if_then_else (ungt (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);"
+ )
+
+-(define_expand "bunlt"
++; broken for cirrus
++(define_expand "bunlt"
+ [(set (pc)
+ (if_then_else (unlt (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);"
+@@ -7049,7 +7052,7 @@
+ (if_then_else (unge (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);"
+ )
+
+@@ -7058,7 +7061,7 @@
+ (if_then_else (unle (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);"
+ )
+
+@@ -7069,7 +7072,7 @@
+ (if_then_else (uneq (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK
+ "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);"
+ )
+
+@@ -7078,7 +7081,7 @@
+ (if_then_else (ltgt (match_dup 1) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK
+ "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);"
+ )
+
+@@ -7086,7 +7089,7 @@
+ ;; Patterns to match conditional branch insns.
+ ;;
+
+-; Special pattern to match UNEQ.
++; Special pattern to match UNEQ for FPA and VFP.
+ (define_insn "*arm_buneq"
+ [(set (pc)
+ (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
+@@ -7102,7 +7105,7 @@
+ (set_attr "length" "8")]
+ )
+
+-; Special pattern to match LTGT.
++; Special pattern to match LTGT for FPA and VFP.
+ (define_insn "*arm_bltgt"
+ [(set (pc)
+ (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
+@@ -7118,6 +7121,38 @@
+ (set_attr "length" "8")]
+ )
+
++; Special pattern to match GE for MAVERICK.
++(define_insn "*arm_bge"
++ [(set (pc)
++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0))
++ (label_ref (match_operand 0 "" ""))
++ (pc)))]
++ "TARGET_ARM && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"beq\\t%l0\;bvs\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "8")]
++)
++
++; Special pattern to match UNLT for MAVERICK.
++(define_insn "*arm_bunlt"
++ [(set (pc)
++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0))
++ (label_ref (match_operand 0 "" ""))
++ (pc)))]
++ "TARGET_ARM && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"bne\\t%l0\;bvc\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "8")]
++)
++
+ (define_insn "*arm_cond_branch"
+ [(set (pc)
+ (if_then_else (match_operator 1 "arm_comparison_operator"
+@@ -7137,7 +7172,7 @@
+ (set_attr "type" "branch")]
+ )
+
+-; Special pattern to match reversed UNEQ.
++; Special pattern to match reversed UNEQ for FPA and VFP.
+ (define_insn "*arm_buneq_reversed"
+ [(set (pc)
+ (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
+@@ -7153,7 +7188,7 @@
+ (set_attr "length" "8")]
+ )
+
+-; Special pattern to match reversed LTGT.
++; Special pattern to match reversed LTGT for FPA and VFP.
+ (define_insn "*arm_bltgt_reversed"
+ [(set (pc)
+ (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
+@@ -7169,6 +7204,39 @@
+ (set_attr "length" "8")]
+ )
+
++; Special pattern to match reversed GE for MAVERICK.
++(define_insn "*arm_bge_reversed"
++ [(set (pc)
++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0))
++ (pc)
++ (label_ref (match_operand 0 "" ""))))]
++ "TARGET_ARM && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"bne\\t%l0\;bvc\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "8")]
++)
++
++; Special pattern to match reversed UNLT for MAVERICK.
++(define_insn "*arm_bunlt_reversed"
++ [(set (pc)
++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0))
++ (pc)
++ (label_ref (match_operand 0 "" ""))))]
++ "TARGET_ARM && (TARGET_MAVERICK)"
++ "*
++ gcc_assert (!arm_ccfsm_state);
++
++ return \"beq\\t%l0\;bvs\\t%l0\";
++ "
++ [(set_attr "conds" "jump_clob")
++ (set_attr "length" "8")]
++)
++
++
+ (define_insn "*arm_cond_branch_reversed"
+ [(set (pc)
+ (if_then_else (match_operator 1 "arm_comparison_operator"
+@@ -7220,8 +7288,9 @@
+ "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
+ )
+
++;; broken for cirrus - definitely
+ (define_expand "sge"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (ge:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM"
++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
+@@ -7227,6 +7296,14 @@
+ "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
+ )
+
++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK
++; (define_expand "sge"
++; [(set (match_operand:SI 0 "s_register_operand" "")
++; (ge:SI (match_dup 1) (const_int 0)))]
++; "TARGET_ARM && (TARGET_MAVERICK)"
++; "gcc_unreachable ();"
++; )
++
+ (define_expand "slt"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (lt:SI (match_dup 1) (const_int 0)))]
+@@ -7248,6 +7325,7 @@
+ "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
+ )
+
++;; broken for cirrus - maybe
+ (define_expand "sgeu"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (geu:SI (match_dup 1) (const_int 0)))]
+@@ -7255,6 +7333,14 @@
+ "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);"
+ )
+
++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK?
++; (define_expand "sgeu"
++; [(set (match_operand:SI 0 "s_register_operand" "")
++; (ge:SI (match_dup 1) (const_int 0)))]
++; "TARGET_ARM && (TARGET_MAVERICK)"
++; "gcc_unreachable ();"
++; )
++
+ (define_expand "sltu"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (ltu:SI (match_dup 1) (const_int 0)))]
+@@ -7281,7 +7367,7 @@
+ (define_expand "sungt"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (ungt:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0,
+ arm_compare_op1);"
+ )
+@@ -7289,23 +7375,32 @@
+ (define_expand "sunge"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (unge:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0,
+ arm_compare_op1);"
+ )
+
++; broken for cirrus
+ (define_expand "sunlt"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (unlt:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0,
+ arm_compare_op1);"
+ )
+
++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK
++; (define_expand "sunlt"
++; [(set (match_operand:SI 0 "s_register_operand" "")
++; (unlt:SI (match_dup 1) (const_int 0)))]
++; "TARGET_ARM && (TARGET_MAVERICK)"
++; "gcc_unreachable ();"
++; )
++
+ (define_expand "sunle"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (unle:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0,
+ arm_compare_op1);"
+ )
+@@ -7371,7 +7466,7 @@
+ enum rtx_code code = GET_CODE (operands[1]);
+ rtx ccreg;
+
+- if (code == UNEQ || code == LTGT)
++ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED)
+ FAIL;
+
+ ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
+@@ -7390,7 +7485,8 @@
+ enum rtx_code code = GET_CODE (operands[1]);
+ rtx ccreg;
+
+- if (code == UNEQ || code == LTGT)
++ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED)
++
+ FAIL;
+
+ /* When compiling for SOFT_FLOAT, ensure both arms are in registers.
+@@ -7409,13 +7505,13 @@
+ (if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
+ (match_operand:DF 2 "s_register_operand" "")
+ (match_operand:DF 3 "arm_float_add_operand" "")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "
+ {
+ enum rtx_code code = GET_CODE (operands[1]);
+ rtx ccreg;
+
+- if (code == UNEQ || code == LTGT)
++ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED)
+ FAIL;
+
+ ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-dominance.patch b/packages/gcc/gcc-4.2.1/arm-crunch-dominance.patch
new file mode 100644
index 0000000000..517ca8d80e
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-dominance.patch
@@ -0,0 +1,12 @@
+--- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-13 11:50:10.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-13 11:50:56.000000000 +1000
+@@ -6556,6 +6556,9 @@
+ enum rtx_code cond1, cond2;
+ int swapped = 0;
+
++ if (TARGET_MAVERICK) // Simple hack for MAVERICK
++ return CCmode;
++
+ /* Currently we will probably get the wrong result if the individual
+ comparisons are not simple. This also ensures that it is safe to
+ reverse a comparison if necessary. */
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-eabi-ieee754-div.patch b/packages/gcc/gcc-4.2.1/arm-crunch-eabi-ieee754-div.patch
new file mode 100644
index 0000000000..940f4a65ae
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-eabi-ieee754-div.patch
@@ -0,0 +1,139 @@
+--- gcc-4.1.2/gcc/config/arm/ieee754-df-original.S 2007-06-25 10:22:06.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-25 10:27:17.000000000 +1000
+@@ -717,6 +717,10 @@
+ cmn r4, #(53 + 1)
+ movle xl, #0
+ bicle xh, xh, #0x7fffffff
++#ifdef __MAVERICK__
++ cfmvdlr mvd0, xl
++ cfmvdhr mvd0, xh
++#endif
+ RETLDM "r4, r5, r6" le
+
+ @ Find out proper shift value.
+@@ -738,6 +742,10 @@
+ adc xh, r2, xh, lsr r4
+ orrs lr, lr, r3, lsl #1
+ biceq xl, xl, r3, lsr #31
++#ifdef __MAVERICK__
++ cfmvdlr mvd0, xl
++ cfmvdhr mvd0, xh
++#endif
+ RETLDM "r4, r5, r6"
+
+ @ shift result right of 21 to 31 bits, or left 11 to 1 bits after
+@@ -752,6 +760,10 @@
+ adc xh, xh, #0
+ orrs lr, lr, r3, lsl #1
+ biceq xl, xl, r3, lsr #31
++#ifdef __MAVERICK__
++ cfmvdlr mvd0, xl
++ cfmvdhr mvd0, xh
++#endif
+ RETLDM "r4, r5, r6"
+
+ @ Shift value right of 32 to 64 bits, or 0 to 32 bits after a switch
+@@ -766,6 +778,10 @@
+ add xl, xl, r3, lsr #31
+ orrs lr, lr, r3, lsl #1
+ biceq xl, xl, r3, lsr #31
++#ifdef __MAVERICK__
++ cfmvdlr mvd0, xl
++ cfmvdhr mvd0, xh
++#endif
+ RETLDM "r4, r5, r6"
+
+ @ One or both arguments are denormalized.
+@@ -808,6 +824,10 @@
+ eor xh, xh, yh
+ bic xh, xh, #0x7fffffff
+ mov xl, #0
++#ifdef __MAVERICK__
++ cfmvdlr mvd0, xl
++ cfmvdhr mvd0, xh
++#endif
+ RETLDM "r4, r5, r6"
+
+ 1: @ One or both args are INF or NAN.
+@@ -837,12 +857,20 @@
+ orr xh, xh, #0x7f000000
+ orr xh, xh, #0x00f00000
+ mov xl, #0
++#ifdef __MAVERICK__
++ cfmvdlr mvd0, xl
++ cfmvdhr mvd0, xh
++#endif
+ RETLDM "r4, r5, r6"
+
+ @ Return a quiet NAN.
+ LSYM(Lml_n):
+ orr xh, xh, #0x7f000000
+ orr xh, xh, #0x00f80000
++#ifdef __MAVERICK__
++ cfmvdlr mvd0, xl
++ cfmvdhr mvd0, xh
++#endif
+ RETLDM "r4, r5, r6"
+
+ FUNC_END aeabi_dmul
+--- gcc-4.1.2/gcc/config/arm/ieee754-sf-original.S 2007-06-25 10:18:52.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-25 10:40:25.000000000 +1000
+@@ -518,6 +518,9 @@
+ @ Check if denormalized result is possible, otherwise return signed 0.
+ cmn r2, #(24 + 1)
+ bicle r0, r0, #0x7fffffff
++#ifdef __MAVERICK__
++ cfmvsr mvf0, r0
++#endif
+ RETc(le)
+
+ @ Shift value right, round, etc.
+@@ -530,6 +533,9 @@
+ adc r0, r0, #0
+ orrs r3, r3, ip, lsl #1
+ biceq r0, r0, ip, lsr #31
++#ifdef __MAVERICK__
++ cfmvsr mvf0, r0
++#endif
+ RET
+
+ @ One or both arguments are denormalized.
+@@ -567,6 +573,9 @@
+ LSYM(Lml_z):
+ eor r0, r0, r1
+ bic r0, r0, #0x7fffffff
++#ifdef __MAVERICK__
++ cfmvsr mvf0, r0
++#endif
+ RET
+
+ 1: @ One or both args are INF or NAN.
+@@ -595,12 +604,18 @@
+ and r0, r0, #0x80000000
+ orr r0, r0, #0x7f000000
+ orr r0, r0, #0x00800000
++#ifdef __MAVERICK__
++ cfmvsr mvf0, r0
++#endif
+ RET
+
+ @ Return a quiet NAN.
+ LSYM(Lml_n):
+ orr r0, r0, #0x7f000000
+ orr r0, r0, #0x00c00000
++#ifdef __MAVERICK__
++ cfmvsr mvf0, r0
++#endif
+ RET
+
+ FUNC_END aeabi_fmul
+@@ -677,6 +692,9 @@
+ adds r2, r2, #127
+ rsbgts r3, r2, #255
+ orrgt r0, r0, r2, lsl #23
++#ifdef __MAVERICK__
++ cfmvsr mvf0, r0
++#endif
+ RETc(gt)
+
+ orr r0, r0, #0x00800000
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-eabi-ieee754.patch b/packages/gcc/gcc-4.2.1/arm-crunch-eabi-ieee754.patch
new file mode 100644
index 0000000000..e4929fa20e
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-eabi-ieee754.patch
@@ -0,0 +1,100 @@
+--- ../gcc-cross-4.1.2-r4-unpatched/gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-07 13:06:52.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-07 13:15:49.000000000 +1000
+@@ -42,8 +42,9 @@
+
+
+ @ For FPA, float words are always big-endian.
++@ For MAVERICK, float words are always little-endian.
+ @ For VFP, floats words follow the memory system mode.
+-#if defined(__VFP_FP__) && !defined(__ARMEB__)
++#if ((defined(__VFP_FP__) && !defined(__ARMEB__)) || defined(__MAVERICK__))
+ #define xl r0
+ #define xh r1
+ #define yl r2
+@@ -451,8 +452,13 @@
+
+ orrs r2, r0, r1
+ #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
++#if defined (__FPA_FP__)
+ mvfeqd f0, #0.0
+ #endif
++#if defined (__MAVERICK__)
++ cfstrd mvd0, #0.0
++#endif
++#endif
+ RETc(eq)
+
+ #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
+@@ -473,8 +479,13 @@
+
+ orrs r2, r0, r1
+ #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
++#if defined (__FPA_FP__)
+ mvfeqd f0, #0.0
+ #endif
++#if defined (__MAVERICK__)
++ cfstrd mvd0, #0.0
++#endif
++#endif
+ RETc(eq)
+
+ #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
+@@ -526,8 +537,14 @@
+ @ Legacy code expects the result to be returned in f0. Copy it
+ @ there as well.
+ LSYM(f0_ret):
++#if defined (__FPA_FP__)
+ stmfd sp!, {r0, r1}
+ ldfd f0, [sp], #8
++#endif
++#if defined (__MAVERICK__)
++ cfmvdlr mvd0, xl
++ cfmvdhr mvd0, xh
++#endif
+ RETLDM
+
+ #endif
+--- ../gcc-cross-4.1.2-r4-unpatched/gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-07 13:06:52.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-07 13:21:43.000000000 +1000
+@@ -302,8 +302,13 @@
+
+ orrs r2, r0, r1
+ #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
++#if defined (__FPA_FP__)
+ mvfeqs f0, #0.0
+ #endif
++#if defined (__MAVERICK__)
++ cfmvsr mvf0, #0.0
++#endif
++#endif
+ RETc(eq)
+
+ mov r3, #0
+@@ -314,8 +319,13 @@
+
+ orrs r2, r0, r1
+ #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
++#if defined (__FPA_FP__)
+ mvfeqs f0, #0.0
+ #endif
++#if defined (__MAVERICK__)
++ cfmvsr mvf0, #0.0
++#endif
++#endif
+ RETc(eq)
+
+ ands r3, ah, #0x80000000 @ sign bit in r3
+@@ -387,8 +397,13 @@
+ #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
+
+ LSYM(f0_ret):
++#if defined (__FPA_FP__)
+ str r0, [sp, #-4]!
+ ldfs f0, [sp], #4
++#endif
++#if defined (__MAVERICK__)
++ cfmvsr mvf0, r0
++#endif
+ RETLDM
+
+ #endif
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-eabi.patch b/packages/gcc/gcc-4.2.1/arm-crunch-eabi.patch
new file mode 100644
index 0000000000..f8992ed499
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-eabi.patch
@@ -0,0 +1,64 @@
+--- /home/hwilliams/original/gcc-4.1.2/gcc/config/arm/t-linux-eabi 2005-10-10 11:04:31.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/t-linux-eabi 2007-05-15 13:53:05.000000000 +1000
+@@ -1,11 +1,21 @@
+ # These functions are included in shared libraries.
+ TARGET_LIBGCC2_CFLAGS = -fPIC
++TARGET_LIBGCC2_CFLAGS += -mcpu=ep9312 -mfpu=maverick
++LIBGCC2_DEBUG_CFLAGS = -g0
+
+ # We do not build a Thumb multilib for Linux because the definition of
+ # CLEAR_INSN_CACHE in linux-gas.h does not work in Thumb mode.
+ MULTILIB_OPTIONS =
+ MULTILIB_DIRNAMES =
+
++LIB1ASMSRC = arm/lib1funcs.asm
++LIB1ASMFUNCS += _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx \
++ _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \
++ _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \
++ _fixsfsi _fixunssfsi
++
++CRTSTUFF_T_CFLAGS += -mcpu=ep9312 -mfpu=maverick
++
+ # Use a version of div0 which raises SIGFPE.
+ LIB1ASMFUNCS := $(filter-out _dvmd_tls,$(LIB1ASMFUNCS)) _dvmd_lnx
+
+diff -ruN arm/elf.h gcc-3.4.3/gcc/config/arm/elf.h
+--- ../gcc-4.1.2-orig/gcc/config/arm/elf.h 2004-02-24 16:25:22.000000000 +0200
++++ gcc-4.1.2/gcc/config/arm/elf.h 2005-02-10 00:31:28.000000000 +0200
+@@ -46,7 +46,7 @@
+
+ #ifndef SUBTARGET_ASM_FLOAT_SPEC
+ #define SUBTARGET_ASM_FLOAT_SPEC "\
+-%{mapcs-float:-mfloat}"
++%{mapcs-float:-mfloat} %{msoft-float:-mfpu=softfpa} %{mcpu=ep9312:-mfpu=maverick}"
+ #endif
+
+ #ifndef ASM_SPEC
+diff -ruN t-linux gcc-4.1.2/gcc/config/arm/t-linux
+--- t-linux 2007-05-09 16:32:28.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/t-linux 2007-05-25 11:02:17.000000000 +1000
+@@ -1,19 +1,22 @@
+ # Just for these, we omit the frame pointer since it makes such a big
+ # difference. It is then pointless adding debugging.
+ TARGET_LIBGCC2_CFLAGS = -fomit-frame-pointer -fPIC
++TARGET_LIBGCC2_CFLAGS += -mcpu=ep9312 -mfpu=maverick -mfloat-abi=softfp -D__MAVERICK__
+ LIBGCC2_DEBUG_CFLAGS = -g0
+
+ LIB1ASMSRC = arm/lib1funcs.asm
+ LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx \
+ _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \
+ _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \
+- _call_via_rX \
+- _fixsfsi _fixunssfsi _floatdidf _floatdisf
++ _fixsfsi _fixunssfsi
+
+ # MULTILIB_OPTIONS = mhard-float/msoft-float
+ # MULTILIB_DIRNAMES = hard-float soft-float
+
+ # EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
+
++# EXTRA_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o
++CRTSTUFF_T_CFLAGS += -mcpu=ep9312 -mfpu=maverick -mfloat-abi=softfp -D__MAVERICK__
++
+ # LIBGCC = stmp-multilib
+ # INSTALL_LIBGCC = install-multilib
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-floatsi-disable-single.patch b/packages/gcc/gcc-4.2.1/arm-crunch-floatsi-disable-single.patch
new file mode 100644
index 0000000000..cdd52244a6
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-floatsi-disable-single.patch
@@ -0,0 +1,38 @@
+--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:12:39.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:16:13.000000000 +1000
+@@ -301,13 +301,14 @@
+ )
+
+ ;; Convert Cirrus-SI to Cirrus-SF
++; appears to be buggy
+ (define_insn "cirrus_floatsisf2"
+ [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
+ (float:SF (match_operand:SI 1 "s_register_operand" "r")))
+ (clobber (match_scratch:DF 2 "=v"))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
+ [(set_attr "length" "8")
+ (set_attr "cirrus" "move")]
+ )
+
+--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:16:53.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:18:20.000000000 +1000
+@@ -3125,14 +3125,15 @@
+
+ ;; Fixed <--> Floating conversion insns
+
++;; Maverick Crunch floatsisf2 is buggy - see cirrus.md
+ (define_expand "floatsisf2"
+ [(set (match_operand:SF 0 "s_register_operand" "")
+ (float:SF (match_operand:SI 1 "s_register_operand" "")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "
+- if (TARGET_MAVERICK)
++ if (TARGET_MAVERICK && 0)
+ {
+ emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
+ DONE;
+ }
+ ")
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-floatsi-disable.patch b/packages/gcc/gcc-4.2.1/arm-crunch-floatsi-disable.patch
new file mode 100644
index 0000000000..aa54ec3e04
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-floatsi-disable.patch
@@ -0,0 +1,61 @@
+--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:12:39.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:16:13.000000000 +1000
+@@ -301,21 +301,23 @@
+ )
+
+ ;; Convert Cirrus-SI to Cirrus-SF
++; appears to be buggy
+ (define_insn "cirrus_floatsisf2"
+ [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
+ (float:SF (match_operand:SI 1 "s_register_operand" "r")))
+ (clobber (match_scratch:DF 2 "=v"))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
+ [(set_attr "length" "8")
+ (set_attr "cirrus" "move")]
+ )
+
++;appears to be buggy
+ (define_insn "cirrus_floatsidf2"
+ [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
+ (float:DF (match_operand:SI 1 "s_register_operand" "r")))
+ (clobber (match_scratch:DF 2 "=v"))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
+ [(set_attr "length" "8")
+ (set_attr "cirrus" "move")]
+--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:16:53.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:18:20.000000000 +1000
+@@ -3125,24 +3125,26 @@
+
+ ;; Fixed <--> Floating conversion insns
+
++;; Maverick Crunch floatsisf2 is buggy - see cirrus.md
+ (define_expand "floatsisf2"
+ [(set (match_operand:SF 0 "s_register_operand" "")
+ (float:SF (match_operand:SI 1 "s_register_operand" "")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "
+- if (TARGET_MAVERICK)
++ if (TARGET_MAVERICK && 0)
+ {
+ emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
+ DONE;
+ }
+ ")
+
++;; Maverick Crunch floatsidf2 is buggy - see cirrus.md
+ (define_expand "floatsidf2"
+ [(set (match_operand:DF 0 "s_register_operand" "")
+ (float:DF (match_operand:SI 1 "s_register_operand" "")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "
+- if (TARGET_MAVERICK)
++ if (TARGET_MAVERICK && 0)
+ {
+ emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
+ DONE;
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-floatunsidf.patch b/packages/gcc/gcc-4.2.1/arm-crunch-floatunsidf.patch
new file mode 100644
index 0000000000..2fe2254db9
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-floatunsidf.patch
@@ -0,0 +1,37 @@
+--- gcc-4.1.2/gcc/config/arm/ieee754-df-original.S 2007-06-25 14:05:35.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-25 14:08:03.000000000 +1000
+@@ -382,6 +382,8 @@
+ FUNC_END aeabi_dadd
+ FUNC_END adddf3
+
++#ifndef __MAVERICK__ /* THIS IS A BAD HACK */
++
+ ARM_FUNC_START floatunsidf
+ ARM_FUNC_ALIAS aeabi_ui2d floatunsidf
+
+@@ -401,8 +403,14 @@
+ FUNC_END aeabi_ui2d
+ FUNC_END floatunsidf
+
++#endif
++
+ ARM_FUNC_START floatsidf
+ ARM_FUNC_ALIAS aeabi_i2d floatsidf
++#ifdef __MAVERICK__ /* THIS IS A BAD HACK */
++ARM_FUNC_ALIAS floatunsidf floatsidf
++ARM_FUNC_ALIAS aeabi_ui2d floatsidf
++#endif
+
+ teq r0, #0
+ moveq r1, #0
+@@ -418,6 +426,10 @@
+ mov xh, #0
+ b LSYM(Lad_l)
+
++#ifdef __MAVERICK__ /* THIS IS A BAD HACK */
++ FUNC_END aeabi_ui2d floatsidf
++ FUNC_END floatunsidf floatsidf
++#endif
+ FUNC_END aeabi_i2d
+ FUNC_END floatsidf
+
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-fp_consts.patch b/packages/gcc/gcc-4.2.1/arm-crunch-fp_consts.patch
new file mode 100644
index 0000000000..5f289bbebe
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-fp_consts.patch
@@ -0,0 +1,13 @@
+--- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-12 16:17:14.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-12 16:17:28.000000000 +1000
+@@ -5218,7 +5218,9 @@
+ int i;
+ REAL_VALUE_TYPE r;
+
++ if (TARGET_MAVERICK)
++ fp_consts_inited = 0;
+- if (TARGET_VFP)
++ else if (TARGET_VFP)
+ fp_consts_inited = 1;
+ else
+ fp_consts_inited = 8;
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-neg.patch b/packages/gcc/gcc-4.2.1/arm-crunch-neg.patch
new file mode 100644
index 0000000000..f14ae0190e
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-neg.patch
@@ -0,0 +1,30 @@
+WARNING: adding this patch causes copysign1.c and mzero3.c to fail...
+diff -urN gcc-4.1.2/gcc/config/arm/arm.md-original gcc-4.1.2/gcc/config/arm/arm.md
+--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-12 12:48:14.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-12 12:49:53.000000000 +1000
+@@ -2985,14 +2985,14 @@
+ (define_expand "negsf2"
+ [(set (match_operand:SF 0 "s_register_operand" "")
+ (neg:SF (match_operand:SF 1 "s_register_operand" "")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ ""
+ )
+
+ (define_expand "negdf2"
+ [(set (match_operand:DF 0 "s_register_operand" "")
+ (neg:DF (match_operand:DF 1 "s_register_operand" "")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "")
+
+ ;; abssi2 doesn't really clobber the condition codes if a different register
+@@ -4097,7 +4097,7 @@
+ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
+ (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))]
+ "TARGET_ARM
+- && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
++ && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP || TARGET_MAVERICK))
+ && !TARGET_IWMMXT"
+ "*
+ switch (which_alternative)
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-neg2.patch b/packages/gcc/gcc-4.2.1/arm-crunch-neg2.patch
new file mode 100644
index 0000000000..4fd91f3215
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-neg2.patch
@@ -0,0 +1,25 @@
+--- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-06-12 17:01:24.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-12 17:03:26.000000000 +1000
+@@ -255,18 +256,20 @@
+ [(set_attr "cirrus" "normal")]
+ )
+
++;; appears to be buggy: neg 0 != -0
+ (define_insn "*cirrus_negsf2"
+ [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
+ (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfnegs%?\\t%V0, %V1"
+ [(set_attr "cirrus" "normal")]
+ )
+
++;; appears to be buggy: neg 0 != -0
+ (define_insn "*cirrus_negdf2"
+ [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
+ (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfnegd%?\\t%V0, %V1"
+ [(set_attr "cirrus" "normal")]
+ )
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-offset.patch b/packages/gcc/gcc-4.2.1/arm-crunch-offset.patch
new file mode 100644
index 0000000000..3a40f0d224
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-offset.patch
@@ -0,0 +1,20 @@
+--- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-12 14:46:20.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-12 14:48:06.000000000 +1000
+@@ -3460,7 +3460,7 @@
+
+ use_ldrd = (TARGET_LDRD
+ && (mode == DImode
+- || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
++ || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_MAVERICK || TARGET_VFP))));
+
+ if (code == POST_INC || code == PRE_DEC
+ || ((code == PRE_INC || code == POST_DEC)
+@@ -3960,7 +3960,7 @@
+ /* VFP addressing modes actually allow greater offsets, but for
+ now we just stick with the lowest common denominator. */
+ if (mode == DImode
+- || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
++ || ((TARGET_SOFT_FLOAT || TARGET_MAVERICK || TARGET_VFP) && mode == DFmode))
+ {
+ low_n = n & 0x0f;
+ n &= ~0x0f;
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-predicates.patch b/packages/gcc/gcc-4.2.1/arm-crunch-predicates.patch
new file mode 100644
index 0000000000..4841ff8178
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-predicates.patch
@@ -0,0 +1,20 @@
+diff -urN gcc-4.1.2/gcc/config/arm/predicates.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/predicates.md
+--- gcc-4.1.2/gcc/config/arm/predicates.md 2005-09-11 17:38:02.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-05-30 12:15:54.000000000 +1000
+@@ -171,8 +171,14 @@
+ (match_code "eq,ne"))
+
+ ;; True for comparisons other than LTGT or UNEQ.
++(define_special_predicate "arm_comparison_operator"
++; (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) ;; original - no LTGT or UNEQ
++; (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltgt,ltu,unordered,ordered,uneq,unlt,unle,unge,ungt")) ;; everything?
++;; True for comparisons other than GE, GEU, UNLT, unordered or ordered. - Cirrus Version - must include ge?
+-(define_special_predicate "arm_comparison_operator"
++;(define_special_predicate "arm_comparison_operator"
+- (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
++(match_code "eq,ne,le,lt,ge,geu,gt,gtu,leu,ltgt,ltu,uneq,unle,unge,ungt")) ;; bad codes removed?
++;(match_code "eq,ne,le,lt,gt,gtu,leu,ltgt,ltu,uneq,unle,unge,ungt")) ;; bad codes removed + ge / geu removed
++
+
+ (define_special_predicate "minmax_operator"
+ (and (match_code "smin,smax,umin,umax")
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-predicates2.patch b/packages/gcc/gcc-4.2.1/arm-crunch-predicates2.patch
new file mode 100644
index 0000000000..3e01158fe1
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-predicates2.patch
@@ -0,0 +1,10 @@
+--- gcc-4.1.2/gcc/config/arm/predicates.md-original 2007-06-13 12:25:35.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-06-13 12:25:42.000000000 +1000
+@@ -206,7 +206,6 @@
+ || mode == CC_DEQmode
+ || mode == CC_DLEmode
+ || mode == CC_DLTmode
+- || mode == CC_DGEmode
+ || mode == CC_DGTmode
+ || mode == CC_DLEUmode
+ || mode == CC_DLTUmode
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-predicates3.patch b/packages/gcc/gcc-4.2.1/arm-crunch-predicates3.patch
new file mode 100644
index 0000000000..99e1e6c88c
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-predicates3.patch
@@ -0,0 +1,116 @@
+diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md
+--- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:50:53.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:43:17.000000000 +1000
+@@ -7488,6 +7488,22 @@
+ arm_compare_op1);"
+ )
+
++;(define_expand "suneq"
++; [(set (match_operand:SI 0 "s_register_operand" "")
++; (uneq:SI (match_dup 1) (const_int 0)))]
++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
++; "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0,
++; arm_compare_op1);"
++;)
++
++;(define_expand "sltgt"
++; [(set (match_operand:SI 0 "s_register_operand" "")
++; (ltgt:SI (match_dup 1) (const_int 0)))]
++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
++; "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0,
++; arm_compare_op1);"
++;)
++
+ ;;; DO NOT add patterns for SUNEQ or SLTGT, these can't be represented with
+ ;;; simple ARM instructions.
+ ;
+@@ -10284,13 +10284,73 @@
+ "TARGET_ARM && arm_arch5e"
+ "pld\\t%a0")
+
++;; Special predication pattern for Maverick Crunch floating-point
++
++(define_cond_exec
++ [(match_operator 0 "maverick_comparison_operator"
++ [(match_operand:CCFP 1 "cc_register" "")
++ (const_int 0)])]
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ ""
++)
++
++;; Special predication pattern for Maverick Crunch - !CCFP
++
++(define_cond_exec
++ [(match_operator 0 "arm_comparison_operator"
++ [(match_operand:CC_NOOV 1 "cc_register" "")
++ (const_int 0)])]
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ ""
++)
++
++(define_cond_exec
++ [(match_operator 0 "arm_comparison_operator"
++ [(match_operand:CC_Z 1 "cc_register" "")
++ (const_int 0)])]
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ ""
++)
++
++(define_cond_exec
++ [(match_operator 0 "arm_comparison_operator"
++ [(match_operand:CC_SWP 1 "cc_register" "")
++ (const_int 0)])]
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ ""
++)
++
++(define_cond_exec
++ [(match_operator 0 "arm_comparison_operator"
++ [(match_operand:CC_C 1 "cc_register" "")
++ (const_int 0)])]
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ ""
++)
++
++(define_cond_exec
++ [(match_operator 0 "arm_comparison_operator"
++ [(match_operand:CC_N 1 "cc_register" "")
++ (const_int 0)])]
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ ""
++)
++
++(define_cond_exec
++ [(match_operator 0 "arm_comparison_operator"
++ [(match_operand:CC 1 "cc_register" "")
++ (const_int 0)])]
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ ""
++)
++
+ ;; General predication pattern
+
+ (define_cond_exec
+ [(match_operator 0 "arm_comparison_operator"
+ [(match_operand 1 "cc_register" "")
+ (const_int 0)])]
+- "TARGET_ARM"
++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+ ""
+ )
+
+diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md gcc-4.1.2/gcc/config/arm/predicates.md
+--- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md 2005-09-11 17:38:02.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-06-14 11:46:13.000000000 +1000
+@@ -172,7 +172,11 @@
+
+ ;; True for comparisons other than LTGT or UNEQ.
+ (define_special_predicate "arm_comparison_operator"
+ (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
++
++;; True for comparisons other than GE, GEU, UNLT, UNORDERED or ORDERED - TODO add LTGT and UNEQ - needs extra support elsewhere
++(define_special_predicate "maverick_comparison_operator"
++(match_code "eq,ne,le,lt,gt,gtu,leu,ltu,unle,unge,ungt"))
+
+ (define_special_predicate "minmax_operator"
+ (and (match_code "smin,smax,umin,umax")
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-saveregs.patch b/packages/gcc/gcc-4.2.1/arm-crunch-saveregs.patch
new file mode 100644
index 0000000000..531ae86610
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-saveregs.patch
@@ -0,0 +1,153 @@
+diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c gcc-4.1.2/gcc/config/arm/arm.c
+--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c 2007-05-09 16:32:29.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-15 09:39:41.000000000 +1000
+@@ -426,7 +435,7 @@
+ #define FL_STRONG (1 << 8) /* StrongARM */
+ #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
+ #define FL_XSCALE (1 << 10) /* XScale */
+-#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
++#define FL_CIRRUS (1 << 11) /* Cirrus Crunch coprocessor. */
+ #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
+ media instructions. */
+ #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
+@@ -490,7 +499,7 @@
+ /* Nonzero if this chip is a StrongARM. */
+ int arm_tune_strongarm = 0;
+
+-/* Nonzero if this chip is a Cirrus variant. */
++/* Nonzero if this chip supports Cirrus Crunch coprocessor. */
+ int arm_arch_cirrus = 0;
+
+ /* Nonzero if this chip supports Intel Wireless MMX technology. */
+@@ -1184,7 +1193,8 @@
+ else
+ */
+ if (arm_arch_cirrus)
+- arm_fpu_arch = FPUTYPE_MAVERICK;
++ /* Cirrus crunch coprocessor still requires soft-float division. */
++ arm_fpu_arch = FPUTYPE_MAVERICK;
+ else
+ arm_fpu_arch = FPUTYPE_FPA_EMU2;
+ #endif
+@@ -1567,6 +1577,9 @@
+ if (regs_ever_live[regno] && !call_used_regs[regno])
+ return 0;
+
++ if (TARGET_MAVERICK)
++ return 0;
++
+ if (TARGET_REALLY_IWMMXT)
+ for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
+ if (regs_ever_live[regno] && ! call_used_regs [regno])
+@@ -9775,7 +9886,19 @@
+ /* This variable is for the Virtual Frame Pointer, not VFP regs. */
+ int vfp_offset = offsets->frame;
+
+- if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
++ if (arm_fpu_arch == FPUTYPE_MAVERICK)
++ {
++ for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--)
++ if (regs_ever_live[reg] && !call_used_regs[reg])
++ {
++ floats_offset += 8; /* more problems - futaris? */
++ /* if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) */
++ asm_fprintf (f, "\tnop\n");
++ asm_fprintf (f, "\tcfldrd\tmvd%d, [%r, #-%d]\n",
++ reg - FIRST_CIRRUS_FP_REGNUM, FP_REGNUM, floats_offset - vfp_offset);
++ }
++ }
++ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
+ {
+ for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
+ if (regs_ever_live[reg] && !call_used_regs[reg])
+@@ -9924,7 +10047,18 @@
+ output_add_immediate (operands);
+ }
+
+- if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
++ if (arm_fpu_arch == FPUTYPE_MAVERICK)
++ { /* order changed - futaris */
++ for (reg = FIRST_CIRRUS_FP_REGNUM; reg <= LAST_CIRRUS_FP_REGNUM; reg++)
++ if (regs_ever_live[reg] && !call_used_regs[reg])
++ {
++ /* if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) */
++ asm_fprintf (f, "\tnop\n");
++ asm_fprintf (f, "\tcfldrd\tmvd%u, [%r], #8\n",
++ reg - FIRST_CIRRUS_FP_REGNUM, SP_REGNUM);
++ } /* reg problems - futaris */
++ }
++ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
+ {
+ for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
+ if (regs_ever_live[reg] && !call_used_regs[reg])
+@@ -10429,9 +10563,19 @@
+ if (! IS_VOLATILE (func_type))
+ {
++ /* Space for saved MAVERICK registers. */
++ if (arm_fpu_arch == FPUTYPE_MAVERICK)
++ {
++ for (regno = FIRST_CIRRUS_FP_REGNUM; regno <= LAST_CIRRUS_FP_REGNUM; regno++)
++ if (regs_ever_live[regno] && !call_used_regs[regno])
++ saved += 8; // 8 in 3.4.3 patch - futaris;
++ }
++ else
+ /* Space for saved FPA registers. */
++ {
+ for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
+ if (regs_ever_live[regno] && ! call_used_regs[regno])
+ saved += 12;
++ }
+
+ /* Space for saved VFP registers. */
+ if (TARGET_HARD_FLOAT && TARGET_VFP)
+@@ -10739,7 +10882,19 @@
+
+ /* Save any floating point call-saved registers used by this
+ function. */
+- if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
++ if (arm_fpu_arch == FPUTYPE_MAVERICK)
++ {
++ for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--)
++ if (regs_ever_live[reg] && !call_used_regs[reg])
++ {
++ insn = gen_rtx_PRE_DEC (DFmode, stack_pointer_rtx); /* think these causes problems */
++ insn = gen_rtx_MEM (DFmode, insn);
++ insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
++ gen_rtx_REG (DFmode, reg)));
++ RTX_FRAME_RELATED_P (insn) = 1; saved_regs += 8; /* added by futaris */
++ }
++ }
++ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
+ {
+ for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
+ if (regs_ever_live[reg] && !call_used_regs[reg])
+@@ -15179,6 +15331,9 @@
+ if (IS_FPA_REGNUM (regno))
+ return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
+
++ if (IS_CIRRUS_REGNUM (regno))
++ return 28 + regno - FIRST_CIRRUS_FP_REGNUM;
++
+ if (IS_VFP_REGNUM (regno))
+ return 64 + regno - FIRST_VFP_REGNUM;
+
+--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-28 15:42:36.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-28 15:42:48.000000000 +1000
+@@ -9800,7 +9800,7 @@
+ return arm_output_epilogue (next_nonnote_insn (insn));
+ "
+ ;; Length is absolute worst case
+- [(set_attr "length" "44")
++ [(set_attr "length" "108")
+ (set_attr "type" "block")
+ ;; We don't clobber the conditions, but the potential length of this
+ ;; operation is sufficient to make conditionalizing the sequence
+@@ -9818,7 +9818,7 @@
+ return thumb_unexpanded_epilogue ();
+ "
+ ; Length is absolute worst case
+- [(set_attr "length" "44")
++ [(set_attr "length" "108")
+ (set_attr "type" "block")
+ ;; We don't clobber the conditions, but the potential length of this
+ ;; operation is sufficient to make conditionalizing the sequence
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-scc.patch b/packages/gcc/gcc-4.2.1/arm-crunch-scc.patch
new file mode 100644
index 0000000000..d1330f2543
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-scc.patch
@@ -0,0 +1,38 @@
+--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-13 12:38:06.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-13 12:40:07.000000000 +1000
+@@ -7375,7 +7375,7 @@
+ (define_expand "sge"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (ge:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
++ "TARGET_ARM"
+ "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
+ )
+
+@@ -7434,7 +7434,7 @@
+ (define_expand "sunordered"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (unordered:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0,
+ arm_compare_op1);"
+ )
+@@ -7442,7 +7442,7 @@
+ (define_expand "sordered"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (ordered:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0,
+ arm_compare_op1);"
+ )
+@@ -7467,7 +7467,7 @@
+ (define_expand "sunlt"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (unlt:SI (match_dup 1) (const_int 0)))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
+ "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0,
+ arm_compare_op1);"
+ )
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-truncsi-disable-new.patch b/packages/gcc/gcc-4.2.1/arm-crunch-truncsi-disable-new.patch
new file mode 100644
index 0000000000..6dea43fa7c
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-truncsi-disable-new.patch
@@ -0,0 +1,33 @@
+--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:46:22.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:46:41.000000000 +1000
+@@ -337,13 +337,14 @@
+ "cfcvt64d%?\\t%V0, %V1"
+ [(set_attr "cirrus" "normal")])
+
++; appears to be buggy
+ (define_insn "cirrus_truncsfsi2"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v"))))
+ (clobber (match_scratch:DF 2 "=v"))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
+ [(set_attr "length" "8")
+ (set_attr "cirrus" "normal")]
+ )
+
+--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:46:56.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:48:08.000000000 +1000
+@@ -3151,10 +3151,11 @@
+ }
+ ")
+
++; appears to be buggy for MAVERICK
+ (define_expand "fix_truncsfsi2"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))]
+- "TARGET_ARM && TARGET_HARD_FLOAT"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "
+ if (TARGET_MAVERICK)
+ {
diff --git a/packages/gcc/gcc-4.2.1/arm-crunch-truncsi-disable.patch b/packages/gcc/gcc-4.2.1/arm-crunch-truncsi-disable.patch
new file mode 100644
index 0000000000..a5d791a0a4
--- /dev/null
+++ b/packages/gcc/gcc-4.2.1/arm-crunch-truncsi-disable.patch
@@ -0,0 +1,56 @@
+--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:46:22.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:46:41.000000000 +1000
+@@ -337,21 +337,23 @@
+ "cfcvt64d%?\\t%V0, %V1"
+ [(set_attr "cirrus" "normal")])
+
++; appears to be buggy
+ (define_insn "cirrus_truncsfsi2"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v"))))
+ (clobber (match_scratch:DF 2 "=v"))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
+ [(set_attr "length" "8")
+ (set_attr "cirrus" "normal")]
+ )
+
++; appears to be buggy
+ (define_insn "cirrus_truncdfsi2"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v"))))
+ (clobber (match_scratch:DF 2 "=v"))]
+- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
+ [(set_attr "length" "8")
+ (set_attr "cirrus" "normal")]
+--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:46:56.000000000 +1000
++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:48:08.000000000 +1000
+@@ -3151,10 +3151,11 @@
+ }
+ ")
+
++; appears to be buggy for MAVERICK
+ (define_expand "fix_truncsfsi2"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))]
+- "TARGET_ARM && TARGET_HARD_FLOAT"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "
+ if (TARGET_MAVERICK)
+ {
+@@ -3167,10 +3168,11 @@
+ }
+ ")
+
++; appears to be buggy for MAVERICK
+ (define_expand "fix_truncdfsi2"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))]
+- "TARGET_ARM && TARGET_HARD_FLOAT"
++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "
+ if (TARGET_MAVERICK)
+ {
diff --git a/packages/gcc/gcc-cross_4.2.1.bb b/packages/gcc/gcc-cross_4.2.1.bb
index 657e5afaca..b11259676e 100644
--- a/packages/gcc/gcc-cross_4.2.1.bb
+++ b/packages/gcc/gcc-cross_4.2.1.bb
@@ -5,7 +5,7 @@ inherit cross
FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/gcc-${PV}"
# NOTE: split PR. If the main .oe changes something that affects its *build*
# remember to increment this one too.
-PR = "r2"
+PR = "r3"
DEPENDS = "virtual/${TARGET_PREFIX}binutils virtual/${TARGET_PREFIX}libc-for-gcc gmp-native mpfr-native"
PROVIDES = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++"
diff --git a/packages/gcc/gcc_4.2.1.bb b/packages/gcc/gcc_4.2.1.bb
index 0ebc117d2a..11599444f8 100644
--- a/packages/gcc/gcc_4.2.1.bb
+++ b/packages/gcc/gcc_4.2.1.bb
@@ -1,4 +1,4 @@
-PR = "r1"
+PR = "r2"
DESCRIPTION = "The GNU cc and gcc C compilers."
HOMEPAGE = "http://www.gnu.org/software/gcc/"
SECTION = "devel"
@@ -36,6 +36,23 @@ SRC_URI = "ftp://ftp.gnu.org/pub/gnu/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \
file://unbreak-armv4t.patch;patch=1 \
file://fix-ICE-in-arm_unwind_emit_set.diff;patch=1 \
file://cache-amnesia.patch;patch=1 \
+ file://arm-crunch-saveregs.patch;patch=1 \
+ file://arm-crunch-20000320.patch;patch=1 \
+ file://arm-crunch-compare.patch;patch=1 \
+ file://arm-crunch-compare-unordered.patch;patch=1 \
+ file://arm-crunch-compare-geu.patch;patch=1 \
+ file://arm-crunch-eabi-ieee754.patch;patch=1 \
+ file://arm-crunch-eabi-ieee754-div.patch;patch=1 \
+ file://arm-crunch-64bit-disable0.patch;patch=1 \
+ file://arm-crunch-offset.patch;patch=1 \
+ file://arm-crunch-fp_consts.patch;patch=1 \
+ file://arm-crunch-neg2.patch;patch=1 \
+ file://arm-crunch-predicates3.patch;patch=1 \
+ file://arm-crunch-cfcvtds-disable.patch;patch=1 \
+ file://arm-crunch-floatsi-disable.patch;patch=1 \
+ file://arm-crunch-truncsi-disable.patch;patch=1 \
+ file://arm-crunch-cfcvt64-disable.patch;patch=1 \
+ file://arm-crunch-cirrus-bugfixes.patch;patch=1 \
"
SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch;patch=1 "
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 01:32:02 +0000