import clean BK tree at cset 1.3670

1 files changed, 174 insertions, 0 deletions

diff --git a/packages/gcc/gcc-3.3.3/arm-xscale.patch b/packages/gcc/gcc-3.3.3/arm-xscale.patch
index e69de29bb2..9ac8f5b688 100644
--- a/packages/gcc/gcc-3.3.3/arm-xscale.patch
+++ b/packages/gcc/gcc-3.3.3/arm-xscale.patch
@@ -0,0 +1,174 @@
+--- gcc/config/arm/arm.c.orig	2004-03-11 14:50:36.000000000 +0000
++++ gcc/config/arm/arm.c	2004-03-11 14:58:05.000000000 +0000
+@@ -275,7 +275,10 @@
+ int arm_is_strong = 0;
+ 
+ /* Nonzero if this chip is an XScale.  */
+-int arm_is_xscale = 0;
++int arm_arch_xscale = 0;
++
++/* Nonzero if tuning for XScale  */
++int arm_tune_xscale = 0;
+ 
+ /* Nonzero if this chip is an ARM6 or an ARM7.  */
+ int arm_is_6_or_7 = 0;
+@@ -684,13 +687,14 @@
+   arm_arch4         = (insn_flags & FL_ARCH4) != 0;
+   arm_arch5         = (insn_flags & FL_ARCH5) != 0;
+   arm_arch5e        = (insn_flags & FL_ARCH5E) != 0;
+-  arm_is_xscale     = (insn_flags & FL_XSCALE) != 0;
++  arm_arch_xscale   = (insn_flags & FL_XSCALE) != 0;
+ 
+   arm_ld_sched      = (tune_flags & FL_LDSCHED) != 0;
+   arm_is_strong     = (tune_flags & FL_STRONG) != 0;
+   thumb_code	    = (TARGET_ARM == 0);
+   arm_is_6_or_7     = (((tune_flags & (FL_MODE26 | FL_MODE32))
+ 		       && !(tune_flags & FL_ARCH4))) != 0;
++  arm_tune_xscale   = (tune_flags & FL_XSCALE) != 0;
+ 
+   /* Default value for floating point code... if no co-processor
+      bus, then schedule for emulated floating point.  Otherwise,
+@@ -762,7 +766,7 @@
+   if (optimize_size || (tune_flags & FL_LDSCHED))
+     arm_constant_limit = 1;
+   
+-  if (arm_is_xscale)
++  if (arm_arch_xscale)
+     arm_constant_limit = 2;
+ 
+   /* If optimizing for size, bump the number of instructions that we
+@@ -2978,7 +2982,7 @@
+ 
+   /* Some true dependencies can have a higher cost depending
+      on precisely how certain input operands are used.  */
+-  if (arm_is_xscale
++  if (arm_tune_xscale
+       && REG_NOTE_KIND (link) == 0
+       && recog_memoized (insn) < 0
+       && recog_memoized (dep) < 0)
+@@ -4425,7 +4429,7 @@
+ 
+      As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
+      for counts of 3 or 4 regs.  */
+-  if (arm_is_xscale && count <= 2 && ! optimize_size)
++  if (arm_tune_xscale && count <= 2 && ! optimize_size)
+     {
+       rtx seq;
+       
+@@ -4492,8 +4496,8 @@
+ 
+   /* See arm_gen_load_multiple for discussion of
+      the pros/cons of ldm/stm usage for XScale.  */
+-  if (arm_is_xscale && count <= 2 && ! optimize_size)
++  if (arm_tune_xscale && count <= 2 && ! optimize_size)
+     {
+       rtx seq;
+       
+
+--- gcc/config/arm/arm.h	23 Apr 2003 16:39:30 -0000	1.189
++++ gcc/config/arm/arm.h	14 May 2003 21:26:33 -0000
+@@ -610,7 +610,10 @@ extern int arm_is_strong;
+ extern int arm_is_cirrus;
+ 
+ /* Nonzero if this chip is an XScale.  */
+-extern int arm_is_xscale;
++extern int arm_arch_xscale;
++
++/* Nonzero if tuning for XScale  */
++extern int arm_tune_xscale;
+ 
+ /* Nonzero if this chip is an ARM6 or an ARM7.  */
+ extern int arm_is_6_or_7;
+@@ -728,7 +731,7 @@ extern int arm_is_6_or_7;
+ #define BIGGEST_ALIGNMENT  32
+ 
+ /* Make strings word-aligned so strcpy from constants will be faster.  */
+-#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
++#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_arch_xscale ? 1 : 2)
+     
+ #define CONSTANT_ALIGNMENT(EXP, ALIGN)				\
+   ((TREE_CODE (EXP) == STRING_CST				\
+@@ -2119,8 +2122,8 @@ do {							\
+ #define MOVE_MAX 4
+ 
+ #undef  MOVE_RATIO
+-#define MOVE_RATIO (arm_is_xscale ? 4 : 2)
++#define MOVE_RATIO (arm_arch_xscale ? 4 : 2)
+ 
+ /* Define if operations between registers always perform the operation
+    on the full register even if a narrower mode is specified.  */
+
+--- gcc/config/arm/arm.md.old	2003-05-23 21:28:39.000000000 +0200
++++ gcc/config/arm/arm.md	2003-05-23 21:30:02.000000000 +0200
+@@ -120,7 +120,7 @@
+ 
+ ;; Operand number of an input operand that is shifted.  Zero if the
+ ;; given instruction does not shift one of its input operands.
+-(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_is_xscale")))
++(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale")))
+ (define_attr "shift" "" (const_int 0))
+ 
+ ; Floating Point Unit.  If we only have floating point emulation, then there
+@@ -1185,7 +1185,7 @@
+ 			 (const_int 0)))
+    (set (match_operand:SI 0 "s_register_operand" "=&r,&r")
+ 	(mult:SI (match_dup 2) (match_dup 1)))]
+-  "TARGET_ARM && !arm_is_xscale"
++  "TARGET_ARM && !arm_arch_xscale"
+   "mul%?s\\t%0, %2, %1"
+   [(set_attr "conds" "set")
+    (set_attr "type" "mult")]
+@@ -1198,7 +1198,7 @@
+ 			  (match_operand:SI 1 "s_register_operand" "%?r,0"))
+ 			 (const_int 0)))
+    (clobber (match_scratch:SI 0 "=&r,&r"))]
+-  "TARGET_ARM && !arm_is_xscale"
++  "TARGET_ARM && !arm_arch_xscale"
+   "mul%?s\\t%0, %2, %1"
+   [(set_attr "conds" "set")
+    (set_attr "type" "mult")]
+@@ -1229,7 +1229,7 @@
+    (set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
+ 	(plus:SI (mult:SI (match_dup 2) (match_dup 1))
+ 		 (match_dup 3)))]
+-  "TARGET_ARM && !arm_is_xscale"
++  "TARGET_ARM && !arm_arch_xscale"
+   "mla%?s\\t%0, %2, %1, %3"
+   [(set_attr "conds" "set")
+    (set_attr "type" "mult")]
+@@ -1244,7 +1244,7 @@
+ 		  (match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
+ 	 (const_int 0)))
+    (clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
+-  "TARGET_ARM && !arm_is_xscale"
++  "TARGET_ARM && !arm_arch_xscale"
+   "mla%?s\\t%0, %2, %1, %3"
+   [(set_attr "conds" "set")
+    (set_attr "type" "mult")]
+@@ -1338,7 +1338,7 @@
+ 		  (match_operand:HI 1 "s_register_operand" "%r"))
+ 		 (sign_extend:SI
+ 		  (match_operand:HI 2 "s_register_operand" "r"))))]
+-  "TARGET_ARM && arm_is_xscale"
++  "TARGET_ARM && arm_arch_xscale"
+   "smulbb%?\\t%0, %1, %2"
+   [(set_attr "type" "mult")]
+ )
+@@ -1350,7 +1350,7 @@
+ 			   (match_operand:HI 2 "s_register_operand" "%r"))
+ 			  (sign_extend:SI
+ 			   (match_operand:HI 3 "s_register_operand" "r")))))]
+-  "TARGET_ARM && arm_is_xscale"
++  "TARGET_ARM && arm_arch_xscale"
+   "smlabb%?\\t%0, %2, %3, %1"
+   [(set_attr "type" "mult")]
+ )
+@@ -1363,7 +1363,7 @@
+ 	 	    (match_operand:HI 2 "s_register_operand" "%r"))
+ 		   (sign_extend:DI
+ 		    (match_operand:HI 3 "s_register_operand" "r")))))]
+-  "TARGET_ARM && arm_is_xscale"
++  "TARGET_ARM && arm_arch_xscale"
+   "smlalbb%?\\t%Q0, %R0, %2, %3"
+ [(set_attr "type" "mult")])
+