diff options
| author | Koen Kooi <koen@openembedded.org> | 2008-05-04 10:02:07 +0000 |
|---|---|---|
| committer | Koen Kooi <koen@openembedded.org> | 2008-05-04 10:02:07 +0000 |
| commit | a1217000556f36a7a2f877f0670331c58ed58c56 (patch) | |
| tree | 43059fce7eee4c21e9e640ecc2cc1c1e4ed9dea9 | |
| parent | 4361a83c42b1cbd41dcfcd62d5069bd12ef85e1c (diff) | |
linux-omap2 git: enable L2 caches on beagleboard in kernel, instead of depending on u-boot
| -rw-r--r-- | packages/linux/linux-omap2-git/beagleboard/l2-cache.patch | 38 | ||||
| -rw-r--r-- | packages/linux/linux-omap2_git.bb | 3 |
2 files changed, 40 insertions, 1 deletions
diff --git a/packages/linux/linux-omap2-git/beagleboard/l2-cache.patch b/packages/linux/linux-omap2-git/beagleboard/l2-cache.patch new file mode 100644 index 0000000000..7e93c29036 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/l2-cache.patch @@ -0,0 +1,38 @@ +diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig +index 15066c2..70f85c1 100644 +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -665,6 +665,12 @@ config CPU_CACHE_ROUND_ROBIN + Say Y here to use the predictable round-robin cache replacement + policy. Unless you specifically require this or are unsure, say N. + ++config CPU_L2CACHE_DISABLE ++ bool "Disable level 2 cache" ++ depends on CPU_V7 ++ help ++ Say Y here to disable the level 2 cache. If unsure, say N. ++ + config CPU_BPREDICT_DISABLE + bool "Disable branch prediction" + depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 +diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S +index a1d7331..432ddab 100644 +--- a/arch/arm/mm/proc-v7.S ++++ b/arch/arm/mm/proc-v7.S +@@ -181,6 +181,16 @@ __v7_setup: + mcr p15, 0, r4, c2, c0, 1 @ load TTB1 + mov r10, #0x1f @ domains 0, 1 = manager + mcr p15, 0, r10, c3, c0, 0 @ load domain access register ++#ifndef CONFIG_CPU_L2CACHE_DISABLE ++ @ L2 cache configuration in the L2 aux control register ++ mrc p15, 1, r10, c9, c0, 2 ++ bic r10, r10, #(1 << 16) @ L2 outer cache ++ mcr p15, 1, r10, c9, c0, 2 ++ @ L2 cache is enabled in the aux control register ++ mrc p15, 0, r10, c1, c0, 1 ++ orr r10, r10, #2 ++ mcr p15, 0, r10, c1, c0, 1 ++#endif + #endif + adr r5, v7_crval + ldmia r5, {r5, r6} diff --git a/packages/linux/linux-omap2_git.bb b/packages/linux/linux-omap2_git.bb index 330321536f..72635d12df 100644 --- a/packages/linux/linux-omap2_git.bb +++ b/packages/linux/linux-omap2_git.bb @@ -5,7 +5,7 @@ FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/linux-omap2-git/${MA SRCREV = "547ba9200727d2334f779cbf46ab62accb1281aa" PV = "2.6.25+git${SRCREV}" -PR = "r6" +PR = "r7" SRC_URI = "git://source.mvista.com/git/linux-omap-2.6.git;protocol=git \ @@ -13,6 +13,7 @@ SRC_URI = "git://source.mvista.com/git/linux-omap-2.6.git;protocol=git \ SRC_URI_append_beagleboard = " file://no-harry-potter.diff;patch=1 \ file://usb-timout.patch;patch=1 \ + file://l2-cache.patch;patch=1 \ " COMPATIBLE_MACHINE = "omap2430sdp|omap2420h4|beagleboard" |