ixp4xx-kernel: Added patchset and metadata for 2.6.16-rc2 kernel.

28 files changed, 24540 insertions, 0 deletions

diff --git a/packages/linux/ixp4xx-kernel/2.6.16/.mtn2git_empty b/packages/linux/ixp4xx-kernel/2.6.16/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/linux/ixp4xx-kernel/2.6.16/.mtn2git_empty
diff --git a/packages/linux/ixp4xx-kernel/2.6.16/05-patch-2.6.16-rc2-ide2 b/packages/linux/ixp4xx-kernel/2.6.16/05-patch-2.6.16-rc2-ide2
new file mode 100644
index 0000000000..3ea46331f6
--- /dev/null
+++ b/packages/linux/ixp4xx-kernel/2.6.16/05-patch-2.6.16-rc2-ide2
@@ -0,0 +1,16885 @@
+diff -u --exclude-from /usr/src/exclude --new-file --recursive linux.vanilla-2.6.16-rc2/arch/i386/pci/fixup.c linux-2.6.16-rc2/arch/i386/pci/fixup.c
+--- linux.vanilla-2.6.16-rc2/arch/i386/pci/fixup.c	2006-02-06 12:21:33.000000000 +0000
++++ linux-2.6.16-rc2/arch/i386/pci/fixup.c	2006-02-01 14:49:17.000000000 +0000
+@@ -74,52 +74,6 @@
+ }
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
+ 
+-static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
+-{
+-	int i;
+-
+-	/*
+-	 * PCI IDE controllers use non-standard I/O port decoding, respect it.
+-	 */
+-	if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
+-		return;
+-	DBG("PCI: IDE base address fixup for %s\n", pci_name(d));
+-	for(i=0; i<4; i++) {
+-		struct resource *r = &d->resource[i];
+-		if ((r->start & ~0x80) == 0x374) {
+-			r->start |= 2;
+-			r->end = r->start;
+-		}
+-	}
+-}
+-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
+-
+-static void __devinit  pci_fixup_ide_trash(struct pci_dev *d)
+-{
+-	int i;
+-
+-	/*
+-	 * Runs the fixup only for the first IDE controller
+-	 * (Shai Fultheim - shai@ftcon.com)
+-	 */
+-	static int called = 0;
+-	if (called)
+-		return;
+-	called = 1;
+-
+-	/*
+-	 * There exist PCI IDE controllers which have utter garbage
+-	 * in first four base registers. Ignore that.
+-	 */
+-	DBG("PCI: IDE base address trash cleared for %s\n", pci_name(d));
+-	for(i=0; i<4; i++)
+-		d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
+-}
+-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
+-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, pci_fixup_ide_trash);
+-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11, pci_fixup_ide_trash);
+-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_9, pci_fixup_ide_trash);
+-
+ static void __devinit  pci_fixup_latency(struct pci_dev *d)
+ {
+ 	/*
+diff -u --exclude-from /usr/src/exclude --new-file --recursive linux.vanilla-2.6.16-rc2/drivers/cdrom/cdrom.c linux-2.6.16-rc2/drivers/cdrom/cdrom.c
+--- linux.vanilla-2.6.16-rc2/drivers/cdrom/cdrom.c	2006-02-06 12:21:34.000000000 +0000
++++ linux-2.6.16-rc2/drivers/cdrom/cdrom.c	2006-01-17 16:34:19.000000000 +0000
+@@ -1131,7 +1131,8 @@
+ 	This ensures that the drive gets unlocked after a mount fails.  This 
+ 	is a goto to avoid bloating the driver with redundant code. */ 
+ clean_up_and_return:
+-	cdinfo(CD_OPEN, "open failed.\n"); 
++	/* Don't log this, its a perfectly normal user occurence */
++	/* cdinfo(CD_WARNING, "open failed.\n");  */
+ 	if (CDROM_CAN(CDC_LOCK) && cdi->options & CDO_LOCK) {
+ 			cdo->lock_door(cdi, 0);
+ 			cdinfo(CD_OPEN, "door unlocked.\n");
+diff -u --exclude-from /usr/src/exclude --new-file --recursive linux.vanilla-2.6.16-rc2/drivers/pci/probe.c linux-2.6.16-rc2/drivers/pci/probe.c
+--- linux.vanilla-2.6.16-rc2/drivers/pci/probe.c	2006-02-06 12:21:35.000000000 +0000
++++ linux-2.6.16-rc2/drivers/pci/probe.c	2006-02-01 15:56:28.000000000 +0000
+@@ -627,6 +627,7 @@
+ static int pci_setup_device(struct pci_dev * dev)
+ {
+ 	u32 class;
++	u16 cmd;
+ 
+ 	sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
+ 		dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
+@@ -654,6 +655,31 @@
+ 		pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
+ 		pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
+ 		pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
++
++		/*
++		 *	Do the ugly legacy mode stuff here rather than broken chip
++		 *	quirk code. Legacy mode ATA controllers have fixed
++		 *	addresses. These are not always echoed in BAR0-3, and
++		 *	BAR0-3 in a few cases contain junk!
++		 */
++		if (class == PCI_CLASS_STORAGE_IDE) {
++			u8 progif;
++			pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
++			if ((progif & 5) != 5) {
++				dev->resource[0].start = 0x1F0;
++				dev->resource[0].end = 0x1F7;
++				dev->resource[0].flags = IORESOURCE_IO;
++				dev->resource[1].start = 0x3F6;
++				dev->resource[1].end = 0x3F6;
++				dev->resource[1].flags = IORESOURCE_IO;
++				dev->resource[2].start = 0x170;
++				dev->resource[2].end = 0x177;
++				dev->resource[2].flags = IORESOURCE_IO;
++				dev->resource[3].start = 0x376;
++				dev->resource[3].end = 0x376;
++				dev->resource[3].flags = IORESOURCE_IO;
++			}
++		}
+ 		break;
+ 
+ 	case PCI_HEADER_TYPE_BRIDGE:		    /* bridge header */
+@@ -687,6 +713,10 @@
+ 		dev->class = PCI_CLASS_NOT_DEFINED;
+ 	}
+ 
++	/* BIOS enabled, so assume there is a good reason */
++	pci_read_config_word(dev, PCI_COMMAND, &cmd);
++	if(cmd & PCI_COMMAND_MASTER)
++		dev->is_enabled = 1;
+ 	/* We found a fine healthy device, go go go... */
+ 	return 0;
+ }
+diff -u --exclude-from /usr/src/exclude --new-file --recursive linux.vanilla-2.6.16-rc2/drivers/scsi/ata_generic.c linux-2.6.16-rc2/drivers/scsi/ata_generic.c
+--- linux.vanilla-2.6.16-rc2/drivers/scsi/ata_generic.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-rc2/drivers/scsi/ata_generic.c	2006-02-07 13:47:27.337665568 +0000
+@@ -0,0 +1,242 @@
++/*
++ *  ata_generic.c - Generic PATA/SATA controller driver.
++ *  Copyright 2005 Red Hat Inc <alan@redhat.com>, all rights reserved.
++ *
++ *  Elements from ide/pci/generic.c 
++ *	    Copyright (C) 2001-2002	Andre Hedrick <andre@linux-ide.org>
++ *	    Portions (C) Copyright 2002  Red Hat Inc <alan@redhat.com>
++ *
++ *  May be copied or modified under the terms of the GNU General Public License
++ *  
++ *  Driver for PCI IDE interfaces implementing the standard bus mastering
++ *  interface functionality. This assumes the BIOS did the drive set up and
++ *  tuning for us. By default we do not grab all IDE class devices as they
++ *  may have other drivers or need fixups to avoid problems. Instead we keep
++ *  a default list of stuff without documentation/driver that appears to
++ *  work.  
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/blkdev.h>
++#include <linux/delay.h>
++#include "scsi.h"
++#include <scsi/scsi_host.h>
++#include <linux/libata.h>
++
++#define DRV_NAME "generic"
++#define DRV_VERSION "0.1"
++
++/*
++ *	A generic parallel ATA driver using libata
++ */
++ 
++static void genpata_phy_reset(struct ata_port *ap)
++{
++	/* We know the BIOS already did the mode work. Don't tempt any
++	   one else to "fix" things */
++	ap->cbl = ATA_CBL_PATA80;
++	ata_port_probe(ap);
++	ata_bus_reset(ap);
++}
++
++/**
++ *	genpata_set_mode	-	mode setting
++ *	@ap: interface to set up
++ *
++ *	Use a non standard set_mode function. We don't want to be tuned.
++ *	The BIOS configured everything. Our job is not to fiddle. We
++ *	read the dma enabled bits from the PCI configuration of the device
++ *	and respect them. 
++ */
++ 
++static void genpata_set_mode(struct ata_port *ap)
++{
++	int dma_enabled;
++	int i;
++
++	/* Bits 5 and 6 indicate if DMA is active on master/slave */
++	dma_enabled = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
++	
++	for (i = 0; i < ATA_MAX_DEVICES; i++) {
++		struct ata_device *dev = &ap->device[i];
++		if (ata_dev_present(dev)) {
++			/* We don't really care */
++			dev->pio_mode = XFER_PIO_0;
++			dev->dma_mode = XFER_MW_DMA_0;
++			/* We do need the right mode information for DMA or PIO 
++			   and this comes from the current configuration flags */
++			/* FIXME: at some point in the future this should become
++			   a library helper which reads the disk modes from the
++			   disk as well */
++			if(dma_enabled & (1 << (5 + i))) {
++				dev->xfer_mode = XFER_MW_DMA_0;
++				dev->xfer_shift = ATA_SHIFT_MWDMA;
++				dev->flags &= ~ATA_DFLAG_PIO;
++			} else {
++				dev->xfer_mode = XFER_PIO_0;
++				dev->xfer_shift = ATA_SHIFT_PIO;
++				dev->flags |= ATA_DFLAG_PIO;
++			}
++		}
++	}
++}
++
++static struct scsi_host_template genpata_sht = {
++	.module			= THIS_MODULE,
++	.name			= DRV_NAME,
++	.ioctl			= ata_scsi_ioctl,
++	.queuecommand		= ata_scsi_queuecmd,
++	.eh_strategy_handler	= ata_scsi_error,
++	.can_queue		= ATA_DEF_QUEUE,
++	.this_id		= ATA_SHT_THIS_ID,
++	.sg_tablesize		= LIBATA_MAX_PRD,
++	.max_sectors		= ATA_MAX_SECTORS,
++	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
++	.emulated		= ATA_SHT_EMULATED,
++	.use_clustering		= ATA_SHT_USE_CLUSTERING,
++	.proc_name		= DRV_NAME,
++	.dma_boundary		= ATA_DMA_BOUNDARY,
++	.slave_configure	= ata_scsi_slave_config,
++	.bios_param		= ata_std_bios_param,
++//	.ordered_flush		= 1,
++};
++
++static struct ata_port_operations genpata_port_ops = {
++	.set_mode	= genpata_set_mode,
++	
++	.port_disable	= ata_port_disable,
++	.tf_load	= ata_tf_load,
++	.tf_read	= ata_tf_read,
++	.check_status 	= ata_check_status,
++	.exec_command	= ata_exec_command,
++	.dev_select 	= ata_std_dev_select,
++
++	.phy_reset	= genpata_phy_reset,
++
++	.bmdma_setup 	= ata_bmdma_setup,
++	.bmdma_start 	= ata_bmdma_start,
++	.bmdma_stop	= ata_bmdma_stop,
++	.bmdma_status 	= ata_bmdma_status,
++	
++	.data_xfer	= ata_pio_data_xfer,
++
++	.qc_prep 	= ata_qc_prep,
++	.qc_issue	= ata_qc_issue_prot,
++	.eng_timeout	= ata_eng_timeout,
++	.irq_handler	= ata_interrupt,
++	.irq_clear	= ata_bmdma_irq_clear,
++
++	.port_start	= ata_port_start,
++	.port_stop	= ata_port_stop,
++	.host_stop	= ata_host_stop
++};	
++	
++static int ide_generic_all;		/* Set to claim all devices */
++
++static int __init ide_generic_all_on(char *unused)
++{
++	ide_generic_all = 1;
++	printk(KERN_INFO "ATA generic will claim all unknown PCI IDE class storage controllers.\n");
++	return 1;
++}
++
++__setup("all-generic-ide", ide_generic_all_on);
++
++/**
++ *	pata_generic_init		-	attach generic IDE
++ *	@dev: PCI device found
++ *	@id: match entry
++ *
++ *	Called each time a matching IDE interface is found. We check if the
++ *	interface is one we wish to claim and if so we perform any chip 
++ *	specific hacks then let the ATA layer do the heavy lifting.
++ */
++ 
++static int pata_generic_init_one(struct pci_dev *dev, const struct pci_device_id *id)
++{
++	u16 command;
++	static struct ata_port_info info = {
++		.sht = &genpata_sht,
++		.host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_IRQ_MASK,
++		.pio_mask = 0x1f,
++		.mwdma_mask = 0x07,
++		.udma_mask = 0x3f,
++		.port_ops = &genpata_port_ops
++	};
++	static struct ata_port_info *port_info[2] = { &info, &info };
++		
++	/* Don't use the generic entry unless instructed to do so */
++	if (id->driver_data == 1 && ide_generic_all == 0)
++		return -ENODEV;
++
++	/* Devices that need care */
++	if (dev->vendor == PCI_VENDOR_ID_UMC &&
++	    dev->device == PCI_DEVICE_ID_UMC_UM8886A &&
++	    (!(PCI_FUNC(dev->devfn) & 1)))
++		return -ENODEV;
++
++	if (dev->vendor == PCI_VENDOR_ID_OPTI &&
++	    dev->device == PCI_DEVICE_ID_OPTI_82C558 &&
++	    (!(PCI_FUNC(dev->devfn) & 1)))
++		return -ENODEV;
++
++	/* Don't re-enable devices in generic mode or we will break some
++	   motherboards with disabled and unused IDE controllers */
++	pci_read_config_word(dev, PCI_COMMAND, &command);
++	if (!(command & PCI_COMMAND_IO))
++		return -ENODEV;
++		
++	if (dev->vendor == PCI_VENDOR_ID_AL)
++	    	ata_pci_clear_simplex(dev);
++
++	return ata_pci_init_one(dev, port_info, 2);
++}
++
++static struct pci_device_id pata_generic[] = {
++	{ PCI_DEVICE(PCI_VENDOR_ID_NS,PCI_DEVICE_ID_NS_87410),},
++	{ PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), },
++	{ PCI_DEVICE(PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), },
++	{ PCI_DEVICE(PCI_VENDOR_ID_UMC,    PCI_DEVICE_ID_UMC_UM8673F), }, 
++	{ PCI_DEVICE(PCI_VENDOR_ID_UMC,    PCI_DEVICE_ID_UMC_UM8886A), },
++	{ PCI_DEVICE(PCI_VENDOR_ID_UMC,    PCI_DEVICE_ID_UMC_UM8886BF), },
++	{ PCI_DEVICE(PCI_VENDOR_ID_HINT,   PCI_DEVICE_ID_HINT_VXPROII_IDE), },
++	{ PCI_DEVICE(PCI_VENDOR_ID_VIA,    PCI_DEVICE_ID_VIA_82C561), },
++	{ PCI_DEVICE(PCI_VENDOR_ID_OPTI,   PCI_DEVICE_ID_OPTI_82C558), },
++	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO), },
++	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), },
++	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2),  },
++	/* Must come last. If you add entries adjust this table appropriately */
++	{ PCI_ANY_ID,		PCI_ANY_ID,			   PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL, 1},
++	{ 0, },
++};
++
++static struct pci_driver pata_generic_pci_driver = {
++        .name 		= DRV_NAME,
++	.id_table	= pata_generic,
++	.probe 		= pata_generic_init_one,
++	.remove		= ata_pci_remove_one
++};
++
++static int __init pata_generic_init(void)
++{
++	return pci_module_init(&pata_generic_pci_driver);
++}
++
++
++static void __exit pata_generic_exit(void)
++{
++	pci_unregister_driver(&pata_generic_pci_driver);
++}
++
++
++MODULE_AUTHOR("Alan Cox");
++MODULE_DESCRIPTION("low-level driver for generic ATA");
++MODULE_LICENSE("GPL");
++MODULE_DEVICE_TABLE(pci, pata_generic);
++MODULE_VERSION(DRV_VERSION);
++
++module_init(pata_generic_init);
++module_exit(pata_generic_exit);
+diff -u --exclude-from /usr/src/exclude --new-file --recursive linux.vanilla-2.6.16-rc2/drivers/scsi/ata_piix.c linux-2.6.16-rc2/drivers/scsi/ata_piix.c
+--- linux.vanilla-2.6.16-rc2/drivers/scsi/ata_piix.c	2006-02-06 12:21:35.000000000 +0000
++++ linux-2.6.16-rc2/drivers/scsi/ata_piix.c	2006-02-06 12:28:58.000000000 +0000
+@@ -91,9 +91,10 @@
+ #include <linux/device.h>
+ #include <scsi/scsi_host.h>
+ #include <linux/libata.h>
++#include <linux/ata.h>
+ 
+ #define DRV_NAME	"ata_piix"
+-#define DRV_VERSION	"1.05"
++#define DRV_VERSION	"1.05-ac1"
+ 
+ enum {
+ 	PIIX_IOCFG		= 0x54, /* IDE I/O configuration register */
+@@ -122,6 +123,17 @@
+ 	piix4_pata		= 2,
+ 	ich6_sata		= 3,
+ 	ich6_sata_ahci		= 4,
++	ich0_pata		= 5,
++	ich2_pata		= 6,
++	ich3_pata		= 7,
++	ich4_pata		= 8,
++	cich_pata		= 9,
++	piix3_pata		= 10,
++	esb_pata		= 11,
++	ich_pata		= 12,
++	ich6_pata		= 13,
++	ich7_pata		= 14,
++	esb2_pata		= 15,
+ 
+ 	PIIX_AHCI_DEVICE	= 6,
+ };
+@@ -130,20 +142,69 @@
+ 				    const struct pci_device_id *ent);
+ 
+ static void piix_pata_phy_reset(struct ata_port *ap);
++static void ich_pata_phy_reset(struct ata_port *ap);
+ static void piix_sata_phy_reset(struct ata_port *ap);
+ static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
+ static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
++static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
+ 
+ static unsigned int in_module_init = 1;
+ 
+ static const struct pci_device_id piix_pci_tbl[] = {
+ #ifdef ATA_ENABLE_PATA
++#if 0
++	/* Neptune and earlier are simple PIO */
++	/* 430HX and friends. MWDMA */
++	{ 0x8086, 0x122e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix3_pata },
++	{ 0x8086, 0x1230, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix3_pata },
++	/* Intel PIIX3 */
++	{ 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix3_pata },
++#endif	
++	/* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
++	/* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
+ 	{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
+ 	{ 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
+ 	{ 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
++	/* Intel PIIX4 */
++	{ 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
++	/* Intel PIIX4 */
++	{ 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
++	/* Intel PIIX */
++	{ 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
++	/* Intel ICH (i810, i815, i840) UDMA 66*/
++	{ 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata },
++	/* Intel ICH0 : UDMA 33*/
++	{ 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich0_pata },
++	/* Intel ICH2M */
++	{ 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich2_pata },
++	/* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
++	{ 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich2_pata },
++	/*  Intel ICH3M */
++	{ 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich3_pata },
++	/* Intel ICH3 (E7500/1) UDMA 100 */
++	{ 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich3_pata },
++#if 0	
++	{ 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, dunno_pata },
++#endif	
++	/* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
++	{ 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich4_pata },
++	{ 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich4_pata },
++	/* Intel ICH5 */
++	{ 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
++	/* C-ICH (i810E2) */
++	{ 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, cich_pata },
++	/* ESB (855GME/875P + 6300ESB) UDMA 100  */	
++	{ 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_pata },
++	/* ICH6 (and 6) (i915) UDMA 100 */
++	{ 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_pata },
++	/* ICH7/7-R (i945, i975) UDMA 100*/
++	{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_pata },
++	{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb2_pata },
+ #endif
+-
+-	/* NOTE: The following PCI ids must be kept in sync with the
++	/*
++	 * SATA ports
++	 *
++	 * NOTE: The following PCI ids must be kept in sync with the
+ 	 * list in drivers/pci/quirks.c.
+ 	 */
+ 
+@@ -213,6 +274,40 @@
+ 	.bmdma_status		= ata_bmdma_status,
+ 	.qc_prep		= ata_qc_prep,
+ 	.qc_issue		= ata_qc_issue_prot,
++	
++	.data_xfer		= ata_pio_data_xfer,
++
++	.eng_timeout		= ata_eng_timeout,
++
++	.irq_handler		= ata_interrupt,
++	.irq_clear		= ata_bmdma_irq_clear,
++
++	.port_start		= ata_port_start,
++	.port_stop		= ata_port_stop,
++	.host_stop		= ata_host_stop,
++};
++
++static const struct ata_port_operations ich_pata_ops = {
++	.port_disable		= ata_port_disable,
++	.set_piomode		= piix_set_piomode,
++	.set_dmamode		= ich_set_dmamode,
++
++	.tf_load		= ata_tf_load,
++	.tf_read		= ata_tf_read,
++	.check_status		= ata_check_status,
++	.exec_command		= ata_exec_command,
++	.dev_select		= ata_std_dev_select,
++
++	.phy_reset		= ich_pata_phy_reset,
++
++	.bmdma_setup		= ata_bmdma_setup,
++	.bmdma_start		= ata_bmdma_start,
++	.bmdma_stop		= ata_bmdma_stop,
++	.bmdma_status		= ata_bmdma_status,
++	.qc_prep		= ata_qc_prep,
++	.qc_issue		= ata_qc_issue_prot,
++
++	.data_xfer		= ata_pio_data_xfer,
+ 
+ 	.eng_timeout		= ata_eng_timeout,
+ 
+@@ -242,6 +337,8 @@
+ 	.qc_prep		= ata_qc_prep,
+ 	.qc_issue		= ata_qc_issue_prot,
+ 
++	.data_xfer		= ata_pio_data_xfer,
++
+ 	.eng_timeout		= ata_eng_timeout,
+ 
+ 	.irq_handler		= ata_interrupt,
+@@ -259,13 +356,9 @@
+ 		.host_flags	= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
+ 				  PIIX_FLAG_CHECKINTR,
+ 		.pio_mask	= 0x1f,	/* pio0-4 */
+-#if 0
+ 		.mwdma_mask	= 0x06, /* mwdma1-2 */
+-#else
+-		.mwdma_mask	= 0x00, /* mwdma broken */
+-#endif
+ 		.udma_mask	= 0x3f, /* udma0-5 */
+-		.port_ops	= &piix_pata_ops,
++		.port_ops	= &ich_pata_ops,
+ 	},
+ 
+ 	/* ich5_sata */
+@@ -284,11 +377,7 @@
+ 		.sht		= &piix_sht,
+ 		.host_flags	= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
+ 		.pio_mask	= 0x1f,	/* pio0-4 */
+-#if 0
+ 		.mwdma_mask	= 0x06, /* mwdma1-2 */
+-#else
+-		.mwdma_mask	= 0x00, /* mwdma broken */
+-#endif
+ 		.udma_mask	= ATA_UDMA_MASK_40C,
+ 		.port_ops	= &piix_pata_ops,
+ 	},
+@@ -316,6 +405,116 @@
+ 		.udma_mask	= 0x7f,	/* udma0-6 */
+ 		.port_ops	= &piix_sata_ops,
+ 	},
++
++	/* ich0_pata */
++	{
++		.sht		= &piix_sht,
++		.host_flags	= ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
++		.pio_mask 	= 0x1f,	/* pio 0-4 */
++		.mwdma_mask	= 0x06, /* MWDMA0 is broken on chip */
++		.udma_mask	= 0x07, /* UDMA33 only */
++		.port_ops	= &ich_pata_ops,
++	},
++	
++	/* ich2_pata */
++	{
++		.sht		= &piix_sht,
++		.host_flags	= ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
++		.pio_mask 	= 0x1f,	/* pio 0-4 */
++		.mwdma_mask	= 0x06, /* MWDMA0 is broken on chip */
++		.udma_mask	= 0x1f, /* UDMA100 */
++		.port_ops	= &ich_pata_ops,
++	},
++	
++	/* ich3_pata */
++	{
++		.sht		= &piix_sht,
++		.host_flags	= ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
++		.pio_mask 	= 0x1f,	/* pio 0-4 */
++		.mwdma_mask	= 0x06, /* MWDMA0 is broken on chip */
++		.udma_mask	= 0x1f, /* UDMA100 */
++		.port_ops	= &ich_pata_ops,
++	},
++	
++	/* ich4_pata */
++	{
++		.sht		= &piix_sht,
++		.host_flags	= ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
++		.pio_mask 	= 0x1f,	/* pio 0-4 */
++		.mwdma_mask	= 0x06, /* Check: maybe 0x07  */
++		.udma_mask	= 0x1f, /* UDMA100 */
++		.port_ops	= &ich_pata_ops,
++	},
++
++	/* cich_pata */
++	{
++		.sht		= &piix_sht,
++		.host_flags	= ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
++		.pio_mask 	= 0x1f,	/* pio 0-4 */
++		.mwdma_mask	= 0x06, /* Check: maybe 0x07  */
++		.udma_mask	= 0x1f, /* UDMA100 */
++		.port_ops	= &ich_pata_ops,
++	},
++
++	/* piix3_pata */
++	{
++		.sht		= &piix_sht,
++		.host_flags	= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
++		.pio_mask	= 0x1f,	/* pio0-4 */
++		.mwdma_mask	= 0x07, /* mwdma1-2 */
++		.udma_mask	= ATA_UDMA_MASK_40C,
++		.port_ops	= &piix_pata_ops,
++	},
++
++	/* esb_pata */
++	{
++		.sht		= &piix_sht,
++		.host_flags	= ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
++		.pio_mask 	= 0x1f,	/* pio 0-4 */
++		.mwdma_mask	= 0x06, /* Check: maybe 0x07  */
++		.udma_mask	= 0x1f, /* UDMA100 */
++		.port_ops	= &piix_pata_ops,
++	},
++
++	/* ich_pata */
++	{
++		.sht		= &piix_sht,
++		.host_flags	= ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
++		.pio_mask 	= 0x1f,	/* pio 0-4 */
++		.mwdma_mask	= 0x06, /* Check: maybe 0x07  */
++		.udma_mask	= 0x07, /* UDMA66 */
++		.port_ops	= &ich_pata_ops,
++	},
++
++	/* ich6_pata */
++	{
++		.sht		= &piix_sht,
++		.host_flags	= ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
++		.pio_mask 	= 0x1f,	/* pio 0-4 */
++		.mwdma_mask	= 0x06, /* Check: maybe 0x07  */
++		.udma_mask	= 0x3f, /* UDMA133 */
++		.port_ops	= &ich_pata_ops,
++	},
++
++	/* ich7_pata */
++	{
++		.sht		= &piix_sht,
++		.host_flags	= ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
++		.pio_mask 	= 0x1f,	/* pio 0-4 */
++		.mwdma_mask	= 0x06, /* Check: maybe 0x07  */
++		.udma_mask	= 0x3f, /* UDMA133 */
++		.port_ops	= &ich_pata_ops,
++	},
++
++	/* esb2_pata */
++	{
++		.sht		= &piix_sht,
++		.host_flags	= ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
++		.pio_mask 	= 0x1f,	/* pio 0-4 */
++		.mwdma_mask	= 0x06, /* Check: maybe 0x07  */
++		.udma_mask	= 0x1f, /* UDMA100  -- CHECKME --*/
++		.port_ops	= &ich_pata_ops,
++	},
+ };
+ 
+ static struct pci_bits piix_enable_bits[] = {
+@@ -339,7 +538,7 @@
+  *	LOCKING:
+  *	None (inherited from caller).
+  */
+-static void piix_pata_cbl_detect(struct ata_port *ap)
++static void ich_pata_cbl_detect(struct ata_port *ap)
+ {
+ 	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
+ 	u8 tmp, mask;
+@@ -366,8 +565,9 @@
+  *	piix_pata_phy_reset - Probe specified port on PATA host controller
+  *	@ap: Port to probe
+  *
+- *	Probe PATA phy.
+- *
++ *	Probe PATA phy. Unlike the ICH we have no IOCFG register and
++ *	don't do UDMA66+ anyway.
++
+  *	LOCKING:
+  *	None (inherited from caller).
+  */
+@@ -381,11 +581,34 @@
+ 		printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
+ 		return;
+ 	}
++	ap->cbl = ATA_CBL_PATA40;
++	ata_port_probe(ap);
++	ata_bus_reset(ap);
++}
+ 
+-	piix_pata_cbl_detect(ap);
+ 
+-	ata_port_probe(ap);
++/**
++ *	ich_pata_phy_reset - Probe specified port on PATA host controller
++ *	@ap: Port to probe
++ *
++ *	Probe PATA phy.
++ *
++ *	LOCKING:
++ *	None (inherited from caller).
++ */
++
++static void ich_pata_phy_reset(struct ata_port *ap)
++{
++	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
+ 
++	if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
++		ata_port_disable(ap);
++		printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
++		return;
++	}
++
++	ich_pata_cbl_detect(ap);
++	ata_port_probe(ap);
+ 	ata_bus_reset(ap);
+ }
+ 
+@@ -481,6 +704,13 @@
+ 	unsigned int slave_port	= 0x44;
+ 	u16 master_data;
+ 	u8 slave_data;
++	u8 udma_enable;
++	int control = 0;
++	
++	/*
++	 *	See Intel Document 298600-004 for the timing programing rules
++	 *	for ICH controllers.
++	 */
+ 
+ 	static const	 /* ISP  RTC */
+ 	u8 timings[][2]	= { { 0, 0 },
+@@ -489,20 +719,30 @@
+ 			    { 2, 1 },
+ 			    { 2, 3 }, };
+ 
++	if (pio > 2)
++		control |= 1;	/* TIME1 enable */
++	if (ata_pio_need_iordy(adev))
++		control |= 2;	/* IE enable */
++
++	/* Intel specifies that the PPE functionality is for disk only */	   
++	if (adev->class == ATA_DEV_ATA)
++		control |= 4;	/* PPE enable */
++		
+ 	pci_read_config_word(dev, master_port, &master_data);
+ 	if (is_slave) {
++		/* Enable SITRE (seperate slave timing register) */
+ 		master_data |= 0x4000;
+-		/* enable PPE, IE and TIME */
+-		master_data |= 0x0070;
++		/* enable PPE1, IE1 and TIME1 as needed */
++		master_data |= (control << 4);
+ 		pci_read_config_byte(dev, slave_port, &slave_data);
+ 		slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
+-		slave_data |=
+-			(timings[pio][0] << 2) |
+-			(timings[pio][1] << (ap->hard_port_no ? 4 : 0));
++		/* Load the timing nibble for this slave */
++		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->hard_port_no ? 4 : 0);
+ 	} else {
++		/* Master keeps the bits in a different format */
+ 		master_data &= 0xccf8;
+-		/* enable PPE, IE and TIME */
+-		master_data |= 0x0007;
++		/* Enable PPE, IE and TIME as appropriate */
++		master_data |= control;
+ 		master_data |=
+ 			(timings[pio][0] << 12) |
+ 			(timings[pio][1] << 8);
+@@ -510,84 +750,165 @@
+ 	pci_write_config_word(dev, master_port, master_data);
+ 	if (is_slave)
+ 		pci_write_config_byte(dev, slave_port, slave_data);
++
++	/* Ensure the UDMA bit is off - it will be turned back on if
++	   UDMA is selected */
++	   
++	if(ap->udma_mask) {
++		pci_read_config_byte(dev, 0x48, &udma_enable);
++		udma_enable &= ~(1 << (2 * ap->hard_port_no + adev->devno));
++		pci_write_config_byte(dev, 0x48, udma_enable);
++	}
+ }
+ 
+ /**
+- *	piix_set_dmamode - Initialize host controller PATA PIO timings
++ *	do_piix_set_dmamode - Initialize host controller PATA PIO timings
+  *	@ap: Port whose timings we are confi