u-boot: add initial support for boc01 machine

8 files changed, 941 insertions, 0 deletions

diff --git a/packages/u-boot/u-boot-1.3.2/boc01/001_01_u-boot-1.3.2_SPI.patch b/packages/u-boot/u-boot-1.3.2/boc01/001_01_u-boot-1.3.2_SPI.patch
new file mode 100644
index 0000000000..36c3b9fe2f
--- /dev/null
+++ b/packages/u-boot/u-boot-1.3.2/boc01/001_01_u-boot-1.3.2_SPI.patch
@@ -0,0 +1,70 @@
+Index: u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c
+===================================================================
+--- u-boot-1.3.2.orig/board/freescale/mpc8313erdb/mpc8313erdb.c	2008-03-09 16:20:02.000000000 +0100
++++ u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c	2008-11-21 15:19:42.000000000 +0100
+@@ -28,6 +28,7 @@
+ #endif
+ #include <pci.h>
+ #include <mpc83xx.h>
++#include <spi.h> 
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+@@ -107,3 +108,33 @@
+ #endif
+ }
+ #endif
++
++
++/*
++ * The following are used to control the SPI chip selects for the SPI command.
++ */
++#ifdef CONFIG_HARD_SPI
++
++#define SPI_CS_MASK	0x80000000
++
++void spi_eeprom_chipsel(int cs)
++{
++	volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
++
++	if (cs)
++		iopd->dat &= ~SPI_CS_MASK;
++	else
++		iopd->dat |=  SPI_CS_MASK;
++}
++
++/*
++ * The SPI command uses this table of functions for controlling the SPI
++ * chip selects.
++ */
++spi_chipsel_type spi_chipsel[] = {
++	spi_eeprom_chipsel,
++};
++int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
++
++#endif /* CONFIG_HARD_SPI */
++
+Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h
+===================================================================
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h	2008-11-21 15:18:35.000000000 +0100
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h	2008-11-21 15:19:42.000000000 +0100
+@@ -369,6 +369,7 @@
+ #define CONFIG_CMD_DATE
+ #define CONFIG_CMD_PCI
+ #define CONFIG_CMD_NAND
++#define CONFIG_CMD_SPI
+ 
+ #if defined(CFG_RAMBOOT)
+     #undef CONFIG_CMD_ENV
+@@ -378,6 +379,11 @@
+ #define CONFIG_CMDLINE_EDITING 1
+ 
+ 
++/* SPI */
++#define CONFIG_MPC8XXX_SPI
++#define CONFIG_HARD_SPI			/* SPI with hardware support */
++#undef CONFIG_SOFT_SPI			/* SPI bit-banged */
++
+ /*
+  * Miscellaneous configurable options
+  */
diff --git a/packages/u-boot/u-boot-1.3.2/boc01/002_02_u-boot-1.3.2_GPIO.patch b/packages/u-boot/u-boot-1.3.2/boc01/002_02_u-boot-1.3.2_GPIO.patch
new file mode 100644
index 0000000000..b837618a91
--- /dev/null
+++ b/packages/u-boot/u-boot-1.3.2/boc01/002_02_u-boot-1.3.2_GPIO.patch
@@ -0,0 +1,162 @@
+Index: u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c
+===================================================================
+--- u-boot-1.3.2.orig/board/freescale/mpc8313erdb/mpc8313erdb.c	2008-11-21 15:29:50.000000000 +0100
++++ u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c	2008-11-21 15:30:25.000000000 +0100
+@@ -109,7 +109,42 @@
+ }
+ #endif
+ 
++#ifdef CONFIG_CMD_GPIO
++void gpio_set(unsigned char ucGpio)
++{
++	unsigned long ulMask=0;
++	volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
++	if(ucGpio<32)
++	{
++		ulMask=1<<(31-ucGpio);
++		iopd->dir |= ulMask;
++		iopd->dat |= ulMask;
++	}
++}
+ 
++void gpio_clear(unsigned char ucGpio)
++{
++	unsigned long ulMask=0;
++	volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
++	if(ucGpio<32)
++	{
++		ulMask=1<<(31-ucGpio);
++		iopd->dir |= ulMask;
++		iopd->dat &= ~ulMask;
++	}
++}
++
++char gpio_get(unsigned char ucGpio)
++{
++	unsigned long ulMask=0;
++	volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
++	if(ucGpio<32)
++	{
++		ulMask=1<<(31-ucGpio);
++	}
++	return (iopd->dat& ulMask)? 1:0;
++}
++#endif
+ /*
+  * The following are used to control the SPI chip selects for the SPI command.
+  */
+Index: u-boot-1.3.2/common/cmd_gpio.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ u-boot-1.3.2/common/cmd_gpio.c	2008-11-21 15:30:25.000000000 +0100
+@@ -0,0 +1,77 @@
++/*
++ * (C) Copyright 2001
++ * Alexandre Coffignal, CenoSYS, alexandre.coffignal@cenosys.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++	
++#include <common.h>
++#include <config.h>
++#include <command.h>
++extern void gpio_set(unsigned char ucGpio);
++extern void gpio_clear(unsigned char ucGpio);
++int do_gpio (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
++{
++	
++	unsigned char ucGpio;
++
++	if (argc < 3) 
++		goto usage;
++
++	ucGpio = simple_strtoul (argv[2], NULL, 10);
++
++	if (!strncmp(argv[1], "set", 3))
++	{
++		gpio_set(ucGpio);
++	}
++	else
++		
++		if (!strncmp(argv[1], "clear", 5))
++		{
++			gpio_clear(ucGpio);
++		}
++		else
++			if (!strncmp(argv[1], "get", 3))
++			{
++				printf("%s %s %d = %d\n",argv[0],argv[1],ucGpio, gpio_get(ucGpio));
++				return 0;
++			}
++			else
++				goto usage;
++
++	printf("%s %s %d\n",argv[0],argv[1],ucGpio);
++		
++	return 0;
++	
++usage :
++	printf ("Usage:\n%s\n", cmdtp->usage);
++	return 1;
++}	/* do_gpio() */
++
++/***************************************************/
++
++U_BOOT_CMD(
++	  gpio,	3,	1,	do_gpio,
++	  "gpio     - General Purpose Input/Output\n",
++	  "        - Set or clear General Purpose Output.\n"
++	  "<set/clear/get> - Set or clear General Purpose Output.\n"
++	  "<gpio> - number of gpio to be set/clear/get \n"
++);
++
+Index: u-boot-1.3.2/common/Makefile
+===================================================================
+--- u-boot-1.3.2.orig/common/Makefile	2008-03-09 16:20:02.000000000 +0100
++++ u-boot-1.3.2/common/Makefile	2008-11-21 15:30:25.000000000 +0100
+@@ -50,6 +50,7 @@
+ COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o
+ COBJS-$(CONFIG_CMD_DOC) += cmd_doc.o
+ COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o
++COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
+ COBJS-y += cmd_eeprom.o
+ COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o
+ COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o
+Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h
+===================================================================
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h	2008-11-21 15:29:50.000000000 +0100
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h	2008-11-21 15:30:53.000000000 +0100
+@@ -370,6 +370,7 @@
+ #define CONFIG_CMD_PCI
+ #define CONFIG_CMD_NAND
+ #define CONFIG_CMD_SPI
++#define CONFIG_CMD_GPIO
+ 
+ #if defined(CFG_RAMBOOT)
+     #undef CONFIG_CMD_ENV
+@@ -453,7 +454,7 @@
+ 
+ /* System IO Config */
+ #define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
+-#define CFG_SICRL	SICRL_USBDR			/* Enable Internal USB Phy  */
++#define CFG_SICRL	(SICRL_USBDR	|SICRL_LBC)		/* Enable Internal USB Phy  */
+ 
+ #define CFG_HID0_INIT	0x000000000
+ #define CFG_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
diff --git a/packages/u-boot/u-boot-1.3.2/boc01/004_01_u-boot-1.3.2_WATCHDOG.patch b/packages/u-boot/u-boot-1.3.2/boc01/004_01_u-boot-1.3.2_WATCHDOG.patch
new file mode 100644
index 0000000000..bb2e400264
--- /dev/null
+++ b/packages/u-boot/u-boot-1.3.2/boc01/004_01_u-boot-1.3.2_WATCHDOG.patch
@@ -0,0 +1,15 @@
+Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h
+===================================================================
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h	2008-11-21 15:30:53.000000000 +0100
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h	2008-11-21 15:32:10.000000000 +0100
+@@ -452,6 +452,10 @@
+ 	HRCWH_BIG_ENDIAN |\
+ 	HRCWH_LALE_NORMAL)
+ 
++
++#define CONFIG_WATCHDOG
++#define CFG_WATCHDOG_VALUE 0xFFFF
++
+ /* System IO Config */
+ #define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
+ #define CFG_SICRL	(SICRL_USBDR	|SICRL_LBC)		/* Enable Internal USB Phy  */
diff --git a/packages/u-boot/u-boot-1.3.2/boc01/006_01_u-boot-1.3.2_EEPROM_INTERSIL.patch b/packages/u-boot/u-boot-1.3.2/boc01/006_01_u-boot-1.3.2_EEPROM_INTERSIL.patch
new file mode 100644
index 0000000000..576b6c0d4e
--- /dev/null
+++ b/packages/u-boot/u-boot-1.3.2/boc01/006_01_u-boot-1.3.2_EEPROM_INTERSIL.patch
@@ -0,0 +1,16 @@
+Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h
+===================================================================
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h	2008-11-21 15:32:10.000000000 +0100
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h	2008-11-21 15:34:43.000000000 +0100
+@@ -268,9 +268,9 @@
+  */
+ #define CONFIG_CMD_EEPROM
+ #define CFG_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
+-#define CFG_I2C_EEPROM_ADDR		0x50	/* Atmel: AT24C256*/
++#define CFG_I2C_EEPROM_ADDR		0x57	/* Intersil 12024 (eeprom)*/
+ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10ms of delay */
+-#define CFG_EEPROM_PAGE_WRITE_BITS	6	/* 64-Byte Page Write Mode */
++#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 16-Byte Page Write Mode */
+ #define CFG_EEPROM_PAGE_WRITE_ENABLE
+ 
+ /* TSEC */
diff --git a/packages/u-boot/u-boot-1.3.2/boc01/007_01_u-boot-1.3.2_CAPSENSE.patch b/packages/u-boot/u-boot-1.3.2/boc01/007_01_u-boot-1.3.2_CAPSENSE.patch
new file mode 100644
index 0000000000..d4ce2f9df5
--- /dev/null
+++ b/packages/u-boot/u-boot-1.3.2/boc01/007_01_u-boot-1.3.2_CAPSENSE.patch
@@ -0,0 +1,342 @@
+Index: u-boot-1.3.2/common/cmd_capsense.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ u-boot-1.3.2/common/cmd_capsense.c	2008-11-21 15:35:49.000000000 +0100
+@@ -0,0 +1,90 @@
++/*
++ * (C) Copyright 2008
++ * Alexandre Coffignal, CénoSYS, alexandre.coffignal@cenosys.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ * 
++ * CapSense Express touch-sensing buttons
++ */
++
++#include <common.h>
++#include <config.h>
++#include <command.h>
++
++#include <capsense.h>
++#include <i2c.h>
++
++#define ARG_SENSOR_NUMBER	1
++int do_capsense (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
++{
++	int i;
++	unsigned char address = CONFIG_CAPSENSE_I2C_ADDRESS;
++	unsigned char sensors[] = CONFIG_CAPSENSE_SENSORS;
++	int old_bus,sensor_number;
++
++	/* switch to correct I2C bus */
++	old_bus = I2C_GET_BUS();
++	I2C_SET_BUS(CFG_CAPSENSE_BUS_NUM);
++
++	/*
++	 * Loop through sensors, read
++	 * state, and output it.
++	 */
++	if(argc==1)
++	{
++		for (i = 0; i < sizeof (sensors); i++)
++		{
++			printf ("CAPSENSE GP%d[%d]: %i\n",sensors[i]&CAPSENSE_INPUT_PORT_MASK?1:0, sensors[i]&CAPSENSE_INPUT_MASK, capsense_get_state(CONFIG_CAPSENSE_I2C_ADDRESS,sensors[i]) );
++		}
++
++	}
++	else
++	{
++		if(argc==2)
++		{
++			sensor_number=simple_strtoul (argv[ARG_SENSOR_NUMBER], NULL, 10);
++			if(sensor_number<sizeof (sensors))
++			{
++				printf ("GP%d[%d]: %i\n",sensors[sensor_number]&CAPSENSE_INPUT_PORT_MASK?1:0, sensors[sensor_number]&CAPSENSE_INPUT_MASK, capsense_get_state(CONFIG_CAPSENSE_I2C_ADDRESS,sensors[sensor_number]) );			
++			}
++			else
++			{
++				printf ("Usage:\n%s\n", cmdtp->usage);
++			}
++		}else
++		{
++			printf ("Usage:\n%s\n", cmdtp->usage);
++		}
++	}	
++
++	/* switch back to original I2C bus */
++	I2C_SET_BUS(old_bus);
++
++	return 0;
++}	/* do_capsense() */
++
++/***************************************************/
++
++U_BOOT_CMD(
++	  capsense,	2,	1,	do_capsense,
++	  "capsense - CapSense Express touch-sensing buttons\n",
++	  "        - Read state of the CapSense Express touch-sensing buttons.\n"
++	  "capsense : Read state of all the CapSense Express touch-sensing buttons.\n"
++	  "capsense [N] Read state of the CapSense Express touch-sensing buttons N.\n"
++	  );
+Index: u-boot-1.3.2/common/Makefile
+===================================================================
+--- u-boot-1.3.2.orig/common/Makefile	2008-11-21 15:30:25.000000000 +0100
++++ u-boot-1.3.2/common/Makefile	2008-11-21 15:35:49.000000000 +0100
+@@ -50,6 +50,7 @@
+ COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o
+ COBJS-$(CONFIG_CMD_DOC) += cmd_doc.o
+ COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o
++COBJS-$(CONFIG_CMD_CAPSENSE) += cmd_capsense.o
+ COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
+ COBJS-y += cmd_eeprom.o
+ COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o
+Index: u-boot-1.3.2/drivers/i2c/CY8C201xx.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ u-boot-1.3.2/drivers/i2c/CY8C201xx.c	2008-11-21 15:35:49.000000000 +0100
+@@ -0,0 +1,106 @@
++/*
++ * (C) Copyright 2008
++ * Alexandre Coffignal, CénoSYS, alexandre.coffignal@cenosys.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/*
++ * CapSense Express touch-sensing buttons
++ */
++
++#include <common.h>
++
++#ifdef CONFIG_CAPSENSE_CY8C201XX
++
++#include <i2c.h>
++#include <capsense.h>
++
++int capsense_read(int address, int reg)
++{
++    int dlen;
++    uchar data[2];
++
++    /*
++     * Validate 'reg' param
++     */
++    if((reg < 0) || (reg > 0x8C))
++    	return -1;
++
++     /*
++     * Prepare to handle 1 byte result.
++     */
++	dlen = 1;
++
++    /*
++     * Now try to read the register.
++     */
++    if (i2c_read(address, reg, 1, data, dlen) != 0)
++    	return -1;
++
++    return (int)data[0];
++} /* capsense_read() */
++
++
++int capsense_write(int address, int reg, int val)
++{
++    int dlen;
++    uchar data[2];
++
++    /*
++     * Validate 'reg' param
++     */
++    if((reg < 0) || (reg > 0x8C))
++    	return -1;
++
++    /*
++     * Handle 1 byte values.
++     */
++ 	dlen = 1;
++	data[0] = (char)(val & 0xff);
++ 
++    /*
++     * Write value to register.
++     */
++    if (i2c_write(address, reg, 1, data, dlen) != 0)
++    	return 1;
++
++    return 0;
++} /* capsense_write() */
++
++int capsense_get_state(int address,int sensors)
++{
++	int port_values=0;
++	int input=sensors&CAPSENSE_INPUT_MASK;
++	
++	if(sensors&CAPSENSE_INPUT_PORT_MASK)
++	{
++		/*INPUT_PORT 1*/
++		port_values=capsense_read(address,CAPSENSE_READ_STATUS_REG+1);
++	}
++	else
++	{
++		/*INPUT_PORT 0*/	
++		port_values=capsense_read(address,CAPSENSE_READ_STATUS_REG);
++	}
++
++	return port_values&(1<<input)?1:0;
++}/* capsense_get_state() */
++
++#endif /* CONFIG_CAPSENSE_CY8C201XX */
+Index: u-boot-1.3.2/drivers/i2c/Makefile
+===================================================================
+--- u-boot-1.3.2.orig/drivers/i2c/Makefile	2008-03-09 16:20:02.000000000 +0100
++++ u-boot-1.3.2/drivers/i2c/Makefile	2008-11-21 15:35:49.000000000 +0100
+@@ -29,6 +29,7 @@
+ COBJS-y += omap1510_i2c.o
+ COBJS-y += omap24xx_i2c.o
+ COBJS-y += tsi108_i2c.o
++COBJS-y += CY8C201xx.o
+ 
+ COBJS	:= $(COBJS-y)
+ SRCS 	:= $(COBJS:.o=.c)
+Index: u-boot-1.3.2/include/capsense.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ u-boot-1.3.2/include/capsense.h	2008-11-21 15:35:49.000000000 +0100
+@@ -0,0 +1,90 @@
++/*
++ * (C) Copyright 2008
++ * Alexandre Coffignal, CénoSYS, alexandre.coffignal@cenosys.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/*
++ * CapSense Express touch-sensing buttons.
++ */
++#ifndef _CAPSENSE_H_
++#define _CAPSENSE_H_
++
++#if defined(CONFIG_CAPSENSE_CY8C201XX)
++
++#define CONFIG_CAPSENSE				/* We have a Capsense */
++
++#ifndef CONFIG_CAPSENSE_SENSORS
++#define CONFIG_CAPSENSE_SENSORS			{0x02,0x84,0x83} /*config for CY3218-CAPEXP1*/
++#endif
++#endif /* CONFIG_CAPSENSE_SENSORS */
++
++extern int capsense_read(int address, int reg);
++extern int capsense_write(int address, int reg, int val);
++extern int capsense_get_state(int address,int sensors);
++#endif
++
++#if !defined(CFG_CAPSENSE_BUS_NUM)
++#define CFG_CAPSENSE_BUS_NUM		0
++
++//-----------------------------------------------
++// Register Map and corresponding constants
++//-----------------------------------------------
++
++
++#define CAPSENSE_STATUS_PORT_REG                          (0x02)
++#define CAPSENSE_OUTPUT_PORT_REG                          (0x04)
++#define CAPSENSE_ENABLE_CAPSENSE_REG                      (0x06)
++#define CAPSENSE_ENABLE_GPIO_REG                          (0x08)
++#define CAPSENSE_INVERSION_PORT_REG                       (0x0A) 
++#define CAPSENSE_INTERRUPT_MASK_REG                       (0x0C)  
++#define CAPSENSE_PORT_STATUS_REG                          (0x0E)
++#define CAPSENSE_DRIVE_MODE_REG                           (0x10)
++#define CAPSENSE_OPER_SELECT_0_REG                        (0x1C) 
++#define CAPSENSE_OPER_SELECT_1_REG                        (0x35)   
++#define CAPSENSE_NOISE_THRESHOLD_REG                      (0x4E)
++#define CAPSENSE_SETTLING_TIME_REG                        (0x50)
++#define CAPSENSE_EXT_CAP_REG                              (0x51)
++#define CAPSENSE_SNS_RST_REG                              (0x51)
++#define CAPSENSE_CLK_SEL_REG                              (0x51)
++#define CAPSENSE_HYSTERESIS_REG                           (0x52)
++#define CAPSENSE_DEBOUNCE_REG                             (0x53)
++#define CAPSENSE_NEG_NOISE_THRESHOLD_REG                  (0x54)
++#define CAPSENSE_FT_PORT_0_REG                            (0x61)
++#define CAPSENSE_FT_PORT_1_REG                            (0x66)
++#define CAPSENSE_IDAC_SETTING_PORT_0_REG                  (0x6B)
++#define CAPSENSE_IDAC_SETTING_PORT_1_REG                  (0x70)
++#define CAPSENSE_SLIDER_CONFIGURATION_REG                 (0x75)
++#define CAPSENSE_SLIDER_RESOLUTION_REG                    (0x77)
++#define CAPSENSE_DEVICE_ID_REG                            (0x7A)
++#define CAPSENSE_DEVICAPSENSE_REG                         (0x7C)
++#define CAPSENSE_SLEEP_CONTROL_PIN_REG                    (0x7E)
++#define CAPSENSE_SLEEP_CONTROL_REG                        (0x7F)
++#define CAPSENSE_STAY_AWAKE_CNTR_REG                      (0x80)
++#define CAPSENSE_BUTTON_SEL_REG                           (0x81)
++#define CAPSENSE_BASELINE_REG                             (0x82)
++#define CAPSENSE_READ_STATUS_REG                          (0x88)
++#define CAPSENSE_CENTROID_REG                             (0x8A)
++
++#define CAPSENSE_COMMAND_REG                              (0xA0)
++
++#define CAPSENSE_INPUT_PORT_MASK						  (0x10)
++#define CAPSENSE_INPUT_MASK							  	(0x7)
++#endif /* _CAPSENSE_H_ */
+Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h
+===================================================================
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h	2008-11-21 15:34:43.000000000 +0100
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h	2008-11-21 15:35:49.000000000 +0100
+@@ -380,6 +380,12 @@
+ #define CONFIG_CMDLINE_EDITING 1
+ 
+ 
++/*Capsense touch sensing buttons*/
++#define CONFIG_CMD_CAPSENSE
++#define CONFIG_CAPSENSE_CY8C201XX		1
++#define CONFIG_CAPSENSE_I2C_ADDRESS		0x25
++#define CONFIG_CAPSENSE_SENSORS			{0x02,0x14,0x13} // GP0[2] GP1[4] GP1[3]
++
+ /* SPI */
+ #define CONFIG_MPC8XXX_SPI
+ #define CONFIG_HARD_SPI			/* SPI with hardware support */
diff --git a/packages/u-boot/u-boot-1.3.2/boc01/008_02_u-boot-1.3.2_TSEC.patch b/packages/u-boot/u-boot-1.3.2/boc01/008_02_u-boot-1.3.2_TSEC.patch
new file mode 100644
index 0000000000..3dd89c5785
--- /dev/null
+++ b/packages/u-boot/u-boot-1.3.2/boc01/008_02_u-boot-1.3.2_TSEC.patch
@@ -0,0 +1,195 @@
+Index: u-boot-1.3.2/drivers/net/tsec.c
+===================================================================
+--- u-boot-1.3.2.orig/drivers/net/tsec.c	2008-03-09 16:20:02.000000000 +0100
++++ u-boot-1.3.2/drivers/net/tsec.c	2008-11-21 15:36:55.000000000 +0100
+@@ -179,6 +179,12 @@
+ 	priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
+ 	priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
+ 
++	/* Init MACCFG2 */
++	priv->regs->maccfg2 = MACCFG2_INIT_SETTINGS;
++
++	/* Init ECNTRL */
++	priv->regs->ecntrl = ECNTRL_INIT_SETTINGS;
++
+ #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+ 	&& !defined(BITBANGMII)
+ 	miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
+@@ -204,7 +210,7 @@
+ 	/* Make sure the controller is stopped */
+ 	tsec_halt(dev);
+ 
+-	/* Init MACCFG2.  Defaults to GMII */
++	/* Init MACCFG2 */
+ 	regs->maccfg2 = MACCFG2_INIT_SETTINGS;
+ 
+ 	/* Init ECNTRL */
+@@ -868,7 +874,11 @@
+ 	if(priv->phyinfo)
+ 		phy_run_commands(priv, priv->phyinfo->startup);
+ 
++#ifdef CONFIG_TSEC_NON_MANAGEABLE_PHY
++	priv->link = 1;
++#else
+ 	adjust_link(dev);
++#endif
+ 
+ 	/* Enable Transmit and Receive */
+ 	regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
+@@ -1318,6 +1328,21 @@
+ 	}
+ };
+ 
++/* a non-manageable PHY interface  */
++struct phy_info phy_info_null =  {
++	0,
++	"Non-manageable PHY",
++	0,
++	(struct phy_cmd[]) { /* config */
++		{miim_end,}
++	},
++	(struct phy_cmd[]) { /* startup */
++		{miim_end,}
++	},
++	(struct phy_cmd[]) { /* shutdown */
++		{miim_end,}
++	}
++};
+ 
+ uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
+ {
+@@ -1473,6 +1498,10 @@
+  */
+ struct phy_info *get_phy_info(struct eth_device *dev)
+ {
++#ifdef CONFIG_TSEC_NON_MANAGEABLE_PHY
++	debug("%s: Using non-manageable PHY interface\n", dev->name);
++	return &phy_info_null;
++#else
+ 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ 	uint phy_reg, phy_ID;
+ 	int i;
+@@ -1503,6 +1532,7 @@
+ 	}
+ 
+ 	return theInfo;
++#endif  // CONFIG_TSEC_NON_MANAGEABLE_PHY
+ }
+ 
+ /* Execute the given series of commands on the given device's
+@@ -1520,6 +1550,7 @@
+ 
+ 	while (phyregs->miimind & MIIMIND_BUSY) ;
+ 
++#if 0
+ 	for (i = 0; cmd->mii_reg != miim_end; i++) {
+ 		if (cmd->mii_data == miim_read) {
+ 			result = read_phy_reg(priv, cmd->mii_reg);
+@@ -1538,6 +1569,7 @@
+ 		}
+ 		cmd++;
+ 	}
++#endif
+ }
+ 
+ /* Relocate the function pointers in the phy cmd lists */
+Index: u-boot-1.3.2/drivers/net/tsec.h
+===================================================================
+--- u-boot-1.3.2.orig/drivers/net/tsec.h	2008-03-09 16:20:02.000000000 +0100
++++ u-boot-1.3.2/drivers/net/tsec.h	2008-11-21 15:36:55.000000000 +0100
+@@ -56,11 +56,11 @@
+ #define MACCFG1_SYNCD_TX_EN	0x00000002
+ #define MACCFG1_TX_EN		0x00000001
+ 
+-#define MACCFG2_INIT_SETTINGS	0x00007205
+ #define MACCFG2_FULL_DUPLEX	0x00000001
+ #define MACCFG2_IF              0x00000300
+ #define MACCFG2_GMII		0x00000200
+ #define MACCFG2_MII             0x00000100
++#define MACCFG2_INIT_SETTINGS	(0x00007005 | MACCFG2_MII) 
+ 
+ #define ECNTRL_INIT_SETTINGS	0x00001000
+ #define ECNTRL_TBI_MODE         0x00000020
+Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h
+===================================================================
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h	2008-11-21 15:35:49.000000000 +0100
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h	2008-11-21 15:37:39.000000000 +0100
+@@ -245,8 +245,8 @@
+ #define CFG_BAUDRATE_TABLE	\
+ 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+ 
+-#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
+-#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
++#define CFG_NS16550_COM1	(CFG_IMMR+0x4600)
++#define CFG_NS16550_COM2	(CFG_IMMR+0x4500)
+ 
+ /* Use the HUSH parser */
+ #define CFG_HUSH_PARSER
+@@ -301,23 +301,24 @@
+  * TSEC configuration
+  */
+ #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
++#define CONFIG_TSEC_NON_MANAGEABLE_PHY  /* Non-manageable PHY interface */
+ 
+ #ifndef CONFIG_NET_MULTI
+ #define CONFIG_NET_MULTI		1
+ #endif
+ 
+ #define CONFIG_GMII			1	/* MII PHY management */
+-#define CONFIG_TSEC1		1
++//#define CONFIG_TSEC1		1
+ 
+ #define CONFIG_TSEC1_NAME	"TSEC0"
+ #define CONFIG_TSEC2		1
+ #define CONFIG_TSEC2_NAME	"TSEC1"
+-#define TSEC1_PHY_ADDR			0x1c
+-#define TSEC2_PHY_ADDR			4
+-#define TSEC1_FLAGS			TSEC_GIGABIT
+-#define TSEC2_FLAGS			TSEC_GIGABIT
++#define TSEC1_PHY_ADDR			0 //0x1c
++#define TSEC2_PHY_ADDR			0 //4
++#define TSEC1_FLAGS			TSEC_REDUCED //TSEC_GIGABIT
++#define TSEC2_FLAGS			TSEC_REDUCED //TSEC_GIGABIT
+ #define TSEC1_PHYIDX			0
+-#define TSEC2_PHYIDX			0
++#define TSEC2_PHYIDX			1 //0
+ 
+ /* Options are: TSEC[0-1] */
+ #define CONFIG_ETHPRIME			"TSEC1"
+@@ -405,9 +406,11 @@
+ #define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+ 
+ /* Digital Thermometer and Thermostat */
+-#define CONFIG_DTT_LM75		1
+-#define CONFIG_DTT_SENSORS	{ 0x48 }
+-
++#define CONFIG_DTT_LM73		1
++#define CONFIG_DTT_SENSORS	{ 0x49 }
++#define CFG_DDT_MAX_TEMP        70
++#define CFG_DTT_MIN_TEMP        -30
++ 
+ /*
+  * For booting Linux, the board info and command line data
+  * have to be in the first 8 MB of memory, since this is
+@@ -453,17 +456,17 @@
+ 	HRCWH_SW_WATCHDOG_DISABLE |\
+ 	HRCWH_ROM_LOC_LOCAL_16BIT |\
+ 	HRCWH_RL_EXT_LEGACY |\
+-	HRCWH_TSEC1M_IN_RGMII |\
+-	HRCWH_TSEC2M_IN_RGMII |\
++	HRCWH_TSEC1M_IN_MII |\
++	HRCWH_TSEC2M_IN_MII |\
+ 	HRCWH_BIG_ENDIAN |\
+ 	HRCWH_LALE_NORMAL)
+ 
+ 
+-#define CONFIG_WATCHDOG
++//#define CONFIG_WATCHDOG
+ #define CFG_WATCHDOG_VALUE 0xFFFF
+ 
+ /* System IO Config */
+-#define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
++#define CFG_SICRH	0 //(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
+ #define CFG_SICRL	(SICRL_USBDR	|SICRL_LBC)		/* Enable Internal USB Phy  */
+ 
+ #define CFG_HID0_INIT	0x000000000
diff --git a/packages/u-boot/u-boot-1.3.2/boc01/009_03_u-boot-1.3.2_Extender_IO.patch b/packages/u-boot/u-boot-1.3.2/boc01/009_03_u-boot-1.3.2_Extender_IO.patch
new file mode 100644
index 0000000000..529a442321
--- /dev/null
+++ b/packages/u-boot/u-boot-1.3.2/boc01/009_03_u-boot-1.3.2_Extender_IO.patch
@@ -0,0 +1,128 @@
+Index: u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c
+===================================================================
+--- u-boot-1.3.2.orig/board/freescale/mpc8313erdb/mpc8313erdb.c	2008-11-21 15:30:25.000000000 +0100
++++ u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c	2008-11-21 15:40:06.000000000 +0100
+@@ -40,10 +40,20 @@
+ 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+ 		gd->flags |= GD_FLG_SILENT;
+ #endif
+-
+ 	return 0;
+ }
+ 
++int misc_init_f(void)
++{
++#ifdef INIT_EXIO
++	ulong	addr;
++	puts("EXIO:  ready\n");
++	addr = ADDR_EXIO;
++	*((u_char *)addr) = INIT_EXIO;
++	
++#endif
++}
++
+ int checkboard(void)
+ {
+ 	puts("Board: Freescale MPC8313ERDB\n");
+Index: u-boot-1.3.2/common/cmd_exio.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ u-boot-1.3.2/common/cmd_exio.c	2008-11-21 15:40:06.000000000 +0100
+@@ -0,0 +1,59 @@
++/*
++ * (C) Copyright 2008
++ * Alexandre Coffignal, CenoSYS, alexandre.coffignal@cenosys.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++	
++#include <common.h>
++#include <config.h>
++#include <command.h>
++extern void init_exio(char value);
++
++int do_exio (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
++{
++	
++	unsigned char ucExio;
++	ulong	addr;
++	if (argc < 2) 
++		goto usage;
++
++	ucExio = simple_strtoul (argv[1], NULL, 10);
++
++	addr = ADDR_EXIO;
++	*((u_char *)addr) = ucExio;
++	
++	printf("%s 0x%2x\n",argv[0],ucExio);
++		
++	return 0;
++	
++usage :
++	printf ("Usage:\n%s\n", cmdtp->usage);
++	return 1;
++}	/* do_gpio() */
++
++/***************************************************/
++
++U_BOOT_CMD(
++	  exio,	2,	1,	do_exio,
++	  "exio     - Extender io Output\n",
++	  "        - Set or clear extender io  Output.\n"
++	  "exio value -  \n"
++);
+Index: u-boot-1.3.2/common/Makefile
+===================================================================
+--- u-boot-1.3.2.orig/common/Makefile	2008-11-21 15:35:49.000000000 +0100
++++ u-boot-1.3.2/common/Makefile	2008-11-21 15:40:06.000000000 +0100
+@@ -52,6 +52,7 @@
+ COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o
+ COBJS-$(CONFIG_CMD_CAPSENSE) += cmd_capsense.o
+ COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
++COBJS-$(CONFIG_CMD_EXIO) += cmd_exio.o
+ COBJS-y += cmd_eeprom.o
+ COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o
+ COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o
+Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h
+===================================================================
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h	2008-11-21 15:38:44.000000000 +0100
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h	2008-11-21 15:40:06.000000000 +0100
+@@ -49,6 +49,7 @@
+ #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+ 
+ #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
++#define CONFIG_MISC_INIT_F
+ 
+ #define CFG_IMMR		0xE0000000
+ 
+@@ -372,6 +373,13 @@
+ #define CONFIG_CMD_NAND
+ #define CONFIG_CMD_SPI
+ #define CONFIG_CMD_GPIO
++#define CONFIG_CMD_EXIO
++
++
++/*Extender io*/
++#define ADDR_EXIO	0xFA000000
++#define INIT_EXIO	0x59
++
+ 
+ #if defined(CFG_RAMBOOT)
+     #undef CONFIG_CMD_ENV
diff --git a/packages/u-boot/u-boot_1.3.2.bb b/packages/u-boot/u-boot_1.3.2.bb
index 0946275f66..32282f16b8 100644
--- a/packages/u-boot/u-boot_1.3.2.bb
+++ b/packages/u-boot/u-boot_1.3.2.bb
@@ -17,6 +17,19 @@ SRC_URI_append_mpc8313e-rdb = "\
            file://mpc8313e-rdb-mtdparts.patch;patch=1 \
            "
 
+SRC_URI_append_boc01 = "\
+           file://mpc8313e-rdb-nand.patch;patch=1 \
+           file://mpc8313e-rdb-eeprom.patch;patch=1 \
+           file://mpc8313e-rdb-lm75.patch;patch=1 \
+           file://001_01_u-boot-1.3.2_SPI.patch;patch=1 \
+           file://002_02_u-boot-1.3.2_GPIO.patch;patch=1 \
+           file://004_01_u-boot-1.3.2_WATCHDOG.patch;patch=1 \
+           file://006_01_u-boot-1.3.2_EEPROM_INTERSIL.patch;patch=1 \
+           file://007_01_u-boot-1.3.2_CAPSENSE.patch;patch=1 \
+           file://008_02_u-boot-1.3.2_TSEC.patch;patch=1 \
+           file://009_03_u-boot-1.3.2_Extender_IO.patch;patch=1 \
+           "
+
 PACKAGE_ARCH = "${MACHINE_ARCH}"
 
 do_deploy_append_mpc8313e-rdb () {