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| author | sharma-mts <86847754+sharma-mts@users.noreply.github.com> | 2022-01-14 13:16:49 -0600 |
|---|---|---|
| committer | John Klug <john.klug@multitech.com> | 2022-02-14 18:37:09 -0600 |
| commit | 01121a51ea3cbc92485cdba8f05b714effe6ac9e (patch) | |
| tree | 3ee671b70170a271d7e4b5129aec18633bc90106 /mtcdt/pins-0.0.dtso | |
| parent | 94426e20b18bc1e9f1661223aa6bcf5c916263fa (diff) | |
| download | mt-dt-overlay-01121a51ea3cbc92485cdba8f05b714effe6ac9e.tar.gz mt-dt-overlay-01121a51ea3cbc92485cdba8f05b714effe6ac9e.tar.bz2 mt-dt-overlay-01121a51ea3cbc92485cdba8f05b714effe6ac9e.zip | |
MTAC-LORA overlay
Diffstat (limited to 'mtcdt/pins-0.0.dtso')
| -rw-r--r-- | mtcdt/pins-0.0.dtso | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/mtcdt/pins-0.0.dtso b/mtcdt/pins-0.0.dtso new file mode 100644 index 0000000..0844052 --- /dev/null +++ b/mtcdt/pins-0.0.dtso @@ -0,0 +1,53 @@ +/* + * DTS file for Multi-Tech Systems MTCDT 0.0 Hardware + * + * Copyright (C) 2021 by Multi-Tech Systems, + * + * Licensed under GPLv2 or later. + */ + +/* + * Location(s): + * Put: MTCDT/0.0/pins.dtbo + */ + +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/at91.h> +#include <dt-bindings/gpio/mt-at91.h> // Explicit PHandles + +/dts-v1/; + +/ { + model = "Multi-Tech Systems MTCDT-0.0"; + compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + fragment@0 { + target-path = "/mts-io"; + __overlay__ { + status = "okay"; + WIFI_BT_LPWKUP-gpios = <GPIO0_PH 6 GPIO_ACTIVE_HIGH>; + CD_LED-gpios = <GPIO0_PH 25 GPIO_ACTIVE_HIGH>; + SIG1_LED-gpios = <GPIO0_PH 26 GPIO_ACTIVE_HIGH>; + SIG2_LED-gpios = <GPIO0_PH 27 GPIO_ACTIVE_HIGH>; + SIG3_LED-gpios = <GPIO0_PH 28 GPIO_ACTIVE_HIGH>; + + AP1_GPIO3-gpios = <GPIO2_PH 8 GPIO_ACTIVE_HIGH>; + AP1_GPIO4-gpios = <GPIO2_PH 9 GPIO_ACTIVE_HIGH>; + AP1_TBD1-gpios = <GPIO2_PH 10 GPIO_ACTIVE_HIGH>; + AP1_TBD2-gpios = <GPIO2_PH 11 GPIO_ACTIVE_HIGH>; + AP1_TBD3-gpios = <GPIO2_PH 12 GPIO_ACTIVE_HIGH>; + AP1_TBD4-gpios = <GPIO2_PH 13 GPIO_ACTIVE_HIGH>; + AP1_TBD5-gpios = <GPIO2_PH 14 GPIO_ACTIVE_HIGH>; + AP2_GPIO3-gpios = <GPIO2_PH 22 GPIO_ACTIVE_HIGH>; + AP2_GPIO4-gpios = <GPIO2_PH 23 GPIO_ACTIVE_HIGH>; + AP2_TBD1-gpios = <GPIO2_PH 24 GPIO_ACTIVE_HIGH>; + AP2_TBD2-gpios = <GPIO2_PH 25 GPIO_ACTIVE_HIGH>; + AP2_TBD3-gpios = <GPIO2_PH 26 GPIO_ACTIVE_HIGH>; + AP2_TBD4-gpios = <GPIO2_PH 27 GPIO_ACTIVE_HIGH>; + AP2_TBD5-gpios = <GPIO2_PH 28 GPIO_ACTIVE_HIGH>; + + }; + }; /* fragment@0 */ +}; |