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authorJesse Gilles <jgilles@multitech.com>2014-11-04 11:23:21 -0600
committerJesse Gilles <jgilles@multitech.com>2014-11-04 11:23:21 -0600
commit812befa503067ad2bae5de58962ff38321c369ca (patch)
treeb472b5118f62e97f760a5b23f3a72130e5ce235b /recipes-bsp/at91bootstrap
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initial commit with MTCDT support
Diffstat (limited to 'recipes-bsp/at91bootstrap')
-rw-r--r--recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch20
-rw-r--r--recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch91
-rw-r--r--recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtcdt.patch60
-rw-r--r--recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91sam9x5_4bit_pmecc_header.bin1
-rwxr-xr-xrecipes-bsp/at91bootstrap/at91bootstrap-3.5.3/create_4bit_pmecc_header.rb5
-rw-r--r--recipes-bsp/at91bootstrap/at91bootstrap_3.5.3.bb28
-rw-r--r--recipes-bsp/at91bootstrap/at91bootstrap_3.5.inc27
7 files changed, 232 insertions, 0 deletions
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch
new file mode 100644
index 0000000..6f007b9
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch
@@ -0,0 +1,20 @@
+Index: at91bootstrap-3.5.2/Makefile
+===================================================================
+--- at91bootstrap-3.5.2.orig/Makefile 2013-02-08 14:38:40.660054339 -0600
++++ at91bootstrap-3.5.2/Makefile 2013-02-08 14:41:30.626272862 -0600
+@@ -359,4 +359,15 @@
+
+ PHONY+=tarball tarballx
+
++install:
++ -install -d $(DESTDIR)
++ install $(AT91BOOTSTRAP) $(DESTDIR)/$(IMAGE)
++ -rm -f $(DESTDIR)/$(SYMLINK)
++ (cd ${DESTDIR} ; \
++ ln -sf ${IMAGE} ${SYMLINK} \
++ )
++
++
++PHONY+=install
++
+ .PHONY: $(PHONY)
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch
new file mode 100644
index 0000000..98ccd41
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch
@@ -0,0 +1,91 @@
+Index: at91bootstrap-3.5.2/driver/at91_slowclk.c
+===================================================================
+--- at91bootstrap-3.5.2.orig/driver/at91_slowclk.c 2013-01-30 04:01:20.000000000 -0600
++++ at91bootstrap-3.5.2/driver/at91_slowclk.c 2013-04-24 11:35:44.369827054 -0500
+@@ -33,12 +33,17 @@
+ {
+ unsigned int reg;
+
+- /*
+- * Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1
+- */
++
+ reg = readl(AT91C_BASE_SCKCR);
+- reg |= AT91C_SLCKSEL_OSC32EN;
+- writel(reg, AT91C_BASE_SCKCR);
++
++ /* Only enable 32768 Hz oscillator if needed */
++ if ( !(reg & AT91C_SLCKSEL_OSC32EN) ) {
++ /*
++ * Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1
++ */
++ reg |= AT91C_SLCKSEL_OSC32EN;
++ writel(reg, AT91C_BASE_SCKCR);
++ }
+
+ /* start a internal timer */
+ start_interval_timer();
+@@ -50,32 +55,40 @@
+ {
+ unsigned int reg;
+
+- /*
+- * Wait 32768 Hz Startup Time for clock stabilization (software loop)
+- * wait about 1s (1000ms)
+- */
+- wait_interval_timer(1000);
+-
+- /*
+- * Switching from internal 32kHz RC oscillator to 32768 Hz oscillator
+- * by setting the bit OSCSEL to 1
+- */
+ reg = readl(AT91C_BASE_SCKCR);
+- reg |= AT91C_SLCKSEL_OSCSEL;
+- writel(reg, AT91C_BASE_SCKCR);
+
+- /*
+- * Waiting 5 slow clock cycles for internal resynchronization
+- * 5 slow clock cycles = ~153 us (5 / 32768)
+- */
+- udelay(153);
+-
+- /*
+- * Disable the 32kHz RC oscillator by setting the bit RCEN to 0
+- */
++ /* Only switch clock source if needed */
++ if ( !(reg & AT91C_SLCKSEL_OSCSEL) ) {
++ dbgu_print("Switching slow clock to external oscillator...\n\r");
++ /*
++ * Wait 32768 Hz Startup Time for clock stabilization (software loop)
++ * wait about 1s (1000ms)
++ */
++ wait_interval_timer(1000);
++
++ /*
++ * Switching from internal 32kHz RC oscillator to 32768 Hz oscillator
++ * by setting the bit OSCSEL to 1
++ */
++ reg |= AT91C_SLCKSEL_OSCSEL;
++ writel(reg, AT91C_BASE_SCKCR);
++
++ /*
++ * Waiting 5 slow clock cycles for internal resynchronization
++ * 5 slow clock cycles = ~153 us (5 / 32768)
++ */
++ udelay(153);
++ }
++
++ /* Only disable internal RC oscillator if needed */
+ reg = readl(AT91C_BASE_SCKCR);
+- reg &= ~AT91C_SLCKSEL_RCEN;
+- writel(reg, AT91C_BASE_SCKCR);
++ if (reg | AT91C_SLCKSEL_RCEN) {
++ /*
++ * Disable the 32kHz RC oscillator by setting the bit RCEN to 0
++ */
++ reg &= ~AT91C_SLCKSEL_RCEN;
++ writel(reg, AT91C_BASE_SCKCR);
++ }
+
+ return 0;
+ }
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtcdt.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtcdt.patch
new file mode 100644
index 0000000..24c27a0
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtcdt.patch
@@ -0,0 +1,60 @@
+Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig
+===================================================================
+--- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig 2013-04-11 05:07:35.000000000 -0500
++++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig 2013-04-29 15:13:01.390913836 -0500
+@@ -42,7 +42,8 @@
+ ALLOW_PIO3=y
+ CONFIG_HAS_PIO3=y
+ CPU_HAS_PMECC=y
+-CONFIG_LOAD_ONE_WIRE=y
++# MTS: don't load one wire
++# CONFIG_LOAD_ONE_WIRE is not set
+ # CONFIG_MMC_SUPPORT is not set
+
+ #
+@@ -81,8 +82,8 @@
+ #
+ # PMECC Configuration
+ #
+-CONFIG_PMECC_CORRECT_BITS_2=y
+-# CONFIG_PMECC_CORRECT_BITS_4 is not set
++# CONFIG_PMECC_CORRECT_BITS_2 is not set
++CONFIG_PMECC_CORRECT_BITS_4=y
+ # CONFIG_PMECC_CORRECT_BITS_8 is not set
+ # CONFIG_PMECC_CORRECT_BITS_12 is not set
+ # CONFIG_PMECC_CORRECT_BITS_24 is not set
+@@ -116,4 +117,5 @@
+ # CONFIG_USER_HW_INIT is not set
+ CONFIG_THUMB=y
+ CONFIG_SCLK=y
+-CONFIG_DISABLE_WATCHDOG=y
++# MTS: don't disable watchdog
++# CONFIG_DISABLE_WATCHDOG is not set
+Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c
+===================================================================
+--- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c 2013-04-11 05:07:35.000000000 -0500
++++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c 2013-04-29 15:14:44.578915819 -0500
+@@ -312,10 +312,8 @@
+
+ reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
+ reg |= AT91C_EBI_CS3A_SM;
+- if (get_cm_rev() == 'A')
+- reg &= ~AT91C_EBI_NFD0_ON_D16;
+- else
+- reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
++ /* MTCDT */
++ reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
+
+ reg &= ~AT91C_EBI_DRV;
+ writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
+@@ -345,9 +343,7 @@
+ AT91C_BASE_SMC + SMC_CTRL3);
+
+ /* Configure the PIO controller */
+- if (get_cm_rev() == 'A')
+- pio_configure(nand_pins_lo);
+- else
++ /* MTCDT */
+ pio_configure(nand_pins_hi);
+
+ writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91sam9x5_4bit_pmecc_header.bin b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91sam9x5_4bit_pmecc_header.bin
new file mode 100644
index 0000000..f8d6073
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91sam9x5_4bit_pmecc_header.bin
@@ -0,0 +1 @@
+$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ \ No newline at end of file
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/create_4bit_pmecc_header.rb b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/create_4bit_pmecc_header.rb
new file mode 100755
index 0000000..780d728
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/create_4bit_pmecc_header.rb
@@ -0,0 +1,5 @@
+#!/usr/bin/env ruby
+
+52.times do
+ print ["052490c0"].pack('H*')
+end
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap_3.5.3.bb b/recipes-bsp/at91bootstrap/at91bootstrap_3.5.3.bb
new file mode 100644
index 0000000..447d77f
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap_3.5.3.bb
@@ -0,0 +1,28 @@
+require at91bootstrap_3.5.inc
+
+PR = "r1"
+
+LICENSE = "custom-freely-distributable"
+LIC_FILES_CHKSUM = "file://main.c;beginline=6;endline=26;md5=6fca71334c9e8b7d033296123c91437f"
+
+SRCREV = "v${PV}"
+SRC_URI = "git://github.com/linux4sam/at91bootstrap \
+ file://at91bootstrap-3.5.2-add-install.patch \
+ file://at91bootstrap-3.5.2-onetime-slow-clock-switch.patch \
+ file://at91sam9x5_4bit_pmecc_header.bin "
+
+S = "${WORKDIR}/git"
+
+SRC_URI_append_mtcdt = " file://at91bootstrap-3.5.3-mtcdt.patch "
+
+# generate a bootstrap file padded with the header needed for 4-bit PMECC
+# The padded file can be flashed via u-boot without any need to set the PMECC header using SAM-BA
+do_pad_4bit_pmecc() {
+ cp -f ${WORKDIR}/at91sam9x5_4bit_pmecc_header.bin ${DEPLOY_DIR_IMAGE}/at91bootstrap_pmecc_padded.bin
+ cat ${DEPLOY_DIR_IMAGE}/at91bootstrap.bin >> ${DEPLOY_DIR_IMAGE}/at91bootstrap_pmecc_padded.bin
+}
+
+do_install_append() {
+ do_pad_4bit_pmecc
+}
+
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap_3.5.inc b/recipes-bsp/at91bootstrap/at91bootstrap_3.5.inc
new file mode 100644
index 0000000..ac147c0
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap_3.5.inc
@@ -0,0 +1,27 @@
+DESCRIPTION = "at91bootstrap: loaded into internal SRAM by AT91 BootROM"
+SECTION = "bootloaders"
+
+PARALLEL_MAKE = ""
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+EXTRA_OEMAKE = "CROSS_COMPILE=${TARGET_PREFIX} DESTDIR=${DEPLOY_DIR_IMAGE} REVISION=${PR}"
+
+do_compile () {
+ unset LDFLAGS
+ unset CFLAGS
+ unset CPPFLAGS
+
+ rm -Rf ${S}/binaries
+ for board in ${AT91BOOTSTRAP_BOARD} ; do
+ oe_runmake mrproper
+ filename=`find board -name ${board}_defconfig`
+ if ! [ "x$filename" == "x" ] ; then
+ cp $filename .config
+ oe_runmake
+ oe_runmake install
+ else
+ echo "${board} could not be built"
+ exit 1
+ fi
+ done
+}