diff options
Diffstat (limited to 'recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch')
| -rw-r--r-- | recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch new file mode 100644 index 0000000..8710ee5 --- /dev/null +++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch @@ -0,0 +1,82 @@ +diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c +--- orig/board/at91sam9x5ek/at91sam9x5ek.c 2019-04-16 14:20:15.036823256 -0500 ++++ new/board/at91sam9x5ek/at91sam9x5ek.c 2019-04-16 14:26:10.648812728 -0500 +@@ -44,6 +44,37 @@ + #include "at91sam9x5ek.h" + #include "board_hw_info.h" + ++ ++static void initialize_mt_gpio(void) ++{ ++ /* Configure DBGU pins */ ++ const struct pio_desc mt_gpio_pins[] = { ++ /* Misc. pins -- Pins PD15-PD18 belong to PERIPH ++ * B A20-A25 until bootstrap shuts them down. ++ * This code prevents these pins from being used ++ * during boot, since we do not ++ * need these pins to boot the system and we ++ * do not want resets to toggle needlessly. ++ * GNSS-RESET is held low because the EXAR ++ * rarely will display the wrong VID/PID on the ++ * USB bus, which prevents the vizzini driver ++ * from loading. Once the VID/PID is bad, a ++ * reboot will preserve the bad VID/PID, so ++ * a power cycle is then required. ++ */ ++ {"GNSS-RESET",AT91C_PIN_PD(15), 0, PIO_PULLUP, PIO_OUTPUT}, ++ {"SECURE-RESET",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"MTQ-RESET",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"USBHUB-RESET",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"GNSS-INT",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"WIFI-BT-LPMODE",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT}, ++ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ }; ++ ++ pio_configure(mt_gpio_pins); ++} ++ ++ + static void at91_dbgu_hw_init(void) + { + /* Configure DBGU pins */ +@@ -185,6 +210,9 @@ + /* Init timer */ + timer_init(); + ++ /* Initialize MT GPIO */ ++ initialize_mt_gpio(); ++ + /* Initialize dbgu */ + initialize_dbgu(); + +@@ -298,10 +326,14 @@ + + reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); + reg |= AT91C_EBI_CS3A_SM; ++#ifdef NOTMTCDT + if (get_cm_rev() == 'A') + reg &= ~AT91C_EBI_NFD0_ON_D16; + else + reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); ++#endif /* NOTMTCDT */ ++ /* MTCDT */ ++ reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); + + reg &= ~AT91C_EBI_DRV; + writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); +@@ -331,11 +363,15 @@ + AT91C_BASE_SMC + SMC_CTRL3); + + /* Configure the PIO controller */ ++#ifdef NOTMTCDT + if (get_cm_rev() == 'A') + pio_configure(nand_pins_lo); + else ++#endif /* NOTMTCDT */ ++ /* MTCDT */ + pio_configure(nand_pins_hi); + ++ + pmc_enable_periph_clock(AT91C_ID_PIOC_D); + } + #endif /* #ifdef CONFIG_NANDFLASH */ |