diff options
Diffstat (limited to 'recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtr.patch')
| -rw-r--r-- | recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtr.patch | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtr.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtr.patch new file mode 100644 index 0000000..cbbe27d --- /dev/null +++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtr.patch @@ -0,0 +1,69 @@ +diff -Naru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c +--- orig/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 17:38:21.769207114 -0500 ++++ new/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 17:51:24.137183953 -0500 +@@ -56,6 +56,31 @@ + writel(0xFF, RTC_SCCR + AT91C_BASE_RTC); + } + ++ ++static void initialize_mt_gpio(void) ++{ ++ /* Configure DBGU pins */ ++ const struct pio_desc mt_gpio_pins[] = { ++ /* Misc. pins -- Pins PD15-PD18 belong to PERIPH ++ * B A20-A25 until bootstrap shuts them down. ++ * This code prevents these pins from being used ++ * during boot, since we do not ++ * need these pins to boot the system and we ++ * do not want resets to toggle needlessly. ++ */ ++ {"PD15",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"PD16",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"PD17",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"PD18",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"PD19",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"PD20IN",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT}, ++ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ }; ++ ++ pio_configure(mt_gpio_pins); ++} ++ ++ + static void at91_dbgu_hw_init(void) + { + /* Configure DBGU pins */ +@@ -200,6 +225,9 @@ + /* Init timer */ + timer_init(); + ++ /* Initialize MT GPIO */ ++ initialize_mt_gpio(); ++ + /* Initialize dbgu */ + initialize_dbgu(); + +@@ -313,10 +341,8 @@ + + reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); + reg |= AT91C_EBI_CS3A_SM; +- if (get_cm_rev() == 'A') +- reg &= ~AT91C_EBI_NFD0_ON_D16; +- else +- reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); ++ /* MTR */ ++ reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); + + reg &= ~AT91C_EBI_DRV; + writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); +@@ -346,9 +372,7 @@ + AT91C_BASE_SMC + SMC_CTRL3); + + /* Configure the PIO controller */ +- if (get_cm_rev() == 'A') +- pio_configure(nand_pins_lo); +- else ++ /* MTR2 */ + pio_configure(nand_pins_hi); + + pmc_enable_periph_clock(AT91C_ID_PIOC_D); |