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Diffstat (limited to 'recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcap.patch')
-rw-r--r--recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcap.patch76
1 files changed, 76 insertions, 0 deletions
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcap.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcap.patch
new file mode 100644
index 0000000..da2e835
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcap.patch
@@ -0,0 +1,76 @@
+diff -Naru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c
+--- orig/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 14:47:38.921510351 -0500
++++ new/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 12:29:01.089756599 -0500
+@@ -56,6 +56,31 @@
+ writel(0xFF, RTC_SCCR + AT91C_BASE_RTC);
+ }
+
++
++static void initialize_mt_gpio(void)
++{
++ const struct pio_desc mt_gpio_pins[] = {
++ {"LORA-RESET",AT91C_PIN_PA(8), 0, PIO_PULLUP, PIO_OUTPUT},
++ {"PA14-UNUSED",AT91C_PIN_PA(14), 0, PIO_PULLUP, PIO_INPUT},
++ {"LORA-32MHZ-CLOCK",AT91C_PIN_PA(26), 0, PIO_DEFAULT, PIO_INPUT},
++ {"LORA-CRESET",AT91C_PIN_PA(29), 0, PIO_PULLUP, PIO_OUTPUT},
++ {"MP8859-ENABLE",AT91C_PIN_PB(12), 0, PIO_DEFAULT, PIO_OUTPUT},
++ {"POE-AT-STATUS",AT91C_PIN_PB(15), 0, PIO_PULLUP, PIO_INPUT},
++ {"PB18-UNUSED",AT91C_PIN_PB(18), 0, PIO_PULLUP, PIO_INPUT},
++ {"ETH-RESET",AT91C_PIN_PC(6), 0, PIO_DEFAULT, PIO_OUTPUT},
++ {"UART-TX-GNSS",AT91C_PIN_PC(8), 0, PIO_DEFAULT, PIO_OUTPUT},
++ {"LED-CD",AT91C_PIN_PC(16), 1, PIO_OPENDRAIN, PIO_OUTPUT},
++ {"ALLOW-RESET",AT91C_PIN_PC(26), 1, PIO_DEFAULT, PIO_OUTPUT},
++ {"GNSS-RESET",AT91C_PIN_PD(15), 0, PIO_PULLUP, PIO_OUTPUT},
++ {"GNSS-INT",AT91C_PIN_PD(19), 1, PIO_DEFAULT, PIO_OUTPUT},
++ {"RADIO-POWER-MONITOR",AT91C_PIN_PD(21), 0, PIO_PULLDOWN, PIO_INPUT},
++ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++ };
++
++ pio_configure(mt_gpio_pins);
++}
++
++
+ static void at91_dbgu_hw_init(void)
+ {
+ /* Configure DBGU pins */
+@@ -200,6 +225,9 @@
+ /* Init timer */
+ timer_init();
+
++ /* Initialize MT GPIO */
++ initialize_mt_gpio();
++
+ /* Initialize dbgu */
+ initialize_dbgu();
+
+@@ -313,10 +341,14 @@
+
+ reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
+ reg |= AT91C_EBI_CS3A_SM;
++#ifdef NOTMTCDT
+ if (get_cm_rev() == 'A')
+ reg &= ~AT91C_EBI_NFD0_ON_D16;
+ else
+ reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
++#endif /* NOTMTCDT */
++ /* MTCDT */
++ reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
+
+ reg &= ~AT91C_EBI_DRV;
+ writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
+@@ -346,11 +378,15 @@
+ AT91C_BASE_SMC + SMC_CTRL3);
+
+ /* Configure the PIO controller */
++#ifdef NOTMTCDT
+ if (get_cm_rev() == 'A')
+ pio_configure(nand_pins_lo);
+ else
++#endif /* NOTMTCDT */
++ /* MTCDT */
+ pio_configure(nand_pins_hi);
+
++
+ pmc_enable_periph_clock(AT91C_ID_PIOC_D);
+ }
+ #endif /* #ifdef CONFIG_NANDFLASH */