diff options
| -rw-r--r-- | recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0001-mtrv1-DDRlowDriveStrength.patch (renamed from recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/mtrv1-DDRlowDriveStrength.patch) | 0 | ||||
| -rw-r--r-- | recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0003-disable-rtc-interrupts.patch (renamed from recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/disable-rtc-interrupts.patch) | 0 | ||||
| -rw-r--r-- | recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcap.patch | 76 | ||||
| -rw-r--r-- | recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcdt.patch (renamed from recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch) | 18 | ||||
| -rw-r--r-- | recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtr.patch | 69 | ||||
| -rw-r--r-- | recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtr.patch | 414 | ||||
| -rw-r--r-- | recipes-bsp/at91bootstrap/at91bootstrap.inc | 12 | ||||
| -rw-r--r-- | recipes-bsp/at91bootstrap/at91bootstrap_3.8.12.bb | 2 |
8 files changed, 161 insertions, 430 deletions
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/mtrv1-DDRlowDriveStrength.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0001-mtrv1-DDRlowDriveStrength.patch index e57ba89..e57ba89 100644 --- a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/mtrv1-DDRlowDriveStrength.patch +++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0001-mtrv1-DDRlowDriveStrength.patch diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/disable-rtc-interrupts.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0003-disable-rtc-interrupts.patch index d262972..d262972 100644 --- a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/disable-rtc-interrupts.patch +++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0003-disable-rtc-interrupts.patch diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcap.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcap.patch new file mode 100644 index 0000000..da2e835 --- /dev/null +++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcap.patch @@ -0,0 +1,76 @@ +diff -Naru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c +--- orig/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 14:47:38.921510351 -0500 ++++ new/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 12:29:01.089756599 -0500 +@@ -56,6 +56,31 @@ + writel(0xFF, RTC_SCCR + AT91C_BASE_RTC); + } + ++ ++static void initialize_mt_gpio(void) ++{ ++ const struct pio_desc mt_gpio_pins[] = { ++ {"LORA-RESET",AT91C_PIN_PA(8), 0, PIO_PULLUP, PIO_OUTPUT}, ++ {"PA14-UNUSED",AT91C_PIN_PA(14), 0, PIO_PULLUP, PIO_INPUT}, ++ {"LORA-32MHZ-CLOCK",AT91C_PIN_PA(26), 0, PIO_DEFAULT, PIO_INPUT}, ++ {"LORA-CRESET",AT91C_PIN_PA(29), 0, PIO_PULLUP, PIO_OUTPUT}, ++ {"MP8859-ENABLE",AT91C_PIN_PB(12), 0, PIO_DEFAULT, PIO_OUTPUT}, ++ {"POE-AT-STATUS",AT91C_PIN_PB(15), 0, PIO_PULLUP, PIO_INPUT}, ++ {"PB18-UNUSED",AT91C_PIN_PB(18), 0, PIO_PULLUP, PIO_INPUT}, ++ {"ETH-RESET",AT91C_PIN_PC(6), 0, PIO_DEFAULT, PIO_OUTPUT}, ++ {"UART-TX-GNSS",AT91C_PIN_PC(8), 0, PIO_DEFAULT, PIO_OUTPUT}, ++ {"LED-CD",AT91C_PIN_PC(16), 1, PIO_OPENDRAIN, PIO_OUTPUT}, ++ {"ALLOW-RESET",AT91C_PIN_PC(26), 1, PIO_DEFAULT, PIO_OUTPUT}, ++ {"GNSS-RESET",AT91C_PIN_PD(15), 0, PIO_PULLUP, PIO_OUTPUT}, ++ {"GNSS-INT",AT91C_PIN_PD(19), 1, PIO_DEFAULT, PIO_OUTPUT}, ++ {"RADIO-POWER-MONITOR",AT91C_PIN_PD(21), 0, PIO_PULLDOWN, PIO_INPUT}, ++ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ }; ++ ++ pio_configure(mt_gpio_pins); ++} ++ ++ + static void at91_dbgu_hw_init(void) + { + /* Configure DBGU pins */ +@@ -200,6 +225,9 @@ + /* Init timer */ + timer_init(); + ++ /* Initialize MT GPIO */ ++ initialize_mt_gpio(); ++ + /* Initialize dbgu */ + initialize_dbgu(); + +@@ -313,10 +341,14 @@ + + reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); + reg |= AT91C_EBI_CS3A_SM; ++#ifdef NOTMTCDT + if (get_cm_rev() == 'A') + reg &= ~AT91C_EBI_NFD0_ON_D16; + else + reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); ++#endif /* NOTMTCDT */ ++ /* MTCDT */ ++ reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); + + reg &= ~AT91C_EBI_DRV; + writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); +@@ -346,11 +378,15 @@ + AT91C_BASE_SMC + SMC_CTRL3); + + /* Configure the PIO controller */ ++#ifdef NOTMTCDT + if (get_cm_rev() == 'A') + pio_configure(nand_pins_lo); + else ++#endif /* NOTMTCDT */ ++ /* MTCDT */ + pio_configure(nand_pins_hi); + ++ + pmc_enable_periph_clock(AT91C_ID_PIOC_D); + } + #endif /* #ifdef CONFIG_NANDFLASH */ diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcdt.patch index 8710ee5..14f01eb 100644 --- a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch +++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtcdt.patch @@ -1,9 +1,9 @@ -diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c ---- orig/board/at91sam9x5ek/at91sam9x5ek.c 2019-04-16 14:20:15.036823256 -0500 -+++ new/board/at91sam9x5ek/at91sam9x5ek.c 2019-04-16 14:26:10.648812728 -0500 -@@ -44,6 +44,37 @@ - #include "at91sam9x5ek.h" - #include "board_hw_info.h" +diff -Naru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c +--- orig/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 16:30:43.653327254 -0500 ++++ new/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 16:16:38.597352272 -0500 +@@ -56,6 +56,37 @@ + writel(0xFF, RTC_SCCR + AT91C_BASE_RTC); + } + +static void initialize_mt_gpio(void) @@ -39,7 +39,7 @@ diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam static void at91_dbgu_hw_init(void) { /* Configure DBGU pins */ -@@ -185,6 +210,9 @@ +@@ -200,6 +231,9 @@ /* Init timer */ timer_init(); @@ -49,7 +49,7 @@ diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam /* Initialize dbgu */ initialize_dbgu(); -@@ -298,10 +326,14 @@ +@@ -313,10 +347,14 @@ reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); reg |= AT91C_EBI_CS3A_SM; @@ -64,7 +64,7 @@ diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam reg &= ~AT91C_EBI_DRV; writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); -@@ -331,11 +363,15 @@ +@@ -346,11 +384,15 @@ AT91C_BASE_SMC + SMC_CTRL3); /* Configure the PIO controller */ diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtr.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtr.patch new file mode 100644 index 0000000..cbbe27d --- /dev/null +++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/0005-at91bootstrap-3.8-mtr.patch @@ -0,0 +1,69 @@ +diff -Naru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c +--- orig/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 17:38:21.769207114 -0500 ++++ new/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 17:51:24.137183953 -0500 +@@ -56,6 +56,31 @@ + writel(0xFF, RTC_SCCR + AT91C_BASE_RTC); + } + ++ ++static void initialize_mt_gpio(void) ++{ ++ /* Configure DBGU pins */ ++ const struct pio_desc mt_gpio_pins[] = { ++ /* Misc. pins -- Pins PD15-PD18 belong to PERIPH ++ * B A20-A25 until bootstrap shuts them down. ++ * This code prevents these pins from being used ++ * during boot, since we do not ++ * need these pins to boot the system and we ++ * do not want resets to toggle needlessly. ++ */ ++ {"PD15",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"PD16",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"PD17",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"PD18",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"PD19",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"PD20IN",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT}, ++ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ }; ++ ++ pio_configure(mt_gpio_pins); ++} ++ ++ + static void at91_dbgu_hw_init(void) + { + /* Configure DBGU pins */ +@@ -200,6 +225,9 @@ + /* Init timer */ + timer_init(); + ++ /* Initialize MT GPIO */ ++ initialize_mt_gpio(); ++ + /* Initialize dbgu */ + initialize_dbgu(); + +@@ -313,10 +341,8 @@ + + reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); + reg |= AT91C_EBI_CS3A_SM; +- if (get_cm_rev() == 'A') +- reg &= ~AT91C_EBI_NFD0_ON_D16; +- else +- reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); ++ /* MTR */ ++ reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); + + reg &= ~AT91C_EBI_DRV; + writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); +@@ -346,9 +372,7 @@ + AT91C_BASE_SMC + SMC_CTRL3); + + /* Configure the PIO controller */ +- if (get_cm_rev() == 'A') +- pio_configure(nand_pins_lo); +- else ++ /* MTR2 */ + pio_configure(nand_pins_hi); + + pmc_enable_periph_clock(AT91C_ID_PIOC_D); diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtr.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtr.patch deleted file mode 100644 index 2993323..0000000 --- a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtr.patch +++ /dev/null @@ -1,414 +0,0 @@ -diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c ---- orig/board/at91sam9x5ek/at91sam9x5ek.c 2019-04-16 14:20:15.036823256 -0500 -+++ new/board/at91sam9x5ek/at91sam9x5ek.c 2019-04-16 14:42:16.920784122 -0500 -@@ -44,6 +44,31 @@ - #include "at91sam9x5ek.h" - #include "board_hw_info.h" - -+ -+static void initialize_mt_gpio(void) -+{ -+ /* Configure DBGU pins */ -+ const struct pio_desc mt_gpio_pins[] = { -+ /* Misc. pins -- Pins PD15-PD18 belong to PERIPH -+ * B A20-A25 until bootstrap shuts them down. -+ * This code prevents these pins from being used -+ * during boot, since we do not -+ * need these pins to boot the system and we -+ * do not want resets to toggle needlessly. -+ */ -+ {"PD15",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT}, -+ {"PD16",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT}, -+ {"PD17",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT}, -+ {"PD18",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT}, -+ {"PD19",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT}, -+ {"PD20IN",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT}, -+ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ }; -+ -+ pio_configure(mt_gpio_pins); -+} -+ -+ - static void at91_dbgu_hw_init(void) - { - /* Configure DBGU pins */ -@@ -185,6 +210,9 @@ - /* Init timer */ - timer_init(); - -+ /* Initialize MT GPIO */ -+ initialize_mt_gpio(); -+ - /* Initialize dbgu */ - initialize_dbgu(); - -@@ -298,10 +326,8 @@ - - reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); - reg |= AT91C_EBI_CS3A_SM; -- if (get_cm_rev() == 'A') -- reg &= ~AT91C_EBI_NFD0_ON_D16; -- else -- reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); -+ /* MTR */ -+ reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); - - reg &= ~AT91C_EBI_DRV; - writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); -@@ -331,9 +357,7 @@ - AT91C_BASE_SMC + SMC_CTRL3); - - /* Configure the PIO controller */ -- if (get_cm_rev() == 'A') -- pio_configure(nand_pins_lo); -- else -+ /* MTR2 */ - pio_configure(nand_pins_hi); - - pmc_enable_periph_clock(AT91C_ID_PIOC_D); -diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c.orig new/board/at91sam9x5ek/at91sam9x5ek.c.orig ---- orig/board/at91sam9x5ek/at91sam9x5ek.c.orig 1969-12-31 18:00:00.000000000 -0600 -+++ new/board/at91sam9x5ek/at91sam9x5ek.c.orig 2019-04-16 14:20:15.036823256 -0500 -@@ -0,0 +1,341 @@ -+/* ---------------------------------------------------------------------------- -+ * ATMEL Microcontroller Software Support -+ * ---------------------------------------------------------------------------- -+ * Copyright (c) 2008, Atmel Corporation -+ * -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * - Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the disclaimer below. -+ * -+ * Atmel's name may not be used to endorse or promote products derived from -+ * this software without specific prior written permission. -+ * -+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include "common.h" -+#include "hardware.h" -+#include "arch/at91_ccfg.h" -+#include "arch/at91_rstc.h" -+#include "arch/at91_pmc.h" -+#include "arch/at91_smc.h" -+#include "arch/at91_pio.h" -+#include "arch/at91_ddrsdrc.h" -+#include "gpio.h" -+#include "pmc.h" -+#include "usart.h" -+#include "debug.h" -+#include "ddramc.h" -+#include "timer.h" -+#include "watchdog.h" -+#include "string.h" -+#include "at91sam9x5ek.h" -+#include "board_hw_info.h" -+ -+static void at91_dbgu_hw_init(void) -+{ -+ /* Configure DBGU pins */ -+ const struct pio_desc dbgu_pins[] = { -+ {"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ {"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ }; -+ -+ pmc_enable_periph_clock(AT91C_ID_PIOA_B); -+ pio_configure(dbgu_pins); -+} -+ -+static void initialize_dbgu(void) -+{ -+ at91_dbgu_hw_init(); -+ usart_init(BAUDRATE(MASTER_CLOCK, BAUD_RATE)); -+} -+ -+#ifdef CONFIG_DDR2 -+/* Using the Micron MT47H64M16HR-3 */ -+static void ddramc_reg_config(struct ddramc_register *ddramc_config) -+{ -+ ddramc_config->mdr = (AT91C_DDRC2_DBW_16_BITS -+ | AT91C_DDRC2_MD_DDR2_SDRAM); -+ -+ ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 /* 10 column bits(1K) */ -+ | AT91C_DDRC2_NR_13 /* 13 row bits (8K) */ -+ | AT91C_DDRC2_CAS_3 /* CAS Latency 3 */ -+ | AT91C_DDRC2_NB_BANKS_8 /* 8 banks */ -+ | AT91C_DDRC2_DISABLE_RESET_DLL -+ | AT91C_DDRC2_DECOD_INTERLEAVED);/*Interleaved decode*/ -+ -+ /* -+ * Make sure to uncomment the following line if the DDR controller -+ * shares the EBI with another memory controller (SMC, NAND,..). -+ * For instance, AT91C_DDRC2_EBISHARE shall be set if NAND flash -+ * data line 0 is positioned on EBI data line 0 (AT91C_EBI_NFD0_ON_D16 bit -+ * cleared in CCFG_EBICSA register). -+ * -+ * For Atmel AT91SAM9x5-EK revision B onwards, this AT91C_DDRC2_EBISHARE bit -+ * is cleared because the NAND flash data line 0 is positioned on EBI -+ * data line number 16 (AT91C_EBI_NFD0_ON_D16 bit set in CCFG_EBICSA -+ * register). Only the DDR controller function is thus used on lower -+ * EBI data lines. -+ */ -+ //ddramc_config->cr |= AT91C_DDRC2_EBISHARE; /* DQM is shared with other controller */ -+ -+ -+ /* -+ * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us. -+ * With a 133 MHz frequency, the refresh timer count register must to be -+ * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824 -+ * or (7.81 x 133 MHz) ~ 1040 i.e. 0x410. -+ */ -+ ddramc_config->rtr = 0x411; /* Refresh timer: 7.8125us */ -+ -+ /* One clock cycle @ 133 MHz = 7.5 ns */ -+ ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */ -+ | AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */ -+ | AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */ -+ | AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */ -+ | AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */ -+ | AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */ -+ | AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */ -+ | AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */ -+ -+ ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */ -+ | AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */ -+ | AT91C_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns*/ -+ | AT91C_DDRC2_TRFC_(18)); /* 18 * 7.5 = 135 ns */ -+ -+ ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(7) /* 7 * 7.5 = 52.5 ns */ -+ | AT91C_DDRC2_TRTP_(2) /* 2 clock cycles min */ -+ | AT91C_DDRC2_TRPA_(3) /* 3 * 7.5 = 22.5 ns */ -+ | AT91C_DDRC2_TXARDS_(7) /* 7 clock cycles */ -+ | AT91C_DDRC2_TXARD_(2)); /* 2 clock cycles */ -+} -+ -+static void ddramc_init(void) -+{ -+ unsigned long csa; -+ struct ddramc_register ddramc_reg; -+ -+ ddramc_reg_config(&ddramc_reg); -+ -+ /* ENABLE DDR2 clock */ -+ pmc_enable_system_clock(AT91C_PMC_DDR); -+ -+ /* Chip select 1 is for DDR2/SDRAM */ -+ csa = readl(AT91C_BASE_CCFG + CCFG_EBICSA); -+ csa |= AT91C_EBI_CS1A_SDRAMC; -+ csa &= ~AT91C_EBI_DBPUC; -+ csa |= AT91C_EBI_DBPDC; -+ csa |= AT91C_EBI_DRV_HD; -+ -+ writel(csa, AT91C_BASE_CCFG + CCFG_EBICSA); -+ -+ /* DDRAM2 Controller initialize */ -+ ddram_initialize(AT91C_BASE_DDRSDRC, AT91C_BASE_CS1, &ddramc_reg); -+} -+#endif /* #ifdef CONFIG_DDR2 */ -+ -+static void one_wire_hw_init(void) -+{ -+ const struct pio_desc wire_pio[] = { -+ {"1-Wire", AT91C_PIN_PB(18), 1, PIO_DEFAULT, PIO_OUTPUT}, -+ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ }; -+ -+ pmc_enable_periph_clock(AT91C_ID_PIOA_B); -+ pio_configure(wire_pio); -+} -+ -+#ifdef CONFIG_HW_INIT -+void hw_init(void) -+{ -+ /* Disable watchdog */ -+ at91_disable_wdt(); -+ -+ /* -+ * At this stage the main oscillator is -+ * supposed to be enabled PCK = MCK = MOSC -+ */ -+ pmc_init_pll(0); -+ -+ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ -+ pmc_cfg_plla(PLLA_SETTINGS); -+ -+ /* Switch PCK/MCK on Main clock output */ -+ pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK); -+ -+ /* Switch PCK/MCK on PLLA output */ -+ pmc_cfg_mck(BOARD_PRESCALER_PLLA); -+ -+ /* Enable External Reset */ -+ writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); -+ -+ /* Init timer */ -+ timer_init(); -+ -+ /* Initialize dbgu */ -+ initialize_dbgu(); -+ -+#ifdef CONFIG_DDR2 -+ /* Initialize DDRAM Controller */ -+ ddramc_init(); -+#endif -+ /* one wire pin init */ -+ one_wire_hw_init(); -+} -+#endif /* #ifdef CONFIG_HW_INIT */ -+ -+#ifdef CONFIG_DATAFLASH -+void at91_spi0_hw_init(void) -+{ -+ /* Configure PINs for SPI0 */ -+ const struct pio_desc spi0_pins[] = { -+ {"MISO", AT91C_PIN_PA(11), 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ {"MOSI", AT91C_PIN_PA(12), 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ {"SPCK", AT91C_PIN_PA(13), 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ {"NPCS", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT}, -+ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ }; -+ -+ pmc_enable_periph_clock(AT91C_ID_PIOA_B); -+ pio_configure(spi0_pins); -+ -+ pmc_enable_periph_clock(AT91C_ID_SPI0); -+} -+#endif /* #ifdef CONFIG_DATAFLASH */ -+ -+#ifdef CONFIG_SDCARD -+#ifdef CONFIG_OF_LIBFDT -+void at91_board_set_dtb_name(char *of_name) -+{ -+ unsigned int cpu_board_id = get_cm_sn(); -+ unsigned int disp_board_id = get_dm_sn(); -+ -+ if (cpu_board_id == BOARD_ID_SAM9G15_CM) -+ strcpy(of_name, "at91sam9g15ek"); -+ else if (cpu_board_id == BOARD_ID_SAM9G25_CM) -+ strcpy(of_name, "at91sam9g25ek"); -+ else if (cpu_board_id == BOARD_ID_SAM9G35_CM) -+ strcpy(of_name, "at91sam9g35ek"); -+ else if (cpu_board_id == BOARD_ID_SAM9X25_CM) -+ strcpy(of_name, "at91sam9x25ek"); -+ else if (cpu_board_id == BOARD_ID_SAM9X35_CM) -+ strcpy(of_name, "at91sam9x35ek"); -+ else -+ dbg_info("WARNING: Not correct CPU board ID\n"); -+ -+ if (disp_board_id == BOARD_ID_PDA_DM) -+ strcat(of_name, "_pda"); -+ -+ strcat(of_name, ".dtb"); -+} -+#endif -+ -+void at91_mci0_hw_init(void) -+{ -+ const struct pio_desc mci_pins[] = { -+ {"MCCK", AT91C_PIN_PA(17), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"MCCDA", AT91C_PIN_PA(16), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"MCDA0", AT91C_PIN_PA(15), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"MCDA1", AT91C_PIN_PA(18), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"MCDA2", AT91C_PIN_PA(19), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"MCDA3", AT91C_PIN_PA(20), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ }; -+ -+ /* Configure the PIO controller */ -+ pmc_enable_periph_clock(AT91C_ID_PIOA_B); -+ pio_configure(mci_pins); -+ -+ /* Enable the clock */ -+ pmc_enable_periph_clock(AT91C_ID_HSMCI0); -+} -+#endif /* #ifdef CONFIG_SDCARD */ -+ -+#ifdef CONFIG_NANDFLASH -+void nandflash_hw_init(void) -+{ -+ unsigned int reg; -+ -+ /* Configure Nand PINs */ -+ const struct pio_desc nand_pins_hi[] = { -+ {"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT}, -+ {"D0", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"D1", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"D2", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"D3", AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"D4", AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"D5", AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"D6", AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"D7", AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ }; -+ -+ const struct pio_desc nand_pins_lo[] = { -+ {"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A}, -+ {"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT}, -+ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, -+ }; -+ -+ reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); -+ reg |= AT91C_EBI_CS3A_SM; -+ if (get_cm_rev() == 'A') -+ reg &= ~AT91C_EBI_NFD0_ON_D16; -+ else -+ reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); -+ -+ reg &= ~AT91C_EBI_DRV; -+ writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); -+ -+ /* Configure SMC CS3 */ -+ writel((AT91C_SMC_NWESETUP_(1) -+ | AT91C_SMC_NCS_WRSETUP_(0) -+ | AT91C_SMC_NRDSETUP_(2) -+ | AT91C_SMC_NCS_RDSETUP_(0)), -+ AT91C_BASE_SMC + SMC_SETUP3); -+ -+ writel((AT91C_SMC_NWEPULSE_(3) -+ | AT91C_SMC_NCS_WRPULSE_(5) -+ | AT91C_SMC_NRDPULSE_(4) -+ | AT91C_SMC_NCS_RDPULSE_(6)), -+ AT91C_BASE_SMC + SMC_PULSE3); -+ -+ writel((AT91C_SMC_NWECYCLE_(5) -+ | AT91C_SMC_NRDCYCLE_(7)), -+ AT91C_BASE_SMC + SMC_CYCLE3); -+ -+ writel((AT91C_SMC_READMODE -+ | AT91C_SMC_WRITEMODE -+ | AT91C_SMC_NWAITM_NWAIT_DISABLE -+ | AT91C_SMC_DBW_WIDTH_BITS_8 -+ | AT91_SMC_TDF_(1)), -+ AT91C_BASE_SMC + SMC_CTRL3); -+ -+ /* Configure the PIO controller */ -+ if (get_cm_rev() == 'A') -+ pio_configure(nand_pins_lo); -+ else -+ pio_configure(nand_pins_hi); -+ -+ pmc_enable_periph_clock(AT91C_ID_PIOC_D); -+} -+#endif /* #ifdef CONFIG_NANDFLASH */ diff --git a/recipes-bsp/at91bootstrap/at91bootstrap.inc b/recipes-bsp/at91bootstrap/at91bootstrap.inc index e887ffe..1126e63 100644 --- a/recipes-bsp/at91bootstrap/at91bootstrap.inc +++ b/recipes-bsp/at91bootstrap/at91bootstrap.inc @@ -19,19 +19,19 @@ inherit cml1 deploy SRC_URI_append = " \ file://defconfig \ file://onetime-slow-clock-switch.patch \ - file://disable-rtc-interrupts.patch \ + file://0003-disable-rtc-interrupts.patch \ file://at91sam9x5_4bit_pmecc_header.bin \ " -SRC_URI_append_mtrv1 = " file://mtrv1-DDRlowDriveStrength.patch \ +SRC_URI_append_mtrv1 = " file://0001-mtrv1-DDRlowDriveStrength.patch \ file://defconfig.mtr \ - file://at91bootstrap-3.8-mtr.patch \ + file://0005-at91bootstrap-3.8-mtr.patch \ " SRC_URI_append_mtr = " file://defconfig.mtr \ - file://at91bootstrap-3.8-mtr.patch \ + file://0005-at91bootstrap-3.8-mtr.patch \ " -SRC_URI_append_mtcdt = " file://at91bootstrap-3.8-mtcdt.patch " -SRC_URI_append_mtcap = " file://at91bootstrap-3.8-mtcdt.patch " +SRC_URI_append_mtcdt = " file://0005-at91bootstrap-3.8-mtcdt.patch " +SRC_URI_append_mtcap = " file://0005-at91bootstrap-3.8-mtcap.patch " DEPENDS += "bc-native" diff --git a/recipes-bsp/at91bootstrap/at91bootstrap_3.8.12.bb b/recipes-bsp/at91bootstrap/at91bootstrap_3.8.12.bb index dcbb649..daf807d 100644 --- a/recipes-bsp/at91bootstrap/at91bootstrap_3.8.12.bb +++ b/recipes-bsp/at91bootstrap/at91bootstrap_3.8.12.bb @@ -1,5 +1,5 @@ require at91bootstrap.inc -PR = "m2" +PR = "m3" LIC_FILES_CHKSUM = "file://main.c;endline=27;md5=a2a70db58191379e2550cbed95449fbd" |