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| author | Andrii Pientsov <andrii.pientsov@globallogic.com> | 2021-01-15 11:36:07 +0200 |
|---|---|---|
| committer | Andrii Pientsov <andrii.pientsov@globallogic.com> | 2021-01-15 11:36:07 +0200 |
| commit | 80ea39818fb8a55028d115720ead3ad6d241dc29 (patch) | |
| tree | 63e7fe799caf0cf482f41dfd71b60f6fb2da2692 /recipes-kernel/vizzini/vizzini_1.1.bb | |
| parent | ead8f56356152afddc2bf072f8338099d4f88d12 (diff) | |
| download | meta-multitech-atmel-80ea39818fb8a55028d115720ead3ad6d241dc29.tar.gz meta-multitech-atmel-80ea39818fb8a55028d115720ead3ad6d241dc29.tar.bz2 meta-multitech-atmel-80ea39818fb8a55028d115720ead3ad6d241dc29.zip | |
Add vizzini-1.1-ledrtig.patch for MTRE device.
Diffstat (limited to 'recipes-kernel/vizzini/vizzini_1.1.bb')
| -rw-r--r-- | recipes-kernel/vizzini/vizzini_1.1.bb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/recipes-kernel/vizzini/vizzini_1.1.bb b/recipes-kernel/vizzini/vizzini_1.1.bb index 8dc75f2..d7c6e0e 100644 --- a/recipes-kernel/vizzini/vizzini_1.1.bb +++ b/recipes-kernel/vizzini/vizzini_1.1.bb @@ -6,5 +6,7 @@ SRC_URI += "file://xr21v141x-lnx3.10-3.11.tar.gz \ file://vizzini-1.1-enable-cts.patch \ file://vizzini-1.1-rs485.patch \ " +SRC_URI_append_mtre = "file://vizzini-1.1-ledrtig.patch \ + " S = "${WORKDIR}/xr21v141x-lnx3.10-3.11" |