linux 5.4: fix ethernet not working on mtr (mii phy) devices

1 files changed, 147 insertions, 0 deletions

diff --git a/recipes-kernel/linux/linux-at91-5.4.81/linux-5.4-revert-net-macb-Properly-handle-phylink-on-at91rm9200.patch b/recipes-kernel/linux/linux-at91-5.4.81/linux-5.4-revert-net-macb-Properly-handle-phylink-on-at91rm9200.patch
new file mode 100644
index 0000000..d3fd677
--- /dev/null
+++ b/recipes-kernel/linux/linux-at91-5.4.81/linux-5.4-revert-net-macb-Properly-handle-phylink-on-at91rm9200.patch
@@ -0,0 +1,147 @@
+From d284f1295267ac26bfb857f99b5b8bad9c4b0036 Mon Sep 17 00:00:00 2001
+From: Mykyta Dorokhin <mykyta.dorokhin@globallogic.com>
+Date: Thu, 4 Feb 2021 02:39:01 +0200
+Subject: [PATCH] Revert "net: macb: Properly handle phylink on at91rm9200"
+
+This reverts commit ee268a316ee9cd6ce5e1799bf846fb0f82b8f424.
+
+MD: The changes introduced by this commit have to do with GigaBit Ethernet MAC (GEM).
+At the same time it breaks Ethernet on not-GigaBit MACs by writing to reserved NCFGR register
+bits (by GEM_BIT(mask) instructions).
+There is a discusiion on this conflict: https://lkml.org/lkml/2020/2/17/371
+
+---
+ drivers/net/ethernet/cadence/macb.h      |  1 -
+ drivers/net/ethernet/cadence/macb_main.c | 60 +++++++++++++++-----------------
+ 2 files changed, 28 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
+index c16cc1c..19fe4f4 100644
+--- a/drivers/net/ethernet/cadence/macb.h
++++ b/drivers/net/ethernet/cadence/macb.h
+@@ -645,7 +645,6 @@
+ #define MACB_CAPS_GEM_HAS_PTP			0x00000040
+ #define MACB_CAPS_BD_RD_PREFETCH		0x00000080
+ #define MACB_CAPS_NEEDS_RSTONUBR		0x00000100
+-#define MACB_CAPS_MACB_IS_EMAC			0x08000000
+ #define MACB_CAPS_FIFO_MODE			0x10000000
+ #define MACB_CAPS_GIGABIT_MODE_AVAILABLE	0x20000000
+ #define MACB_CAPS_SG_DISABLED			0x40000000
+diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
+index 7445e33..4f006d9 100644
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -537,21 +537,8 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode,
+ 	old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
+ 
+ 	/* Clear all the bits we might set later */
+-	ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | MACB_BIT(PAE));
+-
+-	if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
+-		if (state->interface == PHY_INTERFACE_MODE_RMII)
+-			ctrl |= MACB_BIT(RM9200_RMII);
+-	} else {
+-		ctrl &= ~(GEM_BIT(GBE) | GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
+-
+-		/* We do not support MLO_PAUSE_RX yet */
+-		if (state->pause & MLO_PAUSE_TX)
+-			ctrl |= MACB_BIT(PAE);
+-
+-		if (state->interface == PHY_INTERFACE_MODE_SGMII)
+-			ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
+-	}
++	ctrl &= ~(GEM_BIT(GBE) | MACB_BIT(SPD) | MACB_BIT(FD) | MACB_BIT(PAE) |
++		  GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
+ 
+ 	if (state->speed == SPEED_1000)
+ 		ctrl |= GEM_BIT(GBE);
+@@ -561,6 +548,13 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode,
+ 	if (state->duplex)
+ 		ctrl |= MACB_BIT(FD);
+ 
++	/* We do not support MLO_PAUSE_RX yet */
++	if (state->pause & MLO_PAUSE_TX)
++		ctrl |= MACB_BIT(PAE);
++
++	if (state->interface == PHY_INTERFACE_MODE_SGMII)
++		ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
++
+ 	/* Apply the new configuration, if any */
+ 	if (old_ctrl ^ ctrl)
+ 		macb_or_gem_writel(bp, NCFGR, ctrl);
+@@ -579,10 +573,9 @@ static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
+ 	unsigned int q;
+ 	u32 ctrl;
+ 
+-	if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
+-		for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
+-			queue_writel(queue, IDR,
+-				     bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
++	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
++		queue_writel(queue, IDR,
++			     bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
+ 
+ 	/* Disable Rx and Tx */
+ 	ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
+@@ -599,19 +592,17 @@ static void macb_mac_link_up(struct phylink_config *config, unsigned int mode,
+ 	struct macb_queue *queue;
+ 	unsigned int q;
+ 
+-	if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
+-		macb_set_tx_clk(bp->tx_clk, bp->speed, ndev);
++	macb_set_tx_clk(bp->tx_clk, bp->speed, ndev);
+ 
+-		/* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
+-		 * cleared the pipeline and control registers.
+-		 */
+-		bp->macbgem_ops.mog_init_rings(bp);
+-		macb_init_buffers(bp);
++	/* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
++	 * cleared the pipeline and control registers.
++	 */
++	bp->macbgem_ops.mog_init_rings(bp);
++	macb_init_buffers(bp);
+ 
+-		for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
+-			queue_writel(queue, IER,
+-				     bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
+-	}
++	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
++		queue_writel(queue, IER,
++			     bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
+ 
+ 	/* Enable Rx and Tx */
+ 	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
+@@ -4031,6 +4022,7 @@ static int at91ether_init(struct platform_device *pdev)
+ 	struct net_device *dev = platform_get_drvdata(pdev);
+ 	struct macb *bp = netdev_priv(dev);
+ 	int err;
++	u32 reg;
+ 
+ 	bp->queues[0].bp = bp;
+ 
+@@ -4044,7 +4036,11 @@ static int at91ether_init(struct platform_device *pdev)
+ 
+ 	macb_writel(bp, NCR, 0);
+ 
+-	macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
++	reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
++	if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
++		reg |= MACB_BIT(RM9200_RMII);
++
++	macb_writel(bp, NCFGR, reg);
+ 
+ 	return 0;
+ }
+@@ -4197,7 +4193,7 @@ static int fu540_c000_init(struct platform_device *pdev)
+ };
+ 
+ static const struct macb_config emac_config = {
+-	.caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
++	.caps = MACB_CAPS_NEEDS_RSTONUBR,
+ 	.clk_init = at91ether_clk_init,
+ 	.init = at91ether_init,
+ };
+-- 
+1.9.1
+