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Diffstat (limited to 'libloragw/src/loragw_fpga.c')
-rw-r--r--libloragw/src/loragw_fpga.c29
1 files changed, 19 insertions, 10 deletions
diff --git a/libloragw/src/loragw_fpga.c b/libloragw/src/loragw_fpga.c
index ce1c9c6..63c6d3b 100644
--- a/libloragw/src/loragw_fpga.c
+++ b/libloragw/src/loragw_fpga.c
@@ -175,9 +175,14 @@ int lgw_fpga_configure(uint32_t tx_notch_freq) {
DEBUG_MSG("ERROR: Failed to configure FPGA polarity\n");
return LGW_REG_ERROR;
}
- /* Set Attenuator mode to be used for the full card*/
- if (fpga_version == 32) {
- lgw_fpga_reg_w(LGW_FPGA_RF_ATTN_MODE, 0);
+ }
+
+ /* Set Attenuator mode to 1 to allow it to use it*/
+ if (fpga_supports_attenuator()) {
+ x = lgw_fpga_reg_w(LGW_FPGA_RF_ATTN_MODE, 1);
+ if (x != LGW_REG_SUCCESS) {
+ DEBUG_MSG("ERROR: Failed to configure Attenuator mode\n");
+ return LGW_REG_ERROR;
}
}
@@ -361,17 +366,21 @@ int lgw_fpga_reg_rb(uint16_t register_id, uint8_t *data, uint16_t size) {
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
-int lgw_set_attenuation(float attenuation) {
- int i;
- int32_t val;
- if (attenuation > 31.75 || attenuation < 0) {
+int lgw_set_attenuation(uint8_t *attn) {
+ if (*attn > 127) {
return LGW_HAL_ERROR;
}
- i = lgw_fpga_reg_w(LGW_FPGA_RF_ATTN_VALUE, (uint8_t)(attenuation * LGW_RF_ATTN_CONV_CONST));
+ int i;
+ /* The max value allowed for 7 bits of a register */
+ uint8_t max_attn = 127;
+
+ /* Shifting the float value to apply get the adjusted integer */
+ uint8_t shifted_attn = (uint8_t)(*attn * LGW_RF_ATTN_CONV_CONST);
- i = lgw_fpga_reg_r(LGW_FPGA_RF_ATTN_VALUE, &val);
+ /* The attenuator value is bit 0-6 of the register hence must be limited to 127 */
+ uint8_t reg_attn = max_attn ^ ((shifted_attn ^ max_attn) & -(shifted_attn < max_attn));
+ i = lgw_fpga_reg_w(LGW_FPGA_RF_ATTN_VALUE, reg_attn);
if (i == LGW_REG_SUCCESS) {
- DEBUG_PRINTF("INFO: Attenuator set to %u \n", (uint8_t)val);
return LGW_HAL_SUCCESS;
} else {
return LGW_HAL_ERROR;