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authorHarsh Sharma <92harshsharma@gmail.com>2018-06-13 13:33:21 -0500
committerHarsh Sharma <92harshsharma@gmail.com>2018-06-13 13:33:21 -0500
commitd4c63335aec7639c154c5a8e00b5b5f0a10d7f78 (patch)
treee01e38aa9715e2804c8ba361b3e9eb9fd035c38f /libloragw
parent7c383be1542368f2601015d9fc2a417197677677 (diff)
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Applied patch: lora-gateway-v28-skip-IQ-invert
Diffstat (limited to 'libloragw')
-rw-r--r--libloragw/src/loragw_fpga.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/libloragw/src/loragw_fpga.c b/libloragw/src/loragw_fpga.c
index 465f43e..40b0b2e 100644
--- a/libloragw/src/loragw_fpga.c
+++ b/libloragw/src/loragw_fpga.c
@@ -164,11 +164,14 @@ int lgw_fpga_configure(uint32_t tx_notch_freq) {
return LGW_REG_ERROR;
}
- /* Required for Semtech AP2 reference design */
- x = lgw_fpga_reg_w(LGW_FPGA_CTRL_INVERT_IQ, 1);
- if (x != LGW_REG_SUCCESS) {
- DEBUG_MSG("ERROR: Failed to configure FPGA polarity\n");
- return LGW_REG_ERROR;
+
+ if (read_fpga_version() > 28) {
+ /* Required for Semtech AP2 reference design and AP1.5 > v28 */
+ x = lgw_fpga_reg_w(LGW_FPGA_CTRL_INVERT_IQ, 1);
+ if (x != LGW_REG_SUCCESS) {
+ DEBUG_MSG("ERROR: Failed to configure FPGA polarity\n");
+ return LGW_REG_ERROR;
+ }
}
/* Configure TX notch filter */