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	 / _____)             _              | |    
	( (____  _____ ____ _| |_ _____  ____| |__  
	 \____ \| ___ |    (_   _) ___ |/ ___)  _ \ 
	 _____) ) ____| | | || |_| ____( (___| | | |
	(______/|_____)_|_|_| \__)_____)\____)_| |_|
		©2013 Semtech-Cycleo

Lora Gateway SPI stress test
=============================

1. Introduction
----------------

This software is used to check the reliability of the link between the host
platform (on which the program is run) and the Lora concentrator register file
that is the interface through which all interaction with the Lora concentrator
happens.

2. Dependencies
----------------

This program only access the Lora gateway HAL library through its loragw_reg
"named registers" access sub-module.

It was tested with v1.0.0 of the libloragw library, and should be compatible
with any later version of the library and the hardware, assuming the registers
used for the tests are still present.

The registers used are:
 * LGW_VERSION
 * LGW_IMPLICIT_PAYLOAD_LENGHT
 * LGW_FSK_REF_PATTERN_LSB
 * LGW_RX_DATA_BUF_ADDR
 * LGW_RX_DATA_BUF_DATA

A data buffer accessible through the 2 registers above must be implemented.

3. Usage
---------

The tests run forever or until an error is detected.
Press Ctrl+C to stop the application.

When an error is detected, diagnosis information are displayed. Please refer to
the source code for more details on what is displayed for diagnosis.

All tests use pseudo-random data generated by the rand() function. The random
generator is not seeded, and the same sequence of data will be use each time the
program is launched.

Basically, some random data is written, read back and then compared to the
initial written data. Some "useless" read on others registers might be inserted
to be sure that the data read back is coming from the hardware, and not from the
internal buffer(s) of the software driver(s).

Test 1 > R/W on a simple 8-bit register

Test 2 > R/W on a simple 8-bit register with interstitial reads on VERSION

Test 3 > R/W on a 32-bit register (short SPI bursts access)

Test 4 > data buffer R/W (long SPI bursts access)

4. Changelog
-------------

2013-10-24, v1
Initial version.