diff options
Diffstat (limited to 'loragw_hal/src/loragw_reg.c')
| -rw-r--r-- | loragw_hal/src/loragw_reg.c | 61 |
1 files changed, 45 insertions, 16 deletions
diff --git a/loragw_hal/src/loragw_reg.c b/loragw_hal/src/loragw_reg.c index 716c6c0..a9122d2 100644 --- a/loragw_hal/src/loragw_reg.c +++ b/loragw_hal/src/loragw_reg.c @@ -66,7 +66,7 @@ this file is autogenerated from registers description const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {-1,0,0,0,2,0,0}, /* PAGE_REG */ {-1,0,7,0,1,0,0}, /* SOFT_RESET */ - {-1,1,0,0,8,1,101}, /* VERSION */ + {-1,1,0,0,8,1,103}, /* VERSION */ {-1,2,0,0,16,0,0}, /* RX_DATA_BUF_ADDR */ {-1,4,0,0,8,0,0}, /* RX_DATA_BUF_DATA */ {-1,5,0,0,8,0,0}, /* TX_DATA_BUF_ADDR */ @@ -82,8 +82,9 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {-1,16,0,0,1,0,0}, /* MBWSSF_MODEM_ENABLE */ {-1,16,1,0,1,0,0}, /* CONCENTRATOR_MODEM_ENABLE */ {-1,16,2,0,1,0,0}, /* FSK_MODEM_ENABLE */ - {-1,17,0,0,1,0,0}, /* CLK32M_EN */ - {-1,17,1,0,1,0,0}, /* CLKHS_EN */ + {-1,16,3,0,1,0,0}, /* GLOBAL_EN */ + {-1,17,0,0,1,0,1}, /* CLK32M_EN */ + {-1,17,1,0,1,0,1}, /* CLKHS_EN */ {-1,18,0,0,1,0,0}, /* START_BIST0 */ {-1,18,1,0,1,0,0}, /* START_BIST1 */ {-1,18,2,0,1,0,0}, /* CLEAR_BIST0 */ @@ -143,14 +144,16 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {-1,29,0,0,5,0,0}, /* GPIO_MODE */ {-1,30,0,0,5,1,0}, /* GPIO_PIN_REG_IN */ {-1,31,0,0,5,0,0}, /* GPIO_PIN_REG_OUT */ - {-1,32,0,0,8,0,0}, /* MCU_AGC_STATUS */ + {-1,32,0,0,8,1,0}, /* MCU_AGC_STATUS */ + {-1,125,0,0,8,1,0}, /* MCU_ARB_STATUS */ {-1,126,0,0,8,1,1}, /* CHIP_ID */ - {-1,127,0,0,1,0,0}, /* EMERGENCY_FORCE_HOST_CTRL */ + {-1,127,0,0,1,0,1}, /* EMERGENCY_FORCE_HOST_CTRL */ {0,33,0,0,1,0,0}, /* RX_INVERT_IQ */ {0,33,1,0,1,0,1}, /* MODEM_INVERT_IQ */ {0,33,2,0,1,0,0}, /* MBWSSF_MODEM_INVERT_IQ */ {0,33,3,0,1,0,0}, /* RX_EDGE_SELECT */ {0,33,4,0,1,0,0}, /* MISC_RADIO_EN */ + {0,33,5,0,1,0,0}, /* FSK_MODEM_INVERT_IQ */ {0,34,0,0,4,0,7}, /* FILTER_GAIN */ {0,35,0,0,8,0,240}, /* RADIO_SELECT */ {0,36,0,1,13,0,-384}, /* IF_FREQ_0 */ @@ -189,7 +192,6 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {0,77,0,0,4,0,4}, /* CORR_SIG_NOISE_RATIO_SF12 */ {0,78,0,0,4,0,4}, /* CORR_NUM_SAME_PEAK */ {0,78,4,0,3,0,5}, /* CORR_MAC_GAIN */ - {0,79,0,0,12,0,0}, /* ADJUST_MODEM_START_OFFSET_RDX8 */ {0,81,0,0,12,0,0}, /* ADJUST_MODEM_START_OFFSET_RDX4 */ {0,83,0,0,12,0,4092}, /* ADJUST_MODEM_START_OFFSET_SF12_RDX4 */ {0,85,0,0,8,0,7}, /* DBG_CORR_SELECT_SF */ @@ -197,7 +199,7 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {0,87,0,0,8,1,0}, /* DBG_DETECT_CPT */ {0,88,0,0,8,1,0}, /* DBG_SYMB_CPT */ {0,89,0,0,1,0,1}, /* CHIRP_INVERT_RX */ - {0,89,1,0,1,0,0}, /* DC_NOTCH_EN */ + {0,89,1,0,1,0,1}, /* DC_NOTCH_EN */ {0,90,0,0,1,0,0}, /* IMPLICIT_CRC_EN */ {0,90,1,0,3,0,0}, /* IMPLICIT_CODING_RATE */ {0,91,0,0,8,0,0}, /* IMPLICIT_PAYLOAD_LENGHT */ @@ -219,7 +221,6 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {0,103,0,0,8,0,0}, /* ZERO_PAD */ {0,104,0,0,4,0,8}, /* DEC_GAIN_OFFSET */ {0,104,4,0,4,0,7}, /* CHAN_GAIN_OFFSET */ - {0,105,0,0,1,0,1}, /* FORCE_HOST_REG_CTRL */ {0,105,1,0,1,0,1}, /* FORCE_HOST_RADIO_CTRL */ {0,105,2,0,1,0,1}, /* FORCE_HOST_FE_CTRL */ {0,105,3,0,1,0,1}, /* FORCE_DEC_FILTER_GAIN */ @@ -249,13 +250,15 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {1,34,0,0,16,0,0}, /* TX_START_DELAY */ {1,36,0,0,4,0,1}, /* TX_FRAME_SYNCH_PEAK1_POS */ {1,36,4,0,4,0,2}, /* TX_FRAME_SYNCH_PEAK2_POS */ - {1,39,0,0,8,0,0}, /* TX_OFFSET_I */ - {1,40,0,0,8,0,0}, /* TX_OFFSET_Q */ + {1,37,0,0,3,0,0}, /* TX_RAMP_DURATION */ + {1,39,0,1,8,0,0}, /* TX_OFFSET_I */ + {1,40,0,1,8,0,0}, /* TX_OFFSET_Q */ {1,41,0,0,1,0,0}, /* TX_MODE */ {1,41,1,0,4,0,0}, /* TX_ZERO_PAD */ {1,41,5,0,1,0,0}, /* TX_EDGE_SELECT */ + {1,41,6,0,1,0,0}, /* TX_EDGE_SELECT_TOP */ {1,42,0,0,2,0,0}, /* TX_GAIN */ - {1,42,2,0,3,0,0}, /* TX_CHIRP_LOW_PASS */ + {1,42,2,0,3,0,5}, /* TX_CHIRP_LOW_PASS */ {1,42,5,0,2,0,0}, /* TX_FCC_WIDEBAND */ {1,42,7,0,1,0,1}, /* TX_SWAP_IQ */ {1,43,0,0,1,0,0}, /* MBWSSF_IMPLICIT_HEADER */ @@ -286,14 +289,37 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {1,60,0,0,4,0,7}, /* MBWSSF_RATE_SF */ {1,60,4,0,1,0,1}, /* MBWSSF_ONLY_CRC_EN */ {1,61,0,0,8,0,255}, /* MBWSSF_MAX_PAYLOAD_LEN */ - {1,62,0,0,8,1,0}, /* TX_STATUS */ + {1,62,0,0,8,1,128}, /* TX_STATUS */ + {1,63,0,0,3,0,0}, /* FSK_CH_BW_EXPO */ + {1,63,3,0,3,0,0}, /* FSK_RSSI_LENGTH */ + {1,63,6,0,1,0,0}, /* FSK_RX_INVERT */ + {1,63,7,0,1,0,0}, /* FSK_PKT_MODE */ + {1,64,0,0,3,0,0}, /* FSK_PSIZE */ + {1,64,3,0,1,0,0}, /* FSK_CRC_EN */ + {1,64,4,0,2,0,0}, /* FSK_DCFREE_ENC */ + {1,64,6,0,1,0,0}, /* FSK_CRC_IBM */ + {1,65,0,0,5,0,0}, /* FSK_ERROR_OSR_TOL */ + {1,65,7,0,1,0,0}, /* FSK_RADIO_SELECT */ + {1,66,0,0,16,0,0}, /* FSK_BR_RATIO */ + {1,68,0,0,32,0,0}, /* FSK_REF_PATTERN_LSB */ + {1,72,0,0,32,0,0}, /* FSK_REF_PATTERN_MSB */ + {1,76,0,0,8,0,0}, /* FSK_PKT_LENGTH */ + {1,77,0,0,1,0,1}, /* FSK_TX_GAUSSIAN_EN */ + {1,77,1,0,2,0,0}, /* FSK_TX_GAUSSIAN_SELECT_BT */ + {1,77,3,0,1,0,1}, /* FSK_TX_PATTERN_EN */ + {1,77,4,0,1,0,0}, /* FSK_TX_PREAMBLE_SEQ */ + {1,77,5,0,3,0,0}, /* FSK_TX_PSIZE */ + {1,80,0,0,8,0,0}, /* FSK_NODE_ADRS */ + {1,81,0,0,8,0,0}, /* FSK_BROADCAST */ + {1,82,0,0,1,0,1}, /* FSK_AUTO_AFC_ON */ + {1,83,0,0,10,0,0}, /* FSK_PATTERN_TIMEOUT_CFG */ {2,33,0,0,8,0,0}, /* SPI_RADIO_A__DATA */ {2,34,0,0,8,1,0}, /* SPI_RADIO_A__DATA_READBACK */ - {2,35,0,0,14,0,0}, /* SPI_RADIO_A__ADDR */ + {2,35,0,0,8,0,0}, /* SPI_RADIO_A__ADDR */ {2,37,0,0,1,0,0}, /* SPI_RADIO_A__CS */ {2,38,0,0,8,0,0}, /* SPI_RADIO_B__DATA */ {2,39,0,0,8,1,0}, /* SPI_RADIO_B__DATA_READBACK */ - {2,40,0,0,14,0,0}, /* SPI_RADIO_B__ADDR */ + {2,40,0,0,8,0,0}, /* SPI_RADIO_B__ADDR */ {2,42,0,0,1,0,0}, /* SPI_RADIO_B__CS */ {2,43,0,0,1,0,0}, /* RADIO_A_EN */ {2,43,1,0,1,0,0}, /* RADIO_B_EN */ @@ -312,7 +338,6 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {2,47,6,0,1,0,0}, /* CAPTURE_FORCE_TRIGGER */ {2,47,7,0,1,0,0}, /* CAPTURE_WRAP */ {2,48,0,0,16,0,0}, /* CAPTURE_PERIOD */ - {2,50,0,0,3,0,3}, /* LED_REG */ {2,51,0,0,8,1,0}, /* MODEM_STATUS */ {2,52,0,0,8,1,0}, /* VALID_HEADER_COUNTER_0 */ {2,54,0,0,8,1,0}, /* VALID_PACKET_COUNTER_0 */ @@ -359,7 +384,11 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {2,89,1,0,1,0,1}, /* GPS_POL */ {2,90,0,1,8,0,0}, /* SW_TEST_REG1 */ {2,91,2,1,6,0,0}, /* SW_TEST_REG2 */ - {2,92,0,1,16,0,0} /* SW_TEST_REG3 */ + {2,92,0,1,16,0,0}, /* SW_TEST_REG3 */ + {2,94,0,0,4,1,0}, /* DATA_MNGT_STATUS */ + {2,95,0,0,5,1,0}, /* DATA_MNGT_CPT_FRAME_ALLOCATED */ + {2,96,0,0,5,1,0}, /* DATA_MNGT_CPT_FRAME_FINISHED */ + {2,97,0,0,5,1,0} /* DATA_MNGT_CPT_FRAME_READEN */ }; /* -------------------------------------------------------------------------- */ |