diff options
Diffstat (limited to 'loragw_hal/inc')
| -rw-r--r-- | loragw_hal/inc/loragw_aux.h | 28 | ||||
| -rw-r--r-- | loragw_hal/inc/loragw_hal.h | 234 | ||||
| -rw-r--r-- | loragw_hal/inc/loragw_reg.h | 397 | ||||
| -rw-r--r-- | loragw_hal/inc/loragw_spi.h | 92 |
4 files changed, 751 insertions, 0 deletions
diff --git a/loragw_hal/inc/loragw_aux.h b/loragw_hal/inc/loragw_aux.h new file mode 100644 index 0000000..a0cc7cb --- /dev/null +++ b/loragw_hal/inc/loragw_aux.h @@ -0,0 +1,28 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + ©2013 Semtech-Cycleo + +Description: + Lora gateway Hardware Abstraction Layer +*/ + + +#ifndef _LORAGW_AUX_H +#define _LORAGW_AUX_H + +/* -------------------------------------------------------------------------- */ +/* --- PUBLIC FUNCTIONS PROTOTYPES ------------------------------------------ */ + +/** +@brief Wait for a certain time (millisecond accuracy) +@param t number of milliseconds to wait. +*/ +void wait_ms(unsigned long t); + +#endif + +/* --- EOF ------------------------------------------------------------------ */ diff --git a/loragw_hal/inc/loragw_hal.h b/loragw_hal/inc/loragw_hal.h new file mode 100644 index 0000000..39c8ca0 --- /dev/null +++ b/loragw_hal/inc/loragw_hal.h @@ -0,0 +1,234 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + ©2013 Semtech-Cycleo + +Description: + Lora gateway Hardware Abstraction Layer +*/ + + +#ifndef _LORAGW_HAL_H +#define _LORAGW_HAL_H + +/* -------------------------------------------------------------------------- */ +/* --- DEPENDANCIES --------------------------------------------------------- */ + +#include <stdint.h> /* C99 types */ +#include <stdbool.h> /* bool type */ + +/* -------------------------------------------------------------------------- */ +/* --- PUBLIC CONSTANTS ----------------------------------------------------- */ + +/* return status code */ +#define LGW_HAL_SUCCESS 0 +#define LGW_HAL_ERROR -1 + +/* hardware characteristics */ +#define LGW_RF_CHAIN_NB 2 /* number of RF chains */ +#define LGW_IF_CHAIN_NB 10 /* number of IF+modem RX chains */ +#define LGW_MULTI_NB 4 /* number of Lora 'multi SF' chains */ + +#define LGW_PKT_FIFO_SIZE 8 +#define LGW_DATABUFF_SIZE 1024 +#define LGW_RF_BANDWIDTH 800000 + +/* +SX1275 frequency setting : +F_register(24bit) = F_rf (Hz) / F_step(Hz) + = F_rf (Hz) * 2^19 / F_xtal(Hz) + = F_rf (Hz) * 256/15625 +*/ +#define LGW_XTAL_FREQU 32000000 +#define LGW_SW1257_DENUM 15625 /* pll settings denominator when the numerator is 2^8 */ + +/* to use those parameters, declare a local constant, and use 'rf_chain' as index */ +#define LGW_RF_RX_LOWFREQ {863000000, 863000000} +#define LGW_RF_RX_UPFREQ {870000000, 870000000} +#define LGW_RF_TX_LOWFREQ {863000000, 863000000} +#define LGW_RF_TX_UPFREQ {870000000, 870000000} + +/* type of if_chain + modem */ +#define IF_UNDEFINED 0 +#define IF_LORA_STD 0x10 /* if + standard single-SF Lora modem */ +#define IF_LORA_MULTI 0x11 /* if + Lora receiver with multi-SF capability */ +#define IF_FSK_STD 0x20 /* if + standard FSK modem */ + +/* configuration of available IF chains and modems on the hardware */ +/* to use, declare a local constant, and use 'if_chain' as index */ +#define LGW_IFMODEM_CONFIG {\ + IF_LORA_MULTI, \ + IF_LORA_MULTI, \ + IF_LORA_MULTI, \ + IF_LORA_MULTI, \ + IF_UNDEFINED, \ + IF_UNDEFINED, \ + IF_UNDEFINED, \ + IF_UNDEFINED, \ + IF_LORA_STD, \ + IF_FSK_STD } + +/* values available for the 'modulation' parameters */ +#define MOD_UNDEFINED 0 +#define MOD_LORA 0x10 +#define MOD_FSK 0x20 +#define MOD_GFSK 0x21 + +/* values available for the 'bandwidth' parameters */ +#define BW_UNDEFINED 0 +#define BW_500KHZ 0x04 +#define BW_250KHZ 0x08 +#define BW_125KHZ 0x0C +// TODO: add all the supporter FSK bandwidth + +/* values available for the 'datarate' parameters */ +#define DR_UNDEFINED 0 +#define DR_LORA_SF7 0x1002 +#define DR_LORA_SF8 0x1004 +#define DR_LORA_SF9 0x1008 +#define DR_LORA_SF10 0x1010 +#define DR_LORA_SF11 0x1020 +#define DR_LORA_SF12 0x1040 +#define DR_LORA_MULTI 0x107E +// TODO: add FSK datarates + +/* values available for the 'coderate' parameters */ +#define CR_UNDEFINED 0 +#define CR_LORA_4_5 0x11 +#define CR_LORA_4_6 0x12 +#define CR_LORA_4_7 0x13 +#define CR_LORA_4_8 0x14 + +/* values available for the 'status' parameter */ +#define STAT_UNDEFINED 0x00 +#define STAT_NO_CRC 0x01 +#define STAT_CRC_BAD 0x11 +#define STAT_CRC_OK 0x10 + +/* values available for the 'tx_mode' parameter */ +#define IMMEDIATE 0 +#define TIMESTAMPED 1 +#define ON_GPS 2 +//#define ON_EVENT 3 +//#define GPS_DELAYED 4 +//#define EVENT_DELAYED 5 + +/* -------------------------------------------------------------------------- */ +/* --- PUBLIC TYPES --------------------------------------------------------- */ + +/** +@struct lgw_conf_rxrf_s +@brief Configuration structure for a RF chain +*/ +struct lgw_conf_rxrf_s { + bool enable; /*!> enable or disable that RF chain */ + uint32_t freq_hz; /*!> center frequency of the radio in Hz */ +}; + +/** +@struct lgw_conf_rxif_s +@brief Configuration structure for an IF chain +*/ +struct lgw_conf_rxif_s { + bool enable; /*!> enable or disable that IF chain */ + uint8_t rf_chain; /*!> to which RF chain is that IF chain associated */ + int32_t freq_hz; /*!> center frequ of the IF chain, relative to RF chain frequency */ + uint8_t bandwidth; /*!> RX bandwidth, 0 for default */ + uint16_t datarate; /*!> RX datarate, 0 for default */ +}; + +/** +@struct lgw_pkt_rx_s +@brief Structure containing the metadata of a packet that was received and a pointer to the payload +*/ +struct lgw_pkt_rx_s { + uint8_t if_chain; /*!> by which IF chain was packet received */ + uint8_t status; /*!> status of the received packet */ + uint8_t modulation; /*!> modulation used by the packet */ + uint8_t bandwidth; /*!> modulation bandwidth (LORA only) */ + uint16_t datarate; /*!> RX datarate of the packet */ + uint8_t coderate; /*!> error-correcting code of the packet */ + uint32_t count_us; /*!> internal gateway counter for timestamping, 1 microsecond resolution */ + float rssi; /*!> average packet RSSI in dB */ + float snr; /*!> average packet SNR, in dB (LORA only) */ + float snr_min; /*!> minimum packet SNR, in dB (LORA only) */ + float snr_max; /*!> maximum packet SNR, in dB (LORA only) */ + uint16_t crc; /*!> CRC that was received in the payload */ + uint16_t size; /*!> payload size in bytes */ + uint8_t *payload; /*!> pointer to the payload */ +}; + +/** +@struct lgw_pkt_tx_s +@brief Structure containing the configuration of a packet to send and a pointer to the payload +*/ +struct lgw_pkt_tx_s { + uint32_t freq_hz; /*!> center frequency of TX */ + uint8_t tx_mode; /*!> select on what event/time the TX is triggered */ + uint32_t count_us; /*!> timestamp or delay in microseconds for TX trigger */ + uint8_t rf_chain; /*!> through which RF chain will the packet be sent */ + int8_t rf_power; /*!> TX power, in dBm */ + uint8_t modulation; /*!> modulation to use for the packet */ + uint8_t bandwidth; /*!> modulation bandwidth (LORA only) */ + uint16_t f_dev; /*!> frequency deviation (FSK only) */ + uint16_t datarate; /*!> TX datarate */ + uint8_t coderate; /*!> error-correcting code of the packet */ + uint16_t preamble; /*!> set the preamble length, 0 for default */ + bool no_crc; /*!> if true, do not send a CRC in the packet */ + bool no_header; /*!> if true, enable implicit header mode */ + uint16_t size; /*!> payload size in bytes */ + uint8_t *payload; /*!> pointer to the payload */ +}; + +/* -------------------------------------------------------------------------- */ +/* --- PUBLIC FUNCTIONS PROTOTYPES ------------------------------------------ */ + +/** +@brief Configure an RF chain (must configure before start) +@param rf_chain number of the RF chain to configure [0, LGW_RF_CHAIN_NB - 1] +@param conf structure containing the configuration parameters +@return LGW_HAL_ERROR id the operation failed, LGW_HAL_SUCCESS else +*/ +int lgw_rxrf_setconf(uint8_t rf_chain, struct lgw_conf_rxrf_s conf); + +/** +@brief Configure an IF chain + modem (must configure before start) +@param if_chain number of the IF chain + modem to configure [0, LGW_IF_CHAIN_NB - 1] +@param conf structure containing the configuration parameters +@return LGW_HAL_ERROR id the operation failed, LGW_HAL_SUCCESS else +*/ +int lgw_rxif_setconf(uint8_t if_chain, struct lgw_conf_rxif_s conf); + +/** +@brief Connect to the Lora gateway, reset it and configure it according to previously set parameters +@return LGW_HAL_ERROR id the operation failed, LGW_HAL_SUCCESS else +*/ +int lgw_start(void); + +/** +@brief Stop the Lora gateway and disconnect it +@return LGW_HAL_ERROR id the operation failed, LGW_HAL_SUCCESS else +*/ +int lgw_stop(void); + +/** +@brief A non-blocking function that will fetch up to 'max_pkt' packets from the Lora gateway FIFO and data buffer +@param max_pkt maximum number of packet that must be retrieved (equal to the size of the array of struct) +@param pkt_data pointer to an array of struct that will receive the packet metadata and payload pointers +@return LGW_HAL_ERROR id the operation failed, else the number of packets retrieved +*/ +int lgw_receive(uint8_t max_pkt, struct lgw_pkt_rx_s *pkt_data); + +/** +@brief Schedule a packet to be send immediately or after a delay depending on tx_mode +@param pkt_data structure containing the data and metadata for the packet to send +@return LGW_HAL_ERROR id the operation failed, LGW_HAL_SUCCESS else +*/ +int lgw_send(struct lgw_pkt_tx_s pkt_data); + +#endif + +/* --- EOF ------------------------------------------------------------------ */ diff --git a/loragw_hal/inc/loragw_reg.h b/loragw_hal/inc/loragw_reg.h new file mode 100644 index 0000000..e0f9390 --- /dev/null +++ b/loragw_hal/inc/loragw_reg.h @@ -0,0 +1,397 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + ©2013 Semtech-Cycleo + +Description: + Functions used to handle a single Lora gateway. + Registers are addressed by name. + Multi-bytes registers are handled automatically. + Read-modify-write is handled automatically. +*/ + + +#ifndef _LORAGW_REG_H +#define _LORAGW_REG_H + +/* -------------------------------------------------------------------------- */ +/* --- DEPENDANCIES --------------------------------------------------------- */ + +#include <stdint.h> /* C99 types */ +#include <stdbool.h> /* bool type */ + +/* -------------------------------------------------------------------------- */ +/* --- PUBLIC CONSTANTS ----------------------------------------------------- */ + +#define LGW_REG_SUCCESS 0 +#define LGW_REG_ERROR -1 + +/* +auto generated register mapping for C code : 24-Jun-2013 20:29:09 +this file contains autogenerated C struct used to access the LORA register from the Primer firmware +this file is autogenerated from registers description +290 registers are defined +*/ + +#define LGW_PAGE_REG 0 +#define LGW_SOFT_RESET 1 +#define LGW_VERSION 2 +#define LGW_RX_DATA_BUF_ADDR 3 +#define LGW_RX_DATA_BUF_DATA 4 +#define LGW_TX_DATA_BUF_ADDR 5 +#define LGW_TX_DATA_BUF_DATA 6 +#define LGW_CAPTURE_RAM_ADDR 7 +#define LGW_CAPTURE_RAM_DATA 8 +#define LGW_MCU_PROM_ADDR 9 +#define LGW_MCU_PROM_DATA 10 +#define LGW_RX_PACKET_DATA_FIFO_NUM_STORED 11 +#define LGW_RX_PACKET_DATA_FIFO_ADDR_POINTER 12 +#define LGW_RX_PACKET_DATA_FIFO_STATUS 13 +#define LGW_RX_PACKET_DATA_FIFO_PAYLOAD_SIZE 14 +#define LGW_MBWSSF_MODEM_ENABLE 15 +#define LGW_CONCENTRATOR_MODEM_ENABLE 16 +#define LGW_FSK_MODEM_ENABLE 17 +#define LGW_CLK32M_EN 18 +#define LGW_CLKHS_EN 19 +#define LGW_START_BIST0 20 +#define LGW_START_BIST1 21 +#define LGW_CLEAR_BIST0 22 +#define LGW_CLEAR_BIST1 23 +#define LGW_BIST0_FINISHED 24 +#define LGW_BIST1_FINISHED 25 +#define LGW_MCU_AGC_PROG_RAM_BIST_STATUS 26 +#define LGW_MCU_ARB_PROG_RAM_BIST_STATUS 27 +#define LGW_CAPTURE_RAM_BIST_STATUS 28 +#define LGW_CHAN_FIR_RAM0_BIST_STATUS 29 +#define LGW_CHAN_FIR_RAM1_BIST_STATUS 30 +#define LGW_CORR0_RAM_BIST_STATUS 31 +#define LGW_CORR1_RAM_BIST_STATUS 32 +#define LGW_CORR2_RAM_BIST_STATUS 33 +#define LGW_CORR3_RAM_BIST_STATUS 34 +#define LGW_CORR4_RAM_BIST_STATUS 35 +#define LGW_CORR5_RAM_BIST_STATUS 36 +#define LGW_CORR6_RAM_BIST_STATUS 37 +#define LGW_CORR7_RAM_BIST_STATUS 38 +#define LGW_MODEM0_RAM0_BIST_STATUS 39 +#define LGW_MODEM1_RAM0_BIST_STATUS 40 +#define LGW_MODEM2_RAM0_BIST_STATUS 41 +#define LGW_MODEM3_RAM0_BIST_STATUS 42 +#define LGW_MODEM4_RAM0_BIST_STATUS 43 +#define LGW_MODEM5_RAM0_BIST_STATUS 44 +#define LGW_MODEM6_RAM0_BIST_STATUS 45 +#define LGW_MODEM7_RAM0_BIST_STATUS 46 +#define LGW_MODEM0_RAM1_BIST_STATUS 47 +#define LGW_MODEM1_RAM1_BIST_STATUS 48 +#define LGW_MODEM2_RAM1_BIST_STATUS 49 +#define LGW_MODEM3_RAM1_BIST_STATUS 50 +#define LGW_MODEM4_RAM1_BIST_STATUS 51 +#define LGW_MODEM5_RAM1_BIST_STATUS 52 +#define LGW_MODEM6_RAM1_BIST_STATUS 53 +#define LGW_MODEM7_RAM1_BIST_STATUS 54 +#define LGW_MODEM0_RAM2_BIST_STATUS 55 +#define LGW_MODEM1_RAM2_BIST_STATUS 56 +#define LGW_MODEM2_RAM2_BIST_STATUS 57 +#define LGW_MODEM3_RAM2_BIST_STATUS 58 +#define LGW_MODEM4_RAM2_BIST_STATUS 59 +#define LGW_MODEM5_RAM2_BIST_STATUS 60 +#define LGW_MODEM6_RAM2_BIST_STATUS 61 +#define LGW_MODEM7_RAM2_BIST_STATUS 62 +#define LGW_MODEM_MBWSSF_RAM0_BIST_STATUS 63 +#define LGW_MODEM_MBWSSF_RAM1_BIST_STATUS 64 +#define LGW_MODEM_MBWSSF_RAM2_BIST_STATUS 65 +#define LGW_MCU_AGC_DATA_RAM_BIST0_STATUS 66 +#define LGW_MCU_AGC_DATA_RAM_BIST1_STATUS 67 +#define LGW_MCU_ARB_DATA_RAM_BIST0_STATUS 68 +#define LGW_MCU_ARB_DATA_RAM_BIST1_STATUS 69 +#define LGW_TX_TOP_RAM_BIST0_STATUS 70 +#define LGW_TX_TOP_RAM_BIST1_STATUS 71 +#define LGW_DATA_MNGT_RAM_BIST0_STATUS 72 +#define LGW_DATA_MNGT_RAM_BIST1_STATUS 73 +#define LGW_GPIO_SELECT 74 +#define LGW_GPIO_MUX 75 +#define LGW_EMERGENCY_FORCE_HOST_CTRL 76 +#define LGW_RX_INVERT_IQ 77 +#define LGW_MODEM_INVERT_IQ 78 +#define LGW_MBWSSF_MODEM_INVERT_IQ 79 +#define LGW_RX_EDGE_SELECT 80 +#define LGW_MISC_RADIO_EN 81 +#define LGW_FILTER_GAIN 82 +#define LGW_RADIO_SELECT 83 +#define LGW_IF_FREQ_0 84 +#define LGW_IF_FREQ_1 85 +#define LGW_IF_FREQ_2 86 +#define LGW_IF_FREQ_3 87 +#define LGW_IF_FREQ_4 88 +#define LGW_IF_FREQ_5 89 +#define LGW_IF_FREQ_6 90 +#define LGW_IF_FREQ_7 91 +#define LGW_IF_FREQ_8 92 +#define LGW_IF_FREQ_9 93 +#define LGW_CHANN_OVERRIDE_AGC_GAIN 94 +#define LGW_CHANN_AGC_GAIN 95 +#define LGW_CORR0_DETECT_EN 96 +#define LGW_CORR1_DETECT_EN 97 +#define LGW_CORR2_DETECT_EN 98 +#define LGW_CORR3_DETECT_EN 99 +#define LGW_CORR4_DETECT_EN 100 +#define LGW_CORR5_DETECT_EN 101 +#define LGW_CORR6_DETECT_EN 102 +#define LGW_CORR7_DETECT_EN 103 +#define LGW_CORR_SAME_PEAKS_OPTION_SF6 104 +#define LGW_CORR_SAME_PEAKS_OPTION_SF7 105 +#define LGW_CORR_SAME_PEAKS_OPTION_SF8 106 +#define LGW_CORR_SAME_PEAKS_OPTION_SF9 107 +#define LGW_CORR_SAME_PEAKS_OPTION_SF10 108 +#define LGW_CORR_SAME_PEAKS_OPTION_SF11 109 +#define LGW_CORR_SAME_PEAKS_OPTION_SF12 110 +#define LGW_CORR_SIG_NOISE_RATIO_SF6 111 +#define LGW_CORR_SIG_NOISE_RATIO_SF7 112 +#define LGW_CORR_SIG_NOISE_RATIO_SF8 113 +#define LGW_CORR_SIG_NOISE_RATIO_SF9 114 +#define LGW_CORR_SIG_NOISE_RATIO_SF10 115 +#define LGW_CORR_SIG_NOISE_RATIO_SF11 116 +#define LGW_CORR_SIG_NOISE_RATIO_SF12 117 +#define LGW_CORR_NUM_SAME_PEAK 118 +#define LGW_CORR_MAC_GAIN 119 +#define LGW_ADJUST_MODEM_START_OFFSET_RDX8 120 +#define LGW_ADJUST_MODEM_START_OFFSET_RDX4 121 +#define LGW_ADJUST_MODEM_START_OFFSET_SF12_RDX4 122 +#define LGW_DBG_CORR_SELECT_SF 123 +#define LGW_DBG_CORR_SELECT_CHANNEL 124 +#define LGW_DBG_DETECT_CPT 125 +#define LGW_DBG_SYMB_CPT 126 +#define LGW_CHIRP_INVERT_RX 127 +#define LGW_DC_NOTCH_EN 128 +#define LGW_IMPLICIT_CRC_EN 129 +#define LGW_IMPLICIT_CODING_RATE 130 +#define LGW_IMPLICIT_PAYLOAD_LENGHT 131 +#define LGW_FREQ_TO_TIME_INVERT 132 +#define LGW_FREQ_TO_TIME_DRIFT 133 +#define LGW_PAYLOAD_FINE_TIMING_GAIN 134 +#define LGW_PREAMBLE_FINE_TIMING_GAIN 135 +#define LGW_TRACKING_INTEGRAL 136 +#define LGW_FRAME_SYNCH_PEAK1_POS 137 +#define LGW_FRAME_SYNCH_PEAK2_POS 138 +#define LGW_PREAMBLE_SYMB1_NB 139 +#define LGW_FRAME_SYNCH_GAIN 140 +#define LGW_SYNCH_DETECT_TH 141 +#define LGW_LLR_SCALE 142 +#define LGW_SNR_AVG_CST 143 +#define LGW_PPM_OFFSET 144 +#define LGW_MAX_PAYLOAD_LEN 145 +#define LGW_ONLY_CRC_EN 146 +#define LGW_ZERO_PAD 147 +#define LGW_DEC_GAIN_OFFSET 148 +#define LGW_FORCE_HOST_REG_CTRL 149 +#define LGW_FORCE_HOST_RADIO_CTRL 150 +#define LGW_FORCE_HOST_FE_CTRL 151 +#define LGW_FORCE_DEC_FILTER_GAIN 152 +#define LGW_MCU_RST_0 153 +#define LGW_MCU_RST_1 154 +#define LGW_MCU_SELECT_MUX_0 155 +#define LGW_MCU_SELECT_MUX_1 156 +#define LGW_MCU_CORRUPTION_DETECTED_0 157 +#define LGW_MCU_CORRUPTION_DETECTED_1 158 +#define LGW_CHANN_SELECT_RSSI 159 +#define LGW_RSSI_BB_DEFAULT_VALUE 160 +#define LGW_RSSI_DEC_DEFAULT_VALUE 161 +#define LGW_RSSI_CHANN_DEFAULT_VALUE 162 +#define LGW_RSSI_BB_FILTER_ALPHA 163 +#define LGW_RSSI_DEC_FILTER_ALPHA 164 +#define LGW_RSSI_CHANN_FILTER_ALPHA 165 +#define LGW_IQ_MISMATCH_A_AMP_COEFF 166 +#define LGW_IQ_MISMATCH_A_PHI_COEFF 167 +#define LGW_IQ_MISMATCH_B_AMP_COEFF 168 +#define LGW_IQ_MISMATCH_B_SEL_I 169 +#define LGW_IQ_MISMATCH_B_PHI_COEFF 170 +#define LGW_TX_TRIG_IMMEDIATE 171 +#define LGW_TX_TRIG_DELAYED 172 +#define LGW_TX_TRIG_GPS 173 +#define LGW_TX_START_DELAY 174 +#define LGW_TX_FRAME_SYNCH_PEAK1_POS 175 +#define LGW_TX_FRAME_SYNCH_PEAK2_POS 176 +#define LGW_TX_PREAMBLE_SYMB1_NB 177 +#define LGW_TX_OFFSET_I 178 +#define LGW_TX_OFFSET_Q 179 +#define LGW_TX_MODE 180 +#define LGW_TX_ZERO_PAD 181 +#define LGW_TX_PPM_OFFSET 182 +#define LGW_TX_CHIRP_INVERT 183 +#define LGW_TX_CONT_CHIRP 184 +#define LGW_TX_GAIN 185 +#define LGW_TX_CHIRP_LOW_PASS 186 +#define LGW_TX_FCC_WIDEBAND 187 +#define LGW_TX_SWAP_IQ 188 +#define LGW_MBWSSF_IMPLICIT_HEADER 189 +#define LGW_MBWSSF_IMPLICIT_CRC_EN 190 +#define LGW_MBWSSF_IMPLICIT_CODING_RATE 191 +#define LGW_MBWSSF_IMPLICIT_PAYLOAD_LENGHT 192 +#define LGW_MBWSSF_AGC_FREEZE_ON_DETECT 193 +#define LGW_MBWSSF_FRAME_SYNCH_PEAK1_POS 194 +#define LGW_MBWSSF_FRAME_SYNCH_PEAK2_POS 195 +#define LGW_MBWSSF_PREAMBLE_SYMB1_NB 196 +#define LGW_MBWSSF_FRAME_SYNCH_GAIN 197 +#define LGW_MBWSSF_SYNCH_DETECT_TH 198 +#define LGW_MBWSSF_DETECT_MIN_SINGLE_PEAK 199 +#define LGW_MBWSSF_DETECT_TRIG_SAME_PEAK_NB 200 +#define LGW_MBWSSF_FREQ_TO_TIME_INVERT 201 +#define LGW_MBWSSF_FREQ_TO_TIME_DRIFT 202 +#define LGW_MBWSSF_PPM_CORRECTION 203 +#define LGW_MBWSSF_PAYLOAD_FINE_TIMING_GAIN 204 +#define LGW_MBWSSF_PREAMBLE_FINE_TIMING_GAIN 205 +#define LGW_MBWSSF_TRACKING_INTEGRAL 206 +#define LGW_MBWSSF_ZERO_PAD 207 +#define LGW_MBWSSF_MODEM_BW 208 +#define LGW_MBWSSF_RADIO_SELECT 209 +#define LGW_MBWSSF_RX_CHIRP_INVERT 210 +#define LGW_MBWSSF_LLR_SCALE 211 +#define LGW_MBWSSF_SNR_AVG_CST 212 +#define LGW_MBWSSF_PPM_OFFSET 213 +#define LGW_MBWSSF_RATE_SF 214 +#define LGW_MBWSSF_ONLY_CRC_EN 215 +#define LGW_MBWSSF_MAX_PAYLOAD_LEN 216 +#define LGW_SPI_RADIO_A__DATA 217 +#define LGW_SPI_RADIO_A__DATA_READBACK 218 +#define LGW_SPI_RADIO_A__ADDR 219 +#define LGW_SPI_RADIO_A__CS 220 +#define LGW_SPI_RADIO_B__DATA 221 +#define LGW_SPI_RADIO_B__DATA_READBACK 222 +#define LGW_SPI_RADIO_B__ADDR 223 +#define LGW_SPI_RADIO_B__CS 224 +#define LGW_RADIO_A_EN 225 +#define LGW_RADIO_B_EN 226 +#define LGW_RADIO_RST 227 +#define LGW_LNA_A_EN 228 +#define LGW_PA_A_EN 229 +#define LGW_LNA_B_EN 230 +#define LGW_PA_B_EN 231 +#define LGW_PA_A_GAIN 232 +#define LGW_PA_B_GAIN 233 +#define LGW_LNA_A_CTRL_LUT 234 +#define LGW_PA_A_CTRL_LUT 235 +#define LGW_LNA_B_CTRL_LUT 236 +#define LGW_PA_B_CTRL_LUT 237 +#define LGW_CAPTURE_SOURCE 238 +#define LGW_CAPTURE_START 239 +#define LGW_CAPTURE_FORCE_TRIGGER 240 +#define LGW_CAPTURE_WRAP 241 +#define LGW_CAPTURE_PERIOD 242 +#define LGW_LED_REG 243 +#define LGW_MODEM_STATUS 244 +#define LGW_VALID_HEADER_COUNTER_0 245 +#define LGW_VALID_HEADER_COUNTER_1 246 +#define LGW_VALID_PACKET_COUNTER_0 247 +#define LGW_VALID_PACKET_COUNTER_1 248 +#define LGW_VALID_HEADER_COUNTER_MBWSSF 249 +#define LGW_VALID_HEADER_COUNTER_FSK 250 +#define LGW_VALID_PACKET_COUNTER_MBWSSF 251 +#define LGW_VALID_PACKET_COUNTER_FSK 252 +#define LGW_CHANN_RSSI 253 +#define LGW_BB_RSSI 254 +#define LGW_DEC_RSSI 255 +#define LGW_DBG_MCU_DATA 256 +#define LGW_DBG_ARB_MCU_RAM_DATA 257 +#define LGW_DBG_AGC_MCU_RAM_DATA 258 +#define LGW_NEXT_PACKET_CNT 259 +#define LGW_ADDR_CAPTURE_COUNT 260 +#define LGW_TIMESTAMP 261 +#define LGW_DBG_CHANN0_GAIN 262 +#define LGW_DBG_CHANN1_GAIN 263 +#define LGW_DBG_CHANN2_GAIN 264 +#define LGW_DBG_CHANN3_GAIN 265 +#define LGW_DBG_CHANN4_GAIN 266 +#define LGW_DBG_CHANN5_GAIN 267 +#define LGW_DBG_CHANN6_GAIN 268 +#define LGW_DBG_CHANN7_GAIN 269 +#define LGW_DBG_DEC_FILT_GAIN 270 +#define LGW_SPI_DATA_FIFO_PTR 271 +#define LGW_PACKET_DATA_FIFO_PTR 272 +#define LGW_DBG_ARB_MCU_RAM_ADDR 273 +#define LGW_DBG_AGC_MCU_RAM_ADDR 274 +#define LGW_SPI_MASTER_CHIP_SELECT_POLARITY 275 +#define LGW_SPI_MASTER_CPOL 276 +#define LGW_SPI_MASTER_CPHA 277 +#define LGW_SIG_GEN_ANALYSER_MUX_SEL 278 +#define LGW_SIG_GEN_EN 279 +#define LGW_SIG_ANALYSER_EN 280 +#define LGW_SIG_ANALYSER_AVG_LEN 281 +#define LGW_SIG_ANALYSER_PRECISION 282 +#define LGW_SIG_ANALYSER_VALID_OUT 283 +#define LGW_SIG_GEN_FREQ 284 +#define LGW_SIG_ANALYSER_FREQ 285 +#define LGW_SIG_ANALYSER_I_OUT 286 +#define LGW_SIG_ANALYSER_Q_OUT 287 +#define LGW_GPS_EN 288 +#define LGW_GPS_POL 289 + +#define LGW_TOTALREGS 290 + +/* -------------------------------------------------------------------------- */ +/* --- PUBLIC FUNCTIONS PROTOTYPES ------------------------------------------ */ + +/** +@brief Connect Lora gateway by opening SPI link +@return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) +*/ +int lgw_connect(void); + +/** +@brief Disconnect Lora gateway by closing SPI link +@return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) +*/ +int lgw_disconnect(void); + +/** +@brief Use the soft-reset register to put the gateway in initial state +@return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) +*/ +int lgw_soft_reset(void); + +/** +@brief Check if the registers are ok, send diagnostics to stdio/stderr/file +@param f file descriptor to to which the check result will be written +@return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) +*/ +int lgw_reg_check(FILE *f); + +/** +@brief Lora gateway register write +@param register_id register number in the data structure describing registers +@param reg_value signed value to write to the register (for u32, use cast) +@return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) +*/ +int lgw_reg_w(uint16_t register_id, int32_t reg_value); + +/** +@brief Lora gateway register read +@param register_id register number in the data structure describing registers +@param reg_value pointer to a variable where to write register read value +@return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) +*/ +int lgw_reg_r(uint16_t register_id, int32_t *reg_value); + +/** +@brief Lora gateway register burst write +@param register_id register number in the data structure describing registers +@param data pointer to byte array that will be sent to the Lora gateway +@param size size of the transfer, in byte(s) +@return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) +*/ +int lgw_reg_wb(uint16_t register_id, uint8_t *data, uint16_t size); + +/** +@brief Lora gateway register burst read +@param register_id register number in the data structure describing registers +@param data pointer to byte array that will be written from the Lora gateway +@param size size of the transfer, in byte(s) +@return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) +*/ +int lgw_reg_rb(uint16_t register_id, uint8_t *data, uint16_t size); + + +#endif + +/* --- EOF ------------------------------------------------------------------ */ diff --git a/loragw_hal/inc/loragw_spi.h b/loragw_hal/inc/loragw_spi.h new file mode 100644 index 0000000..62cdeb4 --- /dev/null +++ b/loragw_hal/inc/loragw_spi.h @@ -0,0 +1,92 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + ©2013 Semtech-Cycleo + +Description: + Host specific functions to address the LoRa™ gateway registers through a + SPI interface. + Single-byte read/write and burst read/write. + Does not handle pagination. + Could be used with multiple SPI ports in parallel (explicit file descriptor) +*/ + + +#ifndef _LORAGW_SPI_H +#define _LORAGW_SPI_H + +/* -------------------------------------------------------------------------- */ +/* --- DEPENDANCIES --------------------------------------------------------- */ + +#include <stdint.h> /* C99 types*/ + +/* -------------------------------------------------------------------------- */ +/* --- PUBLIC CONSTANTS ----------------------------------------------------- */ + +#define LGW_SPI_SUCCESS 0 +#define LGW_SPI_ERROR -1 +#define LGW_BURST_CHUNK 1024 + +/* -------------------------------------------------------------------------- */ +/* --- PUBLIC FUNCTIONS PROTOTYPES ------------------------------------------ */ + +/** +@brief Lora gateway SPI setup (configure I/O and peripherals) +@param spi_device pointer to SPI file descriptor to be written +@return status of register operation (LGW_SPI_SUCCESS/LGW_SPI_ERROR) +*/ + +int lgw_spi_open(int *spi_device); + +/** +@brief Lora gateway SPI close +@param spi_device SPI file descriptor of the port to close +@return status of register operation (LGW_SPI_SUCCESS/LGW_SPI_ERROR) +*/ + +int lgw_spi_close(int spi_device); + +/** +@brief Lora gateway SPI single-byte write +@param spi_device SPI file descriptor of the target port +@param address 7-bit register address +@param data data byte to write +@return status of register operation (LGW_SPI_SUCCESS/LGW_SPI_ERROR) +*/ +int lgw_spi_w(int spi_device, uint8_t address, uint8_t data); + +/** +@brief Lora gateway SPI single-byte read +@param spi_device SPI file descriptor of the target port +@param address 7-bit register address +@param data data byte to write +@return status of register operation (LGW_SPI_SUCCESS/LGW_SPI_ERROR) +*/ +int lgw_spi_r(int spi_device, uint8_t address, uint8_t *data); + +/** +@brief Lora gateway SPI burst (multiple-byte) write +@param spi_device SPI file descriptor of the target port +@param address 7-bit register address +@param data pointer to byte array that will be sent to the Lora gateway +@param size size of the transfer, in byte(s) +@return status of register operation (LGW_SPI_SUCCESS/LGW_SPI_ERROR) +*/ +int lgw_spi_wb(int spi_device, uint8_t address, uint8_t *data, uint16_t size); + +/** +@brief Lora gateway SPI burst (multiple-byte) read +@param spi_device SPI file descriptor of the target port +@param address 7-bit register address +@param data pointer to byte array that will be written from the Lora gateway +@param size size of the transfer, in byte(s) +@return status of register operation (LGW_SPI_SUCCESS/LGW_SPI_ERROR) +*/ +int lgw_spi_rb(int spi_device, uint8_t address, uint8_t *data, uint16_t size); + +#endif + +/* --- EOF ------------------------------------------------------------------ */ |