summaryrefslogtreecommitdiff
path: root/libloragw
diff options
context:
space:
mode:
Diffstat (limited to 'libloragw')
-rw-r--r--libloragw/VERSION4
-rw-r--r--libloragw/doc/CHANGELOG.TXT7
-rw-r--r--libloragw/library.cfg8
-rw-r--r--libloragw/src/loragw_hal.c15
4 files changed, 24 insertions, 10 deletions
diff --git a/libloragw/VERSION b/libloragw/VERSION
index eafdd0f..94fa4e6 100644
--- a/libloragw/VERSION
+++ b/libloragw/VERSION
@@ -1,8 +1,8 @@
/* Software library version: */
-#define VERSION_LIBRARY "beta8"
+#define VERSION_LIBRARY "1.0.0"
/* API version */
-#define VERSION_API "beta"
+#define VERSION_API "1.0"
/* Accepted value of CHIP_ID (SPI registers) must match reg default value in loragw_reg.c */
#define ACCEPT_CHIP_ID "1"
diff --git a/libloragw/doc/CHANGELOG.TXT b/libloragw/doc/CHANGELOG.TXT
index f1d4a64..ba5866e 100644
--- a/libloragw/doc/CHANGELOG.TXT
+++ b/libloragw/doc/CHANGELOG.TXT
@@ -1,6 +1,13 @@
Lora Gateway HAL changelog
==========================
+ v1.0.0 (from beta 8)
+---------------------
+
+ * switched FTDI as default SPI phy layer in library.cfg
+ * fixed a bug in TX power control; still only two TW power available, 14 and 24 dBm
+ * changed library directory name from loragw_hal to libloragw to follow usual conventions
+
Beta 8 (from beta 7)
---------------------
diff --git a/libloragw/library.cfg b/libloragw/library.cfg
index ac24416..8e3ba0e 100644
--- a/libloragw/library.cfg
+++ b/libloragw/library.cfg
@@ -19,8 +19,8 @@ FLAG_HAL= -D DEBUG_HAL=0
# The flags bellow define which physical link to the nano board will be used
# Pick one and comment the other(s)
-# Pcduino native SPI (Linux device in /dev)
-LGW_PHY= native
-
# FTDI SPI-over-USB bridge
-#LGW_PHY= ftdi
+LGW_PHY= ftdi
+
+# Pcduino native SPI (Linux device in /dev)
+#LGW_PHY= native
diff --git a/libloragw/src/loragw_hal.c b/libloragw/src/loragw_hal.c
index 930f13e..881abd4 100644
--- a/libloragw/src/loragw_hal.c
+++ b/libloragw/src/loragw_hal.c
@@ -886,6 +886,7 @@ int lgw_send(struct lgw_pkt_tx_s pkt_data) {
uint16_t fsk_dr_div; /* divider to configure for target datarate */
int transfer_size = 0; /* data to transfer from host to TX databuffer */
int payload_offset = 0; /* start of the payload content in the databuffer */
+ uint8_t power_nibble = 0; /* 4-bit value to set the firmware TX power */
/* check if the gateway is running */
if (lgw_is_started == false) {
@@ -948,6 +949,14 @@ int lgw_send(struct lgw_pkt_tx_s pkt_data) {
return LGW_HAL_ERROR;
}
+ /* interpretation of TX power */
+ if (pkt_data.rf_power < 24) {
+ power_nibble = 0x0; /* ~15.5 dBm, so 14 after cavity filter + cables */
+ } else {
+ power_nibble = 0xF; /* maximum power ~25.5 dBm, 24 after filter */
+ }
+ // TODO: implement LUT in the firmware and matched value in the HAL
+
/* reset TX command flags */
lgw_reg_w(LGW_TX_TRIG_IMMEDIATE, 0);
lgw_reg_w(LGW_TX_TRIG_DELAYED, 0);
@@ -973,8 +982,7 @@ int lgw_send(struct lgw_pkt_tx_s pkt_data) {
/* parameters depending on modulation */
if (pkt_data.modulation == MOD_LORA) {
/* metadata 7, modulation type, radio chain selection and TX power */
- buff[7] = (0x20 & (pkt_data.rf_chain << 5)) | (0x0F & pkt_data.rf_power); /* bit 4 is 0 -> Lora modulation */
- /* fine control over TX power not supported yet, any value other than 8 is 14 dBm */
+ buff[7] = (0x20 & (pkt_data.rf_chain << 5)) | (0x0F & power_nibble); /* bit 4 is 0 -> Lora modulation */
buff[8] = 0; /* metadata 8, not used */
@@ -1033,8 +1041,7 @@ int lgw_send(struct lgw_pkt_tx_s pkt_data) {
} else if (pkt_data.modulation == MOD_FSK) {
/* metadata 7, modulation type, radio chain selection and TX power */
- buff[7] = (0x20 & (pkt_data.rf_chain << 5)) | 0x10 | (0x0F & pkt_data.rf_power); /* bit 4 is 1 -> FSK modulation */
- /* fine control over TX power not supported yet, any value other than 8 is 14 dBm */
+ buff[7] = (0x20 & (pkt_data.rf_chain << 5)) | 0x10 | (0x0F & power_nibble); /* bit 4 is 1 -> FSK modulation */
buff[8] = 0; /* metadata 8, not used */