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authorJesse Gilles <jgilles@multitech.com>2015-04-06 17:29:55 -0500
committerJesse Gilles <jgilles@multitech.com>2015-04-06 17:29:55 -0500
commitd6e01b5a566c08c89f17ae4a26d4ef003e39167c (patch)
treeabd7d2a69389768b8e359b0d546a9f39397d1c18 /libloragw/src/loragw_hal.c
parent061f14802f86bdb41fe7dd0161461f8b8fa054cf (diff)
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add MTAC-LORA board support
Diffstat (limited to 'libloragw/src/loragw_hal.c')
-rw-r--r--libloragw/src/loragw_hal.c37
1 files changed, 37 insertions, 0 deletions
diff --git a/libloragw/src/loragw_hal.c b/libloragw/src/loragw_hal.c
index 5dbdf45..ecde9d9 100644
--- a/libloragw/src/loragw_hal.c
+++ b/libloragw/src/loragw_hal.c
@@ -128,6 +128,8 @@ F_register(24bit) = F_rf (Hz) / F_step(Hz)
*/
#elif (CFG_BRD_NONE == 1)
#define RSSI_BOARD_OFFSET 0
+#elif (CFG_BRD_MTACLORA == 1)
+ #define RSSI_BOARD_OFFSET 166.0 /* Calibrated 2015-02-23 */
#endif
/* constant arrays defining hardware capability */
@@ -361,6 +363,26 @@ typedef struct {
{ 3, 3, 13, 14},\
{ 3, 3, 15, 15},\
}; // uncalibrated table, lgw_pkt_tx_s.rf_power selects table index */
+#elif (CFG_BRD_MTACLORA == 1)
+ #define CUSTOM_TX_POW_TABLE 1
+ const tx_pow_t tx_pow_table[TX_POW_LUT_SIZE] = {\
+ { 0, 3, 8, -6},\
+ { 0, 3, 10, -3},\
+ { 0, 3, 12, 0},\
+ { 1, 3, 8, 3},\
+ { 1, 3, 10, 6},\
+ { 1, 3, 12, 10},\
+ { 1, 3, 13, 11},\
+ { 2, 3, 9, 12},\
+ { 1, 3, 15, 13},\
+ { 2, 3, 10, 14},\
+ { 2, 3, 11, 16},\
+ { 3, 3, 10, 20},\
+ { 3, 3, 11, 23},\
+ { 3, 3, 12, 24},\
+ { 3, 3, 13, 25},\
+ { 3, 3, 15, 26},\
+ }; /* Calibrated 2015-02-23 */
#endif
/* Strings for version (and options) identification */
@@ -426,6 +448,8 @@ typedef struct {
*/
#elif (CFG_BRD_NONE == 1)
#define CFG_BRD_STR "no_brd"
+#elif (CFG_BRD_MTACLORA == 1)
+ #define CFG_BRD_STR "mtac-lora"
#else
#define CFG_BRD_STR "brd?"
#endif
@@ -1063,6 +1087,9 @@ int lgw_start(void) {
#elif (CFG_BRD_NANO868 == 1)
cal_cmd |= 0x40; /* Bit 6-7: Board type 0: ref, 1: FPGA, 3: board X */
cal_time = 5200; /* measured between 5.0 and 5.1 sec */
+ #elif (CFG_BRD_MTACLORA == 1)
+ cal_cmd |= 0x00;
+ cal_time = 3000; /* Recommended by Semtech 2015-02-23 */
#else
cal_cmd |= 0xC0; /* Bit 6-7: Board type 0: ref, 1: FPGA, 3: board X */
cal_time = 4200; /* measured between 4.0 and 4.1 sec */
@@ -1581,6 +1608,15 @@ int lgw_send(struct lgw_pkt_tx_s pkt_data) {
DEBUG_MSG("ERROR: SELECTED RF_CHAIN IS DISABLED\n");
return LGW_HAL_ERROR;
}
+/* MTAC-LORA build will suport both bands so check Tx freq differently */
+#if (CFG_BRD_MTACLORA == 1)
+ /* if Tx freq is not in the EU nor the US bands */
+ if ( ! ((pkt_data.freq_hz >= LGW_EU868_FREQ_MIN && pkt_data.freq_hz <= LGW_EU868_FREQ_MAX) ||
+ (pkt_data.freq_hz >= LGW_US915_FREQ_MIN && pkt_data.freq_hz <= LGW_US915_FREQ_MAX)) ) {
+ DEBUG_PRINTF("ERROR: FREQUENCY %d IS OUTSIDE ALLOWED BANDS\n", pkt_data.freq_hz);
+ return LGW_HAL_ERROR;
+ }
+#else
if (pkt_data.freq_hz > rf_tx_upfreq[pkt_data.rf_chain]) {
DEBUG_PRINTF("ERROR: FREQUENCY %d HIGHER THAN UPPER LIMIT %d OF RF_CHAIN %d\n", pkt_data.freq_hz, rf_tx_upfreq[pkt_data.rf_chain], pkt_data.rf_chain);
return LGW_HAL_ERROR;
@@ -1588,6 +1624,7 @@ int lgw_send(struct lgw_pkt_tx_s pkt_data) {
DEBUG_PRINTF("ERROR: FREQUENCY %d LOWER THAN LOWER LIMIT %d OF RF_CHAIN %d\n", pkt_data.freq_hz, rf_tx_lowfreq[pkt_data.rf_chain], pkt_data.rf_chain);
return LGW_HAL_ERROR;
}
+#endif
if (!IS_TX_MODE(pkt_data.tx_mode)) {
DEBUG_MSG("ERROR: TX_MODE NOT SUPPORTED\n");
return LGW_HAL_ERROR;