diff options
| author | Sylvain Miermont <smiermont@semtech.com> | 2013-09-03 14:38:31 +0200 |
|---|---|---|
| committer | Sylvain Miermont <smiermont@semtech.com> | 2013-10-23 13:36:30 +0200 |
| commit | 68b8b7a70d9104888997174506fbbaa0abb12a4c (patch) | |
| tree | 6ccdfb8ba0c62e183639574cbb2116b651a054f9 | |
| parent | 33ade9eb698f594e95076a5e4056a70163f14278 (diff) | |
| download | lora_gateway-1.b5.tar.gz lora_gateway-1.b5.tar.bz2 lora_gateway-1.b5.zip | |
Beta 5v1.b5
- updated firmwares and registers to new IP revision (VERSION = 103, bistream r986)
- recalibrated RSSI
- updated registers configuration
- updated size for firmware code memory
- changed TX status code symbols
| -rw-r--r-- | loragw_hal/inc/loragw_hal.h | 4 | ||||
| -rw-r--r-- | loragw_hal/inc/loragw_reg.h | 587 | ||||
| -rw-r--r-- | loragw_hal/src/agc_fw.var | 422 | ||||
| -rw-r--r-- | loragw_hal/src/arb_fw.var | 518 | ||||
| -rw-r--r-- | loragw_hal/src/loragw_hal.c | 90 | ||||
| -rw-r--r-- | loragw_hal/src/loragw_reg.c | 61 | ||||
| -rw-r--r-- | loragw_hal/test/test_loragw_hal.c | 2 |
7 files changed, 1067 insertions, 617 deletions
diff --git a/loragw_hal/inc/loragw_hal.h b/loragw_hal/inc/loragw_hal.h index bc28741..d5daafd 100644 --- a/loragw_hal/inc/loragw_hal.h +++ b/loragw_hal/inc/loragw_hal.h @@ -133,8 +133,8 @@ F_register(24bit) = F_rf (Hz) / F_step(Hz) /* status code for TX_STATUS */ #define TX_STATUS_UNKNOWN 0 #define TX_OFF 1 /* TX modem disabled, it will ignore commands */ -#define TX_EMPTY 2 /* TX modem is free, ready to receive a command */ -#define TX_DELAYED 3 /* TX modem is loaded, ready to send the packet after an event and/or delay */ +#define TX_FREE 2 /* TX modem is free, ready to receive a command */ +#define TX_SCHEDULED 3 /* TX modem is loaded, ready to send the packet after an event and/or delay */ #define TX_EMITTING 4 /* TX modem is emitting */ /* status code for RX_STATUS */ diff --git a/loragw_hal/inc/loragw_reg.h b/loragw_hal/inc/loragw_reg.h index 1fc8d9b..870780f 100644 --- a/loragw_hal/inc/loragw_reg.h +++ b/loragw_hal/inc/loragw_reg.h @@ -54,286 +54,315 @@ this file is autogenerated from registers description #define LGW_MBWSSF_MODEM_ENABLE 15 #define LGW_CONCENTRATOR_MODEM_ENABLE 16 #define LGW_FSK_MODEM_ENABLE 17 -#define LGW_CLK32M_EN 18 -#define LGW_CLKHS_EN 19 -#define LGW_START_BIST0 20 -#define LGW_START_BIST1 21 -#define LGW_CLEAR_BIST0 22 -#define LGW_CLEAR_BIST1 23 -#define LGW_BIST0_FINISHED 24 -#define LGW_BIST1_FINISHED 25 -#define LGW_MCU_AGC_PROG_RAM_BIST_STATUS 26 -#define LGW_MCU_ARB_PROG_RAM_BIST_STATUS 27 -#define LGW_CAPTURE_RAM_BIST_STATUS 28 -#define LGW_CHAN_FIR_RAM0_BIST_STATUS 29 -#define LGW_CHAN_FIR_RAM1_BIST_STATUS 30 -#define LGW_CORR0_RAM_BIST_STATUS 31 -#define LGW_CORR1_RAM_BIST_STATUS 32 -#define LGW_CORR2_RAM_BIST_STATUS 33 -#define LGW_CORR3_RAM_BIST_STATUS 34 -#define LGW_CORR4_RAM_BIST_STATUS 35 -#define LGW_CORR5_RAM_BIST_STATUS 36 -#define LGW_CORR6_RAM_BIST_STATUS 37 -#define LGW_CORR7_RAM_BIST_STATUS 38 -#define LGW_MODEM0_RAM0_BIST_STATUS 39 -#define LGW_MODEM1_RAM0_BIST_STATUS 40 -#define LGW_MODEM2_RAM0_BIST_STATUS 41 -#define LGW_MODEM3_RAM0_BIST_STATUS 42 -#define LGW_MODEM4_RAM0_BIST_STATUS 43 -#define LGW_MODEM5_RAM0_BIST_STATUS 44 -#define LGW_MODEM6_RAM0_BIST_STATUS 45 -#define LGW_MODEM7_RAM0_BIST_STATUS 46 -#define LGW_MODEM0_RAM1_BIST_STATUS 47 -#define LGW_MODEM1_RAM1_BIST_STATUS 48 -#define LGW_MODEM2_RAM1_BIST_STATUS 49 -#define LGW_MODEM3_RAM1_BIST_STATUS 50 -#define LGW_MODEM4_RAM1_BIST_STATUS 51 -#define LGW_MODEM5_RAM1_BIST_STATUS 52 -#define LGW_MODEM6_RAM1_BIST_STATUS 53 -#define LGW_MODEM7_RAM1_BIST_STATUS 54 -#define LGW_MODEM0_RAM2_BIST_STATUS 55 -#define LGW_MODEM1_RAM2_BIST_STATUS 56 -#define LGW_MODEM2_RAM2_BIST_STATUS 57 -#define LGW_MODEM3_RAM2_BIST_STATUS 58 -#define LGW_MODEM4_RAM2_BIST_STATUS 59 -#define LGW_MODEM5_RAM2_BIST_STATUS 60 -#define LGW_MODEM6_RAM2_BIST_STATUS 61 -#define LGW_MODEM7_RAM2_BIST_STATUS 62 -#define LGW_MODEM_MBWSSF_RAM0_BIST_STATUS 63 -#define LGW_MODEM_MBWSSF_RAM1_BIST_STATUS 64 -#define LGW_MODEM_MBWSSF_RAM2_BIST_STATUS 65 -#define LGW_MCU_AGC_DATA_RAM_BIST0_STATUS 66 -#define LGW_MCU_AGC_DATA_RAM_BIST1_STATUS 67 -#define LGW_MCU_ARB_DATA_RAM_BIST0_STATUS 68 -#define LGW_MCU_ARB_DATA_RAM_BIST1_STATUS 69 -#define LGW_TX_TOP_RAM_BIST0_STATUS 70 -#define LGW_TX_TOP_RAM_BIST1_STATUS 71 -#define LGW_DATA_MNGT_RAM_BIST0_STATUS 72 -#define LGW_DATA_MNGT_RAM_BIST1_STATUS 73 -#define LGW_GPIO_SELECT_INPUT 74 -#define LGW_GPIO_SELECT_OUTPUT 75 -#define LGW_GPIO_MODE 76 -#define LGW_GPIO_PIN_REG_IN 77 -#define LGW_GPIO_PIN_REG_OUT 78 -#define LGW_MCU_AGC_STATUS 79 -#define LGW_CHIP_ID 80 -#define LGW_EMERGENCY_FORCE_HOST_CTRL 81 -#define LGW_RX_INVERT_IQ 82 -#define LGW_MODEM_INVERT_IQ 83 -#define LGW_MBWSSF_MODEM_INVERT_IQ 84 -#define LGW_RX_EDGE_SELECT 85 -#define LGW_MISC_RADIO_EN 86 -#define LGW_FILTER_GAIN 87 -#define LGW_RADIO_SELECT 88 -#define LGW_IF_FREQ_0 89 -#define LGW_IF_FREQ_1 90 -#define LGW_IF_FREQ_2 91 -#define LGW_IF_FREQ_3 92 -#define LGW_IF_FREQ_4 93 -#define LGW_IF_FREQ_5 94 -#define LGW_IF_FREQ_6 95 -#define LGW_IF_FREQ_7 96 -#define LGW_IF_FREQ_8 97 -#define LGW_IF_FREQ_9 98 -#define LGW_CHANN_OVERRIDE_AGC_GAIN 99 -#define LGW_CHANN_AGC_GAIN 100 -#define LGW_CORR0_DETECT_EN 101 -#define LGW_CORR1_DETECT_EN 102 -#define LGW_CORR2_DETECT_EN 103 -#define LGW_CORR3_DETECT_EN 104 -#define LGW_CORR4_DETECT_EN 105 -#define LGW_CORR5_DETECT_EN 106 -#define LGW_CORR6_DETECT_EN 107 -#define LGW_CORR7_DETECT_EN 108 -#define LGW_CORR_SAME_PEAKS_OPTION_SF6 109 -#define LGW_CORR_SAME_PEAKS_OPTION_SF7 110 -#define LGW_CORR_SAME_PEAKS_OPTION_SF8 111 -#define LGW_CORR_SAME_PEAKS_OPTION_SF9 112 -#define LGW_CORR_SAME_PEAKS_OPTION_SF10 113 -#define LGW_CORR_SAME_PEAKS_OPTION_SF11 114 -#define LGW_CORR_SAME_PEAKS_OPTION_SF12 115 -#define LGW_CORR_SIG_NOISE_RATIO_SF6 116 -#define LGW_CORR_SIG_NOISE_RATIO_SF7 117 -#define LGW_CORR_SIG_NOISE_RATIO_SF8 118 -#define LGW_CORR_SIG_NOISE_RATIO_SF9 119 -#define LGW_CORR_SIG_NOISE_RATIO_SF10 120 -#define LGW_CORR_SIG_NOISE_RATIO_SF11 121 -#define LGW_CORR_SIG_NOISE_RATIO_SF12 122 -#define LGW_CORR_NUM_SAME_PEAK 123 -#define LGW_CORR_MAC_GAIN 124 -#define LGW_ADJUST_MODEM_START_OFFSET_RDX8 125 -#define LGW_ADJUST_MODEM_START_OFFSET_RDX4 126 -#define LGW_ADJUST_MODEM_START_OFFSET_SF12_RDX4 127 -#define LGW_DBG_CORR_SELECT_SF 128 -#define LGW_DBG_CORR_SELECT_CHANNEL 129 -#define LGW_DBG_DETECT_CPT 130 -#define LGW_DBG_SYMB_CPT 131 -#define LGW_CHIRP_INVERT_RX 132 -#define LGW_DC_NOTCH_EN 133 -#define LGW_IMPLICIT_CRC_EN 134 -#define LGW_IMPLICIT_CODING_RATE 135 -#define LGW_IMPLICIT_PAYLOAD_LENGHT 136 -#define LGW_FREQ_TO_TIME_INVERT 137 -#define LGW_FREQ_TO_TIME_DRIFT 138 -#define LGW_PAYLOAD_FINE_TIMING_GAIN 139 -#define LGW_PREAMBLE_FINE_TIMING_GAIN 140 -#define LGW_TRACKING_INTEGRAL 141 -#define LGW_FRAME_SYNCH_PEAK1_POS 142 -#define LGW_FRAME_SYNCH_PEAK2_POS 143 -#define LGW_PREAMBLE_SYMB1_NB 144 -#define LGW_FRAME_SYNCH_GAIN 145 -#define LGW_SYNCH_DETECT_TH 146 -#define LGW_LLR_SCALE 147 -#define LGW_SNR_AVG_CST 148 -#define LGW_PPM_OFFSET 149 -#define LGW_MAX_PAYLOAD_LEN 150 -#define LGW_ONLY_CRC_EN 151 -#define LGW_ZERO_PAD 152 -#define LGW_DEC_GAIN_OFFSET 153 -#define LGW_CHAN_GAIN_OFFSET 154 -#define LGW_FORCE_HOST_REG_CTRL 155 -#define LGW_FORCE_HOST_RADIO_CTRL 156 -#define LGW_FORCE_HOST_FE_CTRL 157 -#define LGW_FORCE_DEC_FILTER_GAIN 158 -#define LGW_MCU_RST_0 159 -#define LGW_MCU_RST_1 160 -#define LGW_MCU_SELECT_MUX_0 161 -#define LGW_MCU_SELECT_MUX_1 162 -#define LGW_MCU_CORRUPTION_DETECTED_0 163 -#define LGW_MCU_CORRUPTION_DETECTED_1 164 -#define LGW_MCU_SELECT_EDGE_0 165 -#define LGW_MCU_SELECT_EDGE_1 166 -#define LGW_CHANN_SELECT_RSSI 167 -#define LGW_RSSI_BB_DEFAULT_VALUE 168 -#define LGW_RSSI_DEC_DEFAULT_VALUE 169 -#define LGW_RSSI_CHANN_DEFAULT_VALUE 170 -#define LGW_RSSI_BB_FILTER_ALPHA 171 -#define LGW_RSSI_DEC_FILTER_ALPHA 172 -#define LGW_RSSI_CHANN_FILTER_ALPHA 173 -#define LGW_IQ_MISMATCH_A_AMP_COEFF 174 -#define LGW_IQ_MISMATCH_A_PHI_COEFF 175 -#define LGW_IQ_MISMATCH_B_AMP_COEFF 176 -#define LGW_IQ_MISMATCH_B_SEL_I 177 -#define LGW_IQ_MISMATCH_B_PHI_COEFF 178 -#define LGW_TX_TRIG_IMMEDIATE 179 -#define LGW_TX_TRIG_DELAYED 180 -#define LGW_TX_TRIG_GPS 181 -#define LGW_TX_START_DELAY 182 -#define LGW_TX_FRAME_SYNCH_PEAK1_POS 183 -#define LGW_TX_FRAME_SYNCH_PEAK2_POS 184 -#define LGW_TX_OFFSET_I 185 -#define LGW_TX_OFFSET_Q 186 -#define LGW_TX_MODE 187 -#define LGW_TX_ZERO_PAD 188 -#define LGW_TX_EDGE_SELECT 189 -#define LGW_TX_GAIN 190 -#define LGW_TX_CHIRP_LOW_PASS 191 -#define LGW_TX_FCC_WIDEBAND 192 -#define LGW_TX_SWAP_IQ 193 -#define LGW_MBWSSF_IMPLICIT_HEADER 194 -#define LGW_MBWSSF_IMPLICIT_CRC_EN 195 -#define LGW_MBWSSF_IMPLICIT_CODING_RATE 196 -#define LGW_MBWSSF_IMPLICIT_PAYLOAD_LENGHT 197 -#define LGW_MBWSSF_AGC_FREEZE_ON_DETECT 198 -#define LGW_MBWSSF_FRAME_SYNCH_PEAK1_POS 199 -#define LGW_MBWSSF_FRAME_SYNCH_PEAK2_POS 200 -#define LGW_MBWSSF_PREAMBLE_SYMB1_NB 201 -#define LGW_MBWSSF_FRAME_SYNCH_GAIN 202 -#define LGW_MBWSSF_SYNCH_DETECT_TH 203 -#define LGW_MBWSSF_DETECT_MIN_SINGLE_PEAK 204 -#define LGW_MBWSSF_DETECT_TRIG_SAME_PEAK_NB 205 -#define LGW_MBWSSF_FREQ_TO_TIME_INVERT 206 -#define LGW_MBWSSF_FREQ_TO_TIME_DRIFT 207 -#define LGW_MBWSSF_PPM_CORRECTION 208 -#define LGW_MBWSSF_PAYLOAD_FINE_TIMING_GAIN 209 -#define LGW_MBWSSF_PREAMBLE_FINE_TIMING_GAIN 210 -#define LGW_MBWSSF_TRACKING_INTEGRAL 211 -#define LGW_MBWSSF_ZERO_PAD 212 -#define LGW_MBWSSF_MODEM_BW 213 -#define LGW_MBWSSF_RADIO_SELECT 214 -#define LGW_MBWSSF_RX_CHIRP_INVERT 215 -#define LGW_MBWSSF_LLR_SCALE 216 -#define LGW_MBWSSF_SNR_AVG_CST 217 -#define LGW_MBWSSF_PPM_OFFSET 218 -#define LGW_MBWSSF_RATE_SF 219 -#define LGW_MBWSSF_ONLY_CRC_EN 220 -#define LGW_MBWSSF_MAX_PAYLOAD_LEN 221 -#define LGW_TX_STATUS 222 -#define LGW_SPI_RADIO_A__DATA 223 -#define LGW_SPI_RADIO_A__DATA_READBACK 224 -#define LGW_SPI_RADIO_A__ADDR 225 -#define LGW_SPI_RADIO_A__CS 226 -#define LGW_SPI_RADIO_B__DATA 227 -#define LGW_SPI_RADIO_B__DATA_READBACK 228 -#define LGW_SPI_RADIO_B__ADDR 229 -#define LGW_SPI_RADIO_B__CS 230 -#define LGW_RADIO_A_EN 231 -#define LGW_RADIO_B_EN 232 -#define LGW_RADIO_RST 233 -#define LGW_LNA_A_EN 234 -#define LGW_PA_A_EN 235 -#define LGW_LNA_B_EN 236 -#define LGW_PA_B_EN 237 -#define LGW_PA_GAIN 238 -#define LGW_LNA_A_CTRL_LUT 239 -#define LGW_PA_A_CTRL_LUT 240 -#define LGW_LNA_B_CTRL_LUT 241 -#define LGW_PA_B_CTRL_LUT 242 -#define LGW_CAPTURE_SOURCE 243 -#define LGW_CAPTURE_START 244 -#define LGW_CAPTURE_FORCE_TRIGGER 245 -#define LGW_CAPTURE_WRAP 246 -#define LGW_CAPTURE_PERIOD 247 -#define LGW_LED_REG 248 -#define LGW_MODEM_STATUS 249 -#define LGW_VALID_HEADER_COUNTER_0 250 -#define LGW_VALID_PACKET_COUNTER_0 251 -#define LGW_VALID_HEADER_COUNTER_MBWSSF 252 -#define LGW_VALID_HEADER_COUNTER_FSK 253 -#define LGW_VALID_PACKET_COUNTER_MBWSSF 254 -#define LGW_VALID_PACKET_COUNTER_FSK 255 -#define LGW_CHANN_RSSI 256 -#define LGW_BB_RSSI 257 -#define LGW_DEC_RSSI 258 -#define LGW_DBG_MCU_DATA 259 -#define LGW_DBG_ARB_MCU_RAM_DATA 260 -#define LGW_DBG_AGC_MCU_RAM_DATA 261 -#define LGW_NEXT_PACKET_CNT 262 -#define LGW_ADDR_CAPTURE_COUNT 263 -#define LGW_TIMESTAMP 264 -#define LGW_DBG_CHANN0_GAIN 265 -#define LGW_DBG_CHANN1_GAIN 266 -#define LGW_DBG_CHANN2_GAIN 267 -#define LGW_DBG_CHANN3_GAIN 268 -#define LGW_DBG_CHANN4_GAIN 269 -#define LGW_DBG_CHANN5_GAIN 270 -#define LGW_DBG_CHANN6_GAIN 271 -#define LGW_DBG_CHANN7_GAIN 272 -#define LGW_DBG_DEC_FILT_GAIN 273 -#define LGW_SPI_DATA_FIFO_PTR 274 -#define LGW_PACKET_DATA_FIFO_PTR 275 -#define LGW_DBG_ARB_MCU_RAM_ADDR 276 -#define LGW_DBG_AGC_MCU_RAM_ADDR 277 -#define LGW_SPI_MASTER_CHIP_SELECT_POLARITY 278 -#define LGW_SPI_MASTER_CPOL 279 -#define LGW_SPI_MASTER_CPHA 280 -#define LGW_SIG_GEN_ANALYSER_MUX_SEL 281 -#define LGW_SIG_GEN_EN 282 -#define LGW_SIG_ANALYSER_EN 283 -#define LGW_SIG_ANALYSER_AVG_LEN 284 -#define LGW_SIG_ANALYSER_PRECISION 285 -#define LGW_SIG_ANALYSER_VALID_OUT 286 -#define LGW_SIG_GEN_FREQ 287 -#define LGW_SIG_ANALYSER_FREQ 288 -#define LGW_SIG_ANALYSER_I_OUT 289 -#define LGW_SIG_ANALYSER_Q_OUT 290 -#define LGW_GPS_EN 291 -#define LGW_GPS_POL 292 -#define LGW_SW_TEST_REG1 293 -#define LGW_SW_TEST_REG2 294 -#define LGW_SW_TEST_REG3 295 +#define LGW_GLOBAL_EN 18 +#define LGW_CLK32M_EN 19 +#define LGW_CLKHS_EN 20 +#define LGW_START_BIST0 21 +#define LGW_START_BIST1 22 +#define LGW_CLEAR_BIST0 23 +#define LGW_CLEAR_BIST1 24 +#define LGW_BIST0_FINISHED 25 +#define LGW_BIST1_FINISHED 26 +#define LGW_MCU_AGC_PROG_RAM_BIST_STATUS 27 +#define LGW_MCU_ARB_PROG_RAM_BIST_STATUS 28 +#define LGW_CAPTURE_RAM_BIST_STATUS 29 +#define LGW_CHAN_FIR_RAM0_BIST_STATUS 30 +#define LGW_CHAN_FIR_RAM1_BIST_STATUS 31 +#define LGW_CORR0_RAM_BIST_STATUS 32 +#define LGW_CORR1_RAM_BIST_STATUS 33 +#define LGW_CORR2_RAM_BIST_STATUS 34 +#define LGW_CORR3_RAM_BIST_STATUS 35 +#define LGW_CORR4_RAM_BIST_STATUS 36 +#define LGW_CORR5_RAM_BIST_STATUS 37 +#define LGW_CORR6_RAM_BIST_STATUS 38 +#define LGW_CORR7_RAM_BIST_STATUS 39 +#define LGW_MODEM0_RAM0_BIST_STATUS 40 +#define LGW_MODEM1_RAM0_BIST_STATUS 41 +#define LGW_MODEM2_RAM0_BIST_STATUS 42 +#define LGW_MODEM3_RAM0_BIST_STATUS 43 +#define LGW_MODEM4_RAM0_BIST_STATUS 44 +#define LGW_MODEM5_RAM0_BIST_STATUS 45 +#define LGW_MODEM6_RAM0_BIST_STATUS 46 +#define LGW_MODEM7_RAM0_BIST_STATUS 47 +#define LGW_MODEM0_RAM1_BIST_STATUS 48 +#define LGW_MODEM1_RAM1_BIST_STATUS 49 +#define LGW_MODEM2_RAM1_BIST_STATUS 50 +#define LGW_MODEM3_RAM1_BIST_STATUS 51 +#define LGW_MODEM4_RAM1_BIST_STATUS 52 +#define LGW_MODEM5_RAM1_BIST_STATUS 53 +#define LGW_MODEM6_RAM1_BIST_STATUS 54 +#define LGW_MODEM7_RAM1_BIST_STATUS 55 +#define LGW_MODEM0_RAM2_BIST_STATUS 56 +#define LGW_MODEM1_RAM2_BIST_STATUS 57 +#define LGW_MODEM2_RAM2_BIST_STATUS 58 +#define LGW_MODEM3_RAM2_BIST_STATUS 59 +#define LGW_MODEM4_RAM2_BIST_STATUS 60 +#define LGW_MODEM5_RAM2_BIST_STATUS 61 +#define LGW_MODEM6_RAM2_BIST_STATUS 62 +#define LGW_MODEM7_RAM2_BIST_STATUS 63 +#define LGW_MODEM_MBWSSF_RAM0_BIST_STATUS 64 +#define LGW_MODEM_MBWSSF_RAM1_BIST_STATUS 65 +#define LGW_MODEM_MBWSSF_RAM2_BIST_STATUS 66 +#define LGW_MCU_AGC_DATA_RAM_BIST0_STATUS 67 +#define LGW_MCU_AGC_DATA_RAM_BIST1_STATUS 68 +#define LGW_MCU_ARB_DATA_RAM_BIST0_STATUS 69 +#define LGW_MCU_ARB_DATA_RAM_BIST1_STATUS 70 +#define LGW_TX_TOP_RAM_BIST0_STATUS 71 +#define LGW_TX_TOP_RAM_BIST1_STATUS 72 +#define LGW_DATA_MNGT_RAM_BIST0_STATUS 73 +#define LGW_DATA_MNGT_RAM_BIST1_STATUS 74 +#define LGW_GPIO_SELECT_INPUT 75 +#define LGW_GPIO_SELECT_OUTPUT 76 +#define LGW_GPIO_MODE 77 +#define LGW_GPIO_PIN_REG_IN 78 +#define LGW_GPIO_PIN_REG_OUT 79 +#define LGW_MCU_AGC_STATUS 80 +#define LGW_MCU_ARB_STATUS 81 +#define LGW_CHIP_ID 82 +#define LGW_EMERGENCY_FORCE_HOST_CTRL 83 +#define LGW_RX_INVERT_IQ 84 +#define LGW_MODEM_INVERT_IQ 85 +#define LGW_MBWSSF_MODEM_INVERT_IQ 86 +#define LGW_RX_EDGE_SELECT 87 +#define LGW_MISC_RADIO_EN 88 +#define LGW_FSK_MODEM_INVERT_IQ 89 +#define LGW_FILTER_GAIN 90 +#define LGW_RADIO_SELECT 91 +#define LGW_IF_FREQ_0 92 +#define LGW_IF_FREQ_1 93 +#define LGW_IF_FREQ_2 94 +#define LGW_IF_FREQ_3 95 +#define LGW_IF_FREQ_4 96 +#define LGW_IF_FREQ_5 97 +#define LGW_IF_FREQ_6 98 +#define LGW_IF_FREQ_7 99 +#define LGW_IF_FREQ_8 100 +#define LGW_IF_FREQ_9 101 +#define LGW_CHANN_OVERRIDE_AGC_GAIN 102 +#define LGW_CHANN_AGC_GAIN 103 +#define LGW_CORR0_DETECT_EN 104 +#define LGW_CORR1_DETECT_EN 105 +#define LGW_CORR2_DETECT_EN 106 +#define LGW_CORR3_DETECT_EN 107 +#define LGW_CORR4_DETECT_EN 108 +#define LGW_CORR5_DETECT_EN 109 +#define LGW_CORR6_DETECT_EN 110 +#define LGW_CORR7_DETECT_EN 111 +#define LGW_CORR_SAME_PEAKS_OPTION_SF6 112 +#define LGW_CORR_SAME_PEAKS_OPTION_SF7 113 +#define LGW_CORR_SAME_PEAKS_OPTION_SF8 114 +#define LGW_CORR_SAME_PEAKS_OPTION_SF9 115 +#define LGW_CORR_SAME_PEAKS_OPTION_SF10 116 +#define LGW_CORR_SAME_PEAKS_OPTION_SF11 117 +#define LGW_CORR_SAME_PEAKS_OPTION_SF12 118 +#define LGW_CORR_SIG_NOISE_RATIO_SF6 119 +#define LGW_CORR_SIG_NOISE_RATIO_SF7 120 +#define LGW_CORR_SIG_NOISE_RATIO_SF8 121 +#define LGW_CORR_SIG_NOISE_RATIO_SF9 122 +#define LGW_CORR_SIG_NOISE_RATIO_SF10 123 +#define LGW_CORR_SIG_NOISE_RATIO_SF11 124 +#define LGW_CORR_SIG_NOISE_RATIO_SF12 125 +#define LGW_CORR_NUM_SAME_PEAK 126 +#define LGW_CORR_MAC_GAIN 127 +#define LGW_ADJUST_MODEM_START_OFFSET_RDX4 128 +#define LGW_ADJUST_MODEM_START_OFFSET_SF12_RDX4 129 +#define LGW_DBG_CORR_SELECT_SF 130 +#define LGW_DBG_CORR_SELECT_CHANNEL 131 +#define LGW_DBG_DETECT_CPT 132 +#define LGW_DBG_SYMB_CPT 133 +#define LGW_CHIRP_INVERT_RX 134 +#define LGW_DC_NOTCH_EN 135 +#define LGW_IMPLICIT_CRC_EN 136 +#define LGW_IMPLICIT_CODING_RATE 137 +#define LGW_IMPLICIT_PAYLOAD_LENGHT 138 +#define LGW_FREQ_TO_TIME_INVERT 139 +#define LGW_FREQ_TO_TIME_DRIFT 140 +#define LGW_PAYLOAD_FINE_TIMING_GAIN 141 +#define LGW_PREAMBLE_FINE_TIMING_GAIN 142 +#define LGW_TRACKING_INTEGRAL 143 +#define LGW_FRAME_SYNCH_PEAK1_POS 144 +#define LGW_FRAME_SYNCH_PEAK2_POS 145 +#define LGW_PREAMBLE_SYMB1_NB 146 +#define LGW_FRAME_SYNCH_GAIN 147 +#define LGW_SYNCH_DETECT_TH 148 +#define LGW_LLR_SCALE 149 +#define LGW_SNR_AVG_CST 150 +#define LGW_PPM_OFFSET 151 +#define LGW_MAX_PAYLOAD_LEN 152 +#define LGW_ONLY_CRC_EN 153 +#define LGW_ZERO_PAD 154 +#define LGW_DEC_GAIN_OFFSET 155 +#define LGW_CHAN_GAIN_OFFSET 156 +#define LGW_FORCE_HOST_RADIO_CTRL 157 +#define LGW_FORCE_HOST_FE_CTRL 158 +#define LGW_FORCE_DEC_FILTER_GAIN 159 +#define LGW_MCU_RST_0 160 +#define LGW_MCU_RST_1 161 +#define LGW_MCU_SELECT_MUX_0 162 +#define LGW_MCU_SELECT_MUX_1 163 +#define LGW_MCU_CORRUPTION_DETECTED_0 164 +#define LGW_MCU_CORRUPTION_DETECTED_1 165 +#define LGW_MCU_SELECT_EDGE_0 166 +#define LGW_MCU_SELECT_EDGE_1 167 +#define LGW_CHANN_SELECT_RSSI 168 +#define LGW_RSSI_BB_DEFAULT_VALUE 169 +#define LGW_RSSI_DEC_DEFAULT_VALUE 170 +#define LGW_RSSI_CHANN_DEFAULT_VALUE 171 +#define LGW_RSSI_BB_FILTER_ALPHA 172 +#define LGW_RSSI_DEC_FILTER_ALPHA 173 +#define LGW_RSSI_CHANN_FILTER_ALPHA 174 +#define LGW_IQ_MISMATCH_A_AMP_COEFF 175 +#define LGW_IQ_MISMATCH_A_PHI_COEFF 176 +#define LGW_IQ_MISMATCH_B_AMP_COEFF 177 +#define LGW_IQ_MISMATCH_B_SEL_I 178 +#define LGW_IQ_MISMATCH_B_PHI_COEFF 179 +#define LGW_TX_TRIG_IMMEDIATE 180 +#define LGW_TX_TRIG_DELAYED 181 +#define LGW_TX_TRIG_GPS 182 +#define LGW_TX_START_DELAY 183 +#define LGW_TX_FRAME_SYNCH_PEAK1_POS 184 +#define LGW_TX_FRAME_SYNCH_PEAK2_POS 185 +#define LGW_TX_RAMP_DURATION 186 +#define LGW_TX_OFFSET_I 187 +#define LGW_TX_OFFSET_Q 188 +#define LGW_TX_MODE 189 +#define LGW_TX_ZERO_PAD 190 +#define LGW_TX_EDGE_SELECT 191 +#define LGW_TX_EDGE_SELECT_TOP 192 +#define LGW_TX_GAIN 193 +#define LGW_TX_CHIRP_LOW_PASS 194 +#define LGW_TX_FCC_WIDEBAND 195 +#define LGW_TX_SWAP_IQ 196 +#define LGW_MBWSSF_IMPLICIT_HEADER 197 +#define LGW_MBWSSF_IMPLICIT_CRC_EN 198 +#define LGW_MBWSSF_IMPLICIT_CODING_RATE 199 +#define LGW_MBWSSF_IMPLICIT_PAYLOAD_LENGHT 200 +#define LGW_MBWSSF_AGC_FREEZE_ON_DETECT 201 +#define LGW_MBWSSF_FRAME_SYNCH_PEAK1_POS 202 +#define LGW_MBWSSF_FRAME_SYNCH_PEAK2_POS 203 +#define LGW_MBWSSF_PREAMBLE_SYMB1_NB 204 +#define LGW_MBWSSF_FRAME_SYNCH_GAIN 205 +#define LGW_MBWSSF_SYNCH_DETECT_TH 206 +#define LGW_MBWSSF_DETECT_MIN_SINGLE_PEAK 207 +#define LGW_MBWSSF_DETECT_TRIG_SAME_PEAK_NB 208 +#define LGW_MBWSSF_FREQ_TO_TIME_INVERT 209 +#define LGW_MBWSSF_FREQ_TO_TIME_DRIFT 210 +#define LGW_MBWSSF_PPM_CORRECTION 211 +#define LGW_MBWSSF_PAYLOAD_FINE_TIMING_GAIN 212 +#define LGW_MBWSSF_PREAMBLE_FINE_TIMING_GAIN 213 +#define LGW_MBWSSF_TRACKING_INTEGRAL 214 +#define LGW_MBWSSF_ZERO_PAD 215 +#define LGW_MBWSSF_MODEM_BW 216 +#define LGW_MBWSSF_RADIO_SELECT 217 +#define LGW_MBWSSF_RX_CHIRP_INVERT 218 +#define LGW_MBWSSF_LLR_SCALE 219 +#define LGW_MBWSSF_SNR_AVG_CST 220 +#define LGW_MBWSSF_PPM_OFFSET 221 +#define LGW_MBWSSF_RATE_SF 222 +#define LGW_MBWSSF_ONLY_CRC_EN 223 +#define LGW_MBWSSF_MAX_PAYLOAD_LEN 224 +#define LGW_TX_STATUS 225 +#define LGW_FSK_CH_BW_EXPO 226 +#define LGW_FSK_RSSI_LENGTH 227 +#define LGW_FSK_RX_INVERT 228 +#define LGW_FSK_PKT_MODE 229 +#define LGW_FSK_PSIZE 230 +#define LGW_FSK_CRC_EN 231 +#define LGW_FSK_DCFREE_ENC 232 +#define LGW_FSK_CRC_IBM 233 +#define LGW_FSK_ERROR_OSR_TOL 234 +#define LGW_FSK_RADIO_SELECT 235 +#define LGW_FSK_BR_RATIO 236 +#define LGW_FSK_REF_PATTERN_LSB 237 +#define LGW_FSK_REF_PATTERN_MSB 238 +#define LGW_FSK_PKT_LENGTH 239 +#define LGW_FSK_TX_GAUSSIAN_EN 240 +#define LGW_FSK_TX_GAUSSIAN_SELECT_BT 241 +#define LGW_FSK_TX_PATTERN_EN 242 +#define LGW_FSK_TX_PREAMBLE_SEQ 243 +#define LGW_FSK_TX_PSIZE 244 +#define LGW_FSK_NODE_ADRS 245 +#define LGW_FSK_BROADCAST 246 +#define LGW_FSK_AUTO_AFC_ON 247 +#define LGW_FSK_PATTERN_TIMEOUT_CFG 248 +#define LGW_SPI_RADIO_A__DATA 249 +#define LGW_SPI_RADIO_A__DATA_READBACK 250 +#define LGW_SPI_RADIO_A__ADDR 251 +#define LGW_SPI_RADIO_A__CS 252 +#define LGW_SPI_RADIO_B__DATA 253 +#define LGW_SPI_RADIO_B__DATA_READBACK 254 +#define LGW_SPI_RADIO_B__ADDR 255 +#define LGW_SPI_RADIO_B__CS 256 +#define LGW_RADIO_A_EN 257 +#define LGW_RADIO_B_EN 258 +#define LGW_RADIO_RST 259 +#define LGW_LNA_A_EN 260 +#define LGW_PA_A_EN 261 +#define LGW_LNA_B_EN 262 +#define LGW_PA_B_EN 263 +#define LGW_PA_GAIN 264 +#define LGW_LNA_A_CTRL_LUT 265 +#define LGW_PA_A_CTRL_LUT 266 +#define LGW_LNA_B_CTRL_LUT 267 +#define LGW_PA_B_CTRL_LUT 268 +#define LGW_CAPTURE_SOURCE 269 +#define LGW_CAPTURE_START 270 +#define LGW_CAPTURE_FORCE_TRIGGER 271 +#define LGW_CAPTURE_WRAP 272 +#define LGW_CAPTURE_PERIOD 273 +#define LGW_MODEM_STATUS 274 +#define LGW_VALID_HEADER_COUNTER_0 275 +#define LGW_VALID_PACKET_COUNTER_0 276 +#define LGW_VALID_HEADER_COUNTER_MBWSSF 277 +#define LGW_VALID_HEADER_COUNTER_FSK 278 +#define LGW_VALID_PACKET_COUNTER_MBWSSF 279 +#define LGW_VALID_PACKET_COUNTER_FSK 280 +#define LGW_CHANN_RSSI 281 +#define LGW_BB_RSSI 282 +#define LGW_DEC_RSSI 283 +#define LGW_DBG_MCU_DATA 284 +#define LGW_DBG_ARB_MCU_RAM_DATA 285 +#define LGW_DBG_AGC_MCU_RAM_DATA 286 +#define LGW_NEXT_PACKET_CNT 287 +#define LGW_ADDR_CAPTURE_COUNT 288 +#define LGW_TIMESTAMP 289 +#define LGW_DBG_CHANN0_GAIN 290 +#define LGW_DBG_CHANN1_GAIN 291 +#define LGW_DBG_CHANN2_GAIN 292 +#define LGW_DBG_CHANN3_GAIN 293 +#define LGW_DBG_CHANN4_GAIN 294 +#define LGW_DBG_CHANN5_GAIN 295 +#define LGW_DBG_CHANN6_GAIN 296 +#define LGW_DBG_CHANN7_GAIN 297 +#define LGW_DBG_DEC_FILT_GAIN 298 +#define LGW_SPI_DATA_FIFO_PTR 299 +#define LGW_PACKET_DATA_FIFO_PTR 300 +#define LGW_DBG_ARB_MCU_RAM_ADDR 301 +#define LGW_DBG_AGC_MCU_RAM_ADDR 302 +#define LGW_SPI_MASTER_CHIP_SELECT_POLARITY 303 +#define LGW_SPI_MASTER_CPOL 304 +#define LGW_SPI_MASTER_CPHA 305 +#define LGW_SIG_GEN_ANALYSER_MUX_SEL 306 +#define LGW_SIG_GEN_EN 307 +#define LGW_SIG_ANALYSER_EN 308 +#define LGW_SIG_ANALYSER_AVG_LEN 309 +#define LGW_SIG_ANALYSER_PRECISION 310 +#define LGW_SIG_ANALYSER_VALID_OUT 311 +#define LGW_SIG_GEN_FREQ 312 +#define LGW_SIG_ANALYSER_FREQ 313 +#define LGW_SIG_ANALYSER_I_OUT 314 +#define LGW_SIG_ANALYSER_Q_OUT 315 +#define LGW_GPS_EN 316 +#define LGW_GPS_POL 317 +#define LGW_SW_TEST_REG1 318 +#define LGW_SW_TEST_REG2 319 +#define LGW_SW_TEST_REG3 320 +#define LGW_DATA_MNGT_STATUS 321 +#define LGW_DATA_MNGT_CPT_FRAME_ALLOCATED 322 +#define LGW_DATA_MNGT_CPT_FRAME_FINISHED 323 +#define LGW_DATA_MNGT_CPT_FRAME_READEN 324 -#define LGW_TOTALREGS 296 +#define LGW_TOTALREGS 325 /* -------------------------------------------------------------------------- */ /* --- PUBLIC FUNCTIONS PROTOTYPES ------------------------------------------ */ diff --git a/loragw_hal/src/agc_fw.var b/loragw_hal/src/agc_fw.var index c913e0c..7d30fb9 100644 --- a/loragw_hal/src/agc_fw.var +++ b/loragw_hal/src/agc_fw.var @@ -12,217 +12,217 @@ Description: static uint8_t agc_firmware[MCU_AGC_FW_BYTE] = { 0x8A, 0x51, 0x11, 0x28, 0xFF, 0xBF, 0xFF, 0xBF, 0x80, 0x40, 0x03, 0x4E, 0x83, 0x52, 0x03, 0x53, -0xA4, 0xC0, 0x04, 0x88, 0xA5, 0x00, 0x0A, 0xC8, 0xA6, 0x00, 0x01, 0x88, 0xA7, 0x40, 0x8A, 0x51, -0x09, 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0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, diff --git a/loragw_hal/src/arb_fw.var b/loragw_hal/src/arb_fw.var index 58e4f96..014a8e5 100644 --- a/loragw_hal/src/arb_fw.var +++ b/loragw_hal/src/arb_fw.var @@ -11,7 +11,7 @@ Description: */ static uint8_t arb_firmware[MCU_ARB_FW_BYTE] = { -0xFF, 0xE9, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, +0x8A, 0x51, 0x0E, 0xEE, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, @@ -73,70 +73,454 @@ static uint8_t arb_firmware[MCU_ARB_FW_BYTE] = { 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 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0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, +0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, +0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF }; diff --git a/loragw_hal/src/loragw_hal.c b/loragw_hal/src/loragw_hal.c index 1738916..5b261f2 100644 --- a/loragw_hal/src/loragw_hal.c +++ b/loragw_hal/src/loragw_hal.c @@ -58,7 +58,7 @@ const uint32_t rf_rx_bandwidth[LGW_RF_CHAIN_NB] = LGW_RF_RX_BANDWIDTH; const uint32_t rf_tx_lowfreq[LGW_RF_CHAIN_NB] = LGW_RF_TX_LOWFREQ; const uint32_t rf_tx_upfreq[LGW_RF_CHAIN_NB] = LGW_RF_TX_UPFREQ; -#define MCU_ARB_FW_BYTE 2048 /* size of the firmware IN BYTES (= twice the number of 14b words) */ +#define MCU_ARB_FW_BYTE 8192 /* size of the firmware IN BYTES (= twice the number of 14b words) */ #define MCU_AGC_FW_BYTE 8192 /* size of the firmware IN BYTES (= twice the number of 14b words) */ #define SX1257_CLK_OUT 1 @@ -74,8 +74,9 @@ const uint32_t rf_tx_upfreq[LGW_RF_CHAIN_NB] = LGW_RF_TX_UPFREQ; #define SX1257_RX_ADC_TRIM 6 /* 0 to 7, 6 for 32MHz ref, 5 for 36MHz ref */ #define SX1257_RXBB_BW 2 -#define RSSI_OFFSET_LORA_MULTI -127.0 /* calibrated value */ -#define RSSI_OFFSET_LORA_STD 0.0 /* RSSI not working properly on that IF channel */ +#define RSSI_OFFSET_LORA_MULTI -130.0 /* calibrated value */ +#define RSSI_OFFSET_LORA_STD -168.0 /* calibrated for all bandwidth */ +#define RSSI_OFFSET_FSK 0.0 /* TODO */ #define TX_METADATA_NB 16 #define RX_METADATA_NB 16 @@ -322,13 +323,15 @@ void lgw_constant_adjust(void) { // lgw_reg_w(LGW_CHIRP_INVERT_RX,1); /* default 1 */ // lgw_reg_w(LGW_RX_EDGE_SELECT,0); /* default 0 */ // lgw_reg_w(LGW_MBWSSF_MODEM_INVERT_IQ,0); /* default 0 */ - lgw_reg_w(LGW_DC_NOTCH_EN,1); /* default 0 */ - // lgw_reg_w(LGW_RSSI_BB_FILTER_ALPHA,7); /* default 7 */ + // lgw_reg_w(LGW_DC_NOTCH_EN,1); /* default 1 */ + lgw_reg_w(LGW_RSSI_BB_FILTER_ALPHA,9); /* default 7 */ lgw_reg_w(LGW_RSSI_DEC_FILTER_ALPHA,7); /* default 5 */ lgw_reg_w(LGW_RSSI_CHANN_FILTER_ALPHA,7); /* default 8 */ // lgw_reg_w(LGW_RSSI_BB_DEFAULT_VALUE,32); /* default 32 */ lgw_reg_w(LGW_RSSI_CHANN_DEFAULT_VALUE,90); /* default 100 */ lgw_reg_w(LGW_RSSI_DEC_DEFAULT_VALUE,90); /* default 100 */ + // lgw_reg_w(LGW_DEC_GAIN_OFFSET, 8); /* default 8 */ + // lgw_reg_w(LGW_CHAN_GAIN_OFFSET, 7); /* default 7 */ /* Correlator setup */ // lgw_reg_w(LGW_CORR_DETECT_EN,126); /* default 126 */ @@ -364,7 +367,6 @@ void lgw_constant_adjust(void) { // lgw_reg_w(LGW_PAYLOAD_FINE_TIMING_GAIN,2); /* default 2 */ // lgw_reg_w(LGW_TRACKING_INTEGRAL,0); /* default 0 */ // lgw_reg_w(LGW_ADJUST_MODEM_START_OFFSET_RDX8,0); /* default 0 */ - // lgw_reg_w(LGW_ADJUST_MODEM_START_OFFSET_RDX4,0); /* default 0 */ // lgw_reg_w(LGW_ADJUST_MODEM_START_OFFSET_SF12_RDX4,4092); /* default 4092 */ // lgw_reg_w(LGW_MAX_PAYLOAD_LEN,255); /* default 255 */ @@ -384,9 +386,35 @@ void lgw_constant_adjust(void) { // lgw_reg_w(LGW_MBWSSF_TRACKING_INTEGRAL,0); /* default 0 */ // lgw_reg_w(LGW_MBWSSF_AGC_FREEZE_ON_DETECT,1); /* default 1 */ + /* FSK datapath */ + lgw_reg_w(LGW_FSK_RX_INVERT,1); /* default 0 */ + lgw_reg_w(LGW_FSK_MODEM_INVERT_IQ,1); /* default 0 */ + + /* FSK demod */ + // lgw_reg_w(LGW_FSK_AUTO_AFC_ON,0); /* default 0 */ + // lgw_reg_w(LGW_FSK_BROADCAST,0); /* default 0 */ + lgw_reg_w(LGW_FSK_CRC_EN,1); /* default 0 */ + // lgw_reg_w(LGW_FSK_CRC_IBM,0); /* default 0 */ + // lgw_reg_w(LGW_FSK_DCFREE_ENC,0); /* default 0 */ + lgw_reg_w(LGW_FSK_ERROR_OSR_TOL,10); /* default 0 */ + lgw_reg_w(LGW_FSK_MODEM_INVERT_IQ,1); /* default 0 */ + // lgw_reg_w(LGW_FSK_NODE_ADRS,0); /* default 0 */ + lgw_reg_w(LGW_FSK_PATTERN_TIMEOUT_CFG,64); /* default 0 */ + lgw_reg_w(LGW_FSK_PKT_LENGTH,64); /* default 0 */ + lgw_reg_w(LGW_FSK_PKT_MODE,1); /* default 0 */ + lgw_reg_w(LGW_FSK_PSIZE,3); /* default 0 */ + lgw_reg_w(LGW_FSK_REF_PATTERN_LSB,0x55); /* default 0 */ + lgw_reg_w(LGW_FSK_REF_PATTERN_MSB,0x55); /* default 0 */ + lgw_reg_w(LGW_FSK_RSSI_LENGTH,4); /* default 0 */ + lgw_reg_w(LGW_FSK_CH_BW_EXPO,2); /* 125kHz (default 0, 500kHz) */ + + /* FSK mod */ + lgw_reg_w(LGW_FSK_TX_PSIZE,3); /* default 0 */ + lgw_reg_w(LGW_FSK_TX_GAUSSIAN_SELECT_BT,1); /* default 0 */ + /* TX */ // lgw_reg_w(LGW_TX_MODE,0); /* default 0 */ - lgw_reg_w(LGW_TX_START_DELAY,5000); /* default 0 */ + lgw_reg_w(LGW_TX_START_DELAY,1000); /* default 0 */ lgw_reg_w(LGW_TX_SWAP_IQ,1); /* "normal" polarity; default 0 */ return; @@ -465,10 +493,6 @@ int lgw_rxif_setconf(uint8_t if_chain, struct lgw_conf_rxif_s conf) { fill default if necessary, and commit configuration if everything is OK */ switch (ifmod_config[if_chain]) { case IF_LORA_STD: - if (conf.rf_chain != 0) { - DEBUG_MSG("ERROR: LORA_STD IF CHAIN CAN ONLY BE ASSOCIATED TO RF_CHAIN 0\n"); - return LGW_HAL_ERROR; - } /* fill default parameters if needed */ if (conf.bandwidth == 0) { conf.bandwidth = BW_250KHZ; @@ -556,9 +580,10 @@ int lgw_start(void) { /* reset the registers (also shuts the radios down) */ lgw_soft_reset(); - /* Ungate clock (gated by default), needed for SPI master to SX1257 */ - lgw_reg_w(LGW_CLK32M_EN, 1); - lgw_reg_w(LGW_CLKHS_EN, 1); + /* Ungate clocks (gated by default) */ + lgw_reg_w(LGW_GLOBAL_EN, 1); + // lgw_reg_w(LGW_CLK32M_EN, 1); + // lgw_reg_w(LGW_CLKHS_EN, 1); /* switch on and reset the radios (also starts the 32 MHz XTAL) */ lgw_reg_w(LGW_RADIO_A_EN,1); /* radio A *must* be started to get 32 MHz clk */ @@ -581,14 +606,7 @@ int lgw_start(void) { lgw_reg_w(LGW_FORCE_HOST_FE_CTRL,0); lgw_reg_w(LGW_FORCE_DEC_FILTER_GAIN,0); - // /* TODO load the calibration firmware and wait for calibration to end */ - // load_firmware(MCU_AGC, cal_firmware, ARRAY_SIZE(cal_firmware)); - // lgw_reg_w(LGW_MCU_RST, 0); /* start the AGC MCU */ - // lgw_reg_w(LGW_FORCE_HOST_REG_CTRL,0); /* let the AGC MCU control the registers */ - // do { - // lgw_reg_r(LGW_VERSION, &read_value); - // } while (read_value == 0); - // lgw_reg_w(LGW_MCU_RST, 3); /* reset all MCU */ + /* TODO load the calibration firmware and wait for calibration to end */ /* in the absence of calibration firmware, do a "manual" calibration */ lgw_reg_w(LGW_TX_OFFSET_I,10); @@ -653,9 +671,6 @@ int lgw_start(void) { lgw_reg_w(LGW_MCU_RST_0, 0); lgw_reg_w(LGW_MCU_RST_1, 0); - /* Show that nanoC is configured (LED 602 green, blue at reset)*/ - lgw_reg_w(LGW_LED_REG, 5); - lgw_is_started = true; return LGW_HAL_SUCCESS; } @@ -740,16 +755,11 @@ int lgw_receive(uint8_t max_pkt, struct lgw_pkt_rx_s *pkt_data) { if ((ifmod == IF_LORA_MULTI) || (ifmod == IF_LORA_STD)) { DEBUG_MSG("Note: Lora packet\n"); - if ((buff[s+1] & 0x01) == 1) { /* CRC enabled */ - if (stat_fifo == 1) { - p->status = STAT_CRC_OK; - } else if (stat_fifo == 3){ - p->status = STAT_CRC_BAD; - } else { - p->status = STAT_UNDEFINED; - } - } else { - p->status = STAT_NO_CRC; + switch(stat_fifo & 0x07) { + case 5: p->status = STAT_CRC_OK; break; + case 7: p->status = STAT_CRC_BAD; break; + case 1: p->status = STAT_NO_CRC; break; + default: p->status = STAT_UNDEFINED; } p->modulation = MOD_LORA; p->snr = ((float)((int8_t)buff[s+2]))/4; @@ -999,14 +1009,12 @@ int lgw_status(uint8_t select, uint8_t *code) { lgw_reg_r(LGW_TX_STATUS, &read_value); if (lgw_is_started == false) { *code = TX_OFF; - } else if ((read_value & 0x70) == 0) { - *code = TX_EMPTY; - } else if ((read_value & 0x10) != 0) { - *code = TX_DELAYED; - } else if ((read_value & 0x60) != 0) { + } else if ((read_value & 0x10) == 0) { /* bit 4 @1: TX programmed */ + *code = TX_FREE; + } else if ((read_value & 0x60) != 0) { /* bit 5 or 6 @1: TX sequence */ *code = TX_EMITTING; } else { - *code = TX_STATUS_UNKNOWN; + *code = TX_SCHEDULED; } return LGW_HAL_SUCCESS; diff --git a/loragw_hal/src/loragw_reg.c b/loragw_hal/src/loragw_reg.c index 716c6c0..a9122d2 100644 --- a/loragw_hal/src/loragw_reg.c +++ b/loragw_hal/src/loragw_reg.c @@ -66,7 +66,7 @@ this file is autogenerated from registers description const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {-1,0,0,0,2,0,0}, /* PAGE_REG */ {-1,0,7,0,1,0,0}, /* SOFT_RESET */ - {-1,1,0,0,8,1,101}, /* VERSION */ + {-1,1,0,0,8,1,103}, /* VERSION */ {-1,2,0,0,16,0,0}, /* RX_DATA_BUF_ADDR */ {-1,4,0,0,8,0,0}, /* RX_DATA_BUF_DATA */ {-1,5,0,0,8,0,0}, /* TX_DATA_BUF_ADDR */ @@ -82,8 +82,9 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {-1,16,0,0,1,0,0}, /* MBWSSF_MODEM_ENABLE */ {-1,16,1,0,1,0,0}, /* CONCENTRATOR_MODEM_ENABLE */ {-1,16,2,0,1,0,0}, /* FSK_MODEM_ENABLE */ - {-1,17,0,0,1,0,0}, /* CLK32M_EN */ - {-1,17,1,0,1,0,0}, /* CLKHS_EN */ + {-1,16,3,0,1,0,0}, /* GLOBAL_EN */ + {-1,17,0,0,1,0,1}, /* CLK32M_EN */ + {-1,17,1,0,1,0,1}, /* CLKHS_EN */ {-1,18,0,0,1,0,0}, /* START_BIST0 */ {-1,18,1,0,1,0,0}, /* START_BIST1 */ {-1,18,2,0,1,0,0}, /* CLEAR_BIST0 */ @@ -143,14 +144,16 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {-1,29,0,0,5,0,0}, /* GPIO_MODE */ {-1,30,0,0,5,1,0}, /* GPIO_PIN_REG_IN */ {-1,31,0,0,5,0,0}, /* GPIO_PIN_REG_OUT */ - {-1,32,0,0,8,0,0}, /* MCU_AGC_STATUS */ + {-1,32,0,0,8,1,0}, /* MCU_AGC_STATUS */ + {-1,125,0,0,8,1,0}, /* MCU_ARB_STATUS */ {-1,126,0,0,8,1,1}, /* CHIP_ID */ - {-1,127,0,0,1,0,0}, /* EMERGENCY_FORCE_HOST_CTRL */ + {-1,127,0,0,1,0,1}, /* EMERGENCY_FORCE_HOST_CTRL */ {0,33,0,0,1,0,0}, /* RX_INVERT_IQ */ {0,33,1,0,1,0,1}, /* MODEM_INVERT_IQ */ {0,33,2,0,1,0,0}, /* MBWSSF_MODEM_INVERT_IQ */ {0,33,3,0,1,0,0}, /* RX_EDGE_SELECT */ {0,33,4,0,1,0,0}, /* MISC_RADIO_EN */ + {0,33,5,0,1,0,0}, /* FSK_MODEM_INVERT_IQ */ {0,34,0,0,4,0,7}, /* FILTER_GAIN */ {0,35,0,0,8,0,240}, /* RADIO_SELECT */ {0,36,0,1,13,0,-384}, /* IF_FREQ_0 */ @@ -189,7 +192,6 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {0,77,0,0,4,0,4}, /* CORR_SIG_NOISE_RATIO_SF12 */ {0,78,0,0,4,0,4}, /* CORR_NUM_SAME_PEAK */ {0,78,4,0,3,0,5}, /* CORR_MAC_GAIN */ - {0,79,0,0,12,0,0}, /* ADJUST_MODEM_START_OFFSET_RDX8 */ {0,81,0,0,12,0,0}, /* ADJUST_MODEM_START_OFFSET_RDX4 */ {0,83,0,0,12,0,4092}, /* ADJUST_MODEM_START_OFFSET_SF12_RDX4 */ {0,85,0,0,8,0,7}, /* DBG_CORR_SELECT_SF */ @@ -197,7 +199,7 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {0,87,0,0,8,1,0}, /* DBG_DETECT_CPT */ {0,88,0,0,8,1,0}, /* DBG_SYMB_CPT */ {0,89,0,0,1,0,1}, /* CHIRP_INVERT_RX */ - {0,89,1,0,1,0,0}, /* DC_NOTCH_EN */ + {0,89,1,0,1,0,1}, /* DC_NOTCH_EN */ {0,90,0,0,1,0,0}, /* IMPLICIT_CRC_EN */ {0,90,1,0,3,0,0}, /* IMPLICIT_CODING_RATE */ {0,91,0,0,8,0,0}, /* IMPLICIT_PAYLOAD_LENGHT */ @@ -219,7 +221,6 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {0,103,0,0,8,0,0}, /* ZERO_PAD */ {0,104,0,0,4,0,8}, /* DEC_GAIN_OFFSET */ {0,104,4,0,4,0,7}, /* CHAN_GAIN_OFFSET */ - {0,105,0,0,1,0,1}, /* FORCE_HOST_REG_CTRL */ {0,105,1,0,1,0,1}, /* FORCE_HOST_RADIO_CTRL */ {0,105,2,0,1,0,1}, /* FORCE_HOST_FE_CTRL */ {0,105,3,0,1,0,1}, /* FORCE_DEC_FILTER_GAIN */ @@ -249,13 +250,15 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {1,34,0,0,16,0,0}, /* TX_START_DELAY */ {1,36,0,0,4,0,1}, /* TX_FRAME_SYNCH_PEAK1_POS */ {1,36,4,0,4,0,2}, /* TX_FRAME_SYNCH_PEAK2_POS */ - {1,39,0,0,8,0,0}, /* TX_OFFSET_I */ - {1,40,0,0,8,0,0}, /* TX_OFFSET_Q */ + {1,37,0,0,3,0,0}, /* TX_RAMP_DURATION */ + {1,39,0,1,8,0,0}, /* TX_OFFSET_I */ + {1,40,0,1,8,0,0}, /* TX_OFFSET_Q */ {1,41,0,0,1,0,0}, /* TX_MODE */ {1,41,1,0,4,0,0}, /* TX_ZERO_PAD */ {1,41,5,0,1,0,0}, /* TX_EDGE_SELECT */ + {1,41,6,0,1,0,0}, /* TX_EDGE_SELECT_TOP */ {1,42,0,0,2,0,0}, /* TX_GAIN */ - {1,42,2,0,3,0,0}, /* TX_CHIRP_LOW_PASS */ + {1,42,2,0,3,0,5}, /* TX_CHIRP_LOW_PASS */ {1,42,5,0,2,0,0}, /* TX_FCC_WIDEBAND */ {1,42,7,0,1,0,1}, /* TX_SWAP_IQ */ {1,43,0,0,1,0,0}, /* MBWSSF_IMPLICIT_HEADER */ @@ -286,14 +289,37 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {1,60,0,0,4,0,7}, /* MBWSSF_RATE_SF */ {1,60,4,0,1,0,1}, /* MBWSSF_ONLY_CRC_EN */ {1,61,0,0,8,0,255}, /* MBWSSF_MAX_PAYLOAD_LEN */ - {1,62,0,0,8,1,0}, /* TX_STATUS */ + {1,62,0,0,8,1,128}, /* TX_STATUS */ + {1,63,0,0,3,0,0}, /* FSK_CH_BW_EXPO */ + {1,63,3,0,3,0,0}, /* FSK_RSSI_LENGTH */ + {1,63,6,0,1,0,0}, /* FSK_RX_INVERT */ + {1,63,7,0,1,0,0}, /* FSK_PKT_MODE */ + {1,64,0,0,3,0,0}, /* FSK_PSIZE */ + {1,64,3,0,1,0,0}, /* FSK_CRC_EN */ + {1,64,4,0,2,0,0}, /* FSK_DCFREE_ENC */ + {1,64,6,0,1,0,0}, /* FSK_CRC_IBM */ + {1,65,0,0,5,0,0}, /* FSK_ERROR_OSR_TOL */ + {1,65,7,0,1,0,0}, /* FSK_RADIO_SELECT */ + {1,66,0,0,16,0,0}, /* FSK_BR_RATIO */ + {1,68,0,0,32,0,0}, /* FSK_REF_PATTERN_LSB */ + {1,72,0,0,32,0,0}, /* FSK_REF_PATTERN_MSB */ + {1,76,0,0,8,0,0}, /* FSK_PKT_LENGTH */ + {1,77,0,0,1,0,1}, /* FSK_TX_GAUSSIAN_EN */ + {1,77,1,0,2,0,0}, /* FSK_TX_GAUSSIAN_SELECT_BT */ + {1,77,3,0,1,0,1}, /* FSK_TX_PATTERN_EN */ + {1,77,4,0,1,0,0}, /* FSK_TX_PREAMBLE_SEQ */ + {1,77,5,0,3,0,0}, /* FSK_TX_PSIZE */ + {1,80,0,0,8,0,0}, /* FSK_NODE_ADRS */ + {1,81,0,0,8,0,0}, /* FSK_BROADCAST */ + {1,82,0,0,1,0,1}, /* FSK_AUTO_AFC_ON */ + {1,83,0,0,10,0,0}, /* FSK_PATTERN_TIMEOUT_CFG */ {2,33,0,0,8,0,0}, /* SPI_RADIO_A__DATA */ {2,34,0,0,8,1,0}, /* SPI_RADIO_A__DATA_READBACK */ - {2,35,0,0,14,0,0}, /* SPI_RADIO_A__ADDR */ + {2,35,0,0,8,0,0}, /* SPI_RADIO_A__ADDR */ {2,37,0,0,1,0,0}, /* SPI_RADIO_A__CS */ {2,38,0,0,8,0,0}, /* SPI_RADIO_B__DATA */ {2,39,0,0,8,1,0}, /* SPI_RADIO_B__DATA_READBACK */ - {2,40,0,0,14,0,0}, /* SPI_RADIO_B__ADDR */ + {2,40,0,0,8,0,0}, /* SPI_RADIO_B__ADDR */ {2,42,0,0,1,0,0}, /* SPI_RADIO_B__CS */ {2,43,0,0,1,0,0}, /* RADIO_A_EN */ {2,43,1,0,1,0,0}, /* RADIO_B_EN */ @@ -312,7 +338,6 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {2,47,6,0,1,0,0}, /* CAPTURE_FORCE_TRIGGER */ {2,47,7,0,1,0,0}, /* CAPTURE_WRAP */ {2,48,0,0,16,0,0}, /* CAPTURE_PERIOD */ - {2,50,0,0,3,0,3}, /* LED_REG */ {2,51,0,0,8,1,0}, /* MODEM_STATUS */ {2,52,0,0,8,1,0}, /* VALID_HEADER_COUNTER_0 */ {2,54,0,0,8,1,0}, /* VALID_PACKET_COUNTER_0 */ @@ -359,7 +384,11 @@ const struct lgw_reg_s loregs[LGW_TOTALREGS] = { {2,89,1,0,1,0,1}, /* GPS_POL */ {2,90,0,1,8,0,0}, /* SW_TEST_REG1 */ {2,91,2,1,6,0,0}, /* SW_TEST_REG2 */ - {2,92,0,1,16,0,0} /* SW_TEST_REG3 */ + {2,92,0,1,16,0,0}, /* SW_TEST_REG3 */ + {2,94,0,0,4,1,0}, /* DATA_MNGT_STATUS */ + {2,95,0,0,5,1,0}, /* DATA_MNGT_CPT_FRAME_ALLOCATED */ + {2,96,0,0,5,1,0}, /* DATA_MNGT_CPT_FRAME_FINISHED */ + {2,97,0,0,5,1,0} /* DATA_MNGT_CPT_FRAME_READEN */ }; /* -------------------------------------------------------------------------- */ diff --git a/loragw_hal/test/test_loragw_hal.c b/loragw_hal/test/test_loragw_hal.c index 751d00b..f23f55c 100644 --- a/loragw_hal/test/test_loragw_hal.c +++ b/loragw_hal/test/test_loragw_hal.c @@ -248,7 +248,7 @@ int main(int argc, char **argv) wait_ms(100); lgw_status(TX_STATUS, &status_var); /* get TX status */ printf("%d:", status_var); - } while ((status_var != TX_EMPTY) && (j < 100)); + } while ((status_var != TX_FREE) && (j < 100)); ++tx_cnt; printf("\nTX finished\n"); } |