Merge git.multitech.net:corecdp

248 files changed, 73924 insertions, 71 deletions

diff --git a/multitech/conf/distro/corecdp.conf b/multitech/conf/distro/corecdp.conf
index e411b6c..01374c4 100644
--- a/multitech/conf/distro/corecdp.conf
+++ b/multitech/conf/distro/corecdp.conf
@@ -8,7 +8,7 @@ require conf/distro/angstrom-2010.x.conf
 
 DISTRO_NAME = "CoreCDP"
 DISTRO = "corecdp"
-DISTRO_VERSION = "2.2.0"
+DISTRO_VERSION = "2.3.0"
 DISTRO_PR = ".10"
 DISTRO_TYPE = "release"
 TARGET_VENDOR = "-corecdp"
@@ -28,6 +28,11 @@ INHERIT += "logging"
 
 IPKG_VARIANT = "opkg corecdp-version"
 
+# use newer linux headers
+LINUX_LIBC_HEADERS_VERSION = "2.6.39"
+PREFERRED_VERSION_linux-libc-headers = "${LINUX_LIBC_HEADERS_VERSION}"
+PREFERRED_VERSION_linux-libc-headers-native = "${LINUX_LIBC_HEADERS_VERSION}"
+
 # use busybox instead of tinylogin
 IMAGE_LOGIN_MANAGER = "busybox"
 
@@ -40,7 +45,14 @@ PREFERRED_PROVIDER_mtd-utils-static = "mtd-utils-static"
 # java versions from meta-java
 require java.inc
 
+# mask out some OE-classic recipes so we use meta-java instead
+BBMASK .= "|/openembedded/recipes/(jakarta-libs|jakarta-common)/"
+
 PREFERRED_VERSION_lighttpd = "1.4.28"
 
 # don't build bluez4 and the large amount of deps just for libpcap
 PREFERRED_PROVIDER_libpcap = "libpcap-nobluetooth"
+
+PREFERRED_VERSION_iw = "0.9.20"
+PREFERRED_VERSION_wpa-supplicant = "1.0"
+PREFERRED_VERSION_hostap-daemon = "1.0"
diff --git a/multitech/conf/machine/mt100eocg-pcie-dk.conf b/multitech/conf/machine/mt100eocg-pcie-dk.conf
new file mode 100644
index 0000000..e7c4ae3
--- /dev/null
+++ b/multitech/conf/machine/mt100eocg-pcie-dk.conf
@@ -0,0 +1,30 @@
+#@TYPE: Machine
+#@Name: Multi-Tech MT100EOCG PCIE Developer Kit
+#@DESCRIPTION: Machine configuration for the MultiConnect OCG-E with PCIE-DK board
+
+TARGET_ARCH = "arm"
+
+PREFERRED_PROVIDER_virtual/kernel = "linux"
+
+PREFERRED_VERSION_linux = "2.6.39.4"
+MACHINE_KERNEL_PR = "r2"
+PREFERRED_VERSION_mts-io ?= "0.6.0"
+
+KERNEL_IMAGETYPE = "uImage"
+UBOOT_MACHINE = "at91sam9g20ek_nandflash_config"
+
+PREFERRED_VERSION_at91bootstrap = "2.13"
+PREFERRED_VERSION_u-boot = "1.3.4"
+
+#don't try to access tty1
+USE_VT = "0"
+
+MACHINE_FEATURES = "kernel26 ext2 usbhost usbgadget"
+EXTRA_IMAGEDEPENDS += "at91bootstrap u-boot"
+
+# used by sysvinit_2
+SERIAL_CONSOLE = "115200 ttyS0"
+IMAGE_FSTYPES ?= "jffs2"
+EXTRA_IMAGECMD_jffs2 = "--pad --little-endian --eraseblock=0x20000 -n"
+
+require conf/machine/include/tune-arm926ejs.inc
diff --git a/multitech/conf/machine/mt100eocg.conf b/multitech/conf/machine/mt100eocg.conf
index adb620d..7053920 100644
--- a/multitech/conf/machine/mt100eocg.conf
+++ b/multitech/conf/machine/mt100eocg.conf
@@ -7,7 +7,7 @@ TARGET_ARCH = "arm"
 PREFERRED_PROVIDER_virtual/kernel = "linux"
 
 PREFERRED_VERSION_linux = "2.6.35"
-PREFERRED_VERSION_mts-io ?= "0.5.1"
+PREFERRED_VERSION_mts-io ?= "0.6.0"
 
 KERNEL_IMAGETYPE = "uImage"
 UBOOT_MACHINE = "at91sam9g20ek_nandflash_config"
diff --git a/multitech/conf/machine/mtcdp.conf b/multitech/conf/machine/mtcdp.conf
index 0d6a135..4091e56 100644
--- a/multitech/conf/machine/mtcdp.conf
+++ b/multitech/conf/machine/mtcdp.conf
@@ -7,7 +7,7 @@ TARGET_ARCH = "arm"
 PREFERRED_PROVIDER_virtual/kernel = "linux"
 
 PREFERRED_VERSION_linux = "2.6.35"
-PREFERRED_VERSION_mts-io ?= "0.5.1"
+PREFERRED_VERSION_mts-io ?= "0.6.0"
 
 KERNEL_IMAGETYPE = "uImage"
 UBOOT_MACHINE = "at91sam9g20ek_nandflash_config"
diff --git a/multitech/conf/machine/mtocgd3.conf b/multitech/conf/machine/mtocgd3.conf
new file mode 100644
index 0000000..c991d67
--- /dev/null
+++ b/multitech/conf/machine/mtocgd3.conf
@@ -0,0 +1,32 @@
+#@TYPE: Machine
+#@Name: Multi-Tech MTOCGD3
+#@DESCRIPTION: Machine configuration for the MultiConnect OCG-D MTOCGD3 hardware
+
+TARGET_ARCH = "arm"
+
+PREFERRED_PROVIDER_virtual/kernel = "linux"
+
+PREFERRED_VERSION_linux = "2.6.39.4"
+MACHINE_KERNEL_PR = "r7"
+PREFERRED_VERSION_mts-io ?= "0.6.0"
+
+KERNEL_IMAGETYPE = "uImage"
+UBOOT_MACHINE = "at91sam9x5ek_nandflash_config"
+PREFERRED_VERSION_u-boot = "2012.10"
+
+AT91BOOTSTRAP_BOARD = "at91sam9x5eknf_uboot"
+PREFERRED_VERSION_at91bootstrap = "3.5.2"
+
+#don't try to access tty1
+USE_VT = "0"
+
+MACHINE_FEATURES = "kernel26 ext2 usbhost usbgadget"
+EXTRA_IMAGEDEPENDS += "at91bootstrap u-boot"
+
+# used by sysvinit_2
+SERIAL_CONSOLE = "115200 ttyS0"
+
+IMAGE_FSTYPES ?= "jffs2"
+EXTRA_IMAGECMD_jffs2 = "--little-endian --eraseblock=0x20000 --pagesize=0x800 -n"
+
+require conf/machine/include/tune-arm926ejs.inc
diff --git a/multitech/contrib/uboot-setenv-mtocgd3 b/multitech/contrib/uboot-setenv-mtocgd3
new file mode 100644
index 0000000..ecfa2dd
--- /dev/null
+++ b/multitech/contrib/uboot-setenv-mtocgd3
@@ -0,0 +1,59 @@
+print setting U-Boot variables...

+send setenv bootargs              \'mem=128M console=ttyS0,115200 root=/dev/mtdblock8 ro rootfstype=jffs2\'

+send setenv bootcmd               \'nboot.jffs2 ${loadaddr} 0 ${kernel_addr}; bootm ${loadaddr}\'

+send setenv bootdelay             1

+send setenv serverip              192.168.2.2

+send setenv ipaddr                192.168.2.1

+send setenv netmask               255.255.255.0

+send setenv loadaddr              0x22000000

+send setenv stdin                 serial

+send setenv stdout                serial

+send setenv stderr                serial

+send setenv ethact                macb0
+send setenv mtdids                nand0=nand0

+send setenv mtdparts              mtdparts=nand0:256k(bootstrap),512k(u-boot),640k(u-boot-env1),640k(u-boot-env2),6M(kernel),8M(config),8M(oem),-(rootfs)

+send setenv bootstrap_file        oe_bootstrap_pmecc_padded.bin

+send setenv uboot_file            oe_u-boot.bin

+send setenv uboot_env1_file       oe_uboot_env1.bin

+send setenv uboot_env2_file       oe_uboot_env2.bin

+send setenv kernel_file           oe_uImage.bin

+send setenv config_file           oe_config.tar.gz

+send setenv oem_file              oe_oem.tar.gz

+send setenv rootfs_file           oe_rootfs.jffs2

+send setenv bootstrap_addr        0x00000000

+send setenv uboot_addr            0x00040000

+send setenv uboot_env1_addr       0x000C0000

+send setenv uboot_env2_addr       0x00160000

+send setenv kernel_addr           0x00200000

+send setenv config_addr           0x00800000

+send setenv oem_addr              0x01000000

+send setenv rootfs_addr           0x01800000

+send setenv bootstrap_size        0x00040000

+send setenv uboot_size            0x00080000

+send setenv uboot_env1_size       0x000A0000

+send setenv uboot_env2_size       0x000A0000

+send setenv kernel_size           0x00600000

+send setenv config_size           0x00800000

+send setenv oem_size              0x00800000

+send setenv erase_bootstrap       \'nand erase.part bootstrap\'

+send setenv erase_uboot           \'nand erase.part u-boot\'

+send setenv erase_uboot_env1      \'nand erase.part u-boot-env1\'

+send setenv erase_uboot_env2      \'nand erase.part u-boot-env2\'

+send setenv erase_kernel          \'nand erase.part kernel\'

+send setenv erase_config          \'nand erase.part config\'

+send setenv erase_oem             \'nand erase.part oem\'

+send setenv erase_rootfs          \'nand erase.part rootfs\'

+send setenv tftp_bootstrap        \'tftp ${loadaddr} ${bootstrap_file}; run erase_bootstrap; nand write.jffs2 ${fileaddr} bootstrap ${filesize}\'

+send setenv tftp_uboot            \'tftp ${loadaddr} ${uboot_file}; run erase_uboot; nand write.jffs2 ${fileaddr} u-boot ${filesize}\'

+send setenv tftp_uboot_env1       \'tftp ${loadaddr} ${uboot_env1_file}; run erase_uboot_env1; nand write.jffs2 ${fileaddr} u-boot-env1 ${filesize}\'

+send setenv tftp_uboot_env2       \'tftp ${loadaddr} ${uboot_env2_file}; run erase_uboot_env2; nand write.jffs2 ${fileaddr} u-boot-env2 ${filesize}\'

+send setenv tftp_kernel           \'tftp ${loadaddr} ${kernel_file}; run erase_kernel; nand write.jffs2 ${fileaddr} kernel ${filesize}\'

+send setenv tftp_config           \'tftp ${loadaddr} ${config_file}; run erase_config; nand write.jffs2 ${fileaddr} config ${filesize}\'

+send setenv tftp_oem              \'tftp ${loadaddr} ${oem_file}; run erase_oem; nand write.jffs2 ${fileaddr} oem ${filesize}\'

+send setenv tftp_rootfs           \'tftp ${loadaddr} ${rootfs_file}; run erase_rootfs; nand write.jffs2 ${fileaddr} rootfs ${filesize}\'

+send setenv krb                   \'run tftp_kernel; run tftp_rootfs; boot\'

+send setenv rb                    \'run tftp_rootfs; boot\'

+print saving...

+send saveenv

+send saveenv

+send printenv

diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-2.13/mt100eocg/memory_bus_1.8v.patch b/multitech/recipes/at91bootstrap/at91bootstrap-2.13/memory_bus_1.8v.patch
index 045f255..045f255 100644
--- a/multitech/recipes/at91bootstrap/at91bootstrap-2.13/mt100eocg/memory_bus_1.8v.patch
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-2.13/memory_bus_1.8v.patch
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-2.13/mt100eocg-pcie-dk/defconfig b/multitech/recipes/at91bootstrap/at91bootstrap-2.13/mt100eocg-pcie-dk/defconfig
new file mode 100644
index 0000000..8338b3d
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-2.13/mt100eocg-pcie-dk/defconfig
@@ -0,0 +1,91 @@
+#
+# Automatically generated make config: don't edit
+# Tue Jan 12 22:00:36 2010
+#
+HAVE_DOT_CONFIG=y
+CONFIG_BOARDNAME="at91sam9g20nf"
+# CONFIG_AT91SAM9260EK is not set
+# CONFIG_AT91SAM9261EK is not set
+# CONFIG_AT91SAM9263EK is not set
+# CONFIG_AT91SAM9RLEK is not set
+# CONFIG_AT91SAM9XEEK is not set
+# CONFIG_AT91SAM9G10EK is not set
+CONFIG_AT91SAM9G20EK=y
+# CONFIG_AT91SAM9G45EK is not set
+# CONFIG_AT91SAM9G45EKES is not set
+# CONFIG_AT91SAM9M10EK is not set
+# CONFIG_AT91CAP9ADK is not set
+# CONFIG_AT91CAP9STK is not set
+# CONFIG_AFEB9260 is not set
+CONFIG_CHIP="AT91SAM9G20"
+CONFIG_BOARD="at91sam9g20ek"
+CONFIG_MACH_TYPE="0x658"
+CONFIG_LINK_ADDR="0x000000"
+CONFIG_TOP_OF_MEMORY="0x301000"
+CONFIG_BOOTSTRAP_MAXSIZE="13000"
+# CONFIG_CRYSTAL_12_000MHZ is not set
+# CONFIG_CRYSTAL_16_000MHZ is not set
+# CONFIG_CRYSTAL_16_36766MHZ is not set
+CONFIG_CRYSTAL_18_432MHZ=y
+ALLOW_CRYSTAL_18_432MHZ=y
+CONFIG_CRYSTAL="CRYSTAL_18_432MHZ"
+# CONFIG_CPU_CLK_166MHZ is not set
+# CONFIG_CPU_CLK_180MHZ is not set
+# CONFIG_CPU_CLK_200MHZ is not set
+# CONFIG_CPU_CLK_240MHZ is not set
+# CONFIG_CPU_CLK_266MHZ is not set
+CONFIG_CPU_CLK_400MHZ=y
+ALLOW_CPU_CLK_400MHZ=y
+# DISABLE_CPU_CLK_240MHZ is not set
+# CONFIG_BUS_SPEED_83MHZ is not set
+# CONFIG_BUS_SPEED_90MHZ is not set
+# CONFIG_BUS_SPEED_100MHZ is not set
+CONFIG_BUS_SPEED_133MHZ=y
+
+#
+# Memory selection
+#
+CONFIG_SDRAM=y
+# CONFIG_SDDRC is not set
+# CONFIG_DDR2 is not set
+ALLOW_DATAFLASH=y
+# ALLOW_FLASH is not set
+ALLOW_NANDFLASH=y
+# ALLOW_SDCARD is not set
+# ALLOW_PSRAM is not set
+# ALLOW_SDRAM_16BIT is not set
+# CONFIG_RAM_32MB is not set
+CONFIG_RAM_64MB=y
+# CONFIG_RAM_128MB is not set
+# CONFIG_RAM_256MB is not set
+# CONFIG_DATAFLASH is not set
+# CONFIG_FLASH is not set
+CONFIG_NANDFLASH=y
+# CONFIG_SDCARD is not set
+CONFIG_MEMORY="nandflash"
+ALLOW_DATAFLASH_RECOVERY=y
+ALLOW_BOOT_FROM_DATAFLASH_CS0=y
+ALLOW_BOOT_FROM_DATAFLASH_CS1=y
+DATAFLASHCARD_ON_CS0=y
+
+#
+# NAND Flash configuration
+#
+# CONFIG_NANDFLASH_SMALL_BLOCKS is not set
+CONFIG_PROJECT="nandflash"
+CONFIG_LOAD_UBOOT=y
+# CONFIG_LOAD_64KB is not set
+# CONFIG_LOAD_1MB is not set
+# CONFIG_LOAD_4MB is not set
+CONFIG_IMG_ADDRESS="0x00020000"
+CONFIG_IMG_SIZE="0x00040000"
+CONFIG_JUMP_ADDR="0x23F00000"
+CONFIG_APP_CHECK=y
+# CONFIG_LONG_TEST is not set
+CONFIG_DEBUG=y
+CONFIG_VERBOSE=y
+CONFIG_HW_INIT=y
+# CONFIG_USER_HW_INIT is not set
+# CONFIG_THUMB is not set
+CONFIG_SX_AT91=y
+CONFIG_RAW_AT91=y
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/at91bootstrap-3.5.2-add-install.patch b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/at91bootstrap-3.5.2-add-install.patch
new file mode 100644
index 0000000..6f007b9
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/at91bootstrap-3.5.2-add-install.patch
@@ -0,0 +1,20 @@
+Index: at91bootstrap-3.5.2/Makefile
+===================================================================
+--- at91bootstrap-3.5.2.orig/Makefile	2013-02-08 14:38:40.660054339 -0600
++++ at91bootstrap-3.5.2/Makefile	2013-02-08 14:41:30.626272862 -0600
+@@ -359,4 +359,15 @@
+ 
+ PHONY+=tarball tarballx
+ 
++install:
++	-install -d $(DESTDIR)
++	install $(AT91BOOTSTRAP) $(DESTDIR)/$(IMAGE)
++	-rm -f $(DESTDIR)/$(SYMLINK)
++	(cd ${DESTDIR} ; \
++	ln -sf ${IMAGE} ${SYMLINK} \
++	)
++
++
++PHONY+=install
++
+ .PHONY: $(PHONY)
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/at91sam9x5_4bit_pmecc_header.bin b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/at91sam9x5_4bit_pmecc_header.bin
new file mode 100644
index 0000000..f8d6073
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/at91sam9x5_4bit_pmecc_header.bin
@@ -0,0 +1 @@
+$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À$�À
\ No newline at end of file
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/create_4bit_pmecc_header.rb b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/create_4bit_pmecc_header.rb
new file mode 100755
index 0000000..780d728
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/create_4bit_pmecc_header.rb
@@ -0,0 +1,5 @@
+#!/usr/bin/env ruby
+
+52.times do 
+	print ["052490c0"].pack('H*')
+end
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/mtocgd3/at91bootstrap-3.5.2-mtocgd3.patch b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/mtocgd3/at91bootstrap-3.5.2-mtocgd3.patch
new file mode 100644
index 0000000..97ae327
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/mtocgd3/at91bootstrap-3.5.2-mtocgd3.patch
@@ -0,0 +1,65 @@
+Index: at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig
+===================================================================
+--- at91bootstrap-3.5.2.orig/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-02-08 14:05:34.034501648 -0600
++++ at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-02-08 14:07:19.010677033 -0600
+@@ -42,7 +42,8 @@
+ ALLOW_PIO3=y
+ CONFIG_HAS_PIO3=y
+ CPU_HAS_PMECC=y
+-CONFIG_LOAD_ONE_WIRE=y
++# MTS: don't load one wire
++# CONFIG_LOAD_ONE_WIRE is not set
+ 
+ #
+ # Memory selection
+@@ -102,4 +103,5 @@
+ # CONFIG_USER_HW_INIT is not set
+ CONFIG_THUMB=y
+ CONFIG_SCLK=y
+-CONFIG_DISABLE_WATCHDOG=y
++# MTS: don't disable watchdog
++# CONFIG_DISABLE_WATCHDOG is not set
+Index: at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.h
+===================================================================
+--- at91bootstrap-3.5.2.orig/board/at91sam9x5ek/at91sam9x5ek.h	2013-02-08 14:03:42.050364515 -0600
++++ at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.h	2013-02-08 14:07:56.500399983 -0600
+@@ -95,7 +95,8 @@
+ #define CONFIG_SYS_NAND_CLE_PIN		AT91C_PIN_PD(3)
+ #define CONFIG_SYS_NAND_ENABLE_PIN      AT91C_PIN_PD(4)
+ 
+-#define	PMECC_ERROR_CORR_BITS		2
++/* MTS: use 4-bit PMECC */
++#define	PMECC_ERROR_CORR_BITS		4
+ #define	PMECC_SECTOR_SIZE		512
+ 
+ #define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET	0xC000
+Index: at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.c
+===================================================================
+--- at91bootstrap-3.5.2.orig/board/at91sam9x5ek/at91sam9x5ek.c	2013-02-08 14:03:57.562179405 -0600
++++ at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.c	2013-02-08 14:11:56.477737850 -0600
+@@ -268,10 +268,9 @@
+ 
+ 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
+ 	reg |= AT91C_EBI_CS3A_SM;
+-	if ((get_cm_rev() == 'A') && (get_cm_vendor() == VENDOR_EMBEST))
+-		reg &= ~AT91C_EBI_NFD0_ON_D16;
+-	else
+-		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
++	/* MTR2 Rev A NAND is on D0-D7, DDR_MP_EN must be disabled */
++	reg &= ~AT91C_EBI_NFD0_ON_D16;
++	reg &= ~AT91C_EBI_DDR_MP_EN;
+ 
+ 	reg &= ~AT91C_EBI_DRV;
+ 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
+@@ -300,10 +299,7 @@
+ 		| AT91_SMC_TDF_(1)),
+ 		AT91C_BASE_SMC + SMC_CTRL3);
+ 
+-	/* Configure the PIO controller */
+-	if ((get_cm_rev() == 'A') && (get_cm_vendor() == VENDOR_EMBEST))
+-		pio_configure(nand_pins_lo);
+-	else
++	/* MTR2 */
+ 		pio_configure(nand_pins_hi);
+ 
+ 	writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend b/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend
index 2bd3fd8..9b78b06 100644
--- a/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend
+++ b/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend
@@ -1,7 +1,7 @@
 FILESEXTRA := "${THISDIR}"
 FILESPATHBASE =. "${FILESEXTRA}:"
 
-PR .= ".corecdp3"
+PR .= ".corecdp4"
 
 SRC_URI += "file://defconfig \
 			file://nand_ids_toshiba.patch \
@@ -11,3 +11,6 @@ SRC_URI += "file://defconfig \
 # run memory bus at 1.8v for mt100eocg
 SRC_URI_append_mt100eocg = " file://memory_bus_1.8v.patch"
 AT91BOOTSTRAP_FLAGS_append_mt100eocg = " -DCONFIG_USER_EBI_1V8"
+
+SRC_URI_append_mt100eocg-pcie-dk = " file://memory_bus_1.8v.patch"
+AT91BOOTSTRAP_FLAGS_append_mt100eocg-pcie-dk = " -DCONFIG_USER_EBI_1V8"
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap_3.5.2.bb b/multitech/recipes/at91bootstrap/at91bootstrap_3.5.2.bb
new file mode 100644
index 0000000..0957496
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap_3.5.2.bb
@@ -0,0 +1,25 @@
+require at91bootstrap_3.5.inc
+
+PR = "r0"
+
+SRC_URI = "https://github.com/linux4sam/at91bootstrap/archive/v3.5.2.tar.gz \
+	   file://at91bootstrap-3.5.2-add-install.patch"
+
+SRC_URI_append_mtocgd3 = " file://at91bootstrap-3.5.2-mtocgd3.patch \
+                      file://at91sam9x5_4bit_pmecc_header.bin \
+		      "
+
+SRC_URI[md5sum] = "5f818dcd0d4d0fe1f0447b35d3f050eb"
+SRC_URI[sha256sum] = "cea3d75470000f1eff64e1f9dd356a1d7264b0a33b8af9e9461ab64653a6b6fb"
+
+# generate a bootstrap file padded with the header needed for 4-bit PMECC
+# The padded file can be flashed via u-boot without any need to set the PMECC header using SAM-BA
+do_pad_4bit_pmecc() {
+	cp -f ${WORKDIR}/at91sam9x5_4bit_pmecc_header.bin ${DEPLOY_DIR_IMAGE}/at91bootstrap_pmecc_padded.bin
+	cat ${DEPLOY_DIR_IMAGE}/at91bootstrap.bin >> ${DEPLOY_DIR_IMAGE}/at91bootstrap_pmecc_padded.bin
+}
+
+do_install_append_mtocgd3() {
+	do_pad_4bit_pmecc
+}
+
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap_3.5.inc b/multitech/recipes/at91bootstrap/at91bootstrap_3.5.inc
new file mode 100644
index 0000000..ac147c0
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap_3.5.inc
@@ -0,0 +1,27 @@
+DESCRIPTION = "at91bootstrap: loaded into internal SRAM by AT91 BootROM"
+SECTION = "bootloaders"
+
+PARALLEL_MAKE = ""
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+EXTRA_OEMAKE = "CROSS_COMPILE=${TARGET_PREFIX} DESTDIR=${DEPLOY_DIR_IMAGE} REVISION=${PR}"
+
+do_compile () {
+	unset LDFLAGS
+	unset CFLAGS
+	unset CPPFLAGS
+
+	rm -Rf ${S}/binaries
+	for board in ${AT91BOOTSTRAP_BOARD} ; do
+		oe_runmake mrproper
+		filename=`find board -name ${board}_defconfig`
+		if ! [ "x$filename" == "x" ] ; then 
+			cp $filename .config
+			oe_runmake 
+			oe_runmake install
+		else
+			echo "${board} could not be built"
+			exit 1
+		fi
+	done
+}
diff --git a/multitech/recipes/base-files/base-files/mt100eocg-pcie-dk/fstab b/multitech/recipes/base-files/base-files/mt100eocg-pcie-dk/fstab
new file mode 100644
index 0000000..da00b50
--- /dev/null
+++ b/multitech/recipes/base-files/base-files/mt100eocg-pcie-dk/fstab
@@ -0,0 +1,9 @@
+rootfs               /                    auto       defaults              1  1
+proc                 /proc                proc       defaults              0  0
+devpts               /dev/pts             devpts     mode=0620,gid=5       0  0
+usbfs                /proc/bus/usb        usbfs      defaults              0  0
+tmpfs                /var/volatile        tmpfs      defaults              0  0
+tmpfs                /dev/shm             tmpfs      mode=0777             0  0
+tmpfs                /media/ram           tmpfs      defaults              0  0
+
+/dev/mtdblock6       /var/config          jffs2      defaults              0  0
diff --git a/multitech/recipes/base-files/base-files/mt100eocg-pcie-dk/profile b/multitech/recipes/base-files/base-files/mt100eocg-pcie-dk/profile
new file mode 100644
index 0000000..0879251
--- /dev/null
+++ b/multitech/recipes/base-files/base-files/mt100eocg-pcie-dk/profile
@@ -0,0 +1,34 @@
+# /etc/profile: system-wide .profile file for the Bourne shell (sh(1))
+# and Bourne compatible shells (bash(1), ksh(1), ash(1), ...).
+
+PATH="/usr/local/bin:/usr/bin:/bin"
+EDITOR="/bin/vi"			# needed for packages like cron
+test -z "$TERM" && TERM="vt100"	# Basic terminal capab. For screen etc.
+
+if [ ! -e /etc/localtime ]; then
+	TZ="UTC"		# Time Zone. Look at http://theory.uwinnipeg.ca/gnu/glibc/libc_303.html 
+				# for an explanation of how to set this to your local timezone.
+	export TZ
+fi
+
+if [ "`id -u`" -eq 0 ]; then
+   PATH=$PATH:/usr/local/sbin:/usr/sbin:/sbin
+fi
+if [ "$PS1" ]; then
+# works for bash and ash (no other shells known to be in use here)
+   PS1='\$ '
+fi
+
+if [ -d /etc/profile.d ]; then
+  for i in /etc/profile.d/*.sh; do
+    if [ -r $i ]; then
+      . $i
+    fi
+  done
+  unset i
+fi
+
+export PATH PS1 OPIEDIR QPEDIR QTDIR EDITOR TERM
+
+umask 022
+
diff --git a/multitech/recipes/base-files/base-files/mtocgd3/fstab b/multitech/recipes/base-files/base-files/mtocgd3/fstab
new file mode 100644
index 0000000..84dc1f0
--- /dev/null
+++ b/multitech/recipes/base-files/base-files/mtocgd3/fstab
@@ -0,0 +1,12 @@
+rootfs               /                    auto       defaults              1  1
+proc                 /proc                proc       defaults              0  0
+devpts               /dev/pts             devpts     mode=0620,gid=5       0  0
+usbfs                /proc/bus/usb        usbfs      defaults              0  0
+tmpfs                /var/volatile        tmpfs      defaults              0  0
+tmpfs                /dev/shm             tmpfs      mode=0777             0  0
+tmpfs                /media/ram           tmpfs      defaults              0  0
+
+/dev/mtdblock6       /var/config          jffs2      defaults              0  0
+
+# SD card
+/dev/mmcblk0p1       /media/card          auto       defaults,sync         0  0
diff --git a/multitech/recipes/base-files/base-files/mtocgd3/profile b/multitech/recipes/base-files/base-files/mtocgd3/profile
new file mode 100644
index 0000000..0879251
--- /dev/null
+++ b/multitech/recipes/base-files/base-files/mtocgd3/profile
@@ -0,0 +1,34 @@
+# /etc/profile: system-wide .profile file for the Bourne shell (sh(1))
+# and Bourne compatible shells (bash(1), ksh(1), ash(1), ...).
+
+PATH="/usr/local/bin:/usr/bin:/bin"
+EDITOR="/bin/vi"			# needed for packages like cron
+test -z "$TERM" && TERM="vt100"	# Basic terminal capab. For screen etc.
+
+if [ ! -e /etc/localtime ]; then
+	TZ="UTC"		# Time Zone. Look at http://theory.uwinnipeg.ca/gnu/glibc/libc_303.html 
+				# for an explanation of how to set this to your local timezone.
+	export TZ
+fi
+
+if [ "`id -u`" -eq 0 ]; then
+   PATH=$PATH:/usr/local/sbin:/usr/sbin:/sbin
+fi
+if [ "$PS1" ]; then
+# works for bash and ash (no other shells known to be in use here)
+   PS1='\$ '
+fi
+
+if [ -d /etc/profile.d ]; then
+  for i in /etc/profile.d/*.sh; do
+    if [ -r $i ]; then
+      . $i
+    fi
+  done
+  unset i
+fi
+
+export PATH PS1 OPIEDIR QPEDIR QTDIR EDITOR TERM
+
+umask 022
+
diff --git a/multitech/recipes/bluez/bluez4.inc b/multitech/recipes/bluez/bluez4.inc
new file mode 100644
index 0000000..600c192
--- /dev/null
+++ b/multitech/recipes/bluez/bluez4.inc
@@ -0,0 +1,85 @@
+DESCRIPTION = "Linux Bluetooth Stack Userland V4"
+HOMEPAGE = "http://www.bluez.org"
+SECTION = "libs"
+PRIORITY = "optional"
+LICENSE = "GPLv2/LGPLv2.1"
+#DEPENDS = "gst-plugins-base alsa-lib virtual/libusb0 dbus-glib"
+DEPENDS = "virtual/libusb0 dbus-glib"
+INC_PR = "r11"
+
+FILESPATHBASE .= ":${OETREE}/openembedded/recipes/bluez"
+
+# temporary solution until bug 5176 is properly fixed
+PROVIDES += "bluez-utils bluez-libs bluez-utils-dbus"
+RPROVIDES_bluez4 += "bluez-utils bluez-libs bluez-utils-dbus"
+RPROVIDES_bluez4-dev = "bluez-libs-dev"
+
+SRC_URI = "\
+  http://www.kernel.org/pub/linux/bluetooth/bluez-${PV}.tar.gz \
+  file://fix-dfutool-usb-declaration-mismatch.patch \
+  file://bluetooth.conf \
+"
+
+SRC_URI_append_mt100eocg-pcie-dk = "file://bluetooth.init"
+SRC_URI_append_mtocgd3 = "file://bluetooth.init"
+
+S = "${WORKDIR}/bluez-${PV}"
+
+inherit autotools update-rc.d
+
+EXTRA_OECONF = "\
+  --enable-debug \
+  --disable-gstreamer \
+  --disable-alsa \
+  --enable-usb \
+  --enable-netlink \
+  --enable-tools \
+  --enable-bccmd \
+  --disable-hid2hci \
+  --enable-dfutool \
+  --enable-hidd \
+  --enable-pand \
+  --enable-dund \
+  --disable-cups \
+  --enable-test \
+  --enable-manpages \
+  --enable-configfiles \
+  --enable-initscripts \
+  --disable-pcmciarules \
+"
+
+do_install_append() {
+        install -m 0644 ${S}/audio/audio.conf ${D}/${sysconfdir}/bluetooth/
+        install -m 0644 ${S}/network/network.conf ${D}/${sysconfdir}/bluetooth/
+        install -m 0644 ${S}/input/input.conf ${D}/${sysconfdir}/bluetooth/
+        # at_console doesn't really work with the current state of OE, so punch some more holes so people can actually use BT
+        install -m 0644 ${WORKDIR}/bluetooth.conf ${D}/${sysconfdir}/dbus-1/system.d/
+}
+
+do_install_append_mt100eocg-pcie-dk() {
+  install -d ${D}${sysconfdir}/init.d
+  install -m 0755 ${WORKDIR}/bluetooth.init ${D}${sysconfdir}/init.d/bluetooth
+}
+do_install_append_mtocgd3() {
+  install -d ${D}${sysconfdir}/init.d
+  install -m 0755 ${WORKDIR}/bluetooth.init ${D}${sysconfdir}/init.d/bluetooth
+}
+
+INITSCRIPT_NAME = "bluetooth"
+INITSCRIPT_PARAMS = "defaults 23 19"
+
+#PACKAGES =+ "gst-plugin-bluez libasound-module-bluez"
+
+#FILES_gst-plugin-bluez = "${libdir}/gstreamer-0.10/lib*.so"
+#FILES_libasound-module-bluez = "${libdir}/alsa-lib/lib*.so ${datadir}/alsa/bluetooth.conf"
+FILES_${PN} += "${libdir}/bluetooth/plugins/*.so ${base_libdir}/udev"
+FILES_${PN}-dev += "\
+  ${libdir}/bluetooth/plugins/*.la \
+  ${libdir}/alsa-lib/*.la \
+  ${libdir}/gstreamer-0.10/*.la \
+"
+
+FILES_${PN}-dbg += "\
+  ${libdir}/bluetooth/plugins/.debug \
+  ${libdir}/*/.debug \
+"
diff --git a/multitech/recipes/bluez/bluez4_4.98.bb b/multitech/recipes/bluez/bluez4_4.98.bb
new file mode 100644
index 0000000..6d1b4df
--- /dev/null
+++ b/multitech/recipes/bluez/bluez4_4.98.bb
@@ -0,0 +1,20 @@
+require bluez4.inc
+
+SRC_URI[md5sum] = "362864b716950baa04797de735fc237b"
+SRC_URI[sha256sum] = "9a5b655bada7c7a1921cb3bac83b8a32bbe49893e4c7a1377cdc1b0d35f7d233"
+
+#DEPENDS += "libsndfile1"
+
+PR = "${INC_PR}.0"
+
+# Not all distros have a recent enough udev
+BTUDEV = " --disable-udevrules"
+BTUDEV_angstrom = " --enable-udevrules"
+BTUDEV_corecdp = " --enable-udevrules"
+BTUDEV_shr = " --enable-udevrules"
+
+EXTRA_OECONF += "${BTUDEV}"
+
+FILES_${PN}-dbg += "\
+  ${base_libdir}/*/.debug \
+"
diff --git a/multitech/recipes/bluez/files/bluetooth.init b/multitech/recipes/bluez/files/bluetooth.init
new file mode 100755
index 0000000..58318c3
--- /dev/null
+++ b/multitech/recipes/bluez/files/bluetooth.init
@@ -0,0 +1,35 @@
+#!/bin/bash
+
+bt_start() 
+{
+	echo "Enabling bluetooth..."
+	mts-io-sysfs store bt-enabled 0
+	usleep 200000
+	mts-io-sysfs store bt-enabled 1
+	sleep 1
+	echo "Setting up bluetooth device..."
+	hciattach /dev/bt texas
+}
+
+bt_stop() {
+	echo "Disabling bluetooth..."
+	killall hciattach
+	mts-io-sysfs store bt-enabled 0
+}
+
+case "$1" in
+    start)
+	bt_start
+	;;
+    stop)
+	bt_stop
+	;;
+    restart)
+	bt_stop
+	bt_start
+	;;
+    *)
+	echo "Usage $0: start|stop|restart"
+	exit 1
+	;;
+esac
diff --git a/multitech/recipes/compat-wireless/compat-wireless-stable.inc b/multitech/recipes/compat-wireless/compat-wireless-stable.inc
new file mode 100644
index 0000000..8cf156d
--- /dev/null
+++ b/multitech/recipes/compat-wireless/compat-wireless-stable.inc
@@ -0,0 +1,21 @@
+DESCRIPTION = "Latest wireless drivers"
+HOMEPAGE = "http://wireless.kernel.org/en/users/Download"
+SECTION = "kernel/modules"
+LICENSE = "GPL"
+RDEPENDS = "wireless-tools"
+INC_PR = "r0"
+
+S = "${WORKDIR}/compat-wireless-${COMPAT_WIRELESS_VERSION}"
+
+inherit module
+
+EXTRA_OEMAKE = "KLIB_BUILD=${STAGING_KERNEL_DIR} KLIB=${D}"
+
+do_configure_append() {
+	sed -i "s#@./scripts/update-initramfs## " Makefile
+}
+
+do_install() {
+	oe_runmake DEPMOD=echo DESTDIR="${D}" INSTALL_MOD_PATH="${D}" LDFLAGS="" install-modules
+}
+
diff --git a/multitech/recipes/compat-wireless/mt100eocg-pcie-dk/wl12xx_sdio.patch b/multitech/recipes/compat-wireless/mt100eocg-pcie-dk/wl12xx_sdio.patch
new file mode 100644
index 0000000..1b7ae64
--- /dev/null
+++ b/multitech/recipes/compat-wireless/mt100eocg-pcie-dk/wl12xx_sdio.patch
@@ -0,0 +1,25 @@
+Index: compat-wireless/drivers/net/wireless/wl12xx/sdio.c
+===================================================================
+--- compat-wireless.orig/drivers/net/wireless/wl12xx/sdio.c	2013-02-18 11:47:02.831869486 -0600
++++ compat-wireless/drivers/net/wireless/wl12xx/sdio.c	2013-02-18 12:21:04.472513066 -0600
+@@ -277,14 +277,19 @@
+ 	wl->irq = wlan_data->irq;
+ 	if (wl->ref_clock < 0)
+ 		wl->ref_clock = wlan_data->board_ref_clock;
++
++	/* MTPCIE: force irq trigger
+ 	if (wl->tcxo_clock < 0)
+ 		wl->tcxo_clock = wlan_data->board_tcxo_clock;
+ 	wl->platform_quirks = wlan_data->platform_quirks;
+ 
+ 	if (wl->platform_quirks & WL12XX_PLATFORM_QUIRK_EDGE_IRQ)
+-		irqflags = IRQF_TRIGGER_RISING;
++	*/
++		irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
++	/*
+ 	else
+ 		irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
++	*/
+ 
+ 	ret = request_threaded_irq(wl->irq, wl1271_hardirq, wl1271_irq,
+ 				   irqflags,
diff --git a/multitech/recipes/compat-wireless/ti-compat-wireless-wl12xx/wl12xx-arp-reply.patch b/multitech/recipes/compat-wireless/ti-compat-wireless-wl12xx/wl12xx-arp-reply.patch
new file mode 100644
index 0000000..ab438f0
--- /dev/null
+++ b/multitech/recipes/compat-wireless/ti-compat-wireless-wl12xx/wl12xx-arp-reply.patch
@@ -0,0 +1,45 @@
+Index: compat-wireless/drivers/net/wireless/wl12xx/cmd.c
+===================================================================
+--- compat-wireless.orig/drivers/net/wireless/wl12xx/cmd.c	2012-12-31 09:58:56.746126785 -0600
++++ compat-wireless/drivers/net/wireless/wl12xx/cmd.c	2012-12-31 10:02:03.246660822 -0600
+@@ -1214,7 +1214,7 @@
+ 	skb_reserve(skb, sizeof(*hdr) + WL1271_EXTRA_SPACE_MAX);
+ 
+ 	tmpl = (struct wl12xx_arp_rsp_template *)skb_put(skb, sizeof(*tmpl));
+-	memset(tmpl, 0, sizeof(tmpl));
++	memset(tmpl, 0, sizeof(*tmpl));
+ 
+ 	/* llc layer */
+ 	memcpy(tmpl->llc_hdr, rfc1042_header, sizeof(rfc1042_header));
+@@ -1263,7 +1263,7 @@
+ 
+ 	/* mac80211 header */
+ 	hdr = (struct ieee80211_hdr_3addr *)skb_push(skb, sizeof(*hdr));
+-	memset(hdr, 0, sizeof(hdr));
++	memset(hdr, 0, sizeof(*hdr));
+ 	fc = IEEE80211_FTYPE_DATA | IEEE80211_FCTL_TODS;
+ 	if (wl->qos)
+ 		fc |= IEEE80211_STYPE_QOS_DATA;
+Index: compat-wireless/drivers/net/wireless/wl12xx/main.c
+===================================================================
+--- compat-wireless.orig/drivers/net/wireless/wl12xx/main.c	2012-12-31 09:59:00.246129356 -0600
++++ compat-wireless/drivers/net/wireless/wl12xx/main.c	2012-12-31 10:01:26.746205394 -0600
+@@ -4142,10 +4142,14 @@
+ 				goto out;
+ 			}
+ 
+-			ret = wl1271_acx_arp_ip_filter(wl,
+-				(ACX_ARP_FILTER_ARP_FILTERING |
+-				 ACX_ARP_FILTER_AUTO_ARP),
+-				addr);
++//Possible Firmware Issue with TI chip and Auto-ARP Response while using encryption.
++//Disabling Auto-ARP for now.
++//			ret = wl1271_acx_arp_ip_filter(wl,
++//				(ACX_ARP_FILTER_ARP_FILTERING |
++//				 ACX_ARP_FILTER_AUTO_ARP),
++//				addr);
++			ret = wl1271_acx_arp_ip_filter(wl, 0, addr);
++
+ 		} else {
+ 			wl->ip_addr = 0;
+ 			ret = wl1271_acx_arp_ip_filter(wl, 0, addr);
diff --git a/multitech/recipes/compat-wireless/ti-compat-wireless-wl12xx/wl12xx-set-power.patch b/multitech/recipes/compat-wireless/ti-compat-wireless-wl12xx/wl12xx-set-power.patch
new file mode 100644
index 0000000..3cd1342
--- /dev/null
+++ b/multitech/recipes/compat-wireless/ti-compat-wireless-wl12xx/wl12xx-set-power.patch
@@ -0,0 +1,37 @@
+Index: compat-wireless/drivers/net/wireless/wl12xx/sdio.c
+===================================================================
+--- compat-wireless.orig/drivers/net/wireless/wl12xx/sdio.c
++++ compat-wireless/drivers/net/wireless/wl12xx/sdio.c
+@@ -169,6 +169,10 @@ static int wl1271_sdio_power_on(struct w
+ 	struct sdio_func *func = wl_to_func(wl);
+ 	int ret;
+ 
++	// MTS: enable chip on power on
++	if (wl->set_power)
++		wl->set_power(1);
++
+ 	/* If enabled, tell runtime PM not to power off the card */
+ 	if (pm_runtime_enabled(&func->dev)) {
+ 		ret = pm_runtime_get_sync(&func->dev);
+@@ -193,6 +197,10 @@ static int wl1271_sdio_power_off(struct 
+ 	struct sdio_func *func = wl_to_func(wl);
+ 	int ret;
+ 
++	// MTS: disable chip on power off
++	if (wl->set_power)
++		wl->set_power(0);
++
+ 	sdio_disable_func(func);
+ 	sdio_release_host(func);
+ 
+@@ -262,6 +270,10 @@ static int __devinit wl1271_probe(struct
+ 		goto out_free;
+ 	}
+ 
++	// MTS: add set_power to control enable pin
++	if (wlan_data->set_power)
++		wl->set_power = wlan_data->set_power;
++
+ 	wl->irq = wlan_data->irq;
+ 	if (wl->ref_clock < 0)
+ 		wl->ref_clock = wlan_data->board_ref_clock;
diff --git a/multitech/recipes/compat-wireless/ti-compat-wireless-wl12xx_R4SP2.bb b/multitech/recipes/compat-wireless/ti-compat-wireless-wl12xx_R4SP2.bb
new file mode 100644
index 0000000..d000351
--- /dev/null
+++ b/multitech/recipes/compat-wireless/ti-compat-wireless-wl12xx_R4SP2.bb
@@ -0,0 +1,33 @@
+include compat-wireless-stable.inc
+
+LOCAL_PR = "${INC_PR}.1"
+MACHINE_KERNEL_PR_append = "${LOCAL_PR}"
+
+SRC_URI = "https://gforge.ti.com/gf/download/frsrelease/768/5331/ti-compat-wireless-wl12xx-r4-12-12-20.tar.gz \
+	   http://processors.wiki.ti.com/images/2/23/R4_SP2_Patches.zip;name=r4sp2 \
+	file://${WORKDIR}/0004-added-driver-version.patch \
+	file://${WORKDIR}/0005-wl12xx-don-t-allow-scans-in-AP-mode.patch \
+	file://${WORKDIR}/0006-wl12xx-handle-idle-changes-per-interface.patch \
+	file://${WORKDIR}/0007-wl12xx-prevent-double-idle-on-off-transitions.patch \
+	file://${WORKDIR}/0008-wl12xx-remove-warning-message-during-IBSS-Tx.patch \
+	file://${WORKDIR}/0012-mac80211-set-upasd-queues-and-max-sp-only-on-sta-addition.patch \
+	file://${WORKDIR}/0013-wl12xx-Make-sure-HW-is-available-in-sched-scan-ops.patch \
+	file://wl12xx-arp-reply.patch \
+	file://wl12xx-set-power.patch \
+	"
+
+SRC_URI_append_mt100eocg-pcie-dk = " \
+	file://wl12xx_sdio.patch \
+	"
+
+S = "${WORKDIR}/compat-wireless"
+
+SRC_URI[md5sum] =  "89fa40e0ece490cf73920a71df1c3558"
+SRC_URI[sha256sum] =  "752b53b09e9ae168a4a7f32ad009bb2b8b245c152f65ace1edc51a1ef8bba59f"
+SRC_URI[r4sp2.md5sum] =  "2524ae356e5fe528da977dfe19f20b32"
+SRC_URI[r4sp2.sha256sum] =  "72936b852465ba98a72cdfa66bdb49aff66d1a42080514e000211aac078a4b24"
+
+do_configure() {
+	cd ${S}
+        ./scripts/driver-select wl12xx
+}
diff --git a/multitech/recipes/hostap/hostap-daemon-1.0.inc b/multitech/recipes/hostap/hostap-daemon-1.0.inc
new file mode 100644
index 0000000..b0b6a44
--- /dev/null
+++ b/multitech/recipes/hostap/hostap-daemon-1.0.inc
@@ -0,0 +1,26 @@
+HOMEPAGE = "http://hostap.epitest.fi"
+SECTION = "kernel/userland"
+PRIORITY = "optional"
+LICENSE = "GPL"
+DEPENDS = "libnl openssl"
+
+inherit update-rc.d
+INITSCRIPT_NAME=hostapd
+
+do_configure() {
+	install -m 0644 ${WORKDIR}/defconfig ${S}/.config
+}
+
+do_compile() {
+	make
+}
+
+do_install() {
+	install -d ${D}${sbindir} ${D}${sysconfdir}/init.d
+	install -m 0644 ${WORKDIR}/hostapd.conf ${D}${sysconfdir}
+	install -m 0755 ${S}/hostapd ${D}${sbindir}
+	install -m 0755 ${S}/hostapd_cli ${D}${sbindir}
+	install -m 755 ${WORKDIR}/init ${D}${sysconfdir}/init.d/hostapd
+}
+
+CONFFILES_${PN} += "${sysconfdir}/hostapd.conf"
diff --git a/multitech/recipes/hostap/hostap-daemon-1.0/defconfig b/multitech/recipes/hostap/hostap-daemon-1.0/defconfig
new file mode 100644
index 0000000..1f3c6f4
--- /dev/null
+++ b/multitech/recipes/hostap/hostap-daemon-1.0/defconfig
@@ -0,0 +1,145 @@
+# Example hostapd build time configuration
+#
+# This file lists the configuration options that are used when building the
+# hostapd binary. All lines starting with # are ignored. Configuration option
+# lines must be commented out complete, if they are not to be included, i.e.,
+# just setting VARIABLE=n is not disabling that variable.
+#
+# This file is included in Makefile, so variables like CFLAGS and LIBS can also
+# be modified from here. In most cass, these lines should use += in order not
+# to override previous values of the variables.
+
+# Driver interface for Host AP driver
+CONFIG_DRIVER_HOSTAP=y
+
+# Driver interface for wired authenticator
+CONFIG_DRIVER_WIRED=y
+
+# Driver interface for madwifi driver
+#CONFIG_DRIVER_MADWIFI=y
+#CFLAGS += -I../../madwifi # change to the madwifi source directory
+
+# Driver interface for Prism54 driver
+CONFIG_DRIVER_PRISM54=y
+
+# Driver interface for drivers using the nl80211 kernel interface
+CONFIG_DRIVER_NL80211=y
+CONFIG_LIBNL20=y
+# driver_nl80211.c requires a rather new libnl (version 1.1) which may not be
+# shipped with your distribution yet. If that is the case, you need to build
+# newer libnl version and point the hostapd build to use it.
+#LIBNL=/usr/src/libnl
+#CFLAGS += -I$(LIBNL)/include
+#LIBS += -L$(LIBNL)/lib
+
+# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver)
+#CONFIG_DRIVER_BSD=y
+#CFLAGS += -I/usr/local/include
+#LIBS += -L/usr/local/lib
+
+# Driver interface for no driver (e.g., RADIUS server only)
+#CONFIG_DRIVER_NONE=y
+
+# IEEE 802.11F/IAPP
+CONFIG_IAPP=y
+
+# WPA2/IEEE 802.11i RSN pre-authentication
+CONFIG_RSN_PREAUTH=y
+
+# PeerKey handshake for Station to Station Link (IEEE 802.11e DLS)
+CONFIG_PEERKEY=y
+
+# IEEE 802.11w (management frame protection)
+# This version is an experimental implementation based on IEEE 802.11w/D1.0
+# draft and is subject to change since the standard has not yet been finalized.
+# Driver support is also needed for IEEE 802.11w.
+#CONFIG_IEEE80211W=y
+
+# Integrated EAP server
+CONFIG_EAP=y
+
+# EAP-MD5 for the integrated EAP server
+CONFIG_EAP_MD5=y
+
+# EAP-TLS for the integrated EAP server
+CONFIG_EAP_TLS=y
+
+# EAP-MSCHAPv2 for the integrated EAP server
+CONFIG_EAP_MSCHAPV2=y
+
+# EAP-PEAP for the integrated EAP server
+CONFIG_EAP_PEAP=y
+
+# EAP-GTC for the integrated EAP server
+CONFIG_EAP_GTC=y
+
+# EAP-TTLS for the integrated EAP server
+CONFIG_EAP_TTLS=y
+
+# EAP-SIM for the integrated EAP server
+#CONFIG_EAP_SIM=y
+
+# EAP-AKA for the integrated EAP server
+#CONFIG_EAP_AKA=y
+
+# EAP-AKA' for the integrated EAP server
+# This requires CONFIG_EAP_AKA to be enabled, too.
+#CONFIG_EAP_AKA_PRIME=y
+
+# EAP-PAX for the integrated EAP server
+#CONFIG_EAP_PAX=y
+
+# EAP-PSK for the integrated EAP server (this is _not_ needed for WPA-PSK)
+#CONFIG_EAP_PSK=y
+
+# EAP-SAKE for the integrated EAP server
+#CONFIG_EAP_SAKE=y
+
+# EAP-GPSK for the integrated EAP server
+#CONFIG_EAP_GPSK=y
+# Include support for optional SHA256 cipher suite in EAP-GPSK
+#CONFIG_EAP_GPSK_SHA256=y
+
+# EAP-FAST for the integrated EAP server
+# Note: Default OpenSSL package does not include support for all the
+# functionality needed for EAP-FAST. If EAP-FAST is enabled with OpenSSL,
+# the OpenSSL library must be patched (openssl-0.9.9-session-ticket.patch)
+# to add the needed functions.
+#CONFIG_EAP_FAST=y
+
+# Wi-Fi Protected Setup (WPS)
+CONFIG_WPS=y
+# Enable UPnP support for external WPS Registrars
+#CONFIG_WPS_UPNP=y
+
+# EAP-IKEv2
+#CONFIG_EAP_IKEV2=y
+
+# Trusted Network Connect (EAP-TNC)
+#CONFIG_EAP_TNC=y
+
+# PKCS#12 (PFX) support (used to read private key and certificate file from
+# a file that usually has extension .p12 or .pfx)
+CONFIG_PKCS12=y
+
+# RADIUS authentication server. This provides access to the integrated EAP
+# server from external hosts using RADIUS.
+CONFIG_RADIUS_SERVER=y
+
+# Build IPv6 support for RADIUS operations
+CONFIG_IPV6=y
+
+# IEEE Std 802.11r-2008 (Fast BSS Transition)
+#CONFIG_IEEE80211R=y
+
+# Use the hostapd's IEEE 802.11 authentication (ACL), but without
+# the IEEE 802.11 Management capability (e.g., madwifi or FreeBSD/net80211)
+CONFIG_DRIVER_RADIUS_ACL=y
+
+# IEEE 802.11n (High Throughput) support
+CONFIG_IEEE80211N=y
+
+# Remove debugging code that is printing out debug messages to stdout.
+# This can be used to reduce the size of the hostapd considerably if debugging
+# code is not needed.
+#CONFIG_NO_STDOUT_DEBUG=y
diff --git a/multitech/recipes/hostap/hostap-daemon-1.0/hostapd.conf b/multitech/recipes/hostap/hostap-daemon-1.0/hostapd.conf
new file mode 100644
index 0000000..27d9e46
--- /dev/null
+++ b/multitech/recipes/hostap/hostap-daemon-1.0/hostapd.conf
@@ -0,0 +1,1127 @@
+##### hostapd configuration file ##############################################
+# Empty lines and lines starting with # are ignored
+
+# AP netdevice name (without 'ap' postfix, i.e., wlan0 uses wlan0ap for
+# management frames); ath0 for madwifi
+interface=wlan0
+
+# In case of madwifi, atheros, and nl80211 driver interfaces, an additional
+# configuration parameter, bridge, may be used to notify hostapd if the
+# interface is included in a bridge. This parameter is not used with Host AP
+# driver. If the bridge parameter is not set, the drivers will automatically
+# figure out the bridge interface (assuming sysfs is enabled and mounted to
+# /sys) and this parameter may not be needed.
+#
+# For nl80211, this parameter can be used to request the AP interface to be
+# added to the bridge automatically (brctl may refuse to do this before hostapd
+# has been started to change the interface mode). If needed, the bridge
+# interface is also created.
+#bridge=br0
+
+# Driver interface type (hostap/wired/madwifi/test/none/nl80211/bsd);
+# default: hostap). nl80211 is used with all Linux mac80211 drivers.
+# Use driver=none if building hostapd as a standalone RADIUS server that does
+# not control any wireless/wired driver.
+driver=nl80211
+
+# hostapd event logger configuration
+#
+# Two output method: syslog and stdout (only usable if not forking to
+# background).
+#
+# Module bitfield (ORed bitfield of modules that will be logged; -1 = all
+# modules):
+# bit 0 (1) = IEEE 802.11
+# bit 1 (2) = IEEE 802.1X
+# bit 2 (4) = RADIUS
+# bit 3 (8) = WPA
+# bit 4 (16) = driver interface
+# bit 5 (32) = IAPP
+# bit 6 (64) = MLME
+#
+# Levels (minimum value for logged events):
+#  0 = verbose debugging
+#  1 = debugging
+#  2 = informational messages
+#  3 = notification
+#  4 = warning
+#
+logger_syslog=-1
+logger_syslog_level=2
+logger_stdout=-1
+logger_stdout_level=2
+
+# Dump file for state information (on SIGUSR1)
+dump_file=/tmp/hostapd.dump
+
+# Interface for separate control program. If this is specified, hostapd
+# will create this directory and a UNIX domain socket for listening to requests
+# from external programs (CLI/GUI, etc.) for status information and
+# configuration. The socket file will be named based on the interface name, so
+# multiple hostapd processes/interfaces can be run at the same time if more
+# than one interface is used.
+# /var/run/hostapd is the recommended directory for sockets and by default,
+# hostapd_cli will use it when trying to connect with hostapd.
+ctrl_interface=/var/run/hostapd
+
+# Access control for the control interface can be configured by setting the
+# directory to allow only members of a group to use sockets. This way, it is
+# possible to run hostapd as root (since it needs to change network
+# configuration and open raw sockets) and still allow GUI/CLI components to be
+# run as non-root users. However, since the control interface can be used to
+# change the network configuration, this access needs to be protected in many
+# cases. By default, hostapd is configured to use gid 0 (root). If you
+# want to allow non-root users to use the contron interface, add a new group
+# and change this value to match with that group. Add users that should have
+# control interface access to this group.
+#
+# This variable can be a group name or gid.
+#ctrl_interface_group=wheel
+ctrl_interface_group=0
+
+
+##### IEEE 802.11 related configuration #######################################
+
+# SSID to be used in IEEE 802.11 management frames
+ssid=test
+
+# Country code (ISO/IEC 3166-1). Used to set regulatory domain.
+# Set as needed to indicate country in which device is operating.
+# This can limit available channels and transmit power.
+#country_code=US
+
+# Enable IEEE 802.11d. This advertises the country_code and the set of allowed
+# channels and transmit power levels based on the regulatory limits. The
+# country_code setting must be configured with the correct country for
+# IEEE 802.11d functions.
+# (default: 0 = disabled)
+#ieee80211d=1
+
+# Operation mode (a = IEEE 802.11a, b = IEEE 802.11b, g = IEEE 802.11g,
+# Default: IEEE 802.11b
+hw_mode=g
+
+# Channel number (IEEE 802.11)
+# (default: 0, i.e., not set)
+# Please note that some drivers do not use this value from hostapd and the
+# channel will need to be configured separately with iwconfig.
+channel=1
+
+# Beacon interval in kus (1.024 ms) (default: 100; range 15..65535)
+beacon_int=100
+
+# DTIM (delivery traffic information message) period (range 1..255):
+# number of beacons between DTIMs (1 = every beacon includes DTIM element)
+# (default: 2)
+dtim_period=2
+
+# Maximum number of stations allowed in station table. New stations will be
+# rejected after the station table is full. IEEE 802.11 has a limit of 2007
+# different association IDs, so this number should not be larger than that.
+# (default: 2007)
+max_num_sta=255
+
+# RTS/CTS threshold; 2347 = disabled (default); range 0..2347
+# If this field is not included in hostapd.conf, hostapd will not control
+# RTS threshold and 'iwconfig wlan# rts <val>' can be used to set it.
+rts_threshold=2347
+
+# Fragmentation threshold; 2346 = disabled (default); range 256..2346
+# If this field is not included in hostapd.conf, hostapd will not control
+# fragmentation threshold and 'iwconfig wlan# frag <val>' can be used to set
+# it.
+fragm_threshold=2346
+
+# Rate configuration
+# Default is to enable all rates supported by the hardware. This configuration
+# item allows this list be filtered so that only the listed rates will be left
+# in the list. If the list is empty, all rates are used. This list can have
+# entries that are not in the list of rates the hardware supports (such entries
+# are ignored). The entries in this list are in 100 kbps, i.e., 11 Mbps = 110.
+# If this item is present, at least one rate have to be matching with the rates
+# hardware supports.
+# default: use the most common supported rate setting for the selected
+# hw_mode (i.e., this line can be removed from configuration file in most
+# cases)
+#supported_rates=10 20 55 110 60 90 120 180 240 360 480 540
+
+# Basic rate set configuration
+# List of rates (in 100 kbps) that are included in the basic rate set.
+# If this item is not included, usually reasonable default set is used.
+#basic_rates=10 20
+#basic_rates=10 20 55 110
+#basic_rates=60 120 240
+
+# Short Preamble
+# This parameter can be used to enable optional use of short preamble for
+# frames sent at 2 Mbps, 5.5 Mbps, and 11 Mbps to improve network performance.
+# This applies only to IEEE 802.11b-compatible networks and this should only be
+# enabled if the local hardware supports use of short preamble. If any of the
+# associated STAs do not support short preamble, use of short preamble will be
+# disabled (and enabled when such STAs disassociate) dynamically.
+# 0 = do not allow use of short preamble (default)
+# 1 = allow use of short preamble
+#preamble=1
+
+# Station MAC address -based authentication
+# Please note that this kind of access control requires a driver that uses
+# hostapd to take care of management frame processing and as such, this can be
+# used with driver=hostap or driver=nl80211, but not with driver=madwifi.
+# 0 = accept unless in deny list
+# 1 = deny unless in accept list
+# 2 = use external RADIUS server (accept/deny lists are searched first)
+macaddr_acl=0
+
+# Accept/deny lists are read from separate files (containing list of
+# MAC addresses, one per line). Use absolute path name to make sure that the
+# files can be read on SIGHUP configuration reloads.
+#accept_mac_file=/etc/hostapd.accept
+#deny_mac_file=/etc/hostapd.deny
+
+# IEEE 802.11 specifies two authentication algorithms. hostapd can be
+# configured to allow both of these or only one. Open system authentication
+# should be used with IEEE 802.1X.
+# Bit fields of allowed authentication algorithms:
+# bit 0 = Open System Authentication
+# bit 1 = Shared Key Authentication (requires WEP)
+auth_algs=3
+
+# Send empty SSID in beacons and ignore probe request frames that do not
+# specify full SSID, i.e., require stations to know SSID.
+# default: disabled (0)
+# 1 = send empty (length=0) SSID in beacon and ignore probe request for
+#     broadcast SSID
+# 2 = clear SSID (ASCII 0), but keep the original length (this may be required
+#     with some clients that do not support empty SSID) and ignore probe
+#     requests for broadcast SSID
+ignore_broadcast_ssid=0
+
+# TX queue parameters (EDCF / bursting)
+# tx_queue_<queue name>_<param>
+# queues: data0, data1, data2, data3, after_beacon, beacon
+#		(data0 is the highest priority queue)
+# parameters:
+#   aifs: AIFS (default 2)
+#   cwmin: cwMin (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023)
+#   cwmax: cwMax (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023); cwMax >= cwMin
+#   burst: maximum length (in milliseconds with precision of up to 0.1 ms) for
+#          bursting
+#
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# These parameters are used by the access point when transmitting frames
+# to the clients.
+#
+# Low priority / AC_BK = background
+#tx_queue_data3_aifs=7
+#tx_queue_data3_cwmin=15
+#tx_queue_data3_cwmax=1023
+#tx_queue_data3_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=1023 burst=0
+#
+# Normal priority / AC_BE = best effort
+#tx_queue_data2_aifs=3
+#tx_queue_data2_cwmin=15
+#tx_queue_data2_cwmax=63
+#tx_queue_data2_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=127 burst=0
+#
+# High priority / AC_VI = video
+#tx_queue_data1_aifs=1
+#tx_queue_data1_cwmin=7
+#tx_queue_data1_cwmax=15
+#tx_queue_data1_burst=3.0
+# Note: for IEEE 802.11b mode: cWmin=15 cWmax=31 burst=6.0
+#
+# Highest priority / AC_VO = voice
+#tx_queue_data0_aifs=1
+#tx_queue_data0_cwmin=3
+#tx_queue_data0_cwmax=7
+#tx_queue_data0_burst=1.5
+# Note: for IEEE 802.11b mode: cWmin=7 cWmax=15 burst=3.3
+
+# 802.1D Tag (= UP) to AC mappings
+# WMM specifies following mapping of data frames to different ACs. This mapping
+# can be configured using Linux QoS/tc and sch_pktpri.o module.
+# 802.1D Tag	802.1D Designation	Access Category	WMM Designation
+# 1		BK			AC_BK		Background
+# 2		-			AC_BK		Background
+# 0		BE			AC_BE		Best Effort
+# 3		EE			AC_BE		Best Effort
+# 4		CL			AC_VI		Video
+# 5		VI			AC_VI		Video
+# 6		VO			AC_VO		Voice
+# 7		NC			AC_VO		Voice
+# Data frames with no priority information: AC_BE
+# Management frames: AC_VO
+# PS-Poll frames: AC_BE
+
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# for 802.11a or 802.11g networks
+# These parameters are sent to WMM clients when they associate.
+# The parameters will be used by WMM clients for frames transmitted to the
+# access point.
+#
+# note - txop_limit is in units of 32microseconds
+# note - acm is admission control mandatory flag. 0 = admission control not
+# required, 1 = mandatory
+# note - here cwMin and cmMax are in exponent form. the actual cw value used
+# will be (2^n)-1 where n is the value given here
+#
+wmm_enabled=1
+#
+# WMM-PS Unscheduled Automatic Power Save Delivery [U-APSD]
+# Enable this flag if U-APSD supported outside hostapd (eg., Firmware/driver)
+#uapsd_advertisement_enabled=1
+#
+# Low priority / AC_BK = background
+wmm_ac_bk_cwmin=4
+wmm_ac_bk_cwmax=10
+wmm_ac_bk_aifs=7
+wmm_ac_bk_txop_limit=0
+wmm_ac_bk_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=10
+#
+# Normal priority / AC_BE = best effort
+wmm_ac_be_aifs=3
+wmm_ac_be_cwmin=4
+wmm_ac_be_cwmax=10
+wmm_ac_be_txop_limit=0
+wmm_ac_be_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=7
+#
+# High priority / AC_VI = video
+wmm_ac_vi_aifs=2
+wmm_ac_vi_cwmin=3
+wmm_ac_vi_cwmax=4
+wmm_ac_vi_txop_limit=94
+wmm_ac_vi_acm=0
+# Note: for IEEE 802.11b mode: cWmin=4 cWmax=5 txop_limit=188
+#
+# Highest priority / AC_VO = voice
+wmm_ac_vo_aifs=2
+wmm_ac_vo_cwmin=2
+wmm_ac_vo_cwmax=3
+wmm_ac_vo_txop_limit=47
+wmm_ac_vo_acm=0
+# Note: for IEEE 802.11b mode: cWmin=3 cWmax=4 burst=102
+
+# Static WEP key configuration
+#
+# The key number to use when transmitting.
+# It must be between 0 and 3, and the corresponding key must be set.
+# default: not set
+#wep_default_key=0
+# The WEP keys to use.
+# A key may be a quoted string or unquoted hexadecimal digits.
+# The key length should be 5, 13, or 16 characters, or 10, 26, or 32
+# digits, depending on whether 40-bit (64-bit), 104-bit (128-bit), or
+# 128-bit (152-bit) WEP is used.
+# Only the default key must be supplied; the others are optional.
+# default: not set
+#wep_key0=123456789a
+#wep_key1="vwxyz"
+#wep_key2=0102030405060708090a0b0c0d
+#wep_key3=".2.4.6.8.0.23"
+
+# Station inactivity limit
+#
+# If a station does not send anything in ap_max_inactivity seconds, an
+# empty data frame is sent to it in order to verify whether it is
+# still in range. If this frame is not ACKed, the station will be
+# disassociated and then deauthenticated. This feature is used to
+# clear station table of old entries when the STAs move out of the
+# range.
+#
+# The station can associate again with the AP if it is still in range;
+# this inactivity poll is just used as a nicer way of verifying
+# inactivity; i.e., client will not report broken connection because
+# disassociation frame is not sent immediately without first polling
+# the STA with a data frame.
+# default: 300 (i.e., 5 minutes)
+#ap_max_inactivity=300
+
+# Disassociate stations based on excessive transmission failures or other
+# indications of connection loss. This depends on the driver capabilities and
+# may not be available with all drivers.
+#disassoc_low_ack=1
+
+# Maximum allowed Listen Interval (how many Beacon periods STAs are allowed to
+# remain asleep). Default: 65535 (no limit apart from field size)
+#max_listen_interval=100
+
+# WDS (4-address frame) mode with per-station virtual interfaces
+# (only supported with driver=nl80211)
+# This mode allows associated stations to use 4-address frames to allow layer 2
+# bridging to be used.
+#wds_sta=1
+
+# If bridge parameter is set, the WDS STA interface will be added to the same
+# bridge by default. This can be overridden with the wds_bridge parameter to
+# use a separate bridge.
+#wds_bridge=wds-br0
+
+# Client isolation can be used to prevent low-level bridging of frames between
+# associated stations in the BSS. By default, this bridging is allowed.
+#ap_isolate=1
+
+##### IEEE 802.11n related configuration ######################################
+
+# ieee80211n: Whether IEEE 802.11n (HT) is enabled
+# 0 = disabled (default)
+# 1 = enabled
+# Note: You will also need to enable WMM for full HT functionality.
+#ieee80211n=1
+
+# ht_capab: HT capabilities (list of flags)
+# LDPC coding capability: [LDPC] = supported
+# Supported channel width set: [HT40-] = both 20 MHz and 40 MHz with secondary
+#	channel below the primary channel; [HT40+] = both 20 MHz and 40 MHz
+#	with secondary channel below the primary channel
+#	(20 MHz only if neither is set)
+#	Note: There are limits on which channels can be used with HT40- and
+#	HT40+. Following table shows the channels that may be available for
+#	HT40- and HT40+ use per IEEE 802.11n Annex J:
+#	freq		HT40-		HT40+
+#	2.4 GHz		5-13		1-7 (1-9 in Europe/Japan)
+#	5 GHz		40,48,56,64	36,44,52,60
+#	(depending on the location, not all of these channels may be available
+#	for use)
+#	Please note that 40 MHz channels may switch their primary and secondary
+#	channels if needed or creation of 40 MHz channel maybe rejected based
+#	on overlapping BSSes. These changes are done automatically when hostapd
+#	is setting up the 40 MHz channel.
+# Spatial Multiplexing (SM) Power Save: [SMPS-STATIC] or [SMPS-DYNAMIC]
+#	(SMPS disabled if neither is set)
+# HT-greenfield: [GF] (disabled if not set)
+# Short GI for 20 MHz: [SHORT-GI-20] (disabled if not set)
+# Short GI for 40 MHz: [SHORT-GI-40] (disabled if not set)
+# Tx STBC: [TX-STBC] (disabled if not set)
+# Rx STBC: [RX-STBC1] (one spatial stream), [RX-STBC12] (one or two spatial
+#	streams), or [RX-STBC123] (one, two, or three spatial streams); Rx STBC
+#	disabled if none of these set
+# HT-delayed Block Ack: [DELAYED-BA] (disabled if not set)
+# Maximum A-MSDU length: [MAX-AMSDU-7935] for 7935 octets (3839 octets if not
+#	set)
+# DSSS/CCK Mode in 40 MHz: [DSSS_CCK-40] = allowed (not allowed if not set)
+# PSMP support: [PSMP] (disabled if not set)
+# L-SIG TXOP protection support: [LSIG-TXOP-PROT] (disabled if not set)
+#ht_capab=[HT40-][SHORT-GI-20][SHORT-GI-40]
+
+# Require stations to support HT PHY (reject association if they do not)
+#require_ht=1
+
+##### IEEE 802.1X-2004 related configuration ##################################
+
+# Require IEEE 802.1X authorization
+#ieee8021x=1
+
+# IEEE 802.1X/EAPOL version
+# hostapd is implemented based on IEEE Std 802.1X-2004 which defines EAPOL
+# version 2. However, there are many client implementations that do not handle
+# the new version number correctly (they seem to drop the frames completely).
+# In order to make hostapd interoperate with these clients, the version number
+# can be set to the older version (1) with this configuration value.
+#eapol_version=2
+
+# Optional displayable message sent with EAP Request-Identity. The first \0
+# in this string will be converted to ASCII-0 (nul). This can be used to
+# separate network info (comma separated list of attribute=value pairs); see,
+# e.g., RFC 4284.
+#eap_message=hello
+#eap_message=hello\0networkid=netw,nasid=foo,portid=0,NAIRealms=example.com
+
+# WEP rekeying (disabled if key lengths are not set or are set to 0)
+# Key lengths for default/broadcast and individual/unicast keys:
+# 5 = 40-bit WEP (also known as 64-bit WEP with 40 secret bits)
+# 13 = 104-bit WEP (also known as 128-bit WEP with 104 secret bits)
+#wep_key_len_broadcast=5
+#wep_key_len_unicast=5
+# Rekeying period in seconds. 0 = do not rekey (i.e., set keys only once)
+#wep_rekey_period=300
+
+# EAPOL-Key index workaround (set bit7) for WinXP Supplicant (needed only if
+# only broadcast keys are used)
+eapol_key_index_workaround=0
+
+# EAP reauthentication period in seconds (default: 3600 seconds; 0 = disable
+# reauthentication).
+#eap_reauth_period=3600
+
+# Use PAE group address (01:80:c2:00:00:03) instead of individual target
+# address when sending EAPOL frames with driver=wired. This is the most common
+# mechanism used in wired authentication, but it also requires that the port
+# is only used by one station.
+#use_pae_group_addr=1
+
+##### Integrated EAP server ###################################################
+
+# Optionally, hostapd can be configured to use an integrated EAP server
+# to process EAP authentication locally without need for an external RADIUS
+# server. This functionality can be used both as a local authentication server
+# for IEEE 802.1X/EAPOL and as a RADIUS server for other devices.
+
+# Use integrated EAP server instead of external RADIUS authentication
+# server. This is also needed if hostapd is configured to act as a RADIUS
+# authentication server.
+eap_server=0
+
+# Path for EAP server user database
+#eap_user_file=/etc/hostapd.eap_user
+
+# CA certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#ca_cert=/etc/hostapd.ca.pem
+
+# Server certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#server_cert=/etc/hostapd.server.pem
+
+# Private key matching with the server certificate for EAP-TLS/PEAP/TTLS
+# This may point to the same file as server_cert if both certificate and key
+# are included in a single file. PKCS#12 (PFX) file (.p12/.pfx) can also be
+# used by commenting out server_cert and specifying the PFX file as the
+# private_key.
+#private_key=/etc/hostapd.server.prv
+
+# Passphrase for private key
+#private_key_passwd=secret passphrase
+
+# Enable CRL verification.
+# Note: hostapd does not yet support CRL downloading based on CDP. Thus, a
+# valid CRL signed by the CA is required to be included in the ca_cert file.
+# This can be done by using PEM format for CA certificate and CRL and
+# concatenating these into one file. Whenever CRL changes, hostapd needs to be
+# restarted to take the new CRL into use.
+# 0 = do not verify CRLs (default)
+# 1 = check the CRL of the user certificate
+# 2 = check all CRLs in the certificate path
+#check_crl=1
+
+# dh_file: File path to DH/DSA parameters file (in PEM format)
+# This is an optional configuration file for setting parameters for an
+# ephemeral DH key exchange. In most cases, the default RSA authentication does
+# not use this configuration. However, it is possible setup RSA to use
+# ephemeral DH key exchange. In addition, ciphers with DSA keys always use
+# ephemeral DH keys. This can be used to achieve forward secrecy. If the file
+# is in DSA parameters format, it will be automatically converted into DH
+# params. This parameter is required if anonymous EAP-FAST is used.
+# You can generate DH parameters file with OpenSSL, e.g.,
+# "openssl dhparam -out /etc/hostapd.dh.pem 1024"
+#dh_file=/etc/hostapd.dh.pem
+
+# Fragment size for EAP methods
+#fragment_size=1400
+
+# Configuration data for EAP-SIM database/authentication gateway interface.
+# This is a text string in implementation specific format. The example
+# implementation in eap_sim_db.c uses this as the UNIX domain socket name for
+# the HLR/AuC gateway (e.g., hlr_auc_gw). In this case, the path uses "unix:"
+# prefix.
+#eap_sim_db=unix:/tmp/hlr_auc_gw.sock
+
+# Encryption key for EAP-FAST PAC-Opaque values. This key must be a secret,
+# random value. It is configured as a 16-octet value in hex format. It can be
+# generated, e.g., with the following command:
+# od -tx1 -v -N16 /dev/random | colrm 1 8 | tr -d ' '
+#pac_opaque_encr_key=000102030405060708090a0b0c0d0e0f
+
+# EAP-FAST authority identity (A-ID)
+# A-ID indicates the identity of the authority that issues PACs. The A-ID
+# should be unique across all issuing servers. In theory, this is a variable
+# length field, but due to some existing implementations requiring A-ID to be
+# 16 octets in length, it is strongly recommended to use that length for the
+# field to provid interoperability with deployed peer implementations. This
+# field is configured in hex format.
+#eap_fast_a_id=101112131415161718191a1b1c1d1e1f
+
+# EAP-FAST authority identifier information (A-ID-Info)
+# This is a user-friendly name for the A-ID. For example, the enterprise name
+# and server name in a human-readable format. This field is encoded as UTF-8.
+#eap_fast_a_id_info=test server
+
+# Enable/disable different EAP-FAST provisioning modes:
+#0 = provisioning disabled
+#1 = only anonymous provisioning allowed
+#2 = only authenticated provisioning allowed
+#3 = both provisioning modes allowed (default)
+#eap_fast_prov=3
+
+# EAP-FAST PAC-Key lifetime in seconds (hard limit)
+#pac_key_lifetime=604800
+
+# EAP-FAST PAC-Key refresh time in seconds (soft limit on remaining hard
+# limit). The server will generate a new PAC-Key when this number of seconds
+# (or fewer) of the lifetime remains.
+#pac_key_refresh_time=86400
+
+# EAP-SIM and EAP-AKA protected success/failure indication using AT_RESULT_IND
+# (default: 0 = disabled).
+#eap_sim_aka_result_ind=1
+
+# Trusted Network Connect (TNC)
+# If enabled, TNC validation will be required before the peer is allowed to
+# connect. Note: This is only used with EAP-TTLS and EAP-FAST. If any other
+# EAP method is enabled, the peer will be allowed to connect without TNC.
+#tnc=1
+
+
+##### IEEE 802.11f - Inter-Access Point Protocol (IAPP) #######################
+
+# Interface to be used for IAPP broadcast packets
+#iapp_interface=eth0
+
+
+##### RADIUS client configuration #############################################
+# for IEEE 802.1X with external Authentication Server, IEEE 802.11
+# authentication with external ACL for MAC addresses, and accounting
+
+# The own IP address of the access point (used as NAS-IP-Address)
+own_ip_addr=127.0.0.1
+
+# Optional NAS-Identifier string for RADIUS messages. When used, this should be
+# a unique to the NAS within the scope of the RADIUS server. For example, a
+# fully qualified domain name can be used here.
+# When using IEEE 802.11r, nas_identifier must be set and must be between 1 and
+# 48 octets long.
+#nas_identifier=ap.example.com
+
+# RADIUS authentication server
+#auth_server_addr=127.0.0.1
+#auth_server_port=1812
+#auth_server_shared_secret=secret
+
+# RADIUS accounting server
+#acct_server_addr=127.0.0.1
+#acct_server_port=1813
+#acct_server_shared_secret=secret
+
+# Secondary RADIUS servers; to be used if primary one does not reply to
+# RADIUS packets. These are optional and there can be more than one secondary
+# server listed.
+#auth_server_addr=127.0.0.2
+#auth_server_port=1812
+#auth_server_shared_secret=secret2
+#
+#acct_server_addr=127.0.0.2
+#acct_server_port=1813
+#acct_server_shared_secret=secret2
+
+# Retry interval for trying to return to the primary RADIUS server (in
+# seconds). RADIUS client code will automatically try to use the next server
+# when the current server is not replying to requests. If this interval is set,
+# primary server will be retried after configured amount of time even if the
+# currently used secondary server is still working.
+#radius_retry_primary_interval=600
+
+
+# Interim accounting update interval
+# If this is set (larger than 0) and acct_server is configured, hostapd will
+# send interim accounting updates every N seconds. Note: if set, this overrides
+# possible Acct-Interim-Interval attribute in Access-Accept message. Thus, this
+# value should not be configured in hostapd.conf, if RADIUS server is used to
+# control the interim interval.
+# This value should not be less 600 (10 minutes) and must not be less than
+# 60 (1 minute).
+#radius_acct_interim_interval=600
+
+# Dynamic VLAN mode; allow RADIUS authentication server to decide which VLAN
+# is used for the stations. This information is parsed from following RADIUS
+# attributes based on RFC 3580 and RFC 2868: Tunnel-Type (value 13 = VLAN),
+# Tunnel-Medium-Type (value 6 = IEEE 802), Tunnel-Private-Group-ID (value
+# VLANID as a string). vlan_file option below must be configured if dynamic
+# VLANs are used. Optionally, the local MAC ACL list (accept_mac_file) can be
+# used to set static client MAC address to VLAN ID mapping.
+# 0 = disabled (default)
+# 1 = option; use default interface if RADIUS server does not include VLAN ID
+# 2 = required; reject authentication if RADIUS server does not include VLAN ID
+#dynamic_vlan=0
+
+# VLAN interface list for dynamic VLAN mode is read from a separate text file.
+# This list is used to map VLAN ID from the RADIUS server to a network
+# interface. Each station is bound to one interface in the same way as with
+# multiple BSSIDs or SSIDs. Each line in this text file is defining a new
+# interface and the line must include VLAN ID and interface name separated by
+# white space (space or tab).
+#vlan_file=/etc/hostapd.vlan
+
+# Interface where 802.1q tagged packets should appear when a RADIUS server is
+# used to determine which VLAN a station is on.  hostapd creates a bridge for
+# each VLAN.  Then hostapd adds a VLAN interface (associated with the interface
+# indicated by 'vlan_tagged_interface') and the appropriate wireless interface
+# to the bridge.
+#vlan_tagged_interface=eth0
+
+
+##### RADIUS authentication server configuration ##############################
+
+# hostapd can be used as a RADIUS authentication server for other hosts. This
+# requires that the integrated EAP server is also enabled and both
+# authentication services are sharing the same configuration.
+
+# File name of the RADIUS clients configuration for the RADIUS server. If this
+# commented out, RADIUS server is disabled.
+#radius_server_clients=/etc/hostapd.radius_clients
+
+# The UDP port number for the RADIUS authentication server
+#radius_server_auth_port=1812
+
+# Use IPv6 with RADIUS server (IPv4 will also be supported using IPv6 API)
+#radius_server_ipv6=1
+
+
+##### WPA/IEEE 802.11i configuration ##########################################
+
+# Enable WPA. Setting this variable configures the AP to require WPA (either
+# WPA-PSK or WPA-RADIUS/EAP based on other configuration). For WPA-PSK, either
+# wpa_psk or wpa_passphrase must be set and wpa_key_mgmt must include WPA-PSK.
+# For WPA-RADIUS/EAP, ieee8021x must be set (but without dynamic WEP keys),
+# RADIUS authentication server must be configured, and WPA-EAP must be included
+# in wpa_key_mgmt.
+# This field is a bit field that can be used to enable WPA (IEEE 802.11i/D3.0)
+# and/or WPA2 (full IEEE 802.11i/RSN):
+# bit0 = WPA
+# bit1 = IEEE 802.11i/RSN (WPA2) (dot11RSNAEnabled)
+#wpa=1
+
+# WPA pre-shared keys for WPA-PSK. This can be either entered as a 256-bit
+# secret in hex format (64 hex digits), wpa_psk, or as an ASCII passphrase
+# (8..63 characters) that will be converted to PSK. This conversion uses SSID
+# so the PSK changes when ASCII passphrase is used and the SSID is changed.
+# wpa_psk (dot11RSNAConfigPSKValue)
+# wpa_passphrase (dot11RSNAConfigPSKPassPhrase)
+#wpa_psk=0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef
+#wpa_passphrase=secret passphrase
+
+# Optionally, WPA PSKs can be read from a separate text file (containing list
+# of (PSK,MAC address) pairs. This allows more than one PSK to be configured.
+# Use absolute path name to make sure that the files can be read on SIGHUP
+# configuration reloads.
+#wpa_psk_file=/etc/hostapd.wpa_psk
+
+# Set of accepted key management algorithms (WPA-PSK, WPA-EAP, or both). The
+# entries are separated with a space. WPA-PSK-SHA256 and WPA-EAP-SHA256 can be
+# added to enable SHA256-based stronger algorithms.
+# (dot11RSNAConfigAuthenticationSuitesTable)
+#wpa_key_mgmt=WPA-PSK WPA-EAP
+
+# Set of accepted cipher suites (encryption algorithms) for pairwise keys
+# (unicast packets). This is a space separated list of algorithms:
+# CCMP = AES in Counter mode with CBC-MAC [RFC 3610, IEEE 802.11i/D7.0]
+# TKIP = Temporal Key Integrity Protocol [IEEE 802.11i/D7.0]
+# Group cipher suite (encryption algorithm for broadcast and multicast frames)
+# is automatically selected based on this configuration. If only CCMP is
+# allowed as the pairwise cipher, group cipher will also be CCMP. Otherwise,
+# TKIP will be used as the group cipher.
+# (dot11RSNAConfigPairwiseCiphersTable)
+# Pairwise cipher for WPA (v1) (default: TKIP)
+#wpa_pairwise=TKIP CCMP
+# Pairwise cipher for RSN/WPA2 (default: use wpa_pairwise value)
+#rsn_pairwise=CCMP
+
+# Time interval for rekeying GTK (broadcast/multicast encryption keys) in
+# seconds. (dot11RSNAConfigGroupRekeyTime)
+#wpa_group_rekey=600
+
+# Rekey GTK when any STA that possesses the current GTK is leaving the BSS.
+# (dot11RSNAConfigGroupRekeyStrict)
+#wpa_strict_rekey=1
+
+# Time interval for rekeying GMK (master key used internally to generate GTKs
+# (in seconds).
+#wpa_gmk_rekey=86400
+
+# Maximum lifetime for PTK in seconds. This can be used to enforce rekeying of
+# PTK to mitigate some attacks against TKIP deficiencies.
+#wpa_ptk_rekey=600
+
+# Enable IEEE 802.11i/RSN/WPA2 pre-authentication. This is used to speed up
+# roaming be pre-authenticating IEEE 802.1X/EAP part of the full RSN
+# authentication and key handshake before actually associating with a new AP.
+# (dot11RSNAPreauthenticationEnabled)
+#rsn_preauth=1
+#
+# Space separated list of interfaces from which pre-authentication frames are
+# accepted (e.g., 'eth0' or 'eth0 wlan0wds0'. This list should include all
+# interface that are used for connections to other APs. This could include
+# wired interfaces and WDS links. The normal wireless data interface towards
+# associated stations (e.g., wlan0) should not be added, since
+# pre-authentication is only used with APs other than the currently associated
+# one.
+#rsn_preauth_interfaces=eth0
+
+# peerkey: Whether PeerKey negotiation for direct links (IEEE 802.11e) is
+# allowed. This is only used with RSN/WPA2.
+# 0 = disabled (default)
+# 1 = enabled
+#peerkey=1
+
+# ieee80211w: Whether management frame protection (MFP) is enabled
+# 0 = disabled (default)
+# 1 = optional
+# 2 = required
+#ieee80211w=0
+
+# Association SA Query maximum timeout (in TU = 1.024 ms; for MFP)
+# (maximum time to wait for a SA Query response)
+# dot11AssociationSAQueryMaximumTimeout, 1...4294967295
+#assoc_sa_query_max_timeout=1000
+
+# Association SA Query retry timeout (in TU = 1.024 ms; for MFP)
+# (time between two subsequent SA Query requests)
+# dot11AssociationSAQueryRetryTimeout, 1...4294967295
+#assoc_sa_query_retry_timeout=201
+
+# disable_pmksa_caching: Disable PMKSA caching
+# This parameter can be used to disable caching of PMKSA created through EAP
+# authentication. RSN preauthentication may still end up using PMKSA caching if
+# it is enabled (rsn_preauth=1).
+# 0 = PMKSA caching enabled (default)
+# 1 = PMKSA caching disabled
+#disable_pmksa_caching=0
+
+# okc: Opportunistic Key Caching (aka Proactive Key Caching)
+# Allow PMK cache to be shared opportunistically among configured interfaces
+# and BSSes (i.e., all configurations within a single hostapd process).
+# 0 = disabled (default)
+# 1 = enabled
+#okc=1
+
+
+##### IEEE 802.11r configuration ##############################################
+
+# Mobility Domain identifier (dot11FTMobilityDomainID, MDID)
+# MDID is used to indicate a group of APs (within an ESS, i.e., sharing the
+# same SSID) between which a STA can use Fast BSS Transition.
+# 2-octet identifier as a hex string.
+#mobility_domain=a1b2
+
+# PMK-R0 Key Holder identifier (dot11FTR0KeyHolderID)
+# 1 to 48 octet identifier.
+# This is configured with nas_identifier (see RADIUS client section above).
+
+# Default lifetime of the PMK-RO in minutes; range 1..65535
+# (dot11FTR0KeyLifetime)
+#r0_key_lifetime=10000
+
+# PMK-R1 Key Holder identifier (dot11FTR1KeyHolderID)
+# 6-octet identifier as a hex string.
+#r1_key_holder=000102030405
+
+# Reassociation deadline in time units (TUs / 1.024 ms; range 1000..65535)
+# (dot11FTReassociationDeadline)
+#reassociation_deadline=1000
+
+# List of R0KHs in the same Mobility Domain
+# format: <MAC address> <NAS Identifier> <128-bit key as hex string>
+# This list is used to map R0KH-ID (NAS Identifier) to a destination MAC
+# address when requesting PMK-R1 key from the R0KH that the STA used during the
+# Initial Mobility Domain Association.
+#r0kh=02:01:02:03:04:05 r0kh-1.example.com 000102030405060708090a0b0c0d0e0f
+#r0kh=02:01:02:03:04:06 r0kh-2.example.com 00112233445566778899aabbccddeeff
+# And so on.. One line per R0KH.
+
+# List of R1KHs in the same Mobility Domain
+# format: <MAC address> <R1KH-ID> <128-bit key as hex string>
+# This list is used to map R1KH-ID to a destination MAC address when sending
+# PMK-R1 key from the R0KH. This is also the list of authorized R1KHs in the MD
+# that can request PMK-R1 keys.
+#r1kh=02:01:02:03:04:05 02:11:22:33:44:55 000102030405060708090a0b0c0d0e0f
+#r1kh=02:01:02:03:04:06 02:11:22:33:44:66 00112233445566778899aabbccddeeff
+# And so on.. One line per R1KH.
+
+# Whether PMK-R1 push is enabled at R0KH
+# 0 = do not push PMK-R1 to all configured R1KHs (default)
+# 1 = push PMK-R1 to all configured R1KHs whenever a new PMK-R0 is derived
+#pmk_r1_push=1
+
+##### Neighbor table ##########################################################
+# Maximum number of entries kept in AP table (either for neigbor table or for
+# detecting Overlapping Legacy BSS Condition). The oldest entry will be
+# removed when adding a new entry that would make the list grow over this
+# limit. Note! WFA certification for IEEE 802.11g requires that OLBC is
+# enabled, so this field should not be set to 0 when using IEEE 802.11g.
+# default: 255
+#ap_table_max_size=255
+
+# Number of seconds of no frames received after which entries may be deleted
+# from the AP table. Since passive scanning is not usually performed frequently
+# this should not be set to very small value. In addition, there is no
+# guarantee that every scan cycle will receive beacon frames from the
+# neighboring APs.
+# default: 60
+#ap_table_expiration_time=3600
+
+
+##### Wi-Fi Protected Setup (WPS) #############################################
+
+# WPS state
+# 0 = WPS disabled (default)
+# 1 = WPS enabled, not configured
+# 2 = WPS enabled, configured
+#wps_state=2
+
+# AP can be configured into a locked state where new WPS Registrar are not
+# accepted, but previously authorized Registrars (including the internal one)
+# can continue to add new Enrollees.
+#ap_setup_locked=1
+
+# Universally Unique IDentifier (UUID; see RFC 4122) of the device
+# This value is used as the UUID for the internal WPS Registrar. If the AP
+# is also using UPnP, this value should be set to the device's UPnP UUID.
+# If not configured, UUID will be generated based on the local MAC address.
+#uuid=12345678-9abc-def0-1234-56789abcdef0
+
+# Note: If wpa_psk_file is set, WPS is used to generate random, per-device PSKs
+# that will be appended to the wpa_psk_file. If wpa_psk_file is not set, the
+# default PSK (wpa_psk/wpa_passphrase) will be delivered to Enrollees. Use of
+# per-device PSKs is recommended as the more secure option (i.e., make sure to
+# set wpa_psk_file when using WPS with WPA-PSK).
+
+# When an Enrollee requests access to the network with PIN method, the Enrollee
+# PIN will need to be entered for the Registrar. PIN request notifications are
+# sent to hostapd ctrl_iface monitor. In addition, they can be written to a
+# text file that could be used, e.g., to populate the AP administration UI with
+# pending PIN requests. If the following variable is set, the PIN requests will
+# be written to the configured file.
+#wps_pin_requests=/var/run/hostapd_wps_pin_requests
+
+# Device Name
+# User-friendly description of device; up to 32 octets encoded in UTF-8
+#device_name=Wireless AP
+
+# Manufacturer
+# The manufacturer of the device (up to 64 ASCII characters)
+#manufacturer=Company
+
+# Model Name
+# Model of the device (up to 32 ASCII characters)
+#model_name=WAP
+
+# Model Number
+# Additional device description (up to 32 ASCII characters)
+#model_number=123
+
+# Serial Number
+# Serial number of the device (up to 32 characters)
+#serial_number=12345
+
+# Primary Device Type
+# Used format: <categ>-<OUI>-<subcateg>
+# categ = Category as an integer value
+# OUI = OUI and type octet as a 4-octet hex-encoded value; 0050F204 for
+#       default WPS OUI
+# subcateg = OUI-specific Sub Category as an integer value
+# Examples:
+#   1-0050F204-1 (Computer / PC)
+#   1-0050F204-2 (Computer / Server)
+#   5-0050F204-1 (Storage / NAS)
+#   6-0050F204-1 (Network Infrastructure / AP)
+#device_type=6-0050F204-1
+
+# OS Version
+# 4-octet operating system version number (hex string)
+#os_version=01020300
+
+# Config Methods
+# List of the supported configuration methods
+# Available methods: usba ethernet label display ext_nfc_token int_nfc_token
+#	nfc_interface push_button keypad virtual_display physical_display
+#	virtual_push_button physical_push_button
+#config_methods=label virtual_display virtual_push_button keypad
+
+# WPS capability discovery workaround for PBC with Windows 7
+# Windows 7 uses incorrect way of figuring out AP's WPS capabilities by acting
+# as a Registrar and using M1 from the AP. The config methods attribute in that
+# message is supposed to indicate only the configuration method supported by
+# the AP in Enrollee role, i.e., to add an external Registrar. For that case,
+# PBC shall not be used and as such, the PushButton config method is removed
+# from M1 by default. If pbc_in_m1=1 is included in the configuration file,
+# the PushButton config method is left in M1 (if included in config_methods
+# parameter) to allow Windows 7 to use PBC instead of PIN (e.g., from a label
+# in the AP).
+#pbc_in_m1=1
+
+# Static access point PIN for initial configuration and adding Registrars
+# If not set, hostapd will not allow external WPS Registrars to control the
+# access point. The AP PIN can also be set at runtime with hostapd_cli
+# wps_ap_pin command. Use of temporary (enabled by user action) and random
+# AP PIN is much more secure than configuring a static AP PIN here. As such,
+# use of the ap_pin parameter is not recommended if the AP device has means for
+# displaying a random PIN.
+#ap_pin=12345670
+
+# Skip building of automatic WPS credential
+# This can be used to allow the automatically generated Credential attribute to
+# be replaced with pre-configured Credential(s).
+#skip_cred_build=1
+
+# Additional Credential attribute(s)
+# This option can be used to add pre-configured Credential attributes into M8
+# message when acting as a Registrar. If skip_cred_build=1, this data will also
+# be able to override the Credential attribute that would have otherwise been
+# automatically generated based on network configuration. This configuration
+# option points to an external file that much contain the WPS Credential
+# attribute(s) as binary data.
+#extra_cred=hostapd.cred
+
+# Credential processing
+#   0 = process received credentials internally (default)
+#   1 = do not process received credentials; just pass them over ctrl_iface to
+#	external program(s)
+#   2 = process received credentials internally and pass them over ctrl_iface
+#	to external program(s)
+# Note: With wps_cred_processing=1, skip_cred_build should be set to 1 and
+# extra_cred be used to provide the Credential data for Enrollees.
+#
+# wps_cred_processing=1 will disabled automatic updates of hostapd.conf file
+# both for Credential processing and for marking AP Setup Locked based on
+# validation failures of AP PIN. An external program is responsible on updating
+# the configuration appropriately in this case.
+#wps_cred_processing=0
+
+# AP Settings Attributes for M7
+# By default, hostapd generates the AP Settings Attributes for M7 based on the
+# current configuration. It is possible to override this by providing a file
+# with pre-configured attributes. This is similar to extra_cred file format,
+# but the AP Settings attributes are not encapsulated in a Credential
+# attribute.
+#ap_settings=hostapd.ap_settings
+
+# WPS UPnP interface
+# If set, support for external Registrars is enabled.
+#upnp_iface=br0
+
+# Friendly Name (required for UPnP)
+# Short description for end use. Should be less than 64 characters.
+#friendly_name=WPS Access Point
+
+# Manufacturer URL (optional for UPnP)
+#manufacturer_url=http://www.example.com/
+
+# Model Description (recommended for UPnP)
+# Long description for end user. Should be less than 128 characters.
+#model_description=Wireless Access Point
+
+# Model URL (optional for UPnP)
+#model_url=http://www.example.com/model/
+
+# Universal Product Code (optional for UPnP)
+# 12-digit, all-numeric code that identifies the consumer package.
+#upc=123456789012
+
+##### Wi-Fi Direct (P2P) ######################################################
+
+# Enable P2P Device management
+#manage_p2p=1
+
+# Allow cross connection
+#allow_cross_connection=1
+
+#### TDLS (IEEE 802.11z-2010) #################################################
+
+# Prohibit use of TDLS in this BSS
+#tdls_prohibit=1
+
+# Prohibit use of TDLS Channel Switching in this BSS
+#tdls_prohibit_chan_switch=1
+
+##### IEEE 802.11v-2011 #######################################################
+
+# Time advertisement
+# 0 = disabled (default)
+# 2 = UTC time at which the TSF timer is 0
+#time_advertisement=2
+
+# Local time zone as specified in 8.3 of IEEE Std 1003.1-2004:
+# stdoffset[dst[offset][,start[/time],end[/time]]]
+#time_zone=EST5
+
+##### IEEE 802.11u-2011 #######################################################
+
+# Enable Interworking service
+#interworking=1
+
+# Access Network Type
+# 0 = Private network
+# 1 = Private network with guest access
+# 2 = Chargeable public network
+# 3 = Free public network
+# 4 = Personal device network
+# 5 = Emergency services only network
+# 14 = Test or experimental
+# 15 = Wildcard
+#access_network_type=0
+
+# Whether the network provides connectivity to the Internet
+# 0 = Unspecified
+# 1 = Network provides connectivity to the Internet
+#internet=1
+
+# Additional Step Required for Access
+# Note: This is only used with open network, i.e., ASRA shall ne set to 0 if
+# RSN is used.
+#asra=0
+
+# Emergency services reachable
+#esr=0
+
+# Unauthenticated emergency service accessible
+#uesa=0
+
+# Venue Info (optional)
+# The available values are defined in IEEE Std 802.11u-2011, 7.3.1.34.
+# Example values (group,type):
+# 0,0 = Unspecified
+# 1,7 = Convention Center
+# 1,13 = Coffee Shop
+# 2,0 = Unspecified Business
+# 7,1  Private Residence
+#venue_group=7
+#venue_type=1
+
+# Homogeneous ESS identifier (optional; dot11HESSID)
+# If set, this shall be identifical to one of the BSSIDs in the homogeneous
+# ESS and this shall be set to the same value across all BSSs in homogeneous
+# ESS.
+#hessid=02:03:04:05:06:07
+
+# Roaming Consortium List
+# Arbitrary number of Roaming Consortium OIs can be configured with each line
+# adding a new OI to the list. The first three entries are available through
+# Beacon and Probe Response frames. Any additional entry will be available only
+# through ANQP queries. Each OI is between 3 and 15 octets and is configured a
+# a hexstring.
+#roaming_consortium=021122
+#roaming_consortium=2233445566
+
+##### Multiple BSSID support ##################################################
+#
+# Above configuration is using the default interface (wlan#, or multi-SSID VLAN
+# interfaces). Other BSSIDs can be added by using separator 'bss' with
+# default interface name to be allocated for the data packets of the new BSS.
+#
+# hostapd will generate BSSID mask based on the BSSIDs that are
+# configured. hostapd will verify that dev_addr & MASK == dev_addr. If this is
+# not the case, the MAC address of the radio must be changed before starting
+# hostapd (ifconfig wlan0 hw ether <MAC addr>). If a BSSID is configured for
+# every secondary BSS, this limitation is not applied at hostapd and other
+# masks may be used if the driver supports them (e.g., swap the locally
+# administered bit)
+#
+# BSSIDs are assigned in order to each BSS, unless an explicit BSSID is
+# specified using the 'bssid' parameter.
+# If an explicit BSSID is specified, it must be chosen such that it:
+# - results in a valid MASK that covers it and the dev_addr
+# - is not the same as the MAC address of the radio
+# - is not the same as any other explicitly specified BSSID
+#
+# Please note that hostapd uses some of the values configured for the first BSS
+# as the defaults for the following BSSes. However, it is recommended that all
+# BSSes include explicit configuration of all relevant configuration items.
+#
+#bss=wlan0_0
+#ssid=test2
+# most of the above items can be used here (apart from radio interface specific
+# items, like channel)
+
+#bss=wlan0_1
+#bssid=00:13:10:95:fe:0b
+# ...
diff --git a/multitech/recipes/hostap/hostap-daemon-1.0/init b/multitech/recipes/hostap/hostap-daemon-1.0/init
new file mode 100644
index 0000000..79f74b6
--- /dev/null
+++ b/multitech/recipes/hostap/hostap-daemon-1.0/init
@@ -0,0 +1,37 @@
+#!/bin/sh
+DAEMON=/usr/sbin/hostapd
+NAME=hostapd
+DESC="HOSTAP Daemon"
+ARGS="/etc/hostapd.conf -B"
+
+test -f $DAEMON || exit 0
+
+set -e
+
+case "$1" in
+    start)
+	echo -n "Starting $DESC: "
+	start-stop-daemon -S -x $DAEMON -- $ARGS
+	echo "$NAME."
+	;;
+    stop)
+	echo -n "Stopping $DESC: "
+	start-stop-daemon -K -x $DAEMON
+	echo "$NAME."
+	;;
+    restart)
+	$0 stop
+	$0 start
+	;;
+    reload)
+	echo -n "Reloading $DESC: "
+	killall -HUP $(basename ${DAEMON})
+	echo "$NAME."
+	;;
+    *)
+	echo "Usage: $0 {start|stop|restart|reload}"
+	exit 1
+	;;
+esac
+
+exit 0
diff --git a/multitech/recipes/hostap/hostap-daemon_1.0.bb b/multitech/recipes/hostap/hostap-daemon_1.0.bb
new file mode 100644
index 0000000..a726237
--- /dev/null
+++ b/multitech/recipes/hostap/hostap-daemon_1.0.bb
@@ -0,0 +1,18 @@
+DESCRIPTION = "User space daemon for extended IEEE 802.11 management"
+
+require hostap-daemon-1.0.inc
+
+PR = "r1"
+
+#DEFAULT_PREFERENCE = "-1"
+
+SRC_URI = "http://hostap.epitest.fi/releases/hostapd-${PV}.tar.gz \
+	file://defconfig \
+	file://init \
+	file://hostapd.conf"
+SRC_URI[md5sum] = "236247a7bbd4f60d5fa3e99849d1ffc9"
+SRC_URI[sha256sum] = "002e9dcb7e46cf82b5900a2fcf92b30fc8cdfd32a72d7fd4488588f1c013dfcc"
+
+S = "${WORKDIR}/hostapd-${PV}/hostapd"
+
+
diff --git a/multitech/recipes/images/corecdp-base-image.bb b/multitech/recipes/images/corecdp-base-image.bb
index 8f95f2b..53e4a1e 100644
--- a/multitech/recipes/images/corecdp-base-image.bb
+++ b/multitech/recipes/images/corecdp-base-image.bb
@@ -26,8 +26,23 @@ NETWORKING_FEATURES = "ppp \
                        openssl \
                        openssh-sftp-server \
                        rsync \
+                       iperf \
                        "
 
+WIFI_FEATURES = " \
+                libnl \
+                wpa-supplicant \
+                wireless-tools \
+                iw \
+                "
+
+WL1271_SUPPORT = " \
+                ti-compat-wireless-wl12xx wl12xx-firmware \
+                ti-wifi-utils \
+                "
+
+BLUETOOTH_FEATURES = "bluez4"
+
 TIME_FEATURES = "tzdata \
                  cron \
                  ntpdate \
@@ -65,6 +80,13 @@ IMAGE_INSTALL = "task-boot \
                 ${MISC_FEATURES} \
                 "
 
+# Add Wi-fi/Bluetooth support for devices that support it
+IMAGE_INSTALL_append_mtocgd3 = " ${WIFI_FEATURES} ${WL1271_SUPPORT} ${BLUETOOTH_FEATURES} "
+IMAGE_INSTALL_append_mt100eocg-pcie-dk = " ${WIFI_FEATURES} ${WL1271_SUPPORT} ${BLUETOOTH_FEATURES} "
+
+# Add exar usb-serial driver for mtocgd3 hardware
+IMAGE_INSTALL_append_mtocgd3 += "vizzini"
+
 IMAGE_PREPROCESS_COMMAND = "create_etc_timestamp"
 
 export IMAGE_BASENAME = "corecdp-base-image"
diff --git a/multitech/recipes/images/corecdp-wifi-ap-image.bb b/multitech/recipes/images/corecdp-wifi-ap-image.bb
new file mode 100644
index 0000000..c72b882
--- /dev/null
+++ b/multitech/recipes/images/corecdp-wifi-ap-image.bb
@@ -0,0 +1,7 @@
+require corecdp-base-image.bb
+
+IMAGE_INSTALL += " \
+hostap-daemon hostap-utils \
+"
+
+export IMAGE_BASENAME = "corecdp-wifi-ap-image"
diff --git a/multitech/recipes/initscripts/initscripts-1.0/corecdp/umountfs b/multitech/recipes/initscripts/initscripts-1.0/corecdp/umountfs
index a0d7155..f8f47dc 100644
--- a/multitech/recipes/initscripts/initscripts-1.0/corecdp/umountfs
+++ b/multitech/recipes/initscripts/initscripts-1.0/corecdp/umountfs
@@ -101,7 +101,7 @@ flash_upgrade() {
     umount_all
 
     flash_eraseall -j ${rootfs_mtd}
-    ${flash_dir}/nandwrite.static ${rootfs_mtd} ${rootfs_file}
+    ${flash_dir}/nandwrite.static -p ${rootfs_mtd} ${rootfs_file}
 
     echo "Rebooting..."
 
diff --git a/multitech/recipes/initscripts/initscripts_1.0.bbappend b/multitech/recipes/initscripts/initscripts_1.0.bbappend
index 93284e0..af0ba66 100644
--- a/multitech/recipes/initscripts/initscripts_1.0.bbappend
+++ b/multitech/recipes/initscripts/initscripts_1.0.bbappend
@@ -1,4 +1,4 @@
 FILESEXTRA := "${THISDIR}"
 FILESPATHBASE =. "${FILESEXTRA}:"
 
-PR .= ".corecdp2"
+PR .= ".corecdp3"
diff --git a/multitech/recipes/linux-libc-headers/linux-libc-headers_2.6.39.bb b/multitech/recipes/linux-libc-headers/linux-libc-headers_2.6.39.bb
new file mode 100644
index 0000000..c3fa68c
--- /dev/null
+++ b/multitech/recipes/linux-libc-headers/linux-libc-headers_2.6.39.bb
@@ -0,0 +1,26 @@
+require recipes/linux-libc-headers/linux-libc-headers.inc
+
+INHIBIT_DEFAULT_DEPS = "1"
+DEPENDS += "unifdef-native"
+PR = "r0"
+
+DEFAULT_PREFERENCE = "-1"
+
+SRC_URI = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-${PV}.tar.bz2 \
+	  "
+S = "${WORKDIR}/linux-${PV}"
+
+do_configure() {
+	oe_runmake allnoconfig ARCH=$ARCH
+}
+
+do_compile () {
+}
+
+do_install() {
+	oe_runmake headers_install INSTALL_HDR_PATH=${D}${exec_prefix} ARCH=$ARCH
+	rm -f ${D}${exec_prefix}/include/scsi/scsi.h
+}
+
+SRC_URI[md5sum] = "1aab7a741abe08d42e8eccf20de61e05"
+SRC_URI[sha256sum] = "584d17f2a3ee18a9501d7ff36907639e538cfdba4529978b8550c461d45c61f6"
diff --git a/multitech/recipes/linux/linux-2.6.35/mt100eocg/defconfig b/multitech/recipes/linux/linux-2.6.35/mt100eocg/defconfig
index 498d6d7..8a2fa1c 100644
--- a/multitech/recipes/linux/linux-2.6.35/mt100eocg/defconfig
+++ b/multitech/recipes/linux/linux-2.6.35/mt100eocg/defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.35.14
-# Fri Feb 10 09:34:40 2012
+# Wed Oct  3 16:23:24 2012
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -423,6 +423,8 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_ASK_IP_FIB_HASH is not set
+# CONFIG_IP_FIB_TRIE is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
@@ -445,6 +447,14 @@ CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
+# CONFIG_DEFAULT_BIC is not set
+# CONFIG_DEFAULT_CUBIC is not set
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_HYBLA is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_VENO is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
@@ -575,6 +585,9 @@ CONFIG_IP_NF_MANGLE=y
 # CONFIG_IP_NF_ARPTABLES is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+# CONFIG_SCTP_HMAC_MD5 is not set
 # CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
@@ -837,11 +850,11 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
+CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
+CONFIG_TUN=m
 # CONFIG_VETH is not set
 CONFIG_PHYLIB=y
 
@@ -907,6 +920,9 @@ CONFIG_AR9170_USB=m
 CONFIG_AR9170_LEDS=y
 # CONFIG_B43 is not set
 # CONFIG_B43LEGACY is not set
+# CONFIG_B43LEGACY_DMA_AND_PIO_MODE is not set
+# CONFIG_B43LEGACY_DMA_MODE is not set
+# CONFIG_B43LEGACY_PIO_MODE is not set
 # CONFIG_HOSTAP is not set
 # CONFIG_IWM is not set
 CONFIG_LIBERTAS=m
@@ -945,37 +961,37 @@ CONFIG_ZD1211RW=m
 #
 # USB Network Adapters
 #
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
 CONFIG_USB_USBNET=m
 CONFIG_USB_NET_AX8817X=m
 CONFIG_USB_NET_CDCETHER=m
-# CONFIG_USB_NET_CDC_EEM is not set
+CONFIG_USB_NET_CDC_EEM=m
 CONFIG_USB_NET_DM9601=m
 CONFIG_USB_NET_SMSC75XX=m
 CONFIG_USB_NET_SMSC95XX=m
-# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_GL620A=m
 CONFIG_USB_NET_NET1080=m
-# CONFIG_USB_NET_PLUSB is not set
-# CONFIG_USB_NET_MCS7830 is not set
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
 CONFIG_USB_NET_RNDIS_HOST=m
 CONFIG_USB_NET_CDC_SUBSET=m
-# CONFIG_USB_ALI_M5632 is not set
-# CONFIG_USB_AN2720 is not set
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
 CONFIG_USB_BELKIN=y
 CONFIG_USB_ARMLINUX=y
 # CONFIG_USB_EPSON2888 is not set
-# CONFIG_USB_KC2190 is not set
+CONFIG_USB_KC2190=y
 CONFIG_USB_NET_ZAURUS=m
-# CONFIG_USB_NET_INT51X1 is not set
-# CONFIG_USB_IPHETH is not set
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
 CONFIG_USB_SIERRA_NET=m
 # CONFIG_WAN is not set
 CONFIG_PPP=y
 # CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_ASYNC=y
 # CONFIG_PPP_SYNC_TTY is not set
 CONFIG_PPP_DEFLATE=y
@@ -1347,6 +1363,8 @@ CONFIG_USB_S2255=m
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_FB_CARMINE_DRAM_EVAL is not set
+# CONFIG_CARMINE_DRAM_CUSTOM is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
@@ -1399,7 +1417,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 # CONFIG_USB_ISP1362_HCD is not set
-CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD=m
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
diff --git a/multitech/recipes/linux/linux-2.6.35/mtcdp/defconfig b/multitech/recipes/linux/linux-2.6.35/mtcdp/defconfig
index 02e49eb..68eaf6d 100644
--- a/multitech/recipes/linux/linux-2.6.35/mtcdp/defconfig
+++ b/multitech/recipes/linux/linux-2.6.35/mtcdp/defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.35.14
-# Fri Feb 10 09:34:40 2012
+# Wed Oct  3 16:21:51 2012
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -423,6 +423,8 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_ASK_IP_FIB_HASH is not set
+# CONFIG_IP_FIB_TRIE is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
@@ -445,6 +447,14 @@ CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
+# CONFIG_DEFAULT_BIC is not set
+# CONFIG_DEFAULT_CUBIC is not set
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_HYBLA is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_VENO is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
@@ -575,6 +585,9 @@ CONFIG_IP_NF_MANGLE=y
 # CONFIG_IP_NF_ARPTABLES is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+# CONFIG_SCTP_HMAC_MD5 is not set
 # CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
@@ -837,11 +850,11 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
+CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
+CONFIG_TUN=m
 # CONFIG_VETH is not set
 CONFIG_PHYLIB=y
 
@@ -907,6 +920,9 @@ CONFIG_AR9170_USB=m
 CONFIG_AR9170_LEDS=y
 # CONFIG_B43 is not set
 # CONFIG_B43LEGACY is not set
+# CONFIG_B43LEGACY_DMA_AND_PIO_MODE is not set
+# CONFIG_B43LEGACY_DMA_MODE is not set
+# CONFIG_B43LEGACY_PIO_MODE is not set
 # CONFIG_HOSTAP is not set
 # CONFIG_IWM is not set
 CONFIG_LIBERTAS=m
@@ -945,37 +961,37 @@ CONFIG_ZD1211RW=m
 #
 # USB Network Adapters
 #
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
 CONFIG_USB_USBNET=m
 CONFIG_USB_NET_AX8817X=m
 CONFIG_USB_NET_CDCETHER=m
-# CONFIG_USB_NET_CDC_EEM is not set
+CONFIG_USB_NET_CDC_EEM=m
 CONFIG_USB_NET_DM9601=m
 CONFIG_USB_NET_SMSC75XX=m
 CONFIG_USB_NET_SMSC95XX=m
-# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_GL620A=m
 CONFIG_USB_NET_NET1080=m
-# CONFIG_USB_NET_PLUSB is not set
-# CONFIG_USB_NET_MCS7830 is not set
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
 CONFIG_USB_NET_RNDIS_HOST=m
 CONFIG_USB_NET_CDC_SUBSET=m
-# CONFIG_USB_ALI_M5632 is not set
-# CONFIG_USB_AN2720 is not set
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
 CONFIG_USB_BELKIN=y
 CONFIG_USB_ARMLINUX=y
 # CONFIG_USB_EPSON2888 is not set
-# CONFIG_USB_KC2190 is not set
+CONFIG_USB_KC2190=y
 CONFIG_USB_NET_ZAURUS=m
-# CONFIG_USB_NET_INT51X1 is not set
-# CONFIG_USB_IPHETH is not set
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
 CONFIG_USB_SIERRA_NET=m
 # CONFIG_WAN is not set
 CONFIG_PPP=y
 # CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_ASYNC=y
 # CONFIG_PPP_SYNC_TTY is not set
 CONFIG_PPP_DEFLATE=y
@@ -1347,6 +1363,8 @@ CONFIG_USB_S2255=m
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_FB_CARMINE_DRAM_EVAL is not set
+# CONFIG_CARMINE_DRAM_CUSTOM is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0001-dmaengine-at_hdmac-modify-way-to-use-interrupts.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0001-dmaengine-at_hdmac-modify-way-to-use-interrupts.patch
new file mode 100644
index 0000000..4967bd3
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0001-dmaengine-at_hdmac-modify-way-to-use-interrupts.patch
@@ -0,0 +1,75 @@
+From e22e7d2f67c4f8003215863361f19ac6acdb927e Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 1 Feb 2011 19:58:30 +0100
+Subject: [PATCH 001/107] dmaengine: at_hdmac: modify way to use interrupts
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Now we use Buffer Transfer Completed interrupts. If we
+want a chained buffer completed information, we setup the
+ATC_IEN bit in CTRLB register in the lli.
+This is done by set_desc_eol() function and used by
+memcpy/slave_sg functions.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c      |    4 ++--
+ drivers/dma/at_hdmac_regs.h |   11 ++++++++---
+ 2 files changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index 235f53b..5124e09 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -464,7 +464,7 @@ static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
+ 
+ 		for (i = 0; i < atdma->dma_common.chancnt; i++) {
+ 			atchan = &atdma->chan[i];
+-			if (pending & (AT_DMA_CBTC(i) | AT_DMA_ERR(i))) {
++			if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) {
+ 				if (pending & AT_DMA_ERR(i)) {
+ 					/* Disable channel on AHB error */
+ 					dma_writel(atdma, CHDR, atchan->mask);
+@@ -549,7 +549,7 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+ 	}
+ 
+ 	ctrla =   ATC_DEFAULT_CTRLA;
+-	ctrlb =   ATC_DEFAULT_CTRLB
++	ctrlb =   ATC_DEFAULT_CTRLB | ATC_IEN
+ 		| ATC_SRC_ADDR_MODE_INCR
+ 		| ATC_DST_ADDR_MODE_INCR
+ 		| ATC_FC_MEM2MEM;
+diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
+index 495457e..8303306 100644
+--- a/drivers/dma/at_hdmac_regs.h
++++ b/drivers/dma/at_hdmac_regs.h
+@@ -309,8 +309,8 @@ static void atc_setup_irq(struct at_dma_chan *atchan, int on)
+ 	struct at_dma	*atdma = to_at_dma(atchan->chan_common.device);
+ 	u32		ebci;
+ 
+-	/* enable interrupts on buffer chain completion & error */
+-	ebci =    AT_DMA_CBTC(atchan->chan_common.chan_id)
++	/* enable interrupts on buffer transfer completion & error */
++	ebci =    AT_DMA_BTC(atchan->chan_common.chan_id)
+ 		| AT_DMA_ERR(atchan->chan_common.chan_id);
+ 	if (on)
+ 		dma_writel(atdma, EBCIER, ebci);
+@@ -347,7 +347,12 @@ static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
+  */
+ static void set_desc_eol(struct at_desc *desc)
+ {
+-	desc->lli.ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;
++	u32 ctrlb = desc->lli.ctrlb;
++
++	ctrlb &= ~ATC_IEN;
++	ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;
++
++	desc->lli.ctrlb = ctrlb;
+ 	desc->lli.dscr = 0;
+ }
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0002-dmaengine-at_hdmac-add-cyclic-DMA-operation-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0002-dmaengine-at_hdmac-add-cyclic-DMA-operation-support.patch
new file mode 100644
index 0000000..63d1757
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0002-dmaengine-at_hdmac-add-cyclic-DMA-operation-support.patch
@@ -0,0 +1,319 @@
+From 50730e4e5183b199232b7c0f93eadd8af1e439a6 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 1 Feb 2011 16:39:11 +0100
+Subject: [PATCH 002/107] dmaengine: at_hdmac: add cyclic DMA operation
+ support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c      |  187 +++++++++++++++++++++++++++++++++++++++---
+ drivers/dma/at_hdmac_regs.h |   14 +++-
+ 2 files changed, 185 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index 5124e09..a58ae65 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -237,16 +237,12 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
+ static void
+ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
+ {
+-	dma_async_tx_callback		callback;
+-	void				*param;
+ 	struct dma_async_tx_descriptor	*txd = &desc->txd;
+ 
+ 	dev_vdbg(chan2dev(&atchan->chan_common),
+ 		"descriptor %u complete\n", txd->cookie);
+ 
+ 	atchan->completed_cookie = txd->cookie;
+-	callback = txd->callback;
+-	param = txd->callback_param;
+ 
+ 	/* move children to free_list */
+ 	list_splice_init(&desc->tx_list, &atchan->free_list);
+@@ -278,12 +274,19 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
+ 		}
+ 	}
+ 
+-	/*
+-	 * The API requires that no submissions are done from a
+-	 * callback, so we don't need to drop the lock here
+-	 */
+-	if (callback)
+-		callback(param);
++	/* for cyclic transfers,
++	 * no need to replay callback function while stopping */
++	if (!test_bit(ATC_IS_CYCLIC, &atchan->status)) {
++		dma_async_tx_callback	callback = txd->callback;
++		void			*param = txd->callback_param;
++
++		/*
++		 * The API requires that no submissions are done from a
++		 * callback, so we don't need to drop the lock here
++		 */
++		if (callback)
++			callback(param);
++	}
+ 
+ 	dma_run_dependencies(txd);
+ }
+@@ -419,6 +422,26 @@ static void atc_handle_error(struct at_dma_chan *atchan)
+ 	atc_chain_complete(atchan, bad_desc);
+ }
+ 
++/**
++ * atc_handle_cyclic - at the end of a period, run callback function
++ * @atchan: channel used for cyclic operations
++ *
++ * Called with atchan->lock held and bh disabled
++ */
++static void atc_handle_cyclic(struct at_dma_chan *atchan)
++{
++	struct at_desc			*first = atc_first_active(atchan);
++	struct dma_async_tx_descriptor	*txd = &first->txd;
++	dma_async_tx_callback		callback = txd->callback;
++	void				*param = txd->callback_param;
++
++	dev_vdbg(chan2dev(&atchan->chan_common),
++			"new cyclic period llp 0x%08x\n",
++			channel_readl(atchan, DSCR));
++
++	if (callback)
++		callback(param);
++}
+ 
+ /*--  IRQ & Tasklet  ---------------------------------------------------*/
+ 
+@@ -434,8 +457,10 @@ static void atc_tasklet(unsigned long data)
+ 	}
+ 
+ 	spin_lock(&atchan->lock);
+-	if (test_and_clear_bit(0, &atchan->error_status))
++	if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
+ 		atc_handle_error(atchan);
++	else if (test_bit(ATC_IS_CYCLIC, &atchan->status))
++		atc_handle_cyclic(atchan);
+ 	else
+ 		atc_advance_work(atchan);
+ 
+@@ -469,7 +494,7 @@ static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
+ 					/* Disable channel on AHB error */
+ 					dma_writel(atdma, CHDR, atchan->mask);
+ 					/* Give information to tasklet */
+-					set_bit(0, &atchan->error_status);
++					set_bit(ATC_IS_ERROR, &atchan->status);
+ 				}
+ 				tasklet_schedule(&atchan->tasklet);
+ 				ret = IRQ_HANDLED;
+@@ -759,6 +784,127 @@ err_desc_get:
+ 	return NULL;
+ }
+ 
++/**
++ * atc_dma_cyclic_prep - prepare the cyclic DMA transfer
++ * @chan: the DMA channel to prepare
++ * @buf_addr: physical DMA address where the buffer starts
++ * @buf_len: total number of bytes for the entire buffer
++ * @period_len: number of bytes for each period
++ * @direction: transfer direction, to or from device
++ */
++static struct dma_async_tx_descriptor *
++atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
++		size_t period_len, enum dma_data_direction direction)
++{
++	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
++	struct at_dma_slave	*atslave = chan->private;
++	struct at_desc		*first = NULL;
++	struct at_desc		*prev = NULL;
++	unsigned long		was_cyclic;
++	unsigned int		periods = buf_len / period_len;
++	unsigned int		reg_width;
++	u32			ctrla;
++	u32			ctrlb;
++	unsigned int		i;
++
++	dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
++			direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE",
++			buf_addr,
++			periods, buf_len, period_len);
++
++	if (unlikely(!atslave || !buf_len || !period_len)) {
++		dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n");
++		return NULL;
++	}
++
++	was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status);
++	if (was_cyclic) {
++		dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n");
++		return NULL;
++	}
++
++	reg_width = atslave->reg_width;
++
++	/* Check for too big/unaligned periods and unaligned DMA buffer */
++	if (period_len > (ATC_BTSIZE_MAX << reg_width))
++		goto err_out;
++	if (unlikely(period_len & ((1 << reg_width) - 1)))
++		goto err_out;
++	if (unlikely(buf_addr & ((1 << reg_width) - 1)))
++		goto err_out;
++	if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
++		goto err_out;
++
++	/* prepare common CRTLA/CTRLB values */
++	ctrla =   ATC_DEFAULT_CTRLA | atslave->ctrla
++		| ATC_DST_WIDTH(reg_width)
++		| ATC_SRC_WIDTH(reg_width)
++		| period_len >> reg_width;
++	ctrlb = ATC_DEFAULT_CTRLB;
++
++	/* build cyclic linked list */
++	for (i = 0; i < periods; i++) {
++		struct at_desc	*desc;
++
++		desc = atc_desc_get(atchan);
++		if (!desc)
++			goto err_desc_get;
++
++		switch (direction) {
++		case DMA_TO_DEVICE:
++			desc->lli.saddr = buf_addr + (period_len * i);
++			desc->lli.daddr = atslave->tx_reg;
++			desc->lli.ctrla = ctrla;
++			desc->lli.ctrlb = ctrlb
++					| ATC_DST_ADDR_MODE_FIXED
++					| ATC_SRC_ADDR_MODE_INCR
++					| ATC_FC_MEM2PER;
++			break;
++
++		case DMA_FROM_DEVICE:
++			desc->lli.saddr = atslave->rx_reg;
++			desc->lli.daddr = buf_addr + (period_len * i);
++			desc->lli.ctrla = ctrla;
++			desc->lli.ctrlb = ctrlb
++					| ATC_DST_ADDR_MODE_INCR
++					| ATC_SRC_ADDR_MODE_FIXED
++					| ATC_FC_PER2MEM;
++			break;
++
++		default:
++			return NULL;
++		}
++
++		if (!first) {
++			first = desc;
++		} else {
++			/* inform the HW lli about chaining */
++			prev->lli.dscr = desc->txd.phys;
++			/* insert the link descriptor to the LD ring */
++			list_add_tail(&desc->desc_node,
++					&first->tx_list);
++		}
++		prev = desc;
++	}
++
++	/* lets make a cyclic list */
++	prev->lli.dscr = first->txd.phys;
++
++	/* First descriptor of the chain embedds additional information */
++	first->txd.cookie = -EBUSY;
++	first->len = buf_len;
++
++	return &first->txd;
++
++err_desc_get:
++	dev_err(chan2dev(chan), "not enough descriptors available\n");
++	atc_desc_put(atchan, first);
++err_out:
++	clear_bit(ATC_IS_CYCLIC, &atchan->status);
++	return NULL;
++}
++
++
+ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ 		       unsigned long arg)
+ {
+@@ -795,6 +941,10 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ 
+ 	spin_unlock_bh(&atchan->lock);
+ 
++	/* XXX/ukl: should this be done with bh disabled? */
++	/* if channel dedicated to cyclic operations, free it */
++	clear_bit(ATC_IS_CYCLIC, &atchan->status);
++
+ 	return 0;
+ }
+ 
+@@ -853,6 +1003,10 @@ static void atc_issue_pending(struct dma_chan *chan)
+ 
+ 	dev_vdbg(chan2dev(chan), "issue_pending\n");
+ 
++	/* Not needed for cyclic transfers */
++	if (test_bit(ATC_IS_CYCLIC, &atchan->status))
++		return;
++
+ 	spin_lock_bh(&atchan->lock);
+ 	if (!atc_chan_is_enabled(atchan)) {
+ 		atc_advance_work(atchan);
+@@ -1092,10 +1246,15 @@ static int __init at_dma_probe(struct platform_device *pdev)
+ 	if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask))
+ 		atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy;
+ 
+-	if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) {
++	if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask))
+ 		atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg;
++
++	if (dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask))
++		atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic;
++
++	if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ||
++	    dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask))
+ 		atdma->dma_common.device_control = atc_control;
+-	}
+ 
+ 	dma_writel(atdma, EN, AT_DMA_ENABLE);
+ 
+diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
+index 8303306..c79a9e0 100644
+--- a/drivers/dma/at_hdmac_regs.h
++++ b/drivers/dma/at_hdmac_regs.h
+@@ -181,12 +181,22 @@ txd_to_at_desc(struct dma_async_tx_descriptor *txd)
+ /*--  Channels  --------------------------------------------------------*/
+ 
+ /**
++ * atc_status - information bits stored in channel status flag
++ *
++ * Manipulated with atomic operations.
++ */
++enum atc_status {
++	ATC_IS_ERROR = 0,
++	ATC_IS_CYCLIC = 24,
++};
++
++/**
+  * struct at_dma_chan - internal representation of an Atmel HDMAC channel
+  * @chan_common: common dmaengine channel object members
+  * @device: parent device
+  * @ch_regs: memory mapped register base
+  * @mask: channel index in a mask
+- * @error_status: transmit error status information from irq handler
++ * @status: transmit status information from irq/prep* functions
+  *                to tasklet (use atomic operations)
+  * @tasklet: bottom half to finish transaction work
+  * @lock: serializes enqueue/dequeue operations to descriptors lists
+@@ -201,7 +211,7 @@ struct at_dma_chan {
+ 	struct at_dma		*device;
+ 	void __iomem		*ch_regs;
+ 	u8			mask;
+-	unsigned long		error_status;
++	unsigned long		status;
+ 	struct tasklet_struct	tasklet;
+ 
+ 	spinlock_t		lock;
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0003-dmaengine-at_hdmac-debug-information-sg_len-for-prep.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0003-dmaengine-at_hdmac-debug-information-sg_len-for-prep.patch
new file mode 100644
index 0000000..d3770f0
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0003-dmaengine-at_hdmac-debug-information-sg_len-for-prep.patch
@@ -0,0 +1,32 @@
+From a4353fd9418ab145376c08ec57ffd2b7c231db30 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Mon, 7 Feb 2011 15:07:37 +0100
+Subject: [PATCH 003/107] dmaengine: at_hdmac: debug information sg_len for
+ prep_slave_sg
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index a58ae65..1c1508e 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -664,7 +664,8 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
+ 	struct scatterlist	*sg;
+ 	size_t			total_len = 0;
+ 
+-	dev_vdbg(chan2dev(chan), "prep_slave_sg: %s f0x%lx\n",
++	dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n",
++			sg_len,
+ 			direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE",
+ 			flags);
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0004-dmaengine-at_hdmac-remove-channel-status-testing-in-.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0004-dmaengine-at_hdmac-remove-channel-status-testing-in-.patch
new file mode 100644
index 0000000..60c4bfb
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0004-dmaengine-at_hdmac-remove-channel-status-testing-in-.patch
@@ -0,0 +1,41 @@
+From 1e96442285f67be04287e3f2cb536328f2cbae58 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 10 Feb 2011 12:33:54 +0100
+Subject: [PATCH 004/107] dmaengine: at_hdmac: remove channel status testing
+ in tasklet
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There is no need to test if channel is enabled in tasklet:
+- in error path, channel is disabled in interrupt routine
+- in normal path, this test is performed in sub functions to report
+a misuse of the engine.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c |    7 -------
+ 1 files changed, 0 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index 1c1508e..858358a 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -449,13 +449,6 @@ static void atc_tasklet(unsigned long data)
+ {
+ 	struct at_dma_chan *atchan = (struct at_dma_chan *)data;
+ 
+-	/* Channel cannot be enabled here */
+-	if (atc_chan_is_enabled(atchan)) {
+-		dev_err(chan2dev(&atchan->chan_common),
+-			"BUG: channel enabled in tasklet\n");
+-		return;
+-	}
+-
+ 	spin_lock(&atchan->lock);
+ 	if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
+ 		atc_handle_error(atchan);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0005-dmaengine-at_hdmac-specialize-AHB-interfaces-to-opti.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0005-dmaengine-at_hdmac-specialize-AHB-interfaces-to-opti.patch
new file mode 100644
index 0000000..dd7d738
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0005-dmaengine-at_hdmac-specialize-AHB-interfaces-to-opti.patch
@@ -0,0 +1,121 @@
+From d319913ecdc643e960902b456069b7259e260a65 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Mon, 14 Feb 2011 19:27:46 +0100
+Subject: [PATCH 005/107] dmaengine: at_hdmac: specialize AHB interfaces to
+ optimize transfers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DMA controller has two AHB interfaces on the SOC internal
+matrix.
+It is more efficient to specialize each interface as the
+access to memory can introduce latencies that are not compatible
+with peripheral accesses requirements.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c      |   20 ++++++++++----------
+ drivers/dma/at_hdmac_regs.h |    2 ++
+ 2 files changed, 12 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index 858358a..db2c0bd 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -37,8 +37,7 @@
+ 
+ #define	ATC_DEFAULT_CFG		(ATC_FIFOCFG_HALFFIFO)
+ #define	ATC_DEFAULT_CTRLA	(0)
+-#define	ATC_DEFAULT_CTRLB	(ATC_SIF(0)	\
+-				|ATC_DIF(1))
++#define	ATC_DEFAULT_CTRLB	(ATC_SIF(MEM_IF) | ATC_DIF(MEM_IF))
+ 
+ /*
+  * Initial number of descriptors to allocate for each channel. This could
+@@ -670,14 +669,14 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
+ 	reg_width = atslave->reg_width;
+ 
+ 	ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla;
+-	ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN;
++	ctrlb = ATC_IEN;
+ 
+ 	switch (direction) {
+ 	case DMA_TO_DEVICE:
+ 		ctrla |=  ATC_DST_WIDTH(reg_width);
+ 		ctrlb |=  ATC_DST_ADDR_MODE_FIXED
+ 			| ATC_SRC_ADDR_MODE_INCR
+-			| ATC_FC_MEM2PER;
++			| ATC_FC_MEM2PER | ATC_SIF(MEM_IF) | ATC_DIF(PER_IF);
+ 		reg = atslave->tx_reg;
+ 		for_each_sg(sgl, sg, sg_len, i) {
+ 			struct at_desc	*desc;
+@@ -718,7 +717,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
+ 		ctrla |=  ATC_SRC_WIDTH(reg_width);
+ 		ctrlb |=  ATC_DST_ADDR_MODE_INCR
+ 			| ATC_SRC_ADDR_MODE_FIXED
+-			| ATC_FC_PER2MEM;
++			| ATC_FC_PER2MEM | ATC_SIF(PER_IF) | ATC_DIF(MEM_IF);
+ 
+ 		reg = atslave->rx_reg;
+ 		for_each_sg(sgl, sg, sg_len, i) {
+@@ -798,7 +797,7 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+ 	unsigned int		periods = buf_len / period_len;
+ 	unsigned int		reg_width;
+ 	u32			ctrla;
+-	u32			ctrlb;
++	u32			ctrlb = 0;
+ 	unsigned int		i;
+ 
+ 	dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
+@@ -829,12 +828,11 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+ 	if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
+ 		goto err_out;
+ 
+-	/* prepare common CRTLA/CTRLB values */
++	/* prepare common CRTLA value */
+ 	ctrla =   ATC_DEFAULT_CTRLA | atslave->ctrla
+ 		| ATC_DST_WIDTH(reg_width)
+ 		| ATC_SRC_WIDTH(reg_width)
+ 		| period_len >> reg_width;
+-	ctrlb = ATC_DEFAULT_CTRLB;
+ 
+ 	/* build cyclic linked list */
+ 	for (i = 0; i < periods; i++) {
+@@ -852,7 +850,8 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+ 			desc->lli.ctrlb = ctrlb
+ 					| ATC_DST_ADDR_MODE_FIXED
+ 					| ATC_SRC_ADDR_MODE_INCR
+-					| ATC_FC_MEM2PER;
++					| ATC_FC_MEM2PER
++					| ATC_SIF(MEM_IF) | ATC_DIF(PER_IF);
+ 			break;
+ 
+ 		case DMA_FROM_DEVICE:
+@@ -862,7 +861,8 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+ 			desc->lli.ctrlb = ctrlb
+ 					| ATC_DST_ADDR_MODE_INCR
+ 					| ATC_SRC_ADDR_MODE_FIXED
+-					| ATC_FC_PER2MEM;
++					| ATC_FC_PER2MEM
++					| ATC_SIF(PER_IF) | ATC_DIF(MEM_IF);
+ 			break;
+ 
+ 		default:
+diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
+index c79a9e0..9afcb8d 100644
+--- a/drivers/dma/at_hdmac_regs.h
++++ b/drivers/dma/at_hdmac_regs.h
+@@ -103,6 +103,8 @@
+ /* Bitfields in CTRLB */
+ #define	ATC_SIF(i)		(0x3 & (i))	/* Src tx done via AHB-Lite Interface i */
+ #define	ATC_DIF(i)		((0x3 & (i)) <<  4)	/* Dst tx done via AHB-Lite Interface i */
++#define MEM_IF			0		/* specify AHB interface 0 as memory interface */
++#define PER_IF			1		/* specify AHB interface 1 as peripheral interface */
+ #define	ATC_SRC_PIP		(0x1 <<  8)	/* Source Picture-in-Picture enabled */
+ #define	ATC_DST_PIP		(0x1 << 12)	/* Destination Picture-in-Picture enabled */
+ #define	ATC_SRC_DSCR_DIS	(0x1 << 16)	/* Src Descriptor fetch disable */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0006-dmaengine-AT91SAM9X5-has-a-Atmel-AHB-DMA-engine.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0006-dmaengine-AT91SAM9X5-has-a-Atmel-AHB-DMA-engine.patch
new file mode 100644
index 0000000..b388baf
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0006-dmaengine-AT91SAM9X5-has-a-Atmel-AHB-DMA-engine.patch
@@ -0,0 +1,33 @@
+From b58656e215f783ca2099e29ee58396122a8220c7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Mon, 18 Apr 2011 17:19:18 +0200
+Subject: [PATCH 006/107] dmaengine: AT91SAM9X5 has a Atmel AHB DMA engine
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This change was part of a patch provided (non-publically) by Atmel.  I
+split it off because it was unrelated to the commit log and the other
+changes in that commit.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/Kconfig |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
+index a572600..354fcfa 100644
+--- a/drivers/dma/Kconfig
++++ b/drivers/dma/Kconfig
+@@ -91,7 +91,7 @@ config DW_DMAC
+ 
+ config AT_HDMAC
+ 	tristate "Atmel AHB DMA support"
+-	depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
++	depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 || ARCH_AT91SAM9X5
+ 	select DMA_ENGINE
+ 	help
+ 	  Support the Atmel AHB DMA controller.  This can be integrated in
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0007-rtc-at91-workaround-for-5series-ES-chips.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0007-rtc-at91-workaround-for-5series-ES-chips.patch
new file mode 100644
index 0000000..7c802ca
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0007-rtc-at91-workaround-for-5series-ES-chips.patch
@@ -0,0 +1,79 @@
+From ef74ff3fcfc0072cbac374553e1a6b2f3bf099c4 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 19 Oct 2010 13:36:53 +0200
+Subject: [PATCH 007/107] rtc/at91: workaround for 5series ES chips
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The RTC IMR register is not working on 5series ES chips. Fake it with a static
+variable and some accessors functions.
+This workaround does not modify the original RTC code.
+
+XXX: reevaluate if the hardware-guys fixed it, if yes, drop this,
+     patch, if no send them some stinking fish and rework patch to make
+     the driver aware of the shortcoming.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ .../include/mach/at91sam9x5_rtc_workaround.h       |   31 ++++++++++++++++++++
+ drivers/rtc/rtc-at91rm9200.c                       |    4 ++
+ 2 files changed, 35 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-at91/include/mach/at91sam9x5_rtc_workaround.h
+
+diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_rtc_workaround.h b/arch/arm/mach-at91/include/mach/at91sam9x5_rtc_workaround.h
+new file mode 100644
+index 0000000..4b9f0d7
+--- /dev/null
++++ b/arch/arm/mach-at91/include/mach/at91sam9x5_rtc_workaround.h
+@@ -0,0 +1,31 @@
++/*
++ * Real Time Clock workaround header file
++ * 	apply to at91sam9x5 family Engineering Samples
++ *
++ * Copyright (C) 2010 Atmel, Nicolas Ferre <nicolas.ferre@atmel.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the Free
++ * Software Foundation; either version 2 of the License, or (at your option)
++ * any later version.
++ */
++
++static u32 sam9x5es_rtc_imr = 0;
++
++#define at91_sys_read(x)	(		\
++		(x) == AT91_RTC_IMR? 		\
++			sam9x5es_rtc_imr:	\
++			at91_sys_read(x)	\
++	)
++
++#define at91_sys_write(y, x)	do {			\
++	if ((y) == AT91_RTC_IDR) {			\
++		at91_sys_write(AT91_RTC_IDR, (x));	\
++		sam9x5es_rtc_imr &= ~(x);		\
++	} else if ((y) == AT91_RTC_IER) {		\
++		sam9x5es_rtc_imr |= (x);		\
++		at91_sys_write(AT91_RTC_IER, (x));	\
++	} else {					\
++		at91_sys_write((y), (x));		\
++	}						\
++	} while (0)
+diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
+index e39b77a..b9038f4 100644
+--- a/drivers/rtc/rtc-at91rm9200.c
++++ b/drivers/rtc/rtc-at91rm9200.c
+@@ -32,6 +32,10 @@
+ 
+ #include <mach/at91_rtc.h>
+ 
++#if defined(CONFIG_ARCH_AT91SAM9X5)
++#include <mach/at91sam9x5_rtc_workaround.h>
++#endif
++
+ 
+ #define AT91_RTC_EPOCH		1900UL	/* just like arch/arm/common/rtctime.c */
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0008-rtc-AT91SAM9X5-has-an-at91_rtc.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0008-rtc-AT91SAM9X5-has-an-at91_rtc.patch
new file mode 100644
index 0000000..1e4ad49
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0008-rtc-AT91SAM9X5-has-an-at91_rtc.patch
@@ -0,0 +1,41 @@
+From 25d339722fe977695b998ebb8b2ff2fab9faf7bb Mon Sep 17 00:00:00 2001
+From: Dan Liang <dan.liang@atmel.com>
+Date: Mon, 2 Aug 2010 16:01:39 +0800
+Subject: [PATCH 008/107] rtc: AT91SAM9X5 has an at91_rtc
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Dan Liang <dan.liang@atmel.com>
+[ukleinek: reword commit log]
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/rtc/Kconfig |    6 +++---
+ 1 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
+index e187887..fa5a072 100644
+--- a/drivers/rtc/Kconfig
++++ b/drivers/rtc/Kconfig
+@@ -789,15 +789,15 @@ config RTC_DRV_AT32AP700X
+ 
+ config RTC_DRV_AT91RM9200
+ 	tristate "AT91RM9200 or some AT91SAM9 RTC"
+-	depends on ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
++	depends on ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 || ARCH_AT91SAM9X5
+ 	help
+ 	  Driver for the internal RTC (Realtime Clock) module found on
+-	  Atmel AT91RM9200's and some  AT91SAM9 chips. On AT91SAM9 chips
++	  Atmel AT91RM9200's and some AT91SAM9 chips. On AT91SAM9 chips
+ 	  this is powered by the backup power supply.
+ 
+ config RTC_DRV_AT91SAM9
+ 	tristate "AT91SAM9x/AT91CAP9 RTT as RTC"
+-	depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40)
++	depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40 || ARCH_AT91SAM9X5)
+ 	help
+ 	  RTC driver for the Atmel AT91SAM9x and AT91CAP9 internal RTT
+ 	  (Real Time Timer). These timers are powered by the backup power
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0009-ARM-at91-overall-definition-add-5series-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0009-ARM-at91-overall-definition-add-5series-support.patch
new file mode 100644
index 0000000..133588d
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0009-ARM-at91-overall-definition-add-5series-support.patch
@@ -0,0 +1,356 @@
+From 4b93b1ba993ae9c9d60a86d0a55108a4d2ee2244 Mon Sep 17 00:00:00 2001
+From: Dan Liang <dan.liang@atmel.com>
+Date: Tue, 13 Jul 2010 15:56:23 +0800
+Subject: [PATCH 009/107] ARM: at91: overall definition: add 5series support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[at91sam9x5.h]
+Add the definitions of peripheral and system registers for 5series chips family.
+
+[at91sam9x5_matrix.h]
+Add definitions of Matrix registers for 5series chips family.
+
+[cpu.h]
+Add ARCH_ID and basic cpu macros definition for 5series chips family.
+
+Signed-off-by: Dan Liang <dan.liang@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/mach-at91/include/mach/at91sam9x5.h       |  179 ++++++++++++++++++++
+ .../arm/mach-at91/include/mach/at91sam9x5_matrix.h |  136 +++++++++++++++
+ 2 files changed, 315 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-at91/include/mach/at91sam9x5.h
+ create mode 100644 arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
+
+diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
+new file mode 100644
+index 0000000..c263b46
+--- /dev/null
++++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
+@@ -0,0 +1,179 @@
++/*
++ * Chip-specific header file for the AT91SAM9x5 family
++ *
++ *  Copyright (C) 2009-2010 Atmel Corporation.
++ *
++ * Common definitions.
++ * Based on AT91SAM9x5 preliminary datasheet.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91SAM9X5_H
++#define AT91SAM9X5_H
++
++/*
++ * Peripheral identifiers/interrupts.
++ */
++#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
++#define AT91_ID_SYS		1	/* System Controller Interrupt */
++#define AT91SAM9X5_ID_PIOAB	2	/* Parallel I/O Controller A and B */
++#define AT91SAM9X5_ID_PIOCD	3	/* Parallel I/O Controller C and D */
++#define AT91SAM9X5_ID_SMD	4	/* SMD Soft Modem (SMD) */
++#define AT91SAM9X5_ID_USART0	5	/* USART 0 */
++#define AT91SAM9X5_ID_USART1	6	/* USART 1 */
++#define AT91SAM9X5_ID_USART2	7	/* USART 2 */
++#define AT91SAM9X5_ID_USART3	8	/* USART 3 */
++#define AT91SAM9X5_ID_TWI0	9	/* Two-Wire Interface 0 */
++#define AT91SAM9X5_ID_TWI1	10	/* Two-Wire Interface 1 */
++#define AT91SAM9X5_ID_TWI2	11	/* Two-Wire Interface 2 */
++#define AT91SAM9X5_ID_MCI0	12	/* High Speed Multimedia Card Interface 0 */
++#define AT91SAM9X5_ID_SPI0	13	/* Serial Peripheral Interface 0 */
++#define AT91SAM9X5_ID_SPI1	14	/* Serial Peripheral Interface 1 */
++#define AT91SAM9X5_ID_UART0	15	/* UART 0 */
++#define AT91SAM9X5_ID_UART1	16	/* UART 1 */
++#define AT91SAM9X5_ID_TCB	17	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
++#define AT91SAM9X5_ID_PWM	18	/* Pulse Width Modulation Controller */
++#define AT91SAM9X5_ID_ADC	19	/* ADC Controller */
++#define AT91SAM9X5_ID_DMA0	20	/* DMA Controller 0 */
++#define AT91SAM9X5_ID_DMA1	21	/* DMA Controller 1 */
++#define AT91SAM9X5_ID_UHPHS	22	/* USB Host High Speed */
++#define AT91SAM9X5_ID_UDPHS	23	/* USB Device High Speed */
++#define AT91SAM9X5_ID_EMAC0	24	/* Ethernet MAC0 */
++#define AT91SAM9X5_ID_LCDC	25	/* LCD Controller */
++#define AT91SAM9X5_ID_ISI	25	/* Image Sensor Interface */
++#define AT91SAM9X5_ID_MCI1	26	/* High Speed Multimedia Card Interface 1 */
++#define AT91SAM9X5_ID_EMAC1	27	/* Ethernet MAC1 */
++#define AT91SAM9X5_ID_SSC	28	/* Synchronous Serial Controller */
++#define AT91SAM9X5_ID_CAN0	29	/* CAN Controller 0 */
++#define AT91SAM9X5_ID_CAN1	30	/* CAN Controller 1 */
++#define AT91SAM9X5_ID_IRQ0	31	/* Advanced Interrupt Controller */
++
++/*
++ * User Peripheral physical base addresses.
++ */
++#define AT91SAM9X5_BASE_SPI0		0xf0000000
++#define AT91SAM9X5_BASE_SPI1		0xf0004000
++#define AT91SAM9X5_BASE_MCI0		0xf0008000
++#define AT91SAM9X5_BASE_MCI1		0xf000c000
++#define AT91SAM9X5_BASE_SSC		0xf0010000
++#define AT91SAM9X5_BASE_CAN0		0xf8000000
++#define AT91SAM9X5_BASE_CAN1		0xf8004000
++#define AT91SAM9X5_BASE_TCB0		0xf8008000
++#define AT91SAM9X5_BASE_TC0		0xf8008000
++#define AT91SAM9X5_BASE_TC1		0xf8008040
++#define AT91SAM9X5_BASE_TC2		0xf8008080
++#define AT91SAM9X5_BASE_TCB1		0xf800c000
++#define AT91SAM9X5_BASE_TC3		0xf800c000
++#define AT91SAM9X5_BASE_TC4		0xf800c040
++#define AT91SAM9X5_BASE_TC5		0xf800c080
++#define AT91SAM9X5_BASE_TWI0		0xf8010000
++#define AT91SAM9X5_BASE_TWI1		0xf8014000
++#define AT91SAM9X5_BASE_TWI2		0xf8018000
++#define AT91SAM9X5_BASE_USART0		0xf801c000
++#define AT91SAM9X5_BASE_USART1		0xf8020000
++#define AT91SAM9X5_BASE_USART2		0xf8024000
++#define AT91SAM9X5_BASE_USART3		0xf8028000
++#define AT91SAM9X5_BASE_EMAC0		0xf802c000
++#define AT91SAM9X5_BASE_EMAC1		0xf8030000
++#define AT91SAM9X5_BASE_PWMC		0xf8034000
++#define AT91SAM9X5_BASE_LCDC		0xf8038000
++#define AT91SAM9X5_BASE_UDPHS		0xf803c000
++#define AT91SAM9X5_BASE_UART0		0xf8040000
++#define AT91SAM9X5_BASE_UART1		0xf8044000
++#define AT91SAM9X5_BASE_ISI		0xf8048000
++#define AT91SAM9X5_BASE_ADC		0xf804c000
++#define AT91_BASE_SYS			0xffffc000
++
++/*
++ * System Peripherals (offset from AT91_BASE_SYS)
++ */
++#define AT91_MATRIX	(0xffffde00 - AT91_BASE_SYS)
++#define AT91_PMECC	(0xffffe000 - AT91_BASE_SYS)
++#define AT91_PMERRLOC	(0xffffe600 - AT91_BASE_SYS)
++#define AT91_DDRSDRC0	(0xffffe800 - AT91_BASE_SYS)
++#define AT91_SMC	(0xffffea00 - AT91_BASE_SYS)
++#define AT91_DMA0	(0xffffec00 - AT91_BASE_SYS)
++#define AT91_DMA1	(0xffffee00 - AT91_BASE_SYS)
++#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
++#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
++#define AT91_PIOA	(0xfffff400 - AT91_BASE_SYS)
++#define AT91_PIOB	(0xfffff600 - AT91_BASE_SYS)
++#define AT91_PIOC	(0xfffff800 - AT91_BASE_SYS)
++#define AT91_PIOD	(0xfffffa00 - AT91_BASE_SYS)
++#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
++#define AT91_RSTC	(0xfffffe00 - AT91_BASE_SYS)
++#define AT91_SHDWC	(0xfffffe10 - AT91_BASE_SYS)
++#define AT91_PIT	(0xfffffe30 - AT91_BASE_SYS)
++#define AT91_WDT	(0xfffffe40 - AT91_BASE_SYS)
++#define AT91_GPBR	(0xfffffe60 - AT91_BASE_SYS)
++#define AT91_RTC	(0xfffffeb0 - AT91_BASE_SYS)
++
++#define AT91_USART0	AT91SAM9X5_BASE_US0
++#define AT91_USART1	AT91SAM9X5_BASE_US1
++#define AT91_USART2	AT91SAM9X5_BASE_US2
++#define AT91_USART3	AT91SAM9X5_BASE_US3
++
++/*
++ * Internal Memory.
++ */
++#define AT91SAM9X5_SRAM_BASE	0x00300000	/* Internal SRAM base address */
++#define AT91SAM9X5_SRAM_SIZE	SZ_32K		/* Internal SRAM size (32Kb) */
++
++#define AT91SAM9X5_ROM_BASE	0x00100000	/* Internal ROM base address */
++#define AT91SAM9X5_ROM_SIZE	SZ_1M		/* Internal ROM size (1Mb) */
++
++#define AT91SAM9X5_SMD_BASE	0x00400000	/* SMD Controller */
++#define AT91SAM9X5_UDPHS_FIFO	0x00500000	/* USB Device HS controller */
++#define AT91SAM9X5_OHCI_BASE	0x00600000	/* USB Host controller (OHCI) */
++#define AT91SAM9X5_EHCI_BASE	0x00700000	/* USB Host controller (EHCI) */
++
++#define CONFIG_DRAM_BASE	AT91_CHIPSELECT_1
++
++#define CONSISTENT_DMA_SIZE	SZ_4M
++
++/*
++ * DMA0 peripheral identifiers
++ * for hardware handshaking interface
++ */
++#define AT_DMA_ID_MCI0		 0
++#define AT_DMA_ID_SPI0_TX	 1
++#define AT_DMA_ID_SPI0_RX	 2
++#define AT_DMA_ID_USART0_TX	 3
++#define AT_DMA_ID_USART0_RX	 4
++#define AT_DMA_ID_USART1_TX	 5
++#define AT_DMA_ID_USART1_RX	 6
++#define AT_DMA_ID_TWI0_TX	 7
++#define AT_DMA_ID_TWI0_RX	 8
++#define AT_DMA_ID_TWI2_TX	 9
++#define AT_DMA_ID_TWI2_RX	10
++#define AT_DMA_ID_UART0_TX	11
++#define AT_DMA_ID_UART0_RX	12
++#define AT_DMA_ID_SSC_TX	13
++#define AT_DMA_ID_SSC_RX	14
++
++/*
++ * DMA1 peripheral identifiers
++ * for hardware handshaking interface
++ */
++#define AT_DMA_ID_MCI1		 0
++#define AT_DMA_ID_SPI1_TX	 1
++#define AT_DMA_ID_SPI1_RX	 2
++#define AT_DMA_ID_SMD_TX	 3
++#define AT_DMA_ID_SMD_RX	 4
++#define AT_DMA_ID_TWI1_TX	 5
++#define AT_DMA_ID_TWI1_RX	 6
++#define AT_DMA_ID_ADC_RX	 7
++#define AT_DMA_ID_DBGU_TX	 8
++#define AT_DMA_ID_DBGU_RX	 9
++#define AT_DMA_ID_UART1_TX	10
++#define AT_DMA_ID_UART1_RX	11
++#define AT_DMA_ID_USART2_TX	12
++#define AT_DMA_ID_USART2_RX	13
++#define AT_DMA_ID_USART3_TX	14
++#define AT_DMA_ID_USART3_RX	15
++
++#endif
+diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
+new file mode 100644
+index 0000000..c3e6b64
+--- /dev/null
++++ b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
+@@ -0,0 +1,136 @@
++/*
++ * Matrix-centric header file for the AT91SAM9x5 family
++ *
++ *  Copyright (C) 2009-2010 Atmel Corporation.
++ *
++ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
++ * Based on AT91SAM9x5 preliminary datasheet.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91SAM9X5_MATRIX_H
++#define AT91SAM9X5_MATRIX_H
++
++#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
++#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
++#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
++#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
++#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
++#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
++#define AT91_MATRIX_MCFG6	(AT91_MATRIX + 0x18)	/* Master Configuration Register 6 */
++#define AT91_MATRIX_MCFG7	(AT91_MATRIX + 0x1C)	/* Master Configuration Register 7 */
++#define AT91_MATRIX_MCFG8	(AT91_MATRIX + 0x20)	/* Master Configuration Register 8 */
++#define AT91_MATRIX_MCFG9	(AT91_MATRIX + 0x24)	/* Master Configuration Register 9 */
++#define AT91_MATRIX_MCFG10	(AT91_MATRIX + 0x28)	/* Master Configuration Register 10 */
++#define AT91_MATRIX_MCFG11	(AT91_MATRIX + 0x2C)	/* Master Configuration Register 11 */
++#define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
++#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
++#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
++#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
++#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
++#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
++#define			AT91_MATRIX_ULBT_THIRTYTWO	(5 << 0)
++#define			AT91_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
++#define			AT91_MATRIX_ULBT_128		(7 << 0)
++
++#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
++#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
++#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
++#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
++#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
++#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration Register 5 */
++#define AT91_MATRIX_SCFG6	(AT91_MATRIX + 0x58)	/* Slave Configuration Register 6 */
++#define AT91_MATRIX_SCFG7	(AT91_MATRIX + 0x5C)	/* Slave Configuration Register 7 */
++#define AT91_MATRIX_SCFG8	(AT91_MATRIX + 0x60)	/* Slave Configuration Register 8 */
++#define		AT91_MATRIX_SLOT_CYCLE		(0x1ff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
++#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
++#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
++#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
++#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
++#define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
++
++#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
++#define AT91_MATRIX_PRBS0	(AT91_MATRIX + 0x84)	/* Priority Register B for Slave 0 */
++#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
++#define AT91_MATRIX_PRBS1	(AT91_MATRIX + 0x8C)	/* Priority Register B for Slave 1 */
++#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
++#define AT91_MATRIX_PRBS2	(AT91_MATRIX + 0x94)	/* Priority Register B for Slave 2 */
++#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
++#define AT91_MATRIX_PRBS3	(AT91_MATRIX + 0x9C)	/* Priority Register B for Slave 3 */
++#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
++#define AT91_MATRIX_PRBS4	(AT91_MATRIX + 0xA4)	/* Priority Register B for Slave 4 */
++#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
++#define AT91_MATRIX_PRBS5	(AT91_MATRIX + 0xAC)	/* Priority Register B for Slave 5 */
++#define AT91_MATRIX_PRAS6	(AT91_MATRIX + 0xB0)	/* Priority Register A for Slave 6 */
++#define AT91_MATRIX_PRBS6	(AT91_MATRIX + 0xB4)	/* Priority Register B for Slave 6 */
++#define AT91_MATRIX_PRAS7	(AT91_MATRIX + 0xB8)	/* Priority Register A for Slave 7 */
++#define AT91_MATRIX_PRBS7	(AT91_MATRIX + 0xBC)	/* Priority Register B for Slave 7 */
++#define AT91_MATRIX_PRAS8	(AT91_MATRIX + 0xC0)	/* Priority Register A for Slave 8 */
++#define AT91_MATRIX_PRBS8	(AT91_MATRIX + 0xC4)	/* Priority Register B for Slave 8 */
++#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
++#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
++#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
++#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
++#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
++#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
++#define		AT91_MATRIX_M6PR		(3 << 24)	/* Master 6 Priority */
++#define		AT91_MATRIX_M7PR		(3 << 28)	/* Master 7 Priority */
++#define		AT91_MATRIX_M8PR		(3 << 0)	/* Master 8 Priority (in Register B) */
++#define		AT91_MATRIX_M9PR		(3 << 4)	/* Master 9 Priority (in Register B) */
++#define		AT91_MATRIX_M10PR		(3 << 8)	/* Master 10 Priority (in Register B) */
++#define		AT91_MATRIX_M11PR		(3 << 12)	/* Master 11 Priority (in Register B) */
++
++#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
++#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
++#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
++#define		AT91_MATRIX_RCB2		(1 << 2)
++#define		AT91_MATRIX_RCB3		(1 << 3)
++#define		AT91_MATRIX_RCB4		(1 << 4)
++#define		AT91_MATRIX_RCB5		(1 << 5)
++#define		AT91_MATRIX_RCB6		(1 << 6)
++#define		AT91_MATRIX_RCB7		(1 << 7)
++#define		AT91_MATRIX_RCB8		(1 << 8)
++#define		AT91_MATRIX_RCB9		(1 << 9)
++#define		AT91_MATRIX_RCB10		(1 << 10)
++#define		AT91_MATRIX_RCB11		(1 << 11)
++
++#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x120)	/* EBI Chip Select Assignment Register */
++#define		AT91_MATRIX_EBI_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
++#define			AT91_MATRIX_EBI_CS1A_SMC		(0 << 1)
++#define			AT91_MATRIX_EBI_CS1A_SDRAMC		(1 << 1)
++#define		AT91_MATRIX_EBI_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
++#define			AT91_MATRIX_EBI_CS3A_SMC		(0 << 3)
++#define			AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH	(1 << 3)
++#define		AT91_MATRIX_EBI_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
++#define			AT91_MATRIX_EBI_DBPU_ON			(0 << 8)
++#define			AT91_MATRIX_EBI_DBPU_OFF		(1 << 8)
++#define		AT91_MATRIX_EBI_DBPDC		(1 << 9)	/* Data Bus Pull-up Configuration */
++#define			AT91_MATRIX_EBI_DBPD_ON			(0 << 9)
++#define			AT91_MATRIX_EBI_DBPD_OFF		(1 << 9)
++#define		AT91_MATRIX_EBI_EBI_IOSR	(1 << 17)	/* EBI I/O slew rate selection */
++#define			AT91_MATRIX_EBI_EBI_IOSR_REDUCED	(0 << 17)
++#define			AT91_MATRIX_EBI_EBI_IOSR_NORMAL		(1 << 17)
++#define		AT91_MATRIX_NFD0_SELECT		(1 << 24)	/* NAND Flash Data Bus Selection */
++#define			AT91_MATRIX_NFD0_ON_D0			(0 << 24)
++#define			AT91_MATRIX_NFD0_ON_D16			(1 << 24)
++#define		AT91_MATRIX_DDR_MP_EN		(1 << 25)	/* DDR Multi-port Enable */
++#define			AT91_MATRIX_MP_OFF			(0 << 25)
++#define			AT91_MATRIX_MP_ON			(1 << 25)
++
++#define AT91_MATRIX_WPMR	(AT91_MATRIX + 0x1E4)	/* Write Protect Mode Register */
++#define		AT91_MATRIX_WPMR_WPEN		(1 << 0)	/* Write Protect ENable */
++#define			AT91_MATRIX_WPMR_WP_WPDIS		(0 << 0)
++#define			AT91_MATRIX_WPMR_WP_WPEN		(1 << 0)
++#define		AT91_MATRIX_WPMR_WPKEY		(0xFFFFFF << 8)	/* Write Protect KEY */
++
++#define AT91_MATRIX_WPSR	(AT91_MATRIX + 0x1E8)	/* Write Protect Status Register */
++#define		AT91_MATRIX_WPSR_WPVS		(1 << 0)	/* Write Protect Violation Status */
++#define			AT91_MATRIX_WPSR_NO_WPV		(0 << 0)
++#define			AT91_MATRIX_WPSR_WPV		(1 << 0)
++#define		AT91_MATRIX_WPSR_WPVSRC		(0xFFFF << 8)	/* Write Protect Violation Source */
++
++#endif
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0010-ARM-at91-PMC-header-add-5series-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0010-ARM-at91-PMC-header-add-5series-support.patch
new file mode 100644
index 0000000..b6dd5d4
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0010-ARM-at91-PMC-header-add-5series-support.patch
@@ -0,0 +1,121 @@
+From 70174744ea113add6279afb8642ea71acafb8d69 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Fri, 9 Jul 2010 19:33:10 +0200
+Subject: [PATCH 010/107] ARM: at91: PMC header: add 5series support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add 5series chips family support in PMC header file:
+Alternate prescaler location and CSS length for PCKR is added.
+The new Peripheral Control Register management is added.
+Protection mode register is modified to complete its management.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/mach-at91/include/mach/at91_pmc.h |   63 ++++++++++++++++++++++------
+ 1 files changed, 50 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
+index e46f93e..1782178 100644
+--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
++++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
+@@ -47,9 +47,13 @@
+ #define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI BIAS Start-up Time */
+ 
+ #define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register [not on SAM9RL] */
+-#define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
+-#define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x, CAP9] */
+-#define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
++#define		AT91_PMC_MOSCEN		(1    <<  0)		/* Main Oscillator Enable */
++#define		AT91_PMC_OSCBYPASS	(1    <<  1)		/* Oscillator Bypass [SAM9x, CAP9] */
++#define		AT91_PMC_MOSCRCEN	(1    <<  3)		/* Main On-Chip RC Oscillator Enable [some SAM9] */
++#define		AT91_PMC_OSCOUNT	(0xff <<  8)		/* Main Oscillator Start-up Time */
++#define		AT91_PMC_KEY		(0x37 << 16)		/* MOR Writing Key */
++#define		AT91_PMC_MOSCSEL	(1    << 24)		/* Main Oscillator Selection [some SAM9] */
++#define		AT91_PMC_CFDEN		(1    << 25)		/* Clock Failure Detector Enable [some SAM9] */
+ 
+ #define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */
+ #define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
+@@ -74,14 +78,24 @@
+ #define			AT91_PMC_CSS_PLLA		(2 << 0)
+ #define			AT91_PMC_CSS_PLLB		(3 << 0)
+ #define			AT91_PMC_CSS_UPLL		(3 << 0)	/* [some SAM9 only] */
+-#define		AT91_PMC_PRES		(7 <<  2)		/* Master Clock Prescaler */
+-#define			AT91_PMC_PRES_1			(0 << 2)
+-#define			AT91_PMC_PRES_2			(1 << 2)
+-#define			AT91_PMC_PRES_4			(2 << 2)
+-#define			AT91_PMC_PRES_8			(3 << 2)
+-#define			AT91_PMC_PRES_16		(4 << 2)
+-#define			AT91_PMC_PRES_32		(5 << 2)
+-#define			AT91_PMC_PRES_64		(6 << 2)
++#define		PMC_PRES_OFFSET		2
++#define		AT91_PMC_PRES		(7 <<  PMC_PRES_OFFSET)		/* Master Clock Prescaler */
++#define			AT91_PMC_PRES_1			(0 << PMC_PRES_OFFSET)
++#define			AT91_PMC_PRES_2			(1 << PMC_PRES_OFFSET)
++#define			AT91_PMC_PRES_4			(2 << PMC_PRES_OFFSET)
++#define			AT91_PMC_PRES_8			(3 << PMC_PRES_OFFSET)
++#define			AT91_PMC_PRES_16		(4 << PMC_PRES_OFFSET)
++#define			AT91_PMC_PRES_32		(5 << PMC_PRES_OFFSET)
++#define			AT91_PMC_PRES_64		(6 << PMC_PRES_OFFSET)
++#define		PMC_ALT_PRES_OFFSET	4
++#define		AT91_PMC_ALT_PRES	(7 <<  PMC_ALT_PRES_OFFSET)		/* Master Clock Prescaler [alternate location] */
++#define			AT91_PMC_ALT_PRES_1		(0 << PMC_ALT_PRES_OFFSET)
++#define			AT91_PMC_ALT_PRES_2		(1 << PMC_ALT_PRES_OFFSET)
++#define			AT91_PMC_ALT_PRES_4		(2 << PMC_ALT_PRES_OFFSET)
++#define			AT91_PMC_ALT_PRES_8		(3 << PMC_ALT_PRES_OFFSET)
++#define			AT91_PMC_ALT_PRES_16		(4 << PMC_ALT_PRES_OFFSET)
++#define			AT91_PMC_ALT_PRES_32		(5 << PMC_ALT_PRES_OFFSET)
++#define			AT91_PMC_ALT_PRES_64		(6 << PMC_ALT_PRES_OFFSET)
+ #define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
+ #define			AT91RM9200_PMC_MDIV_1		(0 << 8)	/* [AT91RM9200 only] */
+ #define			AT91RM9200_PMC_MDIV_2		(1 << 8)
+@@ -105,7 +119,14 @@
+ #define			AT91_PMC_USBS_UPLL		(1 << 0)
+ #define		AT91_PMC_OHCIUSBDIV	(0xF <<  8)		/* Divider for USB OHCI Clock */
+ 
++#define	AT91_PMC_SMD		(AT91_PMC + 0x3c)	/* Soft Modem Clock Register [some SAM9 only] */
++#define		AT91_PMC_SMDS		(0x1  <<  0)		/* SMD input clock selection */
++#define		AT91_PMC_SMD_DIV	(0x1f <<  8)		/* SMD input clock divider */
++#define		AT91_PMC_SMDDIV(n)	(((n) <<  8) & AT91_PMC_SMD_DIV)
++
+ #define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-N Registers */
++#define		AT91_PMC_ALT_PCKR_CSS	(0x7 <<  0)		/* Programmable Clock Source Selection [alternate length] */
++#define			AT91_PMC_CSS_MASTER		(4 << 0)	/* [some SAM9 only] */
+ #define		AT91_PMC_CSSMCK		(0x1 <<  8)		/* CSS or Master Clock Selection */
+ #define			AT91_PMC_CSSMCK_CSS		(0 << 8)
+ #define			AT91_PMC_CSSMCK_MCK		(1 << 8)
+@@ -123,11 +144,27 @@
+ #define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
+ #define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
+ #define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
++#define		AT91_PMC_MOSCSELS	(1 << 16)		/* Main Oscillator Selection [some SAM9] */
++#define		AT91_PMC_MOSCRCS	(1 << 17)		/* Main On-Chip RC [some SAM9] */
++#define		AT91_PMC_CFDEV		(1 << 18)		/* Clock Failure Detector Event [some SAM9] */
+ #define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */
+ 
+-#define AT91_PMC_PROT		(AT91_PMC + 0xe4)	/* Protect Register [AT91CAP9 revC only] */
+-#define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
++#define AT91_PMC_PROT		(AT91_PMC + 0xe4)	/* Write Protect Mode Register [some SAM9, AT91CAP9 revC only] */
++#define		AT91_PMC_WPEN		(0x1  <<  0)		/* Write Protect Enable */
++#define		AT91_PMC_WPKEY		(0xffffff << 8)		/* Write Protect Key */
++#define		AT91_PMC_PROTKEY	(0x504d43 << 8)		/* Activation Code */
++
++#define AT91_PMC_WPSR		(AT91_PMC + 0xe8)	/* Write Protect Status Register [some SAM9] */
++#define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
++#define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
+ 
+ #define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
+ 
++#define AT91_PMC_PCR		(AT91_PMC + 0x10c)	/* Peripheral Control Register [some SAM9] */
++#define		AT91_PMC_PCR_PID	(0x3f  <<  0)		/* Peripheral ID */
++#define		AT91_PMC_PCR_CMD	(0x1  <<  12)		/* Command */
++#define		AT91_PMC_PCR_DIV	(0x3  <<  16)		/* Divisor Value */
++#define		AT91_PMC_PCRDIV(n)	(((n) <<  16) & AT91_PMC_PCR_DIV)
++#define		AT91_PMC_PCR_EN		(0x1  <<  28)		/* Enable */
++
+ #endif
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0011-ARM-at91-clock-add-5series-chip-family-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0011-ARM-at91-clock-add-5series-chip-family-support.patch
new file mode 100644
index 0000000..180e515
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0011-ARM-at91-clock-add-5series-chip-family-support.patch
@@ -0,0 +1,215 @@
+From 6a6e54c0091962d01f6b343958bbda95487bb9f5 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Mon, 12 Jul 2010 19:24:14 +0200
+Subject: [PATCH 011/107] ARM: at91: clock: add 5series chip family support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Several changes to PMC have to be managed for adding this 5series support:
+- alternate prescaler location for both MCKR and PCKR
+- alternate CSS length for PCKR
+- added cpu_is_at91sam9x5() to functional switches
+- manage UTMI bias like sam9g45 chip family
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/mach-at91/clock.c |   85 ++++++++++++++++++++++++++++++++++----------
+ 1 files changed, 66 insertions(+), 19 deletions(-)
+
+diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
+index 9113da6..6c92db8 100644
+--- a/arch/arm/mach-at91/clock.c
++++ b/arch/arm/mach-at91/clock.c
+@@ -49,24 +49,37 @@
+  */
+ #define cpu_has_utmi()		(  cpu_is_at91cap9() \
+ 				|| cpu_is_at91sam9rl() \
+-				|| cpu_is_at91sam9g45())
++				|| cpu_is_at91sam9g45() \
++				|| cpu_is_at91sam9x5())
+ 
+ #define cpu_has_800M_plla()	(  cpu_is_at91sam9g20() \
+-				|| cpu_is_at91sam9g45())
++				|| cpu_is_at91sam9g45() \
++				|| cpu_is_at91sam9x5())
+ 
+ #define cpu_has_300M_plla()	(cpu_is_at91sam9g10())
+ 
+ #define cpu_has_pllb()		(!(cpu_is_at91sam9rl() \
+-				|| cpu_is_at91sam9g45()))
++				|| cpu_is_at91sam9g45() \
++				|| cpu_is_at91sam9x5()))
+ 
+-#define cpu_has_upll()		(cpu_is_at91sam9g45())
++#define cpu_has_upll()		(cpu_is_at91sam9g45() \
++				|| cpu_is_at91sam9x5())
+ 
+ /* USB host HS & FS */
+ #define cpu_has_uhp()		(!cpu_is_at91sam9rl())
+ 
+ /* USB device FS only */
+ #define cpu_has_udpfs()		(!(cpu_is_at91sam9rl() \
+-				|| cpu_is_at91sam9g45()))
++				|| cpu_is_at91sam9g45() \
++				|| cpu_is_at91sam9x5()))
++
++#define cpu_has_plladiv2()	(cpu_is_at91sam9g45() \
++				|| cpu_is_at91sam9x5())
++
++#define cpu_has_mdiv3()		(cpu_is_at91sam9g45() \
++				|| cpu_is_at91sam9x5())
++
++#define cpu_has_alt_prescaler()	(cpu_is_at91sam9x5())
+ 
+ static LIST_HEAD(clocks);
+ static DEFINE_SPINLOCK(clk_lock);
+@@ -139,13 +152,6 @@ static void pmc_uckr_mode(struct clk *clk, int is_on)
+ {
+ 	unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
+ 
+-	if (cpu_is_at91sam9g45()) {
+-		if (is_on)
+-			uckr |= AT91_PMC_BIASEN;
+-		else
+-			uckr &= ~AT91_PMC_BIASEN;
+-	}
+-
+ 	if (is_on) {
+ 		is_on = AT91_PMC_LOCKU;
+ 		at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
+@@ -210,11 +216,26 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
+ 				return &utmi_clk;
+ 			else if (cpu_has_pllb())
+ 				return &pllb;
++			break;
++		/* alternate PMC: can use master clock */
++		case AT91_PMC_CSS_MASTER:
++			return &mck;
+ 	}
+ 
+ 	return NULL;
+ }
+ 
++
++static int pmc_prescaler_divider(u32 reg)
++{
++	if (cpu_has_alt_prescaler()) {
++		return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
++	} else {
++		return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
++	}
++}
++
++
+ /*
+  * Associate a particular clock with a function (eg, "uart") and device.
+  * The drivers can then request the same 'function' with several different
+@@ -353,12 +374,22 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
+ {
+ 	unsigned long	flags;
+ 	unsigned	prescale;
++	unsigned long	prescale_offset, css_mask;
+ 	unsigned long	actual;
+ 
+ 	if (!clk_is_programmable(clk))
+ 		return -EINVAL;
+ 	if (clk->users)
+ 		return -EBUSY;
++
++	if (cpu_has_alt_prescaler()) {
++		prescale_offset = PMC_ALT_PRES_OFFSET;
++		css_mask = AT91_PMC_ALT_PCKR_CSS;
++	} else {
++		prescale_offset = PMC_PRES_OFFSET;
++		css_mask = AT91_PMC_CSS;
++	}
++
+ 	spin_lock_irqsave(&clk_lock, flags);
+ 
+ 	actual = clk->parent->rate_hz;
+@@ -367,8 +398,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
+ 			u32	pckr;
+ 
+ 			pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
+-			pckr &= AT91_PMC_CSS;	/* clock selection */
+-			pckr |= prescale << 2;
++			pckr &= css_mask;	/* keep clock selection */
++			pckr |= prescale << prescale_offset;
+ 			at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
+ 			clk->rate_hz = actual;
+ 			break;
+@@ -415,11 +446,17 @@ static void __init init_programmable_clock(struct clk *clk)
+ {
+ 	struct clk	*parent;
+ 	u32		pckr;
++	unsigned int	css_mask;
++
++	if (cpu_has_alt_prescaler())
++		css_mask = AT91_PMC_ALT_PCKR_CSS;
++	else
++		css_mask = AT91_PMC_CSS;
+ 
+ 	pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
+-	parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
++	parent = at91_css_to_clk(pckr & css_mask);
+ 	clk->parent = parent;
+-	clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
++	clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
+ }
+ 
+ #endif	/* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
+@@ -697,7 +734,7 @@ int __init at91_clock_init(unsigned long main_clock)
+ 	if (pll_overclock)
+ 		pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
+ 
+-	if (cpu_is_at91sam9g45()) {
++	if (cpu_has_plladiv2()) {
+ 		mckr = at91_sys_read(AT91_PMC_MCKR);
+ 		plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));	/* plla divisor by 2 */
+ 	}
+@@ -719,6 +756,10 @@ int __init at91_clock_init(unsigned long main_clock)
+ 		 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
+ 		 */
+ 		utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
++
++		/* UTMI bias and PLL are managed at the same time */
++		if (cpu_is_at91sam9g45() || cpu_is_at91sam9x5())
++			utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
+ 	}
+ 
+ 	/*
+@@ -737,7 +778,7 @@ int __init at91_clock_init(unsigned long main_clock)
+ 	mckr = at91_sys_read(AT91_PMC_MCKR);
+ 	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
+ 	freq = mck.parent->rate_hz;
+-	freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));				/* prescale */
++	freq /= pmc_prescaler_divider(mckr);					/* prescale */
+ 	if (cpu_is_at91rm9200()) {
+ 		mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));	/* mdiv */
+ 	} else if (cpu_is_at91sam9g20()) {
+@@ -745,13 +786,19 @@ int __init at91_clock_init(unsigned long main_clock)
+ 			freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
+ 		if (mckr & AT91_PMC_PDIV)
+ 			freq /= 2;		/* processor clock division */
+-	} else if (cpu_is_at91sam9g45()) {
++	} else if (cpu_has_mdiv3()) {
+ 		mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
+ 			freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));	/* mdiv */
+ 	} else {
+ 		mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));		/* mdiv */
+ 	}
+ 
++	if (cpu_has_alt_prescaler()) {
++		/* Programmable clocks can use MCK */
++		mck.type |= CLK_TYPE_PRIMARY;
++		mck.id = 4;
++	}
++
+ 	/* Register the PMC's standard clocks */
+ 	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
+ 		list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0012-ARM-at91-AT91SAM9x5-processors-and-EK-board-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0012-ARM-at91-AT91SAM9x5-processors-and-EK-board-support.patch
new file mode 100644
index 0000000..6078e73
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0012-ARM-at91-AT91SAM9x5-processors-and-EK-board-support.patch
@@ -0,0 +1,3216 @@
+From 31f087cd051928de83fe17aee4d1e2a6416e88ee Mon Sep 17 00:00:00 2001
+From: Dan Liang <dan.liang@atmel.com>
+Date: Fri, 23 Jul 2010 13:00:56 +0200
+Subject: [PATCH 012/107] ARM: at91: AT91SAM9x5 processors and EK board
+ support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch is based on many smaller patches by Dan Liang, Hong Xu, Josh
+Wu and Nicolas Ferre.
+
+XXX: try to put support for AT91SAM9x5 into an existing choice item
+
+Signed-off-by: Dan Liang <dan.liang@atmel.com>
+Signed-off-by: Hong Xu <hong.xu@atmel.com>
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+[ukleinek: remove .phys_io and .io_pg_offst]
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/mach-at91/Kconfig                     |   21 +
+ arch/arm/mach-at91/Makefile                    |    4 +
+ arch/arm/mach-at91/at91sam9x5.c                |  416 ++++++
+ arch/arm/mach-at91/at91sam9x5_devices.c        | 1785 ++++++++++++++++++++++++
+ arch/arm/mach-at91/board-sam9x5cm.c            |  236 ++++
+ arch/arm/mach-at91/board-sam9x5ek.c            |  358 +++++
+ arch/arm/mach-at91/generic.h                   |    2 +
+ arch/arm/mach-at91/include/mach/board-sam9x5.h |   91 ++
+ arch/arm/mach-at91/include/mach/board.h        |   18 +-
+ arch/arm/mach-at91/include/mach/hardware.h     |    2 +
+ arch/arm/mach-at91/include/mach/timex.h        |    5 +
+ arch/arm/mach-at91/pm.h                        |   19 +
+ arch/arm/mach-at91/pm_slowclock.S              |   11 +-
+ 13 files changed, 2961 insertions(+), 7 deletions(-)
+ create mode 100644 arch/arm/mach-at91/at91sam9x5.c
+ create mode 100644 arch/arm/mach-at91/at91sam9x5_devices.c
+ create mode 100644 arch/arm/mach-at91/board-sam9x5cm.c
+ create mode 100644 arch/arm/mach-at91/board-sam9x5ek.c
+ create mode 100644 arch/arm/mach-at91/include/mach/board-sam9x5.h
+
+diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
+index 2d299bf..b5d29ef 100644
+--- a/arch/arm/mach-at91/Kconfig
++++ b/arch/arm/mach-at91/Kconfig
+@@ -78,6 +78,13 @@ config ARCH_AT91SAM9G45
+ 	select HAVE_FB_ATMEL
+ 	select HAVE_NET_MACB
+ 
++config ARCH_AT91SAM9X5
++	bool "AT91SAM9X5"
++	select CPU_ARM926T
++	select GENERIC_CLOCKEVENTS
++	select HAVE_FB_ATMEL
++	select HAVE_NET_MACB
++
+ config ARCH_AT91CAP9
+ 	bool "AT91CAP9"
+ 	select CPU_ARM926T
+@@ -426,6 +433,20 @@ endif
+ 
+ # ----------------------------------------------------------
+ 
++if ARCH_AT91SAM9X5
++
++comment "AT91SAM9x5 Series Board Type"
++
++config MACH_AT91SAM9X5EK
++	bool "Atmel AT91SAM9x5 Series Evaluation Kit"
++	help
++	  Select this if you re using Atmel's AT91SAM9x5-EK Evaluation Kit.
++	  Supported chips are sam9g15, sam9g25, sam9x25, sam9g35 and sam9x35.
++
++endif
++
++# ----------------------------------------------------------
++
+ if ARCH_AT91CAP9
+ 
+ comment "AT91CAP9 Board Type"
+diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
+index a83835e..3d82460 100644
+--- a/arch/arm/mach-at91/Makefile
++++ b/arch/arm/mach-at91/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263)	+= at91sam9263.o at91sam926x_time.o at91sam9263_d
+ obj-$(CONFIG_ARCH_AT91SAM9RL)	+= at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o
+ obj-$(CONFIG_ARCH_AT91SAM9G20)	+= at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
+ obj-$(CONFIG_ARCH_AT91SAM9G45)	+= at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
++obj-$(CONFIG_ARCH_AT91SAM9X5)	+= at91sam9x5.o at91sam926x_time.o at91sam9x5_devices.o sam9_smc.o
+ obj-$(CONFIG_ARCH_AT91CAP9)	+= at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
+ obj-$(CONFIG_ARCH_AT572D940HF)  += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
+ obj-$(CONFIG_ARCH_AT91X40)	+= at91x40.o at91x40_time.o
+@@ -75,6 +76,9 @@ obj-$(CONFIG_MACH_SNAPPER_9260)	+= board-snapper9260.o
+ # AT91SAM9G45 board-specific support
+ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
+ 
++# AT91SAM9X5 board-specific support
++obj-$(CONFIG_MACH_AT91SAM9X5EK) += board-sam9x5cm.o board-sam9x5ek.o
++
+ # AT91CAP9 board-specific support
+ obj-$(CONFIG_MACH_AT91CAP9ADK)	+= board-cap9adk.o
+ 
+diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
+new file mode 100644
+index 0000000..de456e6
+--- /dev/null
++++ b/arch/arm/mach-at91/at91sam9x5.c
+@@ -0,0 +1,416 @@
++/*
++ *  Chip-specific setup code for the AT91SAM9x5 family
++ *
++ *  Copyright (C) 2010 Atmel Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/pm.h>
++
++#include <asm/irq.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <mach/at91sam9x5.h>
++#include <mach/at91_pmc.h>
++#include <mach/at91_rstc.h>
++#include <mach/at91_shdwc.h>
++#include <mach/cpu.h>
++
++#include "generic.h"
++#include "clock.h"
++
++static struct map_desc at91sam9x5_io_desc[] __initdata = {
++	{
++		.virtual	= AT91_VA_BASE_SYS,
++		.pfn		= __phys_to_pfn(AT91_BASE_SYS),
++		.length		= SZ_16K,
++		.type		= MT_DEVICE,
++	}, {
++		.virtual	= AT91_IO_VIRT_BASE - AT91SAM9X5_SRAM_SIZE,
++		.pfn		= __phys_to_pfn(AT91SAM9X5_SRAM_BASE),
++		.length		= AT91SAM9X5_SRAM_SIZE,
++		.type		= MT_DEVICE,
++	}
++};
++
++/* --------------------------------------------------------------------
++ *  Clocks
++ * -------------------------------------------------------------------- */
++
++/*
++ * The peripheral clocks.
++ */
++static struct clk pioAB_clk = {
++	.name		= "pioAB_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_PIOAB,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk pioCD_clk = {
++	.name		= "pioCD_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_PIOCD,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk smd_clk = {
++	.name		= "smd_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_SMD,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart0_clk = {
++	.name		= "usart0_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_USART0,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart1_clk = {
++	.name		= "usart1_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_USART1,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart2_clk = {
++	.name		= "usart2_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_USART2,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++/* USART3 clock - Only for sam9g25/sam9x25 */
++static struct clk usart3_clk = {
++	.name		= "usart3_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_USART3,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk twi0_clk = {
++	.name		= "twi0_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_TWI0,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk twi1_clk = {
++	.name		= "twi1_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_TWI1,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk twi2_clk = {
++	.name		= "twi2_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_TWI2,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk mmc0_clk = {
++	.name		= "mci0_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_MCI0,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk spi0_clk = {
++	.name		= "spi0_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_SPI0,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk spi1_clk = {
++	.name		= "spi1_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_SPI1,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk uart0_clk = {
++	.name		= "uart0_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_UART0,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk uart1_clk = {
++	.name		= "uart1_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_UART1,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk tcb0_clk = {
++	.name		= "tcb0_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_TCB,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk pwm_clk = {
++	.name		= "pwm_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_PWM,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk adc_clk = {
++	.name		= "adc_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_ADC,
++	.type	= CLK_TYPE_PERIPHERAL,
++};
++static struct clk dma0_clk = {
++	.name		= "dma0_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_DMA0,
++	.type	= CLK_TYPE_PERIPHERAL,
++};
++static struct clk dma1_clk = {
++	.name		= "dma1_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_DMA1,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk uhphs_clk = {
++	.name		= "uhphs_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_UHPHS,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk udphs_clk = {
++	.name		= "udphs_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_UDPHS,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
++static struct clk macb0_clk = {
++	.name		= "macb0_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_EMAC0,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
++static struct clk lcdc_clk = {
++	.name		= "lcdc_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_LCDC,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++/* isi clock - Only for sam9g25 */
++static struct clk isi_clk = {
++	.name		= "isi_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_ISI,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk mmc1_clk = {
++	.name		= "mci1_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_MCI1,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++/* emac1 clock - Only for sam9x25 */
++static struct clk macb1_clk = {
++	.name		= "macb1_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_EMAC1,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++static struct clk ssc_clk = {
++	.name		= "ssc_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_SSC,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++/* can0 clock - Only for sam9x35 */
++static struct clk can0_clk = {
++	.name		= "can0_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_CAN0,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++/* can1 clock - Only for sam9x35 */
++static struct clk can1_clk = {
++	.name		= "can1_clk",
++	.pmc_mask	= 1 << AT91SAM9X5_ID_CAN1,
++	.type		= CLK_TYPE_PERIPHERAL,
++};
++
++/* One additional fake clock for ohci */
++static struct clk ohci_clk = {
++	.name		= "ohci_clk",
++	.pmc_mask	= 0,
++	.type		= CLK_TYPE_PERIPHERAL,
++	.parent		= &uhphs_clk,
++};
++
++/* One additional fake clock for second TC block */
++static struct clk tcb1_clk = {
++	.name		= "tcb1_clk",
++	.pmc_mask	= 0,
++	.type		= CLK_TYPE_PERIPHERAL,
++	.parent		= &tcb0_clk,
++};
++
++static struct clk *periph_clocks[] __initdata = {
++	&pioAB_clk,
++	&pioCD_clk,
++	&smd_clk,
++	&usart0_clk,
++	&usart1_clk,
++	&usart2_clk,
++	&twi0_clk,
++	&twi1_clk,
++	&twi2_clk,
++	&mmc0_clk,
++	&spi0_clk,
++	&spi1_clk,
++	&uart0_clk,
++	&uart1_clk,
++	&tcb0_clk,
++	&pwm_clk,
++	&adc_clk,
++	&dma0_clk,
++	&dma1_clk,
++	&uhphs_clk,
++	&udphs_clk,
++	&mmc1_clk,
++	&ssc_clk,
++	// irq0
++	&ohci_clk,
++	&tcb1_clk,
++};
++
++/*
++ * The two programmable clocks.
++ * You must configure pin multiplexing to bring these signals out.
++ */
++static struct clk pck0 = {
++	.name		= "pck0",
++	.pmc_mask	= AT91_PMC_PCK0,
++	.type		= CLK_TYPE_PROGRAMMABLE,
++	.id		= 0,
++};
++static struct clk pck1 = {
++	.name		= "pck1",
++	.pmc_mask	= AT91_PMC_PCK1,
++	.type		= CLK_TYPE_PROGRAMMABLE,
++	.id		= 1,
++};
++
++static void __init at91sam9x5_register_clocks(void)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
++		clk_register(periph_clocks[i]);
++
++	if (cpu_is_at91sam9g25()
++	|| cpu_is_at91sam9x25())
++		clk_register(&usart3_clk);
++
++	if (cpu_is_at91sam9g25()
++	|| cpu_is_at91sam9x25()
++	|| cpu_is_at91sam9g35()
++	|| cpu_is_at91sam9x35())
++		clk_register(&macb0_clk);
++
++	if (cpu_is_at91sam9g15()
++	|| cpu_is_at91sam9g35()
++	|| cpu_is_at91sam9x35())
++		clk_register(&lcdc_clk);
++
++	if (cpu_is_at91sam9g25())
++		clk_register(&isi_clk);
++
++	if (cpu_is_at91sam9x25())
++		clk_register(&macb1_clk);
++
++	if (cpu_is_at91sam9x35()) {
++		clk_register(&can0_clk);
++		clk_register(&can1_clk);
++	}
++
++	clk_register(&pck0);
++	clk_register(&pck1);
++}
++
++/* --------------------------------------------------------------------
++ *  GPIO
++ * -------------------------------------------------------------------- */
++
++static struct at91_gpio_bank at91sam9x5_gpio[] = {
++	{
++		.id		= AT91SAM9X5_ID_PIOAB,
++		.offset		= AT91_PIOA,
++		.clock		= &pioAB_clk,
++	}, {
++		.id		= AT91SAM9X5_ID_PIOAB,
++		.offset		= AT91_PIOB,
++		.clock		= &pioAB_clk,
++	}, {
++		.id		= AT91SAM9X5_ID_PIOCD,
++		.offset		= AT91_PIOC,
++		.clock		= &pioCD_clk,
++	}, {
++		.id		= AT91SAM9X5_ID_PIOCD,
++		.offset		= AT91_PIOD,
++		.clock		= &pioCD_clk,
++	}
++};
++
++static void at91sam9x5_reset(void)
++{
++	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
++}
++
++static void at91sam9x5_poweroff(void)
++{
++	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
++}
++
++
++/* --------------------------------------------------------------------
++ *  AT91SAM9x5 processor initialization
++ * -------------------------------------------------------------------- */
++
++void __init at91sam9x5_initialize(unsigned long main_clock)
++{
++	/* Map peripherals */
++	iotable_init(at91sam9x5_io_desc, ARRAY_SIZE(at91sam9x5_io_desc));
++
++	at91_arch_reset = at91sam9x5_reset;
++	pm_power_off = at91sam9x5_poweroff;
++	at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
++
++	/* Init clock subsystem */
++	at91_clock_init(main_clock);
++
++	/* Register the processor-specific clocks */
++	at91sam9x5_register_clocks();
++
++	/* Register GPIO subsystem */
++	at91_gpio_init(at91sam9x5_gpio, 4);
++}
++
++/* --------------------------------------------------------------------
++ *  Interrupt initialization
++ * -------------------------------------------------------------------- */
++
++/*
++ * The default interrupt priority levels (0 = lowest, 7 = highest).
++ */
++static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
++	7,	/* Advanced Interrupt Controller (FIQ) */
++	7,	/* System Peripherals */
++	1,	/* Parallel IO Controller A and B */
++	1,	/* Parallel IO Controller C and D */
++	4,	/* Soft Modem */
++	5,	/* USART 0 */
++	5,	/* USART 1 */
++	5,	/* USART 2 */
++	5,	/* USART 3 */
++	6,	/* Two-Wire Interface 0 */
++	6,	/* Two-Wire Interface 1 */
++	6,	/* Two-Wire Interface 2 */
++	0,	/* Multimedia Card Interface 0 */
++	5,	/* Serial Peripheral Interface 0 */
++	5,	/* Serial Peripheral Interface 1 */
++	5,	/* UART 0 */
++	5,	/* UART 1 */
++	0,	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
++	0,	/* Pulse Width Modulation Controller */
++	0,	/* ADC COntroller */
++	0,	/* DMA Controller 0 */
++	0,	/* DMA Controller 1 */
++	2,	/* USB Host High Speed port */
++	2,	/* USB Device High speed port */
++	3,	/* Ethernet MAC 0 */
++	3,	/* LDC Controller or Image Sensor Interface */
++	0,	/* Multimedia Card Interface 1 */
++	3,	/* Ethernet MAC 1 */
++	4,	/* Synchronous Serial Interface */
++	4,	/* CAN Controller 0 */
++	4,	/* CAN Controller 1 */
++	0,	/* Advanced Interrupt Controller (IRQ0) */
++};
++
++void __init at91sam9x5_init_interrupts(unsigned int priority[NR_AIC_IRQS])
++{
++	if (!priority)
++		priority = at91sam9x5_default_irq_priority;
++
++	/* Initialize the AIC interrupt controller */
++	at91_aic_init(priority);
++
++	/* Enable GPIO interrupts */
++	at91_gpio_irq_setup();
++}
+diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
+new file mode 100644
+index 0000000..e601ae4
+--- /dev/null
++++ b/arch/arm/mach-at91/at91sam9x5_devices.c
+@@ -0,0 +1,1785 @@
++/*
++ *  On-Chip devices setup code for the AT91SAM9x5 family
++ *
++ *  Copyright (C) 2010 Atmel Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++#include <linux/i2c-gpio.h>
++#include <linux/atmel-mci.h>
++
++#include <linux/fb.h>
++#include <video/atmel_lcdc.h>
++#include <mach/atmel_hlcdfb.h>
++
++#include <mach/board.h>
++#include <mach/gpio.h>
++#include <mach/cpu.h>
++#include <mach/at91sam9x5.h>
++#include <mach/at91sam9x5_matrix.h>
++#include <mach/at91sam9_smc.h>
++#include <mach/at_hdmac.h>
++#include <mach/atmel-mci.h>
++
++#include "generic.h"
++
++/* --------------------------------------------------------------------
++ *  HDMAC - AHB DMA Controller
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
++static u64 hdmac_dmamask = DMA_BIT_MASK(32);
++
++/* a single platform data for both DMA controllers as they share
++ * the same characteristics */
++static struct at_dma_platform_data atdma_pdata = {
++	.nr_channels	= 8,
++};
++
++static struct resource hdmac0_resources[] = {
++	[0] = {
++		.start	= AT91_BASE_SYS + AT91_DMA0,
++		.end	= AT91_BASE_SYS + AT91_DMA0 + SZ_512 - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_DMA0,
++		.end	= AT91SAM9X5_ID_DMA0,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at_hdmac0_device = {
++	.name		= "at_hdmac",
++	.id		= 0,
++	.dev		= {
++				.dma_mask		= &hdmac_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &atdma_pdata,
++	},
++	.resource	= hdmac0_resources,
++	.num_resources	= ARRAY_SIZE(hdmac0_resources),
++};
++
++static struct resource hdmac1_resources[] = {
++	[0] = {
++		.start	= AT91_BASE_SYS + AT91_DMA1,
++		.end	= AT91_BASE_SYS + AT91_DMA1 + SZ_512 - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_DMA1,
++		.end	= AT91SAM9X5_ID_DMA1,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at_hdmac1_device = {
++	.name	= "at_hdmac",
++	.id	= 1,
++	.dev	= {
++			.dma_mask			= &hdmac_dmamask,
++			.coherent_dma_mask		= DMA_BIT_MASK(32),
++			.platform_data			= &atdma_pdata,
++	},
++	.resource	= hdmac1_resources,
++	.num_resources	= ARRAY_SIZE(hdmac1_resources),
++};
++
++void __init at91_add_device_hdmac(void)
++{
++	dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
++	dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
++	dma_cap_set(DMA_CYCLIC, atdma_pdata.cap_mask);
++	at91_clock_associate("dma0_clk", &at_hdmac0_device.dev, "dma_clk");
++	platform_device_register(&at_hdmac0_device);
++	at91_clock_associate("dma1_clk", &at_hdmac1_device.dev, "dma_clk");
++	platform_device_register(&at_hdmac1_device);
++}
++#else
++void __init at91_add_device_hdmac(void) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ *  USB Host (OHCI)
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
++static u64 ohci_dmamask = DMA_BIT_MASK(32);
++static struct at91_usbh_data usbh_ohci_data;
++
++static struct resource usbh_ohci_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_OHCI_BASE,
++		.end	= AT91SAM9X5_OHCI_BASE + SZ_1M - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_UHPHS,
++		.end	= AT91SAM9X5_ID_UHPHS,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91_usbh_ohci_device = {
++	.name		= "at91_ohci",
++	.id		= -1,
++	.dev		= {
++				.dma_mask		= &ohci_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &usbh_ohci_data,
++	},
++	.resource	= usbh_ohci_resources,
++	.num_resources	= ARRAY_SIZE(usbh_ohci_resources),
++};
++
++void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
++{
++	int i;
++
++	if (!data)
++		return;
++
++	/* Enable VBus control for UHP ports */
++	for (i = 0; i < data->ports; i++) {
++		if (data->vbus_pin[i])
++			at91_set_gpio_output(data->vbus_pin[i], 0);
++	}
++
++	usbh_ohci_data = *data;
++	platform_device_register(&at91_usbh_ohci_device);
++}
++#else
++void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ *  USB Host HS (EHCI)
++ *  Needs an OHCI host for low and full speed management
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
++static u64 ehci_dmamask = DMA_BIT_MASK(32);
++static struct at91_usbh_data usbh_ehci_data;
++
++static struct resource usbh_ehci_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_EHCI_BASE,
++		.end	= AT91SAM9X5_EHCI_BASE + SZ_1M - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_UHPHS,
++		.end	= AT91SAM9X5_ID_UHPHS,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91_usbh_ehci_device = {
++	.name		= "atmel-ehci",
++	.id		= -1,
++	.dev		= {
++				.dma_mask		= &ehci_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &usbh_ehci_data,
++	},
++	.resource	= usbh_ehci_resources,
++	.num_resources	= ARRAY_SIZE(usbh_ehci_resources),
++};
++
++void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
++{
++	int i;
++
++	if (!data)
++		return;
++
++	/* Enable VBus control for UHP ports */
++	for (i = 0; i < data->ports; i++) {
++		if (data->vbus_pin[i])
++			at91_set_gpio_output(data->vbus_pin[i], 0);
++	}
++
++	usbh_ehci_data = *data;
++	at91_clock_associate("uhphs_clk", &at91_usbh_ehci_device.dev, "ehci_clk");
++	platform_device_register(&at91_usbh_ehci_device);
++}
++#else
++void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ *  USB HS Device (Gadget)
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
++static struct resource usba_udc_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_UDPHS_FIFO,
++		.end	= AT91SAM9X5_UDPHS_FIFO + SZ_512K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_BASE_UDPHS,
++		.end	= AT91SAM9X5_BASE_UDPHS + SZ_1K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[2] = {
++		.start	= AT91SAM9X5_ID_UDPHS,
++		.end	= AT91SAM9X5_ID_UDPHS,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++#define EP(nam, idx, maxpkt, maxbk, dma, isoc)			\
++	[idx] = {						\
++		.name		= nam,				\
++		.index		= idx,				\
++		.fifo_size	= maxpkt,			\
++		.nr_banks	= maxbk,			\
++		.can_dma	= dma,				\
++		.can_isoc	= isoc,				\
++	}
++
++static struct usba_ep_data usba_udc_ep[] __initdata = {
++	EP("ep0", 0, 64, 1, 0, 0),
++	EP("ep1", 1, 1024, 2, 1, 1),
++	EP("ep2", 2, 1024, 2, 1, 1),
++	EP("ep3", 3, 1024, 3, 1, 0),
++	EP("ep4", 4, 1024, 3, 1, 0),
++	EP("ep5", 5, 1024, 3, 1, 1),
++	EP("ep6", 6, 1024, 3, 1, 1),
++};
++
++#undef EP
++
++/*
++ * pdata doesn't have room for any endpoints, so we need to
++ * append room for the ones we need right after it.
++ */
++static struct {
++	struct usba_platform_data pdata;
++	struct usba_ep_data ep[7];
++} usba_udc_data;
++
++static struct platform_device at91_usba_udc_device = {
++	.name		= "atmel_usba_udc",
++	.id		= -1,
++	.dev		= {
++				.platform_data	= &usba_udc_data.pdata,
++	},
++	.resource	= usba_udc_resources,
++	.num_resources	= ARRAY_SIZE(usba_udc_resources),
++};
++
++void __init at91_add_device_usba(struct usba_platform_data *data)
++{
++	usba_udc_data.pdata.vbus_pin = -EINVAL;
++	usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
++	memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
++
++	if (data && data->vbus_pin > 0) {
++		at91_set_gpio_input(data->vbus_pin, 0);
++		at91_set_deglitch(data->vbus_pin, 1);
++		usba_udc_data.pdata.vbus_pin = data->vbus_pin;
++	}
++
++	/* Pullup pin is handled internally by USB device peripheral */
++
++	/* Clocks */
++	at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
++	at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
++
++	platform_device_register(&at91_usba_udc_device);
++}
++#else
++void __init at91_add_device_usba(struct usba_platform_data *data) {}
++#endif
++
++/* --------------------------------------------------------------------
++ *  Ethernet
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
++static u64 eth0_dmamask = DMA_BIT_MASK(32);
++static struct at91_eth_data eth0_data;
++
++static struct resource eth0_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_EMAC0,
++		.end	= AT91SAM9X5_BASE_EMAC0 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_EMAC0,
++		.end	= AT91SAM9X5_ID_EMAC0,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_eth0_device = {
++	.name		= "macb",
++	.id		= 0,
++	.dev		= {
++				.dma_mask		= &eth0_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &eth0_data,
++	},
++	.resource	= eth0_resources,
++	.num_resources	= ARRAY_SIZE(eth0_resources),
++};
++
++static u64 eth1_dmamask = DMA_BIT_MASK(32);
++static struct at91_eth_data eth1_data;
++
++static struct resource eth1_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_EMAC1,
++		.end	= AT91SAM9X5_BASE_EMAC1 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_EMAC1,
++		.end	= AT91SAM9X5_ID_EMAC1,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_eth1_device = {
++	.name		= "macb",
++	.id		= 1,
++	.dev		= {
++				.dma_mask		= &eth1_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &eth1_data,
++	},
++	.resource	= eth1_resources,
++	.num_resources	= ARRAY_SIZE(eth1_resources),
++};
++
++void __init at91_add_device_eth(short eth_id, struct at91_eth_data *data)
++{
++	if (!data)
++		return;
++
++	if (cpu_is_at91sam9g15())
++		return;
++
++	if (eth_id && !cpu_is_at91sam9x25())
++		return;
++
++	if (data->phy_irq_pin) {
++		at91_set_gpio_input(data->phy_irq_pin, 0);
++		at91_set_deglitch(data->phy_irq_pin, 1);
++	}
++
++	if (eth_id == 0) {
++		/* Pins used for MII and RMII */
++		at91_set_A_periph(AT91_PIN_PB4,  0);	/* ETXCK_EREFCK */
++		at91_set_A_periph(AT91_PIN_PB3,  0);	/* ERXDV */
++		at91_set_A_periph(AT91_PIN_PB0,  0);	/* ERX0 */
++		at91_set_A_periph(AT91_PIN_PB1,  0);	/* ERX1 */
++		at91_set_A_periph(AT91_PIN_PB2,  0);	/* ERXER */
++		at91_set_A_periph(AT91_PIN_PB7,  0);	/* ETXEN */
++		at91_set_A_periph(AT91_PIN_PB9,  0);	/* ETX0 */
++		at91_set_A_periph(AT91_PIN_PB10, 0);	/* ETX1 */
++		at91_set_A_periph(AT91_PIN_PB5,  0);	/* EMDIO */
++		at91_set_A_periph(AT91_PIN_PB6,  0);	/* EMDC */
++
++		if (!data->is_rmii) {
++			at91_set_A_periph(AT91_PIN_PB16, 0);	/* ECRS */
++			at91_set_A_periph(AT91_PIN_PB17, 0);	/* ECOL */
++			at91_set_A_periph(AT91_PIN_PB13, 0);	/* ERX2 */
++			at91_set_A_periph(AT91_PIN_PB14, 0);	/* ERX3 */
++			at91_set_A_periph(AT91_PIN_PB15, 0);	/* ERXCK */
++			at91_set_A_periph(AT91_PIN_PB11, 0);	/* ETX2 */
++			at91_set_A_periph(AT91_PIN_PB12, 0);	/* ETX3 */
++			at91_set_A_periph(AT91_PIN_PB8,  0);	/* ETXER */
++		}
++
++		/* Clock */
++		at91_clock_associate("macb0_clk", &at91sam9x5_eth0_device.dev, "macb_clk");
++
++		eth0_data = *data;
++		platform_device_register(&at91sam9x5_eth0_device);
++	} else {
++		if (!data->is_rmii)
++			pr_warn("AT91: Only RMII available on interface %s %d.\n",
++				at91sam9x5_eth0_device.name, eth_id);
++
++		/* Pins used for RMII */
++		at91_set_B_periph(AT91_PIN_PC29,  0);	/* ETXCK_EREFCK */
++		at91_set_B_periph(AT91_PIN_PC28,  0);	/* ECRSDV */
++		at91_set_B_periph(AT91_PIN_PC20,  0);	/* ERX0 */
++		at91_set_B_periph(AT91_PIN_PC21,  0);	/* ERX1 */
++		at91_set_B_periph(AT91_PIN_PC16,  0);	/* ERXER */
++		at91_set_B_periph(AT91_PIN_PC27,  0);	/* ETXEN */
++		at91_set_B_periph(AT91_PIN_PC18,  0);	/* ETX0 */
++		at91_set_B_periph(AT91_PIN_PC19,  0);	/* ETX1 */
++		at91_set_B_periph(AT91_PIN_PC31,  0);	/* EMDIO */
++		at91_set_B_periph(AT91_PIN_PC30,  0);	/* EMDC */
++
++		/* Clock */
++		at91_clock_associate("macb1_clk", &at91sam9x5_eth1_device.dev, "macb_clk");
++
++		eth1_data = *data;
++		platform_device_register(&at91sam9x5_eth1_device);
++	}
++}
++#else
++void __init at91_add_device_eth(short eth_id, struct at91_eth_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ *  MMC / SD
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
++static u64 mmc_dmamask = DMA_BIT_MASK(32);
++static struct mci_platform_data mmc0_data, mmc1_data;
++
++static struct resource mmc0_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_MCI0,
++		.end	= AT91SAM9X5_BASE_MCI0 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_MCI0,
++		.end	= AT91SAM9X5_ID_MCI0,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_mmc0_device = {
++	.name		= "atmel_mci",
++	.id		= 0,
++	.dev		= {
++				.dma_mask		= &mmc_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &mmc0_data,
++	},
++	.resource	= mmc0_resources,
++	.num_resources	= ARRAY_SIZE(mmc0_resources),
++};
++
++static struct resource mmc1_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_MCI1,
++		.end	= AT91SAM9X5_BASE_MCI1 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_MCI1,
++		.end	= AT91SAM9X5_ID_MCI1,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_mmc1_device = {
++	.name		= "atmel_mci",
++	.id		= 1,
++	.dev		= {
++				.dma_mask		= &mmc_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &mmc1_data,
++	},
++	.resource	= mmc1_resources,
++	.num_resources	= ARRAY_SIZE(mmc1_resources),
++};
++
++/* Consider only one slot : slot 0 */
++void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
++{
++
++	if (!data)
++		return;
++
++	/* Must have at least one usable slot */
++	if (!data->slot[0].bus_width)
++		return;
++
++#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
++	{
++	struct at_dma_slave	*atslave;
++	struct mci_dma_data	*alt_atslave;
++
++	alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
++	atslave = &alt_atslave->sdata;
++
++	/* DMA slave channel configuration */
++	atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
++	atslave->cfg = ATC_FIFOCFG_HALFFIFO
++			| ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
++	atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
++	if (mmc_id == 0) {	/* MCI0 */
++		atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
++			      | ATC_DST_PER(AT_DMA_ID_MCI0);
++		atslave->dma_dev = &at_hdmac0_device.dev;
++
++	} else {		/* MCI1 */
++		atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
++			      | ATC_DST_PER(AT_DMA_ID_MCI1);
++		atslave->dma_dev = &at_hdmac1_device.dev;
++	}
++
++	data->dma_slave = alt_atslave;
++	}
++#endif
++
++	/* input/irq */
++	if (data->slot[0].detect_pin) {
++		at91_set_gpio_input(data->slot[0].detect_pin, 1);
++		at91_set_deglitch(data->slot[0].detect_pin, 1);
++	}
++	if (data->slot[0].wp_pin)
++		at91_set_gpio_input(data->slot[0].wp_pin, 1);
++
++	if (mmc_id == 0) {		/* MCI0 */
++
++		/* CLK */
++		at91_set_A_periph(AT91_PIN_PA17, 0);
++
++		/* CMD */
++		at91_set_A_periph(AT91_PIN_PA16, 1);
++
++		/* DAT0, maybe DAT1..DAT3 */
++		at91_set_A_periph(AT91_PIN_PA15, 1);
++		if (data->slot[0].bus_width == 4) {
++			at91_set_A_periph(AT91_PIN_PA18, 1);
++			at91_set_A_periph(AT91_PIN_PA19, 1);
++			at91_set_A_periph(AT91_PIN_PA20, 1);
++		}
++
++		mmc0_data = *data;
++		at91_clock_associate("mci0_clk", &at91sam9x5_mmc0_device.dev, "mci_clk");
++		platform_device_register(&at91sam9x5_mmc0_device);
++
++	} else {			/* MCI1 */
++
++		/* CLK */
++		at91_set_B_periph(AT91_PIN_PA13, 0);
++
++		/* CMD */
++		at91_set_B_periph(AT91_PIN_PA12, 1);
++
++		/* DAT0, maybe DAT1..DAT3 */
++		at91_set_B_periph(AT91_PIN_PA11, 1);
++		if (data->slot[0].bus_width == 4) {
++			at91_set_B_periph(AT91_PIN_PA2, 1);
++			at91_set_B_periph(AT91_PIN_PA3, 1);
++			at91_set_B_periph(AT91_PIN_PA4, 1);
++		}
++
++		mmc1_data = *data;
++		at91_clock_associate("mci1_clk", &at91sam9x5_mmc1_device.dev, "mci_clk");
++		platform_device_register(&at91sam9x5_mmc1_device);
++
++	}
++}
++#else
++void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ *  NAND / SmartMedia
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
++static struct atmel_nand_data nand_data;
++
++#define NAND_BASE	AT91_CHIPSELECT_3
++
++static struct resource nand_resources[] = {
++	[0] = {
++		.start	= NAND_BASE,
++		.end	= NAND_BASE + SZ_256M - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91_BASE_SYS + AT91_PMECC,
++		.end	= AT91_BASE_SYS + AT91_PMECC + SZ_512 - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[2] = {
++		.start	= AT91_BASE_SYS + AT91_PMERRLOC,
++		.end	= AT91_BASE_SYS + AT91_PMERRLOC + SZ_512 - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[3] = {
++		.start	= AT91SAM9X5_ROM_BASE,
++		.end	= AT91SAM9X5_ROM_BASE + AT91SAM9X5_ROM_SIZE,
++		.flags	= IORESOURCE_MEM,
++	}
++};
++
++static struct platform_device at91sam9x5_nand_device = {
++	.name		= "atmel_nand",
++	.id		= -1,
++	.dev		= {
++				.platform_data	= &nand_data,
++	},
++	.resource	= nand_resources,
++	.num_resources	= ARRAY_SIZE(nand_resources),
++};
++
++void __init at91_add_device_nand(struct atmel_nand_data *data)
++{
++	unsigned long csa;
++
++	if (!data)
++		return;
++
++	csa = at91_sys_read(AT91_MATRIX_EBICSA);
++	csa |= AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH;
++
++	if (!data->bus_on_d0) {
++		csa |= AT91_MATRIX_NFD0_ON_D16;
++	       if (!data->bus_width_16)
++			csa |= AT91_MATRIX_MP_ON;
++	} else
++		csa &= ~(AT91_MATRIX_NFD0_ON_D16 | AT91_MATRIX_MP_ON);
++
++	at91_sys_write(AT91_MATRIX_EBICSA, csa);
++
++	/* enable pin */
++	if (data->enable_pin)
++		at91_set_gpio_output(data->enable_pin, 1);
++
++	/* ready/busy pin */
++	if (data->rdy_pin)
++		at91_set_gpio_input(data->rdy_pin, 1);
++
++	/* card detect pin */
++	if (data->det_pin)
++		at91_set_gpio_input(data->det_pin, 1);
++
++	/* configure NANDOE */
++	at91_set_A_periph(AT91_PIN_PD0, 1);
++	/* configure NANDWE */
++	at91_set_A_periph(AT91_PIN_PD1, 1);
++	/* configure ALE */
++	at91_set_A_periph(AT91_PIN_PD2, 1);
++	/* configure CLE */
++	at91_set_A_periph(AT91_PIN_PD3, 1);
++
++	/* configure multiplexed pins for D16~D31 */
++	if (!data->bus_on_d0) {
++		at91_set_A_periph(AT91_PIN_PD6, 1);
++		at91_set_A_periph(AT91_PIN_PD7, 1);
++		at91_set_A_periph(AT91_PIN_PD8, 1);
++		at91_set_A_periph(AT91_PIN_PD9, 1);
++		at91_set_A_periph(AT91_PIN_PD10, 1);
++		at91_set_A_periph(AT91_PIN_PD11, 1);
++		at91_set_A_periph(AT91_PIN_PD12, 1);
++		at91_set_A_periph(AT91_PIN_PD13, 1);
++
++		if (data->bus_width_16) {
++			at91_set_A_periph(AT91_PIN_PD14, 1);
++			at91_set_A_periph(AT91_PIN_PD15, 1);
++			at91_set_A_periph(AT91_PIN_PD16, 1);
++			at91_set_A_periph(AT91_PIN_PD17, 1);
++			at91_set_A_periph(AT91_PIN_PD18, 1);
++			at91_set_A_periph(AT91_PIN_PD19, 1);
++			at91_set_A_periph(AT91_PIN_PD20, 1);
++			at91_set_A_periph(AT91_PIN_PD21, 1);
++		}
++
++	}
++
++	nand_data = *data;
++	platform_device_register(&at91sam9x5_nand_device);
++}
++#else
++void __init at91_add_device_nand(struct atmel_nand_data *data) {}
++#endif
++
++/* --------------------------------------------------------------------
++ *  TWI (i2c)
++ * -------------------------------------------------------------------- */
++
++/*
++ * Prefer the GPIO code since the TWI controller isn't robust
++ * (gets overruns and underruns under load) and can only issue
++ * repeated STARTs in one scenario (the driver doesn't yet handle them).
++ */
++#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
++static struct i2c_gpio_platform_data pdata_i2c0 = {
++	.sda_pin		= AT91_PIN_PA30,
++	.sda_is_open_drain	= 1,
++	.scl_pin		= AT91_PIN_PA31,
++	.scl_is_open_drain	= 1,
++	.udelay			= 2,		/* ~100 kHz */
++};
++
++static struct platform_device at91sam9x5_twi0_device = {
++	.name			= "i2c-gpio",
++	.id			= 0,
++	.dev.platform_data	= &pdata_i2c0,
++};
++
++void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
++{
++	i2c_register_board_info(i2c_id, devices, nr_devices);
++
++	if (i2c_id == 0) {
++		at91_set_GPIO_periph(AT91_PIN_PA30, 1);		/* TWD (SDA) */
++		at91_set_multi_drive(AT91_PIN_PA30, 1);
++
++		at91_set_GPIO_periph(AT91_PIN_PA31, 1);		/* TWCK (SCL) */
++		at91_set_multi_drive(AT91_PIN_PA31, 1);
++
++		platform_device_register(&at91sam9x5_twi0_device);
++	}
++}
++
++#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
++static struct resource twi0_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_TWI0,
++		.end	= AT91SAM9X5_BASE_TWI0 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_TWI0,
++		.end	= AT91SAM9X5_ID_TWI0,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_twi0_device = {
++	.name		= "at91_i2c",
++	.id		= 0,
++	.resource	= twi0_resources,
++	.num_resources	= ARRAY_SIZE(twi0_resources),
++};
++
++void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
++{
++	i2c_register_board_info(i2c_id, devices, nr_devices);
++
++	/* pins used for TWI interface */
++	if (i2c_id == 0) {
++		at91_set_A_periph(AT91_PIN_PA30, 0);		/* TWD */
++		at91_set_multi_drive(AT91_PIN_PA30, 1);
++
++		at91_set_A_periph(AT91_PIN_PA31, 0);		/* TWCK */
++		at91_set_multi_drive(AT91_PIN_PA31, 1);
++
++		platform_device_register(&at91sam9x5_twi0_device);
++	}
++}
++#else
++void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
++#endif
++
++/* --------------------------------------------------------------------
++ *  SPI
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
++static u64 spi_dmamask = DMA_BIT_MASK(32);
++static struct at_dma_slave spi0_sdata, spi1_sdata;
++
++static struct resource spi0_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_SPI0,
++		.end	= AT91SAM9X5_BASE_SPI0 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_SPI0,
++		.end	= AT91SAM9X5_ID_SPI0,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_spi0_device = {
++	.name		= "atmel_spi",
++	.id		= 0,
++	.dev		= {
++				.dma_mask		= &spi_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &spi0_sdata,
++	},
++	.resource	= spi0_resources,
++	.num_resources	= ARRAY_SIZE(spi0_resources),
++};
++
++static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA14, AT91_PIN_PA7, AT91_PIN_PA1, AT91_PIN_PB3 };
++
++static struct resource spi1_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_SPI1,
++		.end	= AT91SAM9X5_BASE_SPI1 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_SPI1,
++		.end	= AT91SAM9X5_ID_SPI1,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_spi1_device = {
++	.name		= "atmel_spi",
++	.id		= 1,
++	.dev		= {
++				.dma_mask		= &spi_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &spi1_sdata,
++	},
++	.resource	= spi1_resources,
++	.num_resources	= ARRAY_SIZE(spi1_resources),
++};
++
++static const unsigned spi1_standard_cs[4] = { AT91_PIN_PA8, AT91_PIN_PA0, AT91_PIN_PA31, AT91_PIN_PA30 };
++
++void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
++{
++	int i;
++	unsigned long cs_pin;
++	short enable_spi0 = 0;
++	short enable_spi1 = 0;
++#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
++	struct at_dma_slave *atslave;
++#endif
++
++	/* Choose SPI chip-selects */
++	for (i = 0; i < nr_devices; i++) {
++		if (devices[i].controller_data)
++			cs_pin = (unsigned long) devices[i].controller_data;
++		else if (devices[i].bus_num == 0)
++			cs_pin = spi0_standard_cs[devices[i].chip_select];
++		else
++			cs_pin = spi1_standard_cs[devices[i].chip_select];
++
++		if (devices[i].bus_num == 0)
++			enable_spi0 = 1;
++		else
++			enable_spi1 = 1;
++
++		/* enable chip-select pin */
++		at91_set_gpio_output(cs_pin, 1);
++
++		/* pass chip-select pin to driver */
++		devices[i].controller_data = (void *) cs_pin;
++	}
++
++	spi_register_board_info(devices, nr_devices);
++
++
++	/* Configure SPI bus(es) */
++	if (enable_spi0) {
++		at91_set_A_periph(AT91_PIN_PA11, 0);	/* SPI0_MISO */
++		at91_set_A_periph(AT91_PIN_PA12, 0);	/* SPI0_MOSI */
++		at91_set_A_periph(AT91_PIN_PA13, 0);	/* SPI0_SPCK */
++
++#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
++		atslave = at91sam9x5_spi0_device.dev.platform_data;
++
++		/* DMA slave channel configuration */
++		atslave->dma_dev = &at_hdmac0_device.dev;
++		atslave->reg_width = AT_DMA_SLAVE_WIDTH_8BIT; /* or 16bits??????? */
++		atslave->cfg = ATC_FIFOCFG_HALFFIFO
++				| ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW
++				| ATC_SRC_PER(AT_DMA_ID_SPI0_RX)
++				| ATC_DST_PER(AT_DMA_ID_SPI0_TX);
++		/*atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;*/ /* Chunk size to 0????? */
++#endif
++
++		at91_clock_associate("spi0_clk", &at91sam9x5_spi0_device.dev, "spi_clk");
++		platform_device_register(&at91sam9x5_spi0_device);
++	}
++	if (enable_spi1) {
++		at91_set_B_periph(AT91_PIN_PA21, 0);	/* SPI1_MISO */
++		at91_set_B_periph(AT91_PIN_PA22, 0);	/* SPI1_MOSI */
++		at91_set_B_periph(AT91_PIN_PA23, 0);	/* SPI1_SPCK */
++
++#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
++		atslave = at91sam9x5_spi1_device.dev.platform_data;
++
++		/* DMA slave channel configuration */
++		atslave->dma_dev = &at_hdmac1_device.dev;
++		atslave->reg_width = AT_DMA_SLAVE_WIDTH_8BIT; /* or 16bits??????? */
++		atslave->cfg = ATC_FIFOCFG_HALFFIFO
++				| ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW
++				| ATC_SRC_PER(AT_DMA_ID_SPI1_RX)
++				| ATC_DST_PER(AT_DMA_ID_SPI1_TX);
++		/*atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;*/ /* Chunk size to 0????? */
++#endif
++
++		at91_clock_associate("spi1_clk", &at91sam9x5_spi1_device.dev, "spi_clk");
++		platform_device_register(&at91sam9x5_spi1_device);
++	}
++}
++#else
++void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * CAN Controllers
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_CAN_AT91) || defined(CONFIG_CAN_AT91_MODULE)
++static struct resource can_resources[][2] = {
++	{
++		{
++			.start	= AT91SAM9X5_BASE_CAN0,
++			.end	= AT91SAM9X5_BASE_CAN0 + SZ_16K - 1,
++			.flags	= IORESOURCE_MEM,
++		}, {
++			.start	= AT91SAM9X5_ID_CAN0,
++			.end	= AT91SAM9X5_ID_CAN0,
++			.flags	= IORESOURCE_IRQ,
++		},
++	}, {
++		{
++			.start	= AT91SAM9X5_BASE_CAN1,
++			.end	= AT91SAM9X5_BASE_CAN1 + SZ_16K - 1,
++			.flags	= IORESOURCE_MEM,
++		}, {
++			.start	= AT91SAM9X5_ID_CAN1,
++			.end	= AT91SAM9X5_ID_CAN1,
++			.flags	= IORESOURCE_IRQ,
++		},
++	},
++};
++
++static struct platform_device at91sam9x5_can_device[] = {
++	{
++		.name = "at91sam9x5_can",
++		.id = 0,
++		.resource = can_resources[0],
++		.num_resources = ARRAY_SIZE(can_resources[0]),
++	}, {
++		.name = "at91sam9x5_can",
++		.id = 1,
++		.resource = can_resources[1],
++		.num_resources = ARRAY_SIZE(can_resources[1]),
++	},
++};
++
++static const struct {
++	unsigned txpin;
++	unsigned rxpin;
++} at91sam9x5_can_pins[] __initconst = {
++	{
++		.txpin = AT91_PIN_PA10,
++		.rxpin = AT91_PIN_PA9,
++	}, {
++		.txpin = AT91_PIN_PA5,
++		.rxpin = AT91_PIN_PA6,
++	},
++};
++
++void __init at91_add_device_can(int id, struct at91_can_data *data)
++{
++	at91_clock_associate("can0_clk", &at91sam9x5_can_device[0].dev, "can_clk");
++	at91_clock_associate("can1_clk", &at91sam9x5_can_device[1].dev, "can_clk");
++	at91_set_B_periph(at91sam9x5_can_pins[id].txpin, 0);
++	at91_set_B_periph(at91sam9x5_can_pins[id].rxpin, 0);
++	at91sam9x5_can_device[id].dev.platform_data = data;
++
++	platform_device_register(&at91sam9x5_can_device[id]);
++}
++#else
++void __init at91_add_device_can(int id, struct at91_can_data *data) {}
++#endif
++
++/* --------------------------------------------------------------------
++ *  LCD Controller
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
++static u64 lcdc_dmamask = DMA_BIT_MASK(32);
++static struct atmel_lcdfb_info lcdc_data;
++
++static struct resource lcdc_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_LCDC,
++		.end	= AT91SAM9X5_BASE_LCDC + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_LCDC,
++		.end	= AT91SAM9X5_ID_LCDC,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91_lcdc_device = {
++	.name		= "atmel_lcdfb",
++	.id		= 0,
++	.dev		= {
++				.dma_mask		= &lcdc_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &lcdc_data,
++	},
++	.resource	= lcdc_resources,
++	.num_resources	= ARRAY_SIZE(lcdc_resources),
++};
++
++void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
++{
++	if (!data)
++		return;
++
++	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDPWM */
++
++	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDVSYNC */
++	at91_set_A_periph(AT91_PIN_PC28, 0);	/* LCDHSYNC */
++
++	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDDISP */
++	at91_set_A_periph(AT91_PIN_PC29, 0);	/* LCDDEN */
++	at91_set_A_periph(AT91_PIN_PC30, 0);	/* LCDPCK */
++
++	at91_set_A_periph(AT91_PIN_PC0, 0);	/* LCDD0 */
++	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDD1 */
++	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDD2 */
++	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDD3 */
++	at91_set_A_periph(AT91_PIN_PC4, 0);	/* LCDD4 */
++	at91_set_A_periph(AT91_PIN_PC5, 0);	/* LCDD5 */
++	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD6 */
++	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD7 */
++	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD8 */
++	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD9 */
++	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD10 */
++	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD11 */
++	at91_set_A_periph(AT91_PIN_PC12, 0);	/* LCDD12 */
++	at91_set_A_periph(AT91_PIN_PC13, 0);	/* LCDD13 */
++	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD14 */
++	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD15 */
++	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD16 */
++	at91_set_A_periph(AT91_PIN_PC17, 0);	/* LCDD17 */
++	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD18 */
++	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD19 */
++	at91_set_A_periph(AT91_PIN_PC20, 0);	/* LCDD20 */
++	at91_set_A_periph(AT91_PIN_PC21, 0);	/* LCDD21 */
++	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD22 */
++	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD23 */
++
++	lcdc_data = *data;
++	platform_device_register(&at91_lcdc_device);
++}
++#else
++void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
++#endif
++
++/* --------------------------------------------------------------------
++ *  Timer/Counter block
++ * -------------------------------------------------------------------- */
++
++#ifdef CONFIG_ATMEL_TCLIB
++static struct resource tcb0_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_TCB0,
++		.end	= AT91SAM9X5_BASE_TCB0 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_TCB,
++		.end	= AT91SAM9X5_ID_TCB,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_tcb0_device = {
++	.name		= "atmel_tcb",
++	.id		= 0,
++	.resource	= tcb0_resources,
++	.num_resources	= ARRAY_SIZE(tcb0_resources),
++};
++
++/* TCB1 begins with TC3 */
++static struct resource tcb1_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_TCB1,
++		.end	= AT91SAM9X5_BASE_TCB1 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_TCB,
++		.end	= AT91SAM9X5_ID_TCB,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_tcb1_device = {
++	.name		= "atmel_tcb",
++	.id		= 1,
++	.resource	= tcb1_resources,
++	.num_resources	= ARRAY_SIZE(tcb1_resources),
++};
++
++static void __init at91_add_device_tc(void)
++{
++	/* this chip has one clock and irq for all six TC channels */
++	at91_clock_associate("tcb0_clk", &at91sam9x5_tcb0_device.dev, "t0_clk");
++	platform_device_register(&at91sam9x5_tcb0_device);
++	at91_clock_associate("tcb1_clk", &at91sam9x5_tcb1_device.dev, "t0_clk");
++	platform_device_register(&at91sam9x5_tcb1_device);
++}
++#else
++static void __init at91_add_device_tc(void) { }
++#endif
++
++/* --------------------------------------------------------------------
++ *  RTC
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
++static struct platform_device at91sam9x5_rtc_device = {
++	.name		= "at91_rtc",
++	.id		= -1,
++	.num_resources	= 0,
++};
++
++static void __init at91_add_device_rtc(void)
++{
++	platform_device_register(&at91sam9x5_rtc_device);
++}
++#else
++static void __init at91_add_device_rtc(void) {}
++#endif
++
++/* --------------------------------------------------------------------
++ *  Touchscreen
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
++static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
++static struct at91_tsadcc_data tsadcc_data;
++
++static struct resource tsadcc_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_ADC,
++		.end	= AT91SAM9X5_BASE_ADC + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_ADC,
++		.end	= AT91SAM9X5_ID_ADC,
++		.flags	= IORESOURCE_IRQ,
++	}
++};
++
++static struct platform_device at91sam9x5_tsadcc_device = {
++	.name		= "atmel_tsadcc",
++	.id		= -1,
++	.dev		= {
++				.dma_mask		= &tsadcc_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &tsadcc_data,
++	},
++	.resource	= tsadcc_resources,
++	.num_resources	= ARRAY_SIZE(tsadcc_resources),
++};
++
++void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
++{
++	if (!data)
++		return;
++
++	/* In 9x5ek, using default pins for touch screen. */
++
++	tsadcc_data = *data;
++	at91_clock_associate("adc_clk", &at91sam9x5_tsadcc_device.dev, "tsc_clk");
++	platform_device_register(&at91sam9x5_tsadcc_device);
++}
++#else
++void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
++#endif
++
++/* --------------------------------------------------------------------
++ *  Watchdog
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
++static struct platform_device at91sam9x5_wdt_device = {
++	.name		= "at91_wdt",
++	.id		= -1,
++	.num_resources	= 0,
++};
++
++static void __init at91_add_device_watchdog(void)
++{
++	platform_device_register(&at91sam9x5_wdt_device);
++}
++#else
++static void __init at91_add_device_watchdog(void) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ *  PWM
++ * --------------------------------------------------------------------*/
++
++#if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
++static u32 pwm_mask;
++
++static struct resource pwm_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_PWMC,
++		.end	= AT91SAM9X5_BASE_PWMC + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_PWMC,
++		.end	= AT91SAM9X5_ID_PWMC,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_pwm_device = {
++	.name	= "atmel_pwm",
++	.id	= -1,
++	.dev	= {
++		.platform_data		= &pwm_mask,
++	},
++	.resource	= pwm_resources,
++	.num_resources	= ARRAY_SIZE(pwm_resources),
++};
++
++void __init at91_add_device_pwm(u32 mask)
++{
++	if (mask & (1 << AT91_PWM0))
++		at91_set_B_periph(AT91_PIN_PB11, 1);	/* enable PWM0 */
++
++	if (mask & (1 << AT91_PWM1))
++		at91_set_B_periph(AT91_PIN_PB12, 1);	/* enable PWM1 */
++
++	if (mask & (1 << AT91_PWM2))
++		at91_set_B_periph(AT91_PIN_PB13, 1);	/* enable PWM2 */
++
++	if (mask & (1 << AT91_PWM3))
++		at91_set_B_periph(AT91_PIN_PB14, 1);	/* enable PWM3 */
++
++	pwm_mask = mask;
++
++	platform_device_register(&at91sam9x5_pwm_device);
++}
++#else
++void __init at91_add_device_pwm(u32 mask) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ *  SSC -- Synchronous Serial Controller
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
++static u64 ssc_dmamask = DMA_BIT_MASK(32);
++static struct at_dma_slave ssc_sdata;
++
++static struct resource ssc_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_SSC,
++		.end	= AT91SAM9X5_BASE_SSC + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_SSC,
++		.end	= AT91SAM9X5_ID_SSC,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_ssc_device = {
++	.name	= "ssc",
++	.id	= 0,
++	.dev	= {
++		.dma_mask		= &ssc_dmamask,
++		.coherent_dma_mask	= DMA_BIT_MASK(32),
++		.platform_data		= &ssc_sdata,
++	},
++	.resource	= ssc_resources,
++	.num_resources	= ARRAY_SIZE(ssc_resources),
++};
++
++static inline void configure_ssc_pins(unsigned pins)
++{
++	if (pins & ATMEL_SSC_TF)
++		at91_set_B_periph(AT91_PIN_PA25, 1);
++	if (pins & ATMEL_SSC_TK)
++		at91_set_B_periph(AT91_PIN_PA24, 1);
++	if (pins & ATMEL_SSC_TD)
++		at91_set_B_periph(AT91_PIN_PA26, 1);
++	if (pins & ATMEL_SSC_RD)
++		at91_set_B_periph(AT91_PIN_PA27, 1);
++	if (pins & ATMEL_SSC_RK)
++		at91_set_B_periph(AT91_PIN_PA28, 1);
++	if (pins & ATMEL_SSC_RF)
++		at91_set_B_periph(AT91_PIN_PA29, 1);
++}
++
++/*
++ * SSC controllers are accessed through library code, instead of any
++ * kind of all-singing/all-dancing driver.  For example one could be
++ * used by a particular I2S audio codec's driver, while another one
++ * on the same system might be used by a custom data capture driver.
++ */
++void __init at91_add_device_ssc(unsigned id, unsigned pins)
++{
++	struct platform_device *pdev;
++
++	/*
++	 * NOTE: caller is responsible for passing information matching
++	 * "pins" to whatever will be using each particular controller.
++	 */
++	if (id == AT91SAM9X5_ID_SSC) {
++#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
++		struct at_dma_slave *atslave;
++
++		atslave = at91sam9x5_ssc_device.dev.platform_data;
++
++		/* DMA slave channel configuration */
++		atslave->dma_dev = &at_hdmac0_device.dev;
++		atslave->reg_width = AT_DMA_SLAVE_WIDTH_16BIT;
++		atslave->cfg = ATC_FIFOCFG_HALFFIFO
++				| ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW
++				| ATC_SRC_PER(AT_DMA_ID_SSC_RX)
++				| ATC_DST_PER(AT_DMA_ID_SSC_TX);
++#endif
++
++		pdev = &at91sam9x5_ssc_device;
++		configure_ssc_pins(pins);
++		at91_clock_associate("ssc_clk", &pdev->dev, "pclk");
++	}
++	else
++		return;
++
++	platform_device_register(pdev);
++}
++
++#else
++void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ *  UART
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_SERIAL_ATMEL)
++static struct resource dbgu_resources[] = {
++	[0] = {
++		.start	= AT91_VA_BASE_SYS + AT91_DBGU,
++		.end	= AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91_ID_SYS,
++		.end	= AT91_ID_SYS,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct atmel_uart_data dbgu_data = {
++	.use_dma_tx	= 0,
++	.use_dma_rx	= 0,
++	.regs		= (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
++};
++
++static u64 dbgu_dmamask = DMA_BIT_MASK(32);
++
++static struct platform_device at91sam9x5_dbgu_device = {
++	.name		= "atmel_usart",
++	.id		= 0,
++	.dev		= {
++				.dma_mask		= &dbgu_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &dbgu_data,
++	},
++	.resource	= dbgu_resources,
++	.num_resources	= ARRAY_SIZE(dbgu_resources),
++};
++
++static inline void configure_dbgu_pins(void)
++{
++	at91_set_A_periph(AT91_PIN_PA9, 0);		/* DRXD */
++	at91_set_A_periph(AT91_PIN_PA10, 1);		/* DTXD */
++}
++
++static struct resource usart0_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_USART0,
++		.end	= AT91SAM9X5_BASE_USART0 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_USART0,
++		.end	= AT91SAM9X5_ID_USART0,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct atmel_uart_data usart0_data = {
++	.use_dma_tx	= 1,
++	.use_dma_rx	= 0,				/* doesn't support */
++};
++
++static u64 usart0_dmamask = DMA_BIT_MASK(32);
++
++static struct platform_device at91sam9x5_usart0_device = {
++	.name		= "atmel_usart",
++	.id		= 1,
++	.dev		= {
++				.dma_mask		= &usart0_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &usart0_data,
++	},
++	.resource	= usart0_resources,
++	.num_resources	= ARRAY_SIZE(usart0_resources),
++};
++
++static inline void configure_usart0_pins(unsigned pins)
++{
++	at91_set_A_periph(AT91_PIN_PA0, 1);		/* TXD0 */
++	at91_set_A_periph(AT91_PIN_PA1, 0);		/* RXD0 */
++
++	if (pins & ATMEL_UART_RTS)
++		at91_set_A_periph(AT91_PIN_PA2, 0);	/* RTS0 */
++	if (pins & ATMEL_UART_CTS)
++		at91_set_A_periph(AT91_PIN_PA3, 0);	/* CTS0 */
++}
++
++
++static struct resource usart1_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_USART1,
++		.end	= AT91SAM9X5_BASE_USART1 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_USART1,
++		.end	= AT91SAM9X5_ID_USART1,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct atmel_uart_data usart1_data = {
++	.use_dma_tx	= 1,
++	.use_dma_rx	= 1,
++};
++
++static u64 usart1_dmamask = DMA_BIT_MASK(32);
++
++static struct platform_device at91sam9x5_usart1_device = {
++	.name		= "atmel_usart",
++	.id		= 2,
++	.dev		= {
++				.dma_mask		= &usart1_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &usart1_data,
++	},
++	.resource	= usart1_resources,
++	.num_resources	= ARRAY_SIZE(usart1_resources),
++};
++
++static inline void configure_usart1_pins(unsigned pins)
++{
++	at91_set_A_periph(AT91_PIN_PA5, 1);		/* TXD1 */
++	at91_set_A_periph(AT91_PIN_PA6, 0);		/* RXD1 */
++
++	if (pins & ATMEL_UART_RTS)
++		at91_set_C_periph(AT91_PIN_PC27, 0);	/* RTS1 */
++	if (pins & ATMEL_UART_CTS)
++		at91_set_C_periph(AT91_PIN_PC28, 0);	/* CTS1 */
++}
++
++static struct resource usart2_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_USART2,
++		.end	= AT91SAM9X5_BASE_USART2 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_USART2,
++		.end	= AT91SAM9X5_ID_USART2,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct atmel_uart_data usart2_data = {
++	.use_dma_tx	= 1,
++	.use_dma_rx	= 1,
++};
++
++static u64 usart2_dmamask = DMA_BIT_MASK(32);
++
++static struct platform_device at91sam9x5_usart2_device = {
++	.name		= "atmel_usart",
++	.id		= 3,
++	.dev		= {
++				.dma_mask		= &usart2_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &usart2_data,
++	},
++	.resource	= usart2_resources,
++	.num_resources	= ARRAY_SIZE(usart2_resources),
++};
++
++static inline void configure_usart2_pins(unsigned pins)
++{
++	at91_set_A_periph(AT91_PIN_PA7, 1);		/* TXD2 */
++	at91_set_A_periph(AT91_PIN_PA8, 0);		/* RXD2 */
++
++	if (pins & ATMEL_UART_RTS)
++		at91_set_B_periph(AT91_PIN_PB0, 0);	/* RTS2 */
++	if (pins & ATMEL_UART_CTS)
++		at91_set_B_periph(AT91_PIN_PB1, 0);	/* CTS2 */
++}
++
++static struct resource usart3_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_USART3,
++		.end	= AT91SAM9X5_BASE_USART3 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_USART3,
++		.end	= AT91SAM9X5_ID_USART3,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct atmel_uart_data usart3_data = {
++	.use_dma_tx	= 1,
++	.use_dma_rx	= 1,
++};
++
++static u64 usart3_dmamask = DMA_BIT_MASK(32);
++
++static struct platform_device at91sam9x5_usart3_device = {
++	.name		= "atmel_usart",
++	.id		= 4,
++	.dev		= {
++				.dma_mask		= &usart3_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &usart3_data,
++	},
++	.resource	= usart3_resources,
++	.num_resources	= ARRAY_SIZE(usart3_resources),
++};
++
++static inline void configure_usart3_pins(unsigned pins)
++{
++	at91_set_B_periph(AT91_PIN_PC22, 1);		/* TXD3 */
++	at91_set_B_periph(AT91_PIN_PC23, 0);		/* RXD3 */
++
++	if (pins & ATMEL_UART_RTS)
++		at91_set_B_periph(AT91_PIN_PC24, 0);	/* RTS3 */
++	if (pins & ATMEL_UART_CTS)
++		at91_set_B_periph(AT91_PIN_PC25, 0);	/* CTS3 */
++}
++
++static struct resource uart0_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_UART0,
++		.end	= AT91SAM9X5_BASE_UART0 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_UART0,
++		.end	= AT91SAM9X5_ID_UART0,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct atmel_uart_data uart0_data = {
++	.use_dma_tx	= 1,
++	.use_dma_rx	= 1,
++};
++
++static u64 uart0_dmamask = DMA_BIT_MASK(32);
++
++static struct platform_device at91sam9x5_uart0_device = {
++	.name		= "atmel_usart",
++	.id		= 5,
++	.dev		= {
++				.dma_mask		= &uart0_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &uart0_data,
++	},
++	.resource	= uart0_resources,
++	.num_resources	= ARRAY_SIZE(uart0_resources),
++};
++
++static inline void configure_uart0_pins(unsigned pins)
++{
++	at91_set_C_periph(AT91_PIN_PC8, 1);		/* UTXD0 */
++	at91_set_C_periph(AT91_PIN_PC9, 0);		/* URXD0 */
++}
++
++static struct resource uart1_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_UART1,
++		.end	= AT91SAM9X5_BASE_UART1 + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_UART1,
++		.end	= AT91SAM9X5_ID_UART1,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct atmel_uart_data uart1_data = {
++	.use_dma_tx	= 1,
++	.use_dma_rx	= 1,
++};
++
++static u64 uart1_dmamask = DMA_BIT_MASK(32);
++
++static struct platform_device at91sam9x5_uart1_device = {
++	.name		= "atmel_usart",
++	.id		= 6,
++	.dev		= {
++				.dma_mask		= &uart1_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &uart1_data,
++	},
++	.resource	= uart1_resources,
++	.num_resources	= ARRAY_SIZE(uart1_resources),
++};
++
++static inline void configure_uart1_pins(unsigned pins)
++{
++	at91_set_C_periph(AT91_PIN_PC16, 1);		/* UTXD1 */
++	at91_set_C_periph(AT91_PIN_PC17, 0);		/* URXD1 */
++}
++
++static struct platform_device *__initdata at91_usarts[ATMEL_MAX_UART];	/* the USARTs to use */
++struct platform_device *atmel_default_console_device;	/* the serial console device */
++
++void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
++{
++	struct platform_device *pdev;
++
++	switch (id) {
++		case 0:		/* DBGU */
++			pdev = &at91sam9x5_dbgu_device;
++			configure_dbgu_pins();
++			at91_clock_associate("mck", &pdev->dev, "usart");
++			break;
++		case AT91SAM9X5_ID_USART0:
++			pdev = &at91sam9x5_usart0_device;
++			configure_usart0_pins(pins);
++			at91_clock_associate("usart0_clk", &pdev->dev, "usart");
++			break;
++		case AT91SAM9X5_ID_USART1:
++			pdev = &at91sam9x5_usart1_device;
++			configure_usart1_pins(pins);
++			at91_clock_associate("usart1_clk", &pdev->dev, "usart");
++			break;
++		case AT91SAM9X5_ID_USART2:
++			pdev = &at91sam9x5_usart2_device;
++			configure_usart2_pins(pins);
++			at91_clock_associate("usart2_clk", &pdev->dev, "usart");
++			break;
++		case AT91SAM9X5_ID_USART3:
++			pdev = &at91sam9x5_usart3_device;
++			configure_usart3_pins(pins);
++			at91_clock_associate("usart3_clk", &pdev->dev, "usart");
++			break;
++		case AT91SAM9X5_ID_UART0:
++			pdev = &at91sam9x5_uart0_device;
++			configure_uart0_pins(pins);
++			at91_clock_associate("uart0_clk", &pdev->dev, "usart");
++			break;
++		case AT91SAM9X5_ID_UART1:
++			pdev = &at91sam9x5_uart1_device;
++			configure_uart1_pins(pins);
++			at91_clock_associate("uart1_clk", &pdev->dev, "usart");
++			break;
++		default:
++			return;
++	}
++	pdev->id = portnr;		/* update to mapped ID */
++
++	if (portnr < ATMEL_MAX_UART)
++		at91_usarts[portnr] = pdev;
++}
++
++void __init at91_set_serial_console(unsigned portnr)
++{
++	if (portnr < ATMEL_MAX_UART)
++		atmel_default_console_device = at91_usarts[portnr];
++}
++
++void __init at91_add_device_serial(void)
++{
++	int i;
++
++	for (i = 0; i < ATMEL_MAX_UART; i++) {
++		if (at91_usarts[i]) {
++#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
++			int peripheral_id		= platform_get_irq(at91_usarts[i], 0);
++			struct atmel_uart_data *pdata	= at91_usarts[i]->dev.platform_data;
++
++			if (pdata->use_dma_tx) {
++				struct at_dma_slave	*atslave;
++
++				atslave = kzalloc(sizeof(struct at_dma_slave), GFP_KERNEL);
++
++				/* DMA slave channel configuration */
++				if (peripheral_id == AT91SAM9X5_ID_USART0
++				    || peripheral_id == AT91SAM9X5_ID_USART1
++				    || peripheral_id == AT91SAM9X5_ID_UART0)
++					atslave->dma_dev = &at_hdmac0_device.dev;
++				else
++					atslave->dma_dev = &at_hdmac1_device.dev;
++
++				atslave->reg_width = DW_DMA_SLAVE_WIDTH_8BIT;
++				atslave->cfg = ATC_FIFOCFG_HALFFIFO
++						| ATC_SRC_H2SEL_SW | ATC_DST_H2SEL_HW
++						| (AT_DMA_ID_USART0_TX << 4); /*ATC_DST_PER(peripheral_id);*/
++
++				pdata->dma_tx_slave = atslave;
++			}
++#endif
++			platform_device_register(at91_usarts[i]);
++		}
++	}
++
++	if (!atmel_default_console_device)
++		printk(KERN_INFO "AT91: No default serial console defined.\n");
++}
++#else
++void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
++void __init at91_set_serial_console(unsigned portnr) {}
++void __init at91_add_device_serial(void) {}
++#endif
++
++
++/* -------------------------------------------------------------------- */
++/*
++ * These devices are always present and don't need any board-specific
++ * setup.
++ */
++static int __init at91_add_standard_devices(void)
++{
++	at91_add_device_hdmac();
++	at91_add_device_rtc();
++	at91_add_device_watchdog();
++	at91_add_device_tc();
++	return 0;
++}
++
++arch_initcall(at91_add_standard_devices);
+diff --git a/arch/arm/mach-at91/board-sam9x5cm.c b/arch/arm/mach-at91/board-sam9x5cm.c
+new file mode 100644
+index 0000000..4fcc150
+--- /dev/null
++++ b/arch/arm/mach-at91/board-sam9x5cm.c
+@@ -0,0 +1,236 @@
++/*
++ *  CPU module specific setup code for the AT91SAM9x5 family
++ *
++ *  Copyright (C) 2011 Atmel Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/spi/flash.h>
++#include <linux/spi/spi.h>
++#include <linux/fb.h>
++#include <linux/gpio_keys.h>
++#include <linux/input.h>
++#include <linux/leds.h>
++#include <linux/clk.h>
++#include <mach/cpu.h>
++
++#include <video/atmel_lcdc.h>
++
++#include <asm/setup.h>
++#include <asm/mach-types.h>
++#include <asm/irq.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++
++#include <mach/hardware.h>
++#include <mach/board.h>
++#include <mach/gpio.h>
++#include <mach/at91sam9_smc.h>
++#include <mach/at91_shdwc.h>
++
++#include "sam9_smc.h"
++#include "generic.h"
++#include <mach/board-sam9x5.h>
++
++void __init cm_map_io(void)
++{
++	/* Initialize processor: 12.000 MHz crystal */
++	at91sam9x5_initialize(12000000);
++
++	/* DGBU on ttyS0. (Rx & Tx only) */
++	at91_register_uart(0, 0, 0);
++
++	/* set serial console to ttyS0 (ie, DBGU) */
++	at91_set_serial_console(0);
++}
++
++void __init cm_init_irq(void)
++{
++	at91sam9x5_init_interrupts(NULL);
++}
++
++/*
++ * SPI devices.
++ */
++static struct mtd_partition cm_spi_flash_parts[] = {
++	{
++		.name = "full",
++		.offset = 0,
++		.size = MTDPART_SIZ_FULL,
++	},
++	{
++		.name = "little",
++		.offset = 0,
++		.size = 24 * SZ_1K,
++	},
++	{
++		.name = "remaining",
++		.offset = MTDPART_OFS_NXTBLK,
++		.size = MTDPART_SIZ_FULL,
++	},
++};
++
++static const struct flash_platform_data cm_spi_flash_data = {
++		/*.type           = "sst25vf032b",*/
++		.name           = "spi_flash",
++		.parts		= cm_spi_flash_parts,
++		.nr_parts	= ARRAY_SIZE(cm_spi_flash_parts),
++};
++
++static struct spi_board_info cm_spi_devices[] = {
++#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
++#if defined(CONFIG_MTD_M25P80)
++	{	/* serial flash chip */
++		.modalias	= "m25p80",
++		.chip_select	= 0,
++		.max_speed_hz	= 15 * 1000 * 1000,
++		.bus_num	= 0,
++		.mode		= SPI_MODE_0,
++		.platform_data  = &cm_spi_flash_data,
++		.irq            = -1,
++	},
++#endif
++#endif
++};
++
++/*
++ * NAND flash
++ */
++static struct mtd_partition __initdata cm_nand_partition[] = {
++	{
++		.name	= "Partition 1",
++		.offset	= 0,
++		.size	= SZ_64M,
++	},
++	{
++		.name	= "Partition 2",
++		.offset	= MTDPART_OFS_NXTBLK,
++		.size	= MTDPART_SIZ_FULL,
++	},
++};
++
++static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
++{
++	*num_partitions = ARRAY_SIZE(cm_nand_partition);
++	return cm_nand_partition;
++}
++
++/* det_pin is not connected */
++static struct atmel_nand_data __initdata cm_nand_data = {
++	.ale		= 21,
++	.cle		= 22,
++	.enable_pin	= AT91_PIN_PD4,
++	.partition_info	= nand_partitions,
++#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
++	.bus_width_16	= 1,
++#endif
++};
++
++static struct sam9_smc_config __initdata cm_nand_smc_config = {
++	.ncs_read_setup		= 0,
++	.nrd_setup		= 1,
++	.ncs_write_setup	= 0,
++	.nwe_setup		= 1,
++
++	.ncs_read_pulse		= 6,
++	.nrd_pulse		= 4,
++	.ncs_write_pulse	= 5,
++	.nwe_pulse		= 3,
++
++	.read_cycle		= 6,
++	.write_cycle		= 5,
++
++	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
++	.tdf_cycles		= 1,
++};
++
++static void __init cm_add_device_nand(void)
++{
++	/* setup bus-width (8 or 16) */
++	if (cm_nand_data.bus_width_16)
++		cm_nand_smc_config.mode |= AT91_SMC_DBW_16;
++	else
++		cm_nand_smc_config.mode |= AT91_SMC_DBW_8;
++
++	/* revision of board modify NAND wiring */
++	if (cm_is_revA()) {
++		cm_nand_data.bus_on_d0 = 1;
++		cm_nand_data.rdy_pin = AT91_PIN_PD6;
++	} else {
++		cm_nand_data.bus_on_d0 = 0;
++		cm_nand_data.rdy_pin = AT91_PIN_PD5;
++	}
++
++	/* configure chip-select 3 (NAND) */
++	sam9_smc_configure(3, &cm_nand_smc_config);
++
++	at91_add_device_nand(&cm_nand_data);
++}
++
++/*
++ * LEDs
++ */
++static struct gpio_led cm_leds[] = {
++	{	/* "left" led, blue, userled1 */
++		.name			= "d1",
++		.gpio			= AT91_PIN_PB18,
++		.default_trigger	= "heartbeat",
++	},
++	{	/* "right" led, red, userled2 */
++		.name			= "d2",
++		.gpio			= AT91_PIN_PD21,
++		.active_low		= 1,
++		.default_trigger	= "mmc0",
++	},
++};
++
++/*
++ * I2C Devices
++ */
++static struct i2c_board_info __initdata cm_i2c_devices[] = {
++	{
++		I2C_BOARD_INFO("24c512", 0x50)
++	},
++};
++
++void __init cm_board_init(u32 *cm_config)
++{
++	int i;
++
++	*cm_config = 0;
++
++	/* SPI */
++	at91_add_device_spi(cm_spi_devices, ARRAY_SIZE(cm_spi_devices));
++	/* Check SPI0 usage to take decision in mother board */
++	for (i = 0; i < ARRAY_SIZE(cm_spi_devices); i++) {
++		if (cm_spi_devices[i].bus_num == 0) {
++			*cm_config |= CM_CONFIG_SPI0_ENABLE;
++			break;
++		}
++	}
++	/* NAND */
++	cm_add_device_nand();
++	/* I2C */
++	at91_add_device_i2c(0, cm_i2c_devices, ARRAY_SIZE(cm_i2c_devices));
++	*cm_config |= CM_CONFIG_I2C0_ENABLE;
++	/* LEDs */
++	at91_gpio_leds(cm_leds, ARRAY_SIZE(cm_leds));
++
++	/* TODO Remove: only for debugging */
++	if (cm_is_revA())
++		printk(KERN_CRIT "AT91: CM rev A\n");
++	else
++		printk(KERN_CRIT "AT91: CM rev B and higher\n");
++}
+diff --git a/arch/arm/mach-at91/board-sam9x5ek.c b/arch/arm/mach-at91/board-sam9x5ek.c
+new file mode 100644
+index 0000000..d86124c
+--- /dev/null
++++ b/arch/arm/mach-at91/board-sam9x5ek.c
+@@ -0,0 +1,358 @@
++/*
++ *  Board-specific setup code for the AT91SAM9x5 Evaluation Kit family
++ *
++ *  Copyright (C) 2010 Atmel Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/spi/flash.h>
++#include <linux/spi/spi.h>
++#include <linux/fb.h>
++#include <linux/gpio_keys.h>
++#include <linux/input.h>
++#include <linux/leds.h>
++#include <linux/clk.h>
++#include <mach/cpu.h>
++
++#include <video/atmel_lcdc.h>
++#include <mach/atmel_hlcdfb.h>
++
++#include <asm/setup.h>
++#include <asm/mach-types.h>
++#include <asm/irq.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++
++#include <mach/hardware.h>
++#include <mach/board.h>
++#include <mach/gpio.h>
++#include <mach/at91sam9_smc.h>
++#include <mach/at91_shdwc.h>
++
++#include "sam9_smc.h"
++#include "generic.h"
++#include <mach/board-sam9x5.h>
++
++static void __init ek_map_io(void)
++{
++	/* Initialize processor and DBGU */
++	cm_map_io();
++
++	/* USART0 on ttyS1. (Rx, Tx) */
++	at91_register_uart(AT91SAM9X5_ID_USART0, 1, 0);
++}
++
++/*
++ * USB Host port (OHCI)
++ */
++/* Port A is shared with gadget port & Port C is full-speed only */
++static struct at91_usbh_data __initdata ek_usbh_fs_data = {
++	.ports		= 3,
++
++};
++
++/*
++ * USB HS Host port (EHCI)
++ */
++/* Port A is shared with gadget port */
++static struct at91_usbh_data __initdata ek_usbh_hs_data = {
++	.ports		= 2,
++};
++
++
++/*
++ * USB HS Device port
++ */
++static struct usba_platform_data __initdata ek_usba_udc_data;
++
++
++/*
++ * MACB Ethernet devices
++ */
++static struct at91_eth_data __initdata ek_macb0_data = {
++	.is_rmii	= 1,
++};
++
++static struct at91_eth_data __initdata ek_macb1_data = {
++	.phy_irq_pin	= AT91_PIN_PC26,
++	.is_rmii	= 1,
++};
++
++
++/*
++ * MCI (SD/MMC)
++ */
++/* mci0 detect_pin is revision dependent */
++static struct mci_platform_data __initdata mci0_data = {
++	.slot[0] = {
++		.bus_width	= 4,
++		.wp_pin		= -1,
++	},
++};
++
++static struct mci_platform_data __initdata mci1_data = {
++	.slot[0] = {
++		.bus_width	= 4,
++		.detect_pin	= AT91_PIN_PD14,
++		.wp_pin		= -1,
++	},
++};
++
++
++/*
++ * LCD Controller
++ */
++#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
++static struct fb_videomode at91_tft_vga_modes[] = {
++	{
++		.name           = "LG",
++		.refresh	= 60,
++		.xres		= 800,		.yres		= 480,
++		.pixclock	= KHZ2PICOS(22223),
++
++		.left_margin	= 64,		.right_margin	= 64,
++		.upper_margin	= 22,		.lower_margin	= 21,
++		.hsync_len	= 128,		.vsync_len	= 2,
++
++		.sync		= 0,
++		.vmode		= FB_VMODE_NONINTERLACED,
++	},
++};
++
++static struct fb_monspecs at91fb_default_monspecs = {
++	.manufacturer	= "LG",
++	.monitor        = "LB043WQ1",
++
++	.modedb		= at91_tft_vga_modes,
++	.modedb_len	= ARRAY_SIZE(at91_tft_vga_modes),
++	.hfmin		= 15000,
++	.hfmax		= 17640,
++	.vfmin		= 57,
++	.vfmax		= 67,
++};
++
++/* Default output mode is TFT 24 bit */
++#define AT91SAM9X5_DEFAULT_LCDCFG5	(LCDC_LCDCFG5_MODE_OUTPUT_24BPP)
++
++/* Driver datas */
++static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
++	.lcdcon_is_backlight		= true,
++	.alpha_enabled			= false,
++	.default_bpp			= 24,
++	/* In 9x5 default_lcdcon2 is used for LCDCFG5 */
++	.default_lcdcon2		= AT91SAM9X5_DEFAULT_LCDCFG5,
++	.default_monspecs		= &at91fb_default_monspecs,
++	.guard_time			= 9,
++	.lcd_wiring_mode		= ATMEL_LCDC_WIRING_RGB,
++};
++
++#else
++static struct atmel_lcdfb_info __initdata ek_lcdc_data;
++#endif
++
++/*
++ * Touchscreen
++ */
++static struct at91_tsadcc_data ek_tsadcc_data = {
++	.adc_clock		= 300000,
++	/*
++	 * XXX: ukl: disable averaging for now at it's broken without a hardware
++	 * change
++	 */
++	.filtering_average	= 0x00,	/* averages 2^filtering_average ADC conversions */
++	.pendet_debounce	= 0x0d,
++	.pendet_sensitivity	= 0x03,
++	.ts_sample_hold_time	= 0x0a,
++};
++
++/*
++ * GPIO Buttons
++ */
++#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
++static struct gpio_keys_button ek_buttons[] = {
++	{	/* BP3, "leftclic" */
++		.code		= BTN_LEFT,
++		.gpio		= AT91_PIN_PD18,
++		.active_low	= 1,
++		.desc		= "left_click",
++		.wakeup		= 1,
++	},
++	{	/* BP4, "rightclic" */
++		.code		= BTN_RIGHT,
++		.gpio		= AT91_PIN_PD19,
++		.active_low	= 1,
++		.desc		= "right_click",
++		.wakeup		= 1,
++	},
++};
++
++static struct gpio_keys_platform_data ek_button_data = {
++	.buttons	= ek_buttons,
++	.nbuttons	= ARRAY_SIZE(ek_buttons),
++};
++
++static struct platform_device ek_button_device = {
++	.name		= "gpio-keys",
++	.id		= -1,
++	.num_resources	= 0,
++	.dev		= {
++		.platform_data	= &ek_button_data,
++	}
++};
++
++static void __init ek_add_device_buttons(void)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(ek_buttons); i++) {
++		at91_set_pulldown(ek_buttons[i].gpio, 0);
++		at91_set_gpio_input(ek_buttons[i].gpio, 1);
++		at91_set_deglitch(ek_buttons[i].gpio, 1);
++	}
++
++	platform_device_register(&ek_button_device);
++}
++#else
++static void __init ek_add_device_buttons(void) {}
++#endif
++
++/*
++ * I2C Devices
++ */
++static struct i2c_board_info __initdata ek_i2c_devices[] = {
++	{
++		I2C_BOARD_INFO("wm8731", 0x1a)
++	},
++#if defined(CONFIG_KEYBOARD_QT1070)
++	{
++		I2C_BOARD_INFO("qt1070", 0x1b),
++		.irq = AT91_PIN_PA7,
++		.flags = I2C_CLIENT_WAKE,
++	},
++#endif
++};
++
++static void __init ek_board_configure_pins(void)
++{
++	if (ek_is_revA()) {
++		/* Port A is shared with gadget port */
++		/*ek_usbh_fs_data.vbus_pin[0] = AT91_PIN_PD9;*/
++		/*ek_usbh_hs_data.vbus_pin[0] = AT91_PIN_PD9;*/
++		ek_usbh_fs_data.vbus_pin[1] = AT91_PIN_PD10;
++		ek_usbh_hs_data.vbus_pin[1] = AT91_PIN_PD10;
++		/* Port C is full-speed only */
++		ek_usbh_fs_data.vbus_pin[2] = AT91_PIN_PD11;
++
++		ek_usba_udc_data.vbus_pin = AT91_PIN_PB8;
++
++		ek_macb0_data.phy_irq_pin = 0;
++
++		mci0_data.slot[0].detect_pin = AT91_PIN_PD13;
++	} else {
++		/* Port A is shared with gadget port */
++		/*ek_usbh_fs_data.vbus_pin[0] = AT91_PIN_PD18;*/
++		/*ek_usbh_hs_data.vbus_pin[0] = AT91_PIN_PD18;*/
++		ek_usbh_fs_data.vbus_pin[1] = AT91_PIN_PD19;
++		ek_usbh_hs_data.vbus_pin[1] = AT91_PIN_PD19;
++		/* Port C is full-speed only */
++		ek_usbh_fs_data.vbus_pin[2] = AT91_PIN_PD20;
++
++		ek_usba_udc_data.vbus_pin = AT91_PIN_PB16;
++
++		ek_macb0_data.phy_irq_pin = AT91_PIN_PB8;
++
++		mci0_data.slot[0].detect_pin = AT91_PIN_PD15;
++
++#if defined(CONFIG_KEYBOARD_QT1070)
++		if (!cpu_is_at91sam9g25())
++			/* conflict with ISI */
++			at91_set_gpio_input(ek_i2c_devices[1].irq, 1);
++#endif
++	}
++}
++
++static void __init ek_board_init(void)
++{
++	u32 cm_config;
++
++	cm_board_init(&cm_config);
++	ek_board_configure_pins();
++	/* Serial */
++	at91_add_device_serial();
++	/* USB HS Host */
++	at91_add_device_usbh_ohci(&ek_usbh_fs_data);
++	at91_add_device_usbh_ehci(&ek_usbh_hs_data);
++	/* USB HS Device */
++	at91_add_device_usba(&ek_usba_udc_data);
++	/* Ethernet */
++	at91_add_device_eth(0, &ek_macb0_data);
++	at91_add_device_eth(1, &ek_macb1_data);
++	/* MMC */
++	at91_add_device_mci(0, &mci0_data);
++	/* Conflict between SPI0 and MCI1 pins */
++	if (!(cm_config & CM_CONFIG_SPI0_ENABLE))
++		at91_add_device_mci(1, &mci1_data);
++	/* I2C */
++	if (cm_config & CM_CONFIG_I2C0_ENABLE)
++		i2c_register_board_info(0,
++				ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
++	else
++		at91_add_device_i2c(0,
++				ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
++
++	if (!cpu_is_at91sam9g25() && !cpu_is_at91sam9x25()) {
++		/* LCD Controller */
++		at91_add_device_lcdc(&ek_lcdc_data);
++		/* Touch Screen */
++		at91_add_device_tsadcc(&ek_tsadcc_data);
++	}
++
++#if 0
++	if (cpu_is_at91sam9x25() || cpu_is_at91sam9x35())
++		/*
++		 * open jumper/solderdrop JP11 to activate CAN0
++		 *
++		 * _note_: this will deactivate the debug uart
++		 */
++		at91_add_device_can(0, NULL);
++#endif
++
++	if (cpu_is_at91sam9x25() || cpu_is_at91sam9x35())
++		/* XXX: this conflicts with usart.1 */
++		at91_add_device_can(1, NULL);
++
++	/* Push Buttons */
++	if (ek_is_revA())
++		ek_add_device_buttons();
++
++	/* SSC (for WM8731) */
++	at91_add_device_ssc(AT91SAM9X5_ID_SSC, ATMEL_SSC_TX | ATMEL_SSC_RX);
++
++	/* TODO Remove: only for debugging */
++	if (ek_is_revA())
++		printk(KERN_CRIT "AT91: EK rev A\n");
++	else
++		printk(KERN_CRIT "AT91: EK rev B and higher\n");
++}
++
++MACHINE_START(AT91SAM9X5EK, "Atmel AT91SAM9X5-EK")
++	/* Maintainer: Atmel */
++/* XXX/ukl: can we drop .boot_params? */
++	.boot_params	= AT91_SDRAM_BASE + 0x100,
++	.timer		= &at91sam926x_timer,
++	.map_io		= ek_map_io,
++	.init_irq	= cm_init_irq,
++	.init_machine	= ek_board_init,
++MACHINE_END
+diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
+index 0c66deb..a775336 100644
+--- a/arch/arm/mach-at91/generic.h
++++ b/arch/arm/mach-at91/generic.h
+@@ -15,6 +15,7 @@ extern void __init at91sam9261_initialize(unsigned long main_clock);
+ extern void __init at91sam9263_initialize(unsigned long main_clock);
+ extern void __init at91sam9rl_initialize(unsigned long main_clock);
+ extern void __init at91sam9g45_initialize(unsigned long main_clock);
++extern void __init at91sam9x5_initialize(unsigned long main_clock);
+ extern void __init at91x40_initialize(unsigned long main_clock);
+ extern void __init at91cap9_initialize(unsigned long main_clock);
+ extern void __init at572d940hf_initialize(unsigned long main_clock);
+@@ -26,6 +27,7 @@ extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
+ extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
+ extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
+ extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
++extern void __init at91sam9x5_init_interrupts(unsigned int priority[]);
+ extern void __init at91x40_init_interrupts(unsigned int priority[]);
+ extern void __init at91cap9_init_interrupts(unsigned int priority[]);
+ extern void __init at572d940hf_init_interrupts(unsigned int priority[]);
+diff --git a/arch/arm/mach-at91/include/mach/board-sam9x5.h b/arch/arm/mach-at91/include/mach/board-sam9x5.h
+new file mode 100644
+index 0000000..be8e1ec
+--- /dev/null
++++ b/arch/arm/mach-at91/include/mach/board-sam9x5.h
+@@ -0,0 +1,91 @@
++/*
++ *  Board-specific header file for the AT91SAM9x5 Evaluation Kit family
++ *
++ *  Copyright (C) 2010 Atmel Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++/*
++ * board revision encoding
++ *
++ *  ATAG_SN    lower 32 bits
++ *     0-4   cpu_module_board_id         5 bits
++ *     5-9   cpu_module_vendor_id        5 bits
++ *     10-14 display_module_board_id     5 bits
++ *     15-19 display_module_vendor_id    5 bits
++ *     20-24 mother_board_id             5 bits
++ *     25-29 mother_board_vendor_id      5 bits
++ *     30-31 reserved for future use     2 bits
++ *
++ * rev: stands for revision code letter: the 'B' in "B1" revision code for
++ *      instance coded as a increment from 'A' starting at 0x0: 0x0 means 'A',
++ *      0x1 means 'B', etc.
++ *
++ * rev_id: stands for revision code identifier ;  it is a number: the '1' in
++ *         "B1" revision code for instance: coded as a increment from '0'
++ *         starting at 0x0: 0x0 means '0', 0x1 means '1', etc.)
++ *
++ *  ATAG_REV
++ *     0-4   cpu_module_board_rev        5 bits
++ *     5-9   display_module_board_rev    5 bits
++ *     10-14 mother_module_board_rev     5 bits
++ *     15-17 cpu_module_board_rev_id     3 bits
++ *     18-20 display_module_board_rev_id 3 bits
++ *     21-23 mother_module_board_rev_id  3 bits
++ *     24-31 reserved for future use     8 bits
++ *
++ * OWI sands for One Wire Information
++ * The information comes form the 1-wire component on each board
++ * and is encoded in ATAGs: both system_serial_low and system_rev
++ */
++
++#define CM_REV_OFFSET		0
++#define CM_REV_SIZE		5
++#define CM_REV_ID_OFFSET	15
++#define CM_REV_ID_SIZE		3
++#define DM_REV_OFFSET		5
++#define DM_REV_SIZE		5
++#define DM_REV_ID_OFFSET	18
++#define DM_REV_ID_SIZE		3
++#define EK_REV_OFFSET		10
++#define EK_REV_SIZE		5
++#define EK_REV_ID_OFFSET	21
++#define EK_REV_ID_SIZE		3
++
++/* Bit manipulation macros */
++#define OWI_BIT(name) \
++        (1 << name##_OFFSET)
++#define OWI_BF(name,value) \
++        (((value) & ((1 << name##_SIZE) - 1)) << name##_OFFSET)
++#define OWI_BFEXT(name,value) \
++        (((value) >> name##_OFFSET) & ((1 << name##_SIZE) - 1))
++#define OWI_BFINS(name,value,old) \
++        ( ((old) & ~(((1 << name##_SIZE) - 1) << name##_OFFSET)) \
++          | SPI_BF(name,value))
++
++#define cm_rev()	OWI_BFEXT(CM_REV, system_rev)
++#define dm_rev()	OWI_BFEXT(DM_REV, system_rev)
++#define ek_rev()	OWI_BFEXT(EK_REV, system_rev)
++
++#define cm_is_revA()	(cm_rev() == 0)
++#define cm_is_revB()	(cm_rev() == ('B' - 'A'))
++
++#define ek_is_revA()	(ek_rev() == 0)
++#define ek_is_revB()	(ek_rev() == ('B' - 'A'))
++
++/* Configuration of CPU Module useful for mother board */
++#define CM_CONFIG_SPI0_ENABLE	(1 <<  0)
++#define CM_CONFIG_SPI1_ENABLE	(1 <<  1)
++#define CM_CONFIG_I2C0_ENABLE	(1 <<  2)
++#define CM_CONFIG_I2C1_ENABLE	(1 <<  3)
++
++
++/* CPU Module prototypes */
++void __init cm_map_io(void);
++void __init cm_init_irq(void);
++void __init cm_board_init(u32 *cm_config);
+diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
+index 2b499eb..42412d5 100644
+--- a/arch/arm/mach-at91/include/mach/board.h
++++ b/arch/arm/mach-at91/include/mach/board.h
+@@ -87,17 +87,21 @@ struct at91_eth_data {
+ 	u8		phy_irq_pin;	/* PHY IRQ */
+ 	u8		is_rmii;	/* using RMII interface? */
+ };
++#if defined(CONFIG_ARCH_AT91SAM9X5)
++extern void __init at91_add_device_eth(short eth_id, struct at91_eth_data *data);
++#else
+ extern void __init at91_add_device_eth(struct at91_eth_data *data);
++#endif
+ 
+ #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
+-	|| defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF)
++	|| defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT91SAM9X5) || defined(CONFIG_ARCH_AT572D940HF)
+ #define eth_platform_data	at91_eth_data
+ #endif
+ 
+  /* USB Host */
+ struct at91_usbh_data {
+ 	u8		ports;		/* number of ports on root hub */
+-	u8		vbus_pin[2];	/* port power-control pin */
++	u8		vbus_pin[3];	/* port power-control pin */
+ };
+ extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
+ extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
+@@ -112,12 +116,13 @@ struct atmel_nand_data {
+ 	u8		ale;		/* address line number connected to ALE */
+ 	u8		cle;		/* address line number connected to CLE */
+ 	u8		bus_width_16;	/* buswidth is 16 bit */
++	u8		bus_on_d0;	/* pins of data bus are connected to D0~D15 */
+ 	struct mtd_partition* (*partition_info)(int, int*);
+ };
+ extern void __init at91_add_device_nand(struct atmel_nand_data *data);
+ 
+  /* I2C*/
+-#if defined(CONFIG_ARCH_AT91SAM9G45)
++#if defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT91SAM9X5)
+ extern void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices);
+ #else
+ extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
+@@ -143,6 +148,7 @@ struct atmel_uart_data {
+ 	short			use_dma_tx;	/* use transmit DMA? */
+ 	short			use_dma_rx;	/* use receive DMA? */
+ 	void __iomem		*regs;		/* virt. base address, if any */
++	struct at_dma_slave	*dma_tx_slave;
+ 	struct serial_rs485	rs485;		/* rs485 settings */
+ };
+ extern void __init at91_add_device_serial(void);
+@@ -187,7 +193,9 @@ extern void __init at91_add_device_isi(void);
+  /* Touchscreen Controller */
+ struct at91_tsadcc_data {
+ 	unsigned int    adc_clock;
++	u8		filtering_average;
+ 	u8		pendet_debounce;
++	u8		pendet_sensitivity;
+ 	u8		ts_sample_hold_time;
+ };
+ extern void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data);
+@@ -196,7 +204,11 @@ extern void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data);
+ struct at91_can_data {
+ 	void (*transceiver_switch)(int on);
+ };
++#ifdef CONFIG_ARCH_AT91SAM9X5
++extern void __init at91_add_device_can(int id, struct at91_can_data *data);
++#else
+ extern void __init at91_add_device_can(struct at91_can_data *data);
++#endif
+ 
+  /* LEDs */
+ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
+diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
+index 3d64a75..6e270c2 100644
+--- a/arch/arm/mach-at91/include/mach/hardware.h
++++ b/arch/arm/mach-at91/include/mach/hardware.h
+@@ -28,6 +28,8 @@
+ #include <mach/at91sam9rl.h>
+ #elif defined(CONFIG_ARCH_AT91SAM9G45)
+ #include <mach/at91sam9g45.h>
++#elif defined(CONFIG_ARCH_AT91SAM9X5)
++#include <mach/at91sam9x5.h>
+ #elif defined(CONFIG_ARCH_AT91CAP9)
+ #include <mach/at91cap9.h>
+ #elif defined(CONFIG_ARCH_AT91X40)
+diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
+index 05a6e8a..23df905 100644
+--- a/arch/arm/mach-at91/include/mach/timex.h
++++ b/arch/arm/mach-at91/include/mach/timex.h
+@@ -72,6 +72,11 @@
+ #define AT91SAM9_MASTER_CLOCK	133333333
+ #define CLOCK_TICK_RATE		(AT91SAM9_MASTER_CLOCK/16)
+ 
++#elif defined(CONFIG_ARCH_AT91SAM9X5)
++
++#define AT91SAM9_MASTER_CLOCK	133333333
++#define CLOCK_TICK_RATE		(AT91SAM9_MASTER_CLOCK/16)
++
+ #elif defined(CONFIG_ARCH_AT91CAP9)
+ 
+ #define AT91CAP9_MASTER_CLOCK	100000000
+diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
+index ce9a206..b93f259 100644
+--- a/arch/arm/mach-at91/pm.h
++++ b/arch/arm/mach-at91/pm.h
+@@ -79,6 +79,25 @@ static inline u32 sdram_selfrefresh_enable(void)
+ 	} while (0)
+ #define wait_for_interrupt_enable()		cpu_do_idle()
+ 
++#elif defined(CONFIG_ARCH_AT91SAM9X5)
++#include <mach/at91sam9_ddrsdr.h>
++
++static inline u32 sdram_selfrefresh_enable(void)
++{
++	u32 lpr, saved_lpr;
++
++	saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
++	lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
++	lpr |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
++
++	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr);
++
++	return saved_lpr;
++}
++
++#define sdram_selfrefresh_disable(saved_lpr)	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
++#define wait_for_interrupt_enable()		cpu_do_idle()
++
+ #else
+ #include <mach/at91sam9_sdramc.h>
+ 
+diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
+index f7922a4..1a44c98 100644
+--- a/arch/arm/mach-at91/pm_slowclock.S
++++ b/arch/arm/mach-at91/pm_slowclock.S
+@@ -20,7 +20,7 @@
+ #include <mach/at91rm9200_mc.h>
+ #elif defined(CONFIG_ARCH_AT91CAP9)
+ #include <mach/at91cap9_ddrsdr.h>
+-#elif defined(CONFIG_ARCH_AT91SAM9G45)
++#elif defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT91SAM9X5)
+ #include <mach/at91sam9_ddrsdr.h>
+ #else
+ #include <mach/at91sam9_sdramc.h>
+@@ -132,7 +132,8 @@ ENTRY(at91_slow_clock)
+ 	mov	r3, #1
+ 	str	r3, [r2, #AT91_SDRAMC_SRR]
+ #elif defined(CONFIG_ARCH_AT91CAP9) \
+-	|| defined(CONFIG_ARCH_AT91SAM9G45)
++	|| defined(CONFIG_ARCH_AT91SAM9G45) \
++	|| defined(CONFIG_ARCH_AT91SAM9X5)
+ 
+ 	/* prepare for DDRAM self-refresh mode */
+ 	ldr	r3, [r2, #AT91_DDRSDRC_LPR]
+@@ -265,7 +266,8 @@ ENTRY(at91_slow_clock)
+ #ifdef CONFIG_ARCH_AT91RM9200
+ 	/* Do nothing - self-refresh is automatically disabled. */
+ #elif defined(CONFIG_ARCH_AT91CAP9) \
+-	|| defined(CONFIG_ARCH_AT91SAM9G45)
++	|| defined(CONFIG_ARCH_AT91SAM9G45) \
++	|| defined(CONFIG_ARCH_AT91SAM9X5)
+ 	/* Restore LPR on AT91 with DDRAM */
+ 	ldr	r3, .saved_sam9_lpr
+ 	str	r3, [r2, #AT91_DDRSDRC_LPR]
+@@ -307,7 +309,8 @@ ENTRY(at91_slow_clock)
+ .at91_va_base_sdramc:
+ 	.word AT91_VA_BASE_SYS
+ #elif defined(CONFIG_ARCH_AT91CAP9) \
+-	|| defined(CONFIG_ARCH_AT91SAM9G45)
++	|| defined(CONFIG_ARCH_AT91SAM9G45) \
++	|| defined(CONFIG_ARCH_AT91SAM9X5)
+ .at91_va_base_sdramc:
+ 	.word AT91_VA_BASE_SYS + AT91_DDRSDRC0
+ #else
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0013-ARM-at91-provide-defconfig-for-at91sam9x5ek.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0013-ARM-at91-provide-defconfig-for-at91sam9x5ek.patch
new file mode 100644
index 0000000..a0510fc
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0013-ARM-at91-provide-defconfig-for-at91sam9x5ek.patch
@@ -0,0 +1,218 @@
+From 480473dce3bc94a6f05bb69fcebf35b059ff77e3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Wed, 20 Apr 2011 17:27:15 +0200
+Subject: [PATCH 013/107] ARM: at91: provide defconfig for at91sam9x5ek
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/configs/at91sam9x5ek_defconfig |  195 +++++++++++++++++++++++++++++++
+ 1 files changed, 195 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/configs/at91sam9x5ek_defconfig
+
+diff --git a/arch/arm/configs/at91sam9x5ek_defconfig b/arch/arm/configs/at91sam9x5ek_defconfig
+new file mode 100644
+index 0000000..1b455fc
+--- /dev/null
++++ b/arch/arm/configs/at91sam9x5ek_defconfig
+@@ -0,0 +1,195 @@
++CONFIG_EXPERIMENTAL=y
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_LOG_BUF_SHIFT=14
++# CONFIG_UTS_NS is not set
++# CONFIG_IPC_NS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_NET_NS is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_SLAB=y
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_LBDAF is not set
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_IOSCHED_DEADLINE is not set
++# CONFIG_IOSCHED_CFQ is not set
++CONFIG_ARCH_AT91=y
++CONFIG_ARCH_AT91SAM9X5=y
++CONFIG_MACH_AT91SAM9X5EK=y
++CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
++CONFIG_AT91_SLOW_CLOCK=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_AEABI=y
++CONFIG_LEDS=y
++CONFIG_LEDS_CPU=y
++CONFIG_UACCESS_WITH_MEMCPY=y
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,8000000 root=/dev/ram0 rw mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data)"
++CONFIG_FPE_NWFPE=y
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++# CONFIG_IPV6 is not set
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NF_CONNTRACK_IPV4=y
++CONFIG_IP_NF_IPTABLES=y
++CONFIG_IP_NF_FILTER=y
++CONFIG_IP_NF_TARGET_REJECT=m
++CONFIG_IP_NF_TARGET_LOG=m
++CONFIG_IP_NF_TARGET_ULOG=m
++CONFIG_NF_NAT=y
++CONFIG_IP_NF_TARGET_MASQUERADE=y
++CONFIG_IP_NF_TARGET_NETMAP=y
++CONFIG_IP_NF_TARGET_REDIRECT=y
++CONFIG_IP_NF_RAW=m
++CONFIG_IP_NF_ARPTABLES=m
++CONFIG_BRIDGE=y
++CONFIG_VLAN_8021Q=m
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_CBQ=m
++CONFIG_NET_SCH_HTB=m
++CONFIG_NET_SCH_HFSC=m
++CONFIG_NET_SCH_TBF=m
++CONFIG_NET_CLS_FW=m
++CONFIG_CAN=y
++CONFIG_CAN_RAW=y
++CONFIG_CAN_DEV=y
++CONFIG_CAN_CALC_BITTIMING=y
++CONFIG_CAN_AT91=y
++# CONFIG_WIRELESS is not set
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++# CONFIG_STANDALONE is not set
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++# CONFIG_FIRMWARE_IN_KERNEL is not set
++CONFIG_MTD=y
++CONFIG_MTD_TESTS=m
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_M25P80=y
++CONFIG_MTD_NAND=y
++CONFIG_MTD_NAND_ATMEL=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=4
++CONFIG_BLK_DEV_RAM_SIZE=8192
++CONFIG_MISC_DEVICES=y
++CONFIG_ATMEL_TCLIB=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_MULTI_LUN=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_DAVICOM_PHY=y
++CONFIG_NET_ETHERNET=y
++CONFIG_MACB=y
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++# CONFIG_WLAN is not set
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
++CONFIG_LEGACY_PTY_COUNT=8
++CONFIG_SERIAL_ATMEL=y
++CONFIG_SERIAL_ATMEL_CONSOLE=y
++CONFIG_HW_RANDOM=y
++CONFIG_SPI=y
++CONFIG_SPI_ATMEL=y
++CONFIG_GPIO_SYSFS=y
++# CONFIG_HWMON is not set
++# CONFIG_MFD_SUPPORT is not set
++CONFIG_FB=y
++CONFIG_FB_ATMEL=y
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++# CONFIG_LCD_CLASS_DEVICE is not set
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_ATMEL_LCDC=y
++# CONFIG_BACKLIGHT_GENERIC is not set
++CONFIG_USB=y
++# CONFIG_USB_DEVICE_CLASS is not set
++CONFIG_USB_EHCI_HCD=y
++# CONFIG_USB_EHCI_TT_NEWSCHED is not set
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_LIBUSUAL=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_ZERO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_FILE_STORAGE=m
++CONFIG_USB_G_SERIAL=m
++CONFIG_USB_CDC_COMPOSITE=m
++CONFIG_USB_G_MULTI=m
++CONFIG_USB_G_MULTI_CDC=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_AT91RM9200=y
++CONFIG_DMADEVICES=y
++CONFIG_AT_HDMAC=y
++CONFIG_DMATEST=m
++CONFIG_UIO=y
++CONFIG_UIO_PDRV=m
++CONFIG_UIO_PDRV_GENIRQ=y
++CONFIG_EXT2_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_SUMMARY=y
++CONFIG_LOGFS=m
++CONFIG_CRAMFS=y
++CONFIG_SQUASHFS=m
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_850=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_15=y
++CONFIG_NLS_UTF8=y
++# CONFIG_ENABLE_WARN_DEPRECATED is not set
++CONFIG_DEBUG_FS=y
++CONFIG_DEBUG_KERNEL=y
++CONFIG_LOCKUP_DETECTOR=y
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_PROVE_LOCKING=y
++CONFIG_DEBUG_SPINLOCK_SLEEP=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_FTRACE is not set
++# CONFIG_ARM_UNWIND is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_CRYPTO_HW is not set
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0014-usb-AT91SAM9X5-has-EHCI.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0014-usb-AT91SAM9X5-has-EHCI.patch
new file mode 100644
index 0000000..8b648f1
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0014-usb-AT91SAM9X5-has-EHCI.patch
@@ -0,0 +1,32 @@
+From 1c36853cd7c5bdf65be94522ec34e1d8e9d843ff Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Mon, 18 Apr 2011 16:53:25 +0200
+Subject: [PATCH 014/107] usb: AT91SAM9X5 has EHCI
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This change was part of a patch provided (non-publically) by Atmel. I
+split it off because it was unrelated to the commit log and the other
+changes in that commit.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/usb/Kconfig |    1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
+index 006489d..041f324 100644
+--- a/drivers/usb/Kconfig
++++ b/drivers/usb/Kconfig
+@@ -60,6 +60,7 @@ config USB_ARCH_HAS_EHCI
+ 	default y if ARCH_IXP4XX
+ 	default y if ARCH_W90X900
+ 	default y if ARCH_AT91SAM9G45
++	default y if ARCH_AT91SAM9X5
+ 	default y if ARCH_MXC
+ 	default y if ARCH_OMAP3
+ 	default y if ARCH_CNS3XXX
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0015-ARM-at91-pio-add-new-PIO3a-features.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0015-ARM-at91-pio-add-new-PIO3a-features.patch
new file mode 100644
index 0000000..286cb00
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0015-ARM-at91-pio-add-new-PIO3a-features.patch
@@ -0,0 +1,440 @@
+From 0746bd00cceb9e00b74fe41a351de0674ade1c0f Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 20 Jul 2010 19:18:51 +0200
+Subject: [PATCH 015/107] ARM: at91: pio: add new PIO3a features
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch adds the support for new PIO controller found on some
+at91sam SOCs.
+- more peripheral multiplexing
+- more features to configure on a PIO (pull-down, Schmitt trigger, debouncer)
+- support for several irq triggering features (type and polarity)
+
+Debugfs at91_gpio file is updated to monitor configuration.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/mach-at91/gpio.c                  |  239 ++++++++++++++++++++++++++--
+ arch/arm/mach-at91/include/mach/at91_pio.h |   25 +++
+ arch/arm/mach-at91/include/mach/gpio.h     |    5 +
+ 3 files changed, 257 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
+index 4615528..6735662 100644
+--- a/arch/arm/mach-at91/gpio.c
++++ b/arch/arm/mach-at91/gpio.c
+@@ -20,6 +20,7 @@
+ #include <linux/module.h>
+ #include <linux/io.h>
+ 
++#include <mach/cpu.h>
+ #include <mach/hardware.h>
+ #include <mach/at91_pio.h>
+ #include <mach/gpio.h>
+@@ -69,6 +70,12 @@ static struct at91_gpio_chip gpio_chip[] = {
+ 
+ static int gpio_banks;
+ 
++/*
++ * Functionnality can change with newer chips
++ */
++#define cpu_has_pio3()	(cpu_is_at91sam9x5())
++
++
+ static inline void __iomem *pin_to_controller(unsigned pin)
+ {
+ 	pin -= PIN_BASE;
+@@ -86,6 +93,52 @@ static inline unsigned pin_to_mask(unsigned pin)
+ }
+ 
+ 
++static char peripheral_function(void __iomem *pio, unsigned mask)
++{
++	char	ret = 'X';
++	u8	select;
++
++	if (pio) {
++		if (cpu_has_pio3()) {
++			select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
++			select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
++			ret = 'A' + select;
++		} else {
++			ret = __raw_readl(pio + PIO_ABSR) & mask ?
++							'B' : 'A';
++		}
++	}
++
++	return ret;
++}
++
++static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
++{
++	char	*trigger = NULL;
++	char	*polarity = NULL;
++
++	if (__raw_readl(pio + PIO_IMR) & mask) {
++		if (!cpu_has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
++			trigger = "edge";
++			polarity = "both";
++		} else {
++			if (__raw_readl(pio + PIO_ELSR) & mask) {
++				trigger = "level";
++				polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
++					"high" : "low";
++			} else {
++				trigger = "edge";
++				polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
++						"rising" : "falling";
++			}
++		}
++		seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
++	} else {
++		seq_printf(s, "GPIO:%s\t\t",
++				__raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
++	}
++}
++
+ /*--------------------------------------------------------------------------*/
+ 
+ /* Not all hardware capabilities are exposed through these calls; they
+@@ -133,7 +186,14 @@ int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
+ 
+ 	__raw_writel(mask, pio + PIO_IDR);
+ 	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+-	__raw_writel(mask, pio + PIO_ASR);
++	if (cpu_has_pio3()) {
++		__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
++							pio + PIO_ABCDSR1);
++		__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
++							pio + PIO_ABCDSR2);
++	} else {
++		__raw_writel(mask, pio + PIO_ASR);
++	}
+ 	__raw_writel(mask, pio + PIO_PDR);
+ 	return 0;
+ }
+@@ -153,7 +213,14 @@ int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
+ 
+ 	__raw_writel(mask, pio + PIO_IDR);
+ 	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+-	__raw_writel(mask, pio + PIO_BSR);
++	if (cpu_has_pio3()) {
++		__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
++							pio + PIO_ABCDSR1);
++		__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
++							pio + PIO_ABCDSR2);
++	} else {
++		__raw_writel(mask, pio + PIO_BSR);
++	}
+ 	__raw_writel(mask, pio + PIO_PDR);
+ 	return 0;
+ }
+@@ -161,6 +228,48 @@ EXPORT_SYMBOL(at91_set_B_periph);
+ 
+ 
+ /*
++ * mux the pin to the "C" internal peripheral role.
++ */
++int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
++{
++	void __iomem	*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	if (!pio || !cpu_has_pio3())
++		return -EINVAL;
++
++	__raw_writel(mask, pio + PIO_IDR);
++	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
++	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
++	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
++	__raw_writel(mask, pio + PIO_PDR);
++	return 0;
++}
++EXPORT_SYMBOL(at91_set_C_periph);
++
++
++/*
++ * mux the pin to the "C" internal peripheral role.
++ */
++int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
++{
++	void __iomem	*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	if (!pio || !cpu_has_pio3())
++		return -EINVAL;
++
++	__raw_writel(mask, pio + PIO_IDR);
++	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
++	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
++	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
++	__raw_writel(mask, pio + PIO_PDR);
++	return 0;
++}
++EXPORT_SYMBOL(at91_set_D_periph);
++
++
++/*
+  * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
+  * configure it for an input.
+  */
+@@ -213,12 +322,37 @@ int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
+ 
+ 	if (!pio)
+ 		return -EINVAL;
++
++	if (cpu_has_pio3() && is_on)
++		__raw_writel(mask, pio + PIO_IFSCDR);
+ 	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
+ 	return 0;
+ }
+ EXPORT_SYMBOL(at91_set_deglitch);
+ 
+ /*
++ * enable/disable the debounce filter;
++ */
++int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
++{
++	void __iomem	*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	if (!pio || !cpu_has_pio3())
++		return -EINVAL;
++
++	if (is_on) {
++		__raw_writel(mask, pio + PIO_IFSCER);
++		__raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
++		__raw_writel(mask, pio + PIO_IFER);
++	} else {
++		__raw_writel(mask, pio + PIO_IFDR);
++	}
++	return 0;
++}
++EXPORT_SYMBOL(at91_set_debounce);
++
++/*
+  * enable/disable the multi-driver; This is only valid for output and
+  * allows the output pin to run as an open collector output.
+  */
+@@ -236,6 +370,41 @@ int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
+ EXPORT_SYMBOL(at91_set_multi_drive);
+ 
+ /*
++ * enable/disable the pull-down.
++ * If pull-up already enabled while calling the function, we disable it.
++ */
++int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
++{
++	void __iomem	*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	if (!pio || !cpu_has_pio3())
++		return -EINVAL;
++
++	/* Disable pull-up anyway */
++	__raw_writel(mask, pio + PIO_PUDR);
++	__raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
++	return 0;
++}
++EXPORT_SYMBOL(at91_set_pulldown);
++
++/*
++ * disable Schmitt trigger
++ */
++int __init_or_module at91_disable_schmitt_trig(unsigned pin)
++{
++	void __iomem	*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	if (!pio || !cpu_has_pio3())
++		return -EINVAL;
++
++	__raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
++	return 0;
++}
++EXPORT_SYMBOL(at91_disable_schmitt_trig);
++
++/*
+  * assuming the pin is muxed as a gpio output, set its value.
+  */
+ int at91_set_gpio_value(unsigned pin, int value)
+@@ -337,7 +506,10 @@ void at91_gpio_resume(void)
+  * To use any AT91_PIN_* as an externally triggered IRQ, first call
+  * at91_set_gpio_input() then maybe enable its glitch filter.
+  * Then just request_irq() with the pin ID; it works like any ARM IRQ
+- * handler, though it always triggers on rising and falling edges.
++ * handler.
++ * First implementation always triggers on rising and falling edges
++ * whereas the newer PIO3a can be additionally configured to trigger on
++ * level, edge with any polarity.
+  *
+  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
+  * configuring them with at91_set_a_periph() or at91_set_b_periph().
+@@ -373,12 +545,52 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
+ 	}
+ }
+ 
++/* Alternate irq type for PIO3a support */
++static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
++{
++	void __iomem	*pio = pin_to_controller(d->irq);
++	unsigned	mask = pin_to_mask(d->irq);
++
++	switch (type) {
++	case IRQ_TYPE_EDGE_RISING:
++		__raw_writel(mask, pio + PIO_ESR);
++		__raw_writel(mask, pio + PIO_REHLSR);
++		break;
++	case IRQ_TYPE_EDGE_FALLING:
++		__raw_writel(mask, pio + PIO_ESR);
++		__raw_writel(mask, pio + PIO_FELLSR);
++		break;
++	case IRQ_TYPE_LEVEL_LOW:
++		__raw_writel(mask, pio + PIO_LSR);
++		__raw_writel(mask, pio + PIO_FELLSR);
++		break;
++	case IRQ_TYPE_LEVEL_HIGH:
++		__raw_writel(mask, pio + PIO_LSR);
++		__raw_writel(mask, pio + PIO_REHLSR);
++		break;
++	case IRQ_TYPE_EDGE_BOTH:
++		/* disable additional interrupt modes:
++		 * fall back to default behavior */
++		__raw_writel(mask, pio + PIO_AIMDR);
++		return 0;
++	case IRQ_TYPE_NONE:
++	default:
++		pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
++		return -EINVAL;
++	}
++
++	/* enable additional interrupt modes */
++	__raw_writel(mask, pio + PIO_AIMER);
++
++	return 0;
++}
++
+ static struct irq_chip gpio_irqchip = {
+ 	.name		= "GPIO",
+ 	.irq_disable	= gpio_irq_mask,
+ 	.irq_mask	= gpio_irq_mask,
+ 	.irq_unmask	= gpio_irq_unmask,
+-	.irq_set_type	= gpio_irq_type,
++	/* .irq_set_type is set in at91_gpio_irq_setup */
+ 	.irq_set_wake	= gpio_irq_set_wake,
+ };
+ 
+@@ -431,7 +643,7 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
+ 	/* print heading */
+ 	seq_printf(s, "Pin\t");
+ 	for (bank = 0; bank < gpio_banks; bank++) {
+-		seq_printf(s, "PIO%c\t", 'A' + bank);
++		seq_printf(s, "PIO%c\t\t", 'A' + bank);
+ 	};
+ 	seq_printf(s, "\n\n");
+ 
+@@ -445,11 +657,10 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
+ 			unsigned	mask = pin_to_mask(pin);
+ 
+ 			if (__raw_readl(pio + PIO_PSR) & mask)
+-				seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
++				gpio_printf(s, pio, mask);
+ 			else
+-				seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
+-
+-			seq_printf(s, "\t");
++				seq_printf(s, "%c\t\t",
++						peripheral_function(pio, mask));
+ 		}
+ 
+ 		seq_printf(s, "\n");
+@@ -496,6 +707,11 @@ void __init at91_gpio_irq_setup(void)
+ 	unsigned		pioc, pin;
+ 	struct at91_gpio_chip	*this, *prev;
+ 
++	if (cpu_has_pio3())
++		gpio_irqchip.irq_set_type = alt_gpio_irq_type;
++	else
++		gpio_irqchip.irq_set_type = gpio_irq_type;
++
+ 	for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
+ 			pioc++ < gpio_banks;
+ 			prev = this, this++) {
+@@ -592,9 +808,8 @@ static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+ 					   at91_get_gpio_value(pin) ?
+ 					   "set" : "clear");
+ 			else
+-				seq_printf(s, "[periph %s]\n",
+-					   __raw_readl(pio + PIO_ABSR) &
+-					   mask ? "B" : "A");
++				seq_printf(s, "[periph %c]\n",
++					   peripheral_function(pio, mask));
+ 		}
+ 	}
+ }
+diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
+index c6a31bf..732b11c 100644
+--- a/arch/arm/mach-at91/include/mach/at91_pio.h
++++ b/arch/arm/mach-at91/include/mach/at91_pio.h
+@@ -40,10 +40,35 @@
+ #define PIO_PUER	0x64	/* Pull-up Enable Register */
+ #define PIO_PUSR	0x68	/* Pull-up Status Register */
+ #define PIO_ASR		0x70	/* Peripheral A Select Register */
++#define PIO_ABCDSR1	0x70	/* Peripheral ABCD Select Register 1 [some sam9 only] */
+ #define PIO_BSR		0x74	/* Peripheral B Select Register */
++#define PIO_ABCDSR2	0x74	/* Peripheral ABCD Select Register 2 [some sam9 only] */
+ #define PIO_ABSR	0x78	/* AB Status Register */
++#define PIO_IFSCDR	0x80	/* Input Filter Slow Clock Disable Register */
++#define PIO_IFSCER	0x84	/* Input Filter Slow Clock Enable Register */
++#define PIO_IFSCSR	0x88	/* Input Filter Slow Clock Status Register */
++#define PIO_SCDR	0x8c	/* Slow Clock Divider Debouncing Register */
++#define		PIO_SCDR_DIV	(0x3fff <<  0)		/* Slow Clock Divider Mask */
++#define PIO_PPDDR	0x90	/* Pad Pull-down Disable Register */
++#define PIO_PPDER	0x94	/* Pad Pull-down Enable Register */
++#define PIO_PPDSR	0x98	/* Pad Pull-down Status Register */
+ #define PIO_OWER	0xa0	/* Output Write Enable Register */
+ #define PIO_OWDR	0xa4	/* Output Write Disable Register */
+ #define PIO_OWSR	0xa8	/* Output Write Status Register */
++#define PIO_AIMER	0xb0	/* Additional Interrupt Modes Enable Register */
++#define PIO_AIMDR	0xb4	/* Additional Interrupt Modes Disable Register */
++#define PIO_AIMMR	0xb8	/* Additional Interrupt Modes Mask Register */
++#define PIO_ESR		0xc0	/* Edge Select Register */
++#define PIO_LSR		0xc4	/* Level Select Register */
++#define PIO_ELSR	0xc8	/* Edge/Level Status Register */
++#define PIO_FELLSR	0xd0	/* Falling Edge/Low Level Select Register */
++#define PIO_REHLSR	0xd4	/* Rising Edge/ High Level Select Register */
++#define PIO_FRLHSR	0xd8	/* Fall/Rise - Low/High Status Register */
++#define PIO_SCHMITT	0x100	/* Schmitt Trigger Register */
++
++#define ABCDSR_PERIPH_A	0x0
++#define ABCDSR_PERIPH_B	0x1
++#define ABCDSR_PERIPH_C	0x2
++#define ABCDSR_PERIPH_D	0x3
+ 
+ #endif
+diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
+index 056dc66..4e4cc4b 100644
+--- a/arch/arm/mach-at91/include/mach/gpio.h
++++ b/arch/arm/mach-at91/include/mach/gpio.h
+@@ -193,10 +193,15 @@
+ extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
+ extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
+ extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
++extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup);
++extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup);
+ extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
+ extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
+ extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
++extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div);
+ extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
++extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on);
++extern int __init_or_module at91_disable_schmitt_trig(unsigned pin);
+ 
+ /* callable at any time */
+ extern int at91_set_gpio_value(unsigned pin, int value);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0016-usb-AT91SAM9X5-has-a-atmel_usba_udc-device.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0016-usb-AT91SAM9X5-has-a-atmel_usba_udc-device.patch
new file mode 100644
index 0000000..2b46fb5
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0016-usb-AT91SAM9X5-has-a-atmel_usba_udc-device.patch
@@ -0,0 +1,39 @@
+From 1027ba75ecaaff666df01c0e60e64ddb747a4b65 Mon Sep 17 00:00:00 2001
+From: Dan Liang <dan.liang@atmel.com>
+Date: Mon, 23 Aug 2010 16:09:46 +0200
+Subject: [PATCH 016/107] usb: AT91SAM9X5 has a atmel_usba_udc device
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Dan Liang <dan.liang@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/usb/gadget/Kconfig |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
+index bc5123c..926d0ea 100644
+--- a/drivers/usb/gadget/Kconfig
++++ b/drivers/usb/gadget/Kconfig
+@@ -124,7 +124,7 @@ choice
+ 
+ config USB_GADGET_AT91
+ 	boolean "Atmel AT91 USB Device Port"
+-	depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91CAP9 && !ARCH_AT91SAM9G45
++	depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91CAP9 && !ARCH_AT91SAM9G45 && !ARCH_AT91SAM9X5
+ 	select USB_GADGET_SELECTED
+ 	help
+ 	   Many Atmel AT91 processors (such as the AT91RM2000) have a
+@@ -143,7 +143,7 @@ config USB_AT91
+ config USB_GADGET_ATMEL_USBA
+ 	boolean "Atmel USBA"
+ 	select USB_GADGET_DUALSPEED
+-	depends on AVR32 || ARCH_AT91CAP9 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
++	depends on AVR32 || ARCH_AT91CAP9 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 || ARCH_AT91SAM9X5
+ 	help
+ 	  USBA is the integrated high-speed USB Device controller on
+ 	  the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0017-clocksource-tcb-add-support-for-32-bit-mode.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0017-clocksource-tcb-add-support-for-32-bit-mode.patch
new file mode 100644
index 0000000..a6d6f22
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0017-clocksource-tcb-add-support-for-32-bit-mode.patch
@@ -0,0 +1,114 @@
+From 5e65851fa541a9e420c85eb90858a909139b5df5 Mon Sep 17 00:00:00 2001
+From: Dan Liang <dan.liang@atmel.com>
+Date: Thu, 2 Sep 2010 13:07:42 +0800
+Subject: [PATCH 017/107] clocksource/tcb: add support for 32-bit mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Support for 32 bit wide Timer Counter blocks. Those TC blocks
+are present in 5 series AT91 SOC family.
+
+CONFIG_ATMEL_TCB_CLKSRC_32BIT is used to distinguish old timer
+and new one. Since channel 0 is wide enough, channel 1 is not
+configured and unused.
+
+XXX: make selecting 32 bit support runtime conditional
+
+Signed-off-by: Dan Liang <dan.liang@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/clocksource/tcb_clksrc.c |   21 +++++++++++++++++++--
+ drivers/misc/Kconfig             |    4 ++++
+ 2 files changed, 23 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
+index 79c47e8..4f612de 100644
+--- a/drivers/clocksource/tcb_clksrc.c
++++ b/drivers/clocksource/tcb_clksrc.c
+@@ -20,6 +20,9 @@
+  *     with a base rate of 5+ MHz, packaged as a clocksource (with
+  *     resolution better than 200 nsec).
+  *
++ *   - Some chips support 32 bit counter in one channel, then the second
++ *     channel is not used.
++ *
+  *   - The third channel may be used to provide a 16-bit clockevent
+  *     source, used in either periodic or oneshot mode.  This runs
+  *     at 32 KiHZ, and can handle delays of up to two seconds.
+@@ -45,10 +48,15 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
+ 	u32		lower, upper;
+ 
+ 	raw_local_irq_save(flags);
++#ifndef CONFIG_ATMEL_TCB_CLKSRC_32BIT
+ 	do {
+ 		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
+ 		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
+ 	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
++#else
++	upper = 0;
++	lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
++#endif
+ 
+ 	raw_local_irq_restore(flags);
+ 	return (upper << 16) | lower;
+@@ -271,14 +279,21 @@ static int __init tcb_clksrc_init(void)
+ 	__raw_writel(best_divisor_idx			/* likely divide-by-8 */
+ 			| ATMEL_TC_WAVE
+ 			| ATMEL_TC_WAVESEL_UP		/* free-run */
++#ifndef CONFIG_ATMEL_TCB_CLKSRC_32BIT
+ 			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
+-			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
++			| ATMEL_TC_ACPC_CLEAR		/* (duty cycle 50%) */
++#endif
++			,
+ 			tcaddr + ATMEL_TC_REG(0, CMR));
++
++#ifndef CONFIG_ATMEL_TCB_CLKSRC_32BIT
+ 	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
+ 	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
++#endif
+ 	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
+ 	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+ 
++#ifndef CONFIG_ATMEL_TCB_CLKSRC_32BIT
+ 	/* channel 1:  waveform mode, input TIOA0 */
+ 	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */
+ 			| ATMEL_TC_WAVE
+@@ -287,8 +302,10 @@ static int __init tcb_clksrc_init(void)
+ 	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
+ 	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
+ 
+-	/* chain channel 0 to channel 1, then reset all the timers */
++	/* chain channel 0 to channel 1 */
+ 	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
++#endif
++	/* reset all the timers */
+ 	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+ 
+ 	/* and away we go! */
+diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+index 4e007c6..a43126c 100644
+--- a/drivers/misc/Kconfig
++++ b/drivers/misc/Kconfig
+@@ -90,6 +90,7 @@ config ATMEL_TCLIB
+ config ATMEL_TCB_CLKSRC
+ 	bool "TC Block Clocksource"
+ 	depends on ATMEL_TCLIB
++	select ATMEL_TCB_CLKSRC_32BIT if ARCH_AT91SAM9X5
+ 	default y
+ 	help
+ 	  Select this to get a high precision clocksource based on a
+@@ -112,6 +113,9 @@ config ATMEL_TCB_CLKSRC_BLOCK
+ 	  TC can be used for other purposes, such as PWM generation and
+ 	  interval timing.
+ 
++config ATMEL_TCB_CLKSRC_32BIT
++	boolean
++
+ config IBM_ASM
+ 	tristate "Device driver for IBM RSA service processor"
+ 	depends on X86 && PCI && INPUT && EXPERIMENTAL
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0018-mmc-atmel-mci-add-support-for-ARCH_AT91SAM9X5.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0018-mmc-atmel-mci-add-support-for-ARCH_AT91SAM9X5.patch
new file mode 100644
index 0000000..9f8c4a3
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0018-mmc-atmel-mci-add-support-for-ARCH_AT91SAM9X5.patch
@@ -0,0 +1,100 @@
+From f78b602acdc2f4868a9a8d508a1d736c84a67855 Mon Sep 17 00:00:00 2001
+From: Dan Liang <dan.liang@atmel.com>
+Date: Tue, 21 Sep 2010 17:30:15 +0800
+Subject: [PATCH 018/107] mmc/atmel-mci: add support for ARCH_AT91SAM9X5
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Change the calculation method for mci clock divider to match new
+MCI IP that is present on 5 series chips.
+Add Kconfig item to enable dma for mci on those chips.
+
+XXX: this patch interdepends with SAM9x5 support
+
+Signed-off-by: Dan Liang <dan.liang@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/mmc/host/Kconfig          |    2 +-
+ drivers/mmc/host/atmel-mci-regs.h |    1 +
+ drivers/mmc/host/atmel-mci.c      |   31 ++++++++++++++++++++++---------
+ 3 files changed, 24 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
+index 94df405..0cfb38d 100644
+--- a/drivers/mmc/host/Kconfig
++++ b/drivers/mmc/host/Kconfig
+@@ -282,7 +282,7 @@ endchoice
+ 
+ config MMC_ATMELMCI_DMA
+ 	bool "Atmel MCI DMA support (EXPERIMENTAL)"
+-	depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE && EXPERIMENTAL
++	depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45 || ARCH_AT91SAM9X5) && DMA_ENGINE && EXPERIMENTAL
+ 	help
+ 	  Say Y here to have the Atmel MCI driver use a DMA engine to
+ 	  do data transfers and thus increase the throughput and
+diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
+index fc8a0fe..bf51583 100644
+--- a/drivers/mmc/host/atmel-mci-regs.h
++++ b/drivers/mmc/host/atmel-mci-regs.h
+@@ -31,6 +31,7 @@
+ # define MCI_MR_PDCFBYTE	(  1 << 13)	/* Force Byte Transfer */
+ # define MCI_MR_PDCPADV		(  1 << 14)	/* Padding Value */
+ # define MCI_MR_PDCMODE		(  1 << 15)	/* PDC-oriented Mode */
++# define MCI_MR_CLKODD(x)	((x) << 16)	/* LSB of clock divider */
+ #define MCI_DTOR		0x0008	/* Data Timeout */
+ # define MCI_DTOCYC(x)		((x) <<  0)	/* Data Timeout Cycles */
+ # define MCI_DTOMUL(x)		((x) <<  4)	/* Data Timeout Multiplier */
+diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
+index ea3888b..f6b2552 100644
+--- a/drivers/mmc/host/atmel-mci.c
++++ b/drivers/mmc/host/atmel-mci.c
+@@ -236,7 +236,7 @@ static bool mci_has_rwproof(void)
+  */
+ static inline bool atmci_is_mci2(void)
+ {
+-	if (cpu_is_at91sam9g45())
++	if (cpu_is_at91sam9g45() || cpu_is_at91sam9x5())
+ 		return true;
+ 
+ 	return false;
+@@ -943,15 +943,28 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ 		}
+ 
+ 		/* Calculate clock divider */
+-		clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
+-		if (clkdiv > 255) {
+-			dev_warn(&mmc->class_dev,
+-				"clock %u too slow; using %lu\n",
+-				clock_min, host->bus_hz / (2 * 256));
+-			clkdiv = 255;
+-		}
++		if (!cpu_is_at91sam9x5()) {
++			clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
++			if (clkdiv > 255) {
++				dev_warn(&mmc->class_dev,
++					"clock %u too slow; using %lu\n",
++					clock_min, host->bus_hz / (2 * 256));
++				clkdiv = 255;
++			}
++
++			host->mode_reg = MCI_MR_CLKDIV(clkdiv);
++		} else {
++			clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
++			if (clkdiv > 511) {
++				dev_warn(&mmc->class_dev,
++					"clock %u too slow; using %lu\n",
++					clock_min, host->bus_hz / (511 + 2));
++				clkdiv = 511;
++			}
+ 
+-		host->mode_reg = MCI_MR_CLKDIV(clkdiv);
++			host->mode_reg = MCI_MR_CLKDIV(clkdiv >> 1)
++					| MCI_MR_CLKODD(clkdiv & 1);
++		}
+ 
+ 		/*
+ 		 * WRPROOF and RDPROOF prevent overruns/underruns by
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0019-serial-atmel-convert-to-use-dma-engine.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0019-serial-atmel-convert-to-use-dma-engine.patch
new file mode 100644
index 0000000..8d0e6c3
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0019-serial-atmel-convert-to-use-dma-engine.patch
@@ -0,0 +1,562 @@
+From 205c6f82d62bc708de77fb3f3a221c4fef53d2eb Mon Sep 17 00:00:00 2001
+From: Dan Liang <dan.liang@atmel.com>
+Date: Mon, 18 Apr 2011 17:33:47 +0200
+Subject: [PATCH 019/107] serial/atmel: convert to use dma engine
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+XXX: make it runtime conditional or convert PDC to dma engine?
+XXX: why is it necessary to #include <mach/at_hdmac.h>?
+
+Signed-off-by: Dan Liang <dan.liang@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/tty/serial/Kconfig        |   10 +-
+ drivers/tty/serial/atmel_serial.c |  293 +++++++++++++++++++++++++++++++++---
+ 2 files changed, 277 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
+index 80484af..9bbe2d0 100644
+--- a/drivers/tty/serial/Kconfig
++++ b/drivers/tty/serial/Kconfig
+@@ -371,7 +371,7 @@ config SERIAL_ATMEL_CONSOLE
+ 
+ config SERIAL_ATMEL_PDC
+ 	bool "Support DMA transfers on AT91 / AT32 serial port"
+-	depends on SERIAL_ATMEL
++	depends on SERIAL_ATMEL && !(ARCH_AT91SAM9X5)
+ 	default y
+ 	help
+ 	  Say Y here if you wish to use the PDC to do DMA transfers to
+@@ -384,6 +384,14 @@ config SERIAL_ATMEL_PDC
+ 	  properly when DMA is enabled. Make sure that ports where
+ 	  this matters don't use DMA.
+ 
++config SERIAL_ATMEL_DMA
++	bool "Atmel Serial DMA support"
++	depends on SERIAL_ATMEL && ARCH_AT91SAM9X5 && DMA_ENGINE && EXPERIMENTAL
++	default y
++	help
++	  Say Y here to have the Atmel serial driver use a DMA engine to do data
++	  transfers and thus increase the throughput and reduce the CPU utilization.
++
+ config SERIAL_ATMEL_TTYAT
+ 	bool "Install as device ttyATn instead of ttySn"
+ 	depends on SERIAL_ATMEL=y
+diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
+index f119d17..205e496 100644
+--- a/drivers/tty/serial/atmel_serial.c
++++ b/drivers/tty/serial/atmel_serial.c
+@@ -45,6 +45,7 @@
+ 
+ #include <asm/mach/serial_at91.h>
+ #include <mach/board.h>
++#include <mach/at_hdmac.h>
+ 
+ #ifdef CONFIG_ARM
+ #include <mach/cpu.h>
+@@ -141,13 +142,22 @@ struct atmel_uart_port {
+ 	u32			backup_imr;	/* IMR saved during suspend */
+ 	int			break_active;	/* break being received */
+ 
+-	short			use_dma_rx;	/* enable PDC receiver */
++	short			use_dma_rx;	/* enable DMA receiver */
+ 	short			pdc_rx_idx;	/* current PDC RX buffer */
+ 	struct atmel_dma_buffer	pdc_rx[2];	/* PDC receier */
+ 
+-	short			use_dma_tx;	/* enable PDC transmitter */
++	short			use_dma_tx;	/* enable DMA transmitter */
+ 	struct atmel_dma_buffer	pdc_tx;		/* PDC transmitter */
+ 
++	spinlock_t			lock_tx;	/* port lock */
++	struct dma_chan			*chan_tx;
++	struct dma_async_tx_descriptor	*desc_tx;
++	dma_cookie_t			cookie_tx;
++
++	signed int			xmit_head;
++	struct scatterlist		sg_tx;
++	unsigned int			sg_len_tx;
++
+ 	struct tasklet_struct	tasklet;
+ 	unsigned int		irq_status;
+ 	unsigned int		irq_status_prev;
+@@ -171,25 +181,39 @@ to_atmel_uart_port(struct uart_port *uart)
+ }
+ 
+ #ifdef CONFIG_SERIAL_ATMEL_PDC
+-static bool atmel_use_dma_rx(struct uart_port *port)
++static bool atmel_use_pdc_rx(struct uart_port *port)
+ {
+ 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ 
+ 	return atmel_port->use_dma_rx;
+ }
+ 
+-static bool atmel_use_dma_tx(struct uart_port *port)
++static bool atmel_use_pdc_tx(struct uart_port *port)
+ {
+ 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ 
+ 	return atmel_port->use_dma_tx;
+ }
+ #else
+-static bool atmel_use_dma_rx(struct uart_port *port)
++static bool atmel_use_pdc_rx(struct uart_port *port)
++{
++	return false;
++}
++
++static bool atmel_use_pdc_tx(struct uart_port *port)
+ {
+ 	return false;
+ }
++#endif
+ 
++#ifdef CONFIG_SERIAL_ATMEL_DMA
++static bool atmel_use_dma_tx(struct uart_port *port)
++{
++	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++
++	return atmel_port->use_dma_tx;
++}
++#else
+ static bool atmel_use_dma_tx(struct uart_port *port)
+ {
+ 	return false;
+@@ -222,7 +246,7 @@ void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
+ 		mode |= ATMEL_US_USMODE_RS485;
+ 	} else {
+ 		dev_dbg(port->dev, "Setting UART to RS232\n");
+-		if (atmel_use_dma_tx(port))
++		if (atmel_use_pdc_tx(port))
+ 			atmel_port->tx_done_mask = ATMEL_US_ENDTX |
+ 				ATMEL_US_TXBUFE;
+ 		else
+@@ -334,10 +358,11 @@ static void atmel_stop_tx(struct uart_port *port)
+ {
+ 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ 
+-	if (atmel_use_dma_tx(port)) {
++	if (atmel_use_pdc_tx(port)) {
+ 		/* disable PDC transmit */
+ 		UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
+ 	}
++
+ 	/* Disable interrupts */
+ 	UART_PUT_IDR(port, atmel_port->tx_done_mask);
+ 
+@@ -352,7 +377,7 @@ static void atmel_start_tx(struct uart_port *port)
+ {
+ 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ 
+-	if (atmel_use_dma_tx(port)) {
++	if (atmel_use_pdc_tx(port)) {
+ 		if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
+ 			/* The transmitter is already running.  Yes, we
+ 			   really need this.*/
+@@ -364,6 +389,7 @@ static void atmel_start_tx(struct uart_port *port)
+ 		/* re-enable PDC transmit */
+ 		UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
+ 	}
++
+ 	/* Enable interrupts */
+ 	UART_PUT_IER(port, atmel_port->tx_done_mask);
+ }
+@@ -375,7 +401,7 @@ static void atmel_start_rx(struct uart_port *port)
+ {
+ 	UART_PUT_CR(port, ATMEL_US_RSTSTA);  /* reset status and receiver */
+ 
+-	if (atmel_use_dma_rx(port)) {
++	if (atmel_use_pdc_rx(port)) {
+ 		/* enable PDC controller */
+ 		UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
+ 			port->read_status_mask);
+@@ -390,7 +416,7 @@ static void atmel_start_rx(struct uart_port *port)
+  */
+ static void atmel_stop_rx(struct uart_port *port)
+ {
+-	if (atmel_use_dma_rx(port)) {
++	if (atmel_use_pdc_rx(port)) {
+ 		/* disable PDC receive */
+ 		UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
+ 		UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
+@@ -547,6 +573,207 @@ static void atmel_tx_chars(struct uart_port *port)
+ 		UART_PUT_IER(port, atmel_port->tx_done_mask);
+ }
+ 
++#ifdef CONFIG_SERIAL_ATMEL_DMA
++static void atmel_dma_tx_complete(void *arg)
++{
++	struct atmel_uart_port *atmel_port = arg;
++	struct uart_port *port = &atmel_port->uart;
++	struct circ_buf *xmit = &port->state->xmit;
++	unsigned long flags;
++
++	spin_lock_irqsave(&port->lock, flags);
++
++	xmit->tail += sg_dma_len(&atmel_port->sg_tx);
++	xmit->tail &= UART_XMIT_SIZE - 1;
++
++	port->icount.tx += sg_dma_len(&atmel_port->sg_tx);
++
++	spin_lock_irq(&atmel_port->lock_tx);
++	async_tx_ack(atmel_port->desc_tx);
++	atmel_port->cookie_tx = -EINVAL;
++	atmel_port->desc_tx = NULL;
++	spin_unlock_irq(&atmel_port->lock_tx);
++
++	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++		uart_write_wakeup(port);
++
++	/* Do we really need this? */
++	if (!uart_circ_empty(xmit)) {
++		tasklet_schedule(&atmel_port->tasklet);
++	}
++
++	spin_unlock_irqrestore(&port->lock, flags);
++}
++
++static void atmel_tx_dma_release(struct atmel_uart_port *atmel_port)
++{
++	struct dma_chan *chan = atmel_port->chan_tx;
++
++	atmel_port->chan_tx = NULL;
++	atmel_port->cookie_tx = -EINVAL;
++	if (chan) {
++		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
++		dma_release_channel(chan);
++	}
++}
++
++/*
++ * Called from tasklet with TXRDY interrupt is disabled.
++ */
++static void atmel_tx_dma(struct uart_port *port)
++{
++	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++	struct circ_buf *xmit = &port->state->xmit;
++	struct dma_chan *chan = atmel_port->chan_tx;
++	struct dma_async_tx_descriptor *desc;
++	struct scatterlist *sg = &atmel_port->sg_tx;
++
++	spin_lock_irq(&atmel_port->lock_tx);
++	/* Make sure we have an idle channel */
++	if (atmel_port->desc_tx != NULL) {
++		spin_lock_irq(&atmel_port->lock_tx);
++		return;
++	}
++	spin_unlock_irq(&atmel_port->lock_tx);
++
++	if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
++		/*
++		 * DMA is idle now.
++		 * Port xmit buffer is already mapped, and it is one page... Just adjust
++		 * offsets and lengths. Since it is a circular buffer, we have to
++		 * transmit till the end, and then the rest. Take the port lock to get a
++		 * consistent xmit buffer state.
++		 */
++		spin_lock_irq(&port->lock);
++		if (atmel_port->xmit_head != -1) {
++			if (atmel_port->xmit_head != xmit->head) {
++				atmel_port->xmit_head = xmit->head;
++			} else {
++				spin_unlock_irq(&port->lock);
++				return;
++			}
++		} else {
++			atmel_port->xmit_head = xmit->head;
++		}
++
++		sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
++		sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1))
++							+ sg->offset;
++		sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
++		spin_unlock_irq(&port->lock);
++
++		BUG_ON(!sg_dma_len(sg));
++
++		desc = chan->device->device_prep_slave_sg(chan,
++				sg, atmel_port->sg_len_tx, DMA_TO_DEVICE,
++				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++		if (!desc) {
++			spin_unlock_irq(&port->lock);
++			printk (KERN_ERR "#### Error! Failed to send via dma!\n");
++			return;
++		}
++
++		dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
++
++		spin_lock_irq(&port->lock);
++		atmel_port->desc_tx = desc;
++		desc->callback = atmel_dma_tx_complete;
++		desc->callback_param = atmel_port;
++		spin_unlock_irq(&port->lock);
++		atmel_port->cookie_tx = desc->tx_submit(desc);
++		if (atmel_port->cookie_tx < 0) {
++			dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
++			/* switch to PIO */
++			atmel_tx_dma_release(atmel_port);
++			return;
++		}
++
++		dma_async_issue_pending(chan);
++	} else {
++		if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
++			/* DMA done, stop TX, start RX for RS485 */
++			atmel_start_rx(port);
++		}
++	}
++
++	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++		uart_write_wakeup(port);
++}
++
++static bool filter(struct dma_chan *chan, void *slave)
++{
++	struct	at_dma_slave		*sl = slave;
++
++	if (sl->dma_dev == chan->device->dev) {
++		chan->private = sl;
++		return true;
++	} else {
++		return false;
++	}
++}
++
++static void atmel_tx_request_dma(struct atmel_uart_port *atmel_port)
++{
++	struct uart_port	*port;
++	struct atmel_uart_data	*pdata;
++	dma_cap_mask_t		mask;
++	struct dma_chan		*chan = NULL;
++
++	if (atmel_port == NULL)
++		return;
++
++	port = &(atmel_port->uart);
++	pdata = (struct atmel_uart_data *)port->private_data;
++
++	if (!pdata) {
++		dev_notice(port->dev, "DMA not available, using PIO\n");
++		return;
++	}
++
++	dma_cap_zero(mask);
++	dma_cap_set(DMA_SLAVE, mask);
++
++	if (atmel_use_dma_tx(port) && pdata->dma_tx_slave) {
++		pdata->dma_tx_slave->tx_reg = port->mapbase + ATMEL_US_THR;
++		chan = dma_request_channel(mask, filter, pdata->dma_tx_slave);
++		dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
++	}
++
++	if (chan) {
++		int nent;
++
++		spin_lock_init(&atmel_port->lock_tx);
++		atmel_port->chan_tx = chan;
++
++		sg_init_table(&atmel_port->sg_tx, 1);
++		/* UART circular tx buffer is an aligned page. */
++		BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
++		sg_set_page(&atmel_port->sg_tx,
++				virt_to_page(port->state->xmit.buf),
++				UART_XMIT_SIZE,
++				(int)port->state->xmit.buf & ~PAGE_MASK);
++				nent = dma_map_sg(port->dev, &atmel_port->sg_tx, 1,
++				DMA_TO_DEVICE);
++
++		if (!nent)
++			dev_dbg(port->dev, "need to release resource of dma\n");
++		else
++			dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
++				sg_dma_len(&atmel_port->sg_tx),
++				port->state->xmit.buf,
++				sg_dma_address(&atmel_port->sg_tx));
++
++		atmel_port->sg_len_tx = nent;
++		atmel_port->xmit_head = -1;
++	}
++}
++#else
++static void atmel_dma_tx_complete(void *arg) {}
++static void atmel_tx_dma_release(struct atmel_uart_port *atmel_port) {}
++static void atmel_tx_dma(struct uart_port *port) {}
++static void atmel_tx_request_dma(struct atmel_uart_port *atmel_port) {}
++#endif
++
+ /*
+  * receive interrupt handler.
+  */
+@@ -555,7 +782,7 @@ atmel_handle_receive(struct uart_port *port, unsigned int pending)
+ {
+ 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ 
+-	if (atmel_use_dma_rx(port)) {
++	if (atmel_use_pdc_rx(port)) {
+ 		/*
+ 		 * PDC receive. Just schedule the tasklet and let it
+ 		 * figure out the details.
+@@ -644,7 +871,7 @@ static irqreturn_t atmel_interrupt(int irq, void *dev_id)
+ /*
+  * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
+  */
+-static void atmel_tx_dma(struct uart_port *port)
++static void atmel_tx_pdc(struct uart_port *port)
+ {
+ 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ 	struct circ_buf *xmit = &port->state->xmit;
+@@ -760,7 +987,7 @@ static void atmel_rx_from_ring(struct uart_port *port)
+ 	spin_lock(&port->lock);
+ }
+ 
+-static void atmel_rx_from_dma(struct uart_port *port)
++static void atmel_rx_from_pdc(struct uart_port *port)
+ {
+ 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ 	struct tty_struct *tty = port->state->port.tty;
+@@ -849,7 +1076,9 @@ static void atmel_tasklet_func(unsigned long data)
+ 	/* The interrupt handler does not take the lock */
+ 	spin_lock(&port->lock);
+ 
+-	if (atmel_use_dma_tx(port))
++	if (atmel_use_pdc_tx(port))
++		atmel_tx_pdc(port);
++	else if (atmel_use_dma_tx(port))
+ 		atmel_tx_dma(port);
+ 	else
+ 		atmel_tx_chars(port);
+@@ -874,8 +1103,8 @@ static void atmel_tasklet_func(unsigned long data)
+ 		atmel_port->irq_status_prev = status;
+ 	}
+ 
+-	if (atmel_use_dma_rx(port))
+-		atmel_rx_from_dma(port);
++	if (atmel_use_pdc_rx(port))
++		atmel_rx_from_pdc(port);
+ 	else
+ 		atmel_rx_from_ring(port);
+ 
+@@ -911,7 +1140,7 @@ static int atmel_startup(struct uart_port *port)
+ 	/*
+ 	 * Initialize DMA (if necessary)
+ 	 */
+-	if (atmel_use_dma_rx(port)) {
++	if (atmel_use_pdc_rx(port)) {
+ 		int i;
+ 
+ 		for (i = 0; i < 2; i++) {
+@@ -945,7 +1174,8 @@ static int atmel_startup(struct uart_port *port)
+ 		UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
+ 		UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
+ 	}
+-	if (atmel_use_dma_tx(port)) {
++	if (atmel_use_pdc_tx(port)) {
++
+ 		struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
+ 		struct circ_buf *xmit = &port->state->xmit;
+ 
+@@ -958,6 +1188,9 @@ static int atmel_startup(struct uart_port *port)
+ 		pdc->ofs = 0;
+ 	}
+ 
++	if (atmel_use_dma_tx(port))
++		atmel_tx_request_dma(atmel_port);
++
+ 	/*
+ 	 * If there is a specific "open" function (to register
+ 	 * control line interrupts)
+@@ -981,7 +1214,7 @@ static int atmel_startup(struct uart_port *port)
+ 	/* enable xmit & rcvr */
+ 	UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
+ 
+-	if (atmel_use_dma_rx(port)) {
++	if (atmel_use_pdc_rx(port)) {
+ 		/* set UART timeout */
+ 		UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
+ 		UART_PUT_CR(port, ATMEL_US_STTTO);
+@@ -1012,7 +1245,7 @@ static void atmel_shutdown(struct uart_port *port)
+ 	/*
+ 	 * Shut-down the DMA.
+ 	 */
+-	if (atmel_use_dma_rx(port)) {
++	if (atmel_use_pdc_rx(port)) {
+ 		int i;
+ 
+ 		for (i = 0; i < 2; i++) {
+@@ -1025,7 +1258,7 @@ static void atmel_shutdown(struct uart_port *port)
+ 			kfree(pdc->buf);
+ 		}
+ 	}
+-	if (atmel_use_dma_tx(port)) {
++	if (atmel_use_pdc_tx(port)) {
+ 		struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
+ 
+ 		dma_unmap_single(port->dev,
+@@ -1034,6 +1267,9 @@ static void atmel_shutdown(struct uart_port *port)
+ 				 DMA_TO_DEVICE);
+ 	}
+ 
++	if (atmel_use_dma_tx(port)) {
++		atmel_tx_dma_release(atmel_port);
++	}
+ 	/*
+ 	 * Disable all interrupts, port and break condition.
+ 	 */
+@@ -1061,10 +1297,16 @@ static void atmel_flush_buffer(struct uart_port *port)
+ {
+ 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ 
+-	if (atmel_use_dma_tx(port)) {
++	if (atmel_use_pdc_tx(port)) {
+ 		UART_PUT_TCR(port, 0);
+ 		atmel_port->pdc_tx.ofs = 0;
+ 	}
++
++	if (atmel_use_dma_tx(port)) {
++		struct dma_chan *chan = atmel_port->chan_tx;
++		if (chan)
++			chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
++	}
+ }
+ 
+ /*
+@@ -1174,7 +1416,7 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
+ 	if (termios->c_iflag & (BRKINT | PARMRK))
+ 		port->read_status_mask |= ATMEL_US_RXBRK;
+ 
+-	if (atmel_use_dma_rx(port))
++	if (atmel_use_pdc_rx(port))
+ 		/* need to enable error interrupts */
+ 		UART_PUT_IER(port, port->read_status_mask);
+ 
+@@ -1426,6 +1668,7 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
+ 	port->dev		= &pdev->dev;
+ 	port->mapbase	= pdev->resource[0].start;
+ 	port->irq	= pdev->resource[1].start;
++	port->private_data	= data;
+ 
+ 	tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
+ 			(unsigned long)port);
+@@ -1455,7 +1698,7 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
+ 	/* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
+ 	if (atmel_port->rs485.flags & SER_RS485_ENABLED)
+ 		atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
+-	else if (atmel_use_dma_tx(port)) {
++	else if (atmel_use_pdc_tx(port)) {
+ 		port->fifosize = PDC_BUFFER_SIZE;
+ 		atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
+ 	} else {
+@@ -1721,7 +1964,7 @@ static int __devinit atmel_serial_probe(struct platform_device *pdev)
+ 
+ 	atmel_init_port(port, pdev);
+ 
+-	if (!atmel_use_dma_rx(&port->uart)) {
++	if (!atmel_use_pdc_rx(&port->uart)) {
+ 		ret = -ENOMEM;
+ 		data = kmalloc(sizeof(struct atmel_uart_char)
+ 				* ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0020-video-atmel_lcdfb-add-support-for-AT91SAM9x5.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0020-video-atmel_lcdfb-add-support-for-AT91SAM9x5.patch
new file mode 100644
index 0000000..03f999c
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0020-video-atmel_lcdfb-add-support-for-AT91SAM9x5.patch
@@ -0,0 +1,1803 @@
+From 71d1ed74b58a2b9d368ef95de74bd3480190a7d1 Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Mon, 1 Nov 2010 16:38:41 +0800
+Subject: [PATCH 020/107] video/atmel_lcdfb: add support for AT91SAM9x5
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+Signed-off-by: Dan Liang <dan.liang@atmel.com>
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+[ukleinek: forward-port to 2.6.39ish, fixed LCDC_LCDIxR_HEOIx]
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/mach-at91/include/mach/atmel_hlcdfb.h |  868 ++++++++++++++++++++++++
+ drivers/video/atmel_lcdfb.c                    |  661 ++++++++++++++-----
+ include/video/atmel_lcdc.h                     |   15 +
+ 3 files changed, 1388 insertions(+), 156 deletions(-)
+ create mode 100644 arch/arm/mach-at91/include/mach/atmel_hlcdfb.h
+
+diff --git a/arch/arm/mach-at91/include/mach/atmel_hlcdfb.h b/arch/arm/mach-at91/include/mach/atmel_hlcdfb.h
+new file mode 100644
+index 0000000..debb8ce
+--- /dev/null
++++ b/arch/arm/mach-at91/include/mach/atmel_hlcdfb.h
+@@ -0,0 +1,868 @@
++/*
++ *  Header file for AT91 High end LCD Controller
++ *
++ *  Data structure and register user interface
++ *
++ *  Copyright (C) 2010 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PUROFFSETE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#ifndef __ATMEL_HLCD_H__
++#define __ATMEL_HLCD_H__
++
++/* Lcdc hardware registers */
++#define ATMEL_LCDC_LCDCFG0	0x0000
++#define LCDC_LCDCFG0_CLKPOL		(0x1 << 0)
++#define LCDC_LCDCFG0_CLKSEL		(0x1 << 2)
++#define LCDC_LCDCFG0_CLKPWMSEL		(0x1 << 3)
++#define LCDC_LCDCFG0_CGDISBASE		(0x1 << 8)
++#define LCDC_LCDCFG0_CGDISOVR1		(0x1 << 9)
++/* XXX: maybe this is 1 << 10? At least the LCD Interrupt registers
++ * use 10 while the documentation specifies 11.
++ */
++#define LCDC_LCDCFG0_CGDISHEO		(0x1 << 11)
++#define LCDC_LCDCFG0_CGDISHCR		(0x1 << 12)
++#define LCDC_LCDCFG0_CLKDIV_OFFSET	16
++#define LCDC_LCDCFG0_CLKDIV		(0xff << LCDC_LCDCFG0_CLKDIV_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG1	0x0004
++#define LCDC_LCDCFG1_HSPW_OFFSET	0
++#define LCDC_LCDCFG1_HSPW		(0x3f << LCDC_LCDCFG1_HSPW_OFFSET)
++#define LCDC_LCDCFG1_VSPW_OFFSET	16
++#define LCDC_LCDCFG1_VSPW		(0x3f << LCDC_LCDCFG1_VSPW_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG2	0x0008
++#define LCDC_LCDCFG2_VFPW_OFFSET	0
++#define LCDC_LCDCFG2_VFPW		(0x3f << LCDC_LCDCFG2_VFPW_OFFSET)
++#define LCDC_LCDCFG2_VBPW_OFFSET	16
++#define LCDC_LCDCFG2_VBPW		(0x3f << LCDC_LCDCFG2_VBPW_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG3	0x000C
++#define LCDC_LCDCFG3_HFPW_OFFSET	0
++#define LCDC_LCDCFG3_HFPW		(0xff << LCDC_LCDCFG3_HFPW_OFFSET)
++#define LCDC_LCDCFG3_HBPW_OFFSET	16
++#define LCDC_LCDCFG3_HBPW		(0xff << LCDC_LCDCFG3_HBPW_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG4	0x0010
++#define LCDC_LCDCFG4_PPL_OFFSET		0
++#define LCDC_LCDCFG4_PPL		(0x7ff << LCDC_LCDCFG4_PPL_OFFSET)
++#define LCDC_LCDCFG4_RPF_OFFSET		16
++#define LCDC_LCDCFG4_RPF		(0x7ff << LCDC_LCDCFG4_RPF_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG5	0x0014
++#define LCDC_LCDCFG5_HSPOL		(0x1 << 0)
++#define LCDC_LCDCFG5_VSPOL		(0x1 << 1)
++#define LCDC_LCDCFG5_VSPDLYS		(0x1 << 2)
++#define LCDC_LCDCFG5_VSPDLYE		(0x1 << 3)
++#define LCDC_LCDCFG5_DISPPOL		(0x1 << 4)
++#define LCDC_LCDCFG5_SERIAL		(0x1 << 5)
++#define LCDC_LCDCFG5_DITHER		(0x1 << 6)
++#define LCDC_LCDCFG5_DISPDLY		(0x1 << 7)
++#define LCDC_LCDCFG5_MODE_OFFSET	8
++#define LCDC_LCDCFG5_MODE		(0x3 << LCDC_LCDCFG5_MODE_OFFSET)
++#define		LCDC_LCDCFG5_MODE_OUTPUT_12BPP		(0x0 << 8)
++#define		LCDC_LCDCFG5_MODE_OUTPUT_16BPP		(0x1 << 8)
++#define		LCDC_LCDCFG5_MODE_OUTPUT_18BPP		(0x2 << 8)
++#define		LCDC_LCDCFG5_MODE_OUTPUT_24BPP		(0x3 << 8)
++#define LCDC_LCDCFG5_VSPSU		(0x1 << 12)
++#define LCDC_LCDCFG5_VSPHO		(0x1 << 13)
++#define LCDC_LCDCFG5_GUARDTIME_OFFSET	16
++#define LCDC_LCDCFG5_GUARDTIME		(0x1f << LCDC_LCDCFG5_GUARDTIME_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG6	0x0018
++#define LCDC_LCDCFG6_PWMPS_OFFSET	0
++#define LCDC_LCDCFG6_PWMPS		(0x7 << LCDC_LCDCFG6_PWMPS_OFFSET)
++#define LCDC_LCDCFG6_PWMPOL		(0x1 << 4)
++#define LCDC_LCDCFG6_PWMCVAL_OFFSET	8
++#define LCDC_LCDCFG6_PWMCVAL		(0xff << LCDC_LCDCFG6_PWMCVAL_OFFSET)
++
++#define ATMEL_LCDC_LCDEN	0x0020
++#define LCDC_LCDEN_CLKEN		(0x1 << 0)
++#define LCDC_LCDEN_SYNCEN		(0x1 << 1)
++#define LCDC_LCDEN_DISPEN		(0x1 << 2)
++#define LCDC_LCDEN_PWMEN		(0x1 << 3)
++
++#define ATMEL_LCDC_LCDDIS	0x0024
++#define LCDC_LCDDIS_CLKDIS		(0x1 << 0)
++#define LCDC_LCDDIS_SYNCDIS		(0x1 << 1)
++#define LCDC_LCDDIS_DISPDIS		(0x1 << 2)
++#define LCDC_LCDDIS_PWMDIS		(0x1 << 3)
++#define LCDC_LCDDIS_CLKRST		(0x1 << 8)
++#define LCDC_LCDDIS_SYNCRST		(0x1 << 9)
++#define LCDC_LCDDIS_DISPRST		(0x1 << 10)
++#define LCDC_LCDDIS_PWMRST		(0x1 << 11)
++
++#define ATMEL_LCDC_LCDSR	0x0028
++#define LCDC_LCDSR_CLKSTS		(0x1 << 0)
++#define LCDC_LCDSR_LCDSTS		(0x1 << 1)
++#define LCDC_LCDSR_DISPSTS		(0x1 << 2)
++#define LCDC_LCDSR_PWMSTS		(0x1 << 3)
++#define LCDC_LCDSR_SIPSTS		(0x1 << 4)
++
++#define ATMEL_LCDC_LCDIER	0x002C
++#define LCDC_LCDIER_SOFIE		(0x1 << 0)
++#define LCDC_LCDIER_DISIE		(0x1 << 1)
++#define LCDC_LCDIER_DISPIE		(0x1 << 2)
++#define LCDC_LCDIER_FIFOERRIE		(0x1 << 4)
++#define LCDC_LCDIER_BASEIE		(0x1 << 8)
++#define LCDC_LCDIER_OVR1IE		(0x1 << 9)
++#define LCDC_LCDIER_HEOIE		(0x1 << 10)
++#define LCDC_LCDIER_HCRIE		(0x1 << 12)
++
++#define ATMEL_LCDC_LCDIDR	0x0030
++#define LCDC_LCDIDR_SOFID		(0x1 << 0)
++#define LCDC_LCDIDR_DISID		(0x1 << 1)
++#define LCDC_LCDIDR_DISPID		(0x1 << 2)
++#define LCDC_LCDIDR_FIFOERRID		(0x1 << 4)
++#define LCDC_LCDIDR_BASEID		(0x1 << 8)
++#define LCDC_LCDIDR_OVR1ID		(0x1 << 9)
++#define LCDC_LCDIDR_HEOID		(0x1 << 10)
++#define LCDC_LCDIDR_HCRID		(0x1 << 12)
++
++#define ATMEL_LCDC_LCDIMR	0x0034
++#define LCDC_LCDIMR_SOFIM		(0x1 << 0)
++#define LCDC_LCDIMR_DISIM		(0x1 << 1)
++#define LCDC_LCDIMR_DISPIM		(0x1 << 2)
++#define LCDC_LCDIMR_FIFOERRIM		(0x1 << 4)
++#define LCDC_LCDIMR_BASEIM		(0x1 << 8)
++#define LCDC_LCDIMR_OVR1IM		(0x1 << 9)
++#define LCDC_LCDIMR_HEOIM		(0x1 << 10)
++#define LCDC_LCDIMR_HCRIM		(0x1 << 12)
++
++#define ATMEL_LCDC_LCDISR	0x0038
++#define LCDC_LCDISR_SOF			(0x1 << 0)
++#define LCDC_LCDISR_DIS			(0x1 << 1)
++#define LCDC_LCDISR_DISP		(0x1 << 2)
++#define LCDC_LCDISR_FIFOERR		(0x1 << 4)
++#define LCDC_LCDISR_BASE		(0x1 << 8)
++#define LCDC_LCDISR_OVR1		(0x1 << 9)
++#define LCDC_LCDISR_HEO			(0x1 << 10)
++#define LCDC_LCDISR_HCR			(0x1 << 12)
++
++#define ATMEL_LCDC_BASECHER	0x0040
++#define LCDC_BASECHER_CHEN		(0x1 << 0)
++#define LCDC_BASECHER_UPDATEEN		(0x1 << 1)
++#define LCDC_BASECHER_A2QEN		(0x1 << 2)
++
++#define ATMEL_LCDC_BASECHDR	0x0044
++#define LCDC_BASECHDR_CHDIS		(0x1 << 0)
++#define LCDC_BASECHDR_CHRST		(0x1 << 8)
++
++#define ATMEL_LCDC_BASECHSR	0x0048
++#define LCDC_BASECHSR_CHSR		(0x1 << 0)
++#define LCDC_BASECHSR_UPDATESR		(0x1 << 1)
++#define LCDC_BASECHSR_A2QSR		(0x1 << 2)
++
++#define ATMEL_LCDC_BASEIER	0x004C
++#define LCDC_BASEIER_DMA		(0x1 << 2)
++#define LCDC_BASEIER_DSCR		(0x1 << 3)
++#define LCDC_BASEIER_ADD		(0x1 << 4)
++#define LCDC_BASEIER_DONE		(0x1 << 5)
++#define LCDC_BASEIER_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_BASEIDR	0x0050
++#define LCDC_BASEIDR_DMA		(0x1 << 2)
++#define LCDC_BASEIDR_DSCR		(0x1 << 3)
++#define LCDC_BASEIDR_ADD		(0x1 << 4)
++#define LCDC_BASEIDR_DONE		(0x1 << 5)
++#define LCDC_BASEIDR_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_BASEIMR	0x0054
++#define LCDC_BASEIMR_DMA		(0x1 << 2)
++#define LCDC_BASEIMR_DSCR		(0x1 << 3)
++#define LCDC_BASEIMR_ADD		(0x1 << 4)
++#define LCDC_BASEIMR_DONE		(0x1 << 5)
++#define LCDC_BASEIMR_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_BASEISR	0x0058
++#define LCDC_BASEISR_DMA		(0x1 << 2)
++#define LCDC_BASEISR_DSCR		(0x1 << 3)
++#define LCDC_BASEISR_ADD		(0x1 << 4)
++#define LCDC_BASEISR_DONE		(0x1 << 5)
++#define LCDC_BASEISR_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_BASEHEAD	0x005C
++
++#define ATMEL_LCDC_BASEADDR	0x0060
++
++#define ATMEL_LCDC_BASECTRL	0x0064
++#define LCDC_BASECTRL_DFETCH		(0x1 << 0)
++#define LCDC_BASECTRL_LFETCH		(0x1 << 1)
++#define LCDC_BASECTRL_DMAIEN		(0x1 << 2)
++#define LCDC_BASECTRL_DSCRIEN		(0x1 << 3)
++#define LCDC_BASECTRL_ADDIEN		(0x1 << 4)
++#define LCDC_BASECTRL_DONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_BASENEXT	0x0068
++
++#define ATMEL_LCDC_BASECFG0	0x006C
++#define LCDC_BASECFG0_BLEN_OFFSET 4
++#define LCDC_BASECFG0_BLEN		(0x3 << LCDC_BASECFG0_BLEN_OFFSET)
++#define		LCDC_BASECFG0_BLEN_AHB_SINGLE		(0x0 << 4)
++#define		LCDC_BASECFG0_BLEN_AHB_INCR4		(0x1 << 4)
++#define		LCDC_BASECFG0_BLEN_AHB_INCR8		(0x2 << 4)
++#define		LCDC_BASECFG0_BLEN_AHB_INCR16		(0x3 << 4)
++#define LCDC_BASECFG0_DLBO		(0x1 << 8)
++
++#define ATMEL_LCDC_BASECFG1	0x0070
++#define LCDC_BASECFG1_CLUTEN		(0x1 << 0)
++#define LCDC_BASECFG1_RGBMODE_OFFSET	4
++#define LCDC_BASECFG1_RGBMODE		(0xf << LCDC_BASECFG1_RGBMODE_OFFSET)
++#define		LCDC_BASECFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
++#define		LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
++#define		LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
++#define		LCDC_BASECFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
++#define		LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
++#define		LCDC_BASECFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
++#define		LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
++#define		LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
++#define		LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
++#define		LCDC_BASECFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
++#define		LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
++#define		LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
++#define		LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
++#define		LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
++#define LCDC_BASECFG1_CLUTMODE_OFFSET	8
++#define LCDC_BASECFG1_CLUTMODE		(0x3 << LCDC_BASECFG1_CLUTMODE_OFFSET)
++#define		LCDC_BASECFG1_CLUTMODE_1BPP		(0x0 << 8)
++#define		LCDC_BASECFG1_CLUTMODE_2BPP		(0x1 << 8)
++#define		LCDC_BASECFG1_CLUTMODE_4BPP		(0x2 << 8)
++#define		LCDC_BASECFG1_CLUTMODE_8BPP		(0x3 << 8)
++
++#define ATMEL_LCDC_BASECFG2	0x0074
++
++#define ATMEL_LCDC_BASECFG3	0x0078
++#define LCDC_BASECFG3_BDEF_OFFSET	0
++#define LCDC_BASECFG3_BDEF		(0xff << LCDC_BASECFG3_BDEF_OFFSET)
++#define LCDC_BASECFG3_GDEF_OFFSET	8
++#define LCDC_BASECFG3_GDEF		(0xff << LCDC_BASECFG3_GDEF_OFFSET)
++#define LCDC_BASECFG3_RDEF_OFFSET	16
++#define LCDC_BASECFG3_RDEF		(0xff << LCDC_BASECFG3_RDEF_OFFSET)
++
++#define ATMEL_LCDC_BASECFG4	0x007C
++#define LCDC_BASECFG4_DMA		(0x1 << 8)
++#define LCDC_BASECFG4_REP		(0x1 << 9)
++
++#define ATMEL_LCDC_OVRCHER1	0x0100
++#define LCDC_OVRCHER1_CHEN		(0x1 << 0)
++#define LCDC_OVRCHER1_UPDATEEN		(0x1 << 1)
++#define LCDC_OVRCHER1_A2QEN		(0x1 << 2)
++
++#define ATMEL_LCDC_OVRCHDR1	0x0104
++#define LCDC_OVRCHDR1_CHDIS		(0x1 << 0)
++#define LCDC_OVRCHDR1_CHRST		(0x1 << 8)
++
++#define ATMEL_LCDC_OVRCHSR1	0x0108
++#define LCDC_OVRCHSR1_CHSR		(0x1 << 0)
++#define LCDC_OVRCHSR1_UPDATESR		(0x1 << 1)
++#define LCDC_OVRCHSR1_A2QSR		(0x1 << 2)
++
++#define ATMEL_LCDC_OVRIER1	0x010C
++#define LCDC_OVRIER1_DMA		(0x1 << 2)
++#define LCDC_OVRIER1_DSCR		(0x1 << 3)
++#define LCDC_OVRIER1_ADD		(0x1 << 4)
++#define LCDC_OVRIER1_DONE		(0x1 << 5)
++#define LCDC_OVRIER1_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_OVRIDR1	0x0110
++#define LCDC_OVRIDR1_DMA		(0x1 << 2)
++#define LCDC_OVRIDR1_DSCR		(0x1 << 3)
++#define LCDC_OVRIDR1_ADD		(0x1 << 4)
++#define LCDC_OVRIDR1_DONE		(0x1 << 5)
++#define LCDC_OVRIDR1_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_OVRIMR1	0x0114
++#define LCDC_OVRIMR1_DMA		(0x1 << 2)
++#define LCDC_OVRIMR1_DSCR		(0x1 << 3)
++#define LCDC_OVRIMR1_ADD		(0x1 << 4)
++#define LCDC_OVRIMR1_DONE		(0x1 << 5)
++#define LCDC_OVRIMR1_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_OVRISR1	0x0118
++#define LCDC_OVRISR1_DMA		(0x1 << 2)
++#define LCDC_OVRISR1_DSCR		(0x1 << 3)
++#define LCDC_OVRISR1_ADD		(0x1 << 4)
++#define LCDC_OVRISR1_DONE		(0x1 << 5)
++#define LCDC_OVRISR1_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_OVRHEAD1	0x011C
++
++#define ATMEL_LCDC_OVRADDR1	0x0120
++
++#define ATMEL_LCDC_OVRCTRL1	0x0124
++#define LCDC_OVRCTRL1_DFETCH		(0x1 << 0)
++#define LCDC_OVRCTRL1_LFETCH		(0x1 << 1)
++#define LCDC_OVRCTRL1_DMAIEN		(0x1 << 2)
++#define LCDC_OVRCTRL1_DSCRIEN		(0x1 << 3)
++#define LCDC_OVRCTRL1_ADDIEN		(0x1 << 4)
++#define LCDC_OVRCTRL1_DONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_OVRNEXT1	0x0128
++
++#define ATMEL_LCDC_OVR1CFG0	0x012C
++#define LCDC_OVR1CFG0_BLEN_OFFSET	4
++#define LCDC_OVR1CFG0_BLEN		(0x3 << LCDC_OVR1CFG0_BLEN_OFFSET)
++#define		LCDC_OVR1CFG0_BLEN_AHB_SINGLE		(0x0 << 4)
++#define		LCDC_OVR1CFG0_BLEN_AHB_INCR4		(0x1 << 4)
++#define		LCDC_OVR1CFG0_BLEN_AHB_INCR8		(0x2 << 4)
++#define		LCDC_OVR1CFG0_BLEN_AHB_INCR16		(0x3 << 4)
++#define LCDC_OVR1CFG0_DLBO		(0x1 << 8)
++#define LCDC_OVR1CFG0_ROTDIS		(0x1 << 12)
++#define LCDC_OVR1CFG0_LOCKDIS		(0x1 << 13)
++
++#define ATMEL_LCDC_OVR1CFG1	0x0130
++#define LCDC_OVR1CFG1_CLUTEN		(0x1 << 0)
++#define LCDC_OVR1CFG1_RGBMODE_OFFSET	4
++#define LCDC_OVR1CFG1_RGBMODE		(0xf << LCDC_OVR1CFG1_RGBMODE_OFFSET)
++#define		LCDC_OVR1CFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
++#define LCDC_OVR1CFG1_CLUTMODE_OFFSET	8
++#define LCDC_OVR1CFG1_CLUTMODE		(0x3 << LCDC_OVR1CFG1_CLUTMODE_OFFSET)
++#define		LCDC_OVR1CFG1_CLUTMODE_1BPP		(0x0 << 8)
++#define		LCDC_OVR1CFG1_CLUTMODE_2BPP		(0x1 << 8)
++#define		LCDC_OVR1CFG1_CLUTMODE_4BPP		(0x2 << 8)
++#define		LCDC_OVR1CFG1_CLUTMODE_8BPP		(0x3 << 8)
++
++#define ATMEL_LCDC_OVR1CFG2	0x0134
++#define LCDC_OVR1CFG2_XOFFSET_OFFSET	0
++#define LCDC_OVR1CFG2_XOFFSET		(0x7ff << LCDC_OVR1CFG2_XOFFSET_OFFSET)
++#define LCDC_OVR1CFG2_YOFFSET_OFFSET	16
++#define LCDC_OVR1CFG2_YOFFSET		(0x7ff << LCDC_OVR1CFG2_YOFFSET_OFFSET)
++
++#define ATMEL_LCDC_OVR1CFG3	0x0138
++#define LCDC_OVR1CFG3_XSIZE_OFFSET	0
++#define LCDC_OVR1CFG3_XSIZE		(0x7ff << LCDC_OVR1CFG3_XSIZE_OFFSET)
++#define LCDC_OVR1CFG3_YSIZE_OFFSET	16
++#define LCDC_OVR1CFG3_YSIZE		(0x7ff << LCDC_OVR1CFG3_YSIZE_OFFSET)
++
++#define ATMEL_LCDC_OVR1CFG4	0x013C
++
++#define ATMEL_LCDC_OVR1CFG5	0x0140
++
++#define ATMEL_LCDC_OVR1CFG6	0x0144
++#define LCDC_OVR1CFG6_BDEF_OFFSET	0
++#define LCDC_OVR1CFG6_BDEF		(0xff << LCDC_OVR1CFG6_BDEF_OFFSET)
++#define LCDC_OVR1CFG6_GDEF_OFFSET	8
++#define LCDC_OVR1CFG6_GDEF		(0xff << LCDC_OVR1CFG6_GDEF_OFFSET)
++#define LCDC_OVR1CFG6_RDEF_OFFSET	16
++#define LCDC_OVR1CFG6_RDEF		(0xff << LCDC_OVR1CFG6_RDEF_OFFSET)
++
++#define ATMEL_LCDC_OVR1CFG7	0x0148
++#define LCDC_OVR1CFG7_BKEY_OFFSET	0
++#define LCDC_OVR1CFG7_BKEY		(0xff << LCDC_OVR1CFG7_BKEY_OFFSET)
++#define LCDC_OVR1CFG7_GKEY_OFFSET	8
++#define LCDC_OVR1CFG7_GKEY		(0xff << LCDC_OVR1CFG7_GKEY_OFFST)
++#define LCDC_OVR1CFG7_RKEY_OFFSET	16
++#define LCDC_OVR1CFG7_RKEY		(0xff << LCDC_OVR1CFG7_RKEY_OFFSET)
++
++#define ATMEL_LCDC_OVR1CFG8	0x014C
++#define LCDC_OVR1CFG8_BMASK_OFFSET	0
++#define LCDC_OVR1CFG8_BMASK		(0xff << LCDC_OVR1CFG8_BMASK_OFFSET)
++#define LCDC_OVR1CFG8_GMASK_OFFSET	8
++#define LCDC_OVR1CFG8_GMASK		(0xff << LCDC_OVR1CFG8_GMASK_OFFSET)
++#define LCDC_OVR1CFG8_RMASK_OFFSET	16
++#define LCDC_OVR1CFG8_RMASK		(0xff << LCDC_OVR1CFG8_RMASK_OFFSET)
++
++#define ATMEL_LCDC_OVR1CFG9	0x0150
++#define LCDC_OVR1CFG9_CRKEY		(0x1 << 0)
++#define LCDC_OVR1CFG9_INV		(0x1 << 1)
++#define LCDC_OVR1CFG9_ITER2BL		(0x1 << 2)
++#define LCDC_OVR1CFG9_ITER		(0x1 << 3)
++#define LCDC_OVR1CFG9_REVALPHA		(0x1 << 4)
++#define LCDC_OVR1CFG9_GAEN		(0x1 << 5)
++#define LCDC_OVR1CFG9_LAEN		(0x1 << 6)
++#define LCDC_OVR1CFG9_OVR		(0x1 << 7)
++#define LCDC_OVR1CFG9_DMA		(0x1 << 8)
++#define LCDC_OVR1CFG9_REP		(0x1 << 9)
++#define LCDC_OVR1CFG9_DSTKEY		(0x1 << 10)
++#define LCDC_OVR1CFG9_GA_OFFSET		16
++#define LCDC_OVR1CFG9_GA		(0xff << LCDC_OVR1CFG9_GA_OFFSET)
++
++#define ATMEL_LCDC_HEOCHER	0x0280
++#define LCDC_HEOCHER_CHEN		(0x1 << 0)
++#define LCDC_HEOCHER_UPDATEEN		(0x1 << 1)
++#define LCDC_HEOCHER_A2QEN		(0x1 << 2)
++
++#define ATMEL_LCDC_HEOCHDR	0x0284
++#define LCDC_HEOCHDR_CHDIS		(0x1 << 0)
++#define LCDC_HEOCHDR_CHRST		(0x1 << 8)
++
++#define ATMEL_LCDC_HEOCHSR	0x0288
++#define LCDC_HEOCHSR_CHSR		(0x1 << 0)
++#define LCDC_HEOCHSR_UPDATESR		(0x1 << 1)
++#define LCDC_HEOCHSR_A2QSR		(0x1 << 2)
++
++#define ATMEL_LCDC_HEOIER	0x028C
++#define LCDC_HEOIER_DMA			(0x1 << 2)
++#define LCDC_HEOIER_DSCR		(0x1 << 3)
++#define LCDC_HEOIER_ADD			(0x1 << 4)
++#define LCDC_HEOIER_DONE		(0x1 << 5)
++#define LCDC_HEOIER_OVR			(0x1 << 6)
++#define LCDC_HEOIER_UDMA		(0x1 << 10)
++#define LCDC_HEOIER_UDSCR		(0x1 << 11)
++#define LCDC_HEOIER_UADD		(0x1 << 12)
++#define LCDC_HEOIER_UDONE		(0x1 << 13)
++#define LCDC_HEOIER_UOVR		(0x1 << 14)
++#define LCDC_HEOIER_VDMA		(0x1 << 18)
++#define LCDC_HEOIER_VDSCR		(0x1 << 19)
++#define LCDC_HEOIER_VADD		(0x1 << 20)
++#define LCDC_HEOIER_VDONE		(0x1 << 21)
++#define LCDC_HEOIER_VOVR		(0x1 << 22)
++
++#define ATMEL_LCDC_HEOIDR	0x0290
++#define LCDC_HEOIDR_DMA			(0x1 << 2)
++#define LCDC_HEOIDR_DSCR		(0x1 << 3)
++#define LCDC_HEOIDR_ADD			(0x1 << 4)
++#define LCDC_HEOIDR_DONE		(0x1 << 5)
++#define LCDC_HEOIDR_OVR			(0x1 << 6)
++#define LCDC_HEOIDR_UDMA		(0x1 << 10)
++#define LCDC_HEOIDR_UDSCR		(0x1 << 11)
++#define LCDC_HEOIDR_UADD		(0x1 << 12)
++#define LCDC_HEOIDR_UDONE		(0x1 << 13)
++#define LCDC_HEOIDR_UOVR		(0x1 << 14)
++#define LCDC_HEOIDR_VDMA		(0x1 << 18)
++#define LCDC_HEOIDR_VDSCR		(0x1 << 19)
++#define LCDC_HEOIDR_VADD		(0x1 << 20)
++#define LCDC_HEOIDR_VDONE		(0x1 << 21)
++#define LCDC_HEOIDR_VOVR		(0x1 << 22)
++
++#define ATMEL_LCDC_HEOIMR	0x0294
++#define LCDC_HEOIMR_DMA			(0x1 << 2)
++#define LCDC_HEOIMR_DSCR		(0x1 << 3)
++#define LCDC_HEOIMR_ADD			(0x1 << 4)
++#define LCDC_HEOIMR_DONE		(0x1 << 5)
++#define LCDC_HEOIMR_OVR			(0x1 << 6)
++#define LCDC_HEOIMR_UDMA		(0x1 << 10)
++#define LCDC_HEOIMR_UDSCR		(0x1 << 11)
++#define LCDC_HEOIMR_UADD		(0x1 << 12)
++#define LCDC_HEOIMR_UDONE		(0x1 << 13)
++#define LCDC_HEOIMR_UOVR		(0x1 << 14)
++#define LCDC_HEOIMR_VDMA		(0x1 << 18)
++#define LCDC_HEOIMR_VDSCR		(0x1 << 19)
++#define LCDC_HEOIMR_VADD		(0x1 << 20)
++#define LCDC_HEOIMR_VDONE		(0x1 << 21)
++#define LCDC_HEOIMR_VOVR		(0x1 << 22)
++
++#define ATMEL_LCDC_HEOISR	0x0298
++#define LCDC_HEOISR_DMA			(0x1 << 2)
++#define LCDC_HEOISR_DSCR		(0x1 << 3)
++#define LCDC_HEOISR_ADD			(0x1 << 4)
++#define LCDC_HEOISR_DONE		(0x1 << 5)
++#define LCDC_HEOISR_OVR			(0x1 << 6)
++#define LCDC_HEOISR_UDMA		(0x1 << 10)
++#define LCDC_HEOISR_UDSCR		(0x1 << 11)
++#define LCDC_HEOISR_UADD		(0x1 << 12)
++#define LCDC_HEOISR_UDONE		(0x1 << 13)
++#define LCDC_HEOISR_UOVR		(0x1 << 14)
++#define LCDC_HEOISR_VDMA		(0x1 << 18)
++#define LCDC_HEOISR_VDSCR		(0x1 << 19)
++#define LCDC_HEOISR_VADD		(0x1 << 20)
++#define LCDC_HEOISR_VDONE		(0x1 << 21)
++#define LCDC_HEOISR_VOVR		(0x1 << 22)
++
++#define ATMEL_LCDC_HEOHEAD	0x029C
++
++#define ATMEL_LCDC_HEOADDR	0x02A0
++
++#define ATMEL_LCDC_HEOCTRL	0x02A4
++#define LCDC_HEOCTRL_DFETCH		(0x1 << 0)
++#define LCDC_HEOCTRL_LFETCH		(0x1 << 1)
++#define LCDC_HEOCTRL_DMAIEN		(0x1 << 2)
++#define LCDC_HEOCTRL_DSCRIEN		(0x1 << 3)
++#define LCDC_HEOCTRL_ADDIEN		(0x1 << 4)
++#define LCDC_HEOCTRL_DONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_HEONEXT	0x02A8
++
++#define ATMEL_LCDC_HEOUHEAD	0x02AC
++
++#define ATMEL_LCDC_HEOUADDR	0x02B0
++
++#define ATMEL_LCDC_HEOUCTRL	0x02B4
++#define LCDC_HEOUCTRL_UDFETCH		(0x1 << 0)
++#define LCDC_HEOUCTRL_UDMAIEN		(0x1 << 2)
++#define LCDC_HEOUCTRL_UDSCRIEN		(0x1 << 3)
++#define LCDC_HEOUCTRL_UADDIEN		(0x1 << 4)
++#define LCDC_HEOUCTRL_UDONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_HEOUNEXT	0x02B8
++
++#define ATMEL_LCDC_HEOVHEAD	0x02BC
++
++#define ATMEL_LCDC_HEOVADDR	0x02C0
++
++#define ATMEL_LCDC_HEOVCTRL	0x02C4
++#define LCDC_HEOVCTRL_VDFETCH		(0x1 << 0)
++#define LCDC_HEOVCTRL_VDMAIEN		(0x1 << 2)
++#define LCDC_HEOVCTRL_VDSCRIEN		(0x1 << 3)
++#define LCDC_HEOVCTRL_VADDIEN		(0x1 << 4)
++#define LCDC_HEOVCTRL_VDONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_HEOVNEXT	0x02C8
++
++#define ATMEL_LCDC_HEOCFG0	0x02CC
++#define LCDC_HEOCFG0_BLEN_OFFSET	4
++#define LCDC_HEOCFG0_BLEN		(0x3 << LCDC_HEOCFG0_BLEN_OFFSET)
++#define		LCDC_HEOCFG0_BLEN_AHB_SINGLE		(0x0 << 4)
++#define		LCDC_HEOCFG0_BLEN_AHB_INCR4		(0x1 << 4)
++#define		LCDC_HEOCFG0_BLEN_AHB_INCR8		(0x2 << 4)
++#define		LCDC_HEOCFG0_BLEN_AHB_INCR16		(0x3 << 4)
++#define LCDC_HEOCFG0_BLENUV_OFFSET	6
++#define LCDC_HEOCFG0_BLENUV		(0x3 << LCDC_HEOCFG0_BLENUV_OFFSET)
++#define		LCDC_HEOCFG0_BLENUV_AHB_SINGLE		(0x0 << 6)
++#define		LCDC_HEOCFG0_BLENUV_AHB_INCR4		(0x1 << 6)
++#define		LCDC_HEOCFG0_BLENUV_AHB_INCR8		(0x2 << 6)
++#define		LCDC_HEOCFG0_BLENUV_AHB_INCR16		(0x3 << 6)
++#define LCDC_HEOCFG0_DLBO		(0x1 << 8)
++#define LCDC_HEOCFG0_ROTDIS		(0x1 << 12)
++#define LCDC_HEOCFG0_LOCKDIS		(0x1 << 13)
++
++#define ATMEL_LCDC_HEOCFG1	0x02D0
++#define LCDC_HEOCFG1_CLUTEN		(0x1 << 0)
++#define LCDC_HEOCFG1_YUVEN		(0x1 << 1)
++#define LCDC_HEOCFG1_RGBMODE_OFFSET	4
++#define LCDC_HEOCFG1_RGBMODE		(0xf << LCDC_HEOCFG1_RGBMODE_OFFSET)
++#define		LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
++#define		LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
++#define		LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
++#define		LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
++#define LCDC_HEOCFG1_CLUTMODE_OFFSET	8
++#define LCDC_HEOCFG1_CLUTMODE		(0x3 << LCDC_HEOCFG1_CLUTMODE_OFFSET)
++#define		LCDC_HEOCFG1_CLUTMODE_1BPP		(0x0 << 8)
++#define		LCDC_HEOCFG1_CLUTMODE_2BPP		(0x1 << 8)
++#define		LCDC_HEOCFG1_CLUTMODE_4BPP		(0x2 << 8)
++#define		LCDC_HEOCFG1_CLUTMODE_8BPP		(0x3 << 8)
++#define LCDC_HEOCFG1_YUVMODE_OFFSET	12
++#define LCDC_HEOCFG1_YUVMODE		(0xf << LCDC_HEOCFG1_YUVMODE_OFFSET)
++#define		LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR	(0x0 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0	(0x1 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1	(0x2 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2	(0x3 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3	(0x4 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR	(0x5 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR	(0x6 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR	(0x7 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR	(0x8 << 12)
++#define LCDC_HEOCFG1_YUV422ROT		(0x1 << 16)
++#define LCDC_HEOCFG1_YUV422SWP		(0x1 << 17)
++
++#define ATMEL_LCDC_HEOCFG2	0x02D4
++#define LCDC_HEOCFG2_XOFFSET_OFFSET	0
++#define LCDC_HEOCFG2_XOFFSET		(0x7ff << LCDC_HEOCFG2_XOFFSET_OFFSET)
++#define LCDC_HEOCFG2_YOFFSET_OFFSET	16
++#define LCDC_HEOCFG2_YOFFSET		(0x7ff << LCDC_HEOCFG2_YOFFSET_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG3	0x02D8
++#define LCDC_HEOCFG3_XSIZE_OFFSET	0
++#define LCDC_HEOCFG3_XSIZE		(0x7ff << LCDC_HEOCFG3_XSIZE_OFFSET)
++#define LCDC_HEOCFG3_YSIZE_OFFSET	16
++#define LCDC_HEOCFG3_YSIZE		(0x7ff << LCDC_HEOCFG3_YSIZE_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG4	0x02DC
++#define LCDC_HEOCFG4_XMEM_SIZE_OFFSET	0
++#define LCDC_HEOCFG4_XMEM_SIZE		(0x7ff << LCDC_HEOCFG4_XMEM_SIZE_OFFSET)
++#define LCDC_HEOCFG4_YMEM_SIZE_OFFSET	16
++#define LCDC_HEOCFG4_YMEM_SIZE		(0x7ff << LCDC_HEOCFG4_YMEM_SIZE_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG5	0x02E0
++
++#define ATMEL_LCDC_HEOCFG6	0x02E4
++
++#define ATMEL_LCDC_HEOCFG7	0x02E8
++
++#define ATMEL_LCDC_HEOCFG8	0x02EC
++
++#define ATMEL_LCDC_HEOCFG9	0x02F0
++#define LCDC_HEOCFG9_BDEF_OFFSET	0
++#define LCDC_HEOCFG9_BDEF		(0xff << LCDC_HEOCFG9_BDEF_OFFSET)
++#define LCDC_HEOCFG9_GDEF_OFFSET	8
++#define LCDC_HEOCFG9_GDEF		(0xff << LCDC_HEOCFG9_GDEF_OFFSET)
++#define LCDC_HEOCFG9_RDEF_OFFSET	16
++#define LCDC_HEOCFG9_RDEF		(0xff << LCDC_HEOCFG9_RDEF_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG10	0x02F4
++#define LCDC_HEOCFG10_BKEY_OFFSET	0
++#define LCDC_HEOCFG10_BKEY		(0xff << LCDC_HEOCFG10_BKEY_OFFSET)
++#define LCDC_HEOCFG10_GKEY_OFFSET	8
++#define LCDC_HEOCFG10_GKEY		(0xff << LCDC_HEOCFG10_GKEY_OFFSET)
++#define LCDC_HEOCFG10_RKEY_OFFSET	16
++#define LCDC_HEOCFG10_RKEY		(0xff << LCDC_HEOCFG10_RKEY_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG11	0x02F8
++#define LCDC_HEOCFG11_BMASK_OFFSET	0
++#define LCDC_HEOCFG11_BMASK		(0xff << LCDC_HEOCFG11_BMASK_OFFSET)
++#define LCDC_HEOCFG11_GMASK_OFFSET	8
++#define LCDC_HEOCFG11_GMASK		(0xff << LCDC_HEOCFG11_GMASK_OFFSET)
++#define LCDC_HEOCFG11_RMASK_OFFSET	16
++#define LCDC_HEOCFG11_RMASK		(0xff << LCDC_HEOCFG11_RMASK_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG12	0x02FC
++#define LCDC_HEOCFG12_CRKEY		(0x1 << 0)
++#define LCDC_HEOCFG12_INV		(0x1 << 1)
++#define LCDC_HEOCFG12_ITER2BL		(0x1 << 2)
++#define LCDC_HEOCFG12_ITER		(0x1 << 3)
++#define LCDC_HEOCFG12_REVALPHA		(0x1 << 4)
++#define LCDC_HEOCFG12_GAEN		(0x1 << 5)
++#define LCDC_HEOCFG12_LAEN		(0x1 << 6)
++#define LCDC_HEOCFG12_OVR		(0x1 << 7)
++#define LCDC_HEOCFG12_DMA		(0x1 << 8)
++#define LCDC_HEOCFG12_REP		(0x1 << 9)
++#define LCDC_HEOCFG12_DSTKEY		(0x1 << 10)
++#define LCDC_HEOCFG12_VIDPRI		(0x1 << 12)
++#define LCDC_HEOCFG12_GA_OFFSET		16
++#define LCDC_HEOCFG12_GA		(0xff << LCDC_HEOCFG12_GA_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG13	0x0300
++#define LCDC_HEOCFG13_XFACTOR_OFFSET	0
++#define LCDC_HEOCFG13_XFACTOR		(0x1fff << LCDC_HEOCFG13_XFACTOR_OFFSET)
++#define LCDC_HEOCFG13_YFACTOR_OFFSET	16
++#define LCDC_HEOCFG13_YFACTOR		(0x1fff << LCDC_HEOCFG13_YFACTOR_OFFSET)
++#define LCDC_HEOCFG13_SCALEN		(0x1 << 31)
++
++#define ATMEL_LCDC_HEOCFG14	0x0304
++#define LCDC_HEOCFG14_CSCRY_OFFSET	0
++#define LCDC_HEOCFG14_CSCRY		(0x3ff << LCDC_HEOCFG14_CSCRY_OFFSET)
++#define LCDC_HEOCFG14_CSCRU_OFFSET	10
++#define LCDC_HEOCFG14_CSCRU		(0x3ff << LCDC_HEOCFG14_CSCRU_OFFSET)
++#define LCDC_HEOCFG14_CSCRV_OFFSET	20
++#define LCDC_HEOCFG14_CSCRV		(0x3ff << LCDC_HEOCFG14_CSCRV_OFFSET)
++#define LCDC_HEOCFG14_CSCYOFF		(0x1 << 30)
++
++#define ATMEL_LCDC_HEOCFG15	0x0308
++#define LCDC_HEOCFG15_CSCGY_OFFSET	0
++#define LCDC_HEOCFG15_CSCGY		(0x3ff << LCDC_HEOCFG15_CSCGY_OFFSET)
++#define LCDC_HEOCFG15_CSCGU_OFFSET	10
++#define LCDC_HEOCFG15_CSCGU		(0x3ff << LCDC_HEOCFG15_CSCGU_OFFSET)
++#define LCDC_HEOCFG15_CSCGV_OFFSET	20
++#define LCDC_HEOCFG15_CSCGV		(0x3ff << LCDC_HEOCFG15_CSCGV_OFFSET)
++#define LCDC_HEOCFG15_CSCUOFF		(0x1 << 30)
++
++#define ATMEL_LCDC_HEOCFG16	0x030C
++#define LCDC_HEOCFG16_CSCBY_OFFSET	0
++#define LCDC_HEOCFG16_CSCBY		(0x3ff << LCDC_HEOCFG16_CSCBY_OFFSET)
++#define LCDC_HEOCFG16_CSCBU_OFFSET	10
++#define LCDC_HEOCFG16_CSCBU		(0x3ff << LCDC_HEOCFG16_CSCBU_OFFSET)
++#define LCDC_HEOCFG16_CSCBV_OFFSET	20
++#define LCDC_HEOCFG16_CSCBV		(0x3ff << LCDC_HEOCFG16_CSCBV_OFFSET)
++#define LCDC_HEOCFG16_CSCVOFF		(0x1 << 30)
++
++#define ATMEL_LCDC_HCRCHER	0x0340
++#define LCDC_HCRCHER_CHEN		(0x1 << 0)
++#define LCDC_HCRCHER_UPDATEEN		(0x1 << 1)
++#define LCDC_HCRCHER_A2QEN		(0x1 << 2)
++
++#define ATMEL_LCDC_HCRCHDR	0x0344
++#define LCDC_HCRCHDR_CHDIS		(0x1 << 0)
++#define LCDC_HCRCHDR_CHRST		(0x1 << 8)
++
++#define ATMEL_LCDC_HCRCHSR	0x0348
++#define LCDC_HCRCHSR_CHSR		(0x1 << 0)
++#define LCDC_HCRCHSR_UPDATESR		(0x1 << 1)
++#define LCDC_HCRCHSR_A2QSR		(0x1 << 2)
++
++#define ATMEL_LCDC_HCRIER	0x034C
++#define LCDC_HCRIER_DMA			(0x1 << 2)
++#define LCDC_HCRIER_DSCR		(0x1 << 3)
++#define LCDC_HCRIER_ADD			(0x1 << 4)
++#define LCDC_HCRIER_DONE		(0x1 << 5)
++#define LCDC_HCRIER_OVR			(0x1 << 6)
++
++#define ATMEL_LCDC_HCRIDR	0x0350
++#define LCDC_HCRIDR_DMA			(0x1 << 2)
++#define LCDC_HCRIDR_DSCR		(0x1 << 3)
++#define LCDC_HCRIDR_ADD			(0x1 << 4)
++#define LCDC_HCRIDR_DONE		(0x1 << 5)
++#define LCDC_HCRIDR_OVR			(0x1 << 6)
++
++#define ATMEL_LCDC_HCRIMR	0x0354
++#define LCDC_HCRIMR_DMA			(0x1 << 2)
++#define LCDC_HCRIMR_DSCR		(0x1 << 3)
++#define LCDC_HCRIMR_ADD			(0x1 << 4)
++#define LCDC_HCRIMR_DONE		(0x1 << 5)
++#define LCDC_HCRIMR_OVR			(0x1 << 6)
++
++#define ATMEL_LCDC_HCRISR	0x0358
++#define LCDC_HCRISR_DMA			(0x1 << 2)
++#define LCDC_HCRISR_DSCR		(0x1 << 3)
++#define LCDC_HCRISR_ADD			(0x1 << 4)
++#define LCDC_HCRISR_DONE		(0x1 << 5)
++#define LCDC_HCRISR_OVR			(0x1 << 6)
++
++#define ATMEL_LCDC_HCRHEAD	0x035C
++
++#define ATMEL_LCDC_HCRADDR	0x0360
++
++#define ATMEL_LCDC_HCRCTRL	0x0364
++#define LCDC_HCRCTRL_DFETCH		(0x1 << 0)
++#define LCDC_HCRCTRL_LFETCH		(0x1 << 1)
++#define LCDC_HCRCTRL_DMAIEN		(0x1 << 2)
++#define LCDC_HCRCTRL_DSCRIEN		(0x1 << 3)
++#define LCDC_HCRCTRL_ADDIEN		(0x1 << 4)
++#define LCDC_HCRCTRL_DONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_HCRNEXT	0x0368
++
++#define ATMEL_LCDC_HCRCFG0	0x036C
++#define LCDC_HCRCFG0_BLEN_OFFSET	4
++#define LCDC_HCRCFG0_BLEN		(0x3 << LCDC_HCRCFG0_BLEN_OFFSET)
++#define		LCDC_HCRCFG0_BLEN_AHB_SINGLE		(0x0 << 4)
++#define		LCDC_HCRCFG0_BLEN_AHB_INCR4		(0x1 << 4)
++#define		LCDC_HCRCFG0_BLEN_AHB_INCR8		(0x2 << 4)
++#define		LCDC_HCRCFG0_BLEN_AHB_INCR16		(0x3 << 4)
++#define LCDC_HCRCFG0_DLBO		(0x1 << 8)
++
++#define ATMEL_LCDC_HCRCFG1	0x0370
++#define LCDC_HCRCFG1_CLUTEN		(0x1 << 0)
++#define LCDC_HCRCFG1_RGBMODE_OFFSET	4
++#define LCDC_HCRCFG1_RGBMODE		(0xf << LCDC_HCRCFG1_RGBMODE_OFFSET)
++#define		LCDC_HCRCFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
++#define		LCDC_HCRCFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
++#define		LCDC_HCRCFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
++#define		LCDC_HCRCFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
++#define LCDC_HCRCFG1_CLUTMODE_OFFSET	8
++#define LCDC_HCRCFG1_CLUTMODE		(0x3 << LCDC_HCRCFG1_CLUTMODE_OFFSET)
++#define		LCDC_HCRCFG1_CLUTMODE_1BPP		(0x0 << 8)
++#define		LCDC_HCRCFG1_CLUTMODE_2BPP		(0x1 << 8)
++#define		LCDC_HCRCFG1_CLUTMODE_4BPP		(0x2 << 8)
++#define		LCDC_HCRCFG1_CLUTMODE_8BPP		(0x3 << 8)
++
++#define ATMEL_LCDC_HCRCFG2	0x0374
++#define LCDC_HCRCFG2_XOFFSET_OFFSET	0
++#define LCDC_HCRCFG2_XOFFSET		(0x7ff << LCDC_HCRCFG2_XOFFSET_OFFSET)
++#define LCDC_HCRCFG2_YOFFSET_OFFSET	16
++#define LCDC_HCRCFG2_YOFFSET		(0x7ff << LCDC_HCRCFG2_YOFFSET_OFFSET)
++
++#define ATMEL_LCDC_HCRCFG3	0x0378
++#define LCDC_HCRCFG3_XSIZE_OFFSET	0
++#define LCDC_HCRCFG3_XSIZE		(0x7f << LCDC_HCRCFG3_XSIZE_OFFSET)
++#define LCDC_HCRCFG3_YSIZE_OFFSET	16
++#define LCDC_HCRCFG3_YSIZE		(0x7f << LCDC_HCRCFG3_YSIZE_OFFSET)
++
++#define ATMEL_LCDC_HCRCFG4	0x037C
++
++#define ATMEL_LCDC_HCRCFG6	0x0384
++#define LCDC_HCRCFG6_BDEF_OFFSET	0
++#define LCDC_HCRCFG6_BDEF		(0xff << LCDC_HCRCFG6_BDEF_OFFSET)
++#define LCDC_HCRCFG6_GDEF_OFFSET	8
++#define LCDC_HCRCFG6_GDEF		(0xff << LCDC_HCRCFG6_GDEF_OFFSET)
++#define LCDC_HCRCFG6_RDEF_OFFSET	16
++#define LCDC_HCRCFG6_RDEF		(0xff << LCDC_HCRCFG6_RDEF_OFFSET)
++
++#define ATMEL_LCDC_HCRCFG7	0x0388
++#define LCDC_HCRCFG7_BKEY_OFFSET	0
++#define LCDC_HCRCFG7_BKEY		(0xff << LCDC_HCRCFG7_BKEY_OFFSET)
++#define LCDC_HCRCFG7_GKEY_OFFSET	8
++#define LCDC_HCRCFG7_GKEY		(0xff << LCDC_HCRCFG7_GKEY_OFFSET)
++#define LCDC_HCRCFG7_RKEY_OFFSET	16
++#define LCDC_HCRCFG7_RKEY		(0xff << LCDC_HCRCFG7_RKEY_OFFSET)
++
++#define ATMEL_LCDC_HCRCFG8	0x038C
++#define LCDC_HCRCFG8_BMASK_OFFSET	0
++#define LCDC_HCRCFG8_BMASK		(0xff << LCDC_HCRCFG8_BMASK_OFFSET)
++#define LCDC_HCRCFG8_GMASK_OFFSET	8
++#define LCDC_HCRCFG8_GMASK		(0xff << LCDC_HCRCFG8_GMASK_OFFSET)
++#define LCDC_HCRCFG8_RMASK_OFFSET	16
++#define LCDC_HCRCFG8_RMASK		(0xff << LCDC_HCRCFG8_RMASK_OFFSET)
++
++#define ATMEL_LCDC_HCRCFG9	0x0390
++#define LCDC_HCRCFG9_CRKEY		(0x1 << 0)
++#define LCDC_HCRCFG9_INV		(0x1 << 1)
++#define LCDC_HCRCFG9_ITER2BL		(0x1 << 2)
++#define LCDC_HCRCFG9_ITER		(0x1 << 3)
++#define LCDC_HCRCFG9_REVALPHA		(0x1 << 4)
++#define LCDC_HCRCFG9_GAEN		(0x1 << 5)
++#define LCDC_HCRCFG9_LAEN		(0x1 << 6)
++#define LCDC_HCRCFG9_OVR		(0x1 << 7)
++#define LCDC_HCRCFG9_DMA		(0x1 << 8)
++#define LCDC_HCRCFG9_REP		(0x1 << 9)
++#define LCDC_HCRCFG9_DSTKEY		(0x1 << 10)
++#define LCDC_HCRCFG9_GA_OFFSET		16
++#define LCDC_HCRCFG9_GA_Msk		(0xff << LCDC_HCRCFG9_GA_OFFSET)
++
++#define ATMEL_LCDC_BASECLUT	0x400
++#define LCDC_BASECLUT_BCLUT_OFFSET	0
++#define LCDC_BASECLUT_BCLUT		(0xff << LCDC_BASECLUT_BCLUT_OFFSET)
++#define LCDC_BASECLUT_GCLUT_OFFSET	8
++#define LCDC_BASECLUT_GCLUT		(0xff << LCDC_BASECLUT_GCLUT_OFFSET)
++#define LCDC_BASECLUT_RCLUT_OFFSET	16
++#define LCDC_BASECLUT_RCLUT		(0xff << LCDC_BASECLUT_RCLUT_OFFSET)
++
++#define ATMEL_LCDC_OVR1CLUT	0x800
++#define LCDC_OVR1CLUT_BCLUT_OFFSET	0
++#define LCDC_OVR1CLUT_BCLUT		(0xff << LCDC_OVR1CLUT_BCLUT_OFFSET)
++#define LCDC_OVR1CLUT_GCLUT_OFFSET	8
++#define LCDC_OVR1CLUT_GCLUT		(0xff << LCDC_OVR1CLUT_GCLUT_OFFSET)
++#define LCDC_OVR1CLUT_RCLUT_OFFSET	16
++#define LCDC_OVR1CLUT_RCLUT		(0xff << LCDC_OVR1CLUT_RCLUT_OFFSET)
++#define LCDC_OVR1CLUT_ACLUT_OFFSET	24
++#define LCDC_OVR1CLUT_ACLUT		(0xff << LCDC_OVR1CLUT_ACLUT_OFFSET)
++
++#define ATMEL_LCDC_HEOCLUT	0x1000
++#define LCDC_HEOCLUT_BCLUT_OFFSET	0
++#define LCDC_HEOCLUT_BCLUT		(0xff << LCDC_HEOCLUT_BCLUT_OFFSET)
++#define LCDC_HEOCLUT_GCLUT_OFFSET	8
++#define LCDC_HEOCLUT_GCLUT		(0xff << LCDC_HEOCLUT_GCLUT_OFFSET)
++#define LCDC_HEOCLUT_RCLUT_OFFSET	16
++#define LCDC_HEOCLUT_RCLUT		(0xff << LCDC_HEOCLUT_RCLUT_OFFSET)
++#define LCDC_HEOCLUT_ACLUT_OFFSET	24
++#define LCDC_HEOCLUT_ACLUT		(0xff << LCDC_HEOCLUT_ACLUT_OFFSET)
++
++#define ATMEL_LCDC_HCRCLUT	0x1400
++#define LCDC_HCRCLUT_BCLUT_OFFSET	0
++#define LCDC_HCRCLUT_BCLUT		(0xff << LCDC_HCRCLUT_BCLUT_OFFSET)
++#define LCDC_HCRCLUT_GCLUT_OFFSET	8
++#define LCDC_HCRCLUT_GCLUT		(0xff << LCDC_HCRCLUT_GCLUT_OFFSET)
++#define LCDC_HCRCLUT_RCLUT_OFFSET	16
++#define LCDC_HCRCLUT_RCLUT		(0xff << LCDC_HCRCLUT_RCLUT_OFFSET)
++#define LCDC_HCRCLUT_ACLUT_OFFSET	24
++#define LCDC_HCRCLUT_ACLUT		(0xff << LCDC_HCRCLUT_ACLUT_OFFSET)
++
++/* Base layer CLUT */
++#define ATMEL_LCDC_LUT(n)	(0x0400 + ((n)*4))
++
++
++#endif /* __ATMEL_HLCDC4_H__ */
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index 4484c72..fa9431b 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -1,7 +1,7 @@
+ /*
+  *  Driver for AT91/AT32 LCD Controller
+  *
+- *  Copyright (C) 2007 Atmel Corporation
++ *  Copyright (C) 2007-2010 Atmel Corporation
+  *
+  * This file is subject to the terms and conditions of the GNU General Public
+  * License.  See the file COPYING in the main directory of this archive for
+@@ -24,6 +24,7 @@
+ #include <mach/gpio.h>
+ 
+ #include <video/atmel_lcdc.h>
++#include <mach/atmel_hlcdfb.h>
+ 
+ #define lcdc_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
+ #define lcdc_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
+@@ -72,6 +73,9 @@ static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
+ 		| ATMEL_LCDC_POL_POSITIVE
+ 		| ATMEL_LCDC_ENA_PWMENABLE;
+ 
++static const u32 contrast_pwm_ctr = LCDC_LCDCFG6_PWMPOL
++		| (ATMEL_LCDC_CVAL_DEFAULT << LCDC_LCDCFG6_PWMCVAL_OFFSET);
++
+ #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
+ 
+ /* some bl->props field just changed */
+@@ -80,6 +84,7 @@ static int atmel_bl_update_status(struct backlight_device *bl)
+ 	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
+ 	int			power = sinfo->bl_power;
+ 	int			brightness = bl->props.brightness;
++	u32			reg;
+ 
+ 	/* REVISIT there may be a meaningful difference between
+ 	 * fb_blank and power ... there seem to be some cases
+@@ -90,14 +95,25 @@ static int atmel_bl_update_status(struct backlight_device *bl)
+ 	else if (bl->props.power != sinfo->bl_power)
+ 		power = bl->props.power;
+ 
+-	if (brightness < 0 && power == FB_BLANK_UNBLANK)
+-		brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
+-	else if (power != FB_BLANK_UNBLANK)
++	if (brightness < 0 && power == FB_BLANK_UNBLANK) {
++		if (cpu_is_at91sam9x5())
++			brightness = lcdc_readl(sinfo, ATMEL_LCDC_LCDCFG6)
++				     >> LCDC_LCDCFG6_PWMCVAL_OFFSET;
++		else
++			brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
++	} else if (power != FB_BLANK_UNBLANK) {
+ 		brightness = 0;
++	}
+ 
+-	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
+-	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
+-			brightness ? contrast_ctr : 0);
++	if (cpu_is_at91sam9x5()) {
++		reg = lcdc_readl(sinfo, ATMEL_LCDC_LCDCFG6) & ~LCDC_LCDCFG6_PWMCVAL;
++		reg |= brightness << LCDC_LCDCFG6_PWMCVAL_OFFSET;
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG6, reg);
++	} else {
++		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
++		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
++				brightness ? contrast_ctr : 0);
++	}
+ 
+ 	bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
+ 
+@@ -108,7 +124,10 @@ static int atmel_bl_get_brightness(struct backlight_device *bl)
+ {
+ 	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
+ 
+-	return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
++	if (cpu_is_at91sam9x5())
++		return lcdc_readl(sinfo, ATMEL_LCDC_LCDCFG6) >> LCDC_LCDCFG6_PWMCVAL_OFFSET;
++	else
++		return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
+ }
+ 
+ static const struct backlight_ops atmel_lcdc_bl_ops = {
+@@ -164,14 +183,17 @@ static void exit_backlight(struct atmel_lcdfb_info *sinfo)
+ 
+ static void init_contrast(struct atmel_lcdfb_info *sinfo)
+ {
+-	/* contrast pwm can be 'inverted' */
+-	if (sinfo->lcdcon_pol_negative)
+-			contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
+-
+-	/* have some default contrast/backlight settings */
+-	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
+-	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
+-
++	if (cpu_is_at91sam9x5()) {
++		/* have some default contrast/backlight settings */
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG6, contrast_pwm_ctr);
++	} else {
++		/* contrast pwm can be 'inverted' */
++		if (sinfo->lcdcon_pol_negative)
++				contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
++		/* have some default contrast/backlight settings */
++		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
++		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
++	}
+ 	if (sinfo->lcdcon_is_backlight)
+ 		init_backlight(sinfo);
+ }
+@@ -213,32 +235,78 @@ static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
+ 
+ static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
+ {
+-	/* Turn off the LCD controller and the DMA controller */
+-	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
+-			sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
++	if (cpu_is_at91sam9x5()) {
++		/* Disable DISP signal */
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_DISPDIS);
++		while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_DISPSTS))
++			msleep(1);
++		/* Disable synchronization */
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_SYNCDIS);
++		while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_LCDSTS))
++			msleep(1);
++		/* Disable pixel clock */
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_CLKDIS);
++		while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_CLKSTS))
++			msleep(1);
++		/* Disable PWM */
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_PWMDIS);
++		while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_PWMSTS))
++			msleep(1);
++	} else {
++		/* Turn off the LCD controller and the DMA controller */
++		lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
++				sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
+ 
+-	/* Wait for the LCDC core to become idle */
+-	while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
+-		msleep(10);
++		/* Wait for the LCDC core to become idle */
++		while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
++			msleep(10);
+ 
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
++		lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
++	}
+ }
+ 
+ static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
+ {
+ 	atmel_lcdfb_stop_nowait(sinfo);
+ 
+-	/* Wait for DMA engine to become idle... */
+-	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
+-		msleep(10);
++	if (cpu_is_at91sam9x5()) {
++		/* Wait for the end of DMA transfer */
++		while (!(lcdc_readl(sinfo, ATMEL_LCDC_BASEISR) & LCDC_BASEISR_DMA))
++			msleep(10);
++	} else {
++		/* Wait for DMA engine to become idle... */
++		while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
++			msleep(10);
++	}
+ }
+ 
+ static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
+ {
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
+-	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
+-		(sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
+-		| ATMEL_LCDC_PWR);
++	u32	value;
++
++	if (cpu_is_at91sam9x5()) {
++		value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_CLKEN);
++		while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_CLKSTS))
++			msleep(1);
++		value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_SYNCEN);
++		while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_LCDSTS))
++			msleep(1);
++		value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_DISPEN);
++		while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_DISPSTS))
++			msleep(1);
++		value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_PWMEN);
++		while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_PWMSTS))
++			msleep(1);
++	} else {
++		lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
++		lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
++			(sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
++			| ATMEL_LCDC_PWR);
++	}
+ }
+ 
+ static void atmel_lcdfb_update_dma(struct fb_info *info,
+@@ -247,14 +315,31 @@ static void atmel_lcdfb_update_dma(struct fb_info *info,
+ 	struct atmel_lcdfb_info *sinfo = info->par;
+ 	struct fb_fix_screeninfo *fix = &info->fix;
+ 	unsigned long dma_addr;
++	struct lcd_dma_desc *desc;
+ 
+ 	dma_addr = (fix->smem_start + var->yoffset * fix->line_length
+ 		    + var->xoffset * var->bits_per_pixel / 8);
+ 
+ 	dma_addr &= ~3UL;
+ 
+-	/* Set framebuffer DMA base address and pixel offset */
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
++	if (cpu_is_at91sam9x5()) {
++		/* Setup the DMA descriptor, this descriptor will loop to itself */
++		desc = (struct lcd_dma_desc *)sinfo->p_dma_desc;
++
++		desc->address = dma_addr;
++		/* Disable DMA transfer interrupt & descriptor loaded interrupt. */
++		desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
++				| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
++		desc->next = sinfo->dma_desc_phys;
++
++		lcdc_writel(sinfo, ATMEL_LCDC_BASEADDR, dma_addr);
++		lcdc_writel(sinfo, ATMEL_LCDC_BASECTRL, desc->control);
++		lcdc_writel(sinfo, ATMEL_LCDC_BASENEXT, sinfo->dma_desc_phys);
++		lcdc_writel(sinfo, ATMEL_LCDC_BASECHER, LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN);
++	} else {
++		/* Set framebuffer DMA base address and pixel offset */
++		lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
++	}
+ 
+ 	atmel_lcdfb_update_dma2d(sinfo, var);
+ }
+@@ -265,12 +350,18 @@ static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
+ 
+ 	dma_free_writecombine(info->device, info->fix.smem_len,
+ 				info->screen_base, info->fix.smem_start);
++
++	if (cpu_is_at91sam9x5()) {
++		if (sinfo->p_dma_desc)
++			dma_free_writecombine(info->device, sizeof(struct lcd_dma_desc),
++						sinfo->p_dma_desc, sinfo->dma_desc_phys);
++	}
+ }
+ 
+ /**
+  *	atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
+  *	@sinfo: the frame buffer to allocate memory for
+- * 	
++ *
+  * 	This function is called only from the atmel_lcdfb_probe()
+  * 	so no locking by fb_info->mm_lock around smem_len setting is needed.
+  */
+@@ -293,6 +384,19 @@ static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
+ 
+ 	memset(info->screen_base, 0, info->fix.smem_len);
+ 
++	if (cpu_is_at91sam9x5()) {
++		sinfo->p_dma_desc = dma_alloc_writecombine(info->device,
++						sizeof(struct lcd_dma_desc),
++						(dma_addr_t *)&(sinfo->dma_desc_phys),
++						GFP_KERNEL);
++
++		if (!sinfo->p_dma_desc) {
++			dma_free_writecombine(info->device, info->fix.smem_len,
++						info->screen_base, info->fix.smem_start);
++			return -ENOMEM;
++		}
++	}
++
+ 	return 0;
+ }
+ 
+@@ -386,18 +490,33 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
+ 	}
+ 
+ 	/* Saturate vertical and horizontal timings at maximum values */
+-	var->vsync_len = min_t(u32, var->vsync_len,
+-			(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
+-	var->upper_margin = min_t(u32, var->upper_margin,
+-			ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
+-	var->lower_margin = min_t(u32, var->lower_margin,
+-			ATMEL_LCDC_VFP);
+-	var->right_margin = min_t(u32, var->right_margin,
+-			(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
+-	var->hsync_len = min_t(u32, var->hsync_len,
+-			(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
+-	var->left_margin = min_t(u32, var->left_margin,
+-			ATMEL_LCDC_HBP + 1);
++	if (cpu_is_at91sam9x5()) {
++		var->vsync_len = min_t(u32, var->vsync_len,
++				(LCDC_LCDCFG1_VSPW >> LCDC_LCDCFG1_VSPW_OFFSET) + 1);
++		var->upper_margin = min_t(u32, var->upper_margin,
++				(LCDC_LCDCFG2_VFPW >> LCDC_LCDCFG2_VFPW_OFFSET) + 1);
++		var->lower_margin = min_t(u32, var->lower_margin,
++				LCDC_LCDCFG2_VBPW >> LCDC_LCDCFG2_VBPW_OFFSET);
++		var->right_margin = min_t(u32, var->right_margin,
++				(LCDC_LCDCFG3_HBPW >> LCDC_LCDCFG3_HBPW_OFFSET) + 1);
++		var->hsync_len = min_t(u32, var->hsync_len,
++				(LCDC_LCDCFG1_HSPW >> LCDC_LCDCFG1_HSPW_OFFSET) + 1);
++		var->left_margin = min_t(u32, var->left_margin,
++				(LCDC_LCDCFG3_HFPW >> LCDC_LCDCFG3_HFPW_OFFSET) + 1);
++	} else {
++		var->vsync_len = min_t(u32, var->vsync_len,
++				(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
++		var->upper_margin = min_t(u32, var->upper_margin,
++				ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
++		var->lower_margin = min_t(u32, var->lower_margin,
++				ATMEL_LCDC_VFP);
++		var->right_margin = min_t(u32, var->right_margin,
++				(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
++		var->hsync_len = min_t(u32, var->hsync_len,
++				(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
++		var->left_margin = min_t(u32, var->left_margin,
++				ATMEL_LCDC_HBP + 1);
++	}
+ 
+ 	/* Some parameters can't be zero */
+ 	var->vsync_len = max_t(u32, var->vsync_len, 1);
+@@ -412,10 +531,53 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
+ 	case 8:
+ 		var->red.offset = var->green.offset = var->blue.offset = 0;
+ 		var->red.length = var->green.length = var->blue.length
+-			= var->bits_per_pixel;
++				= var->bits_per_pixel;
++		break;
++	case 12:
++		if (cpu_is_at91sam9x5()) {
++			/* RGB:444 mode */
++			var->red.offset = 8;
++			var->blue.offset = 0;
++			var->green.offset = 4;
++			var->red.length = var->green.length = var->blue.length = 4;
++		} else {
++			/*TODO: rework*/
++			BUG();
++		}
+ 		break;
+ 	case 15:
++		if (cpu_is_at91sam9x5()) {
++			/* RGB:555 mode */
++			var->red.offset = 10;
++			var->blue.offset = 0;
++			var->green.length = 5;
++			var->red.length = var->green.length = var->blue.length = 5;
++		} else {
++			/*TODO: rework*/
++			BUG();
++		}
++		break;
+ 	case 16:
++		if (cpu_is_at91sam9x5()) {
++			if (sinfo->alpha_enabled) {
++				/* ARGB:4444 mode */
++				var->red.offset = 8;
++				var->blue.offset = 0;
++				var->green.offset = 4;
++				var->transp.offset = 12;
++				var->red.length = var->green.length
++						= var->blue.length
++						= var->transp.length = 4;
++			} else {
++				/* RGB:565 mode */
++				var->red.offset = 11;
++				var->blue.offset = 0;
++				var->green.offset = 5;
++				var->green.length = 6;
++				var->red.length = var->blue.length = 5;
++			}
++			break;
++		}
+ 		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
+ 			/* RGB:565 mode */
+ 			var->red.offset = 11;
+@@ -435,6 +597,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
+ 		var->red.length = var->blue.length = 5;
+ 		break;
+ 	case 32:
++		/* TODO 32 & 24 modes */
+ 		var->transp.offset = 24;
+ 		var->transp.length = 8;
+ 		/* fall through */
+@@ -471,6 +634,252 @@ static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
+ 	atmel_lcdfb_start(sinfo);
+ }
+ 
++static int atmel_lcdfb_setup_9x5_core(struct fb_info *info)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++	unsigned long value;
++	unsigned long clk_value_khz;
++
++	dev_dbg(info->device, "%s:\n", __func__);
++	/* Set pixel clock */
++	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
++
++	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
++
++	if (value < 1) {
++		dev_notice(info->device, "using system clock as pixel clock\n");
++		value = LCDC_LCDCFG0_CLKPOL | LCDC_LCDCFG0_CLKPWMSEL | LCDC_LCDCFG0_CGDISBASE;
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG0, value);
++	} else {
++		info->var.pixclock = KHZ2PICOS(clk_value_khz / value);
++		dev_dbg(info->device, "  updated pixclk:     %lu KHz\n",
++				PICOS2KHZ(info->var.pixclock));
++		value = value - 2;
++		dev_dbg(info->device, "  * programming CLKDIV = 0x%08lx\n",
++					value);
++		value = (value << LCDC_LCDCFG0_CLKDIV_OFFSET)
++			| LCDC_LCDCFG0_CLKPOL
++			| LCDC_LCDCFG0_CGDISBASE;
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG0, value);
++	}
++
++	/* Initialize control register 5 */
++	value = (sinfo->guard_time << LCDC_LCDCFG5_GUARDTIME_OFFSET)
++		| LCDC_LCDCFG5_DISPDLY
++		| LCDC_LCDCFG5_VSPDLYS;
++
++	if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
++		value |= LCDC_LCDCFG5_HSPOL;
++	if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
++		value |= LCDC_LCDCFG5_VSPOL;
++
++	switch (info->var.bits_per_pixel) {
++	case 12:
++		value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
++		break;
++	case 16:
++		if (info->var.transp.offset != 0)
++			value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
++		else
++			value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
++		break;
++	case 18:
++		value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
++		break;
++	case 24:
++	case 32:
++		value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
++		break;
++	default:
++		BUG();
++		break;
++	}
++	dev_dbg(info->device, "  * LCDC_LCDCFG5 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG5, value);
++
++	/* Vertical & Horizontal Timing */
++	value = (info->var.vsync_len - 1) << LCDC_LCDCFG1_VSPW_OFFSET;
++	value |= (info->var.hsync_len - 1) << LCDC_LCDCFG1_HSPW_OFFSET;
++	dev_dbg(info->device, "  * LCDC_LCDCFG1 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG1, value);
++
++	value = (info->var.lower_margin) << LCDC_LCDCFG2_VBPW_OFFSET;
++	value |= (info->var.upper_margin - 1) << LCDC_LCDCFG2_VFPW_OFFSET;
++	dev_dbg(info->device, "  * LCDC_LCDCFG2 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG2, value);
++
++	value = (info->var.right_margin - 1) << LCDC_LCDCFG3_HBPW_OFFSET;
++	value |= (info->var.left_margin - 1) << LCDC_LCDCFG3_HFPW_OFFSET;
++	dev_dbg(info->device, "  * LCDC_LCDCFG3 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG3, value);
++
++	/* Display size */
++	value = (info->var.yres - 1) << LCDC_LCDCFG4_RPF_OFFSET;
++	value |= (info->var.xres - 1) << LCDC_LCDCFG4_PPL_OFFSET;
++	dev_dbg(info->device, "  * LCDC_LCDCFG4 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG4, value);
++
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG0, LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
++	switch (info->var.bits_per_pixel) {
++	case 12:
++		value = LCDC_BASECFG1_RGBMODE_12BPP_RGB_444;
++		break;
++	case 16:
++		if (info->var.transp.offset != 0)
++			value = LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444;
++		else
++			value = LCDC_BASECFG1_RGBMODE_16BPP_RGB_565;
++		break;
++	case 18:
++		value = LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED;
++		break;
++	case 24:
++		value = LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED;
++		break;
++	case 32:
++		value = LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888;
++		break;
++	default:
++		BUG();
++		break;
++	}
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG1, value);
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG2, 0);
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG3, 0);	/* Default color */
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG4, LCDC_BASECFG4_DMA);
++
++	/* Disable all interrupts */
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDIDR, ~0UL);
++	lcdc_writel(sinfo, ATMEL_LCDC_BASEIDR, ~0UL);
++	/* Enable BASE LAYER overflow interrupts, if want to enable DMA interrupt, also need set it at LCDC_BASECTRL reg */
++	lcdc_writel(sinfo, ATMEL_LCDC_BASEIER, LCDC_BASEIER_OVR);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDIER, LCDC_LCDIER_FIFOERRIE | LCDC_LCDIER_BASEIE);
++
++	return 0;
++}
++
++static int atmel_lcdfb_setup_core(struct fb_info *info)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++	unsigned long hozval_linesz;
++	unsigned long value;
++	unsigned long clk_value_khz;
++	unsigned long pix_factor = 2;
++
++	if (cpu_is_at91sam9x5()) {
++		return atmel_lcdfb_setup_9x5_core(info);
++	} else {
++		/* ...set frame size and burst length = 8 words (?) */
++		value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
++		value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
++		lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
++
++		/* Set pixel clock */
++		if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
++			pix_factor = 1;
++
++		clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
++
++		value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
++
++		if (value < pix_factor) {
++			dev_notice(info->device, "Bypassing pixel clock divider\n");
++			lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
++		} else {
++			value = (value / pix_factor) - 1;
++			dev_dbg(info->device, "  * programming CLKVAL = 0x%08lx\n",
++					value);
++			lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
++					value << ATMEL_LCDC_CLKVAL_OFFSET);
++			info->var.pixclock =
++				KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
++			dev_dbg(info->device, "  updated pixclk:     %lu KHz\n",
++						PICOS2KHZ(info->var.pixclock));
++		}
++
++
++		/* Initialize control register 2 */
++		value = sinfo->default_lcdcon2;
++
++		if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
++			value |= ATMEL_LCDC_INVLINE_INVERTED;
++		if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
++			value |= ATMEL_LCDC_INVFRAME_INVERTED;
++
++		switch (info->var.bits_per_pixel) {
++		case 1:
++			value |= ATMEL_LCDC_PIXELSIZE_1;
++			break;
++		case 2:
++			value |= ATMEL_LCDC_PIXELSIZE_2;
++			break;
++		case 4:
++			value |= ATMEL_LCDC_PIXELSIZE_4;
++			break;
++		case 8:
++			value |= ATMEL_LCDC_PIXELSIZE_8;
++			break;
++		case 15: /* fall through */
++		case 16:
++			value |= ATMEL_LCDC_PIXELSIZE_16;
++			break;
++		case 24:
++			value |= ATMEL_LCDC_PIXELSIZE_24;
++			break;
++		case 32:
++			value |= ATMEL_LCDC_PIXELSIZE_32;
++			break;
++		default:
++			BUG();
++			break;
++		}
++		dev_dbg(info->device, "  * LCDCON2 = %08lx\n", value);
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
++
++		/* Vertical timing */
++		value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
++		value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
++		value |= info->var.lower_margin;
++		dev_dbg(info->device, "  * LCDTIM1 = %08lx\n", value);
++		lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
++
++		/* Horizontal timing */
++		value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
++		value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
++		value |= (info->var.left_margin - 1);
++		dev_dbg(info->device, "  * LCDTIM2 = %08lx\n", value);
++		lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
++
++		/* Horizontal value (aka line size) */
++		hozval_linesz = compute_hozval(info->var.xres,
++					lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
++
++		/* Display size */
++		value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
++		value |= info->var.yres - 1;
++		dev_dbg(info->device, "  * LCDFRMCFG = %08lx\n", value);
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
++
++		/* FIFO Threshold: Use formula from data sheet */
++		value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
++		lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
++
++		/* Toggle LCD_MODE every frame */
++		lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
++
++		/* Disable all interrupts */
++		lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
++		/* Enable FIFO & DMA errors */
++		lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
++
++		/* ...wait for DMA engine to become idle... */
++		while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
++			msleep(10);
++
++		return 0;
++	}
++}
++
+ /**
+  *      atmel_lcdfb_set_par - Alters the hardware state.
+  *      @info: frame buffer structure that represents a single frame buffer
+@@ -488,11 +897,7 @@ static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
+ static int atmel_lcdfb_set_par(struct fb_info *info)
+ {
+ 	struct atmel_lcdfb_info *sinfo = info->par;
+-	unsigned long hozval_linesz;
+-	unsigned long value;
+-	unsigned long clk_value_khz;
+ 	unsigned long bits_per_line;
+-	unsigned long pix_factor = 2;
+ 
+ 	might_sleep();
+ 
+@@ -517,98 +922,8 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
+ 	dev_dbg(info->device, "  * update DMA engine\n");
+ 	atmel_lcdfb_update_dma(info, &info->var);
+ 
+-	/* ...set frame size and burst length = 8 words (?) */
+-	value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
+-	value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
+-
+ 	/* Now, the LCDC core... */
+-
+-	/* Set pixel clock */
+-	if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
+-		pix_factor = 1;
+-
+-	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+-
+-	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
+-
+-	if (value < pix_factor) {
+-		dev_notice(info->device, "Bypassing pixel clock divider\n");
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
+-	} else {
+-		value = (value / pix_factor) - 1;
+-		dev_dbg(info->device, "  * programming CLKVAL = 0x%08lx\n",
+-				value);
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
+-				value << ATMEL_LCDC_CLKVAL_OFFSET);
+-		info->var.pixclock =
+-			KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
+-		dev_dbg(info->device, "  updated pixclk:     %lu KHz\n",
+-					PICOS2KHZ(info->var.pixclock));
+-	}
+-
+-
+-	/* Initialize control register 2 */
+-	value = sinfo->default_lcdcon2;
+-
+-	if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
+-		value |= ATMEL_LCDC_INVLINE_INVERTED;
+-	if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
+-		value |= ATMEL_LCDC_INVFRAME_INVERTED;
+-
+-	switch (info->var.bits_per_pixel) {
+-		case 1:	value |= ATMEL_LCDC_PIXELSIZE_1; break;
+-		case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
+-		case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
+-		case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
+-		case 15: /* fall through */
+-		case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
+-		case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
+-		case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
+-		default: BUG(); break;
+-	}
+-	dev_dbg(info->device, "  * LCDCON2 = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
+-
+-	/* Vertical timing */
+-	value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
+-	value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
+-	value |= info->var.lower_margin;
+-	dev_dbg(info->device, "  * LCDTIM1 = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
+-
+-	/* Horizontal timing */
+-	value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
+-	value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
+-	value |= (info->var.left_margin - 1);
+-	dev_dbg(info->device, "  * LCDTIM2 = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
+-
+-	/* Horizontal value (aka line size) */
+-	hozval_linesz = compute_hozval(info->var.xres,
+-					lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
+-
+-	/* Display size */
+-	value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
+-	value |= info->var.yres - 1;
+-	dev_dbg(info->device, "  * LCDFRMCFG = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
+-
+-	/* FIFO Threshold: Use formula from data sheet */
+-	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
+-	lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
+-
+-	/* Toggle LCD_MODE every frame */
+-	lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
+-
+-	/* Disable all interrupts */
+-	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
+-	/* Enable FIFO & DMA errors */
+-	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
+-
+-	/* ...wait for DMA engine to become idle... */
+-	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
+-		msleep(10);
++	atmel_lcdfb_setup_core(info);
+ 
+ 	atmel_lcdfb_start(sinfo);
+ 
+@@ -755,14 +1070,32 @@ static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
+ 	struct fb_info *info = dev_id;
+ 	struct atmel_lcdfb_info *sinfo = info->par;
+ 	u32 status;
++	u32 baselayer_status;
++
++	if (cpu_is_at91sam9x5()) {
++		/* Check for error status via interrupt.*/
++		status = lcdc_readl(sinfo, ATMEL_LCDC_LCDISR);
++		if (status & LCDC_LCDISR_FIFOERR) {
++			dev_warn(info->device, "FIFO underflow %#x\n", status);
++		} else if (status & LCDC_LCDISR_BASE) {
++			/* Check base layer's overflow error. */
++			baselayer_status = lcdc_readl(sinfo, ATMEL_LCDC_BASEISR);
++
++			if (baselayer_status & LCDC_BASEISR_OVR)
++				dev_warn(info->device, "base layer overflow %#x\n",
++							baselayer_status);
+ 
+-	status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
+-	if (status & ATMEL_LCDC_UFLWI) {
+-		dev_warn(info->device, "FIFO underflow %#x\n", status);
+-		/* reset DMA and FIFO to avoid screen shifting */
+-		schedule_work(&sinfo->task);
++		}
++	} else {
++		status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
++		if (status & ATMEL_LCDC_UFLWI) {
++			dev_warn(info->device, "FIFO underflow %#x\n", status);
++			/* reset DMA and FIFO to avoid screen shifting */
++			schedule_work(&sinfo->task);
++		}
++		lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
+ 	}
+-	lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
++
+ 	return IRQ_HANDLED;
+ }
+ 
+@@ -903,6 +1236,8 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
+ 
+ 	/* Initialize video memory */
+ 	map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	sinfo->p_dma_desc = NULL;
++	sinfo->dma_desc_phys = 0;
+ 	if (map) {
+ 		/* use a pre-allocated memory buffer */
+ 		info->fix.smem_start = map->start;
+@@ -1013,7 +1348,7 @@ unmap_mmio:
+ 	exit_backlight(sinfo);
+ 	iounmap(sinfo->mmio);
+ release_mem:
+- 	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
++	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
+ free_fb:
+ 	if (map)
+ 		iounmap(info->screen_base);
+@@ -1058,7 +1393,7 @@ static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
+ 	fb_dealloc_cmap(&info->cmap);
+ 	free_irq(sinfo->irq_base, info);
+ 	iounmap(sinfo->mmio);
+- 	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
++	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
+ 	if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
+ 		iounmap(info->screen_base);
+ 		release_mem_region(info->fix.smem_start, info->fix.smem_len);
+@@ -1083,10 +1418,17 @@ static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
+ 	 * We don't want to handle interrupts while the clock is
+ 	 * stopped. It may take forever.
+ 	 */
+-	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
++	if (cpu_is_at91sam9x5()) {
++		/* Disable all interrupts */
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDIDR, ~0UL);
++		lcdc_writel(sinfo, ATMEL_LCDC_BASEIDR, ~0UL);
++	} else {
++		lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
++
++		sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
++		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
++	}
+ 
+-	sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
+-	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
+ 	if (sinfo->atmel_lcdfb_power_control)
+ 		sinfo->atmel_lcdfb_power_control(0);
+ 
+@@ -1105,11 +1447,18 @@ static int atmel_lcdfb_resume(struct platform_device *pdev)
+ 	atmel_lcdfb_start(sinfo);
+ 	if (sinfo->atmel_lcdfb_power_control)
+ 		sinfo->atmel_lcdfb_power_control(1);
+-	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
+ 
+-	/* Enable FIFO & DMA errors */
+-	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI
+-			| ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
++	if (cpu_is_at91sam9x5()) {
++		/* Enable fifo error & BASE LAYER overflow interrupts */
++		lcdc_writel(sinfo, ATMEL_LCDC_BASEIER, LCDC_BASEIER_OVR);
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDIER, LCDC_LCDIER_FIFOERRIE | LCDC_LCDIER_BASEIE);
++	} else {
++		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
++
++		/* Enable FIFO & DMA errors */
++		lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI
++				| ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
++	}
+ 
+ 	return 0;
+ }
+diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
+index 28447f1..5183ab7 100644
+--- a/include/video/atmel_lcdc.h
++++ b/include/video/atmel_lcdc.h
+@@ -47,12 +47,16 @@ struct atmel_lcdfb_info {
+ 	struct clk		*bus_clk;
+ 	struct clk		*lcdc_clk;
+ 
++	struct lcd_dma_desc	*p_dma_desc;
++	dma_addr_t		dma_desc_phys;
++
+ #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
+ 	struct backlight_device	*backlight;
+ 	u8			bl_power;
+ #endif
+ 	bool			lcdcon_is_backlight;
+ 	bool			lcdcon_pol_negative;
++	bool			alpha_enabled;
+ 	u8			saved_lcdcon;
+ 
+ 	u8			default_bpp;
+@@ -64,6 +68,12 @@ struct atmel_lcdfb_info {
+ 	u32			pseudo_palette[16];
+ };
+ 
++struct lcd_dma_desc {
++	u32	address;
++	u32	control;
++	u32	next;
++};
++
+ #define ATMEL_LCDC_DMABADDR1	0x00
+ #define ATMEL_LCDC_DMABADDR2	0x04
+ #define ATMEL_LCDC_DMAFRMPT1	0x08
+@@ -214,6 +224,11 @@ struct atmel_lcdfb_info {
+ #define	ATMEL_LCDC_OWRI		(1 << 5)
+ #define	ATMEL_LCDC_MERI		(1 << 6)
+ 
++#if !defined(CONFIG_ARCH_AT91SAM9X5)
+ #define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
++#else
++/* Base layer CLUT */
++#define ATMEL_LCDC_LUT(n)	(0x0400 + ((n)*4))
++#endif
+ 
+ #endif /* __ATMEL_LCDC_H__ */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0021-video-atmel_lcdfb-The-output-bpp-should-not-change-a.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0021-video-atmel_lcdfb-The-output-bpp-should-not-change-a.patch
new file mode 100644
index 0000000..4e6b7f3
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0021-video-atmel_lcdfb-The-output-bpp-should-not-change-a.patch
@@ -0,0 +1,66 @@
+From f3d06832afe329d55759ec28d719925a10abc7ac Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Wed, 9 Mar 2011 11:21:51 +0800
+Subject: [PATCH 021/107] video/atmel_lcdfb: The output bpp should not change
+ according to memory bpp
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The 9x5-ek using 24 bits output for its connection to LCD screen.
+The output bpp can now be configurated in board file.
+
+XXX: these are two different changes?
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/atmel_lcdfb.c |   25 +++----------------------
+ 1 files changed, 3 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index fa9431b..7ba17cb 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -664,7 +664,9 @@ static int atmel_lcdfb_setup_9x5_core(struct fb_info *info)
+ 	}
+ 
+ 	/* Initialize control register 5 */
+-	value = (sinfo->guard_time << LCDC_LCDCFG5_GUARDTIME_OFFSET)
++	/* In 9x5, the default_lcdcon2 will use for LCDCFG5 */
++	value = sinfo->default_lcdcon2;
++	value |= (sinfo->guard_time << LCDC_LCDCFG5_GUARDTIME_OFFSET)
+ 		| LCDC_LCDCFG5_DISPDLY
+ 		| LCDC_LCDCFG5_VSPDLYS;
+ 
+@@ -673,27 +675,6 @@ static int atmel_lcdfb_setup_9x5_core(struct fb_info *info)
+ 	if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
+ 		value |= LCDC_LCDCFG5_VSPOL;
+ 
+-	switch (info->var.bits_per_pixel) {
+-	case 12:
+-		value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
+-		break;
+-	case 16:
+-		if (info->var.transp.offset != 0)
+-			value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
+-		else
+-			value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
+-		break;
+-	case 18:
+-		value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
+-		break;
+-	case 24:
+-	case 32:
+-		value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
+-		break;
+-	default:
+-		BUG();
+-		break;
+-	}
+ 	dev_dbg(info->device, "  * LCDC_LCDCFG5 = %08lx\n", value);
+ 	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG5, value);
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0022-input-atmel_tsadcc-add-support-for-ARCH_AT91SAM9X5.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0022-input-atmel_tsadcc-add-support-for-ARCH_AT91SAM9X5.patch
new file mode 100644
index 0000000..042b118
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0022-input-atmel_tsadcc-add-support-for-ARCH_AT91SAM9X5.patch
@@ -0,0 +1,410 @@
+From e8a10c60910fc34ef8d0ac97e19cc8efef10680c Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Wed, 17 Nov 2010 12:28:13 +0100
+Subject: [PATCH 022/107] input: atmel_tsadcc: add support for ARCH_AT91SAM9X5
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+XXX: split header creation in a new patch (or don't do it)
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/input/touchscreen/Kconfig        |    2 +-
+ drivers/input/touchscreen/atmel_tsadcc.c |  150 +++++++++++-----------------
+ drivers/input/touchscreen/atmel_tsadcc.h |  162 ++++++++++++++++++++++++++++++
+ 3 files changed, 223 insertions(+), 91 deletions(-)
+ create mode 100644 drivers/input/touchscreen/atmel_tsadcc.h
+
+diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
+index 434fd80..4b252ce 100644
+--- a/drivers/input/touchscreen/Kconfig
++++ b/drivers/input/touchscreen/Kconfig
+@@ -397,7 +397,7 @@ config TOUCHSCREEN_TOUCHWIN
+ 
+ config TOUCHSCREEN_ATMEL_TSADCC
+ 	tristate "Atmel Touchscreen Interface"
+-	depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
++	depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 || ARCH_AT91SAM9X5
+ 	help
+ 	  Say Y here if you have a 4-wire touchscreen connected to the
+           ADC Controller on your Atmel SoC (such as the AT91SAM9RL).
+diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c
+index 3d9b516..f307b6e 100644
+--- a/drivers/input/touchscreen/atmel_tsadcc.c
++++ b/drivers/input/touchscreen/atmel_tsadcc.c
+@@ -25,74 +25,9 @@
+ #include <mach/board.h>
+ #include <mach/cpu.h>
+ 
+-/* Register definitions based on AT91SAM9RL64 preliminary draft datasheet */
+-
+-#define ATMEL_TSADCC_CR		0x00	/* Control register */
+-#define   ATMEL_TSADCC_SWRST	(1 << 0)	/* Software Reset*/
+-#define	  ATMEL_TSADCC_START	(1 << 1)	/* Start conversion */
+-
+-#define ATMEL_TSADCC_MR		0x04	/* Mode register */
+-#define	  ATMEL_TSADCC_TSAMOD	(3    <<  0)	/* ADC mode */
+-#define	    ATMEL_TSADCC_TSAMOD_ADC_ONLY_MODE	(0x0)	/* ADC Mode */
+-#define	    ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE	(0x1)	/* Touch Screen Only Mode */
+-#define	  ATMEL_TSADCC_LOWRES	(1    <<  4)	/* Resolution selection */
+-#define	  ATMEL_TSADCC_SLEEP	(1    <<  5)	/* Sleep mode */
+-#define	  ATMEL_TSADCC_PENDET	(1    <<  6)	/* Pen Detect selection */
+-#define	  ATMEL_TSADCC_PRES	(1    <<  7)	/* Pressure Measurement Selection */
+-#define	  ATMEL_TSADCC_PRESCAL	(0x3f <<  8)	/* Prescalar Rate Selection */
+-#define	  ATMEL_TSADCC_EPRESCAL	(0xff <<  8)	/* Prescalar Rate Selection (Extended) */
+-#define	  ATMEL_TSADCC_STARTUP	(0x7f << 16)	/* Start Up time */
+-#define	  ATMEL_TSADCC_SHTIM	(0xf  << 24)	/* Sample & Hold time */
+-#define	  ATMEL_TSADCC_PENDBC	(0xf  << 28)	/* Pen Detect debouncing time */
+-
+-#define ATMEL_TSADCC_TRGR	0x08	/* Trigger register */
+-#define	  ATMEL_TSADCC_TRGMOD	(7      <<  0)	/* Trigger mode */
+-#define	    ATMEL_TSADCC_TRGMOD_NONE		(0 << 0)
+-#define     ATMEL_TSADCC_TRGMOD_EXT_RISING	(1 << 0)
+-#define     ATMEL_TSADCC_TRGMOD_EXT_FALLING	(2 << 0)
+-#define     ATMEL_TSADCC_TRGMOD_EXT_ANY		(3 << 0)
+-#define     ATMEL_TSADCC_TRGMOD_PENDET		(4 << 0)
+-#define     ATMEL_TSADCC_TRGMOD_PERIOD		(5 << 0)
+-#define     ATMEL_TSADCC_TRGMOD_CONTINUOUS	(6 << 0)
+-#define   ATMEL_TSADCC_TRGPER	(0xffff << 16)	/* Trigger period */
+-
+-#define ATMEL_TSADCC_TSR	0x0C	/* Touch Screen register */
+-#define	  ATMEL_TSADCC_TSFREQ	(0xf <<  0)	/* TS Frequency in Interleaved mode */
+-#define	  ATMEL_TSADCC_TSSHTIM	(0xf << 24)	/* Sample & Hold time */
+-
+-#define ATMEL_TSADCC_CHER	0x10	/* Channel Enable register */
+-#define ATMEL_TSADCC_CHDR	0x14	/* Channel Disable register */
+-#define ATMEL_TSADCC_CHSR	0x18	/* Channel Status register */
+-#define	  ATMEL_TSADCC_CH(n)	(1 << (n))	/* Channel number */
+-
+-#define ATMEL_TSADCC_SR		0x1C	/* Status register */
+-#define	  ATMEL_TSADCC_EOC(n)	(1 << ((n)+0))	/* End of conversion for channel N */
+-#define	  ATMEL_TSADCC_OVRE(n)	(1 << ((n)+8))	/* Overrun error for channel N */
+-#define	  ATMEL_TSADCC_DRDY	(1 << 16)	/* Data Ready */
+-#define	  ATMEL_TSADCC_GOVRE	(1 << 17)	/* General Overrun Error */
+-#define	  ATMEL_TSADCC_ENDRX	(1 << 18)	/* End of RX Buffer */
+-#define	  ATMEL_TSADCC_RXBUFF	(1 << 19)	/* TX Buffer full */
+-#define	  ATMEL_TSADCC_PENCNT	(1 << 20)	/* Pen contact */
+-#define	  ATMEL_TSADCC_NOCNT	(1 << 21)	/* No contact */
+-
+-#define ATMEL_TSADCC_LCDR	0x20	/* Last Converted Data register */
+-#define	  ATMEL_TSADCC_DATA	(0x3ff << 0)	/* Channel data */
+-
+-#define ATMEL_TSADCC_IER	0x24	/* Interrupt Enable register */
+-#define ATMEL_TSADCC_IDR	0x28	/* Interrupt Disable register */
+-#define ATMEL_TSADCC_IMR	0x2C	/* Interrupt Mask register */
+-#define ATMEL_TSADCC_CDR0	0x30	/* Channel Data 0 */
+-#define ATMEL_TSADCC_CDR1	0x34	/* Channel Data 1 */
+-#define ATMEL_TSADCC_CDR2	0x38	/* Channel Data 2 */
+-#define ATMEL_TSADCC_CDR3	0x3C	/* Channel Data 3 */
+-#define ATMEL_TSADCC_CDR4	0x40	/* Channel Data 4 */
+-#define ATMEL_TSADCC_CDR5	0x44	/* Channel Data 5 */
+-
+-#define ATMEL_TSADCC_XPOS	0x50
+-#define ATMEL_TSADCC_Z1DAT	0x54
+-#define ATMEL_TSADCC_Z2DAT	0x58
+-
+-#define PRESCALER_VAL(x)	((x) >> 8)
++#include "atmel_tsadcc.h"
++
++#define cpu_has_9x5_adc() (cpu_is_at91sam9x5())
+ 
+ #define ADC_DEFAULT_CLOCK	100000
+ 
+@@ -124,12 +59,17 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 
+ 	if (status & ATMEL_TSADCC_NOCNT) {
+ 		/* Contact lost */
+-		reg = atmel_tsadcc_read(ATMEL_TSADCC_MR) | ATMEL_TSADCC_PENDBC;
+-
+-		atmel_tsadcc_write(ATMEL_TSADCC_MR, reg);
++		if (cpu_has_9x5_adc()) {
++			/* 9X5 using TSMR to set PENDBC time */
++			reg = atmel_tsadcc_read(ATMEL_TSADCC_TSMR) | ATMEL_TSADCC_PENDBC;
++			atmel_tsadcc_write(ATMEL_TSADCC_TSMR, reg);
++		} else {
++			reg = atmel_tsadcc_read(ATMEL_TSADCC_MR) | ATMEL_TSADCC_PENDBC;
++			atmel_tsadcc_write(ATMEL_TSADCC_MR, reg);
++		}
+ 		atmel_tsadcc_write(ATMEL_TSADCC_TRGR, ATMEL_TSADCC_TRGMOD_NONE);
+ 		atmel_tsadcc_write(ATMEL_TSADCC_IDR,
+-				   ATMEL_TSADCC_EOC(3) | ATMEL_TSADCC_NOCNT);
++				   ATMEL_TSADCC_CONVERSION_END | ATMEL_TSADCC_NOCNT);
+ 		atmel_tsadcc_write(ATMEL_TSADCC_IER, ATMEL_TSADCC_PENCNT);
+ 
+ 		input_report_key(input_dev, BTN_TOUCH, 0);
+@@ -138,23 +78,31 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 
+ 	} else if (status & ATMEL_TSADCC_PENCNT) {
+ 		/* Pen detected */
+-		reg = atmel_tsadcc_read(ATMEL_TSADCC_MR);
+-		reg &= ~ATMEL_TSADCC_PENDBC;
++		if (cpu_has_9x5_adc()) {
++			reg = atmel_tsadcc_read(ATMEL_TSADCC_TSMR);
++			reg &= ~ATMEL_TSADCC_PENDBC;
++			atmel_tsadcc_write(ATMEL_TSADCC_TSMR, reg);
++		} else {
++			reg = atmel_tsadcc_read(ATMEL_TSADCC_MR);
++			reg &= ~ATMEL_TSADCC_PENDBC;
++			atmel_tsadcc_write(ATMEL_TSADCC_MR, reg);
++		}
+ 
+ 		atmel_tsadcc_write(ATMEL_TSADCC_IDR, ATMEL_TSADCC_PENCNT);
+-		atmel_tsadcc_write(ATMEL_TSADCC_MR, reg);
+ 		atmel_tsadcc_write(ATMEL_TSADCC_IER,
+-				   ATMEL_TSADCC_EOC(3) | ATMEL_TSADCC_NOCNT);
++				   ATMEL_TSADCC_CONVERSION_END | ATMEL_TSADCC_NOCNT);
+ 		atmel_tsadcc_write(ATMEL_TSADCC_TRGR,
+ 				   ATMEL_TSADCC_TRGMOD_PERIOD | (0x0FFF << 16));
+ 
+-	} else if (status & ATMEL_TSADCC_EOC(3)) {
++	} else if ((status & ATMEL_TSADCC_CONVERSION_END) == ATMEL_TSADCC_CONVERSION_END) {
+ 		/* Conversion finished */
+ 
+ 		if (ts_dev->bufferedmeasure) {
+ 			/* Last measurement is always discarded, since it can
+ 			 * be erroneous.
+ 			 * Always report previous measurement */
++			dev_dbg(&input_dev->dev, "x = %d, y = %d\n",
++					ts_dev->prev_absx, ts_dev->prev_absy);
+ 			input_report_abs(input_dev, ABS_X, ts_dev->prev_absx);
+ 			input_report_abs(input_dev, ABS_Y, ts_dev->prev_absy);
+ 			input_report_key(input_dev, BTN_TOUCH, 1);
+@@ -163,11 +111,16 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 			ts_dev->bufferedmeasure = 1;
+ 
+ 		/* Now make new measurement */
+-		ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_CDR3) << 10;
+-		ts_dev->prev_absx /= atmel_tsadcc_read(ATMEL_TSADCC_CDR2);
+-
+-		ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_CDR1) << 10;
+-		ts_dev->prev_absy /= atmel_tsadcc_read(ATMEL_TSADCC_CDR0);
++		if (cpu_has_9x5_adc()) {
++			ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_XPOSR) & 0xffff;
++			ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_YPOSR) & 0xffff;
++		} else {
++			ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_CDR3) << 10;
++			ts_dev->prev_absx /= atmel_tsadcc_read(ATMEL_TSADCC_CDR2);
++
++			ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_CDR1) << 10;
++			ts_dev->prev_absy /= atmel_tsadcc_read(ATMEL_TSADCC_CDR0);
++		}
+ 	}
+ 
+ 	return IRQ_HANDLED;
+@@ -284,18 +237,35 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
+ 
+ 	dev_info(&pdev->dev, "Prescaler is set at: %d\n", prsc);
+ 
+-	reg = ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE		|
+-		((0x00 << 5) & ATMEL_TSADCC_SLEEP)	|	/* Normal Mode */
+-		((0x01 << 6) & ATMEL_TSADCC_PENDET)	|	/* Enable Pen Detect */
+-		(prsc << 8)				|
+-		((0x26 << 16) & ATMEL_TSADCC_STARTUP)	|
+-		((pdata->pendet_debounce << 28) & ATMEL_TSADCC_PENDBC);
++	if (cpu_has_9x5_adc()) {
++		reg = 	((0x01 << 5) & ATMEL_TSADCC_SLEEP)	|	/* Sleep Mode */
++			(prsc << 8)				|
++			((0x8 << 16) & ATMEL_TSADCC_STARTUP)	|
++			((pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TRACKTIM);
++	} else {
++		reg = ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE		|
++			((0x00 << 5) & ATMEL_TSADCC_SLEEP)	|	/* Normal Mode */
++			((0x01 << 6) & ATMEL_TSADCC_PENDET)	|	/* Enable Pen Detect */
++			(prsc << 8)				|
++			((0x26 << 16) & ATMEL_TSADCC_STARTUP)	|
++			((pdata->pendet_debounce << 28) & ATMEL_TSADCC_PENDBC);
++	}
+ 
+ 	atmel_tsadcc_write(ATMEL_TSADCC_CR, ATMEL_TSADCC_SWRST);
+ 	atmel_tsadcc_write(ATMEL_TSADCC_MR, reg);
+ 	atmel_tsadcc_write(ATMEL_TSADCC_TRGR, ATMEL_TSADCC_TRGMOD_NONE);
+-	atmel_tsadcc_write(ATMEL_TSADCC_TSR,
+-		(pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TSSHTIM);
++
++	if (cpu_has_9x5_adc()) {
++		atmel_tsadcc_write(ATMEL_TSADCC_TSMR,
++					ATMEL_TSADCC_TSMODE_4WIRE_NO_PRESS	|
++					ATMEL_TSADCC_NOTSDMA			|
++					ATMEL_TSADCC_PENDET_ENA			|
++					(pdata->pendet_debounce << 28)		|
++					(0x0 << 8));
++	} else {
++		atmel_tsadcc_write(ATMEL_TSADCC_TSR,
++			(pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TSSHTIM);
++	}
+ 
+ 	atmel_tsadcc_read(ATMEL_TSADCC_SR);
+ 	atmel_tsadcc_write(ATMEL_TSADCC_IER, ATMEL_TSADCC_PENCNT);
+diff --git a/drivers/input/touchscreen/atmel_tsadcc.h b/drivers/input/touchscreen/atmel_tsadcc.h
+new file mode 100644
+index 0000000..5918c20
+--- /dev/null
++++ b/drivers/input/touchscreen/atmel_tsadcc.h
+@@ -0,0 +1,162 @@
++/*
++ *  Header file for AT91/AT32 ADC + touchscreen Controller
++ *
++ *  Data structure and register user interface
++ *
++ *  Copyright (C) 2010 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#ifndef __ATMEL_TSADCC_H__
++#define __ATMEL_TSADCC_H__
++
++/* Register definitions based on AT91SAM9RL64 preliminary draft datasheet */
++#define ATMEL_TSADCC_CR		0x00	/* Control register */
++#define   ATMEL_TSADCC_SWRST	(1 << 0)	/* Software Reset*/
++#define	  ATMEL_TSADCC_START	(1 << 1)	/* Start conversion */
++
++#define ATMEL_TSADCC_MR		0x04	/* Mode register */
++#define	  ATMEL_TSADCC_TSAMOD	(3    <<  0)	/* ADC mode */
++#define	    ATMEL_TSADCC_TSAMOD_ADC_ONLY_MODE	(0x0)	/* ADC Mode */
++#define	    ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE	(0x1)	/* Touch Screen Only Mode */
++#define	  ATMEL_TSADCC_LOWRES	(1    <<  4)	/* Resolution selection */
++#define	  ATMEL_TSADCC_SLEEP	(1    <<  5)	/* Sleep mode */
++#define	  ATMEL_TSADCC_PENDET	(1    <<  6)	/* Pen Detect selection */
++#define	  ATMEL_TSADCC_PRES	(1    <<  7)	/* Pressure Measurement Selection */
++#define	  ATMEL_TSADCC_PRESCAL	(0x3f <<  8)	/* Prescalar Rate Selection */
++#define	  ATMEL_TSADCC_EPRESCAL	(0xff <<  8)	/* Prescalar Rate Selection (Extended) */
++#define	  ATMEL_TSADCC_STARTUP	(0x7f << 16)	/* Start Up time */
++#define	  ATMEL_TSADCC_SHTIM	(0xf  << 24)	/* Sample & Hold time */
++#define	  ATMEL_TSADCC_PENDBC	(0xf  << 28)	/* Pen Detect debouncing time */
++
++#define ATMEL_TSADCC_TRGR	0x08	/* Trigger register */
++#define	  ATMEL_TSADCC_TRGMOD	(7      <<  0)	/* Trigger mode */
++#define	    ATMEL_TSADCC_TRGMOD_NONE		(0 << 0)
++#define     ATMEL_TSADCC_TRGMOD_EXT_RISING	(1 << 0)
++#define     ATMEL_TSADCC_TRGMOD_EXT_FALLING	(2 << 0)
++#define     ATMEL_TSADCC_TRGMOD_EXT_ANY		(3 << 0)
++#define     ATMEL_TSADCC_TRGMOD_PENDET		(4 << 0)
++#define     ATMEL_TSADCC_TRGMOD_PERIOD		(5 << 0)
++#define     ATMEL_TSADCC_TRGMOD_CONTINUOUS	(6 << 0)
++#define   ATMEL_TSADCC_TRGPER	(0xffff << 16)	/* Trigger period */
++
++#define ATMEL_TSADCC_TSR	0x0C	/* Touch Screen register */
++#define	  ATMEL_TSADCC_TSFREQ	(0xf <<  0)	/* TS Frequency in Interleaved mode */
++#define	  ATMEL_TSADCC_TSSHTIM	(0xf << 24)	/* Sample & Hold time */
++
++#define ATMEL_TSADCC_CHER	0x10	/* Channel Enable register */
++#define ATMEL_TSADCC_CHDR	0x14	/* Channel Disable register */
++#define ATMEL_TSADCC_CHSR	0x18	/* Channel Status register */
++#define	  ATMEL_TSADCC_CH(n)	(1 << (n))	/* Channel number */
++
++#define ATMEL_TSADCC_SR		0x1C	/* Status register */
++#define	  ATMEL_TSADCC_EOC(n)	(1 << ((n)+0))	/* End of conversion for channel N */
++#define	  ATMEL_TSADCC_OVRE(n)	(1 << ((n)+8))	/* Overrun error for channel N */
++#define	  ATMEL_TSADCC_DRDY	(1 << 16)	/* Data Ready */
++#define	  ATMEL_TSADCC_GOVRE	(1 << 17)	/* General Overrun Error */
++#define	  ATMEL_TSADCC_ENDRX	(1 << 18)	/* End of RX Buffer */
++#define	  ATMEL_TSADCC_RXBUFF	(1 << 19)	/* TX Buffer full */
++#define	  ATMEL_TSADCC_PENCNT	(1 << 20)	/* Pen contact */
++#define	  ATMEL_TSADCC_NOCNT	(1 << 21)	/* No contact */
++
++#define ATMEL_TSADCC_LCDR	0x20	/* Last Converted Data register */
++#define	  ATMEL_TSADCC_DATA	(0x3ff << 0)	/* Channel data */
++
++#define ATMEL_TSADCC_IER	0x24	/* Interrupt Enable register */
++#define ATMEL_TSADCC_IDR	0x28	/* Interrupt Disable register */
++#define ATMEL_TSADCC_IMR	0x2C	/* Interrupt Mask register */
++#define ATMEL_TSADCC_CDR0	0x30	/* Channel Data 0 */
++#define ATMEL_TSADCC_CDR1	0x34	/* Channel Data 1 */
++#define ATMEL_TSADCC_CDR2	0x38	/* Channel Data 2 */
++#define ATMEL_TSADCC_CDR3	0x3C	/* Channel Data 3 */
++#define ATMEL_TSADCC_CDR4	0x40	/* Channel Data 4 */
++#define ATMEL_TSADCC_CDR5	0x44	/* Channel Data 5 */
++
++#define ATMEL_TSADCC_XPOS	0x50
++#define ATMEL_TSADCC_Z1DAT	0x54
++#define ATMEL_TSADCC_Z2DAT	0x58
++
++#define ATMEL_TSADCC_CONVERSION_END		(ATMEL_TSADCC_EOC(3))
++
++/* Register definitions based on AT91SAM9X5 preliminary draft datasheet */
++#define	  ATMEL_TSADCC_TRACKTIM		(0x0f << 24)	/* Tracking Time */
++
++#define ATMEL_TSADCC_ISR	0x30	/* Interrupt Status register */
++#define	  ATMEL_TSADCC_XRDY		(1 << 20)	/* Measure XPOS Ready */
++#define	  ATMEL_TSADCC_YRDY		(1 << 21)	/* Measure YPOS Ready */
++#define	  ATMEL_TSADCC_PRDY		(1 << 22)	/* Measure Pressure Ready */
++#define	  ATMEL_TSADCC_COMPE		(1 << 26)	/* Comparison Event */
++#define	  ATMEL_TSADCC_PEN		(1 << 29)	/* Pen Contact */
++#define	  ATMEL_TSADCC_NOPEN		(1 << 30)	/* No Pen Contact */
++#define	  ATMEL_TSADCC_PENDET_STATUS	(1 << 31)	/* Pen Detect Status (not interrupt source) */
++
++#define ATMEL_TSADCC_TSMR	0xb0
++#define	  ATMEL_TSADCC_TSMODE		(3 <<  0)	/* Touch Screen Mode */
++#define	    ATMEL_TSADCC_TSMODE_NO		(0 << 0)	/* No Touch Screen */
++#define	    ATMEL_TSADCC_TSMODE_4WIRE_NO_PRESS	(1 << 0)	/* 4-wire Touch Screen without pressure measurement */
++#define	    ATMEL_TSADCC_TSMODE_4WIRE_PRESS	(2 << 0)	/* 4-wire Touch Screen with pressure measurement */
++#define	    ATMEL_TSADCC_TSMODE_5WIRE		(3 << 0)	/* 5-wire Touch Screen */
++#define	  ATMEL_TSADCC_TSAV		(3 <<  4)	/* Touch Screen Average */
++#define	    ATMEL_TSADCC_TSAV_1			(0 << 4)	/* No filtering. Only one conversion ADC per measure */
++#define	    ATMEL_TSADCC_TSAV_2			(1 << 4)	/* Averages 2 ADC conversions */
++#define	    ATMEL_TSADCC_TSAV_4			(2 << 4)	/* Averages 4 ADC conversions */
++#define	    ATMEL_TSADCC_TSAV_8			(3 << 4)	/* Averages 8 ADC conversions */
++#define	  ATMEL_TSADCC_TSSCTIM		(0x0f << 16)	/* Touch Screen switches closure time */
++
++#define	  ATMEL_TSADCC_NOTSDMA		(1 << 22)	/* No Touchscreen DMA */
++#define	  ATMEL_TSADCC_PENDET_DIS	(0 << 24)	/* Pen contact detection disable */
++#define	  ATMEL_TSADCC_PENDET_ENA	(1 << 24)	/* Pen contact detection enable */
++
++#define ATMEL_TSADCC_XPOSR	0xb4
++#define	  ATMEL_TSADCC_XSCALE		(0x3ff << 16)	/* Scale of X Position */
++
++#define ATMEL_TSADCC_YPOSR	0xb8
++#define	  ATMEL_TSADCC_YPOS		(0x3ff <<  0)	/* Y Position */
++#define	  ATMEL_TSADCC_YSCALE		(0x3ff << 16)	/* Scale of Y Position */
++
++/* 9x5 ADC registers which conflict with previous definition */
++#ifdef CONFIG_ARCH_AT91SAM9X5
++#undef	 ATMEL_TSADCC_TRGR
++#undef	 ATMEL_TSADCC_SR
++#define ATMEL_TSADCC_SR		ATMEL_TSADCC_ISR
++#define ATMEL_TSADCC_TRGR	0xc0
++
++/* For code compatiable, redefine with 9x5 value */
++#undef	  ATMEL_TSADCC_STARTUP
++#define	  ATMEL_TSADCC_STARTUP		(0x0f << 16)	/* Startup Time */
++#undef	  ATMEL_TSADCC_DRDY
++#define	  ATMEL_TSADCC_DRDY		(1 << 24)	/* Data Ready */
++#undef	  ATMEL_TSADCC_GOVRE
++#define	  ATMEL_TSADCC_GOVRE		(1 << 25)	/* General Overrun */
++#undef	  ATMEL_TSADCC_TSFREQ
++#define	  ATMEL_TSADCC_TSFREQ		(0x0f <<  8)	/* Touch Screen Frequency */
++#undef	  ATMEL_TSADCC_PENDET
++#define	  ATMEL_TSADCC_PENDET		(1 << 24)	/* Pen Contact Detection Enable */
++#undef	  ATMEL_TSADCC_XPOS
++#define	  ATMEL_TSADCC_XPOS		(0x3ff <<  0)	/* X Position */
++
++#undef	  ATMEL_TSADCC_NOCNT
++#define	  ATMEL_TSADCC_NOCNT	ATMEL_TSADCC_NOPEN
++#undef	  ATMEL_TSADCC_PENCNT
++#define	  ATMEL_TSADCC_PENCNT	ATMEL_TSADCC_PEN
++#undef	  ATMEL_TSADCC_CONVERSION_END
++#define	  ATMEL_TSADCC_CONVERSION_END	(ATMEL_TSADCC_XRDY | ATMEL_TSADCC_YRDY | ATMEL_TSADCC_PRDY)
++
++#endif
++
++/* Retrieve prescaler value */
++#define PRESCALER_VAL(x)	((x) >> 8)
++
++#endif /* __ATMEL_TSADCC_H__ */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0023-input-atmel_tsadcc-add-touch-screen-pressure-measure.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0023-input-atmel_tsadcc-add-touch-screen-pressure-measure.patch
new file mode 100644
index 0000000..3597bba
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0023-input-atmel_tsadcc-add-touch-screen-pressure-measure.patch
@@ -0,0 +1,109 @@
+From b119d5f73277fc94d42927cb998333844d9c8fb1 Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Wed, 17 Nov 2010 13:12:11 +0100
+Subject: [PATCH 023/107] input: atmel_tsadcc: add touch screen pressure
+ measurement
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/input/touchscreen/atmel_tsadcc.c |   26 +++++++++++++++++++++++---
+ drivers/input/touchscreen/atmel_tsadcc.h |    4 ++++
+ 2 files changed, 27 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c
+index f307b6e..732b99b 100644
+--- a/drivers/input/touchscreen/atmel_tsadcc.c
++++ b/drivers/input/touchscreen/atmel_tsadcc.c
+@@ -38,6 +38,7 @@ struct atmel_tsadcc {
+ 	int			irq;
+ 	unsigned int		prev_absx;
+ 	unsigned int		prev_absy;
++	unsigned int		prev_absz;
+ 	unsigned char		bufferedmeasure;
+ };
+ 
+@@ -53,6 +54,9 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 
+ 	unsigned int status;
+ 	unsigned int reg;
++	unsigned int z1, z2;
++	unsigned int Rxp = 1;
++	unsigned int factor = 1000;
+ 
+ 	status = atmel_tsadcc_read(ATMEL_TSADCC_SR);
+ 	status &= atmel_tsadcc_read(ATMEL_TSADCC_IMR);
+@@ -101,11 +105,15 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 			/* Last measurement is always discarded, since it can
+ 			 * be erroneous.
+ 			 * Always report previous measurement */
+-			dev_dbg(&input_dev->dev, "x = %d, y = %d\n",
+-					ts_dev->prev_absx, ts_dev->prev_absy);
++			dev_dbg(&input_dev->dev,
++					"x = %d, y = %d, pressure = %d\n",
++					ts_dev->prev_absx, ts_dev->prev_absy,
++					ts_dev->prev_absz);
+ 			input_report_abs(input_dev, ABS_X, ts_dev->prev_absx);
+ 			input_report_abs(input_dev, ABS_Y, ts_dev->prev_absy);
+ 			input_report_key(input_dev, BTN_TOUCH, 1);
++			if (cpu_has_9x5_adc())
++				input_report_abs(input_dev, ABS_PRESSURE, ts_dev->prev_absz);
+ 			input_sync(input_dev);
+ 		} else
+ 			ts_dev->bufferedmeasure = 1;
+@@ -114,6 +122,17 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 		if (cpu_has_9x5_adc()) {
+ 			ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_XPOSR) & 0xffff;
+ 			ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_YPOSR) & 0xffff;
++
++			/* calculate the pressure */
++			reg = atmel_tsadcc_read(ATMEL_TSADCC_PRESSR);
++			z1 = reg & ATMEL_TSADCC_PRESSR_Z1;
++			z2 = (reg & ATMEL_TSADCC_PRESSR_Z2) >> 16;
++
++			if (z1 != 0)
++				ts_dev->prev_absz = Rxp * (ts_dev->prev_absx * factor / 1024) * (z2 * factor / z1 - factor) / factor;
++			else
++				ts_dev->prev_absz = 0;
++
+ 		} else {
+ 			ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_CDR3) << 10;
+ 			ts_dev->prev_absx /= atmel_tsadcc_read(ATMEL_TSADCC_CDR2);
+@@ -209,6 +228,7 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
+ 	__set_bit(EV_ABS, input_dev->evbit);
+ 	input_set_abs_params(input_dev, ABS_X, 0, 0x3FF, 0, 0);
+ 	input_set_abs_params(input_dev, ABS_Y, 0, 0x3FF, 0, 0);
++	input_set_abs_params(input_dev, ABS_PRESSURE, 0, 0xffffff, 0, 0);
+ 
+ 	input_set_capability(input_dev, EV_KEY, BTN_TOUCH);
+ 
+@@ -257,7 +277,7 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
+ 
+ 	if (cpu_has_9x5_adc()) {
+ 		atmel_tsadcc_write(ATMEL_TSADCC_TSMR,
+-					ATMEL_TSADCC_TSMODE_4WIRE_NO_PRESS	|
++					ATMEL_TSADCC_TSMODE_4WIRE_PRESS		|
+ 					ATMEL_TSADCC_NOTSDMA			|
+ 					ATMEL_TSADCC_PENDET_ENA			|
+ 					(pdata->pendet_debounce << 28)		|
+diff --git a/drivers/input/touchscreen/atmel_tsadcc.h b/drivers/input/touchscreen/atmel_tsadcc.h
+index 5918c20..231497e 100644
+--- a/drivers/input/touchscreen/atmel_tsadcc.h
++++ b/drivers/input/touchscreen/atmel_tsadcc.h
+@@ -126,6 +126,10 @@
+ #define	  ATMEL_TSADCC_YPOS		(0x3ff <<  0)	/* Y Position */
+ #define	  ATMEL_TSADCC_YSCALE		(0x3ff << 16)	/* Scale of Y Position */
+ 
++#define ATMEL_TSADCC_PRESSR	0xbc	/* Touchscreen Pressure Register */
++#define	  ATMEL_TSADCC_PRESSR_Z1	(0x3ff <<  0)	/* Data of Z1 Measurement */
++#define	  ATMEL_TSADCC_PRESSR_Z2	(0x3ff << 16)	/* Data of Z2 Measurement */
++
+ /* 9x5 ADC registers which conflict with previous definition */
+ #ifdef CONFIG_ARCH_AT91SAM9X5
+ #undef	 ATMEL_TSADCC_TRGR
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0024-input-atmel_tsadcc-enable-touchscreen-averaging-and-.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0024-input-atmel_tsadcc-enable-touchscreen-averaging-and-.patch
new file mode 100644
index 0000000..8a0b499
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0024-input-atmel_tsadcc-enable-touchscreen-averaging-and-.patch
@@ -0,0 +1,81 @@
+From fb7765b71accce169455b701eda556fb981a78eb Mon Sep 17 00:00:00 2001
+From: Ludovic Desroches <ludovic.desroches@atmel.com>
+Date: Tue, 5 Apr 2011 17:30:03 +0200
+Subject: [PATCH 024/107] input: atmel_tsadcc: enable touchscreen averaging
+ and add fast wake up
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Enable the touchscreen average to improve the resulting events. For this
+to work the trigger period needs to be reduced.
+
+This puts a field into at91_tsadcc_data to allow platforms to specify
+the number of conversions to average over.
+
+XXX: should the trigger period passed by the platform, too, as this
+depends on the number of conversions?
+XXX: seperate fast wake up into a seperate patch? What does it?
+XXX: don't use bare constants
+
+Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/input/touchscreen/atmel_tsadcc.c |   14 ++++++++------
+ drivers/input/touchscreen/atmel_tsadcc.h |    1 +
+ 2 files changed, 9 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c
+index 732b99b..4b6fb94 100644
+--- a/drivers/input/touchscreen/atmel_tsadcc.c
++++ b/drivers/input/touchscreen/atmel_tsadcc.c
+@@ -96,7 +96,7 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 		atmel_tsadcc_write(ATMEL_TSADCC_IER,
+ 				   ATMEL_TSADCC_CONVERSION_END | ATMEL_TSADCC_NOCNT);
+ 		atmel_tsadcc_write(ATMEL_TSADCC_TRGR,
+-				   ATMEL_TSADCC_TRGMOD_PERIOD | (0x0FFF << 16));
++				   ATMEL_TSADCC_TRGMOD_PERIOD | (0x00D0 << 16));
+ 
+ 	} else if ((status & ATMEL_TSADCC_CONVERSION_END) == ATMEL_TSADCC_CONVERSION_END) {
+ 		/* Conversion finished */
+@@ -259,6 +259,7 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
+ 
+ 	if (cpu_has_9x5_adc()) {
+ 		reg = 	((0x01 << 5) & ATMEL_TSADCC_SLEEP)	|	/* Sleep Mode */
++			((0x01 << 6) & ATMEL_TSADCC_FWUP)	|	/* Fast Wake Up */
+ 			(prsc << 8)				|
+ 			((0x8 << 16) & ATMEL_TSADCC_STARTUP)	|
+ 			((pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TRACKTIM);
+@@ -277,11 +278,12 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
+ 
+ 	if (cpu_has_9x5_adc()) {
+ 		atmel_tsadcc_write(ATMEL_TSADCC_TSMR,
+-					ATMEL_TSADCC_TSMODE_4WIRE_PRESS		|
+-					ATMEL_TSADCC_NOTSDMA			|
+-					ATMEL_TSADCC_PENDET_ENA			|
+-					(pdata->pendet_debounce << 28)		|
+-					(0x0 << 8));
++					ATMEL_TSADCC_TSMODE_4WIRE_PRESS	|
++					(pdata->filtering_average << 4)	|	/* Touchscreen average */
++					ATMEL_TSADCC_NOTSDMA		|
++					ATMEL_TSADCC_PENDET_ENA		|
++					(pdata->pendet_debounce << 28)	|
++					(0x3 << 8));				/* Touchscreen freq */
+ 	} else {
+ 		atmel_tsadcc_write(ATMEL_TSADCC_TSR,
+ 			(pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TSSHTIM);
+diff --git a/drivers/input/touchscreen/atmel_tsadcc.h b/drivers/input/touchscreen/atmel_tsadcc.h
+index 231497e..572770a 100644
+--- a/drivers/input/touchscreen/atmel_tsadcc.h
++++ b/drivers/input/touchscreen/atmel_tsadcc.h
+@@ -34,6 +34,7 @@
+ #define	  ATMEL_TSADCC_LOWRES	(1    <<  4)	/* Resolution selection */
+ #define	  ATMEL_TSADCC_SLEEP	(1    <<  5)	/* Sleep mode */
+ #define	  ATMEL_TSADCC_PENDET	(1    <<  6)	/* Pen Detect selection */
++#define   ATMEL_TSADCC_FWUP	(1    <<  6)	/* Fast Wake Up selection (5series) */
+ #define	  ATMEL_TSADCC_PRES	(1    <<  7)	/* Pressure Measurement Selection */
+ #define	  ATMEL_TSADCC_PRESCAL	(0x3f <<  8)	/* Prescalar Rate Selection */
+ #define	  ATMEL_TSADCC_EPRESCAL	(0xff <<  8)	/* Prescalar Rate Selection (Extended) */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0025-input-atmel_tsadcc-add-ACR-register-and-change-trigg.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0025-input-atmel_tsadcc-add-ACR-register-and-change-trigg.patch
new file mode 100644
index 0000000..4d6e9bb
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0025-input-atmel_tsadcc-add-ACR-register-and-change-trigg.patch
@@ -0,0 +1,97 @@
+From 8a9cb430dfa0b998dc4a3c939e993e676a312fed Mon Sep 17 00:00:00 2001
+From: Ludovic Desroches <ludovic.desroches@atmel.com>
+Date: Fri, 6 May 2011 17:54:45 +0200
+Subject: [PATCH 025/107] input: atmel_tsadcc: add ACR register and change
+ trigger period value
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add ACR register which allows to configure internal ADC resistor, that should
+prevent from adding resistor on display module. Furthermore increase
+trigger period which seems to be related with resistor value. A Too small
+value causes continuous irq.
+
+Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/input/touchscreen/atmel_tsadcc.c |   30 +++++++++++++++++++++++++++++-
+ drivers/input/touchscreen/atmel_tsadcc.h |    3 +++
+ 2 files changed, 32 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c
+index 4b6fb94..9c3b330 100644
+--- a/drivers/input/touchscreen/atmel_tsadcc.c
++++ b/drivers/input/touchscreen/atmel_tsadcc.c
+@@ -47,6 +47,17 @@ static void __iomem		*tsc_base;
+ #define atmel_tsadcc_read(reg)		__raw_readl(tsc_base + (reg))
+ #define atmel_tsadcc_write(reg, val)	__raw_writel((val), tsc_base + (reg))
+ 
++static void atmel_tsadcc_dump_conf(struct platform_device *pdev)
++{
++	dev_info(&pdev->dev, "--- configuration ---\n");
++	dev_info(&pdev->dev, "Mode Register: %#x\n", atmel_tsadcc_read(ATMEL_TSADCC_MR));
++	dev_info(&pdev->dev, "Trigger Register: %#x\n", atmel_tsadcc_read(ATMEL_TSADCC_TRGR));
++	dev_info(&pdev->dev, "Touchscreen Mode Register: %#x\n", atmel_tsadcc_read(ATMEL_TSADCC_TSMR));
++	dev_info(&pdev->dev, "Analog Control Register: %#x\n", atmel_tsadcc_read(ATMEL_TSADCC_ACR));
++	dev_info(&pdev->dev, "ADC Channel Status Register: %#x\n", atmel_tsadcc_read(ATMEL_TSADCC_CHSR));
++	dev_info(&pdev->dev, "---------------------\n");
++}
++
+ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ {
+ 	struct atmel_tsadcc	*ts_dev = (struct atmel_tsadcc *)dev;
+@@ -95,8 +106,14 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 		atmel_tsadcc_write(ATMEL_TSADCC_IDR, ATMEL_TSADCC_PENCNT);
+ 		atmel_tsadcc_write(ATMEL_TSADCC_IER,
+ 				   ATMEL_TSADCC_CONVERSION_END | ATMEL_TSADCC_NOCNT);
++		/* this value is related to the resistor bits value of
++		 * ACR register and R64. If internal resistor value is
++		 * increased then this value has to be increased. This
++		 * behavior seems to happen only with averaging on 8
++		 * values
++		 */
+ 		atmel_tsadcc_write(ATMEL_TSADCC_TRGR,
+-				   ATMEL_TSADCC_TRGMOD_PERIOD | (0x00D0 << 16));
++				   ATMEL_TSADCC_TRGMOD_PERIOD | (0x0FF << 16));
+ 
+ 	} else if ((status & ATMEL_TSADCC_CONVERSION_END) == ATMEL_TSADCC_CONVERSION_END) {
+ 		/* Conversion finished */
+@@ -289,9 +306,20 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
+ 			(pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TSSHTIM);
+ 	}
+ 
++	/* Change adc internal resistor value for better pen detection,
++	 * default value is 100 kOhm.
++	 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
++	 * option only available on ES2 and higher
++	 */
++	if (cpu_has_9x5_adc()) {
++		atmel_tsadcc_write(ATMEL_TSADCC_ACR, pdata->pendet_sensitivity);
++	}
++
+ 	atmel_tsadcc_read(ATMEL_TSADCC_SR);
+ 	atmel_tsadcc_write(ATMEL_TSADCC_IER, ATMEL_TSADCC_PENCNT);
+ 
++	/* atmel_tsadcc_dump_conf(pdev); */
++
+ 	/* All went ok, so register to the input system */
+ 	err = input_register_device(input_dev);
+ 	if (err)
+diff --git a/drivers/input/touchscreen/atmel_tsadcc.h b/drivers/input/touchscreen/atmel_tsadcc.h
+index 572770a..fe74506 100644
+--- a/drivers/input/touchscreen/atmel_tsadcc.h
++++ b/drivers/input/touchscreen/atmel_tsadcc.h
+@@ -103,6 +103,9 @@
+ #define	  ATMEL_TSADCC_NOPEN		(1 << 30)	/* No Pen Contact */
+ #define	  ATMEL_TSADCC_PENDET_STATUS	(1 << 31)	/* Pen Detect Status (not interrupt source) */
+ 
++#define ATMEL_TSADCC_ACR	0x94	/* Analog Control Register */
++#define	  ATMEL_TSADCC_PENDET_SENSITIVITY	(0x3 << 0)	/* ADC internal resistor */
++
+ #define ATMEL_TSADCC_TSMR	0xb0
+ #define	  ATMEL_TSADCC_TSMODE		(3 <<  0)	/* Touch Screen Mode */
+ #define	    ATMEL_TSADCC_TSMODE_NO		(0 << 0)	/* No Touch Screen */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0026-MTD-atmel_nand-Add-PMECC-controller-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0026-MTD-atmel_nand-Add-PMECC-controller-support.patch
new file mode 100644
index 0000000..9fdf2d6
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0026-MTD-atmel_nand-Add-PMECC-controller-support.patch
@@ -0,0 +1,1175 @@
+From f3b6daeff4340b90ce98966871fbbdd3e1249578 Mon Sep 17 00:00:00 2001
+From: Hong Xu <hong.xu@atmel.com>
+Date: Wed, 26 Jan 2011 10:40:30 +0800
+Subject: [PATCH 026/107] MTD: atmel_nand: Add PMECC controller support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The PMECC controller is a programmable binary BCH (Bose, Chaudhuri and
+Hocquenghem) encoder/decoder. This controller can be used to generate redundancy
+information for both SLC and MLC NAND Flash devices.
+
+This patch adds support for PMECC controller and was tested on AT91SAM9X5-EK.
+
+Signed-off-by: Hong Xu <hong.xu@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/mtd/nand/Kconfig            |   17 +
+ drivers/mtd/nand/atmel_nand.c       |  236 +++++++++----
+ drivers/mtd/nand/atmel_nand_ecc.h   |   84 +++++
+ drivers/mtd/nand/atmel_nand_pmecc.c |  674 +++++++++++++++++++++++++++++++++++
+ 4 files changed, 947 insertions(+), 64 deletions(-)
+ create mode 100644 drivers/mtd/nand/atmel_nand_pmecc.c
+
+diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
+index edec457..b7b870c 100644
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -371,6 +371,23 @@ config MTD_NAND_ATMEL_ECC_HW
+ 
+ 	  If unsure, say Y
+ 
++config MTD_NAND_ATMEL_PMECC_HW
++	bool "Programmable Hardware ECC (BCH code)"
++	depends on ARCH_AT91SAM9X5
++	help
++	  Use Programmable Hardware ECC controller.
++
++	  The PMECC Controller is a programmable binary BCH (Bose, Chaudhuri
++	  and Hocquenghem) encoder/decoder. This controller can be used to
++	  generate redundancy information for both SLC and MLC NAND Flash
++	  devices.
++
++	  NB : hardware and software ECC schemes are incompatible.
++	  If you switch from one to another, you'll have to erase your
++	  mtd partition.
++
++	  If unsure, say Y
++
+ config MTD_NAND_ATMEL_ECC_SOFT
+ 	bool "Software ECC"
+ 	help
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index 950646a..2145c6e 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -15,6 +15,8 @@
+  *     		(u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
+  *     (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+  *
++ *  Add PMECC support for AT91SAM9X5 Series
++ *     (C) Copyright 2011 ATMEL, Hong Xu
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+@@ -36,7 +38,9 @@
+ #include <mach/board.h>
+ #include <mach/cpu.h>
+ 
+-#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
++#if defined(CONFIG_MTD_NAND_ATMEL_ECC_HW)
++#define hard_ecc	1
++#elif defined(CONFIG_MTD_NAND_ATMEL_PMECC_HW)
+ #define hard_ecc	1
+ #else
+ #define hard_ecc	0
+@@ -51,6 +55,8 @@
+ static int use_dma = 1;
+ module_param(use_dma, int, 0);
+ 
++#define NB_ERROR_MAX  25
++
+ static int on_flash_bbt = 0;
+ module_param(on_flash_bbt, int, 0);
+ 
+@@ -60,8 +66,38 @@ module_param(on_flash_bbt, int, 0);
+ #define ecc_writel(add, reg, value)			\
+ 	__raw_writel((value), add + ATMEL_ECC_##reg)
+ 
+-#include "atmel_nand_ecc.h"	/* Hardware ECC registers */
++/* Register access macros for PMECC */
++#define pmecc_readl(addr, reg) \
++	__raw_readl((addr) + ATMEL_PMECC_##reg)
++
++#define pmecc_writel(addr, reg, value) \
++	__raw_writel((value), (addr) + ATMEL_PMECC_##reg)
++
++#define pmecc_readb_ecc(addr, sector, n) \
++	__raw_readb((addr) + ATMEL_PMECC_ECCx + ((sector) * 0x40) + (n))
++
++#define pmecc_readl_rem(addr, sector, n) \
++	__raw_readl((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + (n))
++
++#define pmerrloc_readl(addr, reg) \
++	__raw_readl((addr) + ATMEL_PMERRLOC_##reg)
++
++#define pmerrloc_writel(addr, reg, value) \
++	__raw_writel((value), (addr) + ATMEL_PMERRLOC_##reg)
++
++#define pmerrloc_writel_sigma(addr, n, value) \
++	__raw_writel((value), (addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
++
++#define pmerrloc_readl_sigma(addr, n) \
++	__raw_readl((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
++
++#define pmerrloc_readl_el(addr, n) \
++	__raw_readl((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
+ 
++/* Include Hardware ECC registers */
++#include "atmel_nand_ecc.h"
++
++#if defined(CONFIG_MTD_NAND_ATMEL_ECC_HW)
+ /* oob layout for large page size
+  * bad block info is on bytes 0 and 1
+  * the bytes have to be consecutives to avoid
+@@ -87,6 +123,7 @@ static struct nand_ecclayout atmel_oobinfo_small = {
+ 		{6, 10}
+ 	},
+ };
++#endif
+ 
+ struct atmel_nand_host {
+ 	struct nand_chip	nand_chip;
+@@ -99,11 +136,45 @@ struct atmel_nand_host {
+ 
+ 	struct completion	comp;
+ 	struct dma_chan		*dma_chan;
++
++#if defined(CONFIG_MTD_NAND_ATMEL_PMECC_HW)
++	void __iomem		*pmerrloc_base;
++	void __iomem		*rom_base;
++	/* defines the error correcting capability */
++	int tt;
++	/* The number of ecc bytes for one sector */
++	int ecc_bytes_per_sector;
++	/* degree of the remainders, GF(2**mm) */
++	int mm;
++	/* length of codeword, nn=2**mm -1 */
++	int nn;
++	/* sector number per page */
++	int sector_number;
++	/* sector size in bytes */
++	int sector_size;
++
++	/* PMECC lookup table for alpha_to and index_of */
++	int16_t *alpha_to;
++	int16_t *index_of;
++
++	int16_t partial_syn[100];
++	int16_t si[100];
++	/* Sigma table */
++	int16_t smu[NB_ERROR_MAX + 2][2 * NB_ERROR_MAX + 1];
++	/** polynomal order */
++	int16_t lmu[NB_ERROR_MAX + 1];
++	uint8_t ecc_table[42 * 8];
++#endif
+ };
+ 
++#if defined(CONFIG_MTD_NAND_ATMEL_PMECC_HW)
++#include "atmel_nand_pmecc.c"
++#endif
++
+ static int cpu_has_dma(void)
+ {
+-	return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
++	return cpu_is_at91sam9rl() || cpu_is_at91sam9g45()
++	       || cpu_is_at91sam9x5();
+ }
+ 
+ /*
+@@ -293,6 +364,7 @@ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+ 		atmel_write_buf8(mtd, buf, len);
+ }
+ 
++#if defined(CONFIG_MTD_NAND_ATMEL_ECC_HW)
+ /*
+  * Calculate HW ECC
+  *
+@@ -479,6 +551,84 @@ static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
+ 	}
+ }
+ 
++static int __init atmel_nand_init_params(struct platform_device *pdev,
++					 struct atmel_nand_host *host)
++{
++	struct resource *regs;
++	struct nand_chip *nand_chip;
++	struct mtd_info *mtd;
++
++	nand_chip = &host->nand_chip;
++	mtd = &host->mtd;
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	if (!regs && hard_ecc) {
++		dev_err(host->dev, "atmel_nand: can't get I/O resource "
++				"regs\nFalling back on software ECC\n");
++	}
++
++	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
++	if (no_ecc)
++		nand_chip->ecc.mode = NAND_ECC_NONE;
++	if (hard_ecc && regs) {
++		host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
++		if (host->ecc == NULL) {
++			printk(KERN_ERR "atmel_nand: ioremap failed\n");
++			goto err_ecc_ioremap;
++		}
++
++		nand_chip->ecc.mode = NAND_ECC_HW;
++		nand_chip->ecc.calculate = atmel_nand_calculate;
++		nand_chip->ecc.correct = atmel_nand_correct;
++		nand_chip->ecc.hwctl = atmel_nand_hwctl;
++		nand_chip->ecc.read_page = atmel_nand_read_page;
++		nand_chip->ecc.bytes = 4;
++	}
++
++	if (nand_chip->ecc.mode == NAND_ECC_HW) {
++		/* ECC is calculated for the whole page (1 step) */
++		nand_chip->ecc.size = mtd->writesize;
++
++		/* set ECC page size and oob layout */
++		switch (mtd->writesize) {
++		case 512:
++			nand_chip->ecc.layout = &atmel_oobinfo_small;
++			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
++			break;
++		case 1024:
++			nand_chip->ecc.layout = &atmel_oobinfo_large;
++			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
++			break;
++		case 2048:
++			nand_chip->ecc.layout = &atmel_oobinfo_large;
++			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
++			break;
++		case 4096:
++			nand_chip->ecc.layout = &atmel_oobinfo_large;
++			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
++			break;
++		default:
++			/* page size not handled by HW ECC */
++			/* switching back to soft ECC */
++			nand_chip->ecc.mode = NAND_ECC_SOFT;
++			nand_chip->ecc.calculate = NULL;
++			nand_chip->ecc.correct = NULL;
++			nand_chip->ecc.hwctl = NULL;
++			nand_chip->ecc.read_page = NULL;
++			nand_chip->ecc.postpad = 0;
++			nand_chip->ecc.prepad = 0;
++			nand_chip->ecc.bytes = 0;
++			break;
++		}
++	}
++
++	return 0;
++
++err_ecc_ioremap:
++	return -EIO;
++}
++#endif
++
+ #ifdef CONFIG_MTD_CMDLINE_PARTS
+ static const char *part_probes[] = { "cmdlinepart", NULL };
+ #endif
+@@ -491,9 +641,8 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 	struct atmel_nand_host *host;
+ 	struct mtd_info *mtd;
+ 	struct nand_chip *nand_chip;
+-	struct resource *regs;
+ 	struct resource *mem;
+-	int res;
++	int res = 0;
+ 
+ #ifdef CONFIG_MTD_PARTITIONS
+ 	struct mtd_partition *partitions = NULL;
+@@ -539,29 +688,9 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 	if (host->board->rdy_pin)
+ 		nand_chip->dev_ready = atmel_nand_device_ready;
+ 
+-	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+-	if (!regs && hard_ecc) {
+-		printk(KERN_ERR "atmel_nand: can't get I/O resource "
+-				"regs\nFalling back on software ECC\n");
+-	}
+-
+ 	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
+ 	if (no_ecc)
+ 		nand_chip->ecc.mode = NAND_ECC_NONE;
+-	if (hard_ecc && regs) {
+-		host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
+-		if (host->ecc == NULL) {
+-			printk(KERN_ERR "atmel_nand: ioremap failed\n");
+-			res = -EIO;
+-			goto err_ecc_ioremap;
+-		}
+-		nand_chip->ecc.mode = NAND_ECC_HW;
+-		nand_chip->ecc.calculate = atmel_nand_calculate;
+-		nand_chip->ecc.correct = atmel_nand_correct;
+-		nand_chip->ecc.hwctl = atmel_nand_hwctl;
+-		nand_chip->ecc.read_page = atmel_nand_read_page;
+-		nand_chip->ecc.bytes = 4;
+-	}
+ 
+ 	nand_chip->chip_delay = 20;		/* 20us command delay time */
+ 
+@@ -613,42 +742,13 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 		goto err_scan_ident;
+ 	}
+ 
+-	if (nand_chip->ecc.mode == NAND_ECC_HW) {
+-		/* ECC is calculated for the whole page (1 step) */
+-		nand_chip->ecc.size = mtd->writesize;
+-
+-		/* set ECC page size and oob layout */
+-		switch (mtd->writesize) {
+-		case 512:
+-			nand_chip->ecc.layout = &atmel_oobinfo_small;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
+-			break;
+-		case 1024:
+-			nand_chip->ecc.layout = &atmel_oobinfo_large;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
+-			break;
+-		case 2048:
+-			nand_chip->ecc.layout = &atmel_oobinfo_large;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
+-			break;
+-		case 4096:
+-			nand_chip->ecc.layout = &atmel_oobinfo_large;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
+-			break;
+-		default:
+-			/* page size not handled by HW ECC */
+-			/* switching back to soft ECC */
+-			nand_chip->ecc.mode = NAND_ECC_SOFT;
+-			nand_chip->ecc.calculate = NULL;
+-			nand_chip->ecc.correct = NULL;
+-			nand_chip->ecc.hwctl = NULL;
+-			nand_chip->ecc.read_page = NULL;
+-			nand_chip->ecc.postpad = 0;
+-			nand_chip->ecc.prepad = 0;
+-			nand_chip->ecc.bytes = 0;
+-			break;
+-		}
+-	}
++#if defined(CONFIG_MTD_NAND_ATMEL_ECC_HW)
++	res = atmel_nand_init_params(pdev, host);
++#elif defined(CONFIG_MTD_NAND_ATMEL_PMECC_HW)
++	res = atmel_pmecc_init_params(pdev, host);
++#endif
++	if (res != 0)
++		goto err;
+ 
+ 	/* second phase scan */
+ 	if (nand_scan_tail(mtd)) {
+@@ -680,6 +780,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 	if (!res)
+ 		return res;
+ 
++err:
+ #ifdef CONFIG_MTD_PARTITIONS
+ err_no_partitions:
+ #endif
+@@ -691,9 +792,6 @@ err_no_card:
+ 	platform_set_drvdata(pdev, NULL);
+ 	if (host->dma_chan)
+ 		dma_release_channel(host->dma_chan);
+-	if (host->ecc)
+-		iounmap(host->ecc);
+-err_ecc_ioremap:
+ 	iounmap(host->io_base);
+ err_nand_ioremap:
+ 	kfree(host);
+@@ -712,6 +810,16 @@ static int __exit atmel_nand_remove(struct platform_device *pdev)
+ 
+ 	atmel_nand_disable(host);
+ 
++#if defined(CONFIG_MTD_NAND_ATMEL_PMECC_HW)
++	if (cpu_has_pmecc())
++			pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
++	if (host->pmerrloc_base) {
++		pmerrloc_writel(host->pmerrloc_base, ELDIS, 0xffffffff);
++		iounmap(host->pmerrloc_base);
++	}
++	if (host->rom_base)
++		iounmap(host->rom_base);
++#endif
+ 	if (host->ecc)
+ 		iounmap(host->ecc);
+ 
+diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
+index 578c776..6e0e2f3 100644
+--- a/drivers/mtd/nand/atmel_nand_ecc.h
++++ b/drivers/mtd/nand/atmel_nand_ecc.h
+@@ -36,4 +36,88 @@
+ #define ATMEL_ECC_NPR		0x10			/* NParity register */
+ #define		ATMEL_ECC_NPARITY	(0xffff << 0)		/* NParity */
+ 
++/* PMECC Register Definitions */
++#define ATMEL_PMECC_CFG			0x000	/* Configuration Register */
++#define		PMECC_CFG_BCH_ERR2		(0 << 0)
++#define		PMECC_CFG_BCH_ERR4		(1 << 0)
++#define		PMECC_CFG_BCH_ERR8		(2 << 0)
++#define		PMECC_CFG_BCH_ERR12		(3 << 0)
++#define		PMECC_CFG_BCH_ERR24		(4 << 0)
++
++#define		PMECC_CFG_SECTOR512		(0 << 4)
++#define		PMECC_CFG_SECTOR1024		(1 << 4)
++
++#define		PMECC_CFG_PAGE_1SECTOR		(0 << 8)
++#define		PMECC_CFG_PAGE_2SECTORS		(1 << 8)
++#define		PMECC_CFG_PAGE_4SECTORS		(2 << 8)
++#define		PMECC_CFG_PAGE_8SECTORS		(3 << 8)
++
++#define		PMECC_CFG_READ_OP		(0 << 12)
++#define		PMECC_CFG_WRITE_OP		(1 << 12)
++
++#define		PMECC_CFG_SPARE_ENABLE		(1 << 16)
++#define		PMECC_CFG_SPARE_DISABLE		(0 << 16)
++
++#define		PMECC_CFG_AUTO_ENABLE		(1 << 20)
++#define		PMECC_CFG_AUTO_DISABLE		(0 << 20)
++
++#define ATMEL_PMECC_SAREA		0x004	/* Spare area size */
++#define ATMEL_PMECC_SADDR		0x008	/* PMECC starting address */
++#define ATMEL_PMECC_EADDR		0x00c	/* PMECC ending address */
++#define ATMEL_PMECC_CLK			0x010	/* PMECC clock control */
++#define		PMECC_CLK_133MHZ		(2 << 0)
++
++#define ATMEL_PMECC_CTRL		0x014	/* PMECC control register */
++#define		PMECC_CTRL_RST			(1 << 0)
++#define		PMECC_CTRL_DATA			(1 << 1)
++#define		PMECC_CTRL_USER			(1 << 2)
++#define		PMECC_CTRL_ENABLE		(1 << 4)
++#define		PMECC_CTRL_DISABLE		(1 << 5)
++
++#define ATMEL_PMECC_SR			0x018	/* PMECC status register */
++#define		PMECC_SR_BUSY			(1 << 0)
++#define		PMECC_SR_ENABLE			(1 << 4)
++
++#define ATMEL_PMECC_IER			0x01c	/* PMECC interrupt enable */
++#define		PMECC_IER_ENABLE		(1 << 0)
++#define ATMEL_PMECC_IDR			0x020	/* PMECC interrupt disable */
++#define		PMECC_IER_DISABLE		(1 << 0)
++#define ATMEL_PMECC_IMR			0x024	/* PMECC interrupt mask */
++#define		PMECC_IER_MASK			(1 << 0)
++#define ATMEL_PMECC_ISR			0x028	/* PMECC interrupt status */
++#define ATMEL_PMECC_ECCx		0x040	/* PMECC ECC x */
++#define ATMEL_PMECC_REMx		0x240	/* PMECC REM x */
++
++/* PMERRLOC Register Definitions */
++#define ATMEL_PMERRLOC_ELCFG		0x000	/* Error location config */
++#define		PMERRLOC_ELCFG_SECTOR_512	(0 << 0)
++#define		PMERRLOC_ELCFG_SECTOR_1024	(1 << 0)
++#define		PMERRLOC_ELCFG_NUM_ERRORS(n)	((n) << 16)
++
++#define ATMEL_PMERRLOC_ELPRIM		0x004	/* Error location primitive */
++#define ATMEL_PMERRLOC_ELEN		0x008	/* Error location enable */
++#define ATMEL_PMERRLOC_ELDIS		0x00c	/* Error location disable */
++#define		PMERRLOC_DISABLE		(1 << 0)
++
++#define ATMEL_PMERRLOC_ELSR		0x010	/* Error location status */
++#define		PMERRLOC_ELSR_BUSY		(1 << 0)
++#define ATMEL_PMERRLOC_ELIER		0x014	/* Error location int enable */
++#define ATMEL_PMERRLOC_ELIDR		0x018	/* Error location int disable */
++#define ATMEL_PMERRLOC_ELIMR		0x01c	/* Error location int mask */
++#define ATMEL_PMERRLOC_ELISR		0x020	/* Error location int status */
++#define		PMERRLOC_ERR_NUM_MASK		(0x1f << 8)
++#define		PMERRLOC_CALC_DONE		(1 << 0)
++#define ATMEL_PMERRLOC_SIGMAx		0x028	/* Error location SIGMA x */
++#define ATMEL_PMERRLOC_ELx		0x08c	/* Error location x */
++
++/* Galois field dimension */
++#define GF_DIMENSION_13			13
++#define GF_DIMENSION_14			14
++
++#define PMECC_LOOKUP_TABLE_SIZE_512	0x2000
++#define PMECC_LOOKUP_TABLE_SIZE_1024	0x4000
++
++#define PMECC_LOOKUP_TABLE_OFFSET_512	0x8000
++#define PMECC_LOOKUP_TABLE_OFFSET_1024	0x10000
++
+ #endif
+diff --git a/drivers/mtd/nand/atmel_nand_pmecc.c b/drivers/mtd/nand/atmel_nand_pmecc.c
+new file mode 100644
+index 0000000..3230666
+--- /dev/null
++++ b/drivers/mtd/nand/atmel_nand_pmecc.c
+@@ -0,0 +1,674 @@
++/*
++ * (C) Copyright 2011 ATMEL, Hong Xu
++ *
++ * PMECC related definitions and routines
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++static struct nand_ecclayout pmecc_oobinfo_2048 = {
++	.eccbytes = 16,
++	.eccpos = { 48, 49, 50, 51, 52, 53, 54, 55,
++		    56, 57, 58, 59, 60, 61, 62, 63
++		  },
++	.oobfree = {
++		{2, 46},
++	},
++};
++
++static int cpu_has_pmecc(void)
++{
++	return cpu_is_at91sam9x5();
++}
++
++static int16_t *pmecc_get_alpha_to(struct atmel_nand_host *host)
++{
++	int16_t *p;
++
++	if (cpu_is_at91sam9x5()) {
++		if (host->sector_size == 512) {
++			p = (int16_t *)((u32)host->rom_base +
++				PMECC_LOOKUP_TABLE_OFFSET_512);
++			return p + PMECC_LOOKUP_TABLE_SIZE_512;
++		} else {
++			p = (int16_t *)((u32)host->rom_base +
++				PMECC_LOOKUP_TABLE_OFFSET_1024);
++			return p + PMECC_LOOKUP_TABLE_SIZE_1024;
++		}
++	}
++
++	return NULL;
++}
++
++static int16_t *pmecc_get_index_of(struct atmel_nand_host *host)
++{
++	int16_t *p = (int16_t *)host->rom_base;
++
++	if (cpu_is_at91sam9x5()) {
++		if (host->sector_size == 512)
++			p = (int16_t *)((u32)host->rom_base +
++				PMECC_LOOKUP_TABLE_OFFSET_512);
++		else
++			p = (int16_t *)((u32)host->rom_base +
++				PMECC_LOOKUP_TABLE_OFFSET_1024);
++
++		return p;
++	}
++
++	return NULL;
++}
++
++static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
++{
++	int i;
++	uint32_t value;
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++
++	/* Fill odd syndromes */
++	for (i = 0; i < host->tt; i++) {
++		value = pmecc_readl_rem(host->ecc, sector, i / 2);
++		if (i % 2 == 0)
++			host->partial_syn[(2 * i) + 1] = value & 0xffff;
++		else
++			host->partial_syn[(2 * i) + 1] = (value & 0xffff0000)
++							  >> 16;
++	}
++}
++
++static void pmecc_substitute(struct mtd_info *mtd)
++{
++	int i, j;
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++	int16_t *si;
++	int16_t *partial_syn = host->partial_syn;
++	int16_t *alpha_to = host->alpha_to;
++	int16_t *index_of = host->index_of;
++
++	/* si[] is a table that holds the current syndrome value,
++	 * an element of that table belongs to the field
++	 */
++	si = host->si;
++
++	for (i = 1; i < 2 * NB_ERROR_MAX; i++)
++		si[i] = 0;
++
++	/* Computation 2t syndromes based on S(x) */
++	/* Odd syndromes */
++	for (i = 1; i <= 2 * host->tt - 1; i = i + 2) {
++		si[i] = 0;
++		for (j = 0; j < host->mm; j++) {
++			if (partial_syn[i] & ((unsigned short)0x1 << j))
++				si[i] = alpha_to[(i * j)] ^ si[i];
++		}
++	}
++	/* Even syndrome = (Odd syndrome) ** 2 */
++	for (i = 2; i <= 2 * host->tt; i = i + 2) {
++		j = i / 2;
++		if (si[j] == 0)
++			si[i] = 0;
++		else
++			si[i] = alpha_to[(2 * index_of[si[j]]) % host->nn];
++	}
++
++	return;
++}
++
++static void pmecc_get_sigma(struct mtd_info *mtd)
++{
++	int i, j, k;
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++	uint32_t dmu_0_count, tmp;
++	int16_t *lmu = host->lmu;
++	int16_t *si = host->si;
++	int16_t tt = host->tt;
++	int16_t *index_of = host->index_of;
++
++	/* mu          */
++	int mu[NB_ERROR_MAX + 1];
++
++	/* discrepancy */
++	int dmu[NB_ERROR_MAX + 1];
++
++	/* delta order   */
++	int delta[NB_ERROR_MAX + 1];
++
++	/* index of largest delta */
++	int ro;
++	int largest;
++	int diff;
++
++	dmu_0_count = 0;
++
++	/* First Row */
++
++	/* Mu */
++	mu[0] = -1;
++
++	/* Actually -1/2 */
++	/* Sigma(x) set to 1 */
++	for (i = 0; i < 2 * NB_ERROR_MAX + 1; i++)
++		host->smu[0][i] = 0;
++
++	host->smu[0][0] = 1;
++
++	/* discrepancy set to 1 */
++	dmu[0] = 1;
++	/* polynom order set to 0 */
++	lmu[0] = 0;
++	/* delta set to -1 */
++	delta[0]  = (mu[0] * 2 - lmu[0]) >> 1;
++
++	/* Second Row */
++
++	/* Mu */
++	mu[1]  = 0;
++	/* Sigma(x) set to 1 */
++	for (i = 0; i < (2 * NB_ERROR_MAX + 1); i++)
++		host->smu[1][i] = 0;
++
++	host->smu[1][0] = 1;
++
++	/* discrepancy set to S1 */
++	dmu[1] = si[1];
++
++	/* polynom order set to 0 */
++	lmu[1] = 0;
++
++	/* delta set to 0 */
++	delta[1]  = (mu[1] * 2 - lmu[1]) >> 1;
++
++	/* Init the Sigma(x) last row */
++	for (i = 0; i < (2 * NB_ERROR_MAX + 1); i++)
++		host->smu[tt + 1][i] = 0;
++
++	for (i = 1; i <= tt; i++) {
++		mu[i+1] = i << 1;
++		/* Begin Computing Sigma (Mu+1) and L(mu) */
++		/* check if discrepancy is set to 0 */
++		if (dmu[i] == 0) {
++			dmu_0_count++;
++
++			if ((tt - (lmu[i] >> 1) - 1) & 0x1)
++				tmp = ((tt - (lmu[i] >> 1) - 1) / 2) + 2;
++			else
++				tmp = ((tt - (lmu[i] >> 1) - 1) / 2) + 1;
++
++			if (dmu_0_count == tmp) {
++				for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
++					host->smu[tt + 1][j] = host->smu[i][j];
++
++				lmu[tt + 1] = lmu[i];
++				return;
++			}
++
++			/* copy polynom */
++			for (j = 0; j <= lmu[i] >> 1; j++)
++				host->smu[i + 1][j] = host->smu[i][j];
++
++			/* copy previous polynom order to the next */
++			lmu[i + 1] = lmu[i];
++		} else {
++			ro = 0;
++			largest = -1;
++			/* find largest delta with dmu != 0 */
++			for (j = 0; j < i; j++) {
++				if ((dmu[j]) && (delta[j] > largest)) {
++					largest = delta[j];
++					ro = j;
++				}
++			}
++
++			/* compute difference */
++			diff = (mu[i] - mu[ro]);
++
++			/* Compute degree of the new smu polynomial */
++			if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
++				lmu[i + 1] = lmu[i];
++			else
++				lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
++
++			/* Init smu[i+1] with 0 */
++			for (k = 0; k < (2 * NB_ERROR_MAX + 1); k++)
++				host->smu[i+1][k] = 0;
++
++			/* Compute smu[i+1] */
++			for (k = 0; k <= lmu[ro] >> 1; k++) {
++				if (!(host->smu[ro][k] && dmu[i]))
++					continue;
++
++				tmp = host->index_of[dmu[i]] + (host->nn -
++				       host->index_of[dmu[ro]]) +
++				      host->index_of[host->smu[ro][k]];
++				host->smu[i + 1][k + diff] =
++					host->alpha_to[tmp % host->nn];
++			}
++
++			for (k = 0; k <= lmu[i] >> 1; k++)
++				host->smu[i + 1][k] ^= host->smu[i][k];
++		}
++
++		/* End Computing Sigma (Mu+1) and L(mu) */
++		/* In either case compute delta */
++		delta[i + 1]  = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
++
++		/* Do not compute discrepancy for the last iteration */
++		if (i >= tt)
++			continue;
++
++		for (k = 0 ; k <= (lmu[i + 1] >> 1); k++) {
++			tmp = 2 * (i - 1);
++			if (k == 0)
++				dmu[i + 1] = si[tmp + 3];
++			else if (host->smu[i+1][k] && si[tmp + 3 - k]) {
++				tmp = index_of[host->smu[i + 1][k]] +
++				      index_of[si[2 * (i - 1) + 3 - k]];
++				tmp %= host->nn;
++				dmu[i + 1] = host->alpha_to[tmp] ^ dmu[i + 1];
++			}
++		}
++	}
++
++	return;
++}
++
++
++static int pmecc_err_location(struct mtd_info *mtd)
++{
++	int i;
++	/* number of error */
++	int err_nbr;
++	/* number of roots */
++	int roots_nbr;
++	int gf_dimension;
++	uint32_t val;
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++
++	if (host->sector_size == 512)
++		gf_dimension = GF_DIMENSION_13;
++	else
++		gf_dimension = GF_DIMENSION_14;
++
++	/* Disable PMECC Error Location IP */
++	pmerrloc_writel(host->pmerrloc_base, ELDIS, 0xffffffff);
++	err_nbr = 0;
++
++	for (i = 0; i <= host->lmu[host->tt + 1] >> 1; i++) {
++		pmerrloc_writel_sigma(host->pmerrloc_base, i,
++				      host->smu[host->tt + 1][i]);
++		err_nbr++;
++	}
++
++	val = pmerrloc_readl(host->pmerrloc_base, ELCFG);
++	val |= ((err_nbr - 1) << 16);
++	pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
++
++	pmerrloc_writel(host->pmerrloc_base, ELEN,
++			host->sector_size * 8 + gf_dimension * host->tt);
++
++	while (!(pmerrloc_readl(host->pmerrloc_base, ELISR)
++		 & PMERRLOC_CALC_DONE))
++		cpu_relax();
++
++	roots_nbr = (pmerrloc_readl(host->pmerrloc_base, ELISR)
++		      & PMERRLOC_ERR_NUM_MASK) >> 8;
++
++	/* Number of roots == degree of smu hence <= tt */
++	if (roots_nbr == host->lmu[host->tt + 1] >> 1)
++		return err_nbr - 1;
++
++	/* Number of roots does not match the degree of smu
++	 * unable to correct error */
++	return -1;
++}
++
++static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf,
++		int extra_bytes, int err_nbr)
++{
++	int i = 0;
++	int byte_pos, bit_pos;
++	int sector_size, ecc_size;
++	uint32_t tmp;
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++
++	sector_size = host->sector_size;
++	/* Get number of ECC bytes */
++	ecc_size = nand_chip->ecc.bytes;
++
++	while (err_nbr) {
++		byte_pos = (pmerrloc_readl_el(host->pmerrloc_base, i) - 1) / 8;
++		bit_pos = (pmerrloc_readl_el(host->pmerrloc_base, i) - 1) % 8;
++		dev_dbg(host->dev, "bad : %02x: byte_pos: %d, bit_pos: %d\n",
++			*(buf + byte_pos), byte_pos, bit_pos);
++
++		if (byte_pos < (sector_size + extra_bytes)) {
++			tmp = sector_size + pmecc_readl(host->ecc, SADDR);
++			if (byte_pos < tmp) {
++				if (*(buf + byte_pos) & (1 << bit_pos))
++					*(buf + byte_pos) &=
++						(0xFF ^ (1 << bit_pos));
++				else
++					*(buf + byte_pos) |= (1 << bit_pos);
++			} else {
++				if (*(buf + byte_pos + ecc_size) &
++				     (1 << bit_pos))
++					*(buf + byte_pos + ecc_size) &=
++						(0xFF ^ (1 << bit_pos));
++				else
++					*(buf + byte_pos + ecc_size) |=
++						(1 << bit_pos);
++			}
++		}
++		dev_dbg(host->dev, "corr: %02x\n", *(buf + byte_pos));
++		i++;
++		err_nbr--;
++	}
++
++	return;
++}
++
++static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
++	u8 *ecc)
++{
++	int i, err_nbr;
++	uint8_t *buf_pos;
++	struct nand_chip *nand_chip = mtd->priv;
++	int eccbytes = nand_chip->ecc.bytes;
++	struct atmel_nand_host *host = nand_chip->priv;
++
++	for (i = 0; i < eccbytes; i++)
++		if (ecc[i] != 0xff)
++			break;
++	/* Erased page, return OK */
++	if (i == eccbytes)
++		return 0;
++
++	pmerrloc_writel(host->pmerrloc_base, ELCFG,
++			(host->sector_size == 512) ? 0 : 1);
++
++	i = 0;
++	while (i < host->sector_number) {
++		err_nbr = 0;
++		if (pmecc_stat & 0x1) {
++			buf_pos = buf + i * host->sector_size;
++
++			pmecc_gen_syndrome(mtd, i);
++			pmecc_substitute(mtd);
++			pmecc_get_sigma(mtd);
++
++			err_nbr = pmecc_err_location(mtd);
++			if (err_nbr == -1) {
++				dev_err(host->dev, "Too many error.\n");
++				mtd->ecc_stats.failed++;
++				return -EFAULT;
++			} else {
++				dev_dbg(host->dev,  "Correct bits...\n");
++				pmecc_correct_data(mtd, buf_pos, 0, err_nbr);
++				mtd->ecc_stats.corrected += err_nbr;
++			}
++		}
++		i++;
++		pmecc_stat >>= 1;
++	}
++
++	return 0;
++}
++
++static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
++		struct nand_chip *chip, uint8_t *buf, int32_t page)
++{
++	struct atmel_nand_host *host = chip->priv;
++	int eccsize = chip->ecc.size;
++	uint32_t *eccpos = chip->ecc.layout->eccpos;
++	int err = 0, stat;
++	int timeout = 10;
++	uint8_t *oob = chip->oob_poi;
++
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
++	pmecc_writel(host->ecc, CFG, (pmecc_readl(host->ecc, CFG)
++		     & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
++
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
++
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
++
++	chip->read_buf(mtd, buf, eccsize);
++	chip->read_buf(mtd, oob, mtd->oobsize);
++
++	while ((pmecc_readl(host->ecc, SR) & PMECC_SR_BUSY) && (timeout-- > 0))
++		cpu_relax();
++
++	stat = pmecc_readl(host->ecc, ISR);
++
++	if (stat != 0) {
++		if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]))
++			err = -1;
++	}
++
++	return err;
++}
++
++static void atmel_nand_pmecc_write_page(struct mtd_info *mtd,
++		struct nand_chip *chip, const uint8_t *buf)
++{
++	int i, j;
++	int timeout = 10;
++	struct atmel_nand_host *host = chip->priv;
++	uint32_t *eccpos = chip->ecc.layout->eccpos;
++
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
++
++	pmecc_writel(host->ecc, CFG, (pmecc_readl(host->ecc, CFG) |
++		PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
++
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
++
++	chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
++
++	while ((pmecc_readl(host->ecc, SR) & PMECC_SR_BUSY) && (timeout-- > 0))
++		cpu_relax();
++
++	for (i = 0; i < host->sector_number; i++) {
++		for (j = 0; j < host->ecc_bytes_per_sector; j++) {
++			int pos;
++
++			pos = i * host->ecc_bytes_per_sector + j;
++			chip->oob_poi[eccpos[pos]] =
++				pmecc_readb_ecc(host->ecc, i, j);
++		}
++	}
++	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
++
++	return;
++}
++
++static void atmel_init_pmecc(struct mtd_info *mtd)
++{
++	uint32_t val;
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++	struct nand_ecclayout *ecc_layout;
++
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
++
++	switch (host->tt) {
++	case 2:
++		val = PMECC_CFG_BCH_ERR2;
++		break;
++	case 4:
++		val = PMECC_CFG_BCH_ERR4;
++		break;
++	case 8:
++		val = PMECC_CFG_BCH_ERR8;
++		break;
++	case 12:
++		val = PMECC_CFG_BCH_ERR12;
++		break;
++	case 24:
++		val = PMECC_CFG_BCH_ERR24;
++		break;
++	}
++
++	if (host->sector_size == 512)
++		val |= PMECC_CFG_SECTOR512;
++	else if (host->sector_size == 1024)
++		val |= PMECC_CFG_SECTOR1024;
++
++	switch (host->sector_number) {
++	case 1:
++		val |= PMECC_CFG_PAGE_1SECTOR;
++		break;
++	case 2:
++		val |= PMECC_CFG_PAGE_2SECTORS;
++		break;
++	case 4:
++		val |= PMECC_CFG_PAGE_4SECTORS;
++		break;
++	case 8:
++		val |= PMECC_CFG_PAGE_8SECTORS;
++		break;
++	}
++
++	val |= PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
++		| PMECC_CFG_AUTO_DISABLE;
++	pmecc_writel(host->ecc, CFG, val);
++
++	ecc_layout = nand_chip->ecc.layout;
++	pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
++	pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
++	pmecc_writel(host->ecc, EADDR,
++			ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
++	pmecc_writel(host->ecc, CLK, PMECC_CLK_133MHZ);
++	pmecc_writel(host->ecc, IDR, 0xff);
++
++	val = pmecc_readl(host->ecc, CTRL);
++	val |= PMECC_CTRL_ENABLE;
++	pmecc_writel(host->ecc, CTRL, val);
++}
++
++static int __init atmel_pmecc_init_params(struct platform_device *pdev,
++					 struct atmel_nand_host *host)
++{
++	struct resource *regs;
++	struct resource *regs_pmerr, *regs_rom;
++	struct nand_chip *nand_chip;
++	struct mtd_info *mtd;
++	int res;
++
++	printk(KERN_ERR "atmel_pmecc_init_params\n");
++
++	nand_chip = &host->nand_chip;
++	mtd = &host->mtd;
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	if (!regs && hard_ecc) {
++		dev_warn(host->dev, "Can't get I/O resource regs\nFalling "
++				"back on software ECC\n");
++	}
++
++	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
++	if (no_ecc)
++		nand_chip->ecc.mode = NAND_ECC_NONE;
++	if (hard_ecc && regs) {
++		host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
++		if (host->ecc == NULL) {
++			printk(KERN_ERR "atmel_nand: ioremap failed\n");
++			res = -EIO;
++			goto err_pmecc_ioremap;
++		}
++
++		regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM,
++						   2);
++		regs_rom = platform_get_resource(pdev, IORESOURCE_MEM,
++						 3);
++		if (regs_pmerr && regs_rom) {
++			host->pmerrloc_base = ioremap(regs_pmerr->start,
++			regs_pmerr->end - regs_pmerr->start + 1);
++			host->rom_base = ioremap(regs_rom->start,
++				regs_rom->end - regs_rom->start + 1);
++
++			if (host->pmerrloc_base && host->rom_base) {
++				nand_chip->ecc.mode = NAND_ECC_HW;
++				nand_chip->ecc.read_page =
++					atmel_nand_pmecc_read_page;
++				nand_chip->ecc.write_page =
++					atmel_nand_pmecc_write_page;
++			} else {
++				dev_err(host->dev, "Can not get I/O resource"
++				" for HW PMECC controller!\n");
++				goto err_pmloc_remap;
++			}
++		}
++
++		if (nand_chip->ecc.mode != NAND_ECC_HW)
++			printk(KERN_ERR "atmel_nand: Can not get I/O resource"
++				" for HW ECC Rolling back to software ECC\n");
++	}
++
++	if (nand_chip->ecc.mode == NAND_ECC_HW) {
++		/* ECC is calculated for the whole page (1 step) */
++		nand_chip->ecc.size = mtd->writesize;
++
++		/* set ECC page size and oob layout */
++		switch (mtd->writesize) {
++		case 2048:
++			nand_chip->ecc.bytes = 16;
++			nand_chip->ecc.steps = 1;
++			nand_chip->ecc.layout = &pmecc_oobinfo_2048;
++			host->mm = GF_DIMENSION_13;
++			host->nn = (1 << host->mm) - 1;
++			/* 2-bits correction */
++			host->tt = 2;
++			host->sector_size = 512;
++			host->sector_number = mtd->writesize /
++					      host->sector_size;
++			host->ecc_bytes_per_sector = 4;
++			host->alpha_to = pmecc_get_alpha_to(host);
++			host->index_of = pmecc_get_index_of(host);
++			break;
++		case 512:
++		case 1024:
++		case 4096:
++			/* TODO */
++			dev_warn(host->dev, "Only 2048 page size is currently"
++				"supported, Rolling back to software ECC\n");
++		default:
++			/* page size not handled by HW ECC */
++			/* switching back to soft ECC */
++			nand_chip->ecc.mode = NAND_ECC_SOFT;
++			nand_chip->ecc.calculate = NULL;
++			nand_chip->ecc.correct = NULL;
++			nand_chip->ecc.hwctl = NULL;
++			nand_chip->ecc.read_page = NULL;
++			nand_chip->ecc.postpad = 0;
++			nand_chip->ecc.prepad = 0;
++			nand_chip->ecc.bytes = 0;
++			break;
++		}
++	}
++
++	/* Initialize PMECC core if applicable */
++	if ((nand_chip->ecc.mode == NAND_ECC_HW) && cpu_has_pmecc())
++		atmel_init_pmecc(mtd);
++
++	return 0;
++err_pmloc_remap:
++	iounmap(host->ecc);
++	if (host->pmerrloc_base)
++		iounmap(host->pmerrloc_base);
++	if (host->rom_base)
++		iounmap(host->rom_base);
++err_pmecc_ioremap:
++	return -EIO;
++}
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0027-MTD-atmel_nand-optimize-read-write-buffer-functions.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0027-MTD-atmel_nand-optimize-read-write-buffer-functions.patch
new file mode 100644
index 0000000..c8d8232
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0027-MTD-atmel_nand-optimize-read-write-buffer-functions.patch
@@ -0,0 +1,130 @@
+From 6ddc4f41327a2782c63817dc8b94dd92edad8352 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Wed, 16 Feb 2011 18:43:37 +0100
+Subject: [PATCH 027/107] MTD: atmel_nand: optimize read/write buffer
+ functions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+For PIO NAND access functions, we use the features of the SMC:
+- no need to take into account the NAND bus width: SMC will deal with this
+- an word aligned memcpy on the NAND chip-select space is able to generate
+  proper SMC behavior while optimizing AHB bus usage thanks to optimized memcpy
+  implementation.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/mtd/nand/atmel_nand.c |   71 +++++++++++++++++-----------------------
+ 1 files changed, 30 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index 2145c6e..e89c8c7 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -230,37 +230,6 @@ static int atmel_nand_device_ready(struct mtd_info *mtd)
+                 !!host->board->rdy_pin_active_low;
+ }
+ 
+-/*
+- * Minimal-overhead PIO for data access.
+- */
+-static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
+-{
+-	struct nand_chip	*nand_chip = mtd->priv;
+-
+-	__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
+-}
+-
+-static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
+-{
+-	struct nand_chip	*nand_chip = mtd->priv;
+-
+-	__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
+-}
+-
+-static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
+-{
+-	struct nand_chip	*nand_chip = mtd->priv;
+-
+-	__raw_writesb(nand_chip->IO_ADDR_W, buf, len);
+-}
+-
+-static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
+-{
+-	struct nand_chip	*nand_chip = mtd->priv;
+-
+-	__raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
+-}
+-
+ static void dma_complete_func(void *completion)
+ {
+ 	complete(completion);
+@@ -335,33 +304,53 @@ err_buf:
+ static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+ {
+ 	struct nand_chip *chip = mtd->priv;
+-	struct atmel_nand_host *host = chip->priv;
++	u32 align;
++	u8 *pbuf;
+ 
+ 	if (use_dma && len > mtd->oobsize)
+ 		/* only use DMA for bigger than oob size: better performances */
+ 		if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
+ 			return;
+ 
+-	if (host->board->bus_width_16)
+-		atmel_read_buf16(mtd, buf, len);
+-	else
+-		atmel_read_buf8(mtd, buf, len);
++	/* if no DMA operation possible, use PIO */
++	pbuf = buf;
++	align = 0x03 & ((unsigned)pbuf);
++
++	if (align) {
++		u32 align_len = 4 - align;
++
++		/* non aligned buffer: re-align to next word boundary */
++		ioread8_rep(chip->IO_ADDR_R, pbuf, align_len);
++		pbuf += align_len;
++		len -= align_len;
++	}
++	memcpy((void *)pbuf, chip->IO_ADDR_R, len);
+ }
+ 
+ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+ {
+ 	struct nand_chip *chip = mtd->priv;
+-	struct atmel_nand_host *host = chip->priv;
++	u32 align;
++	const u8 *pbuf;
+ 
+ 	if (use_dma && len > mtd->oobsize)
+ 		/* only use DMA for bigger than oob size: better performances */
+ 		if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
+ 			return;
+ 
+-	if (host->board->bus_width_16)
+-		atmel_write_buf16(mtd, buf, len);
+-	else
+-		atmel_write_buf8(mtd, buf, len);
++	/* if no DMA operation possible, use PIO */
++	pbuf = buf;
++	align = 0x03 & ((unsigned)pbuf);
++
++	if (align) {
++		u32 align_len = 4 - align;
++
++		/* non aligned buffer: re-align to next word boundary */
++		iowrite8_rep(chip->IO_ADDR_W, pbuf, align_len);
++		pbuf += align_len;
++		len -= align_len;
++	}
++	memcpy(chip->IO_ADDR_W, (void *)pbuf, len);
+ }
+ 
+ #if defined(CONFIG_MTD_NAND_ATMEL_ECC_HW)
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0028-spi-atmel_spi-trivial-change-some-comments.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0028-spi-atmel_spi-trivial-change-some-comments.patch
new file mode 100644
index 0000000..8f41ddb
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0028-spi-atmel_spi-trivial-change-some-comments.patch
@@ -0,0 +1,40 @@
+From 1d7219fce90e166edfd523cdd081753d55117baa Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Wed, 16 Mar 2011 10:55:39 +0800
+Subject: [PATCH 028/107] spi/atmel_spi: trivial: change some comments
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+To be accurate with introduction of dmaengine enabled driver.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/spi/atmel_spi.c |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
+index 1a478bf..033aa52 100644
+--- a/drivers/spi/atmel_spi.c
++++ b/drivers/spi/atmel_spi.c
+@@ -48,6 +48,7 @@ struct atmel_spi {
+ 	struct spi_transfer	*next_transfer;
+ 	unsigned long		next_remaining_bytes;
+ 
++	/* scratch buffer */
+ 	void			*buffer;
+ 	dma_addr_t		buffer_dma;
+ };
+@@ -211,7 +212,7 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
+ }
+ 
+ /*
+- * Submit next transfer for DMA.
++ * Submit next transfer for PDC.
+  * lock is held, spi irq is blocked
+  */
+ static void atmel_spi_next_xfer(struct spi_master *master,
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0029-spi-atmel_spi-add-physical-base-address.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0029-spi-atmel_spi-add-physical-base-address.patch
new file mode 100644
index 0000000..33531dc
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0029-spi-atmel_spi-add-physical-base-address.patch
@@ -0,0 +1,39 @@
+From c49c24fe68646dd74999a52fce7e6d0f32912033 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Wed, 16 Mar 2011 10:50:13 +0800
+Subject: [PATCH 029/107] spi/atmel_spi: add physical base address
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Needed for future use with dmaengine enabled driver.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/spi/atmel_spi.c |    2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
+index 033aa52..c7967c8 100644
+--- a/drivers/spi/atmel_spi.c
++++ b/drivers/spi/atmel_spi.c
+@@ -35,6 +35,7 @@
+ struct atmel_spi {
+ 	spinlock_t		lock;
+ 
++	resource_size_t		phybase;
+ 	void __iomem		*regs;
+ 	int			irq;
+ 	struct clk		*clk;
+@@ -809,6 +810,7 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
+ 	as->regs = ioremap(regs->start, resource_size(regs));
+ 	if (!as->regs)
+ 		goto out_free_buffer;
++	as->phybase = regs->start;
+ 	as->irq = irq;
+ 	as->clk = clk;
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0030-spi-atmel_spi-call-unmapping-on-transfers-buffers.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0030-spi-atmel_spi-call-unmapping-on-transfers-buffers.patch
new file mode 100644
index 0000000..753115f
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0030-spi-atmel_spi-call-unmapping-on-transfers-buffers.patch
@@ -0,0 +1,43 @@
+From 899a00e7d9329dd469569b5270cce53fee85ea73 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Wed, 16 Mar 2011 10:51:31 +0800
+Subject: [PATCH 030/107] spi/atmel_spi: call unmapping on transfers buffers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/spi/atmel_spi.c |    8 +++++---
+ 1 files changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
+index c7967c8..add1f2b 100644
+--- a/drivers/spi/atmel_spi.c
++++ b/drivers/spi/atmel_spi.c
+@@ -858,6 +858,7 @@ static int __exit atmel_spi_remove(struct platform_device *pdev)
+ 	struct spi_master	*master = platform_get_drvdata(pdev);
+ 	struct atmel_spi	*as = spi_master_get_devdata(master);
+ 	struct spi_message	*msg;
++	struct spi_transfer	*xfer;
+ 
+ 	/* reset the hardware and block queue progress */
+ 	spin_lock_irq(&as->lock);
+@@ -869,9 +870,10 @@ static int __exit atmel_spi_remove(struct platform_device *pdev)
+ 
+ 	/* Terminate remaining queued transfers */
+ 	list_for_each_entry(msg, &as->queue, queue) {
+-		/* REVISIT unmapping the dma is a NOP on ARM and AVR32
+-		 * but we shouldn't depend on that...
+-		 */
++		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++			if (!msg->is_dma_mapped)
++				atmel_spi_dma_unmap_xfer(master, xfer);
++		}
+ 		msg->status = -ESHUTDOWN;
+ 		msg->complete(msg->context);
+ 	}
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0031-spi-atmel_spi-status-information-passed-through-cont.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0031-spi-atmel_spi-status-information-passed-through-cont.patch
new file mode 100644
index 0000000..aa83190
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0031-spi-atmel_spi-status-information-passed-through-cont.patch
@@ -0,0 +1,80 @@
+From f048800de322b4cf93a4c9f1c493875c1105308e Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Wed, 16 Mar 2011 11:29:12 +0800
+Subject: [PATCH 031/107] spi/atmel_spi: status information passed through
+ controller data
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The status of transfer is stored in controller data structure
+so that it can be used not only by atmel_spi_msg_done() function.
+This will be useful for upcoming dmaengine enabled driver.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/spi/atmel_spi.c |   13 ++++++++-----
+ 1 files changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
+index add1f2b..f5e7f84 100644
+--- a/drivers/spi/atmel_spi.c
++++ b/drivers/spi/atmel_spi.c
+@@ -48,6 +48,7 @@ struct atmel_spi {
+ 	unsigned long		current_remaining_bytes;
+ 	struct spi_transfer	*next_transfer;
+ 	unsigned long		next_remaining_bytes;
++	int			done_status;
+ 
+ 	/* scratch buffer */
+ 	void			*buffer;
+@@ -392,15 +393,15 @@ static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
+ 
+ static void
+ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
+-		struct spi_message *msg, int status, int stay)
++		struct spi_message *msg, int stay)
+ {
+-	if (!stay || status < 0)
++	if (!stay || as->done_status < 0)
+ 		cs_deactivate(as, msg->spi);
+ 	else
+ 		as->stay = msg->spi;
+ 
+ 	list_del(&msg->queue);
+-	msg->status = status;
++	msg->status = as->done_status;
+ 
+ 	dev_dbg(master->dev.parent,
+ 		"xfer complete: %u bytes transferred\n",
+@@ -412,6 +413,7 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
+ 
+ 	as->current_transfer = NULL;
+ 	as->next_transfer = NULL;
++	as->done_status = 0;
+ 
+ 	/* continue if needed */
+ 	if (list_empty(&as->queue) || as->stopping)
+@@ -489,7 +491,8 @@ atmel_spi_interrupt(int irq, void *dev_id)
+ 		/* Clear any overrun happening while cleaning up */
+ 		spi_readl(as, SR);
+ 
+-		atmel_spi_msg_done(master, as, msg, -EIO, 0);
++		as->done_status = -EIO;
++		atmel_spi_msg_done(master, as, msg, 0);
+ 	} else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
+ 		ret = IRQ_HANDLED;
+ 
+@@ -507,7 +510,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
+ 
+ 			if (atmel_spi_xfer_is_last(msg, xfer)) {
+ 				/* report completed message */
+-				atmel_spi_msg_done(master, as, msg, 0,
++				atmel_spi_msg_done(master, as, msg,
+ 						xfer->cs_change);
+ 			} else {
+ 				if (xfer->cs_change) {
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0032-spi-atmel_spi-add-flag-to-controller-data-for-lock-o.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0032-spi-atmel_spi-add-flag-to-controller-data-for-lock-o.patch
new file mode 100644
index 0000000..fbec5a8
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0032-spi-atmel_spi-add-flag-to-controller-data-for-lock-o.patch
@@ -0,0 +1,119 @@
+From 432d1ee3fc28e73e3ef4ddebd1ced25c5d88dfa3 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Wed, 16 Mar 2011 13:42:40 +0800
+Subject: [PATCH 032/107] spi/atmel_spi: add flag to controller data for lock
+ operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Will allow to drop the lock during DMA operations.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/spi/atmel_spi.c |   31 +++++++++++++++++++------------
+ 1 files changed, 19 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
+index f5e7f84..31293f6 100644
+--- a/drivers/spi/atmel_spi.c
++++ b/drivers/spi/atmel_spi.c
+@@ -34,6 +34,7 @@
+  */
+ struct atmel_spi {
+ 	spinlock_t		lock;
++	unsigned long		flags;
+ 
+ 	resource_size_t		phybase;
+ 	void __iomem		*regs;
+@@ -171,6 +172,16 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
+ 		gpio_set_value(asd->npcs_pin, !active);
+ }
+ 
++static void atmel_spi_lock(struct atmel_spi *as)
++{
++		spin_lock_irqsave(&as->lock, as->flags);
++}
++
++static void atmel_spi_unlock(struct atmel_spi *as)
++{
++		spin_unlock_irqrestore(&as->lock, as->flags);
++}
++
+ static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
+ 					struct spi_transfer *xfer)
+ {
+@@ -407,9 +418,9 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
+ 		"xfer complete: %u bytes transferred\n",
+ 		msg->actual_length);
+ 
+-	spin_unlock(&as->lock);
++	atmel_spi_unlock(as);
+ 	msg->complete(msg->context);
+-	spin_lock(&as->lock);
++	atmel_spi_lock(as);
+ 
+ 	as->current_transfer = NULL;
+ 	as->next_transfer = NULL;
+@@ -636,13 +647,11 @@ static int atmel_spi_setup(struct spi_device *spi)
+ 		spi->controller_state = asd;
+ 		gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
+ 	} else {
+-		unsigned long		flags;
+-
+-		spin_lock_irqsave(&as->lock, flags);
++		atmel_spi_lock(as);
+ 		if (as->stay == spi)
+ 			as->stay = NULL;
+ 		cs_deactivate(as, spi);
+-		spin_unlock_irqrestore(&as->lock, flags);
++		atmel_spi_unlock(as);
+ 	}
+ 
+ 	asd->csr = csr;
+@@ -661,7 +670,6 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
+ {
+ 	struct atmel_spi	*as;
+ 	struct spi_transfer	*xfer;
+-	unsigned long		flags;
+ 	struct device		*controller = spi->master->dev.parent;
+ 	u8			bits;
+ 	struct atmel_spi_device	*asd;
+@@ -726,11 +734,11 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
+ 	msg->status = -EINPROGRESS;
+ 	msg->actual_length = 0;
+ 
+-	spin_lock_irqsave(&as->lock, flags);
++	atmel_spi_lock(as);
+ 	list_add_tail(&msg->queue, &as->queue);
+ 	if (!as->current_transfer)
+ 		atmel_spi_next_message(spi->master);
+-	spin_unlock_irqrestore(&as->lock, flags);
++	atmel_spi_unlock(as);
+ 
+ 	return 0;
+ }
+@@ -740,17 +748,16 @@ static void atmel_spi_cleanup(struct spi_device *spi)
+ 	struct atmel_spi	*as = spi_master_get_devdata(spi->master);
+ 	struct atmel_spi_device	*asd = spi->controller_state;
+ 	unsigned		gpio = (unsigned) spi->controller_data;
+-	unsigned long		flags;
+ 
+ 	if (!asd)
+ 		return;
+ 
+-	spin_lock_irqsave(&as->lock, flags);
++	atmel_spi_lock(as);
+ 	if (as->stay == spi) {
+ 		as->stay = NULL;
+ 		cs_deactivate(as, spi);
+ 	}
+-	spin_unlock_irqrestore(&as->lock, flags);
++	atmel_spi_unlock(as);
+ 
+ 	spi->controller_state = NULL;
+ 	gpio_free(gpio);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0033-spi-atmel_spi-add-dmaengine-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0033-spi-atmel_spi-add-dmaengine-support.patch
new file mode 100644
index 0000000..016f511
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0033-spi-atmel_spi-add-dmaengine-support.patch
@@ -0,0 +1,654 @@
+From be84b03606698da41300ef1dec2e4584874d7f39 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Mon, 21 Mar 2011 17:35:44 +0800
+Subject: [PATCH 033/107] spi/atmel_spi: add dmaengine support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/spi/Kconfig     |    9 +
+ drivers/spi/atmel_spi.c |  483 ++++++++++++++++++++++++++++++++++++++++++++++-
+ 2 files changed, 482 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
+index fc14b8d..1080a0a 100644
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -74,6 +74,15 @@ config SPI_ATMEL
+ 	  This selects a driver for the Atmel SPI Controller, present on
+ 	  many AT32 (AVR32) and AT91 (ARM) chips.
+ 
++config SPI_ATMEL_DMA
++	bool "Atmel SPI DMA support"
++	depends on SPI_ATMEL && (ARCH_AT91SAM9G45 || ARCH_AT91SAM9X5) && DMA_ENGINE && EXPERIMENTAL
++	default y
++	help
++	  Say Y here if you want the Atmel SPI driver to use the DMA engine. Data transfers
++	  will be handled by the DMA controller: it will increase throughput and reduce
++	  CPU utilization.
++
+ config SPI_BFIN
+ 	tristate "SPI controller driver for ADI Blackfin5xx"
+ 	depends on BLACKFIN
+diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
+index 31293f6..12d8a81 100644
+--- a/drivers/spi/atmel_spi.c
++++ b/drivers/spi/atmel_spi.c
+@@ -15,6 +15,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/delay.h>
+ #include <linux/dma-mapping.h>
++#include <linux/dmaengine.h>
+ #include <linux/err.h>
+ #include <linux/interrupt.h>
+ #include <linux/spi/spi.h>
+@@ -24,9 +25,26 @@
+ #include <mach/board.h>
+ #include <mach/gpio.h>
+ #include <mach/cpu.h>
++#include <mach/at_hdmac.h>
+ 
+ #include "atmel_spi.h"
+ 
++#if defined(CONFIG_SPI_ATMEL_DMA)
++/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
++ * cache operations; better heuristics consider wordsize and bitrate.
++ */
++#define DMA_MIN_BYTES	16
++
++struct atmel_spi_dma {
++	struct dma_chan			*chan_rx;
++	struct dma_chan			*chan_tx;
++	struct scatterlist		sgrx;
++	struct scatterlist		sgtx;
++	struct dma_async_tx_descriptor	*data_desc_rx;
++	struct dma_async_tx_descriptor	*data_desc_tx;
++};
++#endif
++
+ /*
+  * The core SPI transfer engine just talks to a register bank to set up
+  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
+@@ -45,6 +63,7 @@ struct atmel_spi {
+ 
+ 	u8			stopping;
+ 	struct list_head	queue;
++	struct tasklet_struct	tasklet;
+ 	struct spi_transfer	*current_transfer;
+ 	unsigned long		current_remaining_bytes;
+ 	struct spi_transfer	*next_transfer;
+@@ -54,6 +73,11 @@ struct atmel_spi {
+ 	/* scratch buffer */
+ 	void			*buffer;
+ 	dma_addr_t		buffer_dma;
++
++#if defined(CONFIG_SPI_ATMEL_DMA)
++	/* dmaengine data */
++	struct atmel_spi_dma	dma;
++#endif
+ };
+ 
+ /* Controller-specific per-slave state */
+@@ -182,6 +206,17 @@ static void atmel_spi_unlock(struct atmel_spi *as)
+ 		spin_unlock_irqrestore(&as->lock, as->flags);
+ }
+ 
++static inline bool atmel_spi_use_dma(struct spi_transfer *xfer)
++{
++#if defined(CONFIG_SPI_ATMEL_DMA)
++	if (xfer->len < DMA_MIN_BYTES)
++		return false;
++	return true;
++#else
++	return false;
++#endif
++}
++
+ static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
+ 					struct spi_transfer *xfer)
+ {
+@@ -193,6 +228,258 @@ static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
+ 	return xfer->delay_usecs == 0 && !xfer->cs_change;
+ }
+ 
++#if defined(CONFIG_SPI_ATMEL_DMA)
++static bool __init filter(struct dma_chan *chan, void *slave)
++{
++	struct	at_dma_slave		*sl = slave;
++
++	if (sl->dma_dev == chan->device->dev) {
++		chan->private = sl;
++		return true;
++	} else {
++		return false;
++	}
++}
++
++static int __init atmel_spi_configure_dma(struct spi_master *master)
++{
++	struct atmel_spi	*as = spi_master_get_devdata(master);
++	struct device		*controller = master->dev.parent;
++	struct at_dma_slave	*sdata;
++
++	sdata = controller->platform_data;
++
++	if (sdata && sdata->dma_dev) {
++		dma_cap_mask_t mask;
++
++		/* setup DMA addresses */
++		sdata->rx_reg = (dma_addr_t)as->phybase + SPI_RDR;
++		sdata->tx_reg = (dma_addr_t)as->phybase + SPI_TDR;
++
++		/* Try to grab two DMA channels */
++		dma_cap_zero(mask);
++		dma_cap_set(DMA_SLAVE, mask);
++		as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
++		if (as->dma.chan_tx)
++			as->dma.chan_rx = dma_request_channel(mask, filter, sdata);
++	}
++	if (!as->dma.chan_rx || !as->dma.chan_tx) {
++		if (as->dma.chan_rx)
++			dma_release_channel(as->dma.chan_rx);
++		if (as->dma.chan_tx)
++			dma_release_channel(as->dma.chan_tx);
++		dev_err(&as->pdev->dev, "DMA channel not available, "
++					"unable to use SPI\n");
++		return -EBUSY;
++	}
++
++	dev_info(&as->pdev->dev, "Using %s (tx) and "
++				" %s (rx) for DMA transfers\n",
++				dma_chan_name(as->dma.chan_tx),
++				dma_chan_name(as->dma.chan_rx));
++
++	return 0;
++}
++
++static void atmel_spi_stop_dma(struct atmel_spi *as)
++{
++	if (as->dma.chan_rx)
++		as->dma.chan_rx->device->device_control(as->dma.chan_rx,
++							DMA_TERMINATE_ALL, 0);
++	if (as->dma.chan_tx)
++		as->dma.chan_tx->device->device_control(as->dma.chan_tx,
++							DMA_TERMINATE_ALL, 0);
++}
++
++static void atmel_spi_release_dma(struct atmel_spi *as)
++{
++	if (as->dma.chan_rx)
++		dma_release_channel(as->dma.chan_rx);
++	if (as->dma.chan_tx)
++		dma_release_channel(as->dma.chan_tx);
++}
++
++/* This function is called by the DMA driver from tasklet context */
++static void dma_callback(void *data)
++{
++	struct spi_master	*master = data;
++	struct atmel_spi	*as = spi_master_get_devdata(master);
++
++	/* trigger SPI tasklet */
++	tasklet_schedule(&as->tasklet);
++}
++
++/*
++ * Next transfer using PIO.
++ * lock is held, spi tasklet is blocked
++ */
++static void atmel_spi_next_xfer_pio(struct spi_master *master,
++				struct spi_transfer *xfer)
++{
++	struct atmel_spi	*as = spi_master_get_devdata(master);
++
++	dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
++
++	as->current_remaining_bytes = xfer->len;
++
++	/* Make sure data is not remaining in RDR */
++	spi_readl(as, RDR);
++	while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
++		spi_readl(as, RDR);
++		cpu_relax();
++	}
++
++	if (xfer->tx_buf)
++		spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
++	else
++		spi_writel(as, TDR, 0);
++
++	dev_dbg(master->dev.parent,
++		"  start pio xfer %p: len %u tx %p rx %p\n",
++		xfer, xfer->len, xfer->tx_buf, xfer->rx_buf);
++
++	/* Enable relevant interrupts */
++	spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
++}
++
++/*
++ * Submit next transfer for DMA.
++ * lock is held, spi tasklet is blocked
++ */
++static int atmel_spi_next_xfer_dma(struct spi_master *master,
++				struct spi_transfer *xfer)
++{
++	struct atmel_spi	*as = spi_master_get_devdata(master);
++	struct dma_chan		*rxchan = as->dma.chan_rx;
++	struct dma_chan		*txchan = as->dma.chan_tx;
++	struct dma_async_tx_descriptor *rxdesc;
++	struct dma_async_tx_descriptor *txdesc;
++	dma_cookie_t		cookie;
++
++	dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma\n");
++
++	/* Check that the channels are available */
++	if (!rxchan || !txchan)
++		return -ENODEV;
++
++	/* release lock for DMA operations */
++	atmel_spi_unlock(as);
++
++	/* prepare the RX dma transfer */
++	sg_init_table(&as->dma.sgrx, 1);
++	sg_dma_len(&as->dma.sgrx) = xfer->len;
++	if (xfer->rx_buf)
++		as->dma.sgrx.dma_address = xfer->rx_dma;
++	else
++		as->dma.sgrx.dma_address = as->buffer_dma;
++
++	/* prepare the TX dma transfer */
++	sg_init_table(&as->dma.sgtx, 1);
++	sg_dma_len(&as->dma.sgtx) = xfer->len;
++	if (xfer->tx_buf) {
++		as->dma.sgtx.dma_address = xfer->tx_dma;
++	} else {
++		as->dma.sgtx.dma_address = as->buffer_dma;
++		memset(as->buffer, 0, xfer->len);
++	}
++
++	/* Send both scatterlists */
++	rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
++					&as->dma.sgrx,
++					1,
++					DMA_FROM_DEVICE,
++					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++	if (!rxdesc)
++		goto err_dma;
++
++	txdesc = txchan->device->device_prep_slave_sg(txchan,
++					&as->dma.sgtx,
++					1,
++					DMA_TO_DEVICE,
++					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++	if (!txdesc)
++		goto err_dma;
++
++	dev_dbg(master->dev.parent,
++		"  start dma xfer %p: len %u tx %p/%08x rx %p/%08x\n",
++		xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
++		xfer->rx_buf, xfer->rx_dma);
++
++	/* Enable relevant interrupts */
++	spi_writel(as, IER, SPI_BIT(OVRES));
++
++	/* Put the callback on the RX transfer only, that should finish last */
++	rxdesc->callback = dma_callback;
++	rxdesc->callback_param = master;
++
++	/* Submit and fire RX and TX with TX last so we're ready to read! */
++	cookie = rxdesc->tx_submit(rxdesc);
++	if (dma_submit_error(cookie))
++		goto err_dma;
++	cookie = txdesc->tx_submit(txdesc);
++	if (dma_submit_error(cookie))
++		goto err_dma;
++	rxchan->device->device_issue_pending(rxchan);
++	txchan->device->device_issue_pending(txchan);
++
++	/* take back lock */
++	atmel_spi_lock(as);
++	return 0;
++
++err_dma:
++	spi_writel(as, IDR, SPI_BIT(OVRES));
++	atmel_spi_stop_dma(as);
++	atmel_spi_lock(as);
++	return -ENOMEM;
++}
++
++/*
++ * Choose way to submit next transfer and start it.
++ * lock is held, spi tasklet is blocked
++ */
++static void atmel_spi_next_xfer(struct spi_master *master,
++				struct spi_message *msg)
++{
++	struct atmel_spi	*as = spi_master_get_devdata(master);
++	struct spi_transfer	*xfer;
++
++	dev_vdbg(&msg->spi->dev, "atmel_spi_next_xfer\n");
++
++	if (!as->current_transfer)
++		xfer = list_entry(msg->transfers.next,
++				struct spi_transfer, transfer_list);
++	else
++		xfer = list_entry(as->current_transfer->transfer_list.next,
++				struct spi_transfer, transfer_list);
++
++	as->current_transfer = xfer;
++
++	if (atmel_spi_use_dma(xfer)) {
++		if (!atmel_spi_next_xfer_dma(master, xfer))
++			return;
++		else
++			dev_err(&msg->spi->dev, "unable to use DMA, fallback to PIO\n");
++	}
++
++	/* use PIO if xfer is short or error appened using DMA */
++	atmel_spi_next_xfer_pio(master, xfer);
++}
++
++static void atmel_spi_disable_dma_irq(struct atmel_spi *as) {}
++#else
++static void atmel_spi_disable_dma_irq(struct atmel_spi *as)
++{
++	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
++}
++
++static int __init atmel_spi_configure_dma(struct spi_master *master)
++{
++	struct atmel_spi	*as = spi_master_get_devdata(master);
++
++	atmel_spi_disable_dma_irq(as);
++	return 0;
++}
++
+ static void atmel_spi_next_xfer_data(struct spi_master *master,
+ 				struct spi_transfer *xfer,
+ 				dma_addr_t *tx_dma,
+@@ -325,6 +612,10 @@ static void atmel_spi_next_xfer(struct spi_master *master,
+ 	spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
+ }
+ 
++static void atmel_spi_stop_dma(struct atmel_spi *as) {}
++static void atmel_spi_release_dma(struct atmel_spi *as) {}
++#endif
++
+ static void atmel_spi_next_message(struct spi_master *master)
+ {
+ 	struct atmel_spi	*as = spi_master_get_devdata(master);
+@@ -428,11 +719,175 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
+ 
+ 	/* continue if needed */
+ 	if (list_empty(&as->queue) || as->stopping)
+-		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
++		atmel_spi_disable_dma_irq(as);
+ 	else
+ 		atmel_spi_next_message(master);
+ }
+ 
++#if defined(CONFIG_SPI_ATMEL_DMA)
++/* Called from IRQ
++ * lock is held
++ *
++ * Must update "current_remaining_bytes" to keep track of data
++ * to transfer.
++ */
++static void
++atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
++{
++	u8		*txp;
++	u8		*rxp;
++	unsigned long	xfer_pos = xfer->len - as->current_remaining_bytes;
++
++	if (xfer->rx_buf) {
++		rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
++		*rxp = spi_readl(as, RDR);
++	} else {
++		spi_readl(as, RDR);
++	}
++
++	as->current_remaining_bytes--;
++
++	if (as->current_remaining_bytes) {
++		if (xfer->tx_buf) {
++			txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
++			spi_writel(as, TDR, *txp);
++		} else {
++			spi_writel(as, TDR, 0);
++		}
++	}
++}
++
++/* Tasklet
++ * Called from DMA callback + pio transfer and overrun IRQ.
++ */
++static void atmel_spi_tasklet_func(unsigned long data)
++{
++	struct spi_master	*master = (struct spi_master *)data;
++	struct atmel_spi	*as = spi_master_get_devdata(master);
++	struct spi_message	*msg;
++	struct spi_transfer	*xfer;
++
++	dev_vdbg(master->dev.parent, "atmel_spi_tasklet_func\n");
++
++	atmel_spi_lock(as);
++
++	xfer = as->current_transfer;
++
++	if (xfer == NULL)
++		/* already been there */
++		goto tasklet_out;
++
++	msg = list_entry(as->queue.next, struct spi_message, queue);
++
++	if (as->done_status < 0) {
++		/* error happened (overrun) */
++		if (atmel_spi_use_dma(xfer))
++			atmel_spi_stop_dma(as);
++	} else {
++		/* only update length if no error */
++		msg->actual_length += xfer->len;
++	}
++
++	if (atmel_spi_use_dma(xfer)) {
++		if (!msg->is_dma_mapped)
++			atmel_spi_dma_unmap_xfer(master, xfer);
++	}
++
++	if (xfer->delay_usecs)
++		udelay(xfer->delay_usecs);
++
++	if (atmel_spi_xfer_is_last(msg, xfer) || as->done_status < 0) {
++		/* report completed (or erroneous) message */
++		atmel_spi_msg_done(master, as, msg, xfer->cs_change);
++	} else {
++		if (xfer->cs_change) {
++			cs_deactivate(as, msg->spi);
++			udelay(1);
++			cs_activate(as, msg->spi);
++		}
++
++		/*
++		 * Not done yet. Submit the next transfer.
++		 *
++		 * FIXME handle protocol options for xfer
++		 */
++		atmel_spi_next_xfer(master, msg);
++	}
++
++tasklet_out:
++	atmel_spi_unlock(as);
++}
++
++
++/* Interrupt with DMA engine management
++ *
++ * No need for locking in this Interrupt handler: done_status is the
++ * only information modified. What we need is the update of this field
++ * before tasklet runs. This is ensured by using barrier.
++ */
++static irqreturn_t
++atmel_spi_interrupt(int irq, void *dev_id)
++{
++	struct spi_master	*master = dev_id;
++	struct atmel_spi	*as = spi_master_get_devdata(master);
++	u32			status, pending, imr;
++	struct spi_transfer	*xfer;
++	int			ret = IRQ_NONE;
++
++	imr = spi_readl(as, IMR);
++	status = spi_readl(as, SR);
++	pending = status & imr;
++
++	if (pending & SPI_BIT(OVRES)) {
++		ret = IRQ_HANDLED;
++		spi_writel(as, IDR, SPI_BIT(OVRES));
++		dev_warn(master->dev.parent, "overrun\n");
++
++		/*
++		 * When we get an overrun, we disregard the current
++		 * transfer. Data will not be copied back from any
++		 * bounce buffer and msg->actual_len will not be
++		 * updated with the last xfer.
++		 *
++		 * We will also not process any remaning transfers in
++		 * the message.
++		 *
++		 * All actions are done in tasklet with done_status indication
++		 */
++		as->done_status = -EIO;
++		smp_wmb();
++
++		/* Clear any overrun happening while cleaning up */
++		spi_readl(as, SR);
++
++		tasklet_schedule(&as->tasklet);
++
++	} else if (pending & SPI_BIT(RDRF)) {
++		atmel_spi_lock(as);
++
++		if (as->current_remaining_bytes) {
++			ret = IRQ_HANDLED;
++			xfer = as->current_transfer;
++			atmel_spi_pump_pio_data(as, xfer);
++			if (!as->current_remaining_bytes) {
++				/* no more data to xfer, kick tasklet */
++				spi_writel(as, IDR, pending);
++				tasklet_schedule(&as->tasklet);
++			}
++		}
++
++		atmel_spi_unlock(as);
++	} else {
++		WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
++		ret = IRQ_HANDLED;
++		spi_writel(as, IDR, pending);
++	}
++
++	return ret;
++}
++#else
++static void atmel_spi_tasklet_func(unsigned long data) {}
++
+ static irqreturn_t
+ atmel_spi_interrupt(int irq, void *dev_id)
+ {
+@@ -550,6 +1005,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
+ 
+ 	return ret;
+ }
++#endif
+ 
+ static int atmel_spi_setup(struct spi_device *spi)
+ {
+@@ -709,13 +1165,9 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
+ 
+ 		/*
+ 		 * DMA map early, for performance (empties dcache ASAP) and
+-		 * better fault reporting.  This is a DMA-only driver.
+-		 *
+-		 * NOTE that if dma_unmap_single() ever starts to do work on
+-		 * platforms supported by this driver, we would need to clean
+-		 * up mappings for previously-mapped transfers.
++		 * better fault reporting.
+ 		 */
+-		if (!msg->is_dma_mapped) {
++		if (!msg->is_dma_mapped && atmel_spi_use_dma(xfer)) {
+ 			if (atmel_spi_dma_map_xfer(as, xfer) < 0)
+ 				return -ENOMEM;
+ 		}
+@@ -816,6 +1268,7 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
+ 
+ 	spin_lock_init(&as->lock);
+ 	INIT_LIST_HEAD(&as->queue);
++	tasklet_init(&as->tasklet, atmel_spi_tasklet_func, (unsigned long)master);
+ 	as->pdev = pdev;
+ 	as->regs = ioremap(regs->start, resource_size(regs));
+ 	if (!as->regs)
+@@ -834,7 +1287,11 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
+ 	spi_writel(as, CR, SPI_BIT(SWRST));
+ 	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
+ 	spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
+-	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
++
++	ret = atmel_spi_configure_dma(master);
++	if (ret)
++		goto out_reset_hw;
++
+ 	spi_writel(as, CR, SPI_BIT(SPIEN));
+ 
+ 	/* go! */
+@@ -843,10 +1300,12 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
+ 
+ 	ret = spi_register_master(master);
+ 	if (ret)
+-		goto out_reset_hw;
++		goto out_free_dma;
+ 
+ 	return 0;
+ 
++out_free_dma:
++	atmel_spi_release_dma(as);
+ out_reset_hw:
+ 	spi_writel(as, CR, SPI_BIT(SWRST));
+ 	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
+@@ -855,6 +1314,7 @@ out_reset_hw:
+ out_unmap_regs:
+ 	iounmap(as->regs);
+ out_free_buffer:
++	tasklet_kill(&as->tasklet);
+ 	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
+ 			as->buffer_dma);
+ out_free:
+@@ -873,6 +1333,8 @@ static int __exit atmel_spi_remove(struct platform_device *pdev)
+ 	/* reset the hardware and block queue progress */
+ 	spin_lock_irq(&as->lock);
+ 	as->stopping = 1;
++	atmel_spi_stop_dma(as);
++	atmel_spi_release_dma(as);
+ 	spi_writel(as, CR, SPI_BIT(SWRST));
+ 	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
+ 	spi_readl(as, SR);
+@@ -881,13 +1343,14 @@ static int __exit atmel_spi_remove(struct platform_device *pdev)
+ 	/* Terminate remaining queued transfers */
+ 	list_for_each_entry(msg, &as->queue, queue) {
+ 		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
+-			if (!msg->is_dma_mapped)
++			if (!msg->is_dma_mapped && atmel_spi_use_dma(xfer))
+ 				atmel_spi_dma_unmap_xfer(master, xfer);
+ 		}
+ 		msg->status = -ESHUTDOWN;
+ 		msg->complete(msg->context);
+ 	}
+ 
++	tasklet_kill(&as->tasklet);
+ 	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
+ 			as->buffer_dma);
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0034-net-can-allow-CAN_AT91-on-AT91SAM9X5.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0034-net-can-allow-CAN_AT91-on-AT91SAM9X5.patch
new file mode 100644
index 0000000..3be4cfa
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0034-net-can-allow-CAN_AT91-on-AT91SAM9X5.patch
@@ -0,0 +1,33 @@
+From a84abb9decfb07211601ac972a2d101b83068ea3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Tue, 26 Apr 2011 15:05:59 +0200
+Subject: [PATCH 034/107] net/can: allow CAN_AT91 on AT91SAM9X5
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/net/can/Kconfig |    5 +++--
+ 1 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
+index 1d699e3..bbf06f7 100644
+--- a/drivers/net/can/Kconfig
++++ b/drivers/net/can/Kconfig
+@@ -58,9 +58,10 @@ config CAN_CALC_BITTIMING
+ 
+ config CAN_AT91
+ 	tristate "Atmel AT91 onchip CAN controller"
+-	depends on CAN_DEV && ARCH_AT91SAM9263
++	depends on CAN_DEV && (ARCH_AT91SAM9263 || ARCH_AT91SAM9X5)
+ 	---help---
+-	  This is a driver for the SoC CAN controller in Atmel's AT91SAM9263.
++	  This is a driver for the SoC CAN controller in Atmel's AT91SAM9263
++	  and AT91SAM9X5 processors.
+ 
+ config CAN_TI_HECC
+ 	depends on CAN_DEV && ARCH_OMAP3
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0035-Input-qt1070-Add-MODULE_DEVICE_TABLE.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0035-Input-qt1070-Add-MODULE_DEVICE_TABLE.patch
new file mode 100644
index 0000000..3d9a39e
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0035-Input-qt1070-Add-MODULE_DEVICE_TABLE.patch
@@ -0,0 +1,34 @@
+From ee417d527f59f8d30ea232e142ba02a95bc541f2 Mon Sep 17 00:00:00 2001
+From: Axel Lin <axel.lin@gmail.com>
+Date: Sun, 24 Apr 2011 15:22:45 +0000
+Subject: [PATCH 035/107] Input: qt1070 - Add MODULE_DEVICE_TABLE
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Adding the necessary MODULE_DEVICE_TABLE() information allows the
+driver to be automatically loaded by udev
+
+Signed-off-by: Axel Lin <axel.lin@gmail.com>
+Signed-off-by: Dmitry Torokhov <dtor@mail.ru>
+Origin: upstream, commit:94bb530c247a29f75fc728e5f8374a83d59d7e45
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/input/keyboard/qt1070.c |    1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/input/keyboard/qt1070.c b/drivers/input/keyboard/qt1070.c
+index fba8404..ca7b891 100644
+--- a/drivers/input/keyboard/qt1070.c
++++ b/drivers/input/keyboard/qt1070.c
+@@ -248,6 +248,7 @@ static const struct i2c_device_id qt1070_id[] = {
+ 	{ "qt1070", 0 },
+ 	{ },
+ };
++MODULE_DEVICE_TABLE(i2c, qt1070_id);
+ 
+ static struct i2c_driver qt1070_driver = {
+ 	.driver	= {
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0036-Input-qt1070-trivial-fix-CHANGE-line-typo.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0036-Input-qt1070-trivial-fix-CHANGE-line-typo.patch
new file mode 100644
index 0000000..3e5a30d
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0036-Input-qt1070-trivial-fix-CHANGE-line-typo.patch
@@ -0,0 +1,30 @@
+From aef9d83e07df0fd4cc590faf597373cdd05f9e7f Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Wed, 25 May 2011 18:33:52 +0200
+Subject: [PATCH 036/107] Input: qt1070: trivial: fix CHANGE line typo
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/input/keyboard/qt1070.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/input/keyboard/qt1070.c b/drivers/input/keyboard/qt1070.c
+index ca7b891..f2cd759 100644
+--- a/drivers/input/keyboard/qt1070.c
++++ b/drivers/input/keyboard/qt1070.c
+@@ -216,7 +216,7 @@ static int __devinit qt1070_probe(struct i2c_client *client,
+ 
+ 	i2c_set_clientdata(client, data);
+ 
+-	/* Read to clear the chang line */
++	/* Read to clear the CHANGE line */
+ 	qt1070_read(client, DET_STATUS);
+ 
+ 	return 0;
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0037-Input-qt1070-add-power-management-suspend-resume.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0037-Input-qt1070-add-power-management-suspend-resume.patch
new file mode 100644
index 0000000..e77a415
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0037-Input-qt1070-add-power-management-suspend-resume.patch
@@ -0,0 +1,166 @@
+From 13daa6596a3b571eb7d46f5e49344fb31833ab8d Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 17 May 2011 15:47:44 +0200
+Subject: [PATCH 037/107] Input: qt1070: add power management suspend/resume
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add the power management suspend/resume functions and enable the wakeup
+capacity of the dedicated IRQ.
+The Low Power Mode of the QT1070 is also positioned on suspend and default
+acquisition frequency is restored on resume. It will allow to save power.
+
+Based on work by Voice Shen.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/input/keyboard/qt1070.c |   85 +++++++++++++++++++++++++++++++++-----
+ 1 files changed, 73 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/input/keyboard/qt1070.c b/drivers/input/keyboard/qt1070.c
+index f2cd759..7aa0f9e 100644
+--- a/drivers/input/keyboard/qt1070.c
++++ b/drivers/input/keyboard/qt1070.c
+@@ -42,6 +42,9 @@
+ #define QT1070_FW_VERSION  0x15
+ 
+ #define DET_STATUS         0x02
++#define DET_STATUS_TOUCH   0x01
++#define DET_STATUS_OVER    0x40
++#define DET_STATUS_CALIBR  0x80
+ 
+ #define KEY_STATUS         0x03
+ 
+@@ -53,6 +56,10 @@
+ #define RESET              0x39
+ #define QT1070_RESET_TIME  255
+ 
++/* Low Power Mode */
++#define LP_MODE            0x54
++#define LP_MODE_LOW        255
++
+ /* AT42QT1070 support up to 7 keys */
+ static const unsigned short qt1070_key2code[] = {
+ 	KEY_0, KEY_1, KEY_2, KEY_3,
+@@ -65,6 +72,7 @@ struct qt1070_data {
+ 	unsigned int irq;
+ 	unsigned short keycodes[ARRAY_SIZE(qt1070_key2code)];
+ 	u8 last_keys;
++	u8 power_mode;
+ };
+ 
+ static int qt1070_read(struct i2c_client *client, u8 reg)
+@@ -114,29 +122,36 @@ static bool __devinit qt1070_identify(struct i2c_client *client)
+ 	return true;
+ }
+ 
+-static irqreturn_t qt1070_interrupt(int irq, void *dev_id)
++static void qt1070_report_key_pressed(struct qt1070_data *data, u8 key)
+ {
+-	struct qt1070_data *data = dev_id;
+-	struct i2c_client *client = data->client;
+ 	struct input_dev *input = data->input;
+ 	int i;
+-	u8 new_keys, keyval, mask = 0x01;
+-
+-	/* Read the detected status register, thus clearing interrupt */
+-	qt1070_read(client, DET_STATUS);
+-
+-	/* Read which key changed */
+-	new_keys = qt1070_read(client, KEY_STATUS);
++	u8 keyval, mask = 0x01;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(qt1070_key2code); i++) {
+-		keyval = new_keys & mask;
++		keyval = key & mask;
+ 		if ((data->last_keys & mask) != keyval)
+ 			input_report_key(input, data->keycodes[i], keyval);
+ 		mask <<= 1;
+ 	}
+ 	input_sync(input);
+ 
+-	data->last_keys = new_keys;
++	data->last_keys = key;
++}
++
++static irqreturn_t qt1070_interrupt(int irq, void *dev_id)
++{
++	struct qt1070_data *data = dev_id;
++	struct i2c_client *client = data->client;
++	u8 new_keys;
++
++	/* Read the detected status register, thus clearing interrupt */
++	qt1070_read(client, DET_STATUS);
++
++	/* Read which key changed */
++	new_keys = qt1070_read(client, KEY_STATUS);
++
++	qt1070_report_key_pressed(data, new_keys);
+ 	return IRQ_HANDLED;
+ }
+ 
+@@ -228,6 +243,51 @@ err_free_mem:
+ 	kfree(data);
+ 	return err;
+ }
++#ifdef CONFIG_PM
++static int qt1070_suspend(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct qt1070_data *data = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(dev)) {
++		enable_irq_wake(client->irq);
++	}
++
++	data->power_mode = qt1070_read(client, LP_MODE);
++	qt1070_write(client, LP_MODE, LP_MODE_LOW);
++
++	return 0;
++}
++
++static int qt1070_resume(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct qt1070_data *data = i2c_get_clientdata(client);
++	u8 new_keys;
++
++	if (device_may_wakeup(dev)) {
++		disable_irq_wake(client->irq);
++	}
++
++	/* Read the detected status register, thus clearing interrupt */
++	qt1070_read(client, DET_STATUS);
++
++	/* Read which key changed */
++	new_keys = qt1070_read(client, KEY_STATUS);
++
++	qt1070_report_key_pressed(data, new_keys);
++
++	/* Restore power mode */
++	qt1070_write(client, LP_MODE, data->power_mode);
++
++	/* Drain remaining status */
++	while (qt1070_read(client, DET_STATUS) & DET_STATUS_TOUCH)
++		udelay(1);
++
++	return 0;
++}
++#endif
++static SIMPLE_DEV_PM_OPS(qt1070_pm, qt1070_suspend, qt1070_resume);
+ 
+ static int __devexit qt1070_remove(struct i2c_client *client)
+ {
+@@ -254,6 +314,7 @@ static struct i2c_driver qt1070_driver = {
+ 	.driver	= {
+ 		.name	= "qt1070",
+ 		.owner	= THIS_MODULE,
++		.pm	= &qt1070_pm,
+ 	},
+ 	.id_table	= qt1070_id,
+ 	.probe		= qt1070_probe,
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0038-dmaengine-at_hdmac-clear-channel-status-on-channel-r.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0038-dmaengine-at_hdmac-clear-channel-status-on-channel-r.patch
new file mode 100644
index 0000000..d0a892f
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0038-dmaengine-at_hdmac-clear-channel-status-on-channel-r.patch
@@ -0,0 +1,30 @@
+From 5b10093c7019fe3827d876bf3bfbdbb6ad015463 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 21 Apr 2011 18:36:43 +0200
+Subject: [PATCH 038/107] dmaengine: at_hdmac: clear channel status on channel
+ release
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c |    1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index db2c0bd..7fb4b57 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -1107,6 +1107,7 @@ static void atc_free_chan_resources(struct dma_chan *chan)
+ 	}
+ 	list_splice_init(&atchan->free_list, &list);
+ 	atchan->descs_allocated = 0;
++	atchan->status = 0;
+ 
+ 	dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
+ }
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0039-dmaengine-at_hdmac-set-residue-as-total-len-in-atc_t.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0039-dmaengine-at_hdmac-set-residue-as-total-len-in-atc_t.patch
new file mode 100644
index 0000000..0925537
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0039-dmaengine-at_hdmac-set-residue-as-total-len-in-atc_t.patch
@@ -0,0 +1,41 @@
+From 22ed20ae109f8b777b9f3068def49eea74ff7ab4 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Mon, 2 May 2011 17:48:30 +0200
+Subject: [PATCH 039/107] dmaengine: at_hdmac: set residue as total len in
+ atc_tx_status
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+If transfer status is !=DMA_SUCCESS, return total transfer len as residue,
+instead of zero.
+
+Idea from dw_dmac patch by Viresh Kumar.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c |    7 ++++++-
+ 1 files changed, 6 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index 7fb4b57..f2f589c 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -979,7 +979,12 @@ atc_tx_status(struct dma_chan *chan,
+ 
+ 	spin_unlock_bh(&atchan->lock);
+ 
+-	dma_set_tx_state(txstate, last_complete, last_used, 0);
++	if (ret != DMA_SUCCESS)
++		dma_set_tx_state(txstate, last_complete, last_used,
++			atc_first_active(atchan)->len);
++	else
++		dma_set_tx_state(txstate, last_complete, last_used, 0);
++
+ 	dev_vdbg(chan2dev(chan), "tx_status: %d (d%d, u%d)\n",
+ 		 cookie, last_complete ? last_complete : 0,
+ 		 last_used ? last_used : 0);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0040-dmaengine-at_hdmac-implement-pause-and-resume-in-atc.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0040-dmaengine-at_hdmac-implement-pause-and-resume-in-atc.patch
new file mode 100644
index 0000000..5538423
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0040-dmaengine-at_hdmac-implement-pause-and-resume-in-atc.patch
@@ -0,0 +1,170 @@
+From 662cdace226d8aba7f0fc0931f5099b125609ea8 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Fri, 6 May 2011 19:56:52 +0200
+Subject: [PATCH 040/107] dmaengine: at_hdmac: implement pause and resume in
+ atc_control
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Pause and resume controls are useful for audio devices. This also returns
+correct status from atc_tx_status() in case chan is paused.
+
+Idea from dw_dmac patch by Linus Walleij.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Acked-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c      |   98 ++++++++++++++++++++++++++++++------------
+ drivers/dma/at_hdmac_regs.h |    1 +
+ 2 files changed, 71 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index f2f589c..1999703 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -484,7 +484,8 @@ static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
+ 			if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) {
+ 				if (pending & AT_DMA_ERR(i)) {
+ 					/* Disable channel on AHB error */
+-					dma_writel(atdma, CHDR, atchan->mask);
++					dma_writel(atdma, CHDR,
++						AT_DMA_RES(i) | atchan->mask);
+ 					/* Give information to tasklet */
+ 					set_bit(ATC_IS_ERROR, &atchan->status);
+ 				}
+@@ -904,40 +905,78 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ {
+ 	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
+ 	struct at_dma		*atdma = to_at_dma(chan->device);
+-	struct at_desc		*desc, *_desc;
++	int			chan_id = atchan->chan_common.chan_id;
++
+ 	LIST_HEAD(list);
+ 
+-	/* Only supports DMA_TERMINATE_ALL */
+-	if (cmd != DMA_TERMINATE_ALL)
+-		return -ENXIO;
++	dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd);
+ 
+-	/*
+-	 * This is only called when something went wrong elsewhere, so
+-	 * we don't really care about the data. Just disable the
+-	 * channel. We still have to poll the channel enable bit due
+-	 * to AHB/HSB limitations.
+-	 */
+-	spin_lock_bh(&atchan->lock);
++	if (cmd == DMA_PAUSE) {
++		int pause_timeout = 1000;
+ 
+-	dma_writel(atdma, CHDR, atchan->mask);
++		spin_lock_bh(&atchan->lock);
+ 
+-	/* confirm that this channel is disabled */
+-	while (dma_readl(atdma, CHSR) & atchan->mask)
+-		cpu_relax();
++		dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
++
++		/* wait for FIFO to be empty */
++		while (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id))) {
++			if (pause_timeout-- > 0) {
++				/* the FIFO can only drain if the peripheral
++				 * is still requesting data:
++				 * -> timeout if it is not the case. */
++				dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
++				spin_unlock_bh(&atchan->lock);
++				return -ETIMEDOUT;
++			}
++			cpu_relax();
++		}
+ 
+-	/* active_list entries will end up before queued entries */
+-	list_splice_init(&atchan->queue, &list);
+-	list_splice_init(&atchan->active_list, &list);
++		set_bit(ATC_IS_PAUSED, &atchan->status);
+ 
+-	/* Flush all pending and queued descriptors */
+-	list_for_each_entry_safe(desc, _desc, &list, desc_node)
+-		atc_chain_complete(atchan, desc);
++		spin_unlock_bh(&atchan->lock);
++	} else if (cmd == DMA_RESUME) {
++		if (!test_bit(ATC_IS_PAUSED, &atchan->status))
++			return 0;
+ 
+-	spin_unlock_bh(&atchan->lock);
++		spin_lock_bh(&atchan->lock);
+ 
+-	/* XXX/ukl: should this be done with bh disabled? */
+-	/* if channel dedicated to cyclic operations, free it */
+-	clear_bit(ATC_IS_CYCLIC, &atchan->status);
++		dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
++		clear_bit(ATC_IS_PAUSED, &atchan->status);
++
++		spin_unlock_bh(&atchan->lock);
++	} else if (cmd == DMA_TERMINATE_ALL) {
++		struct at_desc	*desc, *_desc;
++		/*
++		 * This is only called when something went wrong elsewhere, so
++		 * we don't really care about the data. Just disable the
++		 * channel. We still have to poll the channel enable bit due
++		 * to AHB/HSB limitations.
++		 */
++		spin_lock_bh(&atchan->lock);
++
++		/* disabling channel: must also remove suspend state */
++		dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask);
++
++		/* confirm that this channel is disabled */
++		while (dma_readl(atdma, CHSR) & atchan->mask)
++			cpu_relax();
++
++		/* active_list entries will end up before queued entries */
++		list_splice_init(&atchan->queue, &list);
++		list_splice_init(&atchan->active_list, &list);
++
++		/* Flush all pending and queued descriptors */
++		list_for_each_entry_safe(desc, _desc, &list, desc_node)
++			atc_chain_complete(atchan, desc);
++
++		clear_bit(ATC_IS_PAUSED, &atchan->status);
++		/* if channel dedicated to cyclic operations, free it */
++		clear_bit(ATC_IS_CYCLIC, &atchan->status);
++
++		spin_unlock_bh(&atchan->lock);
++	} else {
++		return -ENXIO;
++	}
+ 
+ 	return 0;
+ }
+@@ -985,8 +1024,11 @@ atc_tx_status(struct dma_chan *chan,
+ 	else
+ 		dma_set_tx_state(txstate, last_complete, last_used, 0);
+ 
+-	dev_vdbg(chan2dev(chan), "tx_status: %d (d%d, u%d)\n",
+-		 cookie, last_complete ? last_complete : 0,
++	if (test_bit(ATC_IS_PAUSED, &atchan->status))
++		ret = DMA_PAUSED;
++
++	dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n",
++		 ret, cookie, last_complete ? last_complete : 0,
+ 		 last_used ? last_used : 0);
+ 
+ 	return ret;
+diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
+index 9afcb8d..629703a 100644
+--- a/drivers/dma/at_hdmac_regs.h
++++ b/drivers/dma/at_hdmac_regs.h
+@@ -189,6 +189,7 @@ txd_to_at_desc(struct dma_async_tx_descriptor *txd)
+  */
+ enum atc_status {
+ 	ATC_IS_ERROR = 0,
++	ATC_IS_PAUSED = 1,
+ 	ATC_IS_CYCLIC = 24,
+ };
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0041-dmaengine-at_hdmac-pause-no-need-to-wait-for-FIFO-em.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0041-dmaengine-at_hdmac-pause-no-need-to-wait-for-FIFO-em.patch
new file mode 100644
index 0000000..af628d0
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0041-dmaengine-at_hdmac-pause-no-need-to-wait-for-FIFO-em.patch
@@ -0,0 +1,60 @@
+From a8a86b647c212d379d8df079d0c57a3ab26848fc Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Mon, 9 May 2011 18:11:37 +0200
+Subject: [PATCH 041/107] dmaengine: at_hdmac: pause: no need to wait for FIFO
+ empty
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+With the addition of the "pause" feature, an active wait was introduced
+to check the "FIFO empty" event. This event was not always happening and
+a timout contition was needed.
+But, in some cases, this event depend on the peripheral connected to the
+channel that is paused: FIFO becomes empty if the peripheral consumes data.
+The timeout is pretty difficult to evaluate. Moreover, this check is not
+needed.
+In conclusion, it seems sensible to entirely remove the checking of
+"FIFO empty" status when pausing.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+[commit msg edited for grammer]
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c |   16 ----------------
+ 1 files changed, 0 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index 1999703..f11f640 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -912,25 +912,9 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ 	dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd);
+ 
+ 	if (cmd == DMA_PAUSE) {
+-		int pause_timeout = 1000;
+-
+ 		spin_lock_bh(&atchan->lock);
+ 
+ 		dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
+-
+-		/* wait for FIFO to be empty */
+-		while (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id))) {
+-			if (pause_timeout-- > 0) {
+-				/* the FIFO can only drain if the peripheral
+-				 * is still requesting data:
+-				 * -> timeout if it is not the case. */
+-				dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
+-				spin_unlock_bh(&atchan->lock);
+-				return -ETIMEDOUT;
+-			}
+-			cpu_relax();
+-		}
+-
+ 		set_bit(ATC_IS_PAUSED, &atchan->status);
+ 
+ 		spin_unlock_bh(&atchan->lock);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0042-dmaengine-at_hdmac-replace-spin_lock-with-irqsave-va.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0042-dmaengine-at_hdmac-replace-spin_lock-with-irqsave-va.patch
new file mode 100644
index 0000000..f936c9c
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0042-dmaengine-at_hdmac-replace-spin_lock-with-irqsave-va.patch
@@ -0,0 +1,244 @@
+From 14a52d058779054c81e68a0feda2a2f382ce16c3 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Mon, 9 May 2011 18:20:21 +0200
+Subject: [PATCH 042/107] dmaengine: at_hdmac: replace spin_lock* with irqsave
+ variants
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+dmaengine routines can be called from interrupt context and with
+interrupts disabled. Whereas spin_unlock_bh can't be called from
+such contexts. So this patch converts all spin_lock* routines
+to irqsave variants.
+
+Also, spin_lock() used in tasklet is converted to irqsave variants,
+as tasklet can be interrupted, and dma requests from such interruptions
+may also call spin_lock.
+
+Idea from dw_dmac patch by Viresh Kumar.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c |   52 +++++++++++++++++++++++++++--------------------
+ 1 files changed, 30 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index f11f640..b29942a 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -106,10 +106,11 @@ static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
+ {
+ 	struct at_desc *desc, *_desc;
+ 	struct at_desc *ret = NULL;
++	unsigned long flags;
+ 	unsigned int i = 0;
+ 	LIST_HEAD(tmp_list);
+ 
+-	spin_lock_bh(&atchan->lock);
++	spin_lock_irqsave(&atchan->lock, flags);
+ 	list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
+ 		i++;
+ 		if (async_tx_test_ack(&desc->txd)) {
+@@ -120,7 +121,7 @@ static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
+ 		dev_dbg(chan2dev(&atchan->chan_common),
+ 				"desc %p not ACKed\n", desc);
+ 	}
+-	spin_unlock_bh(&atchan->lock);
++	spin_unlock_irqrestore(&atchan->lock, flags);
+ 	dev_vdbg(chan2dev(&atchan->chan_common),
+ 		"scanned %u descriptors on freelist\n", i);
+ 
+@@ -128,9 +129,9 @@ static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
+ 	if (!ret) {
+ 		ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC);
+ 		if (ret) {
+-			spin_lock_bh(&atchan->lock);
++			spin_lock_irqsave(&atchan->lock, flags);
+ 			atchan->descs_allocated++;
+-			spin_unlock_bh(&atchan->lock);
++			spin_unlock_irqrestore(&atchan->lock, flags);
+ 		} else {
+ 			dev_err(chan2dev(&atchan->chan_common),
+ 					"not enough descriptors available\n");
+@@ -149,8 +150,9 @@ static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
+ {
+ 	if (desc) {
+ 		struct at_desc *child;
++		unsigned long flags;
+ 
+-		spin_lock_bh(&atchan->lock);
++		spin_lock_irqsave(&atchan->lock, flags);
+ 		list_for_each_entry(child, &desc->tx_list, desc_node)
+ 			dev_vdbg(chan2dev(&atchan->chan_common),
+ 					"moving child desc %p to freelist\n",
+@@ -159,7 +161,7 @@ static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
+ 		dev_vdbg(chan2dev(&atchan->chan_common),
+ 			 "moving desc %p to freelist\n", desc);
+ 		list_add(&desc->desc_node, &atchan->free_list);
+-		spin_unlock_bh(&atchan->lock);
++		spin_unlock_irqrestore(&atchan->lock, flags);
+ 	}
+ }
+ 
+@@ -447,8 +449,9 @@ static void atc_handle_cyclic(struct at_dma_chan *atchan)
+ static void atc_tasklet(unsigned long data)
+ {
+ 	struct at_dma_chan *atchan = (struct at_dma_chan *)data;
++	unsigned long flags;
+ 
+-	spin_lock(&atchan->lock);
++	spin_lock_irqsave(&atchan->lock, flags);
+ 	if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
+ 		atc_handle_error(atchan);
+ 	else if (test_bit(ATC_IS_CYCLIC, &atchan->status))
+@@ -456,7 +459,7 @@ static void atc_tasklet(unsigned long data)
+ 	else
+ 		atc_advance_work(atchan);
+ 
+-	spin_unlock(&atchan->lock);
++	spin_unlock_irqrestore(&atchan->lock, flags);
+ }
+ 
+ static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
+@@ -515,8 +518,9 @@ static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
+ 	struct at_desc		*desc = txd_to_at_desc(tx);
+ 	struct at_dma_chan	*atchan = to_at_dma_chan(tx->chan);
+ 	dma_cookie_t		cookie;
++	unsigned long		flags;
+ 
+-	spin_lock_bh(&atchan->lock);
++	spin_lock_irqsave(&atchan->lock, flags);
+ 	cookie = atc_assign_cookie(atchan, desc);
+ 
+ 	if (list_empty(&atchan->active_list)) {
+@@ -530,7 +534,7 @@ static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
+ 		list_add_tail(&desc->desc_node, &atchan->queue);
+ 	}
+ 
+-	spin_unlock_bh(&atchan->lock);
++	spin_unlock_irqrestore(&atchan->lock, flags);
+ 
+ 	return cookie;
+ }
+@@ -906,28 +910,29 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ 	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
+ 	struct at_dma		*atdma = to_at_dma(chan->device);
+ 	int			chan_id = atchan->chan_common.chan_id;
++	unsigned long		flags;
+ 
+ 	LIST_HEAD(list);
+ 
+ 	dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd);
+ 
+ 	if (cmd == DMA_PAUSE) {
+-		spin_lock_bh(&atchan->lock);
++		spin_lock_irqsave(&atchan->lock, flags);
+ 
+ 		dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
+ 		set_bit(ATC_IS_PAUSED, &atchan->status);
+ 
+-		spin_unlock_bh(&atchan->lock);
++		spin_unlock_irqrestore(&atchan->lock, flags);
+ 	} else if (cmd == DMA_RESUME) {
+ 		if (!test_bit(ATC_IS_PAUSED, &atchan->status))
+ 			return 0;
+ 
+-		spin_lock_bh(&atchan->lock);
++		spin_lock_irqsave(&atchan->lock, flags);
+ 
+ 		dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
+ 		clear_bit(ATC_IS_PAUSED, &atchan->status);
+ 
+-		spin_unlock_bh(&atchan->lock);
++		spin_unlock_irqrestore(&atchan->lock, flags);
+ 	} else if (cmd == DMA_TERMINATE_ALL) {
+ 		struct at_desc	*desc, *_desc;
+ 		/*
+@@ -936,7 +941,7 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ 		 * channel. We still have to poll the channel enable bit due
+ 		 * to AHB/HSB limitations.
+ 		 */
+-		spin_lock_bh(&atchan->lock);
++		spin_lock_irqsave(&atchan->lock, flags);
+ 
+ 		/* disabling channel: must also remove suspend state */
+ 		dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask);
+@@ -957,7 +962,7 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ 		/* if channel dedicated to cyclic operations, free it */
+ 		clear_bit(ATC_IS_CYCLIC, &atchan->status);
+ 
+-		spin_unlock_bh(&atchan->lock);
++		spin_unlock_irqrestore(&atchan->lock, flags);
+ 	} else {
+ 		return -ENXIO;
+ 	}
+@@ -983,9 +988,10 @@ atc_tx_status(struct dma_chan *chan,
+ 	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
+ 	dma_cookie_t		last_used;
+ 	dma_cookie_t		last_complete;
++	unsigned long		flags;
+ 	enum dma_status		ret;
+ 
+-	spin_lock_bh(&atchan->lock);
++	spin_lock_irqsave(&atchan->lock, flags);
+ 
+ 	last_complete = atchan->completed_cookie;
+ 	last_used = chan->cookie;
+@@ -1000,7 +1006,7 @@ atc_tx_status(struct dma_chan *chan,
+ 		ret = dma_async_is_complete(cookie, last_complete, last_used);
+ 	}
+ 
+-	spin_unlock_bh(&atchan->lock);
++	spin_unlock_irqrestore(&atchan->lock, flags);
+ 
+ 	if (ret != DMA_SUCCESS)
+ 		dma_set_tx_state(txstate, last_complete, last_used,
+@@ -1025,6 +1031,7 @@ atc_tx_status(struct dma_chan *chan,
+ static void atc_issue_pending(struct dma_chan *chan)
+ {
+ 	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
++	unsigned long		flags;
+ 
+ 	dev_vdbg(chan2dev(chan), "issue_pending\n");
+ 
+@@ -1032,11 +1039,11 @@ static void atc_issue_pending(struct dma_chan *chan)
+ 	if (test_bit(ATC_IS_CYCLIC, &atchan->status))
+ 		return;
+ 
+-	spin_lock_bh(&atchan->lock);
++	spin_lock_irqsave(&atchan->lock, flags);
+ 	if (!atc_chan_is_enabled(atchan)) {
+ 		atc_advance_work(atchan);
+ 	}
+-	spin_unlock_bh(&atchan->lock);
++	spin_unlock_irqrestore(&atchan->lock, flags);
+ }
+ 
+ /**
+@@ -1052,6 +1059,7 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
+ 	struct at_dma		*atdma = to_at_dma(chan->device);
+ 	struct at_desc		*desc;
+ 	struct at_dma_slave	*atslave;
++	unsigned long		flags;
+ 	int			i;
+ 	u32			cfg;
+ 	LIST_HEAD(tmp_list);
+@@ -1095,11 +1103,11 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
+ 		list_add_tail(&desc->desc_node, &tmp_list);
+ 	}
+ 
+-	spin_lock_bh(&atchan->lock);
++	spin_lock_irqsave(&atchan->lock, flags);
+ 	atchan->descs_allocated = i;
+ 	list_splice(&tmp_list, &atchan->free_list);
+ 	atchan->completed_cookie = chan->cookie = 1;
+-	spin_unlock_bh(&atchan->lock);
++	spin_unlock_irqrestore(&atchan->lock, flags);
+ 
+ 	/* channel parameters */
+ 	channel_writel(atchan, CFG, cfg);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0043-dmaengine-at_hdmac-improve-power-management-routines.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0043-dmaengine-at_hdmac-improve-power-management-routines.patch
new file mode 100644
index 0000000..b146b20
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0043-dmaengine-at_hdmac-improve-power-management-routines.patch
@@ -0,0 +1,182 @@
+From 66d750fa5b628797590fe9505137a4409a5badbe Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 19 May 2011 14:08:48 +0200
+Subject: [PATCH 043/107] dmaengine: at_hdmac: improve power management
+ routines
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Save/restore dma controller state across a suspend-resume sequence.
+The prepare() function will wait for the non-cyclic channels to become idle.
+It also deals with cyclic operations with the start at next period while
+resuming.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c      |   88 ++++++++++++++++++++++++++++++++++++++++++-
+ drivers/dma/at_hdmac_regs.h |    7 +++
+ 2 files changed, 94 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index b29942a..42b0e95 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -1364,27 +1364,113 @@ static void at_dma_shutdown(struct platform_device *pdev)
+ 	clk_disable(atdma->clk);
+ }
+ 
++static int at_dma_prepare(struct device *dev)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct at_dma *atdma = platform_get_drvdata(pdev);
++	struct dma_chan *chan, *_chan;
++
++	list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
++			device_node) {
++		struct at_dma_chan *atchan = to_at_dma_chan(chan);
++		/* wait for transaction completion (except in cyclic case) */
++		if (atc_chan_is_enabled(atchan) &&
++			!test_bit(ATC_IS_CYCLIC, &atchan->status))
++			return -EAGAIN;
++	}
++	return 0;
++}
++
++static void atc_suspend_cyclic(struct at_dma_chan *atchan)
++{
++	struct dma_chan	*chan = &atchan->chan_common;
++
++	/* Channel should be paused by user
++	 * do it anyway even if it is not done already */
++	if (!test_bit(ATC_IS_PAUSED, &atchan->status)) {
++		dev_warn(chan2dev(chan),
++		"cyclic channel not paused, should be done by channel user\n");
++		atc_control(chan, DMA_PAUSE, 0);
++	}
++
++	/* now preserve additional data for cyclic operations */
++	/* next descriptor address in the cyclic list */
++	atchan->save_dscr = channel_readl(atchan, DSCR);
++
++	vdbg_dump_regs(atchan);
++}
++
+ static int at_dma_suspend_noirq(struct device *dev)
+ {
+ 	struct platform_device *pdev = to_platform_device(dev);
+ 	struct at_dma *atdma = platform_get_drvdata(pdev);
++	struct dma_chan *chan, *_chan;
+ 
+-	at_dma_off(platform_get_drvdata(pdev));
++	/* preserve data */
++	list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
++			device_node) {
++		struct at_dma_chan *atchan = to_at_dma_chan(chan);
++
++		if (test_bit(ATC_IS_CYCLIC, &atchan->status))
++			atc_suspend_cyclic(atchan);
++		atchan->save_cfg = channel_readl(atchan, CFG);
++	}
++	atdma->save_imr = dma_readl(atdma, EBCIMR);
++
++	/* disable DMA controller */
++	at_dma_off(atdma);
+ 	clk_disable(atdma->clk);
+ 	return 0;
+ }
+ 
++static void atc_resume_cyclic(struct at_dma_chan *atchan)
++{
++	struct at_dma	*atdma = to_at_dma(atchan->chan_common.device);
++
++	/* restore channel status for cyclic descriptors list:
++	 * next descriptor in the cyclic list at the time of suspend */
++	channel_writel(atchan, SADDR, 0);
++	channel_writel(atchan, DADDR, 0);
++	channel_writel(atchan, CTRLA, 0);
++	channel_writel(atchan, CTRLB, 0);
++	channel_writel(atchan, DSCR, atchan->save_dscr);
++	dma_writel(atdma, CHER, atchan->mask);
++
++	/* channel pause status should be removed by channel user
++	 * We cannot take the initiative to do it here */
++
++	vdbg_dump_regs(atchan);
++}
++
+ static int at_dma_resume_noirq(struct device *dev)
+ {
+ 	struct platform_device *pdev = to_platform_device(dev);
+ 	struct at_dma *atdma = platform_get_drvdata(pdev);
++	struct dma_chan *chan, *_chan;
+ 
++	/* bring back DMA controller */
+ 	clk_enable(atdma->clk);
+ 	dma_writel(atdma, EN, AT_DMA_ENABLE);
++
++	/* clear any pending interrupt */
++	while (dma_readl(atdma, EBCISR))
++		cpu_relax();
++
++	/* restore saved data */
++	dma_writel(atdma, EBCIER, atdma->save_imr);
++	list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
++			device_node) {
++		struct at_dma_chan *atchan = to_at_dma_chan(chan);
++
++		channel_writel(atchan, CFG, atchan->save_cfg);
++		if (test_bit(ATC_IS_CYCLIC, &atchan->status))
++			atc_resume_cyclic(atchan);
++	}
+ 	return 0;
+ }
+ 
+ static const struct dev_pm_ops at_dma_dev_pm_ops = {
++	.prepare = at_dma_prepare,
+ 	.suspend_noirq = at_dma_suspend_noirq,
+ 	.resume_noirq = at_dma_resume_noirq,
+ };
+diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
+index 629703a..a29c698 100644
+--- a/drivers/dma/at_hdmac_regs.h
++++ b/drivers/dma/at_hdmac_regs.h
+@@ -202,6 +202,9 @@ enum atc_status {
+  * @status: transmit status information from irq/prep* functions
+  *                to tasklet (use atomic operations)
+  * @tasklet: bottom half to finish transaction work
++ * @save_cfg: configuration register that is saved on suspend/resume cycle
++ * @save_dscr: for cyclic operations, preserve next descriptor address in
++ *             the cyclic list on suspend/resume cycle
+  * @lock: serializes enqueue/dequeue operations to descriptors lists
+  * @completed_cookie: identifier for the most recently completed operation
+  * @active_list: list of descriptors dmaengine is being running on
+@@ -216,6 +219,8 @@ struct at_dma_chan {
+ 	u8			mask;
+ 	unsigned long		status;
+ 	struct tasklet_struct	tasklet;
++	u32			save_cfg;
++	u32			save_dscr;
+ 
+ 	spinlock_t		lock;
+ 
+@@ -246,6 +251,7 @@ static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
+  * @chan_common: common dmaengine dma_device object members
+  * @ch_regs: memory mapped register base
+  * @clk: dma controller clock
++ * @save_imr: interrupt mask register that is saved on suspend/resume cycle
+  * @all_chan_mask: all channels availlable in a mask
+  * @dma_desc_pool: base of DMA descriptor region (DMA address)
+  * @chan: channels table to store at_dma_chan structures
+@@ -254,6 +260,7 @@ struct at_dma {
+ 	struct dma_device	dma_common;
+ 	void __iomem		*regs;
+ 	struct clk		*clk;
++	u32			save_imr;
+ 
+ 	u8			all_chan_mask;
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0044-sound-atmel-pcm-trivial-typo-in-debug-comment.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0044-sound-atmel-pcm-trivial-typo-in-debug-comment.patch
new file mode 100644
index 0000000..50cc12d
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0044-sound-atmel-pcm-trivial-typo-in-debug-comment.patch
@@ -0,0 +1,30 @@
+From 6186270eb3654216ff51bd159444b46e83ffc5f2 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Wed, 6 Apr 2011 17:27:32 +0200
+Subject: [PATCH 044/107] sound/atmel-pcm: trivial: typo in debug comment
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ sound/soc/atmel/atmel-pcm.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/sound/soc/atmel/atmel-pcm.c b/sound/soc/atmel/atmel-pcm.c
+index d0e7532..51dde4e 100644
+--- a/sound/soc/atmel/atmel-pcm.c
++++ b/sound/soc/atmel/atmel-pcm.c
+@@ -382,7 +382,7 @@ static int atmel_pcm_new(struct snd_card *card,
+ 	}
+ 
+ 	if (dai->driver->capture.channels_min) {
+-		pr_debug("at32-pcm:"
++		pr_debug("atmel-pcm:"
+ 				"Allocating PCM capture DMA buffer\n");
+ 		ret = atmel_pcm_preallocate_dma_buffer(pcm,
+ 			SNDRV_PCM_STREAM_CAPTURE);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0045-sound-atmel-pcm-trivial-typo-in-atmel_pcm_dma_params.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0045-sound-atmel-pcm-trivial-typo-in-atmel_pcm_dma_params.patch
new file mode 100644
index 0000000..e0b6354
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0045-sound-atmel-pcm-trivial-typo-in-atmel_pcm_dma_params.patch
@@ -0,0 +1,31 @@
+From 139378503c1344fbad3f65af947b883055b8230d Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Wed, 6 Apr 2011 17:29:41 +0200
+Subject: [PATCH 045/107] sound/atmel-pcm: trivial: typo in
+ atmel_pcm_dma_params structure comment
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ sound/soc/atmel/atmel-pcm.h |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/sound/soc/atmel/atmel-pcm.h b/sound/soc/atmel/atmel-pcm.h
+index 2597329..5e0a95e 100644
+--- a/sound/soc/atmel/atmel-pcm.h
++++ b/sound/soc/atmel/atmel-pcm.h
+@@ -60,7 +60,7 @@ struct atmel_ssc_mask {
+  * This structure, shared between the PCM driver and the interface,
+  * contains all information required by the PCM driver to perform the
+  * PDC DMA operation.  All fields except dma_intr_handler() are initialized
+- * by the interface.  The dms_intr_handler() pointer is set by the PCM
++ * by the interface.  The dma_intr_handler() pointer is set by the PCM
+  * driver and called by the interface SSC interrupt handler if it is
+  * non-NULL.
+  */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0046-dmaengine-at_hdmac-add-slave-config-operation.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0046-dmaengine-at_hdmac-add-slave-config-operation.patch
new file mode 100644
index 0000000..f8ccbb3
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0046-dmaengine-at_hdmac-add-slave-config-operation.patch
@@ -0,0 +1,58 @@
+From 7499db30444de85e7cc8e7b0cf1576cb90e041ee Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 19 May 2011 17:09:20 +0200
+Subject: [PATCH 046/107] dmaengine: at_hdmac: add slave config operation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/dma/at_hdmac.c |   30 ++++++++++++++++++++++++++++++
+ 1 files changed, 30 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index 42b0e95..f793804 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -933,6 +933,36 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ 		clear_bit(ATC_IS_PAUSED, &atchan->status);
+ 
+ 		spin_unlock_irqrestore(&atchan->lock, flags);
++	} else if (cmd == DMA_SLAVE_CONFIG) {
++		struct dma_slave_config *dmaengine_cfg = (void *)arg;
++		struct at_dma_slave	*atslave = chan->private;
++		enum dma_slave_buswidth sdma_width;
++		enum at_dma_slave_width	atdma_width;
++
++		/* only modify transfer size width */
++		if (!atslave)
++			return -ENXIO;
++
++		if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
++			sdma_width = dmaengine_cfg->src_addr_width;
++		} else {
++			sdma_width = dmaengine_cfg->dst_addr_width;
++		}
++
++		switch (sdma_width) {
++		case DMA_SLAVE_BUSWIDTH_1_BYTE:
++			atdma_width = AT_DMA_SLAVE_WIDTH_8BIT;
++			break;
++		case DMA_SLAVE_BUSWIDTH_2_BYTES:
++			atdma_width = AT_DMA_SLAVE_WIDTH_16BIT;
++			break;
++		case DMA_SLAVE_BUSWIDTH_4_BYTES:
++			atdma_width = AT_DMA_SLAVE_WIDTH_32BIT;
++			break;
++		default:
++			return -EINVAL;
++		}
++		atslave->reg_width = atdma_width;
+ 	} else if (cmd == DMA_TERMINATE_ALL) {
+ 		struct at_desc	*desc, *_desc;
+ 		/*
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0047-SPI-m25p80-add-serial-flash-IDs.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0047-SPI-m25p80-add-serial-flash-IDs.patch
new file mode 100644
index 0000000..e6cf93c
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0047-SPI-m25p80-add-serial-flash-IDs.patch
@@ -0,0 +1,29 @@
+From 691890bc172ede0563732ca42bfea930249423bd Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 19 May 2011 17:12:59 +0200
+Subject: [PATCH 047/107] SPI: m25p80: add serial flash IDs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/mtd/devices/m25p80.c |    1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
+index 3fb981d..1fdc4ab 100644
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -648,6 +648,7 @@ static const struct spi_device_id m25p_ids[] = {
+ 	{ "at25fs040",  INFO(0x1f6604, 0, 64 * 1024,   8, SECT_4K) },
+ 
+ 	{ "at25df041a", INFO(0x1f4401, 0, 64 * 1024,   8, SECT_4K) },
++	{ "at25df321",  INFO(0x1f4701, 0, 64 * 1024,  64, SECT_4K) },
+ 	{ "at25df641",  INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
+ 
+ 	{ "at26f004",   INFO(0x1f0400, 0, 64 * 1024,  8, SECT_4K) },
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0048-sound-wm8731-rework-power-management.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0048-sound-wm8731-rework-power-management.patch
new file mode 100644
index 0000000..e27f502
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0048-sound-wm8731-rework-power-management.patch
@@ -0,0 +1,44 @@
+From e9364a4c457eed43d78f5d4c04f8fa364835fb9f Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 19 May 2011 14:14:34 +0200
+Subject: [PATCH 048/107] sound: wm8731: rework power management
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+- preserve crystal oscillator across suspend/resume sequence:
+  enabled by default,it should be kept enabled on resume.
+- if codec is in active state: set the active bit at resume time.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ sound/soc/codecs/wm8731.c |    5 ++++-
+ 1 files changed, 4 insertions(+), 1 deletions(-)
+
+diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c
+index 0a67c31..aa55b84 100644
+--- a/sound/soc/codecs/wm8731.c
++++ b/sound/soc/codecs/wm8731.c
+@@ -492,7 +492,8 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec,
+ 		break;
+ 	case SND_SOC_BIAS_OFF:
+ 		snd_soc_write(codec, WM8731_ACTIVE, 0x0);
+-		snd_soc_write(codec, WM8731_PWR, 0xffff);
++		/* standby: keep crystal oscillator enabled */
++		snd_soc_write(codec, WM8731_PWR, 0x00df);
+ 		regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies),
+ 				       wm8731->supplies);
+ 		break;
+@@ -544,6 +545,8 @@ static int wm8731_suspend(struct snd_soc_codec *codec, pm_message_t state)
+ static int wm8731_resume(struct snd_soc_codec *codec)
+ {
+ 	wm8731_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++	if (codec->active)
++		snd_soc_write(codec, WM8731_ACTIVE, 0x0001);
+ 
+ 	return 0;
+ }
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0049-atmel-ssc-add-phybase-in-device-structure.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0049-atmel-ssc-add-phybase-in-device-structure.patch
new file mode 100644
index 0000000..44e26a8
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0049-atmel-ssc-add-phybase-in-device-structure.patch
@@ -0,0 +1,44 @@
+From e5b9dfa6b7a9918cfb961b2ea1b5d3456b320edf Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 19 May 2011 17:41:06 +0200
+Subject: [PATCH 049/107] atmel-ssc: add phybase in device structure
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Useful for dmaengine use.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/misc/atmel-ssc.c  |    1 +
+ include/linux/atmel-ssc.h |    1 +
+ 2 files changed, 2 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/misc/atmel-ssc.c b/drivers/misc/atmel-ssc.c
+index 4afffe6..27c9ffa 100644
+--- a/drivers/misc/atmel-ssc.c
++++ b/drivers/misc/atmel-ssc.c
+@@ -101,6 +101,7 @@ static int __init ssc_probe(struct platform_device *pdev)
+ 		retval = -EINVAL;
+ 		goto out_clk;
+ 	}
++	ssc->phybase = regs->start;
+ 
+ 	/* disable all interrupts */
+ 	clk_enable(ssc->clk);
+diff --git a/include/linux/atmel-ssc.h b/include/linux/atmel-ssc.h
+index 0602339..2bab4b4 100644
+--- a/include/linux/atmel-ssc.h
++++ b/include/linux/atmel-ssc.h
+@@ -6,6 +6,7 @@
+ 
+ struct ssc_device {
+ 	struct list_head	list;
++	resource_size_t		phybase;
+ 	void __iomem		*regs;
+ 	struct platform_device	*pdev;
+ 	struct clk		*clk;
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0050-atmel-ssc-dmaengine-usage-switch-depending-on-cpu.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0050-atmel-ssc-dmaengine-usage-switch-depending-on-cpu.patch
new file mode 100644
index 0000000..e705923
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0050-atmel-ssc-dmaengine-usage-switch-depending-on-cpu.patch
@@ -0,0 +1,36 @@
+From c0254163515ae4e8fe27cf3ca1cccfaf84173dfc Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 19 May 2011 17:42:01 +0200
+Subject: [PATCH 050/107] atmel-ssc: dmaengine usage switch depending on cpu
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ include/linux/atmel-ssc.h |    3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+diff --git a/include/linux/atmel-ssc.h b/include/linux/atmel-ssc.h
+index 2bab4b4..52b4c20 100644
+--- a/include/linux/atmel-ssc.h
++++ b/include/linux/atmel-ssc.h
+@@ -3,6 +3,7 @@
+ 
+ #include <linux/platform_device.h>
+ #include <linux/list.h>
++#include <mach/cpu.h>
+ 
+ struct ssc_device {
+ 	struct list_head	list;
+@@ -310,4 +311,6 @@ void ssc_free(struct ssc_device *ssc);
+ #define ssc_readl(base, reg)		__raw_readl(base + SSC_##reg)
+ #define ssc_writel(base, reg, value)	__raw_writel((value), base + SSC_##reg)
+ 
++#define ssc_use_dmaengine()	cpu_is_at91sam9x5()
++
+ #endif /* __INCLUDE_ATMEL_SSC_H */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0051-sound-atmel_ssc_dai-fix-ssc-error-path.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0051-sound-atmel_ssc_dai-fix-ssc-error-path.patch
new file mode 100644
index 0000000..410d4f0
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0051-sound-atmel_ssc_dai-fix-ssc-error-path.patch
@@ -0,0 +1,35 @@
+From 4c6134391085c25e9c59ce2df43d648eeaf4366a Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 26 May 2011 13:25:08 +0200
+Subject: [PATCH 051/107] sound: atmel_ssc_dai: fix ssc error path
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We do not have to free a resource that is not allocated yet.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ sound/soc/atmel/atmel_ssc_dai.c |    4 +---
+ 1 files changed, 1 insertions(+), 3 deletions(-)
+
+diff --git a/sound/soc/atmel/atmel_ssc_dai.c b/sound/soc/atmel/atmel_ssc_dai.c
+index 7fbfa05..a7a7bbc 100644
+--- a/sound/soc/atmel/atmel_ssc_dai.c
++++ b/sound/soc/atmel/atmel_ssc_dai.c
+@@ -838,10 +838,8 @@ int atmel_ssc_set_audio(int ssc_id)
+ 	}
+ 
+ 	ssc_pdev = platform_device_alloc("atmel-ssc-dai", ssc_id);
+-	if (!ssc_pdev) {
+-		ssc_free(ssc);
++	if (!ssc_pdev)
+ 		return -ENOMEM;
+-	}
+ 
+ 	/* If we can grab the SSC briefly to parent the DAI device off it */
+ 	ssc = ssc_request(ssc_id);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0052-sound-atmel_ssc_dai-atmel-pmc-adapt-to-dmaengine-usa.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0052-sound-atmel_ssc_dai-atmel-pmc-adapt-to-dmaengine-usa.patch
new file mode 100644
index 0000000..a701dbb
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0052-sound-atmel_ssc_dai-atmel-pmc-adapt-to-dmaengine-usa.patch
@@ -0,0 +1,706 @@
+From 9feca7e7811843f5a3ca57b3410ee872d2731813 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 19 May 2011 17:52:02 +0200
+Subject: [PATCH 052/107] sound: atmel_ssc_dai/atmel-pmc: adapt to dmaengine
+ usage
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Change xfer_size name to apply to PDC and DMA aswell.
+Specify overrun bit in interrupt mask.
+Add dmaengine specific routines and replace PDC ones in
+pcm_ops if appropriate.
+Uses cyclic DMA API for queuing samples.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ sound/soc/atmel/atmel-pcm.c     |  387 +++++++++++++++++++++++++++++++++++---
+ sound/soc/atmel/atmel-pcm.h     |    4 +-
+ sound/soc/atmel/atmel_ssc_dai.c |   33 ++--
+ 3 files changed, 378 insertions(+), 46 deletions(-)
+
+diff --git a/sound/soc/atmel/atmel-pcm.c b/sound/soc/atmel/atmel-pcm.c
+index 51dde4e..536f325 100644
+--- a/sound/soc/atmel/atmel-pcm.c
++++ b/sound/soc/atmel/atmel-pcm.c
+@@ -37,6 +37,7 @@
+ #include <linux/slab.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/atmel_pdc.h>
++#include <linux/dmaengine.h>
+ #include <linux/atmel-ssc.h>
+ 
+ #include <sound/core.h>
+@@ -44,6 +45,8 @@
+ #include <sound/pcm_params.h>
+ #include <sound/soc.h>
+ 
++#include <mach/at_hdmac.h>
++
+ #include "atmel-pcm.h"
+ 
+ 
+@@ -53,7 +56,7 @@
+ /* TODO: These values were taken from the AT91 platform driver, check
+  *	 them against real values for AT32
+  */
+-static const struct snd_pcm_hardware atmel_pcm_hardware = {
++static const struct snd_pcm_hardware atmel_pcm_pdc_hardware = {
+ 	.info			= SNDRV_PCM_INFO_MMAP |
+ 				  SNDRV_PCM_INFO_MMAP_VALID |
+ 				  SNDRV_PCM_INFO_INTERLEAVED |
+@@ -66,6 +69,22 @@ static const struct snd_pcm_hardware atmel_pcm_hardware = {
+ 	.buffer_bytes_max	= 32 * 1024,
+ };
+ 
++static const struct snd_pcm_hardware atmel_pcm_dma_hardware = {
++	.info			= SNDRV_PCM_INFO_MMAP |
++				  SNDRV_PCM_INFO_MMAP_VALID |
++				  SNDRV_PCM_INFO_INTERLEAVED |
++				  SNDRV_PCM_INFO_RESUME |
++				  SNDRV_PCM_INFO_PAUSE,
++	.formats		= SNDRV_PCM_FMTBIT_S16_LE,
++	.period_bytes_min	= 256,		/* not too low to absorb DMA programming overhead */
++	.period_bytes_max	= 2 * 0xffff,	/* if 2 bytes format */
++	.periods_min		= 8,
++	.periods_max		= 1024,		/* no limit */
++	.buffer_bytes_max	= 64 * 1024,	/* 64KiB */
++};
++
++static const struct snd_pcm_hardware *atmel_pcm_hardware;
++
+ 
+ /*--------------------------------------------------------------------------*\
+  * Data types
+@@ -77,12 +96,19 @@ struct atmel_runtime_data {
+ 	size_t period_size;
+ 
+ 	dma_addr_t period_ptr;		/* physical address of next period */
++	int periods;			/* period index of period_ptr */
+ 
+ 	/* PDC register save */
+ 	u32 pdc_xpr_save;
+ 	u32 pdc_xcr_save;
+ 	u32 pdc_xnpr_save;
+ 	u32 pdc_xncr_save;
++
++	/* dmaengine data */
++	struct at_dma_slave atslave;
++	struct dma_async_tx_descriptor *desc;
++	dma_cookie_t cookie;
++	struct dma_chan *dma_chan;
+ };
+ 
+ 
+@@ -94,7 +120,7 @@ static int atmel_pcm_preallocate_dma_buffer(struct snd_pcm *pcm,
+ {
+ 	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+ 	struct snd_dma_buffer *buf = &substream->dma_buffer;
+-	size_t size = atmel_pcm_hardware.buffer_bytes_max;
++	size_t size = atmel_pcm_hardware->buffer_bytes_max;
+ 
+ 	buf->dev.type = SNDRV_DMA_TYPE_DEV;
+ 	buf->dev.dev = pcm->card->dev;
+@@ -116,7 +142,7 @@ static int atmel_pcm_preallocate_dma_buffer(struct snd_pcm *pcm,
+ /*--------------------------------------------------------------------------*\
+  * ISR
+ \*--------------------------------------------------------------------------*/
+-static void atmel_pcm_dma_irq(u32 ssc_sr,
++static void atmel_pcm_pdc_irq(u32 ssc_sr,
+ 	struct snd_pcm_substream *substream)
+ {
+ 	struct atmel_runtime_data *prtd = substream->runtime->private_data;
+@@ -142,7 +168,7 @@ static void atmel_pcm_dma_irq(u32 ssc_sr,
+ 		ssc_writex(params->ssc->regs, params->pdc->xpr,
+ 			   prtd->period_ptr);
+ 		ssc_writex(params->ssc->regs, params->pdc->xcr,
+-			   prtd->period_size / params->pdc_xfer_size);
++			   prtd->period_size / params->data_xfer_size);
+ 		ssc_writex(params->ssc->regs, ATMEL_PDC_PTCR,
+ 			   params->mask->pdc_enable);
+ 	}
+@@ -156,12 +182,165 @@ static void atmel_pcm_dma_irq(u32 ssc_sr,
+ 		ssc_writex(params->ssc->regs, params->pdc->xnpr,
+ 			   prtd->period_ptr);
+ 		ssc_writex(params->ssc->regs, params->pdc->xncr,
+-			   prtd->period_size / params->pdc_xfer_size);
++			   prtd->period_size / params->data_xfer_size);
+ 	}
+ 
+ 	snd_pcm_period_elapsed(substream);
+ }
+ 
++/**
++ * atmel_pcm_dma_irq: SSC interrupt handler for DMAENGINE enabled SSC
++ *
++ * We use DMAENGINE to send/receive data to/from SSC so this ISR is only to
++ * check if any overrun occured.
++ */
++static void atmel_pcm_dma_irq(u32 ssc_sr,
++	struct snd_pcm_substream *substream)
++{
++	struct atmel_runtime_data *prtd = substream->runtime->private_data;
++	struct atmel_pcm_dma_params *params = prtd->params;
++
++	if (ssc_sr & params->mask->ssc_error) {
++		if (snd_pcm_running(substream))
++			pr_warning("atmel-pcm: buffer %s on %s"
++					" (SSC_SR=%#x)\n",
++					substream->stream == SNDRV_PCM_STREAM_PLAYBACK
++					? "underrun" : "overrun",
++					params->name, ssc_sr);
++
++		/* stop RX and capture stream: will be enabled again at restart */
++		ssc_writex(params->ssc->regs, SSC_CR, params->mask->ssc_disable);
++		snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
++
++		/* now drain RHR and read status to remove xrun condition */
++		ssc_readx(params->ssc->regs, SSC_RHR);
++		ssc_readx(params->ssc->regs, SSC_SR);
++	}
++}
++
++/*--------------------------------------------------------------------------*\
++ * DMAENGINE operations
++\*--------------------------------------------------------------------------*/
++static bool filter(struct dma_chan *chan, void *slave)
++{
++	struct	at_dma_slave		*sl = slave;
++
++	if (sl->dma_dev == chan->device->dev) {
++		chan->private = sl;
++		return true;
++	} else {
++		return false;
++	}
++}
++
++static int atmel_pcm_dma_alloc(struct snd_pcm_substream *substream,
++	struct snd_pcm_hw_params *params)
++{
++	struct snd_pcm_runtime *runtime = substream->runtime;
++	struct atmel_runtime_data *prtd = runtime->private_data;
++	struct ssc_device *ssc = prtd->params->ssc;
++	struct at_dma_slave *sdata = NULL;
++
++	if (ssc->pdev)
++		sdata = ssc->pdev->dev.platform_data;
++
++	if (sdata && sdata->dma_dev) {
++		dma_cap_mask_t mask;
++
++		/* setup DMA addresses */
++		sdata->rx_reg = (dma_addr_t)ssc->phybase + SSC_RHR;
++		sdata->tx_reg = (dma_addr_t)ssc->phybase + SSC_THR;
++
++		/* Try to grab a DMA channel */
++		dma_cap_zero(mask);
++		dma_cap_set(DMA_CYCLIC, mask);
++		prtd->dma_chan = dma_request_channel(mask, filter, sdata);
++	}
++	if (!prtd->dma_chan) {
++		pr_err("atmel-pcm: "
++			"DMA channel not available, unable to use SSC-audio\n");
++		return -EBUSY;
++	}
++
++	return 0;
++}
++
++static void audio_dma_irq(void *data)
++{
++	struct snd_pcm_substream *substream = (struct snd_pcm_substream *)data;
++	struct snd_pcm_runtime *runtime = substream->runtime;
++	struct atmel_runtime_data *prtd = runtime->private_data;
++
++	prtd->period_ptr += prtd->period_size;
++	if (prtd->period_ptr >= prtd->dma_buffer_end)
++		prtd->period_ptr = prtd->dma_buffer;
++
++	snd_pcm_period_elapsed(substream);
++}
++
++static void atmel_pcm_dma_slave_config(struct snd_pcm_substream *substream)
++{
++	struct snd_pcm_runtime *runtime = substream->runtime;
++	struct atmel_runtime_data *prtd = runtime->private_data;
++	struct dma_chan *chan = prtd->dma_chan;
++	struct dma_slave_config slave_config;
++	enum dma_slave_buswidth buswidth;
++
++	switch (prtd->params->data_xfer_size) {
++	case 1:
++		buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
++		break;
++	case 2:
++		buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++		break;
++	case 4:
++		buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
++		break;
++	default:
++		return;
++	}
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		slave_config.direction = DMA_TO_DEVICE;
++		slave_config.dst_addr_width = buswidth;
++	} else {
++		slave_config.direction = DMA_FROM_DEVICE;
++		slave_config.src_addr_width = buswidth;
++	}
++
++	chan->device->device_control(chan, DMA_SLAVE_CONFIG,
++			(unsigned long)&slave_config);
++
++}
++
++static int atmel_pcm_dma_prep(struct snd_pcm_substream *substream)
++{
++	struct snd_pcm_runtime *runtime = substream->runtime;
++	struct atmel_runtime_data *prtd = runtime->private_data;
++	struct dma_chan *chan = prtd->dma_chan;
++
++	if (prtd->desc)
++		/* already been there: redo the prep job */
++		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
++
++	/* setup dma configuration */
++	atmel_pcm_dma_slave_config(substream);
++
++	prtd->desc = chan->device->device_prep_dma_cyclic(chan, prtd->dma_buffer,
++			prtd->period_size * prtd->periods,
++			prtd->period_size,
++			substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
++			DMA_TO_DEVICE : DMA_FROM_DEVICE);
++	if (!prtd->desc) {
++		dev_err(&chan->dev->device, "cannot prepare slave dma\n");
++		return -EINVAL;
++	}
++
++	prtd->desc->callback = audio_dma_irq;
++	prtd->desc->callback_param = substream;
++
++	return 0;
++}
+ 
+ /*--------------------------------------------------------------------------*\
+  * PCM operations
+@@ -172,6 +351,7 @@ static int atmel_pcm_hw_params(struct snd_pcm_substream *substream,
+ 	struct snd_pcm_runtime *runtime = substream->runtime;
+ 	struct atmel_runtime_data *prtd = runtime->private_data;
+ 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	int ret;
+ 
+ 	/* this may get called several times by oss emulation
+ 	 * with different params */
+@@ -180,15 +360,35 @@ static int atmel_pcm_hw_params(struct snd_pcm_substream *substream,
+ 	runtime->dma_bytes = params_buffer_bytes(params);
+ 
+ 	prtd->params = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
+-	prtd->params->dma_intr_handler = atmel_pcm_dma_irq;
+ 
+ 	prtd->dma_buffer = runtime->dma_addr;
+ 	prtd->dma_buffer_end = runtime->dma_addr + runtime->dma_bytes;
+ 	prtd->period_size = params_period_bytes(params);
++	prtd->periods = params_periods(params);
++
++	if (ssc_use_dmaengine()) {
++		if (prtd->dma_chan == NULL) {
++			ret = atmel_pcm_dma_alloc(substream, params);
++			if (ret)
++				return ret;
++		}
++		ret = atmel_pcm_dma_prep(substream);
++		if (ret) {
++			dma_release_channel(prtd->dma_chan);
++			prtd->dma_chan = NULL;
++			return ret;
++		}
++
++		prtd->params->dma_intr_handler = atmel_pcm_dma_irq;
++	} else {
++		prtd->params->dma_intr_handler = atmel_pcm_pdc_irq;
++	}
+ 
+ 	pr_debug("atmel-pcm: "
+-		"hw_params: DMA for %s initialized "
++		"hw_params: %s%s for %s initialized "
+ 		"(dma_bytes=%u, period_size=%u)\n",
++		prtd->dma_chan ? "DMA " : "PDC",
++		prtd->dma_chan ? dma_chan_name(prtd->dma_chan): "",
+ 		prtd->params->name,
+ 		runtime->dma_bytes,
+ 		prtd->period_size);
+@@ -201,15 +401,31 @@ static int atmel_pcm_hw_free(struct snd_pcm_substream *substream)
+ 	struct atmel_pcm_dma_params *params = prtd->params;
+ 
+ 	if (params != NULL) {
+-		ssc_writex(params->ssc->regs, SSC_PDC_PTCR,
+-			   params->mask->pdc_disable);
++		if (ssc_use_dmaengine()) {
++			struct dma_chan *chan = prtd->dma_chan;
++
++			if (chan) {
++				chan->device->device_control(chan,
++							DMA_TERMINATE_ALL, 0);
++				prtd->cookie = 0;
++				prtd->desc = NULL;
++				dma_release_channel(chan);
++				prtd->dma_chan = NULL;
++			}
++		} else {
++			ssc_writex(params->ssc->regs, SSC_PDC_PTCR,
++				   params->mask->pdc_disable);
++		}
+ 		prtd->params->dma_intr_handler = NULL;
+ 	}
+ 
+ 	return 0;
+ }
+ 
+-static int atmel_pcm_prepare(struct snd_pcm_substream *substream)
++/*--------------------------------------------------------------------------*\
++ * PCM callbacks using PDC
++\*--------------------------------------------------------------------------*/
++static int atmel_pcm_pdc_prepare(struct snd_pcm_substream *substream)
+ {
+ 	struct atmel_runtime_data *prtd = substream->runtime->private_data;
+ 	struct atmel_pcm_dma_params *params = prtd->params;
+@@ -221,7 +437,7 @@ static int atmel_pcm_prepare(struct snd_pcm_substream *substream)
+ 	return 0;
+ }
+ 
+-static int atmel_pcm_trigger(struct snd_pcm_substream *substream,
++static int atmel_pcm_pdc_trigger(struct snd_pcm_substream *substream,
+ 	int cmd)
+ {
+ 	struct snd_pcm_runtime *rtd = substream->runtime;
+@@ -240,13 +456,13 @@ static int atmel_pcm_trigger(struct snd_pcm_substream *substream,
+ 		ssc_writex(params->ssc->regs, params->pdc->xpr,
+ 			   prtd->period_ptr);
+ 		ssc_writex(params->ssc->regs, params->pdc->xcr,
+-			   prtd->period_size / params->pdc_xfer_size);
++			   prtd->period_size / params->data_xfer_size);
+ 
+ 		prtd->period_ptr += prtd->period_size;
+ 		ssc_writex(params->ssc->regs, params->pdc->xnpr,
+ 			   prtd->period_ptr);
+ 		ssc_writex(params->ssc->regs, params->pdc->xncr,
+-			   prtd->period_size / params->pdc_xfer_size);
++			   prtd->period_size / params->data_xfer_size);
+ 
+ 		pr_debug("atmel-pcm: trigger: "
+ 			"period_ptr=%lx, xpr=%u, "
+@@ -264,7 +480,7 @@ static int atmel_pcm_trigger(struct snd_pcm_substream *substream,
+ 
+ 		pr_debug("sr=%u imr=%u\n",
+ 			ssc_readx(params->ssc->regs, SSC_SR),
+-			ssc_readx(params->ssc->regs, SSC_IER));
++			ssc_readx(params->ssc->regs, SSC_IMR));
+ 		break;		/* SNDRV_PCM_TRIGGER_START */
+ 
+ 	case SNDRV_PCM_TRIGGER_STOP:
+@@ -287,7 +503,7 @@ static int atmel_pcm_trigger(struct snd_pcm_substream *substream,
+ 	return ret;
+ }
+ 
+-static snd_pcm_uframes_t atmel_pcm_pointer(
++static snd_pcm_uframes_t atmel_pcm_pdc_pointer(
+ 	struct snd_pcm_substream *substream)
+ {
+ 	struct snd_pcm_runtime *runtime = substream->runtime;
+@@ -305,13 +521,109 @@ static snd_pcm_uframes_t atmel_pcm_pointer(
+ 	return x;
+ }
+ 
++/*--------------------------------------------------------------------------*\
++ * PCM callbacks using DMAENGINE
++\*--------------------------------------------------------------------------*/
++static int atmel_pcm_dma_prepare(struct snd_pcm_substream *substream)
++{
++	struct atmel_runtime_data *prtd = substream->runtime->private_data;
++	struct atmel_pcm_dma_params *params = prtd->params;
++
++	ssc_writex(params->ssc->regs, SSC_IDR, params->mask->ssc_error);
++	return 0;
++}
++
++static int atmel_pcm_dma_trigger(struct snd_pcm_substream *substream,
++	int cmd)
++{
++	struct snd_pcm_runtime *rtd = substream->runtime;
++	struct atmel_runtime_data *prtd = rtd->private_data;
++	struct atmel_pcm_dma_params *params = prtd->params;
++	dma_cookie_t cookie;
++	int ret = 0;
++
++	pr_debug("atmel-pcm: trigger %d: buffer_size = %ld,"
++		" dma_area = %p, dma_bytes = %u\n",
++		cmd, rtd->buffer_size, rtd->dma_area, rtd->dma_bytes);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++
++		if (prtd->cookie < DMA_MIN_COOKIE) {
++			cookie = prtd->desc->tx_submit(prtd->desc);
++			if (dma_submit_error(cookie)) {
++				ret = -EINVAL;
++				break;
++			}
++			prtd->cookie = cookie;
++			prtd->period_ptr = prtd->dma_buffer;
++		}
++
++
++		pr_debug("atmel-pcm: trigger: start sr=0x%08x imr=0x%08u\n",
++			ssc_readx(params->ssc->regs, SSC_SR),
++			ssc_readx(params->ssc->regs, SSC_IMR));
++
++		/* fallback */
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++	case SNDRV_PCM_TRIGGER_RESUME:
++		prtd->dma_chan->device->device_control(prtd->dma_chan,
++							DMA_RESUME, 0);
++
++		/* It not already done or comming from xrun state */
++		ssc_readx(params->ssc->regs, SSC_SR);
++		ssc_writex(params->ssc->regs, SSC_IER, params->mask->ssc_error);
++		ssc_writex(params->ssc->regs, SSC_CR, params->mask->ssc_enable);
++
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++		pr_debug("atmel-pcm: trigger: stop cmd = %d\n", cmd);
++
++		ssc_writex(params->ssc->regs, SSC_IDR, params->mask->ssc_error);
++
++		/* fallback */
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++		prtd->dma_chan->device->device_control(prtd->dma_chan,
++							DMA_PAUSE, 0);
++		break;
++	default:
++		ret = -EINVAL;
++	}
++
++	return ret;
++}
++
++static snd_pcm_uframes_t atmel_pcm_dma_pointer(
++	struct snd_pcm_substream *substream)
++{
++	struct snd_pcm_runtime *runtime = substream->runtime;
++	struct atmel_runtime_data *prtd = runtime->private_data;
++	snd_pcm_uframes_t x;
++
++	dev_vdbg(substream->pcm->card->dev, "%s: 0x%08x %ld\n",
++		__func__, prtd->period_ptr,
++		bytes_to_frames(runtime, prtd->period_ptr - prtd->dma_buffer));
++
++	x = bytes_to_frames(runtime, prtd->period_ptr - prtd->dma_buffer);
++
++	if (x >= runtime->buffer_size)
++		x = 0;
++
++	return x;
++}
++
++
++/*--------------------------------------------------------------------------*\
++ * PCM open/close/mmap
++\*--------------------------------------------------------------------------*/
+ static int atmel_pcm_open(struct snd_pcm_substream *substream)
+ {
+ 	struct snd_pcm_runtime *runtime = substream->runtime;
+ 	struct atmel_runtime_data *prtd;
+ 	int ret = 0;
+ 
+-	snd_soc_set_runtime_hwparams(substream, &atmel_pcm_hardware);
++	snd_soc_set_runtime_hwparams(substream, atmel_pcm_hardware);
+ 
+ 	/* ensure that buffer size is a multiple of period size */
+ 	ret = snd_pcm_hw_constraint_integer(runtime,
+@@ -352,9 +664,9 @@ static struct snd_pcm_ops atmel_pcm_ops = {
+ 	.ioctl		= snd_pcm_lib_ioctl,
+ 	.hw_params	= atmel_pcm_hw_params,
+ 	.hw_free	= atmel_pcm_hw_free,
+-	.prepare	= atmel_pcm_prepare,
+-	.trigger	= atmel_pcm_trigger,
+-	.pointer	= atmel_pcm_pointer,
++	.prepare	= atmel_pcm_pdc_prepare,
++	.trigger	= atmel_pcm_pdc_trigger,
++	.pointer	= atmel_pcm_pdc_pointer,
+ 	.mmap		= atmel_pcm_mmap,
+ };
+ 
+@@ -426,14 +738,16 @@ static int atmel_pcm_suspend(struct snd_soc_dai *dai)
+ 	prtd = runtime->private_data;
+ 	params = prtd->params;
+ 
+-	/* disable the PDC and save the PDC registers */
++	if (!ssc_use_dmaengine()) {
++		/* disable the PDC and save the PDC registers */
+ 
+-	ssc_writel(params->ssc->regs, PDC_PTCR, params->mask->pdc_disable);
++		ssc_writel(params->ssc->regs, PDC_PTCR, params->mask->pdc_disable);
+ 
+-	prtd->pdc_xpr_save = ssc_readx(params->ssc->regs, params->pdc->xpr);
+-	prtd->pdc_xcr_save = ssc_readx(params->ssc->regs, params->pdc->xcr);
+-	prtd->pdc_xnpr_save = ssc_readx(params->ssc->regs, params->pdc->xnpr);
+-	prtd->pdc_xncr_save = ssc_readx(params->ssc->regs, params->pdc->xncr);
++		prtd->pdc_xpr_save = ssc_readx(params->ssc->regs, params->pdc->xpr);
++		prtd->pdc_xcr_save = ssc_readx(params->ssc->regs, params->pdc->xcr);
++		prtd->pdc_xnpr_save = ssc_readx(params->ssc->regs, params->pdc->xnpr);
++		prtd->pdc_xncr_save = ssc_readx(params->ssc->regs, params->pdc->xncr);
++	}
+ 
+ 	return 0;
+ }
+@@ -450,13 +764,15 @@ static int atmel_pcm_resume(struct snd_soc_dai *dai)
+ 	prtd = runtime->private_data;
+ 	params = prtd->params;
+ 
+-	/* restore the PDC registers and enable the PDC */
+-	ssc_writex(params->ssc->regs, params->pdc->xpr, prtd->pdc_xpr_save);
+-	ssc_writex(params->ssc->regs, params->pdc->xcr, prtd->pdc_xcr_save);
+-	ssc_writex(params->ssc->regs, params->pdc->xnpr, prtd->pdc_xnpr_save);
+-	ssc_writex(params->ssc->regs, params->pdc->xncr, prtd->pdc_xncr_save);
++	if (!ssc_use_dmaengine()) {
++		/* restore the PDC registers and enable the PDC */
++		ssc_writex(params->ssc->regs, params->pdc->xpr, prtd->pdc_xpr_save);
++		ssc_writex(params->ssc->regs, params->pdc->xcr, prtd->pdc_xcr_save);
++		ssc_writex(params->ssc->regs, params->pdc->xnpr, prtd->pdc_xnpr_save);
++		ssc_writex(params->ssc->regs, params->pdc->xncr, prtd->pdc_xncr_save);
+ 
+-	ssc_writel(params->ssc->regs, PDC_PTCR, params->mask->pdc_enable);
++		ssc_writel(params->ssc->regs, PDC_PTCR, params->mask->pdc_enable);
++	}
+ 	return 0;
+ }
+ #else
+@@ -495,6 +811,15 @@ static struct platform_driver atmel_pcm_driver = {
+ 
+ static int __init snd_atmel_pcm_init(void)
+ {
++	if (ssc_use_dmaengine()) {
++		atmel_pcm_ops.prepare = atmel_pcm_dma_prepare;
++		atmel_pcm_ops.trigger = atmel_pcm_dma_trigger;
++		atmel_pcm_ops.pointer = atmel_pcm_dma_pointer;
++
++		atmel_pcm_hardware = &atmel_pcm_dma_hardware;
++	} else {
++		atmel_pcm_hardware = &atmel_pcm_pdc_hardware;
++	}
+ 	return platform_driver_register(&atmel_pcm_driver);
+ }
+ module_init(snd_atmel_pcm_init);
+diff --git a/sound/soc/atmel/atmel-pcm.h b/sound/soc/atmel/atmel-pcm.h
+index 5e0a95e..b007376 100644
+--- a/sound/soc/atmel/atmel-pcm.h
++++ b/sound/soc/atmel/atmel-pcm.h
+@@ -50,6 +50,7 @@ struct atmel_pdc_regs {
+ struct atmel_ssc_mask {
+ 	u32	ssc_enable;		/* SSC recv/trans enable */
+ 	u32	ssc_disable;		/* SSC recv/trans disable */
++	u32	ssc_error;		/* SSC error conditions */
+ 	u32	ssc_endx;		/* SSC ENDTX or ENDRX */
+ 	u32	ssc_endbuf;		/* SSC TXBUFE or RXBUFF */
+ 	u32	pdc_enable;		/* PDC recv/trans enable */
+@@ -66,7 +67,8 @@ struct atmel_ssc_mask {
+  */
+ struct atmel_pcm_dma_params {
+ 	char *name;			/* stream identifier */
+-	int pdc_xfer_size;		/* PDC counter increment in bytes */
++	int data_xfer_size;		/* PDC counter increment in bytes,
++					   DMA data transfer size in bytes */
+ 	struct ssc_device *ssc;		/* SSC device for stream */
+ 	struct atmel_pdc_regs *pdc;	/* PDC receive or transmit registers */
+ 	struct atmel_ssc_mask *mask;	/* SSC & PDC status bits */
+diff --git a/sound/soc/atmel/atmel_ssc_dai.c b/sound/soc/atmel/atmel_ssc_dai.c
+index a7a7bbc..9412fc3 100644
+--- a/sound/soc/atmel/atmel_ssc_dai.c
++++ b/sound/soc/atmel/atmel_ssc_dai.c
+@@ -48,7 +48,8 @@
+ #include "atmel_ssc_dai.h"
+ 
+ 
+-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
++#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) \
++	|| defined(CONFIG_ARCH_AT91SAM9X5)
+ #define NUM_SSC_DEVICES		1
+ #else
+ #define NUM_SSC_DEVICES		3
+@@ -86,6 +87,7 @@ static struct atmel_ssc_mask ssc_tx_mask = {
+ static struct atmel_ssc_mask ssc_rx_mask = {
+ 	.ssc_enable	= SSC_BIT(CR_RXEN),
+ 	.ssc_disable	= SSC_BIT(CR_RXDIS),
++	.ssc_error	= SSC_BIT(SR_OVRUN),
+ 	.ssc_endx	= SSC_BIT(SR_ENDRX),
+ 	.ssc_endbuf	= SSC_BIT(SR_RXBUFF),
+ 	.pdc_enable	= ATMEL_PDC_RXTEN,
+@@ -183,7 +185,8 @@ static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
+ 		if ((dma_params != NULL) &&
+ 			(dma_params->dma_intr_handler != NULL)) {
+ 			ssc_substream_mask = (dma_params->mask->ssc_endx |
+-					dma_params->mask->ssc_endbuf);
++					dma_params->mask->ssc_endbuf |
++					dma_params->mask->ssc_error);
+ 			if (ssc_sr & ssc_substream_mask) {
+ 				dma_params->dma_intr_handler(ssc_sr,
+ 						dma_params->
+@@ -376,19 +379,19 @@ static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
+ 	switch (params_format(params)) {
+ 	case SNDRV_PCM_FORMAT_S8:
+ 		bits = 8;
+-		dma_params->pdc_xfer_size = 1;
++		dma_params->data_xfer_size = 1;
+ 		break;
+ 	case SNDRV_PCM_FORMAT_S16_LE:
+ 		bits = 16;
+-		dma_params->pdc_xfer_size = 2;
++		dma_params->data_xfer_size = 2;
+ 		break;
+ 	case SNDRV_PCM_FORMAT_S24_LE:
+ 		bits = 24;
+-		dma_params->pdc_xfer_size = 4;
++		dma_params->data_xfer_size = 4;
+ 		break;
+ 	case SNDRV_PCM_FORMAT_S32_LE:
+ 		bits = 32;
+-		dma_params->pdc_xfer_size = 4;
++		dma_params->data_xfer_size = 4;
+ 		break;
+ 	default:
+ 		printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
+@@ -561,15 +564,17 @@ static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
+ 		/* Reset the SSC and its PDC registers */
+ 		ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
+ 
+-		ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
+-		ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
+-		ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
+-		ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
++		if (!ssc_use_dmaengine()) {
++			ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
++			ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
++			ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
++			ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
+ 
+-		ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
+-		ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
+-		ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
+-		ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
++			ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
++			ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
++			ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
++			ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
++		}
+ 
+ 		ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
+ 				ssc_p->name, ssc_p);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0053-sound-sam9x5_wm8731-machine-driver-for-at91sam9x5-wm.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0053-sound-sam9x5_wm8731-machine-driver-for-at91sam9x5-wm.patch
new file mode 100644
index 0000000..7efbec5
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0053-sound-sam9x5_wm8731-machine-driver-for-at91sam9x5-wm.patch
@@ -0,0 +1,291 @@
+From 0aa157c9e71ccccf3abc30fa37eb5c95b392978d Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 19 May 2011 17:57:48 +0200
+Subject: [PATCH 053/107] sound: sam9x5_wm8731: machine driver for at91sam9x5
+ wm8731 boards
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Description of the Asoc machine driver for an at91sam9x5 based board
+with a wm8731 audio DAC. Wm8731 is clocked by a crystal and used as a
+master on the SSC/I2S interface. Its connections are a headphone jack
+and an Line input jack.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ sound/soc/atmel/Kconfig         |    9 ++
+ sound/soc/atmel/Makefile        |    2 +
+ sound/soc/atmel/sam9x5_wm8731.c |  222 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 233 insertions(+), 0 deletions(-)
+ create mode 100644 sound/soc/atmel/sam9x5_wm8731.c
+
+diff --git a/sound/soc/atmel/Kconfig b/sound/soc/atmel/Kconfig
+index bee3c94..2fdb037 100644
+--- a/sound/soc/atmel/Kconfig
++++ b/sound/soc/atmel/Kconfig
+@@ -24,6 +24,15 @@ config SND_AT91_SOC_SAM9G20_WM8731
+ 	  Say Y if you want to add support for SoC audio on WM8731-based
+ 	  AT91sam9g20 evaluation board.
+ 
++config SND_AT91_SOC_SAM9X5_WM8731
++	tristate "SoC Audio support for WM8731-based at91sam9x5 board"
++	depends on ATMEL_SSC && SND_ATMEL_SOC && ARCH_AT91SAM9X5
++	select SND_ATMEL_SOC_SSC
++	select SND_SOC_WM8731
++	help
++	  Say Y if you want to add support for audio SoC on an
++	  at91sam9x5 based board that is using WM8731 codec.
++
+ config SND_AT32_SOC_PLAYPAQ
+         tristate "SoC Audio support for PlayPaq with WM8510"
+         depends on SND_ATMEL_SOC && BOARD_PLAYPAQ && AT91_PROGRAMMABLE_CLOCKS
+diff --git a/sound/soc/atmel/Makefile b/sound/soc/atmel/Makefile
+index e7ea56b..c5f2b62 100644
+--- a/sound/soc/atmel/Makefile
++++ b/sound/soc/atmel/Makefile
+@@ -7,10 +7,12 @@ obj-$(CONFIG_SND_ATMEL_SOC_SSC) += snd-soc-atmel_ssc_dai.o
+ 
+ # AT91 Machine Support
+ snd-soc-sam9g20-wm8731-objs := sam9g20_wm8731.o
++snd-soc-sam9x5-wm8731-objs := sam9x5_wm8731.o
+ 
+ # AT32 Machine Support
+ snd-soc-playpaq-objs := playpaq_wm8510.o
+ 
+ obj-$(CONFIG_SND_AT91_SOC_SAM9G20_WM8731) += snd-soc-sam9g20-wm8731.o
++obj-$(CONFIG_SND_AT91_SOC_SAM9X5_WM8731) += snd-soc-sam9x5-wm8731.o
+ obj-$(CONFIG_SND_AT32_SOC_PLAYPAQ) += snd-soc-playpaq.o
+ obj-$(CONFIG_SND_AT91_SOC_AFEB9260) += snd-soc-afeb9260.o
+diff --git a/sound/soc/atmel/sam9x5_wm8731.c b/sound/soc/atmel/sam9x5_wm8731.c
+new file mode 100644
+index 0000000..009e033
+--- /dev/null
++++ b/sound/soc/atmel/sam9x5_wm8731.c
+@@ -0,0 +1,222 @@
++/*
++ * sam9x5_wm8731   --	SoC audio for AT91SAM9X5-based boards
++ * 			that are using WM8731 as codec.
++ *
++ *  Copyright (C) 2011 Atmel,
++ *  		  Nicolas Ferre <nicolas.ferre@atmel.com>
++ *
++ * Based on sam9g20_wm8731.c by:
++ * Sedji Gaouaou <sedji.gaouaou@atmel.com>
++ *
++ * GPL
++ */
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/timer.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/i2c.h>
++
++#include <linux/atmel-ssc.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++
++#include <asm/mach-types.h>
++#include <mach/hardware.h>
++#include <mach/gpio.h>
++
++#include "../codecs/wm8731.h"
++#include "atmel-pcm.h"
++#include "atmel_ssc_dai.h"
++
++#define MCLK_RATE 12288000
++
++static int at91sam9x5ek_hw_params(struct snd_pcm_substream *substream,
++	struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_dai *codec_dai = rtd->codec_dai;
++	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++	int ret;
++
++	/* set codec DAI configuration */
++	ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
++		SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
++	if (ret < 0)
++		return ret;
++
++	/* set cpu DAI configuration */
++	ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
++		SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
++	if (ret < 0)
++		return ret;
++
++	/* set the codec system clock for DAC and ADC */
++	ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
++		MCLK_RATE, SND_SOC_CLOCK_IN);
++	if (ret < 0) {
++		printk(KERN_ERR "ASoC: Failed to set WM8731 SYSCLK: %d\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static struct snd_soc_ops at91sam9x5ek_ops = {
++	.hw_params = at91sam9x5ek_hw_params,
++};
++
++/*
++ * Audio paths on at91sam9x5ek board:
++ *
++ *  |A| ------------> |      | ---R----> Headphone Jack
++ *  |T| <----\        |  WM  | ---L--/
++ *  |9| ---> CLK <--> | 8751 | <--R----- Line In Jack
++ *  |1| <------------ |      | <--L--/
++ */
++static const struct snd_soc_dapm_widget at91sam9x5ek_dapm_widgets[] = {
++	SND_SOC_DAPM_HP("Headphone Jack", NULL),
++	SND_SOC_DAPM_LINE("Line In Jack", NULL),
++};
++
++static const struct snd_soc_dapm_route intercon[] = {
++	/* headphone jack connected to HPOUT */
++	{"Headphone Jack", NULL, "RHPOUT"},
++	{"Headphone Jack", NULL, "LHPOUT"},
++
++	/* line in jack connected LINEIN */
++	{"LLINEIN", NULL, "Line In Jack"},
++	{"RLINEIN", NULL, "Line In Jack"},
++};
++
++/*
++ * Logic for a wm8731 as connected on a at91sam9x5 based board.
++ */
++static int at91sam9x5ek_wm8731_init(struct snd_soc_pcm_runtime *rtd)
++{
++	struct snd_soc_codec *codec = rtd->codec;
++	struct snd_soc_dai *codec_dai = rtd->codec_dai;
++	struct snd_soc_dapm_context *dapm = &codec->dapm;
++
++	printk(KERN_DEBUG
++			"ASoC: at91sam9x5_wm8731"
++			": at91sam9x5ek_wm8731_init() called\n");
++
++	/* remove some not supported rates in relation with clock
++	 * provided to the wm8731 codec */
++	switch (MCLK_RATE) {
++	case 12288000:
++		codec_dai->driver->playback.rates &= SNDRV_PCM_RATE_8000 |
++						     SNDRV_PCM_RATE_32000 |
++						     SNDRV_PCM_RATE_48000 |
++						     SNDRV_PCM_RATE_96000;
++		codec_dai->driver->capture.rates &= SNDRV_PCM_RATE_8000 |
++						    SNDRV_PCM_RATE_32000 |
++						    SNDRV_PCM_RATE_48000 |
++						    SNDRV_PCM_RATE_96000;
++		break;
++	case 12000000:
++		/* all wm8731 rates supported */
++		break;
++	default:
++		printk(KERN_ERR "ASoC: Codec Master clock rate not defined\n");
++		return -EINVAL;
++	}
++
++	/* set not connected pins */
++	snd_soc_dapm_nc_pin(dapm, "Mic Bias");
++	snd_soc_dapm_nc_pin(dapm, "MICIN");
++	snd_soc_dapm_nc_pin(dapm, "LOUT");
++	snd_soc_dapm_nc_pin(dapm, "ROUT");
++
++	/* add specific widgets */
++	snd_soc_dapm_new_controls(dapm, at91sam9x5ek_dapm_widgets,
++				  ARRAY_SIZE(at91sam9x5ek_dapm_widgets));
++	/* set up specific audio path interconnects */
++	snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
++
++	/* always connected */
++	snd_soc_dapm_enable_pin(dapm, "Headphone Jack");
++	snd_soc_dapm_enable_pin(dapm, "Line In Jack");
++
++	/* signal a DAPM event */
++	snd_soc_dapm_sync(dapm);
++	return 0;
++}
++
++static struct snd_soc_dai_link at91sam9x5ek_dai = {
++	.name = "WM8731",
++	.stream_name = "WM8731 PCM",
++	.cpu_dai_name = "atmel-ssc-dai.0",
++	.codec_dai_name = "wm8731-hifi",
++	.init = at91sam9x5ek_wm8731_init,
++	.platform_name = "atmel-pcm-audio",
++	.codec_name = "wm8731-codec.0-001a",
++	.ops = &at91sam9x5ek_ops,
++};
++
++static struct snd_soc_card snd_soc_at91sam9x5ek = {
++	.name = "AT91SAM9X5",
++	.dai_link = &at91sam9x5ek_dai,
++	.num_links = 1,
++};
++
++static struct platform_device *at91sam9x5ek_snd_device;
++
++static int __init at91sam9x5ek_init(void)
++{
++	int ret;
++
++	if (!machine_is_at91sam9x5ek())
++		return -ENODEV;
++
++	ret = atmel_ssc_set_audio(0);
++	if (ret != 0) {
++		pr_err("ASoC: Failed to set SSC 0 for audio: %d\n", ret);
++		goto err;
++	}
++
++	at91sam9x5ek_snd_device = platform_device_alloc("soc-audio", -1);
++	if (!at91sam9x5ek_snd_device) {
++		printk(KERN_ERR "ASoC: Platform device allocation failed\n");
++		ret = -ENOMEM;
++		goto err;
++	}
++
++	platform_set_drvdata(at91sam9x5ek_snd_device,
++			&snd_soc_at91sam9x5ek);
++
++	ret = platform_device_add(at91sam9x5ek_snd_device);
++	if (ret) {
++		printk(KERN_ERR "ASoC: Platform device allocation failed\n");
++		goto err_device_add;
++	}
++
++	printk(KERN_INFO "ASoC: at91sam9x5ek_init ok\n");
++
++	return ret;
++
++err_device_add:
++	platform_device_put(at91sam9x5ek_snd_device);
++err:
++	return ret;
++}
++
++static void __exit at91sam9x5ek_exit(void)
++{
++	platform_device_unregister(at91sam9x5ek_snd_device);
++	at91sam9x5ek_snd_device = NULL;
++}
++
++module_init(at91sam9x5ek_init);
++module_exit(at91sam9x5ek_exit);
++
++/* Module information */
++MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
++MODULE_DESCRIPTION("ALSA SoC machine driver for AT91SAM9x5 - WM8731");
++MODULE_LICENSE("GPL");
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0054-mtd-atmel_nand-do-not-scream-while-using-PIO-instead.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0054-mtd-atmel_nand-do-not-scream-while-using-PIO-instead.patch
new file mode 100644
index 0000000..2bbd506
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0054-mtd-atmel_nand-do-not-scream-while-using-PIO-instead.patch
@@ -0,0 +1,33 @@
+From a1b192d1b61c8a67b5e4dfa23ddf58d77b7296bb Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Fri, 20 May 2011 11:35:59 +0200
+Subject: [PATCH 054/107] mtd: atmel_nand: do not scream while using PIO
+ instead of DMA
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/mtd/nand/atmel_nand.c |    2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index e89c8c7..c4e07be 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -296,8 +296,10 @@ static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
+ err_dma:
+ 	dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
+ err_buf:
++#if 0
+ 	if (err != 0)
+ 		dev_warn(host->dev, "Fall back to CPU I/O\n");
++#endif
+ 	return err;
+ }
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0055-MMC-PM-suspend-resume-in-atmel-mci.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0055-MMC-PM-suspend-resume-in-atmel-mci.patch
new file mode 100644
index 0000000..0cb9c71
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0055-MMC-PM-suspend-resume-in-atmel-mci.patch
@@ -0,0 +1,83 @@
+From efa965541f4e6b3a5dd06d65a44d7a85cafd73b8 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Mon, 16 May 2011 14:32:07 +0200
+Subject: [PATCH 055/107] MMC: PM: suspend/resume in atmel-mci
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Take care of slots while going to suspend state.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/mmc/host/atmel-mci.c |   51 ++++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 51 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
+index f6b2552..346f91b 100644
+--- a/drivers/mmc/host/atmel-mci.c
++++ b/drivers/mmc/host/atmel-mci.c
+@@ -1891,8 +1891,59 @@ static int __exit atmci_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++#ifdef CONFIG_PM
++static int atmci_suspend(struct platform_device *pdev, pm_message_t mesg)
++{
++	struct atmel_mci *host = platform_get_drvdata(pdev);
++	struct atmel_mci_slot *slot;
++	int i, ret;
++
++	 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
++		slot = host->slot[i];
++		if (!slot)
++			continue;
++		ret = mmc_suspend_host(slot->mmc);
++		if (ret < 0) {
++			while (--i >= 0) {
++				slot = host->slot[i];
++				if (slot)
++					mmc_resume_host(host->slot[i]->mmc);
++			}
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static int atmci_resume(struct platform_device *pdev)
++{
++	struct atmel_mci *host = platform_get_drvdata(pdev);
++	struct atmel_mci_slot *slot;
++	int i, ret;
++
++	for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
++		slot = host->slot[i];
++		if (!slot)
++			continue;
++		ret = mmc_resume_host(slot->mmc);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++#else
++#define atmci_suspend	NULL
++#define atmci_resume	NULL
++#endif
++
++
++
+ static struct platform_driver atmci_driver = {
+ 	.remove		= __exit_p(atmci_remove),
++	.suspend	= atmci_suspend,
++	.resume		= atmci_resume,
+ 	.driver		= {
+ 		.name		= "atmel_mci",
+ 	},
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0056-ASoc-wm8731-fix-wm8731_check_osc-connected-condition.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0056-ASoc-wm8731-fix-wm8731_check_osc-connected-condition.patch
new file mode 100644
index 0000000..9f0e18d
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0056-ASoc-wm8731-fix-wm8731_check_osc-connected-condition.patch
@@ -0,0 +1,37 @@
+From 676d27f65a64deed4d5f5696774c35cfb01bf44e Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 24 May 2011 11:13:47 +0200
+Subject: [PATCH 056/107] ASoc: wm8731: fix wm8731_check_osc() connected
+ condition
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The crystal oscillator is only enabled if the WM8731_SYSCLK_XTAL master clock
+is specified. Fix the connected() struct snd_soc_dapm_route function to take
+this into account. Oscillator is not enabled on machine that need it otherwise.
+
+Machine drivers have to make sure that they use the proper SYSCLK value.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ sound/soc/codecs/wm8731.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c
+index aa55b84..ec176b6 100644
+--- a/sound/soc/codecs/wm8731.c
++++ b/sound/soc/codecs/wm8731.c
+@@ -198,7 +198,7 @@ static int wm8731_check_osc(struct snd_soc_dapm_widget *source,
+ {
+ 	struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(source->codec);
+ 
+-	return wm8731->sysclk_type == WM8731_SYSCLK_MCLK;
++	return wm8731->sysclk_type == WM8731_SYSCLK_XTAL;
+ }
+ 
+ static const struct snd_soc_dapm_route intercon[] = {
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0057-ASoc-sam9g20_wm8731-use-the-proper-SYSCKL-value.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0057-ASoc-sam9g20_wm8731-use-the-proper-SYSCKL-value.patch
new file mode 100644
index 0000000..bc7a352
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0057-ASoc-sam9g20_wm8731-use-the-proper-SYSCKL-value.patch
@@ -0,0 +1,34 @@
+From 7cec4ca2653d0f1053635fa47a60127c0e5b6856 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 24 May 2011 11:24:22 +0200
+Subject: [PATCH 057/107] ASoc: sam9g20_wm8731: use the proper SYSCKL value
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+at91sam9g20 is providing master clock to wm8731: not using a crystal but an
+external MCLK. We can avoid conflict and save power using WM8731_SYSCLK_MCLK as
+we do not need oscillator to be powered.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ sound/soc/atmel/sam9g20_wm8731.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/sound/soc/atmel/sam9g20_wm8731.c b/sound/soc/atmel/sam9g20_wm8731.c
+index af3c730..91cc80d 100644
+--- a/sound/soc/atmel/sam9g20_wm8731.c
++++ b/sound/soc/atmel/sam9g20_wm8731.c
+@@ -146,7 +146,7 @@ static int at91sam9g20ek_wm8731_init(struct snd_soc_pcm_runtime *rtd)
+ 			"at91sam9g20ek_wm8731 "
+ 			": at91sam9g20ek_wm8731_init() called\n");
+ 
+-	ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
++	ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_MCLK,
+ 		MCLK_RATE, SND_SOC_CLOCK_IN);
+ 	if (ret < 0) {
+ 		printk(KERN_ERR "Failed to set WM8731 SYSCLK: %d\n", ret);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0058-sound-atmel_ssc_dai-PM-actually-stopping-clock-on-su.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0058-sound-atmel_ssc_dai-PM-actually-stopping-clock-on-su.patch
new file mode 100644
index 0000000..e007def
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0058-sound-atmel_ssc_dai-PM-actually-stopping-clock-on-su.patch
@@ -0,0 +1,73 @@
+From e1ee811e7bbcce6728f7cd28153a894991c2c230 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Wed, 25 May 2011 19:36:51 +0200
+Subject: [PATCH 058/107] sound: atmel_ssc_dai: PM: actually stopping clock on
+ suspend/resume
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Stop SSC clock on suspend/resume cycle checking if the controller is actually
+initialized. This will save power while sleeping.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ sound/soc/atmel/atmel_ssc_dai.c |   20 +++++++++++++-------
+ 1 files changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/sound/soc/atmel/atmel_ssc_dai.c b/sound/soc/atmel/atmel_ssc_dai.c
+index 9412fc3..43cce80 100644
+--- a/sound/soc/atmel/atmel_ssc_dai.c
++++ b/sound/soc/atmel/atmel_ssc_dai.c
+@@ -631,12 +631,10 @@ static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
+ #ifdef CONFIG_PM
+ static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
+ {
+-	struct atmel_ssc_info *ssc_p;
++	struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
+ 
+ 	if (!cpu_dai->active)
+-		return 0;
+-
+-	ssc_p = &ssc_info[cpu_dai->id];
++		goto out;
+ 
+ 	/* Save the status register before disabling transmit and receive */
+ 	ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
+@@ -652,6 +650,11 @@ static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
+ 	ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
+ 	ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
+ 
++out:
++	if (ssc_p->initialized) {
++		pr_debug("atmel_ssc_dai: suspend - stop clock\n");
++		clk_disable(ssc_p->ssc->clk);
++	}
+ 	return 0;
+ }
+ 
+@@ -659,14 +662,17 @@ static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
+ 
+ static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
+ {
+-	struct atmel_ssc_info *ssc_p;
++	struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
+ 	u32 cr;
+ 
++	if (ssc_p->initialized) {
++		pr_debug("atmel_ssc_dai: resume - restart clock\n");
++		clk_enable(ssc_p->ssc->clk);
++	}
++
+ 	if (!cpu_dai->active)
+ 		return 0;
+ 
+-	ssc_p = &ssc_info[cpu_dai->id];
+-
+ 	/* restore SSC register settings */
+ 	ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
+ 	ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0059-ARM-at91-sam9x5-increase-CONSISTENT_DMA_SIZE.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0059-ARM-at91-sam9x5-increase-CONSISTENT_DMA_SIZE.patch
new file mode 100644
index 0000000..4c36a8e
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0059-ARM-at91-sam9x5-increase-CONSISTENT_DMA_SIZE.patch
@@ -0,0 +1,29 @@
+From 3cf98b7f7bf07aba4e6292df6e942bfe7e20f735 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Fri, 27 May 2011 09:41:44 +0200
+Subject: [PATCH 059/107] ARM: at91/sam9x5: increase CONSISTENT_DMA_SIZE
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/mach-at91/include/mach/at91sam9x5.h |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
+index c263b46..1219b32 100644
+--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
++++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
+@@ -133,7 +133,7 @@
+ 
+ #define CONFIG_DRAM_BASE	AT91_CHIPSELECT_1
+ 
+-#define CONSISTENT_DMA_SIZE	SZ_4M
++#define CONSISTENT_DMA_SIZE	(14 * SZ_1M)
+ 
+ /*
+  * DMA0 peripheral identifiers
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0060-SPI-atmel_spi-add-bit-in-mode-register-to-prevent-ov.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0060-SPI-atmel_spi-add-bit-in-mode-register-to-prevent-ov.patch
new file mode 100644
index 0000000..c9dbc76
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0060-SPI-atmel_spi-add-bit-in-mode-register-to-prevent-ov.patch
@@ -0,0 +1,130 @@
+From c8701994e8c5e940c2b5694e355ff670e0ddf369 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Fri, 27 May 2011 13:32:55 +0200
+Subject: [PATCH 060/107] SPI: atmel_spi: add bit in mode register to prevent
+ overrun
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add the "WDRBT: Wait Data Read Before Transfer" bit in the mode register for
+controllers that support it (v210 and greater).
+This bit will prevent overruns error in reception.
+
+The modification of cs_activate() is need to preserver this initial
+configuration.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/spi/atmel_spi.c |   24 +++++++++++++++++++-----
+ drivers/spi/atmel_spi.h |    9 +++++++++
+ 2 files changed, 28 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
+index 12d8a81..ca9dab5 100644
+--- a/drivers/spi/atmel_spi.c
++++ b/drivers/spi/atmel_spi.c
+@@ -106,6 +106,15 @@ static bool atmel_spi_is_v2(void)
+ 	return !cpu_is_at91rm9200();
+ }
+ 
++static bool atmel_spi_v21x(struct atmel_spi *as)
++{
++	u32 v;
++
++	v = SPI_BFEXT(VERS, spi_readl(as, VERSION));
++	v &= 0x0ff0;
++	return (v == 0x210);
++}
++
+ /*
+  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
+  * they assume that spi slave device state will not change on deselect, so
+@@ -137,6 +146,7 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
+ 	unsigned active = spi->mode & SPI_CS_HIGH;
+ 	u32 mr;
+ 
++	mr = spi_readl(as, MR);
+ 	if (atmel_spi_is_v2()) {
+ 		/*
+ 		 * Always use CSR0. This ensures that the clock
+@@ -144,9 +154,9 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
+ 		 * toggle the CS.
+ 		 */
+ 		spi_writel(as, CSR0, asd->csr);
+-		spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
+-				| SPI_BIT(MSTR));
+-		mr = spi_readl(as, MR);
++		mr &= (SPI_BIT(MODFDIS) | SPI_BIT(MSTR) | SPI_BIT(WDRBT));
++		mr |= SPI_BF(PCS, 0x0e);
++		spi_writel(as, MR, mr);
+ 		gpio_set_value(asd->npcs_pin, active);
+ 	} else {
+ 		u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
+@@ -161,7 +171,6 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
+ 						csr ^ SPI_BIT(CPOL));
+ 		}
+ 
+-		mr = spi_readl(as, MR);
+ 		mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
+ 		if (spi->chip_select != 0)
+ 			gpio_set_value(asd->npcs_pin, active);
+@@ -1224,6 +1233,7 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
+ 	int			irq;
+ 	struct clk		*clk;
+ 	int			ret;
++	u32			mr;
+ 	struct spi_master	*master;
+ 	struct atmel_spi	*as;
+ 
+@@ -1286,7 +1296,11 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
+ 	clk_enable(clk);
+ 	spi_writel(as, CR, SPI_BIT(SWRST));
+ 	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
+-	spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
++	mr = SPI_BIT(MSTR) | SPI_BIT(MODFDIS);
++	if (atmel_spi_v21x(as))
++		mr |= SPI_BIT(WDRBT); /* Prevent overrun errors */
++	spi_writel(as, MR, mr);
++
+ 
+ 	ret = atmel_spi_configure_dma(master);
+ 	if (ret)
+diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
+index 6e06b6a..e3a08ac 100644
+--- a/drivers/spi/atmel_spi.h
++++ b/drivers/spi/atmel_spi.h
+@@ -23,6 +23,7 @@
+ #define SPI_CSR1				0x0034
+ #define SPI_CSR2				0x0038
+ #define SPI_CSR3				0x003c
++#define SPI_VERSION				0x00fc
+ #define SPI_RPR					0x0100
+ #define SPI_RCR					0x0104
+ #define SPI_TPR					0x0108
+@@ -55,6 +56,8 @@
+ #define SPI_FDIV_SIZE				1
+ #define SPI_MODFDIS_OFFSET			4
+ #define SPI_MODFDIS_SIZE			1
++#define SPI_WDRBT_OFFSET			5
++#define SPI_WDRBT_SIZE				1
+ #define SPI_LLB_OFFSET				7
+ #define SPI_LLB_SIZE				1
+ #define SPI_PCS_OFFSET				16
+@@ -110,6 +113,12 @@
+ #define SPI_DLYBCT_OFFSET			24
+ #define SPI_DLYBCT_SIZE				8
+ 
++/* Bitfields in VERSION */
++#define SPI_VERS_OFFSET				0
++#define SPI_VERS_SIZE				12
++#define SPI_MFN_OFFSET				16
++#define SPI_MFN_SIZE				3
++
+ /* Bitfields in RCR */
+ #define SPI_RXCTR_OFFSET			0
+ #define SPI_RXCTR_SIZE				16
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0061-media-at91sam9x5-video-new-driver-for-the-high-end-o.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0061-media-at91sam9x5-video-new-driver-for-the-high-end-o.patch
new file mode 100644
index 0000000..5d930dc
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0061-media-at91sam9x5-video-new-driver-for-the-high-end-o.patch
@@ -0,0 +1,1530 @@
+From 18e4aead1dcdb0493291049f928d9378082b71bb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Tue, 24 May 2011 23:45:21 +0200
+Subject: [PATCH 061/107] media/at91sam9x5-video: new driver for the high end
+ overlay on at91sam9x5
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/media/video/Kconfig            |    8 +
+ drivers/media/video/Makefile           |    1 +
+ drivers/media/video/at91sam9x5-video.c | 1440 ++++++++++++++++++++++++++++++++
+ drivers/video/atmel_lcdfb.c            |    7 +-
+ 4 files changed, 1453 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/media/video/at91sam9x5-video.c
+
+diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
+index 00f51dd..c937e4d 100644
+--- a/drivers/media/video/Kconfig
++++ b/drivers/media/video/Kconfig
+@@ -81,6 +81,14 @@ menuconfig VIDEO_CAPTURE_DRIVERS
+ 
+ if VIDEO_CAPTURE_DRIVERS && VIDEO_V4L2
+ 
++config VIDEO_AT91SAM9X5
++	tristate "Support for AT91SAM9X5 Video"
++	depends on ARCH_AT91SAM9X5
++	depends on VIDEO_V4L2
++	select VIDEOBUF2_DMA_CONTIG
++	help
++	  support for the "High End Overlay" found in Atmel's AT91SAM9X5 SoCs.
++
+ config VIDEO_ADV_DEBUG
+ 	bool "Enable advanced debug functionality"
+ 	default n
+diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
+index ace5d8b..5a7620d 100644
+--- a/drivers/media/video/Makefile
++++ b/drivers/media/video/Makefile
+@@ -105,6 +105,7 @@ obj-$(CONFIG_VIDEO_MXB) += mxb.o
+ obj-$(CONFIG_VIDEO_HEXIUM_ORION) += hexium_orion.o
+ obj-$(CONFIG_VIDEO_HEXIUM_GEMINI) += hexium_gemini.o
+ obj-$(CONFIG_VIDEO_TIMBERDALE)	+= timblogiw.o
++obj-$(CONFIG_VIDEO_AT91SAM9X5) += at91sam9x5-video.o
+ 
+ obj-$(CONFIG_VIDEOBUF_GEN) += videobuf-core.o
+ obj-$(CONFIG_VIDEOBUF_DMA_SG) += videobuf-dma-sg.o
+diff --git a/drivers/media/video/at91sam9x5-video.c b/drivers/media/video/at91sam9x5-video.c
+new file mode 100644
+index 0000000..1e5154b
+--- /dev/null
++++ b/drivers/media/video/at91sam9x5-video.c
+@@ -0,0 +1,1440 @@
++/*
++ * Copyright (C) 2011 Pengutronix
++ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
++ *
++ * This program is free software; you can redistribute it and/or modify it under
++ * the terms of the GNU General Public License version 2 as published by the
++ * Free Software Foundation.
++ */
++
++/*
++ * XXX:
++ * - handle setting of global alpha
++ * - handle more formats
++ * - complete this list :-)
++ */
++
++#include <linux/err.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++
++#include <media/v4l2-common.h>
++#include <media/v4l2-dev.h>
++#include <media/v4l2-ioctl.h>
++#include <media/videobuf2-dma-contig.h>
++
++#define debug(fmt, ...)
++
++#define DRIVER_NAME "at91sam9x5-video"
++
++#define REG_HEOCHER		0x00
++#define REG_HEOCHER_CHEN		0x00000001
++#define REG_HEOCHER_UPDATEEN		0x00000002
++#define REG_HEOCHER_A2QEN		0x00000004
++
++#define REG_HEOCHDR		0x04
++#define REG_HEOCHDR_CHDIS		0x00000001
++#define REG_HEOCHDR_CHRST		0x00000100
++
++#define REG_HEOCHSR		0x08
++#define REG_HEOCHSR_CHSR		0x00000001
++#define REG_HEOCHSR_UPDATESR		0x00000002
++#define REG_HEOCHSR_A2QSR		0x00000004
++
++#define REG_HEOIER		0x0c
++#define REG_HEOIDR		0x10
++#define REG_HEOIMR		0x14
++#define REG_HEOISR		0x18
++#define REG_HEOIxR_DMA			0x00000004
++#define REG_HEOIxR_DSCR			0x00000008
++#define REG_HEOIxR_ADD			0x00000010
++#define REG_HEOIxR_DONE			0x00000020
++#define REG_HEOIxR_OVR			0x00000040
++#define REG_HEOIxR_UDMA			0x00000400
++#define REG_HEOIxR_UDSCR		0x00000800
++#define REG_HEOIxR_UADD			0x00001000
++#define REG_HEOIxR_UDONE		0x00002000
++#define REG_HEOIxR_UOVR			0x00004000
++#define REG_HEOIxR_VDMA			0x00040000
++#define REG_HEOIxR_VDSCR		0x00080000
++#define REG_HEOIxR_VADD			0x00100000
++#define REG_HEOIxR_VDONE		0x00200000
++#define REG_HEOIxR_VOVR			0x00400000
++
++#define REG_HEOHEAD		0x1c
++#define REG_HEOUHEAD		0x2c
++#define REG_HEOVHEAD		0x3c
++
++#define REG_HEOADDR		0x20
++#define REG_HEOUADDR		0x30
++#define REG_HEOVADDR		0x40
++
++#define REG_HEOCTRL		0x24
++#define REG_HEOUCTRL		0x34
++#define REG_HEOVCTRL		0x44
++#define REG_HEOxCTRL_DFETCH		0x00000001
++#define REG_HEOCTRL_LFETCH		0x00000002
++#define REG_HEOxCTRL_DMAIEN		0x00000004
++#define REG_HEOxCTRL_DSCRIEN		0x00000008
++#define REG_HEOxCTRL_ADDIEN		0x00000010
++#define REG_HEOxCTRL_DONEIEN		0x00000020
++
++#define REG_HEONEXT		0x28
++#define REG_HEOUNEXT		0x38
++#define REG_HEOVNEXT		0x48
++
++#define REG_HEOCFG0		0x4c
++#define REG_HEOCFG0_DLBO		0x00000100
++#define REG_HEOCFG0_BLEN		0x00000030
++#define REG_HEOCFG0_BLEN_INCR1			0x00000000
++#define REG_HEOCFG0_BLEN_INCR4			0x00000010
++#define REG_HEOCFG0_BLEN_INCR8			0x00000020
++#define REG_HEOCFG0_BLEN_INCR16			0x00000030
++#define REG_HEOCFG0_BLENUV		0x000000c0
++#define REG_HEOCFG0_BLENUV_INCR1		0x00000000
++#define REG_HEOCFG0_BLENUV_INCR4		0x00000040
++#define REG_HEOCFG0_BLENUV_INCR8		0x00000080
++#define REG_HEOCFG0_BLENUV_INCR16		0x000000c0
++
++#define REG_HEOCFG1		0x50
++#define REG_HEOCFG1_CLUTEN		0x00000001
++#define REG_HEOCFG1_YUVEN		0x00000002
++#define REG_HEOCFG1_YUVMODE_12YCBCRP	0x00008000
++
++#define REG_HEOCFG2		0x54
++#define REG_HEOCFG2_XPOS		0x000007ff
++#define REG_HEOCFG2_YPOS		0x07ff0000
++
++#define REG_HEOCFG3		0x58
++#define REG_HEOCFG3_XSIZE		0x000007ff
++#define REG_HEOCFG3_YSIZE		0x07ff0000
++
++#define REG_HEOCFG4		0x5c
++#define REG_HEOCFG4_XMEMSIZE		0x000007ff
++#define REG_HEOCFG4_YMEMSIZE		0x07ff0000
++
++#define REG_HEOCFG5		0x60
++#define REG_HEOCFG5_XSTRIDE		0xffffffff
++
++#define REG_HEOCFG6		0x64
++#define REG_HEOCFG6_PSTRIDE		0xffffffff
++
++#define REG_HEOCFG7		0x68
++#define REG_HEOCFG7_UVXSTRIDE		0xffffffff
++
++#define REG_HEOCFG8		0x6c
++#define REG_HEOCFG8_UVPSTRIDE		0xffffffff
++
++#define REG_HEOCFG9		0x70
++#define REG_HEOCFG10		0x74
++#define REG_HEOCFG11		0x78
++
++#define REG_HEOCFG12		0x7c
++#define REG_HEOCFG12_CRKEY		0x00000001
++#define REG_HEOCFG12_INV		0x00000002
++#define REG_HEOCFG12_ITER2BL		0x00000004
++#define REG_HEOCFG12_ITER		0x00000008
++#define REG_HEOCFG12_REVALPHA		0x00000010
++#define REG_HEOCFG12_GAEN		0x00000020
++#define REG_HEOCFG12_LAEN		0x00000040
++#define REG_HEOCFG12_OVR		0x00000080
++#define REG_HEOCFG12_DMA		0x00000100
++#define REG_HEOCFG12_REP		0x00000200
++#define REG_HEOCFG12_DSTKEY		0x00000400
++#define REG_HEOCFG12_VIDPRI		0x00001000
++#define REG_HEOCFG12_GA			0x00ff0000
++
++#define REG_HEOCFG13		0x80
++#define REG_HEOCFG13_XFACTOR		0x00001fff
++#define REG_HEOCFG13_YFACTOR		0x1fff0000
++#define REG_HEOCFG13_SCALEN		0x80000000
++
++#define REG_HEOCFG14		0x84
++#define REG_HEOCFG15		0x88
++#define REG_HEOCFG16		0x8c
++
++#define valtomask(val, mask)	(((val) << __ffs((mask))) & (mask))
++#define valfrommask(val, mask)	(((val) & (mask)) >> __ffs((mask)))
++
++struct at91sam9x5_video_pdata {
++	u16 base_width;
++	u16 base_height;
++};
++
++struct at91sam9x5_video_bufinfo {
++	struct vb2_buffer *vb;
++	unsigned u_planeno, v_planeno;
++	unsigned long plane_size[3];
++};
++
++struct at91sam9x5_video_priv {
++	struct platform_device *pdev;
++
++	/* framebuffer stuff */
++	struct notifier_block fb_notifier;
++	struct fb_info *fbinfo;
++
++	struct video_device *video_dev;
++
++	void __iomem *regbase;
++	unsigned int irq;
++
++	struct vb2_queue queue;
++	void *alloc_ctx;
++
++	struct at91sam9x5_video_bufinfo cur, next;
++
++	/* protects the members after lock and hardware access */
++	spinlock_t lock;
++
++	enum {
++		/* DMA not running */
++		at91sam9x5_video_HW_IDLE,
++		/* DMA running, unless cfgstate is BAD */
++		at91sam9x5_video_HW_RUNNING,
++	} hwstate;
++
++	enum {
++		at91sam9x5_video_CFG_GOOD,
++		/* the shadow registers need an update */
++		at91sam9x5_video_CFG_GOOD_LATCH,
++		at91sam9x5_video_CFG_BAD,
++	} cfgstate;
++
++	/* if true the vid_out config in hardware doesn't match sw config */
++	int cfgupdate;
++
++	int valid_config;
++
++	struct v4l2_pix_format fmt_vid_out_cur, fmt_vid_out_next;
++
++	int rotation;
++
++	struct v4l2_window fmt_vid_overlay;
++
++	/*
++	 * For YUV formats Y data is always in plane 0. U, V are either both in
++	 * 0, both in 1, or U in 1 or V in 2. -1 for formats that don't use U
++	 * and V.
++	 */
++	int u_planeno, v_planeno;
++
++	unsigned long plane_size[3];
++
++	/*
++	 * These are the offsets into the buffers to start the hardware for.
++	 * Depending on rotation and overlay position this is more or less ugly
++	 * to calculate. (y_offset is used for rgb data, too.)
++	 */
++	u32 y_offset, u_offset, v_offset;
++
++	u32 irqstat;
++};
++
++static u32 at91sam9x5_video_read32(struct at91sam9x5_video_priv *priv,
++		size_t offset)
++{
++	/* XXX: really use the __raw variants? */
++	return __raw_readl(priv->regbase + offset);
++}
++
++static void at91sam9x5_video_write32(struct at91sam9x5_video_priv *priv,
++		size_t offset, u32 val)
++{
++	debug("$%x := %08x, $08 == %08x\n", offset, val,
++			at91sam9x5_video_read32(priv, REG_HEOCHSR));
++	__raw_writel(val, priv->regbase + offset);
++	debug("$08 == %08x\n", at91sam9x5_video_read32(priv, REG_HEOCHSR));
++}
++
++static int __at91sam9x5_video_buf_in_use(struct at91sam9x5_video_priv *priv,
++		struct at91sam9x5_video_bufinfo *bi,
++		size_t heoaddr_offset, unsigned planeno)
++{
++	if (planeno >= 0) {
++		u32 heoaddr = at91sam9x5_video_read32(priv, heoaddr_offset);
++		dma_addr_t plane_paddr =
++			vb2_dma_contig_plane_paddr(bi->vb, planeno);
++
++		if (heoaddr - plane_paddr <= bi->plane_size[planeno])
++			return 1;
++	}
++
++	return 0;
++}
++
++
++static int at91sam9x5_video_buf_in_use(struct at91sam9x5_video_priv *priv,
++		struct at91sam9x5_video_bufinfo *bi)
++{
++	if (__at91sam9x5_video_buf_in_use(priv, bi, REG_HEOADDR, 0))
++		return 1;
++	if (__at91sam9x5_video_buf_in_use(priv, bi,
++				REG_HEOUADDR, bi->u_planeno))
++		return 1;
++	if (__at91sam9x5_video_buf_in_use(priv, bi,
++				REG_HEOVADDR, bi->v_planeno))
++		return 1;
++
++	return 0;
++}
++
++static u32 at91sam9x5_video_handle_irqstat(struct at91sam9x5_video_priv *priv)
++{
++	u32 heoisr = at91sam9x5_video_read32(priv, REG_HEOISR);
++
++	debug("cur=%p, next=%p, heoisr=%08x\n", priv->cur.vb,
++			priv->next.vb, heoisr);
++	debug("cfgupdate=%d hwstate=%d cfgstate=%d\n",
++			priv->cfgupdate, priv->hwstate, priv->cfgstate);
++
++	if (!priv->cur.vb) {
++		priv->cur = priv->next;
++		priv->next.vb = NULL;
++	}
++
++	if (priv->hwstate == at91sam9x5_video_HW_IDLE &&
++			!(at91sam9x5_video_read32(priv, REG_HEOCHSR) &
++				REG_HEOCHSR_CHSR)) {
++		if (priv->cur.vb) {
++			vb2_buffer_done(priv->cur.vb, VB2_BUF_STATE_DONE);
++			priv->cur.vb = NULL;
++		}
++
++		if (priv->next.vb) {
++			vb2_buffer_done(priv->next.vb, VB2_BUF_STATE_DONE);
++			priv->next.vb = NULL;
++		}
++
++		at91sam9x5_video_write32(priv, REG_HEOIDR,
++				REG_HEOIxR_ADD | REG_HEOIxR_DMA |
++				REG_HEOIxR_UADD | REG_HEOIxR_UDMA |
++				REG_HEOIxR_VADD | REG_HEOIxR_VDMA);
++
++	} else if (priv->cur.vb && priv->next.vb) {
++		int hwrunning = 1;
++		if (priv->cfgstate == at91sam9x5_video_CFG_BAD &&
++				!(at91sam9x5_video_read32(priv, REG_HEOCHSR) &
++					REG_HEOCHSR_CHSR))
++			hwrunning = 0;
++
++		if (!hwrunning || !at91sam9x5_video_buf_in_use(priv,
++					&priv->cur)) {
++			vb2_buffer_done(priv->cur.vb, VB2_BUF_STATE_DONE);
++			priv->cur = priv->next;
++			priv->next.vb = NULL;
++		}
++	} else if (priv->next.vb) {
++		priv->cur = priv->next;
++		priv->next.vb = NULL;
++	}
++
++	return heoisr;
++}
++
++static irqreturn_t at91sam9x5_video_irq(int irq, void *data)
++{
++	struct at91sam9x5_video_priv *priv = data;
++	unsigned long flags;
++	u32 handled, heoimr;
++
++	spin_lock_irqsave(&priv->lock, flags);
++
++	heoimr = at91sam9x5_video_read32(priv, REG_HEOIMR);
++	handled = at91sam9x5_video_handle_irqstat(priv);
++
++	debug("%x, HEOCHSR = %08x\n", handled,
++			at91sam9x5_video_read32(priv, REG_HEOCHSR));
++
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	if (handled & heoimr)
++		return IRQ_HANDLED;
++	else
++		return IRQ_NONE;
++}
++
++static inline int sign(int x)
++{
++	if (x > 0)
++		return 1;
++	else if (x < 0)
++		return -1;
++	else
++		return 0;
++}
++
++static void at91sam9x5_video_show_buf(struct at91sam9x5_video_priv *priv,
++		struct vb2_buffer *vb)
++{
++	dma_addr_t buffer = vb2_dma_contig_plane_paddr(vb, 0);
++	void *vaddr = vb2_plane_vaddr(vb, 0);
++	struct v4l2_pix_format *pix = &priv->fmt_vid_out_cur;
++	/* XXX: format dependant */
++	size_t offset_dmadesc = ALIGN(pix->width * pix->height +
++			ALIGN(pix->width, 2) * ALIGN(pix->height, 2) / 2, 32);
++	u32 *dmadesc = vaddr + offset_dmadesc;
++	u32 heocher;
++
++	if (priv->cfgstate == at91sam9x5_video_CFG_GOOD_LATCH) {
++		heocher = REG_HEOCHER_UPDATEEN;
++		priv->cfgstate = at91sam9x5_video_CFG_GOOD;
++	} else {
++		BUG_ON(priv->cfgstate != at91sam9x5_video_CFG_GOOD);
++		heocher = 0;
++	}
++
++	debug("vout=%ux%u, heocher=%08x\n", pix->width, pix->height, heocher);
++
++	dmadesc[0] = buffer + priv->y_offset;
++	dmadesc[1] = REG_HEOxCTRL_DFETCH;
++	dmadesc[2] = buffer + offset_dmadesc;
++
++	if (priv->u_planeno >= 0) {
++		dmadesc[3] = vb2_dma_contig_plane_paddr(vb, priv->u_planeno) +
++			priv->u_offset;
++		dmadesc[4] = REG_HEOxCTRL_DFETCH;
++		dmadesc[5] = buffer + offset_dmadesc + 3 * 4;
++	}
++
++	if (priv->v_planeno >= 0) {
++		dmadesc[6] = vb2_dma_contig_plane_paddr(vb, priv->v_planeno) +
++			priv->v_offset;
++		dmadesc[7] = REG_HEOxCTRL_DFETCH;
++		dmadesc[8] = buffer + offset_dmadesc + 6 * 4;
++	}
++
++
++	debug("HEOCHSR = %08x\n", at91sam9x5_video_read32(priv, REG_HEOCHSR));
++	if (likely(priv->hwstate == at91sam9x5_video_HW_RUNNING)) {
++
++		at91sam9x5_video_write32(priv, REG_HEOHEAD, dmadesc[2]);
++
++		if (priv->u_planeno >= 0)
++			at91sam9x5_video_write32(priv,
++					REG_HEOUHEAD, dmadesc[5]);
++
++		if (priv->v_planeno >= 0)
++			at91sam9x5_video_write32(priv,
++					REG_HEOVHEAD, dmadesc[8]);
++
++		at91sam9x5_video_write32(priv,
++				REG_HEOCHER, heocher | REG_HEOCHER_A2QEN);
++
++	} else {
++
++		at91sam9x5_video_write32(priv, REG_HEOADDR, dmadesc[0]);
++		at91sam9x5_video_write32(priv, REG_HEOCTRL, dmadesc[1]);
++		at91sam9x5_video_write32(priv, REG_HEONEXT, dmadesc[2]);
++
++		if (priv->u_planeno >= 0) {
++			at91sam9x5_video_write32(priv,
++					REG_HEOUADDR, dmadesc[3]);
++			at91sam9x5_video_write32(priv,
++					REG_HEOUCTRL, dmadesc[4]);
++			at91sam9x5_video_write32(priv,
++					REG_HEOUNEXT, dmadesc[5]);
++		}
++
++		if (priv->v_planeno >= 0) {
++			at91sam9x5_video_write32(priv,
++					REG_HEOVADDR, dmadesc[6]);
++			at91sam9x5_video_write32(priv,
++					REG_HEOVCTRL, dmadesc[7]);
++			at91sam9x5_video_write32(priv,
++					REG_HEOVNEXT, dmadesc[8]);
++		}
++
++		at91sam9x5_video_write32(priv, REG_HEOCHER,
++				heocher | REG_HEOCHER_CHEN);
++
++		priv->hwstate = at91sam9x5_video_HW_RUNNING;
++	}
++
++	if (priv->cur.vb && at91sam9x5_video_buf_in_use(priv, &priv->cur)) {
++		if (priv->next.vb) {
++			/* drop next; XXX: is this an error? */
++			debug("drop %p\n", priv->next.vb);
++			vb2_buffer_done(priv->next.vb, VB2_BUF_STATE_ERROR);
++		}
++	} else {
++		if (priv->cur.vb)
++			vb2_buffer_done(priv->cur.vb, VB2_BUF_STATE_DONE);
++
++		priv->cur = priv->next;
++	}
++	priv->next.vb = vb;
++	priv->next.u_planeno = priv->u_planeno;
++	priv->next.v_planeno = priv->v_planeno;
++	priv->next.plane_size[0] = priv->plane_size[0];
++	priv->next.plane_size[1] = priv->plane_size[1];
++	priv->next.plane_size[2] = priv->plane_size[2];
++}
++
++static int experimental;
++module_param(experimental, bool, 0644);
++MODULE_PARM_DESC(experimental, "enable experimental features");
++
++static void at91sam9x5_video_params(unsigned width, unsigned height,
++		int rotation, u32 *xstride, u32 *pstride, u32 *tloffset)
++{
++/* offset of pixel at (x, y) in the buffer */
++#define po(x, y) ((x) + width * (y))
++
++	/* offsets of the edges in counter-clockwise order */
++	const unsigned e[] = {
++		po(0, 0),
++		po(0, height - 1),
++		po(width - 1, height - 1),
++		po(width - 1, 0),
++	};
++
++	/*
++	 * offsets of the pixels next to the corresponding edges
++	 * If edge[i] goes to the top left corner, edge_neighbour[i] is
++	 * located just below of edge[i].
++	 */
++	const unsigned en[] = {
++		po(0, 1),
++		po(1, height - 1),
++		po(width - 1, height - 2),
++		po(width - 2, 0),
++	};
++
++#define ro(r) ((rotation + (r)) % 4)
++
++	*xstride = en[ro(0)] - e[ro(3)];
++	*pstride = e[ro(3)] - en[ro(3)];
++	*tloffset = e[ro(0)];
++}
++
++static void at91sam9x5_video_update_config_real(
++		struct at91sam9x5_video_priv *priv)
++{
++	struct v4l2_pix_format *pix = &priv->fmt_vid_out_cur;
++	struct v4l2_window *win = &priv->fmt_vid_overlay;
++	struct v4l2_rect *rect = &win->w;
++	/* XXX: check for overflow? */
++	s32 right = rect->left + rect->width, bottom = rect->top + rect->height;
++
++	unsigned hwxpos, hwypos, hwxsize, hwysize;
++	unsigned hwxmem_size, hwymem_size;
++	s32 hwxstride, hwpstride;
++	s32 hwuvxstride, hwuvpstride;
++	s32 rotated_pixwidth, rotated_pixheight;
++
++	debug("vout=%ux%u, ovl=(%d,%d)+(%d,%d)\n", pix->width, pix->height,
++			rect->left, rect->top, rect->width, rect->height);
++
++	if (!experimental && priv->rotation) {
++		dev_info(&priv->video_dev->dev, "disable rotation\n");
++		priv->rotation = 0;
++	}
++
++	if (rect->left < 0)
++		hwxpos = 0;
++	else
++		hwxpos = rect->left;
++
++	if (rect->top < 0)
++		hwypos = 0;
++	else
++		hwypos = rect->top;
++
++	if (right > priv->fbinfo->var.xres)
++		hwxsize = priv->fbinfo->var.xres - hwxpos;
++	else
++		hwxsize = right - hwxpos;
++
++	if (bottom > priv->fbinfo->var.yres)
++		hwysize = priv->fbinfo->var.yres - hwypos;
++	else
++		hwysize = bottom - hwypos;
++
++	at91sam9x5_video_write32(priv, REG_HEOCFG2,
++			valtomask(hwxpos, REG_HEOCFG2_XPOS) |
++			valtomask(hwypos, REG_HEOCFG2_YPOS));
++
++	at91sam9x5_video_write32(priv, REG_HEOCFG3,
++			valtomask(hwxsize - 1, REG_HEOCFG3_XSIZE) |
++			valtomask(hwysize - 1, REG_HEOCFG3_YSIZE));
++
++	/* XXX:
++	 *  - clipping
++	 */
++	at91sam9x5_video_write32(priv, REG_HEOCFG1,
++			REG_HEOCFG1_YUVMODE_12YCBCRP |
++			REG_HEOCFG1_YUVEN);
++	at91sam9x5_video_write32(priv, REG_HEOCFG12,
++			REG_HEOCFG12_GAEN |
++			REG_HEOCFG12_OVR |
++			REG_HEOCFG12_DMA |
++			REG_HEOCFG12_REP |
++			REG_HEOCFG12_GA);
++
++#define vx(pos) xedge[(priv->rotation + pos) % 4]
++#define vy(pos) yedge[(priv->rotation + pos) % 4]
++
++	if (priv->rotation & 1) {
++		rotated_pixwidth = pix->height;
++		rotated_pixheight = pix->width;
++	} else {
++		rotated_pixwidth = pix->width;
++		rotated_pixheight = pix->height;
++	}
++
++	hwxmem_size = rotated_pixwidth * hwxsize / rect->width;
++	hwymem_size = rotated_pixheight * hwysize / rect->height;
++
++	at91sam9x5_video_write32(priv, REG_HEOCFG4,
++			valtomask(hwxmem_size - 1, REG_HEOCFG4_XMEMSIZE) |
++			valtomask(hwymem_size - 1, REG_HEOCFG4_YMEMSIZE));
++
++	at91sam9x5_video_write32(priv, REG_HEOCFG13,
++			REG_HEOCFG13_SCALEN |
++			valtomask(1024 * hwxmem_size / hwxsize,
++				REG_HEOCFG13_XFACTOR) |
++			valtomask(1024 * hwymem_size / hwysize,
++				REG_HEOCFG13_YFACTOR));
++
++	at91sam9x5_video_params(pix->width, pix->height, priv->rotation,
++			&hwxstride, &hwpstride, &priv->y_offset);
++
++	/* XXX: format-dependant */
++	at91sam9x5_video_params(DIV_ROUND_UP(pix->width, 2),
++			DIV_ROUND_UP(pix->height, 2), priv->rotation,
++			&hwuvxstride, &hwuvpstride, &priv->u_offset);
++
++	at91sam9x5_video_write32(priv, REG_HEOCFG5,
++			valtomask(hwxstride - 1, REG_HEOCFG5_XSTRIDE));
++	at91sam9x5_video_write32(priv, REG_HEOCFG6,
++			valtomask(hwpstride - 1, REG_HEOCFG6_PSTRIDE));
++
++	at91sam9x5_video_write32(priv, REG_HEOCFG7,
++			valtomask(hwuvxstride - 1, REG_HEOCFG7_UVXSTRIDE));
++	at91sam9x5_video_write32(priv, REG_HEOCFG8,
++			valtomask(hwuvpstride - 1, REG_HEOCFG8_UVPSTRIDE));
++
++	/* XXX: format dependant */
++	priv->u_planeno = 0;
++	priv->v_planeno = 0;
++	priv->u_offset += pix->width * pix->height;
++	priv->v_offset = priv->u_offset +
++		DIV_ROUND_UP(pix->width, 2) * DIV_ROUND_UP(pix->height, 2);
++
++	/* XXX: evaluate pix->colorspace */
++	at91sam9x5_video_write32(priv, REG_HEOCFG14, 0x4c900091);
++	at91sam9x5_video_write32(priv, REG_HEOCFG15, 0x7a5f5090);
++	at91sam9x5_video_write32(priv, REG_HEOCFG16, 0x40040890);
++}
++
++static void at91sam9x5_video_update_config(struct at91sam9x5_video_priv *priv,
++		int overlay_only)
++{
++	debug("cfgupdate=%d overlay_only=%d\n", priv->cfgupdate, overlay_only);
++
++	at91sam9x5_video_handle_irqstat(priv);
++
++	if (priv->cfgupdate || overlay_only) {
++		struct v4l2_pix_format *pix = &priv->fmt_vid_out_cur;
++		struct v4l2_window *win = &priv->fmt_vid_overlay;
++		struct v4l2_rect *rect = &win->w;
++
++		if (!overlay_only) {
++			*pix = priv->fmt_vid_out_next;
++			priv->cfgupdate = 0;
++		}
++
++		/* XXX: handle clipping */
++		if (rect->width <= 0 || rect->height <= 0 ||
++				/* vid_out is set */
++				pix->width <= 0 ||
++				pix->height <= 0 ||
++				/* window is partly invisible or too small */
++				rect->left < 0 ||
++				rect->top < 0 ||
++				rect->left >= (int)priv->fbinfo->var.xres - 5 ||
++				rect->top >= (int)priv->fbinfo->var.yres - 5 ||
++				rect->left + rect->width >
++					(int)priv->fbinfo->var.xres ||
++				rect->top + rect->height >
++					(int)priv->fbinfo->var.yres) {
++
++			if (priv->cfgstate == at91sam9x5_video_CFG_GOOD ||
++					priv->cfgstate ==
++					at91sam9x5_video_CFG_GOOD_LATCH)
++				at91sam9x5_video_write32(priv,
++						REG_HEOCHDR, REG_HEOCHDR_CHDIS);
++
++			priv->cfgstate = at91sam9x5_video_CFG_BAD;
++		} else {
++			at91sam9x5_video_update_config_real(priv);
++
++			debug("hwstate=%d cfgstate=%d\n",
++					priv->hwstate, priv->cfgstate);
++			if (overlay_only && priv->hwstate ==
++					at91sam9x5_video_HW_RUNNING) {
++				if (priv->cfgstate ==
++						at91sam9x5_video_CFG_BAD) {
++					priv->cfgstate =
++						at91sam9x5_video_CFG_GOOD_LATCH;
++					priv->hwstate =
++						at91sam9x5_video_HW_IDLE;
++
++					at91sam9x5_video_show_buf(priv,
++							priv->cur.vb);
++				} else
++					at91sam9x5_video_write32(priv,
++							REG_HEOCHER,
++							REG_HEOCHER_UPDATEEN);
++			} else
++				priv->cfgstate =
++					at91sam9x5_video_CFG_GOOD_LATCH;
++		}
++
++	}
++}
++
++static int at91sam9x5_video_vb_queue_setup(struct vb2_queue *q,
++		unsigned int *num_buffers, unsigned int *num_planes,
++		unsigned long sizes[], void *alloc_ctxs[])
++{
++	struct at91sam9x5_video_priv *priv =
++		container_of(q, struct at91sam9x5_video_priv, queue);
++	struct v4l2_pix_format *pix = &priv->fmt_vid_out_next;
++
++	debug("vout=%ux%u\n", pix->width, pix->height);
++
++	/* XXX */
++	*num_planes = 1;
++
++	/*
++	 * The last 9 (aligned) words are used for the 3 dma descriptors (3
++	 * 32-bit words each). The additional 32 bits are for alignment.
++	 * XXX: is that allowed and done right?
++	 * XXX: format-dependant
++	 */
++	sizes[0] = pix->width * pix->height +
++		ALIGN(pix->width, 2) * ALIGN(pix->height, 2) / 2 +
++		10 * 32;
++	priv->plane_size[0] = sizes[0];
++
++	alloc_ctxs[0] = priv->alloc_ctx;
++
++	return 0;
++}
++
++static void at91sam9x5_video_vb_wait_prepare(struct vb2_queue *q)
++{
++	struct at91sam9x5_video_priv *priv =
++		container_of(q, struct at91sam9x5_video_priv, queue);
++	unsigned long flags;
++
++	debug("cfgupdate=%d hwstate=%d cfgstate=%d\n",
++			priv->cfgupdate, priv->hwstate, priv->cfgstate);
++	debug("bufs=%p,%p\n", priv->cur.vb, priv->next.vb);
++	spin_lock_irqsave(&priv->lock, flags);
++
++	at91sam9x5_video_handle_irqstat(priv);
++
++	at91sam9x5_video_write32(priv, REG_HEOIER,
++			REG_HEOIxR_ADD | REG_HEOIxR_DMA |
++			REG_HEOIxR_UADD | REG_HEOIxR_UDMA |
++			REG_HEOIxR_VADD | REG_HEOIxR_VDMA);
++
++	spin_unlock_irqrestore(&priv->lock, flags);
++}
++
++static void at91sam9x5_video_vb_wait_finish(struct vb2_queue *q)
++{
++	struct at91sam9x5_video_priv *priv =
++		container_of(q, struct at91sam9x5_video_priv, queue);
++	unsigned long flags;
++
++	debug("cfgupdate=%d hwstate=%d cfgstate=%d\n",
++			priv->cfgupdate, priv->hwstate, priv->cfgstate);
++	debug("bufs=%p,%p\n", priv->cur.vb, priv->next.vb);
++	spin_lock_irqsave(&priv->lock, flags);
++
++	at91sam9x5_video_write32(priv, REG_HEOIDR,
++			REG_HEOIxR_ADD | REG_HEOIxR_DMA |
++			REG_HEOIxR_UADD | REG_HEOIxR_UDMA |
++			REG_HEOIxR_VADD | REG_HEOIxR_VDMA);
++
++	spin_unlock_irqrestore(&priv->lock, flags);
++}
++
++static int at91sam9x5_video_vb_buf_prepare(struct vb2_buffer *vb)
++{
++	struct vb2_queue *q = vb->vb2_queue;
++	struct at91sam9x5_video_priv *priv =
++		container_of(q, struct at91sam9x5_video_priv, queue);
++	struct v4l2_pix_format *pix = &priv->fmt_vid_out_cur;
++	unsigned long flags;
++
++	spin_lock_irqsave(&priv->lock, flags);
++	if (priv->cfgupdate)
++		pix = &priv->fmt_vid_out_next;
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	debug("vout=%ux%u\n", pix->width, pix->height);
++	debug("buflen=%u\n", vb->v4l2_planes[0].length);
++
++	/* XXX: format-dependant */
++	if (vb->v4l2_planes[0].length < pix->width * pix->height +
++			ALIGN(pix->width, 2) * ALIGN(pix->height, 2) / 2 +
++			10 * 32)
++		return -EINVAL;
++
++	return 0;
++}
++
++static void at91sam9x5_video_vb_buf_queue(struct vb2_buffer *vb)
++{
++	struct vb2_queue *q = vb->vb2_queue;
++	struct at91sam9x5_video_priv *priv =
++		container_of(q, struct at91sam9x5_video_priv, queue);
++	unsigned long flags;
++
++	spin_lock_irqsave(&priv->lock, flags);
++
++	at91sam9x5_video_update_config(priv, 0);
++
++	switch (priv->cfgstate) {
++	case at91sam9x5_video_CFG_GOOD:
++	case at91sam9x5_video_CFG_GOOD_LATCH:
++		/* show_buf takes care of the eventual hwstate update */
++		at91sam9x5_video_show_buf(priv, vb);
++		break;
++
++	case at91sam9x5_video_CFG_BAD:
++		vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
++		priv->hwstate = at91sam9x5_video_HW_RUNNING;
++		break;
++	}
++
++	spin_unlock_irqrestore(&priv->lock, flags);
++}
++
++const struct vb2_ops at91sam9x5_video_vb_ops = {
++	.queue_setup = at91sam9x5_video_vb_queue_setup,
++
++	.wait_prepare = at91sam9x5_video_vb_wait_prepare,
++	.wait_finish = at91sam9x5_video_vb_wait_finish,
++
++	.buf_prepare = at91sam9x5_video_vb_buf_prepare,
++	.buf_queue = at91sam9x5_video_vb_buf_queue,
++};
++
++static int at91sam9x5_video_vidioc_querycap(struct file *filp,
++		void *fh, struct v4l2_capability *cap)
++{
++	strcpy(cap->driver, DRIVER_NAME);
++	cap->capabilities = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING |
++		V4L2_CAP_VIDEO_OVERLAY;
++
++	/* XXX */
++	cap->version = 0;
++	cap->card[0] = '\0';
++	cap->bus_info[0] = '\0';
++
++	return 0;
++}
++
++static int at91sam9x5_video_vidioc_g_fmt_vid_out(struct file *filp,
++		void *fh, struct v4l2_format *f)
++{
++	struct video_device *vdev = filp->private_data;
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++	unsigned long flags;
++
++	if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++		return -EINVAL;
++
++	spin_lock_irqsave(&priv->lock, flags);
++
++	f->fmt.pix = priv->fmt_vid_out_next;
++
++	spin_unlock_irqrestore(&priv->lock, flags);
++	return 0;
++}
++
++static int at91sam9x5_video_vidioc_s_fmt_vid_out(struct file *filp,
++		void *fh, struct v4l2_format *f)
++{
++	struct video_device *vdev = filp->private_data;
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++	struct v4l2_pix_format *pix = &f->fmt.pix;
++	unsigned long flags;
++
++	if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++		return -EINVAL;
++
++	if (pix->pixelformat != V4L2_PIX_FMT_YUV420)
++		return -EINVAL;
++
++	debug("vout=%ux%u\n", pix->width, pix->height);
++
++	spin_lock_irqsave(&priv->lock, flags);
++
++	priv->fmt_vid_out_next = *pix;
++
++	priv->cfgupdate = 1;
++
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	return 0;
++}
++
++static int at91sam9x5_video_vidioc_g_fmt_vid_overlay(struct file *filp,
++		void *fh, struct v4l2_format *f)
++{
++	struct video_device *vdev = filp->private_data;
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++	unsigned long flags;
++
++	if (f->type != V4L2_BUF_TYPE_VIDEO_OVERLAY)
++		return -EINVAL;
++
++	spin_lock_irqsave(&priv->lock, flags);
++
++	f->fmt.win = priv->fmt_vid_overlay;
++
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	return 0;
++}
++
++static int at91sam9x5_video_vidioc_s_fmt_vid_overlay(struct file *filp,
++		void *fh, struct v4l2_format *f)
++{
++	struct video_device *vdev = filp->private_data;
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++	struct v4l2_window *win = &f->fmt.win;
++	unsigned long flags;
++
++	if (f->type != V4L2_BUF_TYPE_VIDEO_OVERLAY)
++		return -EINVAL;
++
++	debug("rect=(%d,%d)+(%d,%d)\n",
++			win->w.left, win->w.top, win->w.width, win->w.height);
++
++	spin_lock_irqsave(&priv->lock, flags);
++
++	priv->fmt_vid_overlay = *win;
++
++	at91sam9x5_video_update_config(priv, 1);
++
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	return 0;
++}
++
++static int at91sam9x5_video_vidioc_enum_fmt_vid_out(struct file *filp,
++		void *fh, struct v4l2_fmtdesc *f)
++{
++	/* XXX: support more formats */
++	if (f->index > 0)
++		return -EINVAL;
++
++	f->pixelformat = V4L2_PIX_FMT_YUV420;
++	return 0;
++}
++
++static int at91sam9x5_video_vidioc_reqbufs(struct file *filp,
++		void *fh, struct v4l2_requestbuffers *b)
++{
++	struct video_device *vdev = filp->private_data;
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++	struct vb2_queue *q = &priv->queue;
++
++	if (b->type != q->type) {
++		dev_err(&priv->pdev->dev, "invalid buffer type (%d != %d)\n",
++				b->type, q->type);
++		return -EINVAL;
++	}
++
++	return vb2_reqbufs(q, b);
++}
++
++static int at91sam9x5_video_vidioc_querybuf(struct file *filp,
++		void *fh, struct v4l2_buffer *b)
++{
++	struct video_device *vdev = filp->private_data;
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++
++	return vb2_querybuf(&priv->queue, b);
++}
++
++static int at91sam9x5_video_vidioc_qbuf(struct file *filp,
++		void *fh, struct v4l2_buffer *b)
++{
++	struct video_device *vdev = filp->private_data;
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++
++	return vb2_qbuf(&priv->queue, b);
++}
++
++static int at91sam9x5_video_vidioc_dqbuf(struct file *filp,
++		void *fh, struct v4l2_buffer *b)
++{
++	struct video_device *vdev = filp->private_data;
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++
++	return vb2_dqbuf(&priv->queue, b, filp->f_flags & O_NONBLOCK);
++}
++
++static int at91sam9x5_video_vidioc_streamon(struct file *filp,
++		void *fh, enum v4l2_buf_type type)
++{
++	struct video_device *vdev = video_devdata(filp);
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++
++	return vb2_streamon(&priv->queue, type);
++}
++
++static int at91sam9x5_video_vidioc_streamoff(struct file *filp,
++		void *fh, enum v4l2_buf_type type)
++{
++	struct video_device *vdev = video_devdata(filp);
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++	unsigned long flags;
++
++	spin_lock_irqsave(&priv->lock, flags);
++
++	/* disable channel */
++	at91sam9x5_video_write32(priv, REG_HEOCHDR, REG_HEOCHDR_CHDIS);
++
++	at91sam9x5_video_handle_irqstat(priv);
++
++	if (priv->cur.vb)
++		at91sam9x5_video_write32(priv, REG_HEOIER,
++				REG_HEOIxR_ADD | REG_HEOIxR_DMA |
++				REG_HEOIxR_UADD | REG_HEOIxR_UDMA |
++				REG_HEOIxR_VADD | REG_HEOIxR_VDMA);
++
++	priv->hwstate = at91sam9x5_video_HW_IDLE;
++
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	return vb2_streamoff(&priv->queue, type);
++}
++
++static int at91sam9x5_video_vidioc_queryctrl(struct file *filp, void *fh,
++		struct v4l2_queryctrl *a)
++{
++	int ret;
++
++	switch (a->id) {
++	case V4L2_CID_ROTATE:
++		ret = v4l2_ctrl_query_fill(a, 0, 270, 90, 0);
++		break;
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	return ret;
++}
++
++static int at91sam9x5_video_vidioc_g_ctrl(struct file *filp, void *fh,
++		struct v4l2_control *a)
++{
++	struct video_device *vdev = video_devdata(filp);
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++	int ret = 0;
++
++	switch (a->id) {
++	case V4L2_CID_ROTATE:
++		a->value = 90 * priv->rotation;
++		break;
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	return ret;
++}
++
++static int at91sam9x5_video_vidioc_s_ctrl(struct file *filp, void *fh,
++		struct v4l2_control *a)
++{
++	struct video_device *vdev = video_devdata(filp);
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++	int ret;
++	unsigned long flags;
++
++	switch (a->id) {
++	case V4L2_CID_ROTATE:
++		if (a->value / 90 * 90 != a->value ||
++				(a->value / 90) % 4 != a->value / 90) {
++			ret = -EINVAL;
++		} else {
++			debug("rotation: %d\n", a->value);
++			spin_lock_irqsave(&priv->lock, flags);
++			priv->rotation = a->value / 90;
++			at91sam9x5_video_update_config(priv, 1);
++			spin_unlock_irqrestore(&priv->lock, flags);
++		}
++		break;
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	return ret;
++}
++
++static const struct v4l2_ioctl_ops at91sam9x5_video_ioctl_ops = {
++	.vidioc_querycap = at91sam9x5_video_vidioc_querycap,
++	.vidioc_g_fmt_vid_out = at91sam9x5_video_vidioc_g_fmt_vid_out,
++	.vidioc_s_fmt_vid_out = at91sam9x5_video_vidioc_s_fmt_vid_out,
++	.vidioc_g_fmt_vid_overlay = at91sam9x5_video_vidioc_g_fmt_vid_overlay,
++	.vidioc_s_fmt_vid_overlay = at91sam9x5_video_vidioc_s_fmt_vid_overlay,
++	.vidioc_enum_fmt_vid_out = at91sam9x5_video_vidioc_enum_fmt_vid_out,
++	.vidioc_reqbufs = at91sam9x5_video_vidioc_reqbufs,
++	.vidioc_querybuf = at91sam9x5_video_vidioc_querybuf,
++	.vidioc_qbuf = at91sam9x5_video_vidioc_qbuf,
++	.vidioc_dqbuf = at91sam9x5_video_vidioc_dqbuf,
++	.vidioc_streamon = at91sam9x5_video_vidioc_streamon,
++	.vidioc_streamoff = at91sam9x5_video_vidioc_streamoff,
++	.vidioc_queryctrl = at91sam9x5_video_vidioc_queryctrl,
++	.vidioc_g_ctrl = at91sam9x5_video_vidioc_g_ctrl,
++	.vidioc_s_ctrl = at91sam9x5_video_vidioc_s_ctrl,
++};
++
++static int at91sam9x5_video_open(struct file *filp)
++{
++	struct video_device *vdev = video_devdata(filp);
++
++	/*
++	 * XXX: allow only one open? Or is that already enforced by the
++	 * framework?
++	 */
++	filp->private_data = vdev;
++
++	return 0;
++}
++
++static int at91sam9x5_video_release(struct file *filp)
++{
++	struct video_device *vdev = video_devdata(filp);
++
++	dev_dbg(&vdev->dev, "%s\n", __func__);
++
++	return 0;
++}
++
++static int at91sam9x5_video_mmap(struct file *filp, struct vm_area_struct *vma)
++{
++	struct video_device *vdev = video_devdata(filp);
++	struct at91sam9x5_video_priv *priv = video_get_drvdata(vdev);
++
++	dev_dbg(&vdev->dev, "%s\n", __func__);
++
++	/* returning -EIO here makes gst-launch segfault */
++	return vb2_mmap(&priv->queue, vma);
++}
++
++static struct v4l2_file_operations at91sam9x5_video_fops = {
++	.owner = THIS_MODULE,
++	.open = at91sam9x5_video_open,
++	.release = at91sam9x5_video_release,
++	.ioctl = video_ioctl2,
++	.mmap = at91sam9x5_video_mmap,
++};
++
++static int at91sam9x5_video_register(struct at91sam9x5_video_priv *priv,
++		struct fb_info *fbinfo)
++{
++	int ret = -ENOMEM;
++	struct platform_device *pdev = priv->pdev;
++	struct resource *res;
++	const struct at91sam9x5_video_pdata *pdata =
++		dev_get_platdata(&pdev->dev);
++	struct vb2_queue *q = &priv->queue;
++	unsigned long flags;
++
++	spin_lock_irqsave(&priv->lock, flags);
++	if (priv->fbinfo) {
++		spin_unlock_irqrestore(&priv->lock, flags);
++		return -EBUSY;
++	}
++	priv->fbinfo = fbinfo;
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	/* XXX: this doesn't belong here, does it? */
++	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++
++	if (!pdata) {
++		dev_err(&pdev->dev, "failed to get platform data\n");
++		goto err_get_pdata;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(&pdev->dev, "failed to get register base\n");
++		goto err_get_regbase;
++	}
++
++	priv->regbase = ioremap(res->start, resource_size(res));
++	if (!priv->regbase) {
++		dev_err(&pdev->dev, "failed to remap register base\n");
++		goto err_ioremap;
++	}
++
++	/*
++	 * XXX: video_device_alloc is just a kzalloc, so embedding struct
++	 * video_device into struct at91sam9x5_video_priv would work, too.
++	 * Is that allowed?
++	 */
++	priv->video_dev = video_device_alloc();
++	if (!priv->video_dev) {
++		dev_err(&pdev->dev, "failed to alloc video device for %p\n",
++				fbinfo);
++		goto err_video_device_alloc;
++	}
++
++	priv->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
++	if (IS_ERR(priv->alloc_ctx)) {
++		ret = PTR_ERR(priv->alloc_ctx);
++		dev_err(&pdev->dev, "failed to init alloc_ctx (%d)\n", ret);
++		goto err_init_ctx;
++	}
++
++	q->ops = &at91sam9x5_video_vb_ops;
++	q->mem_ops = &vb2_dma_contig_memops;
++	q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
++	q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_WRITE;
++
++	ret = vb2_queue_init(q);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to init queue (%d)\n", ret);
++		goto err_queue_init;
++	}
++
++	priv->video_dev->fops = &at91sam9x5_video_fops;
++	priv->video_dev->ioctl_ops = &at91sam9x5_video_ioctl_ops;
++	priv->video_dev->release = video_device_release;
++
++	video_set_drvdata(priv->video_dev, priv);
++
++	/* reset channel and clear status */
++	at91sam9x5_video_write32(priv, REG_HEOCHDR, REG_HEOCHDR_CHRST);
++	(void)at91sam9x5_video_read32(priv, REG_HEOISR);
++
++	/* set maximal bursting */
++	at91sam9x5_video_write32(priv, REG_HEOCFG0,
++			REG_HEOCFG0_BLEN_INCR16 |
++			REG_HEOCFG0_BLENUV_INCR16);
++
++	ret = platform_get_irq(pdev, 0);
++	if (ret <= 0) {
++		dev_err(&pdev->dev, "failed to get irq from resources (%d)\n",
++				ret);
++		if (!ret)
++			ret = -ENXIO;
++		goto err_get_irq;
++	}
++	priv->irq = ret;
++
++	ret = request_irq(priv->irq, at91sam9x5_video_irq, IRQF_SHARED,
++			DRIVER_NAME, priv);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to request irq (%d)\n", ret);
++		goto err_request_irq;
++	}
++
++	ret = video_register_device(priv->video_dev,
++			/* XXX: really grabber? */ VFL_TYPE_GRABBER, -1);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to register video device (%d)\n",
++				ret);
++
++		free_irq(priv->irq, priv);
++ err_request_irq:
++ err_get_irq:
++
++		vb2_queue_release(q);
++err_queue_init:
++
++		vb2_dma_contig_cleanup_ctx(priv->alloc_ctx);
++ err_init_ctx:
++
++		video_device_release(priv->video_dev);
++ err_video_device_alloc:
++
++		iounmap(priv->regbase);
++
++		priv->fbinfo = NULL;
++	}
++ err_ioremap:
++ err_get_regbase:
++ err_get_pdata:
++
++	return ret;
++}
++
++static void at91sam9x5_video_unregister(struct at91sam9x5_video_priv *priv)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&priv->lock, flags);
++
++	if (!priv->fbinfo) {
++		spin_unlock_irqrestore(&priv->lock, flags);
++		return;
++	}
++	/* XXX: handle fbinfo being NULL in various callbacks */
++	priv->fbinfo = NULL;
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	/* silence DMA */
++	at91sam9x5_video_write32(priv, REG_HEOIDR,
++			REG_HEOIxR_ADD | REG_HEOIxR_DMA | REG_HEOIxR_UADD |
++			REG_HEOIxR_UDMA | REG_HEOIxR_VADD | REG_HEOIxR_VDMA);
++
++	video_unregister_device(priv->video_dev);
++	free_irq(priv->irq, priv);
++	vb2_queue_release(&priv->queue);
++	vb2_dma_contig_cleanup_ctx(priv->alloc_ctx);
++	video_device_release(priv->video_dev);
++	iounmap(priv->regbase);
++}
++
++static int at91sam9x5_video_fb_event_notify(struct notifier_block *self,
++		unsigned long action, void *data)
++{
++	struct at91sam9x5_video_priv *priv =
++		container_of(self, struct at91sam9x5_video_priv, fb_notifier);
++	struct fb_event *event = data;
++	struct fb_info *fbinfo = event->info;
++
++	/* XXX: only do this for atmel_lcdfb devices! */
++	switch (action) {
++	case FB_EVENT_FB_REGISTERED:
++		at91sam9x5_video_register(priv, fbinfo);
++		break;
++
++	case FB_EVENT_FB_UNREGISTERED:
++		at91sam9x5_video_unregister(priv);
++		break;
++	}
++	return 0;
++}
++
++static int __devinit at91sam9x5_video_probe(struct platform_device *pdev)
++{
++	int ret = -ENOMEM;
++	size_t i;
++	struct at91sam9x5_video_priv *priv = kzalloc(sizeof(*priv), GFP_KERNEL);
++
++	if (!priv) {
++		dev_err(&pdev->dev, "failed to allocate driver private data\n");
++		goto err_alloc_priv;
++	}
++
++	priv->pdev = pdev;
++	priv->fb_notifier.notifier_call = at91sam9x5_video_fb_event_notify;
++
++	platform_set_drvdata(pdev, priv);
++
++	spin_lock_init(&priv->lock);
++
++	ret = fb_register_client(&priv->fb_notifier);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to register fb client (%d)\n", ret);
++
++		kfree(priv);
++err_alloc_priv:
++
++		return ret;
++	}
++
++	/* XXX: This is racy. If a new fb is registered then
++	 * at91sam9x5_video_register is called twice. This should be solved
++	 * somewhere in drivers/fb. priv->fbinfo is used to prevent multiple
++	 * registration.
++	 */
++
++	for (i = 0; i < ARRAY_SIZE(registered_fb); ++i)
++		if (registered_fb[i])
++			at91sam9x5_video_register(priv, registered_fb[i]);
++
++	return 0;
++}
++
++int __devexit at91sam9x5_video_remove(struct platform_device *pdev)
++{
++	struct at91sam9x5_video_priv *priv = platform_get_drvdata(pdev);
++
++	fb_unregister_client(&priv->fb_notifier);
++	at91sam9x5_video_unregister(priv);
++	kfree(priv);
++
++	return 0;
++}
++
++static struct platform_driver at91sam9x5_video_driver = {
++	.driver = {
++		.name = DRIVER_NAME,
++		.owner = THIS_MODULE,
++	},
++	.probe = at91sam9x5_video_probe,
++	.remove = at91sam9x5_video_remove,
++};
++
++static struct platform_device *at91sam9x5_video_device;
++static int __init at91sam9x5_video_init(void)
++{
++	/* XXX: register the device in arch/arm/mach-at91 */
++	int ret;
++	const struct resource res[] = {
++		{
++			.start = 0xf8038280,
++			.end = 0xf803833f,
++			.flags = IORESOURCE_MEM,
++		}, {
++			.start = 25,
++			.end = 25,
++			.flags = IORESOURCE_IRQ,
++		},
++	};
++	const struct at91sam9x5_video_pdata pdata = {
++		.base_width = 800,
++		.base_height = 480,
++	};
++
++	ret = platform_driver_register(&at91sam9x5_video_driver);
++	if (ret) {
++		pr_err("failed to register driver (%d)", ret);
++		goto err_driver_register;
++	}
++
++	at91sam9x5_video_device = platform_device_register_resndata(NULL,
++			DRIVER_NAME, -1,
++			res, ARRAY_SIZE(res), &pdata, sizeof(pdata));
++	if (IS_ERR(at91sam9x5_video_device)) {
++		ret = PTR_ERR(at91sam9x5_video_device);
++		pr_err("failed to register device (%d)", ret);
++		platform_driver_unregister(&at91sam9x5_video_driver);
++	}
++
++ err_driver_register:
++	return ret;
++}
++module_init(at91sam9x5_video_init);
++
++static void __exit at91sam9x5_video_exit(void)
++{
++	platform_device_unregister(at91sam9x5_video_device);
++	platform_driver_unregister(&at91sam9x5_video_driver);
++}
++module_exit(at91sam9x5_video_exit);
++
++MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index 7ba17cb..2a943ae 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -734,7 +734,7 @@ static int atmel_lcdfb_setup_9x5_core(struct fb_info *info)
+ 	lcdc_writel(sinfo, ATMEL_LCDC_BASEIDR, ~0UL);
+ 	/* Enable BASE LAYER overflow interrupts, if want to enable DMA interrupt, also need set it at LCDC_BASECTRL reg */
+ 	lcdc_writel(sinfo, ATMEL_LCDC_BASEIER, LCDC_BASEIER_OVR);
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDIER, LCDC_LCDIER_FIFOERRIE | LCDC_LCDIER_BASEIE);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDIER, LCDC_LCDIER_FIFOERRIE | LCDC_LCDIER_BASEIE | LCDC_LCDIER_HEOIE);
+ 
+ 	return 0;
+ }
+@@ -1066,7 +1066,8 @@ static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
+ 				dev_warn(info->device, "base layer overflow %#x\n",
+ 							baselayer_status);
+ 
+-		}
++		} else
++			return IRQ_NONE;
+ 	} else {
+ 		status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
+ 		if (status & ATMEL_LCDC_UFLWI) {
+@@ -1266,7 +1267,7 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
+ 	init_contrast(sinfo);
+ 
+ 	/* interrupt */
+-	ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
++	ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, IRQF_SHARED, pdev->name, info);
+ 	if (ret) {
+ 		dev_err(dev, "request_irq failed: %d\n", ret);
+ 		goto unmap_mmio;
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0062-can-at91_can-don-t-align-struct-definitions.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0062-can-at91_can-don-t-align-struct-definitions.patch
new file mode 100644
index 0000000..d958172
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0062-can-at91_can-don-t-align-struct-definitions.patch
@@ -0,0 +1,81 @@
+From 05f0ec4badc2fa76dae2785cba53df2ed500895c Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Sun, 30 Jan 2011 22:14:49 +0100
+Subject: [PATCH 062/107] can: at91_can: don't align struct definitions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Applied-Upstream: v3.1, commit:44d8566
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/net/can/at91_can.c |   34 +++++++++++++++++-----------------
+ 1 files changed, 17 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
+index 74efb5a..8f15ae4 100644
+--- a/drivers/net/can/at91_can.c
++++ b/drivers/net/can/at91_can.c
+@@ -157,21 +157,21 @@ enum at91_mb_mode {
+ #define AT91_IRQ_ALL		(0x1fffffff)
+ 
+ struct at91_priv {
+-	struct can_priv		can;	   /* must be the first member! */
+-	struct net_device	*dev;
+-	struct napi_struct	napi;
++	struct can_priv can;		/* must be the first member! */
++	struct net_device *dev;
++	struct napi_struct napi;
+ 
+-	void __iomem		*reg_base;
++	void __iomem *reg_base;
+ 
+-	u32			reg_sr;
+-	unsigned int		tx_next;
+-	unsigned int		tx_echo;
+-	unsigned int		rx_next;
++	u32 reg_sr;
++	unsigned int tx_next;
++	unsigned int tx_echo;
++	unsigned int rx_next;
+ 
+-	struct clk		*clk;
+-	struct at91_can_data	*pdata;
++	struct clk *clk;
++	struct at91_can_data *pdata;
+ 
+-	canid_t			mb0_id;
++	canid_t mb0_id;
+ };
+ 
+ static struct can_bittiming_const at91_bittiming_const = {
+@@ -271,7 +271,7 @@ static void at91_setup_mailboxes(struct net_device *dev)
+ 
+ 	/* reset acceptance mask and id register */
+ 	for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) {
+-		at91_write(priv, AT91_MAM(i), 0x0 );
++		at91_write(priv, AT91_MAM(i), 0x0);
+ 		at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
+ 	}
+ 
+@@ -1231,11 +1231,11 @@ static int __devexit at91_can_remove(struct platform_device *pdev)
+ }
+ 
+ static struct platform_driver at91_can_driver = {
+-	.probe		= at91_can_probe,
+-	.remove		= __devexit_p(at91_can_remove),
+-	.driver		= {
+-		.name	= KBUILD_MODNAME,
+-		.owner	= THIS_MODULE,
++	.probe = at91_can_probe,
++	.remove = __devexit_p(at91_can_remove),
++	.driver = {
++		.name = KBUILD_MODNAME,
++		.owner = THIS_MODULE,
+ 	},
+ };
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0063-can-at91_can-fix-comment-about-priv-tx_next.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0063-can-at91_can-fix-comment-about-priv-tx_next.patch
new file mode 100644
index 0000000..a7a99f7
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0063-can-at91_can-fix-comment-about-priv-tx_next.patch
@@ -0,0 +1,31 @@
+From bfb1a854ef000d59a9af5957540dde72c75d875b Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Sat, 16 Apr 2011 13:25:15 +0200
+Subject: [PATCH 063/107] can: at91_can: fix comment about priv->tx_next
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Applied-Upstream: v3.1, commit:5613fff
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/net/can/at91_can.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
+index 8f15ae4..afd0f5d 100644
+--- a/drivers/net/can/at91_can.c
++++ b/drivers/net/can/at91_can.c
+@@ -375,7 +375,7 @@ static void at91_chip_stop(struct net_device *dev, enum can_state state)
+  * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
+  * encode the mailbox number, the upper 4 bits the mailbox priority:
+  *
+- * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) ||
++ * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) |
+  *                 (mb - AT91_MB_TX_FIRST);
+  *
+  */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0064-can-at91_can-don-t-copy-data-to-rx-ed-RTR-frames.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0064-can-at91_can-don-t-copy-data-to-rx-ed-RTR-frames.patch
new file mode 100644
index 0000000..cb7287c
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0064-can-at91_can-don-t-copy-data-to-rx-ed-RTR-frames.patch
@@ -0,0 +1,42 @@
+From e98b3a1a9cf098bd77e0a75d223c0ec466a6f8f2 Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Thu, 21 Oct 2010 18:39:26 +0200
+Subject: [PATCH 064/107] can: at91_can: don't copy data to rx'ed RTR frames
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Acked-by: Wolfgang Grandegger <wg@grandegger.com>
+Applied-Upstream: v3.1, commit:e14ee40
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/net/can/at91_can.c |   10 ++++++----
+ 1 files changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
+index afd0f5d..5358d70 100644
+--- a/drivers/net/can/at91_can.c
++++ b/drivers/net/can/at91_can.c
+@@ -513,12 +513,14 @@ static void at91_read_mb(struct net_device *dev, unsigned int mb,
+ 		cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
+ 
+ 	reg_msr = at91_read(priv, AT91_MSR(mb));
+-	if (reg_msr & AT91_MSR_MRTR)
+-		cf->can_id |= CAN_RTR_FLAG;
+ 	cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
+ 
+-	*(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
+-	*(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
++	if (reg_msr & AT91_MSR_MRTR)
++		cf->can_id |= CAN_RTR_FLAG;
++	else {
++		*(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
++		*(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
++	}
+ 
+ 	/* allow RX of extended frames */
+ 	at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0065-can-at91_can-let-get_tx_-functions-return-unsigned-i.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0065-can-at91_can-let-get_tx_-functions-return-unsigned-i.patch
new file mode 100644
index 0000000..0709071
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0065-can-at91_can-let-get_tx_-functions-return-unsigned-i.patch
@@ -0,0 +1,44 @@
+From faca8b47ba90bf3ab89a467afdac0ce2659ee3d5 Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Tue, 3 May 2011 17:47:55 +0200
+Subject: [PATCH 065/107] can: at91_can: let get_tx_* functions return
+ unsigned int
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Applied-Upstream: v3.1, commit:9c2e0a6
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/net/can/at91_can.c |    6 +++---
+ 1 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
+index 5358d70..716f22b 100644
+--- a/drivers/net/can/at91_can.c
++++ b/drivers/net/can/at91_can.c
+@@ -186,17 +186,17 @@ static struct can_bittiming_const at91_bittiming_const = {
+ 	.brp_inc	= 1,
+ };
+ 
+-static inline int get_tx_next_mb(const struct at91_priv *priv)
++static inline unsigned int get_tx_next_mb(const struct at91_priv *priv)
+ {
+ 	return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
+ }
+ 
+-static inline int get_tx_next_prio(const struct at91_priv *priv)
++static inline unsigned int get_tx_next_prio(const struct at91_priv *priv)
+ {
+ 	return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf;
+ }
+ 
+-static inline int get_tx_echo_mb(const struct at91_priv *priv)
++static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
+ {
+ 	return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
+ }
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0066-can-at91_can-directly-define-AT91_MB_RX_LAST.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0066-can-at91_can-directly-define-AT91_MB_RX_LAST.patch
new file mode 100644
index 0000000..5acfa3d
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0066-can-at91_can-directly-define-AT91_MB_RX_LAST.patch
@@ -0,0 +1,39 @@
+From 83f3681bb95d906f176355187b5bada0229999d1 Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Sat, 30 Apr 2011 20:46:12 +0200
+Subject: [PATCH 066/107] can: at91_can: directly define AT91_MB_RX_LAST
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+...instead of deriving it from AT91_MB_RX_FIRST and AT91_MB_RX_NUM.
+This removes a level of computation, when switching the driver from
+compile time constants to runtime values.
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Applied-Upstream: v3.1, commit:267cbe04
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/net/can/at91_can.c |    3 +--
+ 1 files changed, 1 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
+index 716f22b..9ce00fa 100644
+--- a/drivers/net/can/at91_can.c
++++ b/drivers/net/can/at91_can.c
+@@ -47,11 +47,10 @@
+  * RX/TX Mailbox split
+  * don't dare to touch
+  */
+-#define AT91_MB_RX_NUM		11
+ #define AT91_MB_TX_SHIFT	2
+ 
+ #define AT91_MB_RX_FIRST	1
+-#define AT91_MB_RX_LAST		(AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
++#define AT91_MB_RX_LAST		11
+ 
+ #define AT91_MB_RX_MASK(i)	((1 << (i)) - 1)
+ #define AT91_MB_RX_SPLIT	8
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0067-can-at91_can-rename-AT91_MB_RX_MASK-to-AT91_IRQ_MB_R.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0067-can-at91_can-rename-AT91_MB_RX_MASK-to-AT91_IRQ_MB_R.patch
new file mode 100644
index 0000000..47af3eb
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0067-can-at91_can-rename-AT91_MB_RX_MASK-to-AT91_IRQ_MB_R.patch
@@ -0,0 +1,74 @@
+From 4467291b29f43ba2db20412149f68b33e32ac5a2 Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Tue, 3 May 2011 16:37:16 +0200
+Subject: [PATCH 067/107] can: at91_can: rename AT91_MB_RX_MASK to
+ AT91_IRQ_MB_RX
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+... and use it for AT91_NEXT_MB_MASK,
+AT91_IRQ_MB_RX and AT91_IRQ_MB_RX, too.
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Applied-Upstream: v3.1, commit:b049994
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/net/can/at91_can.c |   18 +++++++++---------
+ 1 files changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
+index 9ce00fa..8699484 100644
+--- a/drivers/net/can/at91_can.c
++++ b/drivers/net/can/at91_can.c
+@@ -52,11 +52,11 @@
+ #define AT91_MB_RX_FIRST	1
+ #define AT91_MB_RX_LAST		11
+ 
+-#define AT91_MB_RX_MASK(i)	((1 << (i)) - 1)
++#define AT91_MB_MASK(i)		((1 << (i)) - 1)
+ #define AT91_MB_RX_SPLIT	8
+ #define AT91_MB_RX_LOW_LAST	(AT91_MB_RX_SPLIT - 1)
+-#define AT91_MB_RX_LOW_MASK	(AT91_MB_RX_MASK(AT91_MB_RX_SPLIT) & \
+-				 ~AT91_MB_RX_MASK(AT91_MB_RX_FIRST))
++#define AT91_MB_RX_LOW_MASK	(AT91_MB_MASK(AT91_MB_RX_SPLIT) & \
++				 ~AT91_MB_MASK(AT91_MB_RX_FIRST))
+ 
+ #define AT91_MB_TX_NUM		(1 << AT91_MB_TX_SHIFT)
+ #define AT91_MB_TX_FIRST	(AT91_MB_RX_LAST + 1)
+@@ -64,7 +64,7 @@
+ 
+ #define AT91_NEXT_PRIO_SHIFT	(AT91_MB_TX_SHIFT)
+ #define AT91_NEXT_PRIO_MASK	(0xf << AT91_MB_TX_SHIFT)
+-#define AT91_NEXT_MB_MASK	(AT91_MB_TX_NUM - 1)
++#define AT91_NEXT_MB_MASK	(AT91_MB_MASK(AT91_MB_TX_SHIFT))
+ #define AT91_NEXT_MASK		((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
+ 
+ /* Common registers */
+@@ -127,10 +127,10 @@ enum at91_mb_mode {
+ };
+ 
+ /* Interrupt mask bits */
+-#define AT91_IRQ_MB_RX		((1 << (AT91_MB_RX_LAST + 1)) \
+-				 - (1 << AT91_MB_RX_FIRST))
+-#define AT91_IRQ_MB_TX		((1 << (AT91_MB_TX_LAST + 1)) \
+-				 - (1 << AT91_MB_TX_FIRST))
++#define AT91_IRQ_MB_RX		(AT91_MB_MASK(AT91_MB_RX_LAST + 1) & \
++				 ~AT91_MB_MASK(AT91_MB_RX_FIRST))
++#define AT91_IRQ_MB_TX		(AT91_MB_MASK(AT91_MB_TX_LAST + 1) & \
++				 ~AT91_MB_MASK(AT91_MB_TX_FIRST))
+ #define AT91_IRQ_MB_ALL		(AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
+ 
+ #define AT91_IRQ_ERRA		(1 << 16)
+@@ -735,7 +735,7 @@ static int at91_poll(struct napi_struct *napi, int quota)
+ 	if (work_done < quota) {
+ 		/* enable IRQs for frame errors and all mailboxes >= rx_next */
+ 		u32 reg_ier = AT91_IRQ_ERR_FRAME;
+-		reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next);
++		reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_MASK(priv->rx_next);
+ 
+ 		napi_complete(napi);
+ 		at91_write(priv, AT91_IER, reg_ier);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0068-can-at91_can-convert-derived-mailbox-constants-into-.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0068-can-at91_can-convert-derived-mailbox-constants-into-.patch
new file mode 100644
index 0000000..e757c8b
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0068-can-at91_can-convert-derived-mailbox-constants-into-.patch
@@ -0,0 +1,296 @@
+From 7ed5674423392303ccc14045b0595a72e5d25aed Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Tue, 3 May 2011 17:31:40 +0200
+Subject: [PATCH 068/107] can: at91_can: convert derived mailbox constants
+ into functions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is the first of two patches converting the at91_can driver from a
+compile time mailbox setup to a dynamic one.
+
+This patch converts all derived mailbox constants to functions.
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Applied-Upstream: v3.1, commit:7900899
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/net/can/at91_can.c |  125 +++++++++++++++++++++++++++++---------------
+ 1 files changed, 83 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
+index 8699484..900ff67 100644
+--- a/drivers/net/can/at91_can.c
++++ b/drivers/net/can/at91_can.c
+@@ -54,18 +54,7 @@
+ 
+ #define AT91_MB_MASK(i)		((1 << (i)) - 1)
+ #define AT91_MB_RX_SPLIT	8
+-#define AT91_MB_RX_LOW_LAST	(AT91_MB_RX_SPLIT - 1)
+-#define AT91_MB_RX_LOW_MASK	(AT91_MB_MASK(AT91_MB_RX_SPLIT) & \
+-				 ~AT91_MB_MASK(AT91_MB_RX_FIRST))
+ 
+-#define AT91_MB_TX_NUM		(1 << AT91_MB_TX_SHIFT)
+-#define AT91_MB_TX_FIRST	(AT91_MB_RX_LAST + 1)
+-#define AT91_MB_TX_LAST		(AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1)
+-
+-#define AT91_NEXT_PRIO_SHIFT	(AT91_MB_TX_SHIFT)
+-#define AT91_NEXT_PRIO_MASK	(0xf << AT91_MB_TX_SHIFT)
+-#define AT91_NEXT_MB_MASK	(AT91_MB_MASK(AT91_MB_TX_SHIFT))
+-#define AT91_NEXT_MASK		((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
+ 
+ /* Common registers */
+ enum at91_reg {
+@@ -127,12 +116,6 @@ enum at91_mb_mode {
+ };
+ 
+ /* Interrupt mask bits */
+-#define AT91_IRQ_MB_RX		(AT91_MB_MASK(AT91_MB_RX_LAST + 1) & \
+-				 ~AT91_MB_MASK(AT91_MB_RX_FIRST))
+-#define AT91_IRQ_MB_TX		(AT91_MB_MASK(AT91_MB_TX_LAST + 1) & \
+-				 ~AT91_MB_MASK(AT91_MB_TX_FIRST))
+-#define AT91_IRQ_MB_ALL		(AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
+-
+ #define AT91_IRQ_ERRA		(1 << 16)
+ #define AT91_IRQ_WARN		(1 << 17)
+ #define AT91_IRQ_ERRP		(1 << 18)
+@@ -185,19 +168,77 @@ static struct can_bittiming_const at91_bittiming_const = {
+ 	.brp_inc	= 1,
+ };
+ 
++static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv)
++{
++	return AT91_MB_RX_SPLIT - 1;
++}
++
++static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv)
++{
++	return AT91_MB_MASK(AT91_MB_RX_SPLIT) &
++		~AT91_MB_MASK(AT91_MB_RX_FIRST);
++}
++
++static inline unsigned int get_mb_tx_num(const struct at91_priv *priv)
++{
++	return 1 << AT91_MB_TX_SHIFT;
++}
++
++static inline unsigned int get_mb_tx_first(const struct at91_priv *priv)
++{
++	return AT91_MB_RX_LAST + 1;
++}
++
++static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)
++{
++	return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1;
++}
++
++static inline unsigned int get_next_prio_shift(const struct at91_priv *priv)
++{
++	return AT91_MB_TX_SHIFT;
++}
++
++static inline unsigned int get_next_prio_mask(const struct at91_priv *priv)
++{
++	return 0xf << AT91_MB_TX_SHIFT;
++}
++
++static inline unsigned int get_next_mb_mask(const struct at91_priv *priv)
++{
++	return AT91_MB_MASK(AT91_MB_TX_SHIFT);
++}
++
++static inline unsigned int get_next_mask(const struct at91_priv *priv)
++{
++	return get_next_mb_mask(priv) | get_next_prio_mask(priv);
++}
++
++static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv)
++{
++	return AT91_MB_MASK(AT91_MB_RX_LAST + 1) &
++		~AT91_MB_MASK(AT91_MB_RX_FIRST);
++}
++
++static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv)
++{
++	return AT91_MB_MASK(get_mb_tx_last(priv) + 1) &
++		~AT91_MB_MASK(get_mb_tx_first(priv));
++}
++
+ static inline unsigned int get_tx_next_mb(const struct at91_priv *priv)
+ {
+-	return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
++	return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
+ }
+ 
+ static inline unsigned int get_tx_next_prio(const struct at91_priv *priv)
+ {
+-	return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf;
++	return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf;
+ }
+ 
+ static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
+ {
+-	return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
++	return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
+ }
+ 
+ static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
+@@ -275,7 +316,7 @@ static void at91_setup_mailboxes(struct net_device *dev)
+ 	}
+ 
+ 	/* The last 4 mailboxes are used for transmitting. */
+-	for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++)
++	for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++)
+ 		set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
+ 
+ 	/* Reset tx and rx helper pointers */
+@@ -335,7 +376,7 @@ static void at91_chip_start(struct net_device *dev)
+ 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
+ 
+ 	/* Enable interrupts */
+-	reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
++	reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
+ 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
+ 	at91_write(priv, AT91_IER, reg_ier);
+ }
+@@ -416,7 +457,7 @@ static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
+ 	stats->tx_bytes += cf->can_dlc;
+ 
+ 	/* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
+-	can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST);
++	can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv));
+ 
+ 	/*
+ 	 * we have to stop the queue and deliver all messages in case
+@@ -429,7 +470,7 @@ static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
+ 	priv->tx_next++;
+ 	if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
+ 	      AT91_MSR_MRDY) ||
+-	    (priv->tx_next & AT91_NEXT_MASK) == 0)
++	    (priv->tx_next & get_next_mask(priv)) == 0)
+ 		netif_stop_queue(dev);
+ 
+ 	/* Enable interrupt for this mailbox */
+@@ -446,7 +487,7 @@ static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
+  */
+ static inline void at91_activate_rx_low(const struct at91_priv *priv)
+ {
+-	u32 mask = AT91_MB_RX_LOW_MASK;
++	u32 mask = get_mb_rx_low_mask(priv);
+ 	at91_write(priv, AT91_TCR, mask);
+ }
+ 
+@@ -611,23 +652,23 @@ static int at91_poll_rx(struct net_device *dev, int quota)
+ 	unsigned int mb;
+ 	int received = 0;
+ 
+-	if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
+-	    reg_sr & AT91_MB_RX_LOW_MASK)
++	if (priv->rx_next > get_mb_rx_low_last(priv) &&
++	    reg_sr & get_mb_rx_low_mask(priv))
+ 		netdev_info(dev,
+ 			"order of incoming frames cannot be guaranteed\n");
+ 
+  again:
+-	for (mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, priv->rx_next);
+-	     mb < AT91_MB_RX_LAST + 1 && quota > 0;
++	for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next);
++	     mb < get_mb_tx_first(priv) && quota > 0;
+ 	     reg_sr = at91_read(priv, AT91_SR),
+-	     mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, ++priv->rx_next)) {
++	     mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) {
+ 		at91_read_msg(dev, mb);
+ 
+ 		/* reactivate mailboxes */
+-		if (mb == AT91_MB_RX_LOW_LAST)
++		if (mb == get_mb_rx_low_last(priv))
+ 			/* all lower mailboxed, if just finished it */
+ 			at91_activate_rx_low(priv);
+-		else if (mb > AT91_MB_RX_LOW_LAST)
++		else if (mb > get_mb_rx_low_last(priv))
+ 			/* only the mailbox we read */
+ 			at91_activate_rx_mb(priv, mb);
+ 
+@@ -636,7 +677,7 @@ static int at91_poll_rx(struct net_device *dev, int quota)
+ 	}
+ 
+ 	/* upper group completed, look again in lower */
+-	if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
++	if (priv->rx_next > get_mb_rx_low_last(priv) &&
+ 	    quota > 0 && mb > AT91_MB_RX_LAST) {
+ 		priv->rx_next = AT91_MB_RX_FIRST;
+ 		goto again;
+@@ -721,7 +762,7 @@ static int at91_poll(struct napi_struct *napi, int quota)
+ 	u32 reg_sr = at91_read(priv, AT91_SR);
+ 	int work_done = 0;
+ 
+-	if (reg_sr & AT91_IRQ_MB_RX)
++	if (reg_sr & get_irq_mb_rx(priv))
+ 		work_done += at91_poll_rx(dev, quota - work_done);
+ 
+ 	/*
+@@ -735,7 +776,7 @@ static int at91_poll(struct napi_struct *napi, int quota)
+ 	if (work_done < quota) {
+ 		/* enable IRQs for frame errors and all mailboxes >= rx_next */
+ 		u32 reg_ier = AT91_IRQ_ERR_FRAME;
+-		reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_MASK(priv->rx_next);
++		reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next);
+ 
+ 		napi_complete(napi);
+ 		at91_write(priv, AT91_IER, reg_ier);
+@@ -784,7 +825,7 @@ static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
+ 		if (likely(reg_msr & AT91_MSR_MRDY &&
+ 			   ~reg_msr & AT91_MSR_MABT)) {
+ 			/* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
+-			can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST);
++			can_get_echo_skb(dev, mb - get_mb_tx_first(priv));
+ 			dev->stats.tx_packets++;
+ 		}
+ 	}
+@@ -794,8 +835,8 @@ static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
+ 	 * we get a TX int for the last can frame directly before a
+ 	 * wrap around.
+ 	 */
+-	if ((priv->tx_next & AT91_NEXT_MASK) != 0 ||
+-	    (priv->tx_echo & AT91_NEXT_MASK) == 0)
++	if ((priv->tx_next & get_next_mask(priv)) != 0 ||
++	    (priv->tx_echo & get_next_mask(priv)) == 0)
+ 		netif_wake_queue(dev);
+ }
+ 
+@@ -969,19 +1010,19 @@ static irqreturn_t at91_irq(int irq, void *dev_id)
+ 	handled = IRQ_HANDLED;
+ 
+ 	/* Receive or error interrupt? -> napi */
+-	if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) {
++	if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) {
+ 		/*
+ 		 * The error bits are clear on read,
+ 		 * save for later use.
+ 		 */
+ 		priv->reg_sr = reg_sr;
+ 		at91_write(priv, AT91_IDR,
+-			   AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME);
++			   get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME);
+ 		napi_schedule(&priv->napi);
+ 	}
+ 
+ 	/* Transmission complete interrupt */
+-	if (reg_sr & AT91_IRQ_MB_TX)
++	if (reg_sr & get_irq_mb_tx(priv))
+ 		at91_irq_tx(dev, reg_sr);
+ 
+ 	at91_irq_err(dev);
+@@ -1158,7 +1199,7 @@ static int __devinit at91_can_probe(struct platform_device *pdev)
+ 		goto exit_release;
+ 	}
+ 
+-	dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM);
++	dev = alloc_candev(sizeof(struct at91_priv), 1 << AT91_MB_TX_SHIFT);
+ 	if (!dev) {
+ 		err = -ENOMEM;
+ 		goto exit_iounmap;
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0069-can-at91_can-add-id_table-and-convert-prime-mailbox-.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0069-can-at91_can-add-id_table-and-convert-prime-mailbox-.patch
new file mode 100644
index 0000000..d9cee95
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0069-can-at91_can-add-id_table-and-convert-prime-mailbox-.patch
@@ -0,0 +1,337 @@
+From ba269f591624cb00895324940c224d8ba8f6af95 Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Tue, 3 May 2011 17:41:09 +0200
+Subject: [PATCH 069/107] can: at91_can: add id_table and convert prime
+ mailbox constats to functions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is the second of two patches converting the at91_can driver from a
+compile time mailbox setup to a dynamic one.
+
+This patch first adds a id_table to the platform driver. Depending on the
+driver_data the constants for the mailbox setup is selected. Then all
+remaining prime mailbox constants are converted to functions, using the
+run time selected mailbox constants.
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Applied-Upstream: v3.1, commit:d3d4726
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/net/can/at91_can.c |  137 +++++++++++++++++++++++++++++++------------
+ 1 files changed, 99 insertions(+), 38 deletions(-)
+
+diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
+index 900ff67..248e03f 100644
+--- a/drivers/net/can/at91_can.c
++++ b/drivers/net/can/at91_can.c
+@@ -41,20 +41,7 @@
+ 
+ #include <mach/board.h>
+ 
+-#define AT91_NAPI_WEIGHT	11
+-
+-/*
+- * RX/TX Mailbox split
+- * don't dare to touch
+- */
+-#define AT91_MB_TX_SHIFT	2
+-
+-#define AT91_MB_RX_FIRST	1
+-#define AT91_MB_RX_LAST		11
+-
+ #define AT91_MB_MASK(i)		((1 << (i)) - 1)
+-#define AT91_MB_RX_SPLIT	8
+-
+ 
+ /* Common registers */
+ enum at91_reg {
+@@ -138,6 +125,18 @@ enum at91_mb_mode {
+ 
+ #define AT91_IRQ_ALL		(0x1fffffff)
+ 
++enum at91_devtype {
++	AT91_DEVTYPE_SAM9263,
++};
++
++struct at91_devtype_data {
++	unsigned int rx_first;
++	unsigned int rx_split;
++	unsigned int rx_last;
++	unsigned int tx_shift;
++	enum at91_devtype type;
++};
++
+ struct at91_priv {
+ 	struct can_priv can;		/* must be the first member! */
+ 	struct net_device *dev;
+@@ -149,6 +148,7 @@ struct at91_priv {
+ 	unsigned int tx_next;
+ 	unsigned int tx_echo;
+ 	unsigned int rx_next;
++	struct at91_devtype_data devtype_data;
+ 
+ 	struct clk *clk;
+ 	struct at91_can_data *pdata;
+@@ -156,6 +156,15 @@ struct at91_priv {
+ 	canid_t mb0_id;
+ };
+ 
++static const struct at91_devtype_data at91_devtype_data[] __devinitconst = {
++	[AT91_DEVTYPE_SAM9263] = {
++		.rx_first = 1,
++		.rx_split = 8,
++		.rx_last = 11,
++		.tx_shift = 2,
++	},
++};
++
+ static struct can_bittiming_const at91_bittiming_const = {
+ 	.name		= KBUILD_MODNAME,
+ 	.tseg1_min	= 4,
+@@ -168,25 +177,58 @@ static struct can_bittiming_const at91_bittiming_const = {
+ 	.brp_inc	= 1,
+ };
+ 
++#define AT91_IS(_model) \
++static inline int at91_is_sam##_model(const struct at91_priv *priv) \
++{ \
++	return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
++}
++
++AT91_IS(9263);
++
++static inline unsigned int get_mb_rx_first(const struct at91_priv *priv)
++{
++	return priv->devtype_data.rx_first;
++}
++
++static inline unsigned int get_mb_rx_last(const struct at91_priv *priv)
++{
++	return priv->devtype_data.rx_last;
++}
++
++static inline unsigned int get_mb_rx_split(const struct at91_priv *priv)
++{
++	return priv->devtype_data.rx_split;
++}
++
++static inline unsigned int get_mb_rx_num(const struct at91_priv *priv)
++{
++	return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1;
++}
++
+ static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv)
+ {
+-	return AT91_MB_RX_SPLIT - 1;
++	return get_mb_rx_split(priv) - 1;
+ }
+ 
+ static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv)
+ {
+-	return AT91_MB_MASK(AT91_MB_RX_SPLIT) &
+-		~AT91_MB_MASK(AT91_MB_RX_FIRST);
++	return AT91_MB_MASK(get_mb_rx_split(priv)) &
++		~AT91_MB_MASK(get_mb_rx_first(priv));
++}
++
++static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv)
++{
++	return priv->devtype_data.tx_shift;
+ }
+ 
+ static inline unsigned int get_mb_tx_num(const struct at91_priv *priv)
+ {
+-	return 1 << AT91_MB_TX_SHIFT;
++	return 1 << get_mb_tx_shift(priv);
+ }
+ 
+ static inline unsigned int get_mb_tx_first(const struct at91_priv *priv)
+ {
+-	return AT91_MB_RX_LAST + 1;
++	return get_mb_rx_last(priv) + 1;
+ }
+ 
+ static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)
+@@ -196,17 +238,17 @@ static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)
+ 
+ static inline unsigned int get_next_prio_shift(const struct at91_priv *priv)
+ {
+-	return AT91_MB_TX_SHIFT;
++	return get_mb_tx_shift(priv);
+ }
+ 
+ static inline unsigned int get_next_prio_mask(const struct at91_priv *priv)
+ {
+-	return 0xf << AT91_MB_TX_SHIFT;
++	return 0xf << get_mb_tx_shift(priv);
+ }
+ 
+ static inline unsigned int get_next_mb_mask(const struct at91_priv *priv)
+ {
+-	return AT91_MB_MASK(AT91_MB_TX_SHIFT);
++	return AT91_MB_MASK(get_mb_tx_shift(priv));
+ }
+ 
+ static inline unsigned int get_next_mask(const struct at91_priv *priv)
+@@ -216,8 +258,8 @@ static inline unsigned int get_next_mask(const struct at91_priv *priv)
+ 
+ static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv)
+ {
+-	return AT91_MB_MASK(AT91_MB_RX_LAST + 1) &
+-		~AT91_MB_MASK(AT91_MB_RX_FIRST);
++	return AT91_MB_MASK(get_mb_rx_last(priv) + 1) &
++		~AT91_MB_MASK(get_mb_rx_first(priv));
+ }
+ 
+ static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv)
+@@ -299,18 +341,18 @@ static void at91_setup_mailboxes(struct net_device *dev)
+ 	 * overflow.
+ 	 */
+ 	reg_mid = at91_can_id_to_reg_mid(priv->mb0_id);
+-	for (i = 0; i < AT91_MB_RX_FIRST; i++) {
++	for (i = 0; i < get_mb_rx_first(priv); i++) {
+ 		set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
+ 		at91_write(priv, AT91_MID(i), reg_mid);
+ 		at91_write(priv, AT91_MCR(i), 0x0);	/* clear dlc */
+ 	}
+ 
+-	for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++)
++	for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++)
+ 		set_mb_mode(priv, i, AT91_MB_MODE_RX);
+-	set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR);
++	set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR);
+ 
+ 	/* reset acceptance mask and id register */
+-	for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) {
++	for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) {
+ 		at91_write(priv, AT91_MAM(i), 0x0);
+ 		at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
+ 	}
+@@ -321,7 +363,7 @@ static void at91_setup_mailboxes(struct net_device *dev)
+ 
+ 	/* Reset tx and rx helper pointers */
+ 	priv->tx_next = priv->tx_echo = 0;
+-	priv->rx_next = AT91_MB_RX_FIRST;
++	priv->rx_next = get_mb_rx_first(priv);
+ }
+ 
+ static int at91_set_bittiming(struct net_device *dev)
+@@ -415,8 +457,8 @@ static void at91_chip_stop(struct net_device *dev, enum can_state state)
+  * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
+  * encode the mailbox number, the upper 4 bits the mailbox priority:
+  *
+- * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) |
+- *                 (mb - AT91_MB_TX_FIRST);
++ * priv->tx_next = (prio << get_next_prio_shift(priv)) |
++ *                 (mb - get_mb_tx_first(priv));
+  *
+  */
+ static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
+@@ -565,7 +607,7 @@ static void at91_read_mb(struct net_device *dev, unsigned int mb,
+ 	/* allow RX of extended frames */
+ 	at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
+ 
+-	if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI))
++	if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI))
+ 		at91_rx_overflow_err(dev);
+ }
+ 
+@@ -603,8 +645,9 @@ static void at91_read_msg(struct net_device *dev, unsigned int mb)
+  *
+  * Theory of Operation:
+  *
+- * 11 of the 16 mailboxes on the chip are reserved for RX. we split
+- * them into 2 groups. The lower group holds 7 and upper 4 mailboxes.
++ * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last())
++ * on the chip are reserved for RX. We split them into 2 groups. The
++ * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last().
+  *
+  * Like it or not, but the chip always saves a received CAN message
+  * into the first free mailbox it finds (starting with the
+@@ -678,8 +721,8 @@ static int at91_poll_rx(struct net_device *dev, int quota)
+ 
+ 	/* upper group completed, look again in lower */
+ 	if (priv->rx_next > get_mb_rx_low_last(priv) &&
+-	    quota > 0 && mb > AT91_MB_RX_LAST) {
+-		priv->rx_next = AT91_MB_RX_FIRST;
++	    quota > 0 && mb > get_mb_rx_last(priv)) {
++		priv->rx_next = get_mb_rx_first(priv);
+ 		goto again;
+ 	}
+ 
+@@ -1165,6 +1208,8 @@ static struct attribute_group at91_sysfs_attr_group = {
+ 
+ static int __devinit at91_can_probe(struct platform_device *pdev)
+ {
++	const struct at91_devtype_data *devtype_data;
++	enum at91_devtype devtype;
+ 	struct net_device *dev;
+ 	struct at91_priv *priv;
+ 	struct resource *res;
+@@ -1172,6 +1217,9 @@ static int __devinit at91_can_probe(struct platform_device *pdev)
+ 	void __iomem *addr;
+ 	int err, irq;
+ 
++	devtype = pdev->id_entry->driver_data;
++	devtype_data = &at91_devtype_data[devtype];
++
+ 	clk = clk_get(&pdev->dev, "can_clk");
+ 	if (IS_ERR(clk)) {
+ 		dev_err(&pdev->dev, "no clock defined\n");
+@@ -1199,7 +1247,8 @@ static int __devinit at91_can_probe(struct platform_device *pdev)
+ 		goto exit_release;
+ 	}
+ 
+-	dev = alloc_candev(sizeof(struct at91_priv), 1 << AT91_MB_TX_SHIFT);
++	dev = alloc_candev(sizeof(struct at91_priv),
++			   1 << devtype_data->tx_shift);
+ 	if (!dev) {
+ 		err = -ENOMEM;
+ 		goto exit_iounmap;
+@@ -1216,13 +1265,15 @@ static int __devinit at91_can_probe(struct platform_device *pdev)
+ 	priv->can.do_set_mode = at91_set_mode;
+ 	priv->can.do_get_berr_counter = at91_get_berr_counter;
+ 	priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
+-	priv->reg_base = addr;
+ 	priv->dev = dev;
++	priv->reg_base = addr;
++	priv->devtype_data = *devtype_data;
++	priv->devtype_data.type = devtype;
+ 	priv->clk = clk;
+ 	priv->pdata = pdev->dev.platform_data;
+ 	priv->mb0_id = 0x7ff;
+ 
+-	netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT);
++	netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv));
+ 
+ 	dev_set_drvdata(&pdev->dev, dev);
+ 	SET_NETDEV_DEV(dev, &pdev->dev);
+@@ -1272,6 +1323,15 @@ static int __devexit at91_can_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++static const struct platform_device_id at91_can_id_table[] = {
++	{
++		.name = "at91_can",
++		.driver_data = AT91_DEVTYPE_SAM9263,
++	}, {
++		/* sentinel */
++	}
++};
++
+ static struct platform_driver at91_can_driver = {
+ 	.probe = at91_can_probe,
+ 	.remove = __devexit_p(at91_can_remove),
+@@ -1279,6 +1339,7 @@ static struct platform_driver at91_can_driver = {
+ 		.name = KBUILD_MODNAME,
+ 		.owner = THIS_MODULE,
+ 	},
++	.id_table = at91_can_id_table,
+ };
+ 
+ static int __init at91_can_module_init(void)
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0070-can-at91_can-register-mb0-sysfs-entry-only-on-at91sa.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0070-can-at91_can-register-mb0-sysfs-entry-only-on-at91sa.patch
new file mode 100644
index 0000000..dcf155a
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0070-can-at91_can-register-mb0-sysfs-entry-only-on-at91sa.patch
@@ -0,0 +1,45 @@
+From d2c865e1724b16dcdd5156d8c1d2d2cf6f4129dc Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Wed, 1 Jun 2011 00:20:17 +0200
+Subject: [PATCH 070/107] can: at91_can: register mb0 sysfs entry only on
+ at91sam9263
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch prepares the driver for the at91sam9X5 processors,
+which don't have the mb0 bug.
+(See commit 3a5655a5b545e9647c3437473ee3d815fe1b9050 for more details.)
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Applied-Upstream: v3.1, commit:07a648e
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/net/can/at91_can.c |    4 +++-
+ 1 files changed, 3 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
+index 248e03f..2b97281 100644
+--- a/drivers/net/can/at91_can.c
++++ b/drivers/net/can/at91_can.c
+@@ -1257,7 +1257,6 @@ static int __devinit at91_can_probe(struct platform_device *pdev)
+ 	dev->netdev_ops	= &at91_netdev_ops;
+ 	dev->irq = irq;
+ 	dev->flags |= IFF_ECHO;
+-	dev->sysfs_groups[0] = &at91_sysfs_attr_group;
+ 
+ 	priv = netdev_priv(dev);
+ 	priv->can.clock.freq = clk_get_rate(clk);
+@@ -1275,6 +1274,9 @@ static int __devinit at91_can_probe(struct platform_device *pdev)
+ 
+ 	netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv));
+ 
++	if (at91_is_sam9263(priv))
++		dev->sysfs_groups[0] = &at91_sysfs_attr_group;
++
+ 	dev_set_drvdata(&pdev->dev, dev);
+ 	SET_NETDEV_DEV(dev, &pdev->dev);
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0071-can-at91_can-add-support-for-the-AT91SAM9X5-SOCs.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0071-can-at91_can-add-support-for-the-AT91SAM9X5-SOCs.patch
new file mode 100644
index 0000000..dc96db0
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0071-can-at91_can-add-support-for-the-AT91SAM9X5-SOCs.patch
@@ -0,0 +1,139 @@
+From a46409cbd2b3141e654b30d8a987ef4a09c7d40a Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Sun, 17 Apr 2011 00:08:45 +0200
+Subject: [PATCH 071/107] can: at91_can: add support for the AT91SAM9X5 SOCs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The AT91SAM9X5 SOCs have a similar CAN core, but they only have 8 compared
+to 16 mailboxes on the AT91SAM9263 SOC. Another difference is that the bits
+defining the state of the CAN core are cleared on read, thus the driver
+has to derive the state by looking at the error counters.
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Applied-Upstream: v3.1, commit:6388b39
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/net/can/at91_can.c |   69 +++++++++++++++++++++++++++++++++++---------
+ 1 files changed, 55 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
+index 2b97281..121ede6 100644
+--- a/drivers/net/can/at91_can.c
++++ b/drivers/net/can/at91_can.c
+@@ -127,6 +127,7 @@ enum at91_mb_mode {
+ 
+ enum at91_devtype {
+ 	AT91_DEVTYPE_SAM9263,
++	AT91_DEVTYPE_SAM9X5,
+ };
+ 
+ struct at91_devtype_data {
+@@ -163,6 +164,12 @@ static const struct at91_devtype_data at91_devtype_data[] __devinitconst = {
+ 		.rx_last = 11,
+ 		.tx_shift = 2,
+ 	},
++	[AT91_DEVTYPE_SAM9X5] = {
++		.rx_first = 0,
++		.rx_split = 4,
++		.rx_last = 5,
++		.tx_shift = 1,
++	},
+ };
+ 
+ static struct can_bittiming_const at91_bittiming_const = {
+@@ -184,6 +191,7 @@ static inline int at91_is_sam##_model(const struct at91_priv *priv) \
+ }
+ 
+ AT91_IS(9263);
++AT91_IS(9X5);
+ 
+ static inline unsigned int get_mb_rx_first(const struct at91_priv *priv)
+ {
+@@ -991,6 +999,29 @@ static void at91_irq_err_state(struct net_device *dev,
+ 	at91_write(priv, AT91_IER, reg_ier);
+ }
+ 
++static int at91_get_state_by_bec(const struct net_device *dev,
++		enum can_state *state)
++{
++	struct can_berr_counter bec;
++	int err;
++
++	err = at91_get_berr_counter(dev, &bec);
++	if (err)
++		return err;
++
++	if (bec.txerr < 96 && bec.rxerr < 96)
++		*state = CAN_STATE_ERROR_ACTIVE;
++	else if (bec.txerr < 128 && bec.rxerr < 128)
++		*state = CAN_STATE_ERROR_WARNING;
++	else if (bec.txerr < 256 && bec.rxerr < 256)
++		*state = CAN_STATE_ERROR_PASSIVE;
++	else
++		*state = CAN_STATE_BUS_OFF;
++
++	return 0;
++}
++
++
+ static void at91_irq_err(struct net_device *dev)
+ {
+ 	struct at91_priv *priv = netdev_priv(dev);
+@@ -998,21 +1029,28 @@ static void at91_irq_err(struct net_device *dev)
+ 	struct can_frame *cf;
+ 	enum can_state new_state;
+ 	u32 reg_sr;
++	int err;
+ 
+-	reg_sr = at91_read(priv, AT91_SR);
+-
+-	/* we need to look at the unmasked reg_sr */
+-	if (unlikely(reg_sr & AT91_IRQ_BOFF))
+-		new_state = CAN_STATE_BUS_OFF;
+-	else if (unlikely(reg_sr & AT91_IRQ_ERRP))
+-		new_state = CAN_STATE_ERROR_PASSIVE;
+-	else if (unlikely(reg_sr & AT91_IRQ_WARN))
+-		new_state = CAN_STATE_ERROR_WARNING;
+-	else if (likely(reg_sr & AT91_IRQ_ERRA))
+-		new_state = CAN_STATE_ERROR_ACTIVE;
+-	else {
+-		netdev_err(dev, "BUG! hardware in undefined state\n");
+-		return;
++	if (at91_is_sam9263(priv)) {
++		reg_sr = at91_read(priv, AT91_SR);
++
++		/* we need to look at the unmasked reg_sr */
++		if (unlikely(reg_sr & AT91_IRQ_BOFF))
++			new_state = CAN_STATE_BUS_OFF;
++		else if (unlikely(reg_sr & AT91_IRQ_ERRP))
++			new_state = CAN_STATE_ERROR_PASSIVE;
++		else if (unlikely(reg_sr & AT91_IRQ_WARN))
++			new_state = CAN_STATE_ERROR_WARNING;
++		else if (likely(reg_sr & AT91_IRQ_ERRA))
++			new_state = CAN_STATE_ERROR_ACTIVE;
++		else {
++			netdev_err(dev, "BUG! hardware in undefined state\n");
++			return;
++		}
++	} else {
++		err = at91_get_state_by_bec(dev, &new_state);
++		if (err)
++			return;
+ 	}
+ 
+ 	/* state hasn't changed */
+@@ -1330,6 +1368,9 @@ static const struct platform_device_id at91_can_id_table[] = {
+ 		.name = "at91_can",
+ 		.driver_data = AT91_DEVTYPE_SAM9263,
+ 	}, {
++		.name = "at91sam9x5_can",
++		.driver_data = AT91_DEVTYPE_SAM9X5,
++	}, {
+ 		/* sentinel */
+ 	}
+ };
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0072-media-V4L-videobuf2-memops-use-pr_debug-for-debug-me.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0072-media-V4L-videobuf2-memops-use-pr_debug-for-debug-me.patch
new file mode 100644
index 0000000..19a8529
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0072-media-V4L-videobuf2-memops-use-pr_debug-for-debug-me.patch
@@ -0,0 +1,51 @@
+From fe4fd5253bfef5de174fd5c4ca69de6f9b91ddaa Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Wed, 1 Jun 2011 22:13:59 +0200
+Subject: [PATCH 072/107] [media] V4L/videobuf2-memops: use pr_debug for debug
+ messages
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Otherwise they clutter the dmesg buffer even on a production kernel.
+
+Forwarded: 1306959563-7108-1-git-send-email-u.kleine-koenig@pengutronix.de
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/media/video/videobuf2-memops.c |    6 +++---
+ 1 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/video/videobuf2-memops.c b/drivers/media/video/videobuf2-memops.c
+index 5370a3a..1987e1b1 100644
+--- a/drivers/media/video/videobuf2-memops.c
++++ b/drivers/media/video/videobuf2-memops.c
+@@ -177,7 +177,7 @@ int vb2_mmap_pfn_range(struct vm_area_struct *vma, unsigned long paddr,
+ 
+ 	vma->vm_ops->open(vma);
+ 
+-	printk(KERN_DEBUG "%s: mapped paddr 0x%08lx at 0x%08lx, size %ld\n",
++	pr_debug("%s: mapped paddr 0x%08lx at 0x%08lx, size %ld\n",
+ 			__func__, paddr, vma->vm_start, size);
+ 
+ 	return 0;
+@@ -195,7 +195,7 @@ static void vb2_common_vm_open(struct vm_area_struct *vma)
+ {
+ 	struct vb2_vmarea_handler *h = vma->vm_private_data;
+ 
+-	printk(KERN_DEBUG "%s: %p, refcount: %d, vma: %08lx-%08lx\n",
++	pr_debug("%s: %p, refcount: %d, vma: %08lx-%08lx\n",
+ 	       __func__, h, atomic_read(h->refcount), vma->vm_start,
+ 	       vma->vm_end);
+ 
+@@ -213,7 +213,7 @@ static void vb2_common_vm_close(struct vm_area_struct *vma)
+ {
+ 	struct vb2_vmarea_handler *h = vma->vm_private_data;
+ 
+-	printk(KERN_DEBUG "%s: %p, refcount: %d, vma: %08lx-%08lx\n",
++	pr_debug("%s: %p, refcount: %d, vma: %08lx-%08lx\n",
+ 	       __func__, h, atomic_read(h->refcount), vma->vm_start,
+ 	       vma->vm_end);
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0073-video-atmelfb-initially-split-atmelfb-into-a-driver-.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0073-video-atmelfb-initially-split-atmelfb-into-a-driver-.patch
new file mode 100644
index 0000000..4ff9d16
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0073-video-atmelfb-initially-split-atmelfb-into-a-driver-.patch
@@ -0,0 +1,2622 @@
+From f6a5d666df5107051f4b716b8ed7e8e9a8a2d06a Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Thu, 19 May 2011 09:42:55 +0200
+Subject: [PATCH 073/107] video: atmelfb: initially split atmelfb into a
+ driver and library part
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/Makefile           |    2 +-
+ drivers/video/atmel_lcdfb.c      | 1410 +-------------------------------------
+ drivers/video/atmel_lcdfb_core.c | 1077 +++++++++++++++++++++++++++++
+ include/video/atmel_lcdc.h       |   17 +-
+ 4 files changed, 1104 insertions(+), 1402 deletions(-)
+ create mode 100644 drivers/video/atmel_lcdfb_core.c
+
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index 2ea44b6..e963559 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -91,7 +91,7 @@ obj-$(CONFIG_FB_EP93XX)		  += ep93xx-fb.o
+ obj-$(CONFIG_FB_SA1100)           += sa1100fb.o
+ obj-$(CONFIG_FB_HIT)              += hitfb.o
+ obj-$(CONFIG_FB_EPSON1355)	  += epson1355fb.o
+-obj-$(CONFIG_FB_ATMEL)		  += atmel_lcdfb.o
++obj-$(CONFIG_FB_ATMEL)		  += atmel_lcdfb.o atmel_lcdfb_core.o
+ obj-$(CONFIG_FB_PVR2)             += pvr2fb.o
+ obj-$(CONFIG_FB_VOODOO1)          += sstfb.o
+ obj-$(CONFIG_FB_ARMCLCD)	  += amba-clcd.o
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index 2a943ae..4e1454c 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -10,1384 +10,12 @@
+ 
+ #include <linux/kernel.h>
+ #include <linux/platform_device.h>
+-#include <linux/dma-mapping.h>
+ #include <linux/interrupt.h>
+-#include <linux/clk.h>
+ #include <linux/fb.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+-#include <linux/backlight.h>
+-#include <linux/gfp.h>
+-
+-#include <mach/board.h>
+-#include <mach/cpu.h>
+-#include <mach/gpio.h>
+ 
+ #include <video/atmel_lcdc.h>
+-#include <mach/atmel_hlcdfb.h>
+-
+-#define lcdc_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
+-#define lcdc_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
+-
+-/* configurable parameters */
+-#define ATMEL_LCDC_CVAL_DEFAULT		0xc8
+-#define ATMEL_LCDC_DMA_BURST_LEN	8	/* words */
+-#define ATMEL_LCDC_FIFO_SIZE		512	/* words */
+-
+-#if defined(CONFIG_ARCH_AT91)
+-#define	ATMEL_LCDFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
+-					 | FBINFO_PARTIAL_PAN_OK \
+-					 | FBINFO_HWACCEL_YPAN)
+-
+-static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
+-					struct fb_var_screeninfo *var)
+-{
+-
+-}
+-#elif defined(CONFIG_AVR32)
+-#define	ATMEL_LCDFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
+-					| FBINFO_PARTIAL_PAN_OK \
+-					| FBINFO_HWACCEL_XPAN \
+-					| FBINFO_HWACCEL_YPAN)
+-
+-static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
+-				     struct fb_var_screeninfo *var)
+-{
+-	u32 dma2dcfg;
+-	u32 pixeloff;
+-
+-	pixeloff = (var->xoffset * var->bits_per_pixel) & 0x1f;
+-
+-	dma2dcfg = ((var->xres_virtual - var->xres) * var->bits_per_pixel) / 8;
+-	dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
+-
+-	/* Update configuration */
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
+-		    lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
+-		    | ATMEL_LCDC_DMAUPDT);
+-}
+-#endif
+-
+-static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
+-		| ATMEL_LCDC_POL_POSITIVE
+-		| ATMEL_LCDC_ENA_PWMENABLE;
+-
+-static const u32 contrast_pwm_ctr = LCDC_LCDCFG6_PWMPOL
+-		| (ATMEL_LCDC_CVAL_DEFAULT << LCDC_LCDCFG6_PWMCVAL_OFFSET);
+-
+-#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
+-
+-/* some bl->props field just changed */
+-static int atmel_bl_update_status(struct backlight_device *bl)
+-{
+-	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
+-	int			power = sinfo->bl_power;
+-	int			brightness = bl->props.brightness;
+-	u32			reg;
+-
+-	/* REVISIT there may be a meaningful difference between
+-	 * fb_blank and power ... there seem to be some cases
+-	 * this doesn't handle correctly.
+-	 */
+-	if (bl->props.fb_blank != sinfo->bl_power)
+-		power = bl->props.fb_blank;
+-	else if (bl->props.power != sinfo->bl_power)
+-		power = bl->props.power;
+-
+-	if (brightness < 0 && power == FB_BLANK_UNBLANK) {
+-		if (cpu_is_at91sam9x5())
+-			brightness = lcdc_readl(sinfo, ATMEL_LCDC_LCDCFG6)
+-				     >> LCDC_LCDCFG6_PWMCVAL_OFFSET;
+-		else
+-			brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
+-	} else if (power != FB_BLANK_UNBLANK) {
+-		brightness = 0;
+-	}
+-
+-	if (cpu_is_at91sam9x5()) {
+-		reg = lcdc_readl(sinfo, ATMEL_LCDC_LCDCFG6) & ~LCDC_LCDCFG6_PWMCVAL;
+-		reg |= brightness << LCDC_LCDCFG6_PWMCVAL_OFFSET;
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG6, reg);
+-	} else {
+-		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
+-		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
+-				brightness ? contrast_ctr : 0);
+-	}
+-
+-	bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
+-
+-	return 0;
+-}
+-
+-static int atmel_bl_get_brightness(struct backlight_device *bl)
+-{
+-	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
+-
+-	if (cpu_is_at91sam9x5())
+-		return lcdc_readl(sinfo, ATMEL_LCDC_LCDCFG6) >> LCDC_LCDCFG6_PWMCVAL_OFFSET;
+-	else
+-		return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
+-}
+-
+-static const struct backlight_ops atmel_lcdc_bl_ops = {
+-	.update_status = atmel_bl_update_status,
+-	.get_brightness = atmel_bl_get_brightness,
+-};
+-
+-static void init_backlight(struct atmel_lcdfb_info *sinfo)
+-{
+-	struct backlight_properties props;
+-	struct backlight_device	*bl;
+-
+-	sinfo->bl_power = FB_BLANK_UNBLANK;
+-
+-	if (sinfo->backlight)
+-		return;
+-
+-	memset(&props, 0, sizeof(struct backlight_properties));
+-	props.type = BACKLIGHT_RAW;
+-	props.max_brightness = 0xff;
+-	bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo,
+-				       &atmel_lcdc_bl_ops, &props);
+-	if (IS_ERR(bl)) {
+-		dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
+-				PTR_ERR(bl));
+-		return;
+-	}
+-	sinfo->backlight = bl;
+-
+-	bl->props.power = FB_BLANK_UNBLANK;
+-	bl->props.fb_blank = FB_BLANK_UNBLANK;
+-	bl->props.brightness = atmel_bl_get_brightness(bl);
+-}
+-
+-static void exit_backlight(struct atmel_lcdfb_info *sinfo)
+-{
+-	if (sinfo->backlight)
+-		backlight_device_unregister(sinfo->backlight);
+-}
+-
+-#else
+-
+-static void init_backlight(struct atmel_lcdfb_info *sinfo)
+-{
+-	dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
+-}
+-
+-static void exit_backlight(struct atmel_lcdfb_info *sinfo)
+-{
+-}
+-
+-#endif
+-
+-static void init_contrast(struct atmel_lcdfb_info *sinfo)
+-{
+-	if (cpu_is_at91sam9x5()) {
+-		/* have some default contrast/backlight settings */
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG6, contrast_pwm_ctr);
+-	} else {
+-		/* contrast pwm can be 'inverted' */
+-		if (sinfo->lcdcon_pol_negative)
+-				contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
+-		/* have some default contrast/backlight settings */
+-		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
+-		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
+-	}
+-	if (sinfo->lcdcon_is_backlight)
+-		init_backlight(sinfo);
+-}
+-
+-
+-static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
+-	.type		= FB_TYPE_PACKED_PIXELS,
+-	.visual		= FB_VISUAL_TRUECOLOR,
+-	.xpanstep	= 0,
+-	.ypanstep	= 1,
+-	.ywrapstep	= 0,
+-	.accel		= FB_ACCEL_NONE,
+-};
+-
+-static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
+-{
+-	unsigned long value;
+-
+-	if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
+-		|| cpu_is_at32ap7000()))
+-		return xres;
+-
+-	value = xres;
+-	if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
+-		/* STN display */
+-		if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
+-			value *= 3;
+-		}
+-		if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
+-		   || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
+-		      && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
+-			value = DIV_ROUND_UP(value, 4);
+-		else
+-			value = DIV_ROUND_UP(value, 8);
+-	}
+-
+-	return value;
+-}
+-
+-static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
+-{
+-	if (cpu_is_at91sam9x5()) {
+-		/* Disable DISP signal */
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_DISPDIS);
+-		while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_DISPSTS))
+-			msleep(1);
+-		/* Disable synchronization */
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_SYNCDIS);
+-		while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_LCDSTS))
+-			msleep(1);
+-		/* Disable pixel clock */
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_CLKDIS);
+-		while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_CLKSTS))
+-			msleep(1);
+-		/* Disable PWM */
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_PWMDIS);
+-		while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_PWMSTS))
+-			msleep(1);
+-	} else {
+-		/* Turn off the LCD controller and the DMA controller */
+-		lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
+-				sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
+-
+-		/* Wait for the LCDC core to become idle */
+-		while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
+-			msleep(10);
+-
+-		lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
+-	}
+-}
+-
+-static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
+-{
+-	atmel_lcdfb_stop_nowait(sinfo);
+-
+-	if (cpu_is_at91sam9x5()) {
+-		/* Wait for the end of DMA transfer */
+-		while (!(lcdc_readl(sinfo, ATMEL_LCDC_BASEISR) & LCDC_BASEISR_DMA))
+-			msleep(10);
+-	} else {
+-		/* Wait for DMA engine to become idle... */
+-		while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
+-			msleep(10);
+-	}
+-}
+-
+-static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
+-{
+-	u32	value;
+-
+-	if (cpu_is_at91sam9x5()) {
+-		value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_CLKEN);
+-		while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_CLKSTS))
+-			msleep(1);
+-		value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_SYNCEN);
+-		while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_LCDSTS))
+-			msleep(1);
+-		value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_DISPEN);
+-		while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_DISPSTS))
+-			msleep(1);
+-		value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_PWMEN);
+-		while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_PWMSTS))
+-			msleep(1);
+-	} else {
+-		lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
+-		lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
+-			(sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
+-			| ATMEL_LCDC_PWR);
+-	}
+-}
+-
+-static void atmel_lcdfb_update_dma(struct fb_info *info,
+-			       struct fb_var_screeninfo *var)
+-{
+-	struct atmel_lcdfb_info *sinfo = info->par;
+-	struct fb_fix_screeninfo *fix = &info->fix;
+-	unsigned long dma_addr;
+-	struct lcd_dma_desc *desc;
+-
+-	dma_addr = (fix->smem_start + var->yoffset * fix->line_length
+-		    + var->xoffset * var->bits_per_pixel / 8);
+-
+-	dma_addr &= ~3UL;
+-
+-	if (cpu_is_at91sam9x5()) {
+-		/* Setup the DMA descriptor, this descriptor will loop to itself */
+-		desc = (struct lcd_dma_desc *)sinfo->p_dma_desc;
+-
+-		desc->address = dma_addr;
+-		/* Disable DMA transfer interrupt & descriptor loaded interrupt. */
+-		desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
+-				| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
+-		desc->next = sinfo->dma_desc_phys;
+-
+-		lcdc_writel(sinfo, ATMEL_LCDC_BASEADDR, dma_addr);
+-		lcdc_writel(sinfo, ATMEL_LCDC_BASECTRL, desc->control);
+-		lcdc_writel(sinfo, ATMEL_LCDC_BASENEXT, sinfo->dma_desc_phys);
+-		lcdc_writel(sinfo, ATMEL_LCDC_BASECHER, LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN);
+-	} else {
+-		/* Set framebuffer DMA base address and pixel offset */
+-		lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
+-	}
+-
+-	atmel_lcdfb_update_dma2d(sinfo, var);
+-}
+-
+-static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
+-{
+-	struct fb_info *info = sinfo->info;
+-
+-	dma_free_writecombine(info->device, info->fix.smem_len,
+-				info->screen_base, info->fix.smem_start);
+-
+-	if (cpu_is_at91sam9x5()) {
+-		if (sinfo->p_dma_desc)
+-			dma_free_writecombine(info->device, sizeof(struct lcd_dma_desc),
+-						sinfo->p_dma_desc, sinfo->dma_desc_phys);
+-	}
+-}
+-
+-/**
+- *	atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
+- *	@sinfo: the frame buffer to allocate memory for
+- *
+- * 	This function is called only from the atmel_lcdfb_probe()
+- * 	so no locking by fb_info->mm_lock around smem_len setting is needed.
+- */
+-static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
+-{
+-	struct fb_info *info = sinfo->info;
+-	struct fb_var_screeninfo *var = &info->var;
+-	unsigned int smem_len;
+-
+-	smem_len = (var->xres_virtual * var->yres_virtual
+-		    * ((var->bits_per_pixel + 7) / 8));
+-	info->fix.smem_len = max(smem_len, sinfo->smem_len);
+-
+-	info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len,
+-					(dma_addr_t *)&info->fix.smem_start, GFP_KERNEL);
+-
+-	if (!info->screen_base) {
+-		return -ENOMEM;
+-	}
+-
+-	memset(info->screen_base, 0, info->fix.smem_len);
+-
+-	if (cpu_is_at91sam9x5()) {
+-		sinfo->p_dma_desc = dma_alloc_writecombine(info->device,
+-						sizeof(struct lcd_dma_desc),
+-						(dma_addr_t *)&(sinfo->dma_desc_phys),
+-						GFP_KERNEL);
+-
+-		if (!sinfo->p_dma_desc) {
+-			dma_free_writecombine(info->device, info->fix.smem_len,
+-						info->screen_base, info->fix.smem_start);
+-			return -ENOMEM;
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+-static const struct fb_videomode *atmel_lcdfb_choose_mode(struct fb_var_screeninfo *var,
+-						     struct fb_info *info)
+-{
+-	struct fb_videomode varfbmode;
+-	const struct fb_videomode *fbmode = NULL;
+-
+-	fb_var_to_videomode(&varfbmode, var);
+-	fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist);
+-	if (fbmode)
+-		fb_videomode_to_var(var, fbmode);
+-	return fbmode;
+-}
+-
+-
+-/**
+- *      atmel_lcdfb_check_var - Validates a var passed in.
+- *      @var: frame buffer variable screen structure
+- *      @info: frame buffer structure that represents a single frame buffer
+- *
+- *	Checks to see if the hardware supports the state requested by
+- *	var passed in. This function does not alter the hardware
+- *	state!!!  This means the data stored in struct fb_info and
+- *	struct atmel_lcdfb_info do not change. This includes the var
+- *	inside of struct fb_info.  Do NOT change these. This function
+- *	can be called on its own if we intent to only test a mode and
+- *	not actually set it. The stuff in modedb.c is a example of
+- *	this. If the var passed in is slightly off by what the
+- *	hardware can support then we alter the var PASSED in to what
+- *	we can do. If the hardware doesn't support mode change a
+- *	-EINVAL will be returned by the upper layers. You don't need
+- *	to implement this function then. If you hardware doesn't
+- *	support changing the resolution then this function is not
+- *	needed. In this case the driver would just provide a var that
+- *	represents the static state the screen is in.
+- *
+- *	Returns negative errno on error, or zero on success.
+- */
+-static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
+-			     struct fb_info *info)
+-{
+-	struct device *dev = info->device;
+-	struct atmel_lcdfb_info *sinfo = info->par;
+-	unsigned long clk_value_khz;
+-
+-	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+-
+-	dev_dbg(dev, "%s:\n", __func__);
+-
+-	if (!(var->pixclock && var->bits_per_pixel)) {
+-		/* choose a suitable mode if possible */
+-		if (!atmel_lcdfb_choose_mode(var, info)) {
+-			dev_err(dev, "needed value not specified\n");
+-			return -EINVAL;
+-		}
+-	}
+-
+-	dev_dbg(dev, "  resolution: %ux%u\n", var->xres, var->yres);
+-	dev_dbg(dev, "  pixclk:     %lu KHz\n", PICOS2KHZ(var->pixclock));
+-	dev_dbg(dev, "  bpp:        %u\n", var->bits_per_pixel);
+-	dev_dbg(dev, "  clk:        %lu KHz\n", clk_value_khz);
+-
+-	if (PICOS2KHZ(var->pixclock) > clk_value_khz) {
+-		dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
+-		return -EINVAL;
+-	}
+-
+-	/* Do not allow to have real resoulution larger than virtual */
+-	if (var->xres > var->xres_virtual)
+-		var->xres_virtual = var->xres;
+-
+-	if (var->yres > var->yres_virtual)
+-		var->yres_virtual = var->yres;
+-
+-	/* Force same alignment for each line */
+-	var->xres = (var->xres + 3) & ~3UL;
+-	var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
+-
+-	var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
+-	var->transp.msb_right = 0;
+-	var->transp.offset = var->transp.length = 0;
+-	var->xoffset = var->yoffset = 0;
+-
+-	if (info->fix.smem_len) {
+-		unsigned int smem_len = (var->xres_virtual * var->yres_virtual
+-					 * ((var->bits_per_pixel + 7) / 8));
+-		if (smem_len > info->fix.smem_len)
+-			return -EINVAL;
+-	}
+-
+-	/* Saturate vertical and horizontal timings at maximum values */
+-	if (cpu_is_at91sam9x5()) {
+-		var->vsync_len = min_t(u32, var->vsync_len,
+-				(LCDC_LCDCFG1_VSPW >> LCDC_LCDCFG1_VSPW_OFFSET) + 1);
+-		var->upper_margin = min_t(u32, var->upper_margin,
+-				(LCDC_LCDCFG2_VFPW >> LCDC_LCDCFG2_VFPW_OFFSET) + 1);
+-		var->lower_margin = min_t(u32, var->lower_margin,
+-				LCDC_LCDCFG2_VBPW >> LCDC_LCDCFG2_VBPW_OFFSET);
+-		var->right_margin = min_t(u32, var->right_margin,
+-				(LCDC_LCDCFG3_HBPW >> LCDC_LCDCFG3_HBPW_OFFSET) + 1);
+-		var->hsync_len = min_t(u32, var->hsync_len,
+-				(LCDC_LCDCFG1_HSPW >> LCDC_LCDCFG1_HSPW_OFFSET) + 1);
+-		var->left_margin = min_t(u32, var->left_margin,
+-				(LCDC_LCDCFG3_HFPW >> LCDC_LCDCFG3_HFPW_OFFSET) + 1);
+-	} else {
+-		var->vsync_len = min_t(u32, var->vsync_len,
+-				(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
+-		var->upper_margin = min_t(u32, var->upper_margin,
+-				ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
+-		var->lower_margin = min_t(u32, var->lower_margin,
+-				ATMEL_LCDC_VFP);
+-		var->right_margin = min_t(u32, var->right_margin,
+-				(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
+-		var->hsync_len = min_t(u32, var->hsync_len,
+-				(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
+-		var->left_margin = min_t(u32, var->left_margin,
+-				ATMEL_LCDC_HBP + 1);
+-	}
+-
+-	/* Some parameters can't be zero */
+-	var->vsync_len = max_t(u32, var->vsync_len, 1);
+-	var->right_margin = max_t(u32, var->right_margin, 1);
+-	var->hsync_len = max_t(u32, var->hsync_len, 1);
+-	var->left_margin = max_t(u32, var->left_margin, 1);
+-
+-	switch (var->bits_per_pixel) {
+-	case 1:
+-	case 2:
+-	case 4:
+-	case 8:
+-		var->red.offset = var->green.offset = var->blue.offset = 0;
+-		var->red.length = var->green.length = var->blue.length
+-				= var->bits_per_pixel;
+-		break;
+-	case 12:
+-		if (cpu_is_at91sam9x5()) {
+-			/* RGB:444 mode */
+-			var->red.offset = 8;
+-			var->blue.offset = 0;
+-			var->green.offset = 4;
+-			var->red.length = var->green.length = var->blue.length = 4;
+-		} else {
+-			/*TODO: rework*/
+-			BUG();
+-		}
+-		break;
+-	case 15:
+-		if (cpu_is_at91sam9x5()) {
+-			/* RGB:555 mode */
+-			var->red.offset = 10;
+-			var->blue.offset = 0;
+-			var->green.length = 5;
+-			var->red.length = var->green.length = var->blue.length = 5;
+-		} else {
+-			/*TODO: rework*/
+-			BUG();
+-		}
+-		break;
+-	case 16:
+-		if (cpu_is_at91sam9x5()) {
+-			if (sinfo->alpha_enabled) {
+-				/* ARGB:4444 mode */
+-				var->red.offset = 8;
+-				var->blue.offset = 0;
+-				var->green.offset = 4;
+-				var->transp.offset = 12;
+-				var->red.length = var->green.length
+-						= var->blue.length
+-						= var->transp.length = 4;
+-			} else {
+-				/* RGB:565 mode */
+-				var->red.offset = 11;
+-				var->blue.offset = 0;
+-				var->green.offset = 5;
+-				var->green.length = 6;
+-				var->red.length = var->blue.length = 5;
+-			}
+-			break;
+-		}
+-		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
+-			/* RGB:565 mode */
+-			var->red.offset = 11;
+-			var->blue.offset = 0;
+-			var->green.length = 6;
+-		} else if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB555) {
+-			var->red.offset = 10;
+-			var->blue.offset = 0;
+-			var->green.length = 5;
+-		} else {
+-			/* BGR:555 mode */
+-			var->red.offset = 0;
+-			var->blue.offset = 10;
+-			var->green.length = 5;
+-		}
+-		var->green.offset = 5;
+-		var->red.length = var->blue.length = 5;
+-		break;
+-	case 32:
+-		/* TODO 32 & 24 modes */
+-		var->transp.offset = 24;
+-		var->transp.length = 8;
+-		/* fall through */
+-	case 24:
+-		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
+-			/* RGB:888 mode */
+-			var->red.offset = 16;
+-			var->blue.offset = 0;
+-		} else {
+-			/* BGR:888 mode */
+-			var->red.offset = 0;
+-			var->blue.offset = 16;
+-		}
+-		var->green.offset = 8;
+-		var->red.length = var->green.length = var->blue.length = 8;
+-		break;
+-	default:
+-		dev_err(dev, "color depth %d not supported\n",
+-					var->bits_per_pixel);
+-		return -EINVAL;
+-	}
+-
+-	return 0;
+-}
+-
+-/*
+- * LCD reset sequence
+- */
+-static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
+-{
+-	might_sleep();
+-
+-	atmel_lcdfb_stop(sinfo);
+-	atmel_lcdfb_start(sinfo);
+-}
+-
+-static int atmel_lcdfb_setup_9x5_core(struct fb_info *info)
+-{
+-	struct atmel_lcdfb_info *sinfo = info->par;
+-	unsigned long value;
+-	unsigned long clk_value_khz;
+-
+-	dev_dbg(info->device, "%s:\n", __func__);
+-	/* Set pixel clock */
+-	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+-
+-	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
+-
+-	if (value < 1) {
+-		dev_notice(info->device, "using system clock as pixel clock\n");
+-		value = LCDC_LCDCFG0_CLKPOL | LCDC_LCDCFG0_CLKPWMSEL | LCDC_LCDCFG0_CGDISBASE;
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG0, value);
+-	} else {
+-		info->var.pixclock = KHZ2PICOS(clk_value_khz / value);
+-		dev_dbg(info->device, "  updated pixclk:     %lu KHz\n",
+-				PICOS2KHZ(info->var.pixclock));
+-		value = value - 2;
+-		dev_dbg(info->device, "  * programming CLKDIV = 0x%08lx\n",
+-					value);
+-		value = (value << LCDC_LCDCFG0_CLKDIV_OFFSET)
+-			| LCDC_LCDCFG0_CLKPOL
+-			| LCDC_LCDCFG0_CGDISBASE;
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG0, value);
+-	}
+-
+-	/* Initialize control register 5 */
+-	/* In 9x5, the default_lcdcon2 will use for LCDCFG5 */
+-	value = sinfo->default_lcdcon2;
+-	value |= (sinfo->guard_time << LCDC_LCDCFG5_GUARDTIME_OFFSET)
+-		| LCDC_LCDCFG5_DISPDLY
+-		| LCDC_LCDCFG5_VSPDLYS;
+-
+-	if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
+-		value |= LCDC_LCDCFG5_HSPOL;
+-	if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
+-		value |= LCDC_LCDCFG5_VSPOL;
+-
+-	dev_dbg(info->device, "  * LCDC_LCDCFG5 = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG5, value);
+-
+-	/* Vertical & Horizontal Timing */
+-	value = (info->var.vsync_len - 1) << LCDC_LCDCFG1_VSPW_OFFSET;
+-	value |= (info->var.hsync_len - 1) << LCDC_LCDCFG1_HSPW_OFFSET;
+-	dev_dbg(info->device, "  * LCDC_LCDCFG1 = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG1, value);
+-
+-	value = (info->var.lower_margin) << LCDC_LCDCFG2_VBPW_OFFSET;
+-	value |= (info->var.upper_margin - 1) << LCDC_LCDCFG2_VFPW_OFFSET;
+-	dev_dbg(info->device, "  * LCDC_LCDCFG2 = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG2, value);
+-
+-	value = (info->var.right_margin - 1) << LCDC_LCDCFG3_HBPW_OFFSET;
+-	value |= (info->var.left_margin - 1) << LCDC_LCDCFG3_HFPW_OFFSET;
+-	dev_dbg(info->device, "  * LCDC_LCDCFG3 = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG3, value);
+-
+-	/* Display size */
+-	value = (info->var.yres - 1) << LCDC_LCDCFG4_RPF_OFFSET;
+-	value |= (info->var.xres - 1) << LCDC_LCDCFG4_PPL_OFFSET;
+-	dev_dbg(info->device, "  * LCDC_LCDCFG4 = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG4, value);
+-
+-	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG0, LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
+-	switch (info->var.bits_per_pixel) {
+-	case 12:
+-		value = LCDC_BASECFG1_RGBMODE_12BPP_RGB_444;
+-		break;
+-	case 16:
+-		if (info->var.transp.offset != 0)
+-			value = LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444;
+-		else
+-			value = LCDC_BASECFG1_RGBMODE_16BPP_RGB_565;
+-		break;
+-	case 18:
+-		value = LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED;
+-		break;
+-	case 24:
+-		value = LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED;
+-		break;
+-	case 32:
+-		value = LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888;
+-		break;
+-	default:
+-		BUG();
+-		break;
+-	}
+-	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG1, value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG2, 0);
+-	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG3, 0);	/* Default color */
+-	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG4, LCDC_BASECFG4_DMA);
+-
+-	/* Disable all interrupts */
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDIDR, ~0UL);
+-	lcdc_writel(sinfo, ATMEL_LCDC_BASEIDR, ~0UL);
+-	/* Enable BASE LAYER overflow interrupts, if want to enable DMA interrupt, also need set it at LCDC_BASECTRL reg */
+-	lcdc_writel(sinfo, ATMEL_LCDC_BASEIER, LCDC_BASEIER_OVR);
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDIER, LCDC_LCDIER_FIFOERRIE | LCDC_LCDIER_BASEIE | LCDC_LCDIER_HEOIE);
+-
+-	return 0;
+-}
+-
+-static int atmel_lcdfb_setup_core(struct fb_info *info)
+-{
+-	struct atmel_lcdfb_info *sinfo = info->par;
+-	unsigned long hozval_linesz;
+-	unsigned long value;
+-	unsigned long clk_value_khz;
+-	unsigned long pix_factor = 2;
+-
+-	if (cpu_is_at91sam9x5()) {
+-		return atmel_lcdfb_setup_9x5_core(info);
+-	} else {
+-		/* ...set frame size and burst length = 8 words (?) */
+-		value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
+-		value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
+-		lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
+-
+-		/* Set pixel clock */
+-		if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
+-			pix_factor = 1;
+-
+-		clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+-
+-		value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
+-
+-		if (value < pix_factor) {
+-			dev_notice(info->device, "Bypassing pixel clock divider\n");
+-			lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
+-		} else {
+-			value = (value / pix_factor) - 1;
+-			dev_dbg(info->device, "  * programming CLKVAL = 0x%08lx\n",
+-					value);
+-			lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
+-					value << ATMEL_LCDC_CLKVAL_OFFSET);
+-			info->var.pixclock =
+-				KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
+-			dev_dbg(info->device, "  updated pixclk:     %lu KHz\n",
+-						PICOS2KHZ(info->var.pixclock));
+-		}
+-
+-
+-		/* Initialize control register 2 */
+-		value = sinfo->default_lcdcon2;
+-
+-		if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
+-			value |= ATMEL_LCDC_INVLINE_INVERTED;
+-		if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
+-			value |= ATMEL_LCDC_INVFRAME_INVERTED;
+-
+-		switch (info->var.bits_per_pixel) {
+-		case 1:
+-			value |= ATMEL_LCDC_PIXELSIZE_1;
+-			break;
+-		case 2:
+-			value |= ATMEL_LCDC_PIXELSIZE_2;
+-			break;
+-		case 4:
+-			value |= ATMEL_LCDC_PIXELSIZE_4;
+-			break;
+-		case 8:
+-			value |= ATMEL_LCDC_PIXELSIZE_8;
+-			break;
+-		case 15: /* fall through */
+-		case 16:
+-			value |= ATMEL_LCDC_PIXELSIZE_16;
+-			break;
+-		case 24:
+-			value |= ATMEL_LCDC_PIXELSIZE_24;
+-			break;
+-		case 32:
+-			value |= ATMEL_LCDC_PIXELSIZE_32;
+-			break;
+-		default:
+-			BUG();
+-			break;
+-		}
+-		dev_dbg(info->device, "  * LCDCON2 = %08lx\n", value);
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
+-
+-		/* Vertical timing */
+-		value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
+-		value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
+-		value |= info->var.lower_margin;
+-		dev_dbg(info->device, "  * LCDTIM1 = %08lx\n", value);
+-		lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
+-
+-		/* Horizontal timing */
+-		value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
+-		value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
+-		value |= (info->var.left_margin - 1);
+-		dev_dbg(info->device, "  * LCDTIM2 = %08lx\n", value);
+-		lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
+-
+-		/* Horizontal value (aka line size) */
+-		hozval_linesz = compute_hozval(info->var.xres,
+-					lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
+-
+-		/* Display size */
+-		value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
+-		value |= info->var.yres - 1;
+-		dev_dbg(info->device, "  * LCDFRMCFG = %08lx\n", value);
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
+-
+-		/* FIFO Threshold: Use formula from data sheet */
+-		value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
+-		lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
+-
+-		/* Toggle LCD_MODE every frame */
+-		lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
+-
+-		/* Disable all interrupts */
+-		lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
+-		/* Enable FIFO & DMA errors */
+-		lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
+-
+-		/* ...wait for DMA engine to become idle... */
+-		while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
+-			msleep(10);
+-
+-		return 0;
+-	}
+-}
+-
+-/**
+- *      atmel_lcdfb_set_par - Alters the hardware state.
+- *      @info: frame buffer structure that represents a single frame buffer
+- *
+- *	Using the fb_var_screeninfo in fb_info we set the resolution
+- *	of the this particular framebuffer. This function alters the
+- *	par AND the fb_fix_screeninfo stored in fb_info. It doesn't
+- *	not alter var in fb_info since we are using that data. This
+- *	means we depend on the data in var inside fb_info to be
+- *	supported by the hardware.  atmel_lcdfb_check_var is always called
+- *	before atmel_lcdfb_set_par to ensure this.  Again if you can't
+- *	change the resolution you don't need this function.
+- *
+- */
+-static int atmel_lcdfb_set_par(struct fb_info *info)
+-{
+-	struct atmel_lcdfb_info *sinfo = info->par;
+-	unsigned long bits_per_line;
+-
+-	might_sleep();
+-
+-	dev_dbg(info->device, "%s:\n", __func__);
+-	dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
+-		 info->var.xres, info->var.yres,
+-		 info->var.xres_virtual, info->var.yres_virtual);
+-
+-	atmel_lcdfb_stop_nowait(sinfo);
+-
+-	if (info->var.bits_per_pixel == 1)
+-		info->fix.visual = FB_VISUAL_MONO01;
+-	else if (info->var.bits_per_pixel <= 8)
+-		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+-	else
+-		info->fix.visual = FB_VISUAL_TRUECOLOR;
+-
+-	bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
+-	info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
+-
+-	/* Re-initialize the DMA engine... */
+-	dev_dbg(info->device, "  * update DMA engine\n");
+-	atmel_lcdfb_update_dma(info, &info->var);
+-
+-	/* Now, the LCDC core... */
+-	atmel_lcdfb_setup_core(info);
+-
+-	atmel_lcdfb_start(sinfo);
+-
+-	dev_dbg(info->device, "  * DONE\n");
+-
+-	return 0;
+-}
+-
+-static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
+-{
+-	chan &= 0xffff;
+-	chan >>= 16 - bf->length;
+-	return chan << bf->offset;
+-}
+-
+-/**
+- *  	atmel_lcdfb_setcolreg - Optional function. Sets a color register.
+- *      @regno: Which register in the CLUT we are programming
+- *      @red: The red value which can be up to 16 bits wide
+- *	@green: The green value which can be up to 16 bits wide
+- *	@blue:  The blue value which can be up to 16 bits wide.
+- *	@transp: If supported the alpha value which can be up to 16 bits wide.
+- *      @info: frame buffer info structure
+- *
+- *  	Set a single color register. The values supplied have a 16 bit
+- *  	magnitude which needs to be scaled in this function for the hardware.
+- *	Things to take into consideration are how many color registers, if
+- *	any, are supported with the current color visual. With truecolor mode
+- *	no color palettes are supported. Here a pseudo palette is created
+- *	which we store the value in pseudo_palette in struct fb_info. For
+- *	pseudocolor mode we have a limited color palette. To deal with this
+- *	we can program what color is displayed for a particular pixel value.
+- *	DirectColor is similar in that we can program each color field. If
+- *	we have a static colormap we don't need to implement this function.
+- *
+- *	Returns negative errno on error, or zero on success. In an
+- *	ideal world, this would have been the case, but as it turns
+- *	out, the other drivers return 1 on failure, so that's what
+- *	we're going to do.
+- */
+-static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
+-			     unsigned int green, unsigned int blue,
+-			     unsigned int transp, struct fb_info *info)
+-{
+-	struct atmel_lcdfb_info *sinfo = info->par;
+-	unsigned int val;
+-	u32 *pal;
+-	int ret = 1;
+-
+-	if (info->var.grayscale)
+-		red = green = blue = (19595 * red + 38470 * green
+-				      + 7471 * blue) >> 16;
+-
+-	switch (info->fix.visual) {
+-	case FB_VISUAL_TRUECOLOR:
+-		if (regno < 16) {
+-			pal = info->pseudo_palette;
+-
+-			val  = chan_to_field(red, &info->var.red);
+-			val |= chan_to_field(green, &info->var.green);
+-			val |= chan_to_field(blue, &info->var.blue);
+-
+-			pal[regno] = val;
+-			ret = 0;
+-		}
+-		break;
+-
+-	case FB_VISUAL_PSEUDOCOLOR:
+-		if (regno < 256) {
+-			val  = ((red   >> 11) & 0x001f);
+-			val |= ((green >>  6) & 0x03e0);
+-			val |= ((blue  >>  1) & 0x7c00);
+-
+-			/*
+-			 * TODO: intensity bit. Maybe something like
+-			 *   ~(red[10] ^ green[10] ^ blue[10]) & 1
+-			 */
+-
+-			lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
+-			ret = 0;
+-		}
+-		break;
+-
+-	case FB_VISUAL_MONO01:
+-		if (regno < 2) {
+-			val = (regno == 0) ? 0x00 : 0x1F;
+-			lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
+-			ret = 0;
+-		}
+-		break;
+-
+-	}
+-
+-	return ret;
+-}
+-
+-static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
+-			       struct fb_info *info)
+-{
+-	dev_dbg(info->device, "%s\n", __func__);
+-
+-	atmel_lcdfb_update_dma(info, var);
+-
+-	return 0;
+-}
+-
+-static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info)
+-{
+-	struct atmel_lcdfb_info *sinfo = info->par;
+-
+-	switch (blank_mode) {
+-	case FB_BLANK_UNBLANK:
+-	case FB_BLANK_NORMAL:
+-		atmel_lcdfb_start(sinfo);
+-		break;
+-	case FB_BLANK_VSYNC_SUSPEND:
+-	case FB_BLANK_HSYNC_SUSPEND:
+-		break;
+-	case FB_BLANK_POWERDOWN:
+-		atmel_lcdfb_stop(sinfo);
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	/* let fbcon do a soft blank for us */
+-	return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
+-}
+-
+-static struct fb_ops atmel_lcdfb_ops = {
+-	.owner		= THIS_MODULE,
+-	.fb_check_var	= atmel_lcdfb_check_var,
+-	.fb_set_par	= atmel_lcdfb_set_par,
+-	.fb_setcolreg	= atmel_lcdfb_setcolreg,
+-	.fb_blank	= atmel_lcdfb_blank,
+-	.fb_pan_display	= atmel_lcdfb_pan_display,
+-	.fb_fillrect	= cfb_fillrect,
+-	.fb_copyarea	= cfb_copyarea,
+-	.fb_imageblit	= cfb_imageblit,
+-};
+-
+-static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
+-{
+-	struct fb_info *info = dev_id;
+-	struct atmel_lcdfb_info *sinfo = info->par;
+-	u32 status;
+-	u32 baselayer_status;
+-
+-	if (cpu_is_at91sam9x5()) {
+-		/* Check for error status via interrupt.*/
+-		status = lcdc_readl(sinfo, ATMEL_LCDC_LCDISR);
+-		if (status & LCDC_LCDISR_FIFOERR) {
+-			dev_warn(info->device, "FIFO underflow %#x\n", status);
+-		} else if (status & LCDC_LCDISR_BASE) {
+-			/* Check base layer's overflow error. */
+-			baselayer_status = lcdc_readl(sinfo, ATMEL_LCDC_BASEISR);
+-
+-			if (baselayer_status & LCDC_BASEISR_OVR)
+-				dev_warn(info->device, "base layer overflow %#x\n",
+-							baselayer_status);
+-
+-		} else
+-			return IRQ_NONE;
+-	} else {
+-		status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
+-		if (status & ATMEL_LCDC_UFLWI) {
+-			dev_warn(info->device, "FIFO underflow %#x\n", status);
+-			/* reset DMA and FIFO to avoid screen shifting */
+-			schedule_work(&sinfo->task);
+-		}
+-		lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
+-	}
+-
+-	return IRQ_HANDLED;
+-}
+-
+-/*
+- * LCD controller task (to reset the LCD)
+- */
+-static void atmel_lcdfb_task(struct work_struct *work)
+-{
+-	struct atmel_lcdfb_info *sinfo =
+-		container_of(work, struct atmel_lcdfb_info, task);
+-
+-	atmel_lcdfb_reset(sinfo);
+-}
+-
+-static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
+-{
+-	struct fb_info *info = sinfo->info;
+-	int ret = 0;
+-
+-	info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
+-
+-	dev_info(info->device,
+-	       "%luKiB frame buffer at %08lx (mapped at %p)\n",
+-	       (unsigned long)info->fix.smem_len / 1024,
+-	       (unsigned long)info->fix.smem_start,
+-	       info->screen_base);
+-
+-	/* Allocate colormap */
+-	ret = fb_alloc_cmap(&info->cmap, 256, 0);
+-	if (ret < 0)
+-		dev_err(info->device, "Alloc color map failed\n");
+-
+-	return ret;
+-}
+-
+-static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
+-{
+-	if (sinfo->bus_clk)
+-		clk_enable(sinfo->bus_clk);
+-	clk_enable(sinfo->lcdc_clk);
+-}
+-
+-static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
+-{
+-	if (sinfo->bus_clk)
+-		clk_disable(sinfo->bus_clk);
+-	clk_disable(sinfo->lcdc_clk);
+-}
+-
+-
+-static int __init atmel_lcdfb_probe(struct platform_device *pdev)
+-{
+-	struct device *dev = &pdev->dev;
+-	struct fb_info *info;
+-	struct atmel_lcdfb_info *sinfo;
+-	struct atmel_lcdfb_info *pdata_sinfo;
+-	struct fb_videomode fbmode;
+-	struct resource *regs = NULL;
+-	struct resource *map = NULL;
+-	int ret;
+-
+-	dev_dbg(dev, "%s BEGIN\n", __func__);
+-
+-	ret = -ENOMEM;
+-	info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
+-	if (!info) {
+-		dev_err(dev, "cannot allocate memory\n");
+-		goto out;
+-	}
+-
+-	sinfo = info->par;
+-
+-	if (dev->platform_data) {
+-		pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data;
+-		sinfo->default_bpp = pdata_sinfo->default_bpp;
+-		sinfo->default_dmacon = pdata_sinfo->default_dmacon;
+-		sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2;
+-		sinfo->default_monspecs = pdata_sinfo->default_monspecs;
+-		sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control;
+-		sinfo->guard_time = pdata_sinfo->guard_time;
+-		sinfo->smem_len = pdata_sinfo->smem_len;
+-		sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight;
+-		sinfo->lcdcon_pol_negative = pdata_sinfo->lcdcon_pol_negative;
+-		sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode;
+-	} else {
+-		dev_err(dev, "cannot get default configuration\n");
+-		goto free_info;
+-	}
+-	sinfo->info = info;
+-	sinfo->pdev = pdev;
+-
+-	strcpy(info->fix.id, sinfo->pdev->name);
+-	info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
+-	info->pseudo_palette = sinfo->pseudo_palette;
+-	info->fbops = &atmel_lcdfb_ops;
+-
+-	memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
+-	info->fix = atmel_lcdfb_fix;
+-
+-	/* Enable LCDC Clocks */
+-	if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()
+-	 || cpu_is_at32ap7000()) {
+-		sinfo->bus_clk = clk_get(dev, "hck1");
+-		if (IS_ERR(sinfo->bus_clk)) {
+-			ret = PTR_ERR(sinfo->bus_clk);
+-			goto free_info;
+-		}
+-	}
+-	sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
+-	if (IS_ERR(sinfo->lcdc_clk)) {
+-		ret = PTR_ERR(sinfo->lcdc_clk);
+-		goto put_bus_clk;
+-	}
+-	atmel_lcdfb_start_clock(sinfo);
+-
+-	ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
+-			info->monspecs.modedb_len, info->monspecs.modedb,
+-			sinfo->default_bpp);
+-	if (!ret) {
+-		dev_err(dev, "no suitable video mode found\n");
+-		goto stop_clk;
+-	}
+-
+-
+-	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	if (!regs) {
+-		dev_err(dev, "resources unusable\n");
+-		ret = -ENXIO;
+-		goto stop_clk;
+-	}
+-
+-	sinfo->irq_base = platform_get_irq(pdev, 0);
+-	if (sinfo->irq_base < 0) {
+-		dev_err(dev, "unable to get irq\n");
+-		ret = sinfo->irq_base;
+-		goto stop_clk;
+-	}
+-
+-	/* Initialize video memory */
+-	map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+-	sinfo->p_dma_desc = NULL;
+-	sinfo->dma_desc_phys = 0;
+-	if (map) {
+-		/* use a pre-allocated memory buffer */
+-		info->fix.smem_start = map->start;
+-		info->fix.smem_len = map->end - map->start + 1;
+-		if (!request_mem_region(info->fix.smem_start,
+-					info->fix.smem_len, pdev->name)) {
+-			ret = -EBUSY;
+-			goto stop_clk;
+-		}
+-
+-		info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
+-		if (!info->screen_base)
+-			goto release_intmem;
+-
+-		/*
+-		 * Don't clear the framebuffer -- someone may have set
+-		 * up a splash image.
+-		 */
+-	} else {
+-		/* alocate memory buffer */
+-		ret = atmel_lcdfb_alloc_video_memory(sinfo);
+-		if (ret < 0) {
+-			dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
+-			goto stop_clk;
+-		}
+-	}
+-
+-	/* LCDC registers */
+-	info->fix.mmio_start = regs->start;
+-	info->fix.mmio_len = regs->end - regs->start + 1;
+-
+-	if (!request_mem_region(info->fix.mmio_start,
+-				info->fix.mmio_len, pdev->name)) {
+-		ret = -EBUSY;
+-		goto free_fb;
+-	}
+-
+-	sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
+-	if (!sinfo->mmio) {
+-		dev_err(dev, "cannot map LCDC registers\n");
+-		goto release_mem;
+-	}
+-
+-	/* Initialize PWM for contrast or backlight ("off") */
+-	init_contrast(sinfo);
+-
+-	/* interrupt */
+-	ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, IRQF_SHARED, pdev->name, info);
+-	if (ret) {
+-		dev_err(dev, "request_irq failed: %d\n", ret);
+-		goto unmap_mmio;
+-	}
+-
+-	/* Some operations on the LCDC might sleep and
+-	 * require a preemptible task context */
+-	INIT_WORK(&sinfo->task, atmel_lcdfb_task);
+-
+-	ret = atmel_lcdfb_init_fbinfo(sinfo);
+-	if (ret < 0) {
+-		dev_err(dev, "init fbinfo failed: %d\n", ret);
+-		goto unregister_irqs;
+-	}
+-
+-	/*
+-	 * This makes sure that our colour bitfield
+-	 * descriptors are correctly initialised.
+-	 */
+-	atmel_lcdfb_check_var(&info->var, info);
+-
+-	ret = fb_set_var(info, &info->var);
+-	if (ret) {
+-		dev_warn(dev, "unable to set display parameters\n");
+-		goto free_cmap;
+-	}
+-
+-	dev_set_drvdata(dev, info);
+-
+-	/*
+-	 * Tell the world that we're ready to go
+-	 */
+-	ret = register_framebuffer(info);
+-	if (ret < 0) {
+-		dev_err(dev, "failed to register framebuffer device: %d\n", ret);
+-		goto reset_drvdata;
+-	}
+-
+-	/* add selected videomode to modelist */
+-	fb_var_to_videomode(&fbmode, &info->var);
+-	fb_add_videomode(&fbmode, &info->modelist);
+-
+-	/* Power up the LCDC screen */
+-	if (sinfo->atmel_lcdfb_power_control)
+-		sinfo->atmel_lcdfb_power_control(1);
+-
+-	dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n",
+-		       info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
+-
+-	return 0;
+-
+-reset_drvdata:
+-	dev_set_drvdata(dev, NULL);
+-free_cmap:
+-	fb_dealloc_cmap(&info->cmap);
+-unregister_irqs:
+-	cancel_work_sync(&sinfo->task);
+-	free_irq(sinfo->irq_base, info);
+-unmap_mmio:
+-	exit_backlight(sinfo);
+-	iounmap(sinfo->mmio);
+-release_mem:
+-	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
+-free_fb:
+-	if (map)
+-		iounmap(info->screen_base);
+-	else
+-		atmel_lcdfb_free_video_memory(sinfo);
+-
+-release_intmem:
+-	if (map)
+-		release_mem_region(info->fix.smem_start, info->fix.smem_len);
+-stop_clk:
+-	atmel_lcdfb_stop_clock(sinfo);
+-	clk_put(sinfo->lcdc_clk);
+-put_bus_clk:
+-	if (sinfo->bus_clk)
+-		clk_put(sinfo->bus_clk);
+-free_info:
+-	framebuffer_release(info);
+-out:
+-	dev_dbg(dev, "%s FAILED\n", __func__);
+-	return ret;
+-}
+-
+-static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
+-{
+-	struct device *dev = &pdev->dev;
+-	struct fb_info *info = dev_get_drvdata(dev);
+-	struct atmel_lcdfb_info *sinfo;
+-
+-	if (!info || !info->par)
+-		return 0;
+-	sinfo = info->par;
+-
+-	cancel_work_sync(&sinfo->task);
+-	exit_backlight(sinfo);
+-	if (sinfo->atmel_lcdfb_power_control)
+-		sinfo->atmel_lcdfb_power_control(0);
+-	unregister_framebuffer(info);
+-	atmel_lcdfb_stop_clock(sinfo);
+-	clk_put(sinfo->lcdc_clk);
+-	if (sinfo->bus_clk)
+-		clk_put(sinfo->bus_clk);
+-	fb_dealloc_cmap(&info->cmap);
+-	free_irq(sinfo->irq_base, info);
+-	iounmap(sinfo->mmio);
+-	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
+-	if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
+-		iounmap(info->screen_base);
+-		release_mem_region(info->fix.smem_start, info->fix.smem_len);
+-	} else {
+-		atmel_lcdfb_free_video_memory(sinfo);
+-	}
+-
+-	dev_set_drvdata(dev, NULL);
+-	framebuffer_release(info);
+-
+-	return 0;
+-}
+ 
+ #ifdef CONFIG_PM
+ 
+@@ -1400,16 +28,10 @@ static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
+ 	 * We don't want to handle interrupts while the clock is
+ 	 * stopped. It may take forever.
+ 	 */
+-	if (cpu_is_at91sam9x5()) {
+-		/* Disable all interrupts */
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDIDR, ~0UL);
+-		lcdc_writel(sinfo, ATMEL_LCDC_BASEIDR, ~0UL);
+-	} else {
+-		lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
++	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
+ 
+-		sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
+-		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
+-	}
++	sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
++	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
+ 
+ 	if (sinfo->atmel_lcdfb_power_control)
+ 		sinfo->atmel_lcdfb_power_control(0);
+@@ -1430,17 +52,11 @@ static int atmel_lcdfb_resume(struct platform_device *pdev)
+ 	if (sinfo->atmel_lcdfb_power_control)
+ 		sinfo->atmel_lcdfb_power_control(1);
+ 
+-	if (cpu_is_at91sam9x5()) {
+-		/* Enable fifo error & BASE LAYER overflow interrupts */
+-		lcdc_writel(sinfo, ATMEL_LCDC_BASEIER, LCDC_BASEIER_OVR);
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDIER, LCDC_LCDIER_FIFOERRIE | LCDC_LCDIER_BASEIE);
+-	} else {
+-		lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
++	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
+ 
+-		/* Enable FIFO & DMA errors */
+-		lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI
+-				| ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
+-	}
++	/* Enable FIFO & DMA errors */
++	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI
++			| ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
+ 
+ 	return 0;
+ }
+@@ -1450,6 +66,15 @@ static int atmel_lcdfb_resume(struct platform_device *pdev)
+ #define atmel_lcdfb_resume	NULL
+ #endif
+ 
++static int __init atmel_lcdfb_probe(struct platform_device *pdev)
++{
++	return __atmel_lcdfb_probe(pdev);
++}
++static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
++{
++	return __atmel_lcdfb_remove(pdev);
++}
++
+ static struct platform_driver atmel_lcdfb_driver = {
+ 	.remove		= __exit_p(atmel_lcdfb_remove),
+ 	.suspend	= atmel_lcdfb_suspend,
+@@ -1465,13 +90,12 @@ static int __init atmel_lcdfb_init(void)
+ {
+ 	return platform_driver_probe(&atmel_lcdfb_driver, atmel_lcdfb_probe);
+ }
++module_init(atmel_lcdfb_init);
+ 
+ static void __exit atmel_lcdfb_exit(void)
+ {
+ 	platform_driver_unregister(&atmel_lcdfb_driver);
+ }
+-
+-module_init(atmel_lcdfb_init);
+ module_exit(atmel_lcdfb_exit);
+ 
+ MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver");
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+new file mode 100644
+index 0000000..54bdbcb
+--- /dev/null
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -0,0 +1,1077 @@
++/*
++ *  Driver for AT91/AT32 LCD Controller
++ *
++ *  Copyright (C) 2007 Atmel Corporation
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file COPYING in the main directory of this archive for
++ * more details.
++ */
++
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/backlight.h>
++#include <linux/gfp.h>
++
++#include <mach/board.h>
++#include <mach/cpu.h>
++#include <mach/gpio.h>
++
++#include <video/atmel_lcdc.h>
++
++/* configurable parameters */
++#define ATMEL_LCDC_CVAL_DEFAULT		0xc8
++#define ATMEL_LCDC_DMA_BURST_LEN	8	/* words */
++#define ATMEL_LCDC_FIFO_SIZE		512	/* words */
++
++#if defined(CONFIG_ARCH_AT91)
++#define	ATMEL_LCDFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
++					 | FBINFO_PARTIAL_PAN_OK \
++					 | FBINFO_HWACCEL_YPAN)
++
++static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
++					struct fb_var_screeninfo *var)
++{
++
++}
++#elif defined(CONFIG_AVR32)
++#define	ATMEL_LCDFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
++					| FBINFO_PARTIAL_PAN_OK \
++					| FBINFO_HWACCEL_XPAN \
++					| FBINFO_HWACCEL_YPAN)
++
++static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
++				     struct fb_var_screeninfo *var)
++{
++	u32 dma2dcfg;
++	u32 pixeloff;
++
++	pixeloff = (var->xoffset * var->bits_per_pixel) & 0x1f;
++
++	dma2dcfg = ((var->xres_virtual - var->xres) * var->bits_per_pixel) / 8;
++	dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
++	lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
++
++	/* Update configuration */
++	lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
++		    lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
++		    | ATMEL_LCDC_DMAUPDT);
++}
++#endif
++
++static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
++		| ATMEL_LCDC_POL_POSITIVE
++		| ATMEL_LCDC_ENA_PWMENABLE;
++
++#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
++
++/* some bl->props field just changed */
++static int atmel_bl_update_status(struct backlight_device *bl)
++{
++	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
++	int			power = sinfo->bl_power;
++	int			brightness = bl->props.brightness;
++
++	/* REVISIT there may be a meaningful difference between
++	 * fb_blank and power ... there seem to be some cases
++	 * this doesn't handle correctly.
++	 */
++	if (bl->props.fb_blank != sinfo->bl_power)
++		power = bl->props.fb_blank;
++	else if (bl->props.power != sinfo->bl_power)
++		power = bl->props.power;
++
++	if (brightness < 0 && power == FB_BLANK_UNBLANK)
++		brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
++	else if (power != FB_BLANK_UNBLANK)
++		brightness = 0;
++
++	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
++	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
++			brightness ? contrast_ctr : 0);
++
++	bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
++
++	return 0;
++}
++
++static int atmel_bl_get_brightness(struct backlight_device *bl)
++{
++	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
++
++	return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
++}
++
++static const struct backlight_ops atmel_lcdc_bl_ops = {
++	.update_status = atmel_bl_update_status,
++	.get_brightness = atmel_bl_get_brightness,
++};
++
++static void init_backlight(struct atmel_lcdfb_info *sinfo)
++{
++	struct backlight_properties props;
++	struct backlight_device	*bl;
++
++	sinfo->bl_power = FB_BLANK_UNBLANK;
++
++	if (sinfo->backlight)
++		return;
++
++	memset(&props, 0, sizeof(struct backlight_properties));
++	props.type = BACKLIGHT_RAW;
++	props.max_brightness = 0xff;
++	bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo,
++				       &atmel_lcdc_bl_ops, &props);
++	if (IS_ERR(bl)) {
++		dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
++				PTR_ERR(bl));
++		return;
++	}
++	sinfo->backlight = bl;
++
++	bl->props.power = FB_BLANK_UNBLANK;
++	bl->props.fb_blank = FB_BLANK_UNBLANK;
++	bl->props.brightness = atmel_bl_get_brightness(bl);
++}
++
++static void exit_backlight(struct atmel_lcdfb_info *sinfo)
++{
++	if (sinfo->backlight)
++		backlight_device_unregister(sinfo->backlight);
++}
++
++#else
++
++static void init_backlight(struct atmel_lcdfb_info *sinfo)
++{
++	dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
++}
++
++static void exit_backlight(struct atmel_lcdfb_info *sinfo)
++{
++}
++
++#endif
++
++static void init_contrast(struct atmel_lcdfb_info *sinfo)
++{
++	/* contrast pwm can be 'inverted' */
++	if (sinfo->lcdcon_pol_negative)
++			contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
++
++	/* have some default contrast/backlight settings */
++	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
++	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
++
++	if (sinfo->lcdcon_is_backlight)
++		init_backlight(sinfo);
++}
++
++
++static struct fb_fix_screeninfo atmel_lcdfb_fix = {
++	.type		= FB_TYPE_PACKED_PIXELS,
++	.visual		= FB_VISUAL_TRUECOLOR,
++	.xpanstep	= 0,
++	.ypanstep	= 1,
++	.ywrapstep	= 0,
++	.accel		= FB_ACCEL_NONE,
++};
++
++static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
++{
++	unsigned long value;
++
++	if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
++		|| cpu_is_at32ap7000()))
++		return xres;
++
++	value = xres;
++	if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
++		/* STN display */
++		if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
++			value *= 3;
++		}
++		if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
++		   || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
++		      && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
++			value = DIV_ROUND_UP(value, 4);
++		else
++			value = DIV_ROUND_UP(value, 8);
++	}
++
++	return value;
++}
++
++static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
++{
++	/* Turn off the LCD controller and the DMA controller */
++	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
++			sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
++
++	/* Wait for the LCDC core to become idle */
++	while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
++		msleep(10);
++
++	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
++}
++
++void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
++{
++	atmel_lcdfb_stop_nowait(sinfo);
++
++	/* Wait for DMA engine to become idle... */
++	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
++		msleep(10);
++}
++EXPORT_SYMBOL_GPL(atmel_lcdfb_stop);
++
++void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
++{
++	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
++	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
++		(sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
++		| ATMEL_LCDC_PWR);
++}
++EXPORT_SYMBOL_GPL(atmel_lcdfb_start);
++
++static void atmel_lcdfb_update_dma(struct fb_info *info,
++			       struct fb_var_screeninfo *var)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++	struct fb_fix_screeninfo *fix = &info->fix;
++	unsigned long dma_addr;
++
++	dma_addr = (fix->smem_start + var->yoffset * fix->line_length
++		    + var->xoffset * var->bits_per_pixel / 8);
++
++	dma_addr &= ~3UL;
++
++	/* Set framebuffer DMA base address and pixel offset */
++	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
++
++	atmel_lcdfb_update_dma2d(sinfo, var);
++}
++
++static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
++{
++	struct fb_info *info = sinfo->info;
++
++	dma_free_writecombine(info->device, info->fix.smem_len,
++				info->screen_base, info->fix.smem_start);
++}
++
++/**
++ *	atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
++ *	@sinfo: the frame buffer to allocate memory for
++ * 	
++ * 	This function is called only from the atmel_lcdfb_probe()
++ * 	so no locking by fb_info->mm_lock around smem_len setting is needed.
++ */
++static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
++{
++	struct fb_info *info = sinfo->info;
++	struct fb_var_screeninfo *var = &info->var;
++	unsigned int smem_len;
++
++	smem_len = (var->xres_virtual * var->yres_virtual
++		    * ((var->bits_per_pixel + 7) / 8));
++	info->fix.smem_len = max(smem_len, sinfo->smem_len);
++
++	info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len,
++					(dma_addr_t *)&info->fix.smem_start, GFP_KERNEL);
++
++	if (!info->screen_base) {
++		return -ENOMEM;
++	}
++
++	memset(info->screen_base, 0, info->fix.smem_len);
++
++	return 0;
++}
++
++static const struct fb_videomode *atmel_lcdfb_choose_mode(struct fb_var_screeninfo *var,
++						     struct fb_info *info)
++{
++	struct fb_videomode varfbmode;
++	const struct fb_videomode *fbmode = NULL;
++
++	fb_var_to_videomode(&varfbmode, var);
++	fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist);
++	if (fbmode)
++		fb_videomode_to_var(var, fbmode);
++	return fbmode;
++}
++
++
++/**
++ *      atmel_lcdfb_check_var - Validates a var passed in.
++ *      @var: frame buffer variable screen structure
++ *      @info: frame buffer structure that represents a single frame buffer
++ *
++ *	Checks to see if the hardware supports the state requested by
++ *	var passed in. This function does not alter the hardware
++ *	state!!!  This means the data stored in struct fb_info and
++ *	struct atmel_lcdfb_info do not change. This includes the var
++ *	inside of struct fb_info.  Do NOT change these. This function
++ *	can be called on its own if we intent to only test a mode and
++ *	not actually set it. The stuff in modedb.c is a example of
++ *	this. If the var passed in is slightly off by what the
++ *	hardware can support then we alter the var PASSED in to what
++ *	we can do. If the hardware doesn't support mode change a
++ *	-EINVAL will be returned by the upper layers. You don't need
++ *	to implement this function then. If you hardware doesn't
++ *	support changing the resolution then this function is not
++ *	needed. In this case the driver would just provide a var that
++ *	represents the static state the screen is in.
++ *
++ *	Returns negative errno on error, or zero on success.
++ */
++static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
++			     struct fb_info *info)
++{
++	struct device *dev = info->device;
++	struct atmel_lcdfb_info *sinfo = info->par;
++	unsigned long clk_value_khz;
++
++	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
++
++	dev_dbg(dev, "%s:\n", __func__);
++
++	if (!(var->pixclock && var->bits_per_pixel)) {
++		/* choose a suitable mode if possible */
++		if (!atmel_lcdfb_choose_mode(var, info)) {
++			dev_err(dev, "needed value not specified\n");
++			return -EINVAL;
++		}
++	}
++
++	dev_dbg(dev, "  resolution: %ux%u\n", var->xres, var->yres);
++	dev_dbg(dev, "  pixclk:     %lu KHz\n", PICOS2KHZ(var->pixclock));
++	dev_dbg(dev, "  bpp:        %u\n", var->bits_per_pixel);
++	dev_dbg(dev, "  clk:        %lu KHz\n", clk_value_khz);
++
++	if (PICOS2KHZ(var->pixclock) > clk_value_khz) {
++		dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
++		return -EINVAL;
++	}
++
++	/* Do not allow to have real resoulution larger than virtual */
++	if (var->xres > var->xres_virtual)
++		var->xres_virtual = var->xres;
++
++	if (var->yres > var->yres_virtual)
++		var->yres_virtual = var->yres;
++
++	/* Force same alignment for each line */
++	var->xres = (var->xres + 3) & ~3UL;
++	var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
++
++	var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
++	var->transp.msb_right = 0;
++	var->transp.offset = var->transp.length = 0;
++	var->xoffset = var->yoffset = 0;
++
++	if (info->fix.smem_len) {
++		unsigned int smem_len = (var->xres_virtual * var->yres_virtual
++					 * ((var->bits_per_pixel + 7) / 8));
++		if (smem_len > info->fix.smem_len)
++			return -EINVAL;
++	}
++
++	/* Saturate vertical and horizontal timings at maximum values */
++	var->vsync_len = min_t(u32, var->vsync_len,
++			(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
++	var->upper_margin = min_t(u32, var->upper_margin,
++			ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
++	var->lower_margin = min_t(u32, var->lower_margin,
++			ATMEL_LCDC_VFP);
++	var->right_margin = min_t(u32, var->right_margin,
++			(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
++	var->hsync_len = min_t(u32, var->hsync_len,
++			(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
++	var->left_margin = min_t(u32, var->left_margin,
++			ATMEL_LCDC_HBP + 1);
++
++	/* Some parameters can't be zero */
++	var->vsync_len = max_t(u32, var->vsync_len, 1);
++	var->right_margin = max_t(u32, var->right_margin, 1);
++	var->hsync_len = max_t(u32, var->hsync_len, 1);
++	var->left_margin = max_t(u32, var->left_margin, 1);
++
++	switch (var->bits_per_pixel) {
++	case 1:
++	case 2:
++	case 4:
++	case 8:
++		var->red.offset = var->green.offset = var->blue.offset = 0;
++		var->red.length = var->green.length = var->blue.length
++			= var->bits_per_pixel;
++		break;
++	case 15:
++	case 16:
++		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
++			/* RGB:565 mode */
++			var->red.offset = 11;
++			var->blue.offset = 0;
++			var->green.length = 6;
++		} else if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB555) {
++			var->red.offset = 10;
++			var->blue.offset = 0;
++			var->green.length = 5;
++		} else {
++			/* BGR:555 mode */
++			var->red.offset = 0;
++			var->blue.offset = 10;
++			var->green.length = 5;
++		}
++		var->green.offset = 5;
++		var->red.length = var->blue.length = 5;
++		break;
++	case 32:
++		var->transp.offset = 24;
++		var->transp.length = 8;
++		/* fall through */
++	case 24:
++		if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
++			/* RGB:888 mode */
++			var->red.offset = 16;
++			var->blue.offset = 0;
++		} else {
++			/* BGR:888 mode */
++			var->red.offset = 0;
++			var->blue.offset = 16;
++		}
++		var->green.offset = 8;
++		var->red.length = var->green.length = var->blue.length = 8;
++		break;
++	default:
++		dev_err(dev, "color depth %d not supported\n",
++					var->bits_per_pixel);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++/*
++ * LCD reset sequence
++ */
++static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
++{
++	might_sleep();
++
++	atmel_lcdfb_stop(sinfo);
++	atmel_lcdfb_start(sinfo);
++}
++
++/**
++ *      atmel_lcdfb_set_par - Alters the hardware state.
++ *      @info: frame buffer structure that represents a single frame buffer
++ *
++ *	Using the fb_var_screeninfo in fb_info we set the resolution
++ *	of the this particular framebuffer. This function alters the
++ *	par AND the fb_fix_screeninfo stored in fb_info. It doesn't
++ *	not alter var in fb_info since we are using that data. This
++ *	means we depend on the data in var inside fb_info to be
++ *	supported by the hardware.  atmel_lcdfb_check_var is always called
++ *	before atmel_lcdfb_set_par to ensure this.  Again if you can't
++ *	change the resolution you don't need this function.
++ *
++ */
++static int atmel_lcdfb_set_par(struct fb_info *info)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++	unsigned long hozval_linesz;
++	unsigned long value;
++	unsigned long clk_value_khz;
++	unsigned long bits_per_line;
++	unsigned long pix_factor = 2;
++
++	might_sleep();
++
++	dev_dbg(info->device, "%s:\n", __func__);
++	dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
++		 info->var.xres, info->var.yres,
++		 info->var.xres_virtual, info->var.yres_virtual);
++
++	atmel_lcdfb_stop_nowait(sinfo);
++
++	if (info->var.bits_per_pixel == 1)
++		info->fix.visual = FB_VISUAL_MONO01;
++	else if (info->var.bits_per_pixel <= 8)
++		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
++	else
++		info->fix.visual = FB_VISUAL_TRUECOLOR;
++
++	bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
++	info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
++
++	/* Re-initialize the DMA engine... */
++	dev_dbg(info->device, "  * update DMA engine\n");
++	atmel_lcdfb_update_dma(info, &info->var);
++
++	/* ...set frame size and burst length = 8 words (?) */
++	value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
++	value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
++	lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
++
++	/* Now, the LCDC core... */
++
++	/* Set pixel clock */
++	if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
++		pix_factor = 1;
++
++	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
++
++	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
++
++	if (value < pix_factor) {
++		dev_notice(info->device, "Bypassing pixel clock divider\n");
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
++	} else {
++		value = (value / pix_factor) - 1;
++		dev_dbg(info->device, "  * programming CLKVAL = 0x%08lx\n",
++				value);
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
++				value << ATMEL_LCDC_CLKVAL_OFFSET);
++		info->var.pixclock =
++			KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
++		dev_dbg(info->device, "  updated pixclk:     %lu KHz\n",
++					PICOS2KHZ(info->var.pixclock));
++	}
++
++
++	/* Initialize control register 2 */
++	value = sinfo->default_lcdcon2;
++
++	if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
++		value |= ATMEL_LCDC_INVLINE_INVERTED;
++	if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
++		value |= ATMEL_LCDC_INVFRAME_INVERTED;
++
++	switch (info->var.bits_per_pixel) {
++		case 1:	value |= ATMEL_LCDC_PIXELSIZE_1; break;
++		case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
++		case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
++		case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
++		case 15: /* fall through */
++		case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
++		case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
++		case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
++		default: BUG(); break;
++	}
++	dev_dbg(info->device, "  * LCDCON2 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
++
++	/* Vertical timing */
++	value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
++	value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
++	value |= info->var.lower_margin;
++	dev_dbg(info->device, "  * LCDTIM1 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
++
++	/* Horizontal timing */
++	value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
++	value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
++	value |= (info->var.left_margin - 1);
++	dev_dbg(info->device, "  * LCDTIM2 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
++
++	/* Horizontal value (aka line size) */
++	hozval_linesz = compute_hozval(info->var.xres,
++					lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
++
++	/* Display size */
++	value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
++	value |= info->var.yres - 1;
++	dev_dbg(info->device, "  * LCDFRMCFG = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
++
++	/* FIFO Threshold: Use formula from data sheet */
++	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
++	lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
++
++	/* Toggle LCD_MODE every frame */
++	lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
++
++	/* Disable all interrupts */
++	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
++	/* Enable FIFO & DMA errors */
++	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
++
++	/* ...wait for DMA engine to become idle... */
++	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
++		msleep(10);
++
++	atmel_lcdfb_start(sinfo);
++
++	dev_dbg(info->device, "  * DONE\n");
++
++	return 0;
++}
++
++static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
++{
++	chan &= 0xffff;
++	chan >>= 16 - bf->length;
++	return chan << bf->offset;
++}
++
++/**
++ *  	atmel_lcdfb_setcolreg - Optional function. Sets a color register.
++ *      @regno: Which register in the CLUT we are programming
++ *      @red: The red value which can be up to 16 bits wide
++ *	@green: The green value which can be up to 16 bits wide
++ *	@blue:  The blue value which can be up to 16 bits wide.
++ *	@transp: If supported the alpha value which can be up to 16 bits wide.
++ *      @info: frame buffer info structure
++ *
++ *  	Set a single color register. The values supplied have a 16 bit
++ *  	magnitude which needs to be scaled in this function for the hardware.
++ *	Things to take into consideration are how many color registers, if
++ *	any, are supported with the current color visual. With truecolor mode
++ *	no color palettes are supported. Here a pseudo palette is created
++ *	which we store the value in pseudo_palette in struct fb_info. For
++ *	pseudocolor mode we have a limited color palette. To deal with this
++ *	we can program what color is displayed for a particular pixel value.
++ *	DirectColor is similar in that we can program each color field. If
++ *	we have a static colormap we don't need to implement this function.
++ *
++ *	Returns negative errno on error, or zero on success. In an
++ *	ideal world, this would have been the case, but as it turns
++ *	out, the other drivers return 1 on failure, so that's what
++ *	we're going to do.
++ */
++static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
++			     unsigned int green, unsigned int blue,
++			     unsigned int transp, struct fb_info *info)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++	unsigned int val;
++	u32 *pal;
++	int ret = 1;
++
++	if (info->var.grayscale)
++		red = green = blue = (19595 * red + 38470 * green
++				      + 7471 * blue) >> 16;
++
++	switch (info->fix.visual) {
++	case FB_VISUAL_TRUECOLOR:
++		if (regno < 16) {
++			pal = info->pseudo_palette;
++
++			val  = chan_to_field(red, &info->var.red);
++			val |= chan_to_field(green, &info->var.green);
++			val |= chan_to_field(blue, &info->var.blue);
++
++			pal[regno] = val;
++			ret = 0;
++		}
++		break;
++
++	case FB_VISUAL_PSEUDOCOLOR:
++		if (regno < 256) {
++			val  = ((red   >> 11) & 0x001f);
++			val |= ((green >>  6) & 0x03e0);
++			val |= ((blue  >>  1) & 0x7c00);
++
++			/*
++			 * TODO: intensity bit. Maybe something like
++			 *   ~(red[10] ^ green[10] ^ blue[10]) & 1
++			 */
++
++			lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
++			ret = 0;
++		}
++		break;
++
++	case FB_VISUAL_MONO01:
++		if (regno < 2) {
++			val = (regno == 0) ? 0x00 : 0x1F;
++			lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
++			ret = 0;
++		}
++		break;
++
++	}
++
++	return ret;
++}
++
++static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
++			       struct fb_info *info)
++{
++	dev_dbg(info->device, "%s\n", __func__);
++
++	atmel_lcdfb_update_dma(info, var);
++
++	return 0;
++}
++
++static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++
++	switch (blank_mode) {
++	case FB_BLANK_UNBLANK:
++	case FB_BLANK_NORMAL:
++		atmel_lcdfb_start(sinfo);
++		break;
++	case FB_BLANK_VSYNC_SUSPEND:
++	case FB_BLANK_HSYNC_SUSPEND:
++		break;
++	case FB_BLANK_POWERDOWN:
++		atmel_lcdfb_stop(sinfo);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	/* let fbcon do a soft blank for us */
++	return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
++}
++
++static struct fb_ops atmel_lcdfb_ops = {
++	.owner		= THIS_MODULE,
++	.fb_check_var	= atmel_lcdfb_check_var,
++	.fb_set_par	= atmel_lcdfb_set_par,
++	.fb_setcolreg	= atmel_lcdfb_setcolreg,
++	.fb_blank	= atmel_lcdfb_blank,
++	.fb_pan_display	= atmel_lcdfb_pan_display,
++	.fb_fillrect	= cfb_fillrect,
++	.fb_copyarea	= cfb_copyarea,
++	.fb_imageblit	= cfb_imageblit,
++};
++
++static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
++{
++	struct fb_info *info = dev_id;
++	struct atmel_lcdfb_info *sinfo = info->par;
++	u32 status;
++
++	status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
++	if (status & ATMEL_LCDC_UFLWI) {
++		dev_warn(info->device, "FIFO underflow %#x\n", status);
++		/* reset DMA and FIFO to avoid screen shifting */
++		schedule_work(&sinfo->task);
++	}
++	lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
++	return IRQ_HANDLED;
++}
++
++/*
++ * LCD controller task (to reset the LCD)
++ */
++static void atmel_lcdfb_task(struct work_struct *work)
++{
++	struct atmel_lcdfb_info *sinfo =
++		container_of(work, struct atmel_lcdfb_info, task);
++
++	atmel_lcdfb_reset(sinfo);
++}
++
++static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
++{
++	struct fb_info *info = sinfo->info;
++	int ret = 0;
++
++	info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
++
++	dev_info(info->device,
++	       "%luKiB frame buffer at %08lx (mapped at %p)\n",
++	       (unsigned long)info->fix.smem_len / 1024,
++	       (unsigned long)info->fix.smem_start,
++	       info->screen_base);
++
++	/* Allocate colormap */
++	ret = fb_alloc_cmap(&info->cmap, 256, 0);
++	if (ret < 0)
++		dev_err(info->device, "Alloc color map failed\n");
++
++	return ret;
++}
++
++void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
++{
++	if (sinfo->bus_clk)
++		clk_enable(sinfo->bus_clk);
++	clk_enable(sinfo->lcdc_clk);
++}
++EXPORT_SYMBOL_GPL(atmel_lcdfb_start_clock);
++
++void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
++{
++	if (sinfo->bus_clk)
++		clk_disable(sinfo->bus_clk);
++	clk_disable(sinfo->lcdc_clk);
++}
++EXPORT_SYMBOL_GPL(atmel_lcdfb_stop_clock);
++
++
++int __atmel_lcdfb_probe(struct platform_device *pdev,
++			struct atmel_lcdfb_devdata *dev_data)
++{
++	struct device *dev = &pdev->dev;
++	struct fb_info *info;
++	struct atmel_lcdfb_info *sinfo;
++	struct atmel_lcdfb_info *pdata_sinfo;
++	struct fb_videomode fbmode;
++	struct resource *regs = NULL;
++	struct resource *map = NULL;
++	int ret;
++
++	dev_dbg(dev, "%s BEGIN\n", __func__);
++
++	ret = -ENOMEM;
++	info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
++	if (!info) {
++		dev_err(dev, "cannot allocate memory\n");
++		goto out;
++	}
++
++	sinfo = info->par;
++
++	if (dev->platform_data) {
++		pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data;
++		sinfo->default_bpp = pdata_sinfo->default_bpp;
++		sinfo->default_dmacon = pdata_sinfo->default_dmacon;
++		sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2;
++		sinfo->default_monspecs = pdata_sinfo->default_monspecs;
++		sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control;
++		sinfo->guard_time = pdata_sinfo->guard_time;
++		sinfo->smem_len = pdata_sinfo->smem_len;
++		sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight;
++		sinfo->lcdcon_pol_negative = pdata_sinfo->lcdcon_pol_negative;
++		sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode;
++	} else {
++		dev_err(dev, "cannot get default configuration\n");
++		goto free_info;
++	}
++	sinfo->info = info;
++	sinfo->pdev = pdev;
++
++	strcpy(info->fix.id, sinfo->pdev->name);
++	info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
++	info->pseudo_palette = sinfo->pseudo_palette;
++	info->fbops = &atmel_lcdfb_ops;
++
++	memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
++	info->fix = atmel_lcdfb_fix;
++
++	/* Enable LCDC Clocks */
++	if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()
++	 || cpu_is_at32ap7000()) {
++		sinfo->bus_clk = clk_get(dev, "hck1");
++		if (IS_ERR(sinfo->bus_clk)) {
++			ret = PTR_ERR(sinfo->bus_clk);
++			goto free_info;
++		}
++	}
++	sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
++	if (IS_ERR(sinfo->lcdc_clk)) {
++		ret = PTR_ERR(sinfo->lcdc_clk);
++		goto put_bus_clk;
++	}
++	atmel_lcdfb_start_clock(sinfo);
++
++	ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
++			info->monspecs.modedb_len, info->monspecs.modedb,
++			sinfo->default_bpp);
++	if (!ret) {
++		dev_err(dev, "no suitable video mode found\n");
++		goto stop_clk;
++	}
++
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!regs) {
++		dev_err(dev, "resources unusable\n");
++		ret = -ENXIO;
++		goto stop_clk;
++	}
++
++	sinfo->irq_base = platform_get_irq(pdev, 0);
++	if (sinfo->irq_base < 0) {
++		dev_err(dev, "unable to get irq\n");
++		ret = sinfo->irq_base;
++		goto stop_clk;
++	}
++
++	/* Initialize video memory */
++	map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	if (map) {
++		/* use a pre-allocated memory buffer */
++		info->fix.smem_start = map->start;
++		info->fix.smem_len = map->end - map->start + 1;
++		if (!request_mem_region(info->fix.smem_start,
++					info->fix.smem_len, pdev->name)) {
++			ret = -EBUSY;
++			goto stop_clk;
++		}
++
++		info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
++		if (!info->screen_base)
++			goto release_intmem;
++
++		/*
++		 * Don't clear the framebuffer -- someone may have set
++		 * up a splash image.
++		 */
++	} else {
++		/* alocate memory buffer */
++		ret = atmel_lcdfb_alloc_video_memory(sinfo);
++		if (ret < 0) {
++			dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
++			goto stop_clk;
++		}
++	}
++
++	/* LCDC registers */
++	info->fix.mmio_start = regs->start;
++	info->fix.mmio_len = regs->end - regs->start + 1;
++
++	if (!request_mem_region(info->fix.mmio_start,
++				info->fix.mmio_len, pdev->name)) {
++		ret = -EBUSY;
++		goto free_fb;
++	}
++
++	sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
++	if (!sinfo->mmio) {
++		dev_err(dev, "cannot map LCDC registers\n");
++		goto release_mem;
++	}
++
++	/* Initialize PWM for contrast or backlight ("off") */
++	init_contrast(sinfo);
++
++	/* interrupt */
++	ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
++	if (ret) {
++		dev_err(dev, "request_irq failed: %d\n", ret);
++		goto unmap_mmio;
++	}
++
++	/* Some operations on the LCDC might sleep and
++	 * require a preemptible task context */
++	INIT_WORK(&sinfo->task, atmel_lcdfb_task);
++
++	ret = atmel_lcdfb_init_fbinfo(sinfo);
++	if (ret < 0) {
++		dev_err(dev, "init fbinfo failed: %d\n", ret);
++		goto unregister_irqs;
++	}
++
++	/*
++	 * This makes sure that our colour bitfield
++	 * descriptors are correctly initialised.
++	 */
++	atmel_lcdfb_check_var(&info->var, info);
++
++	ret = fb_set_var(info, &info->var);
++	if (ret) {
++		dev_warn(dev, "unable to set display parameters\n");
++		goto free_cmap;
++	}
++
++	dev_set_drvdata(dev, info);
++
++	/*
++	 * Tell the world that we're ready to go
++	 */
++	ret = register_framebuffer(info);
++	if (ret < 0) {
++		dev_err(dev, "failed to register framebuffer device: %d\n", ret);
++		goto reset_drvdata;
++	}
++
++	/* add selected videomode to modelist */
++	fb_var_to_videomode(&fbmode, &info->var);
++	fb_add_videomode(&fbmode, &info->modelist);
++
++	/* Power up the LCDC screen */
++	if (sinfo->atmel_lcdfb_power_control)
++		sinfo->atmel_lcdfb_power_control(1);
++
++	dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n",
++		       info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
++
++	return 0;
++
++reset_drvdata:
++	dev_set_drvdata(dev, NULL);
++free_cmap:
++	fb_dealloc_cmap(&info->cmap);
++unregister_irqs:
++	cancel_work_sync(&sinfo->task);
++	free_irq(sinfo->irq_base, info);
++unmap_mmio:
++	exit_backlight(sinfo);
++	iounmap(sinfo->mmio);
++release_mem:
++ 	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
++free_fb:
++	if (map)
++		iounmap(info->screen_base);
++	else
++		atmel_lcdfb_free_video_memory(sinfo);
++
++release_intmem:
++	if (map)
++		release_mem_region(info->fix.smem_start, info->fix.smem_len);
++stop_clk:
++	atmel_lcdfb_stop_clock(sinfo);
++	clk_put(sinfo->lcdc_clk);
++put_bus_clk:
++	if (sinfo->bus_clk)
++		clk_put(sinfo->bus_clk);
++free_info:
++	framebuffer_release(info);
++out:
++	dev_dbg(dev, "%s FAILED\n", __func__);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(__atmel_lcdfb_probe);
++
++int __atmel_lcdfb_remove(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct fb_info *info = dev_get_drvdata(dev);
++	struct atmel_lcdfb_info *sinfo;
++
++	if (!info || !info->par)
++		return 0;
++	sinfo = info->par;
++
++	cancel_work_sync(&sinfo->task);
++	exit_backlight(sinfo);
++	if (sinfo->atmel_lcdfb_power_control)
++		sinfo->atmel_lcdfb_power_control(0);
++	unregister_framebuffer(info);
++	atmel_lcdfb_stop_clock(sinfo);
++	clk_put(sinfo->lcdc_clk);
++	if (sinfo->bus_clk)
++		clk_put(sinfo->bus_clk);
++	fb_dealloc_cmap(&info->cmap);
++	free_irq(sinfo->irq_base, info);
++	iounmap(sinfo->mmio);
++ 	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
++	if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
++		iounmap(info->screen_base);
++		release_mem_region(info->fix.smem_start, info->fix.smem_len);
++	} else {
++		atmel_lcdfb_free_video_memory(sinfo);
++	}
++
++	dev_set_drvdata(dev, NULL);
++	framebuffer_release(info);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(__atmel_lcdfb_remove);
+diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
+index 5183ab7..4fa084b 100644
+--- a/include/video/atmel_lcdc.h
++++ b/include/video/atmel_lcdc.h
+@@ -32,6 +32,13 @@
+ #define ATMEL_LCDC_WIRING_RGB	1
+ #define ATMEL_LCDC_WIRING_RGB555	2
+ 
++extern void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo);
++extern void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo);
++extern void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo);
++extern void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo);
++
++extern int __atmel_lcdfb_probe(struct platform_device *pdev);
++extern int __atmel_lcdfb_remove(struct platform_device *pdev);
+ 
+  /* LCD Controller info data structure, stored in device platform_data */
+ struct atmel_lcdfb_info {
+@@ -47,9 +54,6 @@ struct atmel_lcdfb_info {
+ 	struct clk		*bus_clk;
+ 	struct clk		*lcdc_clk;
+ 
+-	struct lcd_dma_desc	*p_dma_desc;
+-	dma_addr_t		dma_desc_phys;
+-
+ #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
+ 	struct backlight_device	*backlight;
+ 	u8			bl_power;
+@@ -68,11 +72,8 @@ struct atmel_lcdfb_info {
+ 	u32			pseudo_palette[16];
+ };
+ 
+-struct lcd_dma_desc {
+-	u32	address;
+-	u32	control;
+-	u32	next;
+-};
++#define lcdc_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
++#define lcdc_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
+ 
+ #define ATMEL_LCDC_DMABADDR1	0x00
+ #define ATMEL_LCDC_DMABADDR2	0x04
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0074-video-atmelfb-refactor-core-setup.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0074-video-atmelfb-refactor-core-setup.patch
new file mode 100644
index 0000000..045683f
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0074-video-atmelfb-refactor-core-setup.patch
@@ -0,0 +1,403 @@
+From 9bcc93b07d7b2465b9cce20bcd86bef247a880e8 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Thu, 19 May 2011 14:29:36 +0200
+Subject: [PATCH 074/107] video: atmelfb: refactor core setup
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/atmel_lcdfb.c      |  158 +++++++++++++++++++++++++++++++++++++-
+ drivers/video/atmel_lcdfb_core.c |  126 +-----------------------------
+ include/video/atmel_lcdc.h       |    8 ++-
+ 3 files changed, 166 insertions(+), 126 deletions(-)
+
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index 4e1454c..85063d6 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -12,12 +12,162 @@
+ #include <linux/platform_device.h>
+ #include <linux/interrupt.h>
+ #include <linux/fb.h>
++#include <linux/clk.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ 
++#include <mach/board.h>
++#include <mach/cpu.h>
++
+ #include <video/atmel_lcdc.h>
+ 
+-#ifdef CONFIG_PM
++/* configurable parameters */
++#define ATMEL_LCDC_DMA_BURST_LEN	8	/* words */
++#define ATMEL_LCDC_FIFO_SIZE		512	/* words */
++
++static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
++{
++	unsigned long value;
++
++	if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
++		|| cpu_is_at32ap7000()))
++		return xres;
++
++	value = xres;
++	if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
++		/* STN display */
++		if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
++			value *= 3;
++		}
++		if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
++		   || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
++		      && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
++			value = DIV_ROUND_UP(value, 4);
++		else
++			value = DIV_ROUND_UP(value, 8);
++	}
++
++	return value;
++}
++
++static int atmel_lcdfb_setup_core(struct fb_info *info)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++	unsigned long hozval_linesz;
++	unsigned long value;
++	unsigned long clk_value_khz;
++	unsigned long pix_factor = 2;
++
++	/* ...set frame size and burst length = 8 words (?) */
++	value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
++	value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
++	lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
++
++	/* Set pixel clock */
++	if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
++		pix_factor = 1;
++
++	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
++
++	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
++
++	if (value < pix_factor) {
++		dev_notice(info->device, "Bypassing pixel clock divider\n");
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
++	} else {
++		value = (value / pix_factor) - 1;
++		dev_dbg(info->device, "  * programming CLKVAL = 0x%08lx\n",
++				value);
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
++				value << ATMEL_LCDC_CLKVAL_OFFSET);
++		info->var.pixclock =
++			KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
++		dev_dbg(info->device, "  updated pixclk:     %lu KHz\n",
++					PICOS2KHZ(info->var.pixclock));
++	}
++
++
++	/* Initialize control register 2 */
++	value = sinfo->default_lcdcon2;
++
++	if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
++		value |= ATMEL_LCDC_INVLINE_INVERTED;
++	if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
++		value |= ATMEL_LCDC_INVFRAME_INVERTED;
++
++	switch (info->var.bits_per_pixel) {
++	case 1:
++		value |= ATMEL_LCDC_PIXELSIZE_1;
++		break;
++	case 2:
++		value |= ATMEL_LCDC_PIXELSIZE_2;
++		break;
++	case 4:
++		value |= ATMEL_LCDC_PIXELSIZE_4;
++		break;
++	case 8:
++		value |= ATMEL_LCDC_PIXELSIZE_8;
++		break;
++	case 15: /* fall through */
++	case 16:
++		value |= ATMEL_LCDC_PIXELSIZE_16;
++		break;
++	case 24:
++		value |= ATMEL_LCDC_PIXELSIZE_24;
++		break;
++	case 32:
++		value |= ATMEL_LCDC_PIXELSIZE_32;
++		break;
++	default:
++		BUG();
++		break;
++	}
++	dev_dbg(info->device, "  * LCDCON2 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
++
++	/* Vertical timing */
++	value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
++	value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
++	value |= info->var.lower_margin;
++	dev_dbg(info->device, "  * LCDTIM1 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
++
++	/* Horizontal timing */
++	value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
++	value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
++	value |= (info->var.left_margin - 1);
++	dev_dbg(info->device, "  * LCDTIM2 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
++
++	/* Horizontal value (aka line size) */
++	hozval_linesz = compute_hozval(info->var.xres,
++				lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
++
++	/* Display size */
++	value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
++	value |= info->var.yres - 1;
++	dev_dbg(info->device, "  * LCDFRMCFG = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
++
++	/* FIFO Threshold: Use formula from data sheet */
++	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
++	lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
++
++	/* Toggle LCD_MODE every frame */
++	lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
++
++	/* Disable all interrupts */
++	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
++	/* Enable FIFO & DMA errors */
++	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
++
++	/* ...wait for DMA engine to become idle... */
++	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
++		msleep(10);
++
++	return 0;
++}
++
+ 
+ static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
+ {
+@@ -66,9 +216,13 @@ static int atmel_lcdfb_resume(struct platform_device *pdev)
+ #define atmel_lcdfb_resume	NULL
+ #endif
+ 
++static struct atmel_lcdfb_devdata dev_data = {
++	.setup_core = atmel_lcdfb_setup_core,
++};
++
+ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
+ {
+-	return __atmel_lcdfb_probe(pdev);
++	return __atmel_lcdfb_probe(pdev, &dev_data);
+ }
+ static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
+ {
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+index 54bdbcb..9a7c5eb 100644
+--- a/drivers/video/atmel_lcdfb_core.c
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -27,8 +27,6 @@
+ 
+ /* configurable parameters */
+ #define ATMEL_LCDC_CVAL_DEFAULT		0xc8
+-#define ATMEL_LCDC_DMA_BURST_LEN	8	/* words */
+-#define ATMEL_LCDC_FIFO_SIZE		512	/* words */
+ 
+ #if defined(CONFIG_ARCH_AT91)
+ #define	ATMEL_LCDFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
+@@ -183,31 +181,6 @@ static struct fb_fix_screeninfo atmel_lcdfb_fix = {
+ 	.accel		= FB_ACCEL_NONE,
+ };
+ 
+-static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
+-{
+-	unsigned long value;
+-
+-	if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
+-		|| cpu_is_at32ap7000()))
+-		return xres;
+-
+-	value = xres;
+-	if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
+-		/* STN display */
+-		if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
+-			value *= 3;
+-		}
+-		if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
+-		   || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
+-		      && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
+-			value = DIV_ROUND_UP(value, 4);
+-		else
+-			value = DIV_ROUND_UP(value, 8);
+-	}
+-
+-	return value;
+-}
+-
+ static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
+ {
+ 	/* Turn off the LCD controller and the DMA controller */
+@@ -487,11 +460,7 @@ static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
+ static int atmel_lcdfb_set_par(struct fb_info *info)
+ {
+ 	struct atmel_lcdfb_info *sinfo = info->par;
+-	unsigned long hozval_linesz;
+-	unsigned long value;
+-	unsigned long clk_value_khz;
+ 	unsigned long bits_per_line;
+-	unsigned long pix_factor = 2;
+ 
+ 	might_sleep();
+ 
+@@ -516,98 +485,8 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
+ 	dev_dbg(info->device, "  * update DMA engine\n");
+ 	atmel_lcdfb_update_dma(info, &info->var);
+ 
+-	/* ...set frame size and burst length = 8 words (?) */
+-	value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
+-	value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
+-
+ 	/* Now, the LCDC core... */
+-
+-	/* Set pixel clock */
+-	if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
+-		pix_factor = 1;
+-
+-	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+-
+-	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
+-
+-	if (value < pix_factor) {
+-		dev_notice(info->device, "Bypassing pixel clock divider\n");
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
+-	} else {
+-		value = (value / pix_factor) - 1;
+-		dev_dbg(info->device, "  * programming CLKVAL = 0x%08lx\n",
+-				value);
+-		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
+-				value << ATMEL_LCDC_CLKVAL_OFFSET);
+-		info->var.pixclock =
+-			KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
+-		dev_dbg(info->device, "  updated pixclk:     %lu KHz\n",
+-					PICOS2KHZ(info->var.pixclock));
+-	}
+-
+-
+-	/* Initialize control register 2 */
+-	value = sinfo->default_lcdcon2;
+-
+-	if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
+-		value |= ATMEL_LCDC_INVLINE_INVERTED;
+-	if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
+-		value |= ATMEL_LCDC_INVFRAME_INVERTED;
+-
+-	switch (info->var.bits_per_pixel) {
+-		case 1:	value |= ATMEL_LCDC_PIXELSIZE_1; break;
+-		case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
+-		case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
+-		case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
+-		case 15: /* fall through */
+-		case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
+-		case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
+-		case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
+-		default: BUG(); break;
+-	}
+-	dev_dbg(info->device, "  * LCDCON2 = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
+-
+-	/* Vertical timing */
+-	value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
+-	value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
+-	value |= info->var.lower_margin;
+-	dev_dbg(info->device, "  * LCDTIM1 = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
+-
+-	/* Horizontal timing */
+-	value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
+-	value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
+-	value |= (info->var.left_margin - 1);
+-	dev_dbg(info->device, "  * LCDTIM2 = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
+-
+-	/* Horizontal value (aka line size) */
+-	hozval_linesz = compute_hozval(info->var.xres,
+-					lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
+-
+-	/* Display size */
+-	value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
+-	value |= info->var.yres - 1;
+-	dev_dbg(info->device, "  * LCDFRMCFG = %08lx\n", value);
+-	lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
+-
+-	/* FIFO Threshold: Use formula from data sheet */
+-	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
+-	lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
+-
+-	/* Toggle LCD_MODE every frame */
+-	lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
+-
+-	/* Disable all interrupts */
+-	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
+-	/* Enable FIFO & DMA errors */
+-	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
+-
+-	/* ...wait for DMA engine to become idle... */
+-	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
+-		msleep(10);
++	sinfo->dev_data->setup_core(info);
+ 
+ 	atmel_lcdfb_start(sinfo);
+ 
+@@ -837,7 +716,7 @@ int __atmel_lcdfb_probe(struct platform_device *pdev,
+ 
+ 	sinfo = info->par;
+ 
+-	if (dev->platform_data) {
++	if (dev->platform_data && dev_data) {
+ 		pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data;
+ 		sinfo->default_bpp = pdata_sinfo->default_bpp;
+ 		sinfo->default_dmacon = pdata_sinfo->default_dmacon;
+@@ -849,6 +728,7 @@ int __atmel_lcdfb_probe(struct platform_device *pdev,
+ 		sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight;
+ 		sinfo->lcdcon_pol_negative = pdata_sinfo->lcdcon_pol_negative;
+ 		sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode;
++		sinfo->dev_data = dev_data;
+ 	} else {
+ 		dev_err(dev, "cannot get default configuration\n");
+ 		goto free_info;
+diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
+index 4fa084b..b1a5fad1 100644
+--- a/include/video/atmel_lcdc.h
++++ b/include/video/atmel_lcdc.h
+@@ -37,15 +37,21 @@ extern void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo);
+ extern void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo);
+ extern void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo);
+ 
+-extern int __atmel_lcdfb_probe(struct platform_device *pdev);
++extern int __atmel_lcdfb_probe(struct platform_device *pdev,
++				struct atmel_lcdfb_devdata *devdata);
+ extern int __atmel_lcdfb_remove(struct platform_device *pdev);
+ 
++struct atmel_lcdfb_devdata {
++	int (*setup_core)(struct fb_info *info);
++};
++
+  /* LCD Controller info data structure, stored in device platform_data */
+ struct atmel_lcdfb_info {
+ 	spinlock_t		lock;
+ 	struct fb_info		*info;
+ 	void __iomem		*mmio;
+ 	int			irq_base;
++	struct atmel_lcdfb_devdata *dev_data;
+ 	struct work_struct	task;
+ 
+ 	unsigned int		guard_time;
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0075-video-atmelfb-refactor-start-stop.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0075-video-atmelfb-refactor-start-stop.patch
new file mode 100644
index 0000000..7a6c7ca
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0075-video-atmelfb-refactor-start-stop.patch
@@ -0,0 +1,196 @@
+From 129f891e93a10824f98ba2533744a6e0488c2afb Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Thu, 19 May 2011 15:12:30 +0200
+Subject: [PATCH 075/107] video: atmelfb: refactor start/stop
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/atmel_lcdfb.c      |   30 ++++++++++++++++++++++-
+ drivers/video/atmel_lcdfb_core.c |   50 +++++++++----------------------------
+ include/video/atmel_lcdc.h       |    9 ++++--
+ 3 files changed, 47 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index 85063d6..422be1a 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -25,6 +25,32 @@
+ #define ATMEL_LCDC_DMA_BURST_LEN	8	/* words */
+ #define ATMEL_LCDC_FIFO_SIZE		512	/* words */
+ 
++void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
++{
++	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
++	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
++		(sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
++		| ATMEL_LCDC_PWR);
++}
++
++static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo, u32 flags)
++{
++	/* Turn off the LCD controller and the DMA controller */
++	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
++			sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
++
++	/* Wait for the LCDC core to become idle */
++	while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
++		msleep(10);
++
++	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
++
++	if (!(flags & ATMEL_LCDC_STOP_NOWAIT))
++		/* Wait for DMA engine to become idle... */
++		while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
++			msleep(10);
++}
++
+ static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
+ {
+ 	unsigned long value;
+@@ -186,7 +212,7 @@ static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
+ 	if (sinfo->atmel_lcdfb_power_control)
+ 		sinfo->atmel_lcdfb_power_control(0);
+ 
+-	atmel_lcdfb_stop(sinfo);
++	atmel_lcdfb_stop(sinfo, 0);
+ 	atmel_lcdfb_stop_clock(sinfo);
+ 
+ 	return 0;
+@@ -218,6 +244,8 @@ static int atmel_lcdfb_resume(struct platform_device *pdev)
+ 
+ static struct atmel_lcdfb_devdata dev_data = {
+ 	.setup_core = atmel_lcdfb_setup_core,
++	.start = atmel_lcdfb_start,
++	.stop = atmel_lcdfb_stop,
+ };
+ 
+ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+index 9a7c5eb..8413b76 100644
+--- a/drivers/video/atmel_lcdfb_core.c
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -181,38 +181,6 @@ static struct fb_fix_screeninfo atmel_lcdfb_fix = {
+ 	.accel		= FB_ACCEL_NONE,
+ };
+ 
+-static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
+-{
+-	/* Turn off the LCD controller and the DMA controller */
+-	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
+-			sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
+-
+-	/* Wait for the LCDC core to become idle */
+-	while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
+-		msleep(10);
+-
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
+-}
+-
+-void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
+-{
+-	atmel_lcdfb_stop_nowait(sinfo);
+-
+-	/* Wait for DMA engine to become idle... */
+-	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
+-		msleep(10);
+-}
+-EXPORT_SYMBOL_GPL(atmel_lcdfb_stop);
+-
+-void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
+-{
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
+-	lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
+-		(sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
+-		| ATMEL_LCDC_PWR);
+-}
+-EXPORT_SYMBOL_GPL(atmel_lcdfb_start);
+-
+ static void atmel_lcdfb_update_dma(struct fb_info *info,
+ 			       struct fb_var_screeninfo *var)
+ {
+@@ -439,8 +407,10 @@ static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
+ {
+ 	might_sleep();
+ 
+-	atmel_lcdfb_stop(sinfo);
+-	atmel_lcdfb_start(sinfo);
++	if (sinfo->dev_data->stop)
++		sinfo->dev_data->stop(sinfo, 0);
++	if (sinfo->dev_data->start)
++		sinfo->dev_data->start(sinfo);
+ }
+ 
+ /**
+@@ -469,7 +439,8 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
+ 		 info->var.xres, info->var.yres,
+ 		 info->var.xres_virtual, info->var.yres_virtual);
+ 
+-	atmel_lcdfb_stop_nowait(sinfo);
++	if (sinfo->dev_data->stop)
++		sinfo->dev_data->stop(sinfo, ATMEL_LCDC_STOP_NOWAIT);
+ 
+ 	if (info->var.bits_per_pixel == 1)
+ 		info->fix.visual = FB_VISUAL_MONO01;
+@@ -488,7 +459,8 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
+ 	/* Now, the LCDC core... */
+ 	sinfo->dev_data->setup_core(info);
+ 
+-	atmel_lcdfb_start(sinfo);
++	if (sinfo->dev_data->start)
++		sinfo->dev_data->start(sinfo);
+ 
+ 	dev_dbg(info->device, "  * DONE\n");
+ 
+@@ -600,13 +572,15 @@ static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info)
+ 	switch (blank_mode) {
+ 	case FB_BLANK_UNBLANK:
+ 	case FB_BLANK_NORMAL:
+-		atmel_lcdfb_start(sinfo);
++		if (sinfo->dev_data->start)
++			sinfo->dev_data->start(sinfo);
+ 		break;
+ 	case FB_BLANK_VSYNC_SUSPEND:
+ 	case FB_BLANK_HSYNC_SUSPEND:
+ 		break;
+ 	case FB_BLANK_POWERDOWN:
+-		atmel_lcdfb_stop(sinfo);
++		if (sinfo->dev_data->stop)
++			sinfo->dev_data->stop(sinfo, 0);
+ 		break;
+ 	default:
+ 		return -EINVAL;
+diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
+index b1a5fad1..ea7ce31 100644
+--- a/include/video/atmel_lcdc.h
++++ b/include/video/atmel_lcdc.h
+@@ -32,17 +32,20 @@
+ #define ATMEL_LCDC_WIRING_RGB	1
+ #define ATMEL_LCDC_WIRING_RGB555	2
+ 
+-extern void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo);
+-extern void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo);
++#define ATMEL_LCDC_STOP_NOWAIT (1 << 0)
++
+ extern void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo);
+ extern void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo);
+-
+ extern int __atmel_lcdfb_probe(struct platform_device *pdev,
+ 				struct atmel_lcdfb_devdata *devdata);
+ extern int __atmel_lcdfb_remove(struct platform_device *pdev);
+ 
++struct atmel_lcdfb_info;
++
+ struct atmel_lcdfb_devdata {
+ 	int (*setup_core)(struct fb_info *info);
++	void (*start)(struct atmel_lcdfb_info *sinfo);
++	void (*stop)(struct atmel_lcdfb_info *sinfo, u32 flags);
+ };
+ 
+  /* LCD Controller info data structure, stored in device platform_data */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0076-video-atmelfb-refactor-isr.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0076-video-atmelfb-refactor-isr.patch
new file mode 100644
index 0000000..86ae469
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0076-video-atmelfb-refactor-isr.patch
@@ -0,0 +1,154 @@
+From 8e18c2a07ac0e90f347bbb66aa83b8a7ea008152 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Thu, 19 May 2011 15:37:12 +0200
+Subject: [PATCH 076/107] video: atmelfb: refactor isr
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/atmel_lcdfb.c      |   18 +++++++++++++++++
+ drivers/video/atmel_lcdfb_core.c |   39 +++++++++++--------------------------
+ include/video/atmel_lcdc.h       |    2 +
+ 3 files changed, 32 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index 422be1a..3653e2a 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -194,6 +194,23 @@ static int atmel_lcdfb_setup_core(struct fb_info *info)
+ 	return 0;
+ }
+ 
++static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
++{
++	struct fb_info *info = dev_id;
++	struct atmel_lcdfb_info *sinfo = info->par;
++	u32 status;
++
++	status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
++	if (status & ATMEL_LCDC_UFLWI) {
++		dev_warn(info->device, "FIFO underflow %#x\n", status);
++		/* reset DMA and FIFO to avoid screen shifting */
++		schedule_work(&sinfo->task);
++	}
++	lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
++	return IRQ_HANDLED;
++}
++
++#ifdef CONFIG_PM
+ 
+ static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
+ {
+@@ -246,6 +263,7 @@ static struct atmel_lcdfb_devdata dev_data = {
+ 	.setup_core = atmel_lcdfb_setup_core,
+ 	.start = atmel_lcdfb_start,
+ 	.stop = atmel_lcdfb_stop,
++	.isr = atmel_lcdfb_interrupt,
+ };
+ 
+ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+index 8413b76..eab4d88 100644
+--- a/drivers/video/atmel_lcdfb_core.c
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -602,22 +602,6 @@ static struct fb_ops atmel_lcdfb_ops = {
+ 	.fb_imageblit	= cfb_imageblit,
+ };
+ 
+-static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
+-{
+-	struct fb_info *info = dev_id;
+-	struct atmel_lcdfb_info *sinfo = info->par;
+-	u32 status;
+-
+-	status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
+-	if (status & ATMEL_LCDC_UFLWI) {
+-		dev_warn(info->device, "FIFO underflow %#x\n", status);
+-		/* reset DMA and FIFO to avoid screen shifting */
+-		schedule_work(&sinfo->task);
+-	}
+-	lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
+-	return IRQ_HANDLED;
+-}
+-
+ /*
+  * LCD controller task (to reset the LCD)
+  */
+@@ -750,12 +734,8 @@ int __atmel_lcdfb_probe(struct platform_device *pdev,
+ 		goto stop_clk;
+ 	}
+ 
++	/* No error checking, some devices can do without IRQ */
+ 	sinfo->irq_base = platform_get_irq(pdev, 0);
+-	if (sinfo->irq_base < 0) {
+-		dev_err(dev, "unable to get irq\n");
+-		ret = sinfo->irq_base;
+-		goto stop_clk;
+-	}
+ 
+ 	/* Initialize video memory */
+ 	map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+@@ -806,10 +786,13 @@ int __atmel_lcdfb_probe(struct platform_device *pdev,
+ 	init_contrast(sinfo);
+ 
+ 	/* interrupt */
+-	ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
+-	if (ret) {
+-		dev_err(dev, "request_irq failed: %d\n", ret);
+-		goto unmap_mmio;
++	if (sinfo->irq_base >= 0) {
++		ret = request_irq(sinfo->irq_base, sinfo->dev_data->isr,
++				IRQF_SHARED, pdev->name, info);
++		if (ret) {
++			dev_err(dev, "request_irq failed: %d\n", ret);
++			goto unmap_mmio;
++		}
+ 	}
+ 
+ 	/* Some operations on the LCDC might sleep and
+@@ -864,7 +847,8 @@ free_cmap:
+ 	fb_dealloc_cmap(&info->cmap);
+ unregister_irqs:
+ 	cancel_work_sync(&sinfo->task);
+-	free_irq(sinfo->irq_base, info);
++	if (sinfo->irq_base >= 0)
++		free_irq(sinfo->irq_base, info);
+ unmap_mmio:
+ 	exit_backlight(sinfo);
+ 	iounmap(sinfo->mmio);
+@@ -913,7 +897,8 @@ int __atmel_lcdfb_remove(struct platform_device *pdev)
+ 	if (sinfo->bus_clk)
+ 		clk_put(sinfo->bus_clk);
+ 	fb_dealloc_cmap(&info->cmap);
+-	free_irq(sinfo->irq_base, info);
++	if (sinfo->irq_base >= 0)
++		free_irq(sinfo->irq_base, info);
+ 	iounmap(sinfo->mmio);
+  	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
+ 	if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
+diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
+index ea7ce31..14b5664 100644
+--- a/include/video/atmel_lcdc.h
++++ b/include/video/atmel_lcdc.h
+@@ -23,6 +23,7 @@
+ #define __ATMEL_LCDC_H__
+ 
+ #include <linux/workqueue.h>
++#include <linux/interrupt.h>
+ 
+ /* Way LCD wires are connected to the chip:
+  * Some Atmel chips use BGR color mode (instead of standard RGB)
+@@ -46,6 +47,7 @@ struct atmel_lcdfb_devdata {
+ 	int (*setup_core)(struct fb_info *info);
+ 	void (*start)(struct atmel_lcdfb_info *sinfo);
+ 	void (*stop)(struct atmel_lcdfb_info *sinfo, u32 flags);
++	irqreturn_t (*isr)(int irq, void *dev_id);
+ };
+ 
+  /* LCD Controller info data structure, stored in device platform_data */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0077-video-atmelfb-refactor-backlight-routines.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0077-video-atmelfb-refactor-backlight-routines.patch
new file mode 100644
index 0000000..d49197a
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0077-video-atmelfb-refactor-backlight-routines.patch
@@ -0,0 +1,256 @@
+From cdde3f0de6b5fb035fd79751d93f30f7420fa246 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Thu, 19 May 2011 16:40:13 +0200
+Subject: [PATCH 077/107] video: atmelfb: refactor backlight routines
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/atmel_lcdfb.c      |   61 +++++++++++++++++++++++++++++++
+ drivers/video/atmel_lcdfb_core.c |   73 ++++----------------------------------
+ include/video/atmel_lcdc.h       |    3 ++
+ 3 files changed, 71 insertions(+), 66 deletions(-)
+
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index 3653e2a..046e6c5 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -11,6 +11,7 @@
+ #include <linux/kernel.h>
+ #include <linux/platform_device.h>
+ #include <linux/interrupt.h>
++#include <linux/backlight.h>
+ #include <linux/fb.h>
+ #include <linux/clk.h>
+ #include <linux/init.h>
+@@ -22,9 +23,67 @@
+ #include <video/atmel_lcdc.h>
+ 
+ /* configurable parameters */
++#define ATMEL_LCDC_CVAL_DEFAULT		0xc8
+ #define ATMEL_LCDC_DMA_BURST_LEN	8	/* words */
+ #define ATMEL_LCDC_FIFO_SIZE		512	/* words */
+ 
++static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
++		| ATMEL_LCDC_POL_POSITIVE
++		| ATMEL_LCDC_ENA_PWMENABLE;
++
++/* some bl->props field just changed */
++static int atmel_bl_update_status(struct backlight_device *bl)
++{
++	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
++	int power = sinfo->bl_power;
++	int brightness = bl->props.brightness;
++
++	/* REVISIT there may be a meaningful difference between
++	 * fb_blank and power ... there seem to be some cases
++	 * this doesn't handle correctly.
++	 */
++	if (bl->props.fb_blank != sinfo->bl_power)
++		power = bl->props.fb_blank;
++	else if (bl->props.power != sinfo->bl_power)
++		power = bl->props.power;
++
++	if (brightness < 0 && power == FB_BLANK_UNBLANK)
++		brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
++	else if (power != FB_BLANK_UNBLANK)
++		brightness = 0;
++
++	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
++	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
++			brightness ? contrast_ctr : 0);
++
++	bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
++
++	return 0;
++}
++
++static int atmel_bl_get_brightness(struct backlight_device *bl)
++{
++	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
++
++	return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
++}
++
++static const struct backlight_ops atmel_lcdc_bl_ops = {
++	.update_status = atmel_bl_update_status,
++	.get_brightness = atmel_bl_get_brightness,
++};
++
++static void atmel_lcdfb_init_contrast(struct atmel_lcdfb_info *sinfo)
++{
++	/* contrast pwm can be 'inverted' */
++	if (sinfo->lcdcon_pol_negative)
++			contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
++
++	/* have some default contrast/backlight settings */
++	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
++	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
++}
++
+ void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
+ {
+ 	lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
+@@ -264,6 +323,8 @@ static struct atmel_lcdfb_devdata dev_data = {
+ 	.start = atmel_lcdfb_start,
+ 	.stop = atmel_lcdfb_stop,
+ 	.isr = atmel_lcdfb_interrupt,
++	.bl_ops = &atmel_lcdc_bl_ops,
++	.init_contrast = atmel_lcdfb_init_contrast,
+ };
+ 
+ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+index eab4d88..ef63996 100644
+--- a/drivers/video/atmel_lcdfb_core.c
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -16,7 +16,6 @@
+ #include <linux/fb.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+-#include <linux/backlight.h>
+ #include <linux/gfp.h>
+ 
+ #include <mach/board.h>
+@@ -63,54 +62,8 @@ static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
+ }
+ #endif
+ 
+-static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
+-		| ATMEL_LCDC_POL_POSITIVE
+-		| ATMEL_LCDC_ENA_PWMENABLE;
+-
+ #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
+ 
+-/* some bl->props field just changed */
+-static int atmel_bl_update_status(struct backlight_device *bl)
+-{
+-	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
+-	int			power = sinfo->bl_power;
+-	int			brightness = bl->props.brightness;
+-
+-	/* REVISIT there may be a meaningful difference between
+-	 * fb_blank and power ... there seem to be some cases
+-	 * this doesn't handle correctly.
+-	 */
+-	if (bl->props.fb_blank != sinfo->bl_power)
+-		power = bl->props.fb_blank;
+-	else if (bl->props.power != sinfo->bl_power)
+-		power = bl->props.power;
+-
+-	if (brightness < 0 && power == FB_BLANK_UNBLANK)
+-		brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
+-	else if (power != FB_BLANK_UNBLANK)
+-		brightness = 0;
+-
+-	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
+-	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
+-			brightness ? contrast_ctr : 0);
+-
+-	bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
+-
+-	return 0;
+-}
+-
+-static int atmel_bl_get_brightness(struct backlight_device *bl)
+-{
+-	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
+-
+-	return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
+-}
+-
+-static const struct backlight_ops atmel_lcdc_bl_ops = {
+-	.update_status = atmel_bl_update_status,
+-	.get_brightness = atmel_bl_get_brightness,
+-};
+-
+ static void init_backlight(struct atmel_lcdfb_info *sinfo)
+ {
+ 	struct backlight_properties props;
+@@ -118,14 +71,14 @@ static void init_backlight(struct atmel_lcdfb_info *sinfo)
+ 
+ 	sinfo->bl_power = FB_BLANK_UNBLANK;
+ 
+-	if (sinfo->backlight)
++	if (sinfo->backlight || !sinfo->dev_data->bl_ops)
+ 		return;
+ 
+ 	memset(&props, 0, sizeof(struct backlight_properties));
+ 	props.type = BACKLIGHT_RAW;
+ 	props.max_brightness = 0xff;
+ 	bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo,
+-				       &atmel_lcdc_bl_ops, &props);
++				       sinfo->dev_data->bl_ops, &props);
+ 	if (IS_ERR(bl)) {
+ 		dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
+ 				PTR_ERR(bl));
+@@ -135,7 +88,7 @@ static void init_backlight(struct atmel_lcdfb_info *sinfo)
+ 
+ 	bl->props.power = FB_BLANK_UNBLANK;
+ 	bl->props.fb_blank = FB_BLANK_UNBLANK;
+-	bl->props.brightness = atmel_bl_get_brightness(bl);
++	bl->props.brightness = sinfo->dev_data->bl_ops->get_brightness(bl);
+ }
+ 
+ static void exit_backlight(struct atmel_lcdfb_info *sinfo)
+@@ -157,21 +110,6 @@ static void exit_backlight(struct atmel_lcdfb_info *sinfo)
+ 
+ #endif
+ 
+-static void init_contrast(struct atmel_lcdfb_info *sinfo)
+-{
+-	/* contrast pwm can be 'inverted' */
+-	if (sinfo->lcdcon_pol_negative)
+-			contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
+-
+-	/* have some default contrast/backlight settings */
+-	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
+-	lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
+-
+-	if (sinfo->lcdcon_is_backlight)
+-		init_backlight(sinfo);
+-}
+-
+-
+ static struct fb_fix_screeninfo atmel_lcdfb_fix = {
+ 	.type		= FB_TYPE_PACKED_PIXELS,
+ 	.visual		= FB_VISUAL_TRUECOLOR,
+@@ -783,7 +721,10 @@ int __atmel_lcdfb_probe(struct platform_device *pdev,
+ 	}
+ 
+ 	/* Initialize PWM for contrast or backlight ("off") */
+-	init_contrast(sinfo);
++	if (sinfo->dev_data->init_contrast)
++		sinfo->dev_data->init_contrast(sinfo);
++	if (sinfo->lcdcon_is_backlight)
++		init_backlight(sinfo);
+ 
+ 	/* interrupt */
+ 	if (sinfo->irq_base >= 0) {
+diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
+index 14b5664..e7c0a3f 100644
+--- a/include/video/atmel_lcdc.h
++++ b/include/video/atmel_lcdc.h
+@@ -24,6 +24,7 @@
+ 
+ #include <linux/workqueue.h>
+ #include <linux/interrupt.h>
++#include <linux/backlight.h>
+ 
+ /* Way LCD wires are connected to the chip:
+  * Some Atmel chips use BGR color mode (instead of standard RGB)
+@@ -48,6 +49,8 @@ struct atmel_lcdfb_devdata {
+ 	void (*start)(struct atmel_lcdfb_info *sinfo);
+ 	void (*stop)(struct atmel_lcdfb_info *sinfo, u32 flags);
+ 	irqreturn_t (*isr)(int irq, void *dev_id);
++	void (*init_contrast)(struct atmel_lcdfb_info *sinfo);
++	const struct backlight_ops *bl_ops;
+ };
+ 
+  /* LCD Controller info data structure, stored in device platform_data */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0078-video-atmelfb-refactor-dma_update.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0078-video-atmelfb-refactor-dma_update.patch
new file mode 100644
index 0000000..5af1159
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0078-video-atmelfb-refactor-dma_update.patch
@@ -0,0 +1,211 @@
+From f1495d8f9cdd7d7c142776f83568b145533884ef Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Fri, 20 May 2011 14:31:29 +0200
+Subject: [PATCH 078/107] video: atmelfb: refactor dma_update
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/atmel_lcdfb.c      |   55 ++++++++++++++++++++++++++++++++++
+ drivers/video/atmel_lcdfb_core.c |   61 +++----------------------------------
+ include/video/atmel_lcdc.h       |    2 +
+ 3 files changed, 62 insertions(+), 56 deletions(-)
+
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index 046e6c5..cd6d22e 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -31,6 +31,59 @@ static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
+ 		| ATMEL_LCDC_POL_POSITIVE
+ 		| ATMEL_LCDC_ENA_PWMENABLE;
+ 
++#if defined(CONFIG_ARCH_AT91)
++#define	ATMEL_LCDFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
++					 | FBINFO_PARTIAL_PAN_OK \
++					 | FBINFO_HWACCEL_YPAN)
++
++static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
++					struct fb_var_screeninfo *var)
++{
++
++}
++#elif defined(CONFIG_AVR32)
++#define	ATMEL_LCDFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
++					| FBINFO_PARTIAL_PAN_OK \
++					| FBINFO_HWACCEL_XPAN \
++					| FBINFO_HWACCEL_YPAN)
++
++static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
++				     struct fb_var_screeninfo *var)
++{
++	u32 dma2dcfg;
++	u32 pixeloff;
++
++	pixeloff = (var->xoffset * var->bits_per_pixel) & 0x1f;
++
++	dma2dcfg = ((var->xres_virtual - var->xres) * var->bits_per_pixel) / 8;
++	dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
++	lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
++
++	/* Update configuration */
++	lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
++		    lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
++		    | ATMEL_LCDC_DMAUPDT);
++}
++#endif
++
++static void atmel_lcdfb_update_dma(struct fb_info *info,
++			       struct fb_var_screeninfo *var)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++	struct fb_fix_screeninfo *fix = &info->fix;
++	unsigned long dma_addr;
++
++	dma_addr = (fix->smem_start + var->yoffset * fix->line_length
++		    + var->xoffset * var->bits_per_pixel / 8);
++
++	dma_addr &= ~3UL;
++
++	/* Set framebuffer DMA base address and pixel offset */
++	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
++
++	atmel_lcdfb_update_dma2d(sinfo, var);
++}
++
+ /* some bl->props field just changed */
+ static int atmel_bl_update_status(struct backlight_device *bl)
+ {
+@@ -323,8 +376,10 @@ static struct atmel_lcdfb_devdata dev_data = {
+ 	.start = atmel_lcdfb_start,
+ 	.stop = atmel_lcdfb_stop,
+ 	.isr = atmel_lcdfb_interrupt,
++	.update_dma = atmel_lcdfb_update_dma,
+ 	.bl_ops = &atmel_lcdc_bl_ops,
+ 	.init_contrast = atmel_lcdfb_init_contrast,
++	.fbinfo_flags = ATMEL_LCDFB_FBINFO_DEFAULT,
+ };
+ 
+ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+index ef63996..4146e9b 100644
+--- a/drivers/video/atmel_lcdfb_core.c
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -27,41 +27,6 @@
+ /* configurable parameters */
+ #define ATMEL_LCDC_CVAL_DEFAULT		0xc8
+ 
+-#if defined(CONFIG_ARCH_AT91)
+-#define	ATMEL_LCDFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
+-					 | FBINFO_PARTIAL_PAN_OK \
+-					 | FBINFO_HWACCEL_YPAN)
+-
+-static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
+-					struct fb_var_screeninfo *var)
+-{
+-
+-}
+-#elif defined(CONFIG_AVR32)
+-#define	ATMEL_LCDFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
+-					| FBINFO_PARTIAL_PAN_OK \
+-					| FBINFO_HWACCEL_XPAN \
+-					| FBINFO_HWACCEL_YPAN)
+-
+-static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
+-				     struct fb_var_screeninfo *var)
+-{
+-	u32 dma2dcfg;
+-	u32 pixeloff;
+-
+-	pixeloff = (var->xoffset * var->bits_per_pixel) & 0x1f;
+-
+-	dma2dcfg = ((var->xres_virtual - var->xres) * var->bits_per_pixel) / 8;
+-	dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
+-
+-	/* Update configuration */
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
+-		    lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
+-		    | ATMEL_LCDC_DMAUPDT);
+-}
+-#endif
+-
+ #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
+ 
+ static void init_backlight(struct atmel_lcdfb_info *sinfo)
+@@ -119,24 +84,6 @@ static struct fb_fix_screeninfo atmel_lcdfb_fix = {
+ 	.accel		= FB_ACCEL_NONE,
+ };
+ 
+-static void atmel_lcdfb_update_dma(struct fb_info *info,
+-			       struct fb_var_screeninfo *var)
+-{
+-	struct atmel_lcdfb_info *sinfo = info->par;
+-	struct fb_fix_screeninfo *fix = &info->fix;
+-	unsigned long dma_addr;
+-
+-	dma_addr = (fix->smem_start + var->yoffset * fix->line_length
+-		    + var->xoffset * var->bits_per_pixel / 8);
+-
+-	dma_addr &= ~3UL;
+-
+-	/* Set framebuffer DMA base address and pixel offset */
+-	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
+-
+-	atmel_lcdfb_update_dma2d(sinfo, var);
+-}
+-
+ static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
+ {
+ 	struct fb_info *info = sinfo->info;
+@@ -392,7 +339,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
+ 
+ 	/* Re-initialize the DMA engine... */
+ 	dev_dbg(info->device, "  * update DMA engine\n");
+-	atmel_lcdfb_update_dma(info, &info->var);
++	sinfo->dev_data->update_dma(info, &info->var);
+ 
+ 	/* Now, the LCDC core... */
+ 	sinfo->dev_data->setup_core(info);
+@@ -496,9 +443,11 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
+ static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
+ 			       struct fb_info *info)
+ {
++	struct atmel_lcdfb_info *sinfo = info->par;
++
+ 	dev_dbg(info->device, "%s\n", __func__);
+ 
+-	atmel_lcdfb_update_dma(info, var);
++	sinfo->dev_data->update_dma(info, var);
+ 
+ 	return 0;
+ }
+@@ -633,7 +582,7 @@ int __atmel_lcdfb_probe(struct platform_device *pdev,
+ 	sinfo->pdev = pdev;
+ 
+ 	strcpy(info->fix.id, sinfo->pdev->name);
+-	info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
++	info->flags = dev_data->fbinfo_flags;
+ 	info->pseudo_palette = sinfo->pseudo_palette;
+ 	info->fbops = &atmel_lcdfb_ops;
+ 
+diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
+index e7c0a3f..866ab47 100644
+--- a/include/video/atmel_lcdc.h
++++ b/include/video/atmel_lcdc.h
+@@ -49,8 +49,10 @@ struct atmel_lcdfb_devdata {
+ 	void (*start)(struct atmel_lcdfb_info *sinfo);
+ 	void (*stop)(struct atmel_lcdfb_info *sinfo, u32 flags);
+ 	irqreturn_t (*isr)(int irq, void *dev_id);
++	void (*update_dma)(struct fb_info *info, struct fb_var_screeninfo *var);
+ 	void (*init_contrast)(struct atmel_lcdfb_info *sinfo);
+ 	const struct backlight_ops *bl_ops;
++	int fbinfo_flags;
+ };
+ 
+  /* LCD Controller info data structure, stored in device platform_data */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0079-video-atmelfb-refactor-LUT.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0079-video-atmelfb-refactor-LUT.patch
new file mode 100644
index 0000000..ab76f70
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0079-video-atmelfb-refactor-LUT.patch
@@ -0,0 +1,80 @@
+From e765be3c1f14cafb2c8c9ffcd0dd6504c37a20d1 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Fri, 20 May 2011 14:51:45 +0200
+Subject: [PATCH 079/107] video: atmelfb: refactor LUT
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/atmel_lcdfb.c      |    1 +
+ drivers/video/atmel_lcdfb_core.c |    6 ++++--
+ include/video/atmel_lcdc.h       |    8 ++------
+ 3 files changed, 7 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index cd6d22e..f8993cd 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -380,6 +380,7 @@ static struct atmel_lcdfb_devdata dev_data = {
+ 	.bl_ops = &atmel_lcdc_bl_ops,
+ 	.init_contrast = atmel_lcdfb_init_contrast,
+ 	.fbinfo_flags = ATMEL_LCDFB_FBINFO_DEFAULT,
++	.lut_base = ATMEL_LCDC_LUT,
+ };
+ 
+ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+index 4146e9b..0edafb6 100644
+--- a/drivers/video/atmel_lcdfb_core.c
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -422,7 +422,8 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
+ 			 *   ~(red[10] ^ green[10] ^ blue[10]) & 1
+ 			 */
+ 
+-			lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
++			lcdc_writel(sinfo, sinfo->dev_data->lut_base + regno * 4,
++					val);
+ 			ret = 0;
+ 		}
+ 		break;
+@@ -430,7 +431,8 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
+ 	case FB_VISUAL_MONO01:
+ 		if (regno < 2) {
+ 			val = (regno == 0) ? 0x00 : 0x1F;
+-			lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
++			lcdc_writel(sinfo, sinfo->dev_data->lut_base + regno * 4,
++					val);
+ 			ret = 0;
+ 		}
+ 		break;
+diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
+index 866ab47..6c470c4 100644
+--- a/include/video/atmel_lcdc.h
++++ b/include/video/atmel_lcdc.h
+@@ -53,6 +53,7 @@ struct atmel_lcdfb_devdata {
+ 	void (*init_contrast)(struct atmel_lcdfb_info *sinfo);
+ 	const struct backlight_ops *bl_ops;
+ 	int fbinfo_flags;
++	u32 lut_base;
+ };
+ 
+  /* LCD Controller info data structure, stored in device platform_data */
+@@ -241,11 +242,6 @@ struct atmel_lcdfb_info {
+ #define	ATMEL_LCDC_OWRI		(1 << 5)
+ #define	ATMEL_LCDC_MERI		(1 << 6)
+ 
+-#if !defined(CONFIG_ARCH_AT91SAM9X5)
+-#define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
+-#else
+-/* Base layer CLUT */
+-#define ATMEL_LCDC_LUT(n)	(0x0400 + ((n)*4))
+-#endif
++#define ATMEL_LCDC_LUT		0x0c00
+ 
+ #endif /* __ATMEL_LCDC_H__ */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0080-video-atmelfb-refactor-limit_screeninfo.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0080-video-atmelfb-refactor-limit_screeninfo.patch
new file mode 100644
index 0000000..d115da5
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0080-video-atmelfb-refactor-limit_screeninfo.patch
@@ -0,0 +1,92 @@
+From 41af945f4205a245cbb3a4227a4b8407df628e03 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Fri, 20 May 2011 15:04:10 +0200
+Subject: [PATCH 080/107] video: atmelfb: refactor limit_screeninfo
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/atmel_lcdfb.c      |   18 ++++++++++++++++++
+ drivers/video/atmel_lcdfb_core.c |   14 ++------------
+ include/video/atmel_lcdc.h       |    1 +
+ 3 files changed, 21 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index f8993cd..7a48e9c 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -306,6 +306,23 @@ static int atmel_lcdfb_setup_core(struct fb_info *info)
+ 	return 0;
+ }
+ 
++static void atmelfb_limit_screeninfo(struct fb_var_screeninfo *var)
++{
++	/* Saturate vertical and horizontal timings at maximum values */
++	var->vsync_len = min_t(u32, var->vsync_len,
++			(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
++	var->upper_margin = min_t(u32, var->upper_margin,
++			ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
++	var->lower_margin = min_t(u32, var->lower_margin,
++			ATMEL_LCDC_VFP);
++	var->right_margin = min_t(u32, var->right_margin,
++			(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
++	var->hsync_len = min_t(u32, var->hsync_len,
++			(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
++	var->left_margin = min_t(u32, var->left_margin,
++			ATMEL_LCDC_HBP + 1);
++}
++
+ static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
+ {
+ 	struct fb_info *info = dev_id;
+@@ -379,6 +396,7 @@ static struct atmel_lcdfb_devdata dev_data = {
+ 	.update_dma = atmel_lcdfb_update_dma,
+ 	.bl_ops = &atmel_lcdc_bl_ops,
+ 	.init_contrast = atmel_lcdfb_init_contrast,
++	.limit_screeninfo = atmelfb_limit_screeninfo,
+ 	.fbinfo_flags = ATMEL_LCDFB_FBINFO_DEFAULT,
+ 	.lut_base = ATMEL_LCDC_LUT,
+ };
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+index 0edafb6..20a4e4f 100644
+--- a/drivers/video/atmel_lcdfb_core.c
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -211,18 +211,8 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
+ 	}
+ 
+ 	/* Saturate vertical and horizontal timings at maximum values */
+-	var->vsync_len = min_t(u32, var->vsync_len,
+-			(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
+-	var->upper_margin = min_t(u32, var->upper_margin,
+-			ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
+-	var->lower_margin = min_t(u32, var->lower_margin,
+-			ATMEL_LCDC_VFP);
+-	var->right_margin = min_t(u32, var->right_margin,
+-			(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
+-	var->hsync_len = min_t(u32, var->hsync_len,
+-			(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
+-	var->left_margin = min_t(u32, var->left_margin,
+-			ATMEL_LCDC_HBP + 1);
++	if (sinfo->dev_data->limit_screeninfo)
++		sinfo->dev_data->limit_screeninfo(var);
+ 
+ 	/* Some parameters can't be zero */
+ 	var->vsync_len = max_t(u32, var->vsync_len, 1);
+diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
+index 6c470c4..6031b5a 100644
+--- a/include/video/atmel_lcdc.h
++++ b/include/video/atmel_lcdc.h
+@@ -51,6 +51,7 @@ struct atmel_lcdfb_devdata {
+ 	irqreturn_t (*isr)(int irq, void *dev_id);
+ 	void (*update_dma)(struct fb_info *info, struct fb_var_screeninfo *var);
+ 	void (*init_contrast)(struct atmel_lcdfb_info *sinfo);
++	void (*limit_screeninfo)(struct fb_var_screeninfo *var);
+ 	const struct backlight_ops *bl_ops;
+ 	int fbinfo_flags;
+ 	u32 lut_base;
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0081-arm-at91-refactor-lcdc-includes.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0081-arm-at91-refactor-lcdc-includes.patch
new file mode 100644
index 0000000..61135dd
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0081-arm-at91-refactor-lcdc-includes.patch
@@ -0,0 +1,2648 @@
+From 49526d6bdc4a61e24b8d68fa68cb3718ab936353 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Wed, 25 May 2011 15:38:50 +0200
+Subject: [PATCH 081/107] arm: at91: refactor lcdc-includes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Among others the HEO-ISR bit is fixed.
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/mach-at91/at91cap9_devices.c             |    3 +-
+ arch/arm/mach-at91/at91sam9261_devices.c          |    3 +-
+ arch/arm/mach-at91/at91sam9263_devices.c          |    3 +-
+ arch/arm/mach-at91/at91sam9g45_devices.c          |    3 +-
+ arch/arm/mach-at91/at91sam9rl_devices.c           |    3 +-
+ arch/arm/mach-at91/at91sam9x5_devices.c           |    6 +-
+ arch/arm/mach-at91/board-cap9adk.c                |    3 +-
+ arch/arm/mach-at91/board-neocore926.c             |    3 +-
+ arch/arm/mach-at91/board-sam9261ek.c              |    3 +-
+ arch/arm/mach-at91/board-sam9263ek.c              |    3 +-
+ arch/arm/mach-at91/board-sam9m10g45ek.c           |    3 +-
+ arch/arm/mach-at91/board-sam9rlek.c               |    3 +-
+ arch/arm/mach-at91/board-sam9x5cm.c               |    2 +-
+ arch/arm/mach-at91/board-sam9x5ek.c               |    4 +-
+ arch/arm/mach-at91/include/mach/atmel_hlcdc.h     |  721 +++++++++++++++++
+ arch/arm/mach-at91/include/mach/atmel_hlcdc_ovl.h |  156 ++++
+ arch/arm/mach-at91/include/mach/atmel_hlcdfb.h    |  868 ---------------------
+ arch/arm/mach-at91/include/mach/atmel_lcdc.h      |  177 +++++
+ drivers/video/atmel_lcdfb.c                       |    3 +-
+ drivers/video/atmel_lcdfb_core.c                  |    2 +-
+ include/video/atmel_lcdc.h                        |  248 ------
+ include/video/atmel_lcdfb.h                       |  100 +++
+ 22 files changed, 1185 insertions(+), 1135 deletions(-)
+ create mode 100644 arch/arm/mach-at91/include/mach/atmel_hlcdc.h
+ create mode 100644 arch/arm/mach-at91/include/mach/atmel_hlcdc_ovl.h
+ delete mode 100644 arch/arm/mach-at91/include/mach/atmel_hlcdfb.h
+ create mode 100644 arch/arm/mach-at91/include/mach/atmel_lcdc.h
+ delete mode 100644 include/video/atmel_lcdc.h
+ create mode 100644 include/video/atmel_lcdfb.h
+
+diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
+index 9ffbf3a..3398087 100644
+--- a/arch/arm/mach-at91/at91cap9_devices.c
++++ b/arch/arm/mach-at91/at91cap9_devices.c
+@@ -19,11 +19,12 @@
+ #include <linux/platform_device.h>
+ #include <linux/i2c-gpio.h>
+ 
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <mach/board.h>
+ #include <mach/cpu.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_lcdc.h>
+ #include <mach/at91cap9.h>
+ #include <mach/at91cap9_matrix.h>
+ #include <mach/at91sam9_smc.h>
+diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
+index 59fc483..24301b2 100644
+--- a/arch/arm/mach-at91/at91sam9261_devices.c
++++ b/arch/arm/mach-at91/at91sam9261_devices.c
+@@ -18,10 +18,11 @@
+ #include <linux/i2c-gpio.h>
+ 
+ #include <linux/fb.h>
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_lcdc.h>
+ #include <mach/at91sam9261.h>
+ #include <mach/at91sam9261_matrix.h>
+ #include <mach/at91sam9_smc.h>
+diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
+index fb5c23a..9bb45ae 100644
+--- a/arch/arm/mach-at91/at91sam9263_devices.c
++++ b/arch/arm/mach-at91/at91sam9263_devices.c
+@@ -17,10 +17,11 @@
+ #include <linux/i2c-gpio.h>
+ 
+ #include <linux/fb.h>
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_lcdc.h>
+ #include <mach/at91sam9263.h>
+ #include <mach/at91sam9263_matrix.h>
+ #include <mach/at91sam9_smc.h>
+diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
+index 1e8f275..f40b254 100644
+--- a/arch/arm/mach-at91/at91sam9g45_devices.c
++++ b/arch/arm/mach-at91/at91sam9g45_devices.c
+@@ -18,10 +18,11 @@
+ #include <linux/atmel-mci.h>
+ 
+ #include <linux/fb.h>
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_lcdc.h>
+ #include <mach/at91sam9g45.h>
+ #include <mach/at91sam9g45_matrix.h>
+ #include <mach/at91sam9_smc.h>
+diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
+index 53aaa94..7ca92f1 100644
+--- a/arch/arm/mach-at91/at91sam9rl_devices.c
++++ b/arch/arm/mach-at91/at91sam9rl_devices.c
+@@ -14,10 +14,11 @@
+ #include <linux/i2c-gpio.h>
+ 
+ #include <linux/fb.h>
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_lcdc.h>
+ #include <mach/at91sam9rl.h>
+ #include <mach/at91sam9rl_matrix.h>
+ #include <mach/at91sam9_smc.h>
+diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
+index e601ae4..36a192a 100644
+--- a/arch/arm/mach-at91/at91sam9x5_devices.c
++++ b/arch/arm/mach-at91/at91sam9x5_devices.c
+@@ -16,13 +16,13 @@
+ #include <linux/platform_device.h>
+ #include <linux/i2c-gpio.h>
+ #include <linux/atmel-mci.h>
+-
+ #include <linux/fb.h>
+-#include <video/atmel_lcdc.h>
+-#include <mach/atmel_hlcdfb.h>
++
++#include <video/atmel_lcdfb.h>
+ 
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_hlcdc.h>
+ #include <mach/cpu.h>
+ #include <mach/at91sam9x5.h>
+ #include <mach/at91sam9x5_matrix.h>
+diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
+index e727444..017c7f4 100644
+--- a/arch/arm/mach-at91/board-cap9adk.c
++++ b/arch/arm/mach-at91/board-cap9adk.c
+@@ -31,7 +31,7 @@
+ #include <linux/fb.h>
+ #include <linux/mtd/physmap.h>
+ 
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <mach/hardware.h>
+ #include <asm/setup.h>
+@@ -42,6 +42,7 @@
+ 
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_lcdc.h>
+ #include <mach/at91cap9_matrix.h>
+ #include <mach/at91sam9_smc.h>
+ 
+diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
+index fe5f1d4..7dd7f18 100644
+--- a/arch/arm/mach-at91/board-neocore926.c
++++ b/arch/arm/mach-at91/board-neocore926.c
+@@ -31,7 +31,7 @@
+ #include <linux/gpio_keys.h>
+ #include <linux/input.h>
+ 
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <asm/setup.h>
+ #include <asm/mach-types.h>
+@@ -45,6 +45,7 @@
+ #include <mach/hardware.h>
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_lcdc.h>
+ #include <mach/at91sam9_smc.h>
+ 
+ #include "sam9_smc.h"
+diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
+index 14acc90..b737e59 100644
+--- a/arch/arm/mach-at91/board-sam9261ek.c
++++ b/arch/arm/mach-at91/board-sam9261ek.c
+@@ -33,7 +33,7 @@
+ #include <linux/gpio_keys.h>
+ #include <linux/input.h>
+ 
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <asm/setup.h>
+ #include <asm/mach-types.h>
+@@ -46,6 +46,7 @@
+ #include <mach/hardware.h>
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_lcdc.h>
+ #include <mach/at91sam9_smc.h>
+ #include <mach/at91_shdwc.h>
+ 
+diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
+index bfe490d..3640554 100644
+--- a/arch/arm/mach-at91/board-sam9263ek.c
++++ b/arch/arm/mach-at91/board-sam9263ek.c
+@@ -32,7 +32,7 @@
+ #include <linux/input.h>
+ #include <linux/leds.h>
+ 
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <asm/setup.h>
+ #include <asm/mach-types.h>
+@@ -45,6 +45,7 @@
+ #include <mach/hardware.h>
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_lcdc.h>
+ #include <mach/at91sam9_smc.h>
+ #include <mach/at91_shdwc.h>
+ 
+diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
+index 6c999db..b2b1a8b 100644
+--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
++++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
+@@ -27,7 +27,7 @@
+ #include <linux/atmel-mci.h>
+ 
+ #include <mach/hardware.h>
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <asm/setup.h>
+ #include <asm/mach-types.h>
+@@ -39,6 +39,7 @@
+ 
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_lcdc.h>
+ #include <mach/at91sam9_smc.h>
+ #include <mach/at91_shdwc.h>
+ 
+diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
+index 3bf3408..721186f 100644
+--- a/arch/arm/mach-at91/board-sam9rlek.c
++++ b/arch/arm/mach-at91/board-sam9rlek.c
+@@ -18,7 +18,7 @@
+ #include <linux/input.h>
+ #include <linux/gpio_keys.h>
+ 
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <asm/setup.h>
+ #include <asm/mach-types.h>
+@@ -31,6 +31,7 @@
+ #include <mach/hardware.h>
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_lcdc.h>
+ #include <mach/at91sam9_smc.h>
+ #include <mach/at91_shdwc.h>
+ 
+diff --git a/arch/arm/mach-at91/board-sam9x5cm.c b/arch/arm/mach-at91/board-sam9x5cm.c
+index 4fcc150..53d8046 100644
+--- a/arch/arm/mach-at91/board-sam9x5cm.c
++++ b/arch/arm/mach-at91/board-sam9x5cm.c
+@@ -24,7 +24,7 @@
+ #include <linux/clk.h>
+ #include <mach/cpu.h>
+ 
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <asm/setup.h>
+ #include <asm/mach-types.h>
+diff --git a/arch/arm/mach-at91/board-sam9x5ek.c b/arch/arm/mach-at91/board-sam9x5ek.c
+index d86124c..a005b69 100644
+--- a/arch/arm/mach-at91/board-sam9x5ek.c
++++ b/arch/arm/mach-at91/board-sam9x5ek.c
+@@ -24,8 +24,7 @@
+ #include <linux/clk.h>
+ #include <mach/cpu.h>
+ 
+-#include <video/atmel_lcdc.h>
+-#include <mach/atmel_hlcdfb.h>
++#include <video/atmel_lcdfb.h>
+ 
+ #include <asm/setup.h>
+ #include <asm/mach-types.h>
+@@ -38,6 +37,7 @@
+ #include <mach/hardware.h>
+ #include <mach/board.h>
+ #include <mach/gpio.h>
++#include <mach/atmel_hlcdc.h>
+ #include <mach/at91sam9_smc.h>
+ #include <mach/at91_shdwc.h>
+ 
+diff --git a/arch/arm/mach-at91/include/mach/atmel_hlcdc.h b/arch/arm/mach-at91/include/mach/atmel_hlcdc.h
+new file mode 100644
+index 0000000..0b26f27
+--- /dev/null
++++ b/arch/arm/mach-at91/include/mach/atmel_hlcdc.h
+@@ -0,0 +1,721 @@
++/*
++ *  Header file for AT91 High end LCD Controller
++ *
++ *  Data structure and register user interface
++ *
++ *  Copyright (C) 2010 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PUROFFSETE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#ifndef __MACH_ATMEL_HLCD_H__
++#define __MACH_ATMEL_HLCD_H__
++
++/* Lcdc hardware registers */
++#define ATMEL_LCDC_LCDCFG0	0x0000
++#define LCDC_LCDCFG0_CLKPOL		(0x1 << 0)
++#define LCDC_LCDCFG0_CLKSEL		(0x1 << 2)
++#define LCDC_LCDCFG0_CLKPWMSEL		(0x1 << 3)
++#define LCDC_LCDCFG0_CGDISBASE		(0x1 << 8)
++#define LCDC_LCDCFG0_CGDISOVR1		(0x1 << 9)
++/* XXX: maybe this is 1 << 10? At least the LCD Interrupt registers
++ * use 10 while the documentation specifies 11.
++ */
++#define LCDC_LCDCFG0_CGDISHEO		(0x1 << 11)
++#define LCDC_LCDCFG0_CGDISHCR		(0x1 << 12)
++#define LCDC_LCDCFG0_CLKDIV_OFFSET	16
++#define LCDC_LCDCFG0_CLKDIV		(0xff << LCDC_LCDCFG0_CLKDIV_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG1	0x0004
++#define LCDC_LCDCFG1_HSPW_OFFSET	0
++#define LCDC_LCDCFG1_HSPW		(0x3f << LCDC_LCDCFG1_HSPW_OFFSET)
++#define LCDC_LCDCFG1_VSPW_OFFSET	16
++#define LCDC_LCDCFG1_VSPW		(0x3f << LCDC_LCDCFG1_VSPW_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG2	0x0008
++#define LCDC_LCDCFG2_VFPW_OFFSET	0
++#define LCDC_LCDCFG2_VFPW		(0x3f << LCDC_LCDCFG2_VFPW_OFFSET)
++#define LCDC_LCDCFG2_VBPW_OFFSET	16
++#define LCDC_LCDCFG2_VBPW		(0x3f << LCDC_LCDCFG2_VBPW_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG3	0x000C
++#define LCDC_LCDCFG3_HFPW_OFFSET	0
++#define LCDC_LCDCFG3_HFPW		(0xff << LCDC_LCDCFG3_HFPW_OFFSET)
++#define LCDC_LCDCFG3_HBPW_OFFSET	16
++#define LCDC_LCDCFG3_HBPW		(0xff << LCDC_LCDCFG3_HBPW_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG4	0x0010
++#define LCDC_LCDCFG4_PPL_OFFSET		0
++#define LCDC_LCDCFG4_PPL		(0x7ff << LCDC_LCDCFG4_PPL_OFFSET)
++#define LCDC_LCDCFG4_RPF_OFFSET		16
++#define LCDC_LCDCFG4_RPF		(0x7ff << LCDC_LCDCFG4_RPF_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG5	0x0014
++#define LCDC_LCDCFG5_HSPOL		(0x1 << 0)
++#define LCDC_LCDCFG5_VSPOL		(0x1 << 1)
++#define LCDC_LCDCFG5_VSPDLYS		(0x1 << 2)
++#define LCDC_LCDCFG5_VSPDLYE		(0x1 << 3)
++#define LCDC_LCDCFG5_DISPPOL		(0x1 << 4)
++#define LCDC_LCDCFG5_SERIAL		(0x1 << 5)
++#define LCDC_LCDCFG5_DITHER		(0x1 << 6)
++#define LCDC_LCDCFG5_DISPDLY		(0x1 << 7)
++#define LCDC_LCDCFG5_MODE_OFFSET	8
++#define LCDC_LCDCFG5_MODE		(0x3 << LCDC_LCDCFG5_MODE_OFFSET)
++#define		LCDC_LCDCFG5_MODE_OUTPUT_12BPP		(0x0 << 8)
++#define		LCDC_LCDCFG5_MODE_OUTPUT_16BPP		(0x1 << 8)
++#define		LCDC_LCDCFG5_MODE_OUTPUT_18BPP		(0x2 << 8)
++#define		LCDC_LCDCFG5_MODE_OUTPUT_24BPP		(0x3 << 8)
++#define LCDC_LCDCFG5_VSPSU		(0x1 << 12)
++#define LCDC_LCDCFG5_VSPHO		(0x1 << 13)
++#define LCDC_LCDCFG5_GUARDTIME_OFFSET	16
++#define LCDC_LCDCFG5_GUARDTIME		(0x1f << LCDC_LCDCFG5_GUARDTIME_OFFSET)
++
++#define ATMEL_LCDC_LCDCFG6	0x0018
++#define LCDC_LCDCFG6_PWMPS_OFFSET	0
++#define LCDC_LCDCFG6_PWMPS		(0x7 << LCDC_LCDCFG6_PWMPS_OFFSET)
++#define LCDC_LCDCFG6_PWMPOL		(0x1 << 4)
++#define LCDC_LCDCFG6_PWMCVAL_OFFSET	8
++#define LCDC_LCDCFG6_PWMCVAL		(0xff << LCDC_LCDCFG6_PWMCVAL_OFFSET)
++
++#define ATMEL_LCDC_LCDEN	0x0020
++#define LCDC_LCDEN_CLKEN		(0x1 << 0)
++#define LCDC_LCDEN_SYNCEN		(0x1 << 1)
++#define LCDC_LCDEN_DISPEN		(0x1 << 2)
++#define LCDC_LCDEN_PWMEN		(0x1 << 3)
++
++#define ATMEL_LCDC_LCDDIS	0x0024
++#define LCDC_LCDDIS_CLKDIS		(0x1 << 0)
++#define LCDC_LCDDIS_SYNCDIS		(0x1 << 1)
++#define LCDC_LCDDIS_DISPDIS		(0x1 << 2)
++#define LCDC_LCDDIS_PWMDIS		(0x1 << 3)
++#define LCDC_LCDDIS_CLKRST		(0x1 << 8)
++#define LCDC_LCDDIS_SYNCRST		(0x1 << 9)
++#define LCDC_LCDDIS_DISPRST		(0x1 << 10)
++#define LCDC_LCDDIS_PWMRST		(0x1 << 11)
++
++#define ATMEL_LCDC_LCDSR	0x0028
++#define LCDC_LCDSR_CLKSTS		(0x1 << 0)
++#define LCDC_LCDSR_LCDSTS		(0x1 << 1)
++#define LCDC_LCDSR_DISPSTS		(0x1 << 2)
++#define LCDC_LCDSR_PWMSTS		(0x1 << 3)
++#define LCDC_LCDSR_SIPSTS		(0x1 << 4)
++
++#define ATMEL_LCDC_LCDIER	0x002C
++#define LCDC_LCDIER_SOFIE		(0x1 << 0)
++#define LCDC_LCDIER_DISIE		(0x1 << 1)
++#define LCDC_LCDIER_DISPIE		(0x1 << 2)
++#define LCDC_LCDIER_FIFOERRIE		(0x1 << 4)
++#define LCDC_LCDIER_BASEIE		(0x1 << 8)
++#define LCDC_LCDIER_OVR1IE		(0x1 << 9)
++#define LCDC_LCDIER_HEOIE		(0x1 << 10)
++#define LCDC_LCDIER_HCRIE		(0x1 << 12)
++
++#define ATMEL_LCDC_LCDIDR	0x0030
++#define LCDC_LCDIDR_SOFID		(0x1 << 0)
++#define LCDC_LCDIDR_DISID		(0x1 << 1)
++#define LCDC_LCDIDR_DISPID		(0x1 << 2)
++#define LCDC_LCDIDR_FIFOERRID		(0x1 << 4)
++#define LCDC_LCDIDR_BASEID		(0x1 << 8)
++#define LCDC_LCDIDR_OVR1ID		(0x1 << 9)
++#define LCDC_LCDIDR_HEOID		(0x1 << 10)
++#define LCDC_LCDIDR_HCRID		(0x1 << 12)
++
++#define ATMEL_LCDC_LCDIMR	0x0034
++#define LCDC_LCDIMR_SOFIM		(0x1 << 0)
++#define LCDC_LCDIMR_DISIM		(0x1 << 1)
++#define LCDC_LCDIMR_DISPIM		(0x1 << 2)
++#define LCDC_LCDIMR_FIFOERRIM		(0x1 << 4)
++#define LCDC_LCDIMR_BASEIM		(0x1 << 8)
++#define LCDC_LCDIMR_OVR1IM		(0x1 << 9)
++#define LCDC_LCDIMR_HEOIM		(0x1 << 10)
++#define LCDC_LCDIMR_HCRIM		(0x1 << 12)
++
++#define ATMEL_LCDC_LCDISR	0x0038
++#define LCDC_LCDISR_SOF			(0x1 << 0)
++#define LCDC_LCDISR_DIS			(0x1 << 1)
++#define LCDC_LCDISR_DISP		(0x1 << 2)
++#define LCDC_LCDISR_FIFOERR		(0x1 << 4)
++#define LCDC_LCDISR_BASE		(0x1 << 8)
++#define LCDC_LCDISR_OVR1		(0x1 << 9)
++#define LCDC_LCDISR_HEO			(0x1 << 10)
++#define LCDC_LCDISR_HCR			(0x1 << 12)
++
++#define ATMEL_LCDC_BASECHER	0x0040
++#define LCDC_BASECHER_CHEN		(0x1 << 0)
++#define LCDC_BASECHER_UPDATEEN		(0x1 << 1)
++#define LCDC_BASECHER_A2QEN		(0x1 << 2)
++
++#define ATMEL_LCDC_BASECHDR	0x0044
++#define LCDC_BASECHDR_CHDIS		(0x1 << 0)
++#define LCDC_BASECHDR_CHRST		(0x1 << 8)
++
++#define ATMEL_LCDC_BASECHSR	0x0048
++#define LCDC_BASECHSR_CHSR		(0x1 << 0)
++#define LCDC_BASECHSR_UPDATESR		(0x1 << 1)
++#define LCDC_BASECHSR_A2QSR		(0x1 << 2)
++
++#define ATMEL_LCDC_BASEIER	0x004C
++#define LCDC_BASEIER_DMA		(0x1 << 2)
++#define LCDC_BASEIER_DSCR		(0x1 << 3)
++#define LCDC_BASEIER_ADD		(0x1 << 4)
++#define LCDC_BASEIER_DONE		(0x1 << 5)
++#define LCDC_BASEIER_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_BASEIDR	0x0050
++#define LCDC_BASEIDR_DMA		(0x1 << 2)
++#define LCDC_BASEIDR_DSCR		(0x1 << 3)
++#define LCDC_BASEIDR_ADD		(0x1 << 4)
++#define LCDC_BASEIDR_DONE		(0x1 << 5)
++#define LCDC_BASEIDR_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_BASEIMR	0x0054
++#define LCDC_BASEIMR_DMA		(0x1 << 2)
++#define LCDC_BASEIMR_DSCR		(0x1 << 3)
++#define LCDC_BASEIMR_ADD		(0x1 << 4)
++#define LCDC_BASEIMR_DONE		(0x1 << 5)
++#define LCDC_BASEIMR_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_BASEISR	0x0058
++#define LCDC_BASEISR_DMA		(0x1 << 2)
++#define LCDC_BASEISR_DSCR		(0x1 << 3)
++#define LCDC_BASEISR_ADD		(0x1 << 4)
++#define LCDC_BASEISR_DONE		(0x1 << 5)
++#define LCDC_BASEISR_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_BASEHEAD	0x005C
++
++#define ATMEL_LCDC_BASEADDR	0x0060
++
++#define ATMEL_LCDC_BASECTRL	0x0064
++#define LCDC_BASECTRL_DFETCH		(0x1 << 0)
++#define LCDC_BASECTRL_LFETCH		(0x1 << 1)
++#define LCDC_BASECTRL_DMAIEN		(0x1 << 2)
++#define LCDC_BASECTRL_DSCRIEN		(0x1 << 3)
++#define LCDC_BASECTRL_ADDIEN		(0x1 << 4)
++#define LCDC_BASECTRL_DONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_BASENEXT	0x0068
++
++#define ATMEL_LCDC_BASECFG0	0x006C
++#define LCDC_BASECFG0_BLEN_OFFSET 4
++#define LCDC_BASECFG0_BLEN		(0x3 << LCDC_BASECFG0_BLEN_OFFSET)
++#define		LCDC_BASECFG0_BLEN_AHB_SINGLE		(0x0 << 4)
++#define		LCDC_BASECFG0_BLEN_AHB_INCR4		(0x1 << 4)
++#define		LCDC_BASECFG0_BLEN_AHB_INCR8		(0x2 << 4)
++#define		LCDC_BASECFG0_BLEN_AHB_INCR16		(0x3 << 4)
++#define LCDC_BASECFG0_DLBO		(0x1 << 8)
++
++#define ATMEL_LCDC_BASECFG1	0x0070
++#define LCDC_BASECFG1_CLUTEN		(0x1 << 0)
++#define LCDC_BASECFG1_RGBMODE_OFFSET	4
++#define LCDC_BASECFG1_RGBMODE		(0xf << LCDC_BASECFG1_RGBMODE_OFFSET)
++#define		LCDC_BASECFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
++#define		LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
++#define		LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
++#define		LCDC_BASECFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
++#define		LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
++#define		LCDC_BASECFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
++#define		LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
++#define		LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
++#define		LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
++#define		LCDC_BASECFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
++#define		LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
++#define		LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
++#define		LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
++#define		LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
++#define LCDC_BASECFG1_CLUTMODE_OFFSET	8
++#define LCDC_BASECFG1_CLUTMODE		(0x3 << LCDC_BASECFG1_CLUTMODE_OFFSET)
++#define		LCDC_BASECFG1_CLUTMODE_1BPP		(0x0 << 8)
++#define		LCDC_BASECFG1_CLUTMODE_2BPP		(0x1 << 8)
++#define		LCDC_BASECFG1_CLUTMODE_4BPP		(0x2 << 8)
++#define		LCDC_BASECFG1_CLUTMODE_8BPP		(0x3 << 8)
++
++#define ATMEL_LCDC_BASECFG2	0x0074
++
++#define ATMEL_LCDC_BASECFG3	0x0078
++#define LCDC_BASECFG3_BDEF_OFFSET	0
++#define LCDC_BASECFG3_BDEF		(0xff << LCDC_BASECFG3_BDEF_OFFSET)
++#define LCDC_BASECFG3_GDEF_OFFSET	8
++#define LCDC_BASECFG3_GDEF		(0xff << LCDC_BASECFG3_GDEF_OFFSET)
++#define LCDC_BASECFG3_RDEF_OFFSET	16
++#define LCDC_BASECFG3_RDEF		(0xff << LCDC_BASECFG3_RDEF_OFFSET)
++
++#define ATMEL_LCDC_BASECFG4	0x007C
++#define LCDC_BASECFG4_DMA		(0x1 << 8)
++#define LCDC_BASECFG4_REP		(0x1 << 9)
++
++#define ATMEL_LCDC_HEOCHER	0x0280
++#define LCDC_HEOCHER_CHEN		(0x1 << 0)
++#define LCDC_HEOCHER_UPDATEEN		(0x1 << 1)
++#define LCDC_HEOCHER_A2QEN		(0x1 << 2)
++
++#define ATMEL_LCDC_HEOCHDR	0x0284
++#define LCDC_HEOCHDR_CHDIS		(0x1 << 0)
++#define LCDC_HEOCHDR_CHRST		(0x1 << 8)
++
++#define ATMEL_LCDC_HEOCHSR	0x0288
++#define LCDC_HEOCHSR_CHSR		(0x1 << 0)
++#define LCDC_HEOCHSR_UPDATESR		(0x1 << 1)
++#define LCDC_HEOCHSR_A2QSR		(0x1 << 2)
++
++#define ATMEL_LCDC_HEOIER	0x028C
++#define LCDC_HEOIER_DMA			(0x1 << 2)
++#define LCDC_HEOIER_DSCR		(0x1 << 3)
++#define LCDC_HEOIER_ADD			(0x1 << 4)
++#define LCDC_HEOIER_DONE		(0x1 << 5)
++#define LCDC_HEOIER_OVR			(0x1 << 6)
++#define LCDC_HEOIER_UDMA		(0x1 << 10)
++#define LCDC_HEOIER_UDSCR		(0x1 << 11)
++#define LCDC_HEOIER_UADD		(0x1 << 12)
++#define LCDC_HEOIER_UDONE		(0x1 << 13)
++#define LCDC_HEOIER_UOVR		(0x1 << 14)
++#define LCDC_HEOIER_VDMA		(0x1 << 18)
++#define LCDC_HEOIER_VDSCR		(0x1 << 19)
++#define LCDC_HEOIER_VADD		(0x1 << 20)
++#define LCDC_HEOIER_VDONE		(0x1 << 21)
++#define LCDC_HEOIER_VOVR		(0x1 << 22)
++
++#define ATMEL_LCDC_HEOIDR	0x0290
++#define LCDC_HEOIDR_DMA			(0x1 << 2)
++#define LCDC_HEOIDR_DSCR		(0x1 << 3)
++#define LCDC_HEOIDR_ADD			(0x1 << 4)
++#define LCDC_HEOIDR_DONE		(0x1 << 5)
++#define LCDC_HEOIDR_OVR			(0x1 << 6)
++#define LCDC_HEOIDR_UDMA		(0x1 << 10)
++#define LCDC_HEOIDR_UDSCR		(0x1 << 11)
++#define LCDC_HEOIDR_UADD		(0x1 << 12)
++#define LCDC_HEOIDR_UDONE		(0x1 << 13)
++#define LCDC_HEOIDR_UOVR		(0x1 << 14)
++#define LCDC_HEOIDR_VDMA		(0x1 << 18)
++#define LCDC_HEOIDR_VDSCR		(0x1 << 19)
++#define LCDC_HEOIDR_VADD		(0x1 << 20)
++#define LCDC_HEOIDR_VDONE		(0x1 << 21)
++#define LCDC_HEOIDR_VOVR		(0x1 << 22)
++
++#define ATMEL_LCDC_HEOIMR	0x0294
++#define LCDC_HEOIMR_DMA			(0x1 << 2)
++#define LCDC_HEOIMR_DSCR		(0x1 << 3)
++#define LCDC_HEOIMR_ADD			(0x1 << 4)
++#define LCDC_HEOIMR_DONE		(0x1 << 5)
++#define LCDC_HEOIMR_OVR			(0x1 << 6)
++#define LCDC_HEOIMR_UDMA		(0x1 << 10)
++#define LCDC_HEOIMR_UDSCR		(0x1 << 11)
++#define LCDC_HEOIMR_UADD		(0x1 << 12)
++#define LCDC_HEOIMR_UDONE		(0x1 << 13)
++#define LCDC_HEOIMR_UOVR		(0x1 << 14)
++#define LCDC_HEOIMR_VDMA		(0x1 << 18)
++#define LCDC_HEOIMR_VDSCR		(0x1 << 19)
++#define LCDC_HEOIMR_VADD		(0x1 << 20)
++#define LCDC_HEOIMR_VDONE		(0x1 << 21)
++#define LCDC_HEOIMR_VOVR		(0x1 << 22)
++
++#define ATMEL_LCDC_HEOISR	0x0298
++#define LCDC_HEOISR_DMA			(0x1 << 2)
++#define LCDC_HEOISR_DSCR		(0x1 << 3)
++#define LCDC_HEOISR_ADD			(0x1 << 4)
++#define LCDC_HEOISR_DONE		(0x1 << 5)
++#define LCDC_HEOISR_OVR			(0x1 << 6)
++#define LCDC_HEOISR_UDMA		(0x1 << 10)
++#define LCDC_HEOISR_UDSCR		(0x1 << 11)
++#define LCDC_HEOISR_UADD		(0x1 << 12)
++#define LCDC_HEOISR_UDONE		(0x1 << 13)
++#define LCDC_HEOISR_UOVR		(0x1 << 14)
++#define LCDC_HEOISR_VDMA		(0x1 << 18)
++#define LCDC_HEOISR_VDSCR		(0x1 << 19)
++#define LCDC_HEOISR_VADD		(0x1 << 20)
++#define LCDC_HEOISR_VDONE		(0x1 << 21)
++#define LCDC_HEOISR_VOVR		(0x1 << 22)
++
++#define ATMEL_LCDC_HEOHEAD	0x029C
++
++#define ATMEL_LCDC_HEOADDR	0x02A0
++
++#define ATMEL_LCDC_HEOCTRL	0x02A4
++#define LCDC_HEOCTRL_DFETCH		(0x1 << 0)
++#define LCDC_HEOCTRL_LFETCH		(0x1 << 1)
++#define LCDC_HEOCTRL_DMAIEN		(0x1 << 2)
++#define LCDC_HEOCTRL_DSCRIEN		(0x1 << 3)
++#define LCDC_HEOCTRL_ADDIEN		(0x1 << 4)
++#define LCDC_HEOCTRL_DONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_HEONEXT	0x02A8
++
++#define ATMEL_LCDC_HEOUHEAD	0x02AC
++
++#define ATMEL_LCDC_HEOUADDR	0x02B0
++
++#define ATMEL_LCDC_HEOUCTRL	0x02B4
++#define LCDC_HEOUCTRL_UDFETCH		(0x1 << 0)
++#define LCDC_HEOUCTRL_UDMAIEN		(0x1 << 2)
++#define LCDC_HEOUCTRL_UDSCRIEN		(0x1 << 3)
++#define LCDC_HEOUCTRL_UADDIEN		(0x1 << 4)
++#define LCDC_HEOUCTRL_UDONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_HEOUNEXT	0x02B8
++
++#define ATMEL_LCDC_HEOVHEAD	0x02BC
++
++#define ATMEL_LCDC_HEOVADDR	0x02C0
++
++#define ATMEL_LCDC_HEOVCTRL	0x02C4
++#define LCDC_HEOVCTRL_VDFETCH		(0x1 << 0)
++#define LCDC_HEOVCTRL_VDMAIEN		(0x1 << 2)
++#define LCDC_HEOVCTRL_VDSCRIEN		(0x1 << 3)
++#define LCDC_HEOVCTRL_VADDIEN		(0x1 << 4)
++#define LCDC_HEOVCTRL_VDONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_HEOVNEXT	0x02C8
++
++#define ATMEL_LCDC_HEOCFG0	0x02CC
++#define LCDC_HEOCFG0_BLEN_OFFSET	4
++#define LCDC_HEOCFG0_BLEN		(0x3 << LCDC_HEOCFG0_BLEN_OFFSET)
++#define		LCDC_HEOCFG0_BLEN_AHB_SINGLE		(0x0 << 4)
++#define		LCDC_HEOCFG0_BLEN_AHB_INCR4		(0x1 << 4)
++#define		LCDC_HEOCFG0_BLEN_AHB_INCR8		(0x2 << 4)
++#define		LCDC_HEOCFG0_BLEN_AHB_INCR16		(0x3 << 4)
++#define LCDC_HEOCFG0_BLENUV_OFFSET	6
++#define LCDC_HEOCFG0_BLENUV		(0x3 << LCDC_HEOCFG0_BLENUV_OFFSET)
++#define		LCDC_HEOCFG0_BLENUV_AHB_SINGLE		(0x0 << 6)
++#define		LCDC_HEOCFG0_BLENUV_AHB_INCR4		(0x1 << 6)
++#define		LCDC_HEOCFG0_BLENUV_AHB_INCR8		(0x2 << 6)
++#define		LCDC_HEOCFG0_BLENUV_AHB_INCR16		(0x3 << 6)
++#define LCDC_HEOCFG0_DLBO		(0x1 << 8)
++#define LCDC_HEOCFG0_ROTDIS		(0x1 << 12)
++#define LCDC_HEOCFG0_LOCKDIS		(0x1 << 13)
++
++#define ATMEL_LCDC_HEOCFG1	0x02D0
++#define LCDC_HEOCFG1_CLUTEN		(0x1 << 0)
++#define LCDC_HEOCFG1_YUVEN		(0x1 << 1)
++#define LCDC_HEOCFG1_RGBMODE_OFFSET	4
++#define LCDC_HEOCFG1_RGBMODE		(0xf << LCDC_HEOCFG1_RGBMODE_OFFSET)
++#define		LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
++#define		LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
++#define		LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
++#define		LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
++#define		LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
++#define LCDC_HEOCFG1_CLUTMODE_OFFSET	8
++#define LCDC_HEOCFG1_CLUTMODE		(0x3 << LCDC_HEOCFG1_CLUTMODE_OFFSET)
++#define		LCDC_HEOCFG1_CLUTMODE_1BPP		(0x0 << 8)
++#define		LCDC_HEOCFG1_CLUTMODE_2BPP		(0x1 << 8)
++#define		LCDC_HEOCFG1_CLUTMODE_4BPP		(0x2 << 8)
++#define		LCDC_HEOCFG1_CLUTMODE_8BPP		(0x3 << 8)
++#define LCDC_HEOCFG1_YUVMODE_OFFSET	12
++#define LCDC_HEOCFG1_YUVMODE		(0xf << LCDC_HEOCFG1_YUVMODE_OFFSET)
++#define		LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR	(0x0 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0	(0x1 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1	(0x2 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2	(0x3 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3	(0x4 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR	(0x5 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR	(0x6 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR	(0x7 << 12)
++#define		LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR	(0x8 << 12)
++#define LCDC_HEOCFG1_YUV422ROT		(0x1 << 16)
++#define LCDC_HEOCFG1_YUV422SWP		(0x1 << 17)
++
++#define ATMEL_LCDC_HEOCFG2	0x02D4
++#define LCDC_HEOCFG2_XOFFSET_OFFSET	0
++#define LCDC_HEOCFG2_XOFFSET		(0x7ff << LCDC_HEOCFG2_XOFFSET_OFFSET)
++#define LCDC_HEOCFG2_YOFFSET_OFFSET	16
++#define LCDC_HEOCFG2_YOFFSET		(0x7ff << LCDC_HEOCFG2_YOFFSET_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG3	0x02D8
++#define LCDC_HEOCFG3_XSIZE_OFFSET	0
++#define LCDC_HEOCFG3_XSIZE		(0x7ff << LCDC_HEOCFG3_XSIZE_OFFSET)
++#define LCDC_HEOCFG3_YSIZE_OFFSET	16
++#define LCDC_HEOCFG3_YSIZE		(0x7ff << LCDC_HEOCFG3_YSIZE_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG4	0x02DC
++#define LCDC_HEOCFG4_XMEM_SIZE_OFFSET	0
++#define LCDC_HEOCFG4_XMEM_SIZE		(0x7ff << LCDC_HEOCFG4_XMEM_SIZE_OFFSET)
++#define LCDC_HEOCFG4_YMEM_SIZE_OFFSET	16
++#define LCDC_HEOCFG4_YMEM_SIZE		(0x7ff << LCDC_HEOCFG4_YMEM_SIZE_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG5	0x02E0
++
++#define ATMEL_LCDC_HEOCFG6	0x02E4
++
++#define ATMEL_LCDC_HEOCFG7	0x02E8
++
++#define ATMEL_LCDC_HEOCFG8	0x02EC
++
++#define ATMEL_LCDC_HEOCFG9	0x02F0
++#define LCDC_HEOCFG9_BDEF_OFFSET	0
++#define LCDC_HEOCFG9_BDEF		(0xff << LCDC_HEOCFG9_BDEF_OFFSET)
++#define LCDC_HEOCFG9_GDEF_OFFSET	8
++#define LCDC_HEOCFG9_GDEF		(0xff << LCDC_HEOCFG9_GDEF_OFFSET)
++#define LCDC_HEOCFG9_RDEF_OFFSET	16
++#define LCDC_HEOCFG9_RDEF		(0xff << LCDC_HEOCFG9_RDEF_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG10	0x02F4
++#define LCDC_HEOCFG10_BKEY_OFFSET	0
++#define LCDC_HEOCFG10_BKEY		(0xff << LCDC_HEOCFG10_BKEY_OFFSET)
++#define LCDC_HEOCFG10_GKEY_OFFSET	8
++#define LCDC_HEOCFG10_GKEY		(0xff << LCDC_HEOCFG10_GKEY_OFFSET)
++#define LCDC_HEOCFG10_RKEY_OFFSET	16
++#define LCDC_HEOCFG10_RKEY		(0xff << LCDC_HEOCFG10_RKEY_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG11	0x02F8
++#define LCDC_HEOCFG11_BMASK_OFFSET	0
++#define LCDC_HEOCFG11_BMASK		(0xff << LCDC_HEOCFG11_BMASK_OFFSET)
++#define LCDC_HEOCFG11_GMASK_OFFSET	8
++#define LCDC_HEOCFG11_GMASK		(0xff << LCDC_HEOCFG11_GMASK_OFFSET)
++#define LCDC_HEOCFG11_RMASK_OFFSET	16
++#define LCDC_HEOCFG11_RMASK		(0xff << LCDC_HEOCFG11_RMASK_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG12	0x02FC
++#define LCDC_HEOCFG12_CRKEY		(0x1 << 0)
++#define LCDC_HEOCFG12_INV		(0x1 << 1)
++#define LCDC_HEOCFG12_ITER2BL		(0x1 << 2)
++#define LCDC_HEOCFG12_ITER		(0x1 << 3)
++#define LCDC_HEOCFG12_REVALPHA		(0x1 << 4)
++#define LCDC_HEOCFG12_GAEN		(0x1 << 5)
++#define LCDC_HEOCFG12_LAEN		(0x1 << 6)
++#define LCDC_HEOCFG12_OVR		(0x1 << 7)
++#define LCDC_HEOCFG12_DMA		(0x1 << 8)
++#define LCDC_HEOCFG12_REP		(0x1 << 9)
++#define LCDC_HEOCFG12_DSTKEY		(0x1 << 10)
++#define LCDC_HEOCFG12_VIDPRI		(0x1 << 12)
++#define LCDC_HEOCFG12_GA_OFFSET		16
++#define LCDC_HEOCFG12_GA		(0xff << LCDC_HEOCFG12_GA_OFFSET)
++
++#define ATMEL_LCDC_HEOCFG13	0x0300
++#define LCDC_HEOCFG13_XFACTOR_OFFSET	0
++#define LCDC_HEOCFG13_XFACTOR		(0x1fff << LCDC_HEOCFG13_XFACTOR_OFFSET)
++#define LCDC_HEOCFG13_YFACTOR_OFFSET	16
++#define LCDC_HEOCFG13_YFACTOR		(0x1fff << LCDC_HEOCFG13_YFACTOR_OFFSET)
++#define LCDC_HEOCFG13_SCALEN		(0x1 << 31)
++
++#define ATMEL_LCDC_HEOCFG14	0x0304
++#define LCDC_HEOCFG14_CSCRY_OFFSET	0
++#define LCDC_HEOCFG14_CSCRY		(0x3ff << LCDC_HEOCFG14_CSCRY_OFFSET)
++#define LCDC_HEOCFG14_CSCRU_OFFSET	10
++#define LCDC_HEOCFG14_CSCRU		(0x3ff << LCDC_HEOCFG14_CSCRU_OFFSET)
++#define LCDC_HEOCFG14_CSCRV_OFFSET	20
++#define LCDC_HEOCFG14_CSCRV		(0x3ff << LCDC_HEOCFG14_CSCRV_OFFSET)
++#define LCDC_HEOCFG14_CSCYOFF		(0x1 << 30)
++
++#define ATMEL_LCDC_HEOCFG15	0x0308
++#define LCDC_HEOCFG15_CSCGY_OFFSET	0
++#define LCDC_HEOCFG15_CSCGY		(0x3ff << LCDC_HEOCFG15_CSCGY_OFFSET)
++#define LCDC_HEOCFG15_CSCGU_OFFSET	10
++#define LCDC_HEOCFG15_CSCGU		(0x3ff << LCDC_HEOCFG15_CSCGU_OFFSET)
++#define LCDC_HEOCFG15_CSCGV_OFFSET	20
++#define LCDC_HEOCFG15_CSCGV		(0x3ff << LCDC_HEOCFG15_CSCGV_OFFSET)
++#define LCDC_HEOCFG15_CSCUOFF		(0x1 << 30)
++
++#define ATMEL_LCDC_HEOCFG16	0x030C
++#define LCDC_HEOCFG16_CSCBY_OFFSET	0
++#define LCDC_HEOCFG16_CSCBY		(0x3ff << LCDC_HEOCFG16_CSCBY_OFFSET)
++#define LCDC_HEOCFG16_CSCBU_OFFSET	10
++#define LCDC_HEOCFG16_CSCBU		(0x3ff << LCDC_HEOCFG16_CSCBU_OFFSET)
++#define LCDC_HEOCFG16_CSCBV_OFFSET	20
++#define LCDC_HEOCFG16_CSCBV		(0x3ff << LCDC_HEOCFG16_CSCBV_OFFSET)
++#define LCDC_HEOCFG16_CSCVOFF		(0x1 << 30)
++
++#define ATMEL_LCDC_HCRCHER	0x0340
++#define LCDC_HCRCHER_CHEN		(0x1 << 0)
++#define LCDC_HCRCHER_UPDATEEN		(0x1 << 1)
++#define LCDC_HCRCHER_A2QEN		(0x1 << 2)
++
++#define ATMEL_LCDC_HCRCHDR	0x0344
++#define LCDC_HCRCHDR_CHDIS		(0x1 << 0)
++#define LCDC_HCRCHDR_CHRST		(0x1 << 8)
++
++#define ATMEL_LCDC_HCRCHSR	0x0348
++#define LCDC_HCRCHSR_CHSR		(0x1 << 0)
++#define LCDC_HCRCHSR_UPDATESR		(0x1 << 1)
++#define LCDC_HCRCHSR_A2QSR		(0x1 << 2)
++
++#define ATMEL_LCDC_HCRIER	0x034C
++#define LCDC_HCRIER_DMA			(0x1 << 2)
++#define LCDC_HCRIER_DSCR		(0x1 << 3)
++#define LCDC_HCRIER_ADD			(0x1 << 4)
++#define LCDC_HCRIER_DONE		(0x1 << 5)
++#define LCDC_HCRIER_OVR			(0x1 << 6)
++
++#define ATMEL_LCDC_HCRIDR	0x0350
++#define LCDC_HCRIDR_DMA			(0x1 << 2)
++#define LCDC_HCRIDR_DSCR		(0x1 << 3)
++#define LCDC_HCRIDR_ADD			(0x1 << 4)
++#define LCDC_HCRIDR_DONE		(0x1 << 5)
++#define LCDC_HCRIDR_OVR			(0x1 << 6)
++
++#define ATMEL_LCDC_HCRIMR	0x0354
++#define LCDC_HCRIMR_DMA			(0x1 << 2)
++#define LCDC_HCRIMR_DSCR		(0x1 << 3)
++#define LCDC_HCRIMR_ADD			(0x1 << 4)
++#define LCDC_HCRIMR_DONE		(0x1 << 5)
++#define LCDC_HCRIMR_OVR			(0x1 << 6)
++
++#define ATMEL_LCDC_HCRISR	0x0358
++#define LCDC_HCRISR_DMA			(0x1 << 2)
++#define LCDC_HCRISR_DSCR		(0x1 << 3)
++#define LCDC_HCRISR_ADD			(0x1 << 4)
++#define LCDC_HCRISR_DONE		(0x1 << 5)
++#define LCDC_HCRISR_OVR			(0x1 << 6)
++
++#define ATMEL_LCDC_HCRHEAD	0x035C
++
++#define ATMEL_LCDC_HCRADDR	0x0360
++
++#define ATMEL_LCDC_HCRCTRL	0x0364
++#define LCDC_HCRCTRL_DFETCH		(0x1 << 0)
++#define LCDC_HCRCTRL_LFETCH		(0x1 << 1)
++#define LCDC_HCRCTRL_DMAIEN		(0x1 << 2)
++#define LCDC_HCRCTRL_DSCRIEN		(0x1 << 3)
++#define LCDC_HCRCTRL_ADDIEN		(0x1 << 4)
++#define LCDC_HCRCTRL_DONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_HCRNEXT	0x0368
++
++#define ATMEL_LCDC_HCRCFG0	0x036C
++#define LCDC_HCRCFG0_BLEN_OFFSET	4
++#define LCDC_HCRCFG0_BLEN		(0x3 << LCDC_HCRCFG0_BLEN_OFFSET)
++#define		LCDC_HCRCFG0_BLEN_AHB_SINGLE		(0x0 << 4)
++#define		LCDC_HCRCFG0_BLEN_AHB_INCR4		(0x1 << 4)
++#define		LCDC_HCRCFG0_BLEN_AHB_INCR8		(0x2 << 4)
++#define		LCDC_HCRCFG0_BLEN_AHB_INCR16		(0x3 << 4)
++#define LCDC_HCRCFG0_DLBO		(0x1 << 8)
++
++#define ATMEL_LCDC_HCRCFG1	0x0370
++#define LCDC_HCRCFG1_CLUTEN		(0x1 << 0)
++#define LCDC_HCRCFG1_RGBMODE_OFFSET	4
++#define LCDC_HCRCFG1_RGBMODE		(0xf << LCDC_HCRCFG1_RGBMODE_OFFSET)
++#define		LCDC_HCRCFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
++#define		LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
++#define		LCDC_HCRCFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
++#define		LCDC_HCRCFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
++#define		LCDC_HCRCFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
++#define LCDC_HCRCFG1_CLUTMODE_OFFSET	8
++#define LCDC_HCRCFG1_CLUTMODE		(0x3 << LCDC_HCRCFG1_CLUTMODE_OFFSET)
++#define		LCDC_HCRCFG1_CLUTMODE_1BPP		(0x0 << 8)
++#define		LCDC_HCRCFG1_CLUTMODE_2BPP		(0x1 << 8)
++#define		LCDC_HCRCFG1_CLUTMODE_4BPP		(0x2 << 8)
++#define		LCDC_HCRCFG1_CLUTMODE_8BPP		(0x3 << 8)
++
++#define ATMEL_LCDC_HCRCFG2	0x0374
++#define LCDC_HCRCFG2_XOFFSET_OFFSET	0
++#define LCDC_HCRCFG2_XOFFSET		(0x7ff << LCDC_HCRCFG2_XOFFSET_OFFSET)
++#define LCDC_HCRCFG2_YOFFSET_OFFSET	16
++#define LCDC_HCRCFG2_YOFFSET		(0x7ff << LCDC_HCRCFG2_YOFFSET_OFFSET)
++
++#define ATMEL_LCDC_HCRCFG3	0x0378
++#define LCDC_HCRCFG3_XSIZE_OFFSET	0
++#define LCDC_HCRCFG3_XSIZE		(0x7f << LCDC_HCRCFG3_XSIZE_OFFSET)
++#define LCDC_HCRCFG3_YSIZE_OFFSET	16
++#define LCDC_HCRCFG3_YSIZE		(0x7f << LCDC_HCRCFG3_YSIZE_OFFSET)
++
++#define ATMEL_LCDC_HCRCFG4	0x037C
++
++#define ATMEL_LCDC_HCRCFG6	0x0384
++#define LCDC_HCRCFG6_BDEF_OFFSET	0
++#define LCDC_HCRCFG6_BDEF		(0xff << LCDC_HCRCFG6_BDEF_OFFSET)
++#define LCDC_HCRCFG6_GDEF_OFFSET	8
++#define LCDC_HCRCFG6_GDEF		(0xff << LCDC_HCRCFG6_GDEF_OFFSET)
++#define LCDC_HCRCFG6_RDEF_OFFSET	16
++#define LCDC_HCRCFG6_RDEF		(0xff << LCDC_HCRCFG6_RDEF_OFFSET)
++
++#define ATMEL_LCDC_HCRCFG7	0x0388
++#define LCDC_HCRCFG7_BKEY_OFFSET	0
++#define LCDC_HCRCFG7_BKEY		(0xff << LCDC_HCRCFG7_BKEY_OFFSET)
++#define LCDC_HCRCFG7_GKEY_OFFSET	8
++#define LCDC_HCRCFG7_GKEY		(0xff << LCDC_HCRCFG7_GKEY_OFFSET)
++#define LCDC_HCRCFG7_RKEY_OFFSET	16
++#define LCDC_HCRCFG7_RKEY		(0xff << LCDC_HCRCFG7_RKEY_OFFSET)
++
++#define ATMEL_LCDC_HCRCFG8	0x038C
++#define LCDC_HCRCFG8_BMASK_OFFSET	0
++#define LCDC_HCRCFG8_BMASK		(0xff << LCDC_HCRCFG8_BMASK_OFFSET)
++#define LCDC_HCRCFG8_GMASK_OFFSET	8
++#define LCDC_HCRCFG8_GMASK		(0xff << LCDC_HCRCFG8_GMASK_OFFSET)
++#define LCDC_HCRCFG8_RMASK_OFFSET	16
++#define LCDC_HCRCFG8_RMASK		(0xff << LCDC_HCRCFG8_RMASK_OFFSET)
++
++#define ATMEL_LCDC_HCRCFG9	0x0390
++#define LCDC_HCRCFG9_CRKEY		(0x1 << 0)
++#define LCDC_HCRCFG9_INV		(0x1 << 1)
++#define LCDC_HCRCFG9_ITER2BL		(0x1 << 2)
++#define LCDC_HCRCFG9_ITER		(0x1 << 3)
++#define LCDC_HCRCFG9_REVALPHA		(0x1 << 4)
++#define LCDC_HCRCFG9_GAEN		(0x1 << 5)
++#define LCDC_HCRCFG9_LAEN		(0x1 << 6)
++#define LCDC_HCRCFG9_OVR		(0x1 << 7)
++#define LCDC_HCRCFG9_DMA		(0x1 << 8)
++#define LCDC_HCRCFG9_REP		(0x1 << 9)
++#define LCDC_HCRCFG9_DSTKEY		(0x1 << 10)
++#define LCDC_HCRCFG9_GA_OFFSET		16
++#define LCDC_HCRCFG9_GA_Msk		(0xff << LCDC_HCRCFG9_GA_OFFSET)
++
++#define ATMEL_LCDC_BASECLUT	0x400
++#define LCDC_BASECLUT_BCLUT_OFFSET	0
++#define LCDC_BASECLUT_BCLUT		(0xff << LCDC_BASECLUT_BCLUT_OFFSET)
++#define LCDC_BASECLUT_GCLUT_OFFSET	8
++#define LCDC_BASECLUT_GCLUT		(0xff << LCDC_BASECLUT_GCLUT_OFFSET)
++#define LCDC_BASECLUT_RCLUT_OFFSET	16
++#define LCDC_BASECLUT_RCLUT		(0xff << LCDC_BASECLUT_RCLUT_OFFSET)
++
++#define ATMEL_LCDC_OVR1CLUT	0x800
++#define LCDC_OVR1CLUT_BCLUT_OFFSET	0
++#define LCDC_OVR1CLUT_BCLUT		(0xff << LCDC_OVR1CLUT_BCLUT_OFFSET)
++#define LCDC_OVR1CLUT_GCLUT_OFFSET	8
++#define LCDC_OVR1CLUT_GCLUT		(0xff << LCDC_OVR1CLUT_GCLUT_OFFSET)
++#define LCDC_OVR1CLUT_RCLUT_OFFSET	16
++#define LCDC_OVR1CLUT_RCLUT		(0xff << LCDC_OVR1CLUT_RCLUT_OFFSET)
++#define LCDC_OVR1CLUT_ACLUT_OFFSET	24
++#define LCDC_OVR1CLUT_ACLUT		(0xff << LCDC_OVR1CLUT_ACLUT_OFFSET)
++
++#define ATMEL_LCDC_HEOCLUT	0x1000
++#define LCDC_HEOCLUT_BCLUT_OFFSET	0
++#define LCDC_HEOCLUT_BCLUT		(0xff << LCDC_HEOCLUT_BCLUT_OFFSET)
++#define LCDC_HEOCLUT_GCLUT_OFFSET	8
++#define LCDC_HEOCLUT_GCLUT		(0xff << LCDC_HEOCLUT_GCLUT_OFFSET)
++#define LCDC_HEOCLUT_RCLUT_OFFSET	16
++#define LCDC_HEOCLUT_RCLUT		(0xff << LCDC_HEOCLUT_RCLUT_OFFSET)
++#define LCDC_HEOCLUT_ACLUT_OFFSET	24
++#define LCDC_HEOCLUT_ACLUT		(0xff << LCDC_HEOCLUT_ACLUT_OFFSET)
++
++#define ATMEL_LCDC_HCRCLUT	0x1400
++#define LCDC_HCRCLUT_BCLUT_OFFSET	0
++#define LCDC_HCRCLUT_BCLUT		(0xff << LCDC_HCRCLUT_BCLUT_OFFSET)
++#define LCDC_HCRCLUT_GCLUT_OFFSET	8
++#define LCDC_HCRCLUT_GCLUT		(0xff << LCDC_HCRCLUT_GCLUT_OFFSET)
++#define LCDC_HCRCLUT_RCLUT_OFFSET	16
++#define LCDC_HCRCLUT_RCLUT		(0xff << LCDC_HCRCLUT_RCLUT_OFFSET)
++#define LCDC_HCRCLUT_ACLUT_OFFSET	24
++#define LCDC_HCRCLUT_ACLUT		(0xff << LCDC_HCRCLUT_ACLUT_OFFSET)
++
++/* Base layer CLUT */
++#define ATMEL_HLCDC_LUT			0x0400
++
++
++#endif /* __MACH_ATMEL_HLCDC4_H__ */
+diff --git a/arch/arm/mach-at91/include/mach/atmel_hlcdc_ovl.h b/arch/arm/mach-at91/include/mach/atmel_hlcdc_ovl.h
+new file mode 100644
+index 0000000..4416403
+--- /dev/null
++++ b/arch/arm/mach-at91/include/mach/atmel_hlcdc_ovl.h
+@@ -0,0 +1,156 @@
++#ifndef __MACH_ATMEL_HLCD_OVL_H__
++#define __MACH_ATMEL_HLCD_OVL_H__
++
++/*
++ * OVL has a seperate resource which already starts at offset 0x100.
++ * So, these defines start at 0x0. The manual will list them at 0x100.
++ */
++
++#define ATMEL_LCDC_OVRCHER1	0x0000
++#define LCDC_OVRCHER1_CHEN		(0x1 << 0)
++#define LCDC_OVRCHER1_UPDATEEN		(0x1 << 1)
++#define LCDC_OVRCHER1_A2QEN		(0x1 << 2)
++
++#define ATMEL_LCDC_OVRCHDR1	0x0004
++#define LCDC_OVRCHDR1_CHDIS		(0x1 << 0)
++#define LCDC_OVRCHDR1_CHRST		(0x1 << 8)
++
++#define ATMEL_LCDC_OVRCHSR1	0x0008
++#define LCDC_OVRCHSR1_CHSR		(0x1 << 0)
++#define LCDC_OVRCHSR1_UPDATESR		(0x1 << 1)
++#define LCDC_OVRCHSR1_A2QSR		(0x1 << 2)
++
++#define ATMEL_LCDC_OVRIER1	0x000C
++#define LCDC_OVRIER1_DMA		(0x1 << 2)
++#define LCDC_OVRIER1_DSCR		(0x1 << 3)
++#define LCDC_OVRIER1_ADD		(0x1 << 4)
++#define LCDC_OVRIER1_DONE		(0x1 << 5)
++#define LCDC_OVRIER1_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_OVRIDR1	0x0010
++#define LCDC_OVRIDR1_DMA		(0x1 << 2)
++#define LCDC_OVRIDR1_DSCR		(0x1 << 3)
++#define LCDC_OVRIDR1_ADD		(0x1 << 4)
++#define LCDC_OVRIDR1_DONE		(0x1 << 5)
++#define LCDC_OVRIDR1_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_OVRIMR1	0x0014
++#define LCDC_OVRIMR1_DMA		(0x1 << 2)
++#define LCDC_OVRIMR1_DSCR		(0x1 << 3)
++#define LCDC_OVRIMR1_ADD		(0x1 << 4)
++#define LCDC_OVRIMR1_DONE		(0x1 << 5)
++#define LCDC_OVRIMR1_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_OVRISR1	0x0018
++#define LCDC_OVRISR1_DMA		(0x1 << 2)
++#define LCDC_OVRISR1_DSCR		(0x1 << 3)
++#define LCDC_OVRISR1_ADD		(0x1 << 4)
++#define LCDC_OVRISR1_DONE		(0x1 << 5)
++#define LCDC_OVRISR1_OVR		(0x1 << 6)
++
++#define ATMEL_LCDC_OVRHEAD1	0x001C
++
++#define ATMEL_LCDC_OVRADDR1	0x0020
++
++#define ATMEL_LCDC_OVRCTRL1	0x0024
++#define LCDC_OVRCTRL1_DFETCH		(0x1 << 0)
++#define LCDC_OVRCTRL1_LFETCH		(0x1 << 1)
++#define LCDC_OVRCTRL1_DMAIEN		(0x1 << 2)
++#define LCDC_OVRCTRL1_DSCRIEN		(0x1 << 3)
++#define LCDC_OVRCTRL1_ADDIEN		(0x1 << 4)
++#define LCDC_OVRCTRL1_DONEIEN		(0x1 << 5)
++
++#define ATMEL_LCDC_OVRNEXT1	0x0028
++
++#define ATMEL_LCDC_OVR1CFG0	0x002C
++#define LCDC_OVR1CFG0_BLEN_OFFSET	4
++#define LCDC_OVR1CFG0_BLEN		(0x3 << LCDC_OVR1CFG0_BLEN_OFFSET)
++#define		LCDC_OVR1CFG0_BLEN_AHB_SINGLE		(0x0 << 4)
++#define		LCDC_OVR1CFG0_BLEN_AHB_INCR4		(0x1 << 4)
++#define		LCDC_OVR1CFG0_BLEN_AHB_INCR8		(0x2 << 4)
++#define		LCDC_OVR1CFG0_BLEN_AHB_INCR16		(0x3 << 4)
++#define LCDC_OVR1CFG0_DLBO		(0x1 << 8)
++#define LCDC_OVR1CFG0_ROTDIS		(0x1 << 12)
++#define LCDC_OVR1CFG0_LOCKDIS		(0x1 << 13)
++
++#define ATMEL_LCDC_OVR1CFG1	0x0030
++#define LCDC_OVR1CFG1_CLUTEN		(0x1 << 0)
++#define LCDC_OVR1CFG1_RGBMODE_OFFSET	4
++#define LCDC_OVR1CFG1_RGBMODE		(0xf << LCDC_OVR1CFG1_RGBMODE_OFFSET)
++#define		LCDC_OVR1CFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
++#define		LCDC_OVR1CFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
++#define LCDC_OVR1CFG1_CLUTMODE_OFFSET	8
++#define LCDC_OVR1CFG1_CLUTMODE		(0x3 << LCDC_OVR1CFG1_CLUTMODE_OFFSET)
++#define		LCDC_OVR1CFG1_CLUTMODE_1BPP		(0x0 << 8)
++#define		LCDC_OVR1CFG1_CLUTMODE_2BPP		(0x1 << 8)
++#define		LCDC_OVR1CFG1_CLUTMODE_4BPP		(0x2 << 8)
++#define		LCDC_OVR1CFG1_CLUTMODE_8BPP		(0x3 << 8)
++
++#define ATMEL_LCDC_OVR1CFG2	0x0034
++#define LCDC_OVR1CFG2_XOFFSET_OFFSET	0
++#define LCDC_OVR1CFG2_XOFFSET		(0x7ff << LCDC_OVR1CFG2_XOFFSET_OFFSET)
++#define LCDC_OVR1CFG2_YOFFSET_OFFSET	16
++#define LCDC_OVR1CFG2_YOFFSET		(0x7ff << LCDC_OVR1CFG2_YOFFSET_OFFSET)
++
++#define ATMEL_LCDC_OVR1CFG3	0x0038
++#define LCDC_OVR1CFG3_XSIZE_OFFSET	0
++#define LCDC_OVR1CFG3_XSIZE		(0x7ff << LCDC_OVR1CFG3_XSIZE_OFFSET)
++#define LCDC_OVR1CFG3_YSIZE_OFFSET	16
++#define LCDC_OVR1CFG3_YSIZE		(0x7ff << LCDC_OVR1CFG3_YSIZE_OFFSET)
++
++#define ATMEL_LCDC_OVR1CFG4	0x003C
++
++#define ATMEL_LCDC_OVR1CFG5	0x0040
++
++#define ATMEL_LCDC_OVR1CFG6	0x0044
++#define LCDC_OVR1CFG6_BDEF_OFFSET	0
++#define LCDC_OVR1CFG6_BDEF		(0xff << LCDC_OVR1CFG6_BDEF_OFFSET)
++#define LCDC_OVR1CFG6_GDEF_OFFSET	8
++#define LCDC_OVR1CFG6_GDEF		(0xff << LCDC_OVR1CFG6_GDEF_OFFSET)
++#define LCDC_OVR1CFG6_RDEF_OFFSET	16
++#define LCDC_OVR1CFG6_RDEF		(0xff << LCDC_OVR1CFG6_RDEF_OFFSET)
++
++#define ATMEL_LCDC_OVR1CFG7	0x0048
++#define LCDC_OVR1CFG7_BKEY_OFFSET	0
++#define LCDC_OVR1CFG7_BKEY		(0xff << LCDC_OVR1CFG7_BKEY_OFFSET)
++#define LCDC_OVR1CFG7_GKEY_OFFSET	8
++#define LCDC_OVR1CFG7_GKEY		(0xff << LCDC_OVR1CFG7_GKEY_OFFST)
++#define LCDC_OVR1CFG7_RKEY_OFFSET	16
++#define LCDC_OVR1CFG7_RKEY		(0xff << LCDC_OVR1CFG7_RKEY_OFFSET)
++
++#define ATMEL_LCDC_OVR1CFG8	0x004C
++#define LCDC_OVR1CFG8_BMASK_OFFSET	0
++#define LCDC_OVR1CFG8_BMASK		(0xff << LCDC_OVR1CFG8_BMASK_OFFSET)
++#define LCDC_OVR1CFG8_GMASK_OFFSET	8
++#define LCDC_OVR1CFG8_GMASK		(0xff << LCDC_OVR1CFG8_GMASK_OFFSET)
++#define LCDC_OVR1CFG8_RMASK_OFFSET	16
++#define LCDC_OVR1CFG8_RMASK		(0xff << LCDC_OVR1CFG8_RMASK_OFFSET)
++
++#define ATMEL_LCDC_OVR1CFG9	0x0050
++#define LCDC_OVR1CFG9_CRKEY		(0x1 << 0)
++#define LCDC_OVR1CFG9_INV		(0x1 << 1)
++#define LCDC_OVR1CFG9_ITER2BL		(0x1 << 2)
++#define LCDC_OVR1CFG9_ITER		(0x1 << 3)
++#define LCDC_OVR1CFG9_REVALPHA		(0x1 << 4)
++#define LCDC_OVR1CFG9_GAEN		(0x1 << 5)
++#define LCDC_OVR1CFG9_LAEN		(0x1 << 6)
++#define LCDC_OVR1CFG9_OVR		(0x1 << 7)
++#define LCDC_OVR1CFG9_DMA		(0x1 << 8)
++#define LCDC_OVR1CFG9_REP		(0x1 << 9)
++#define LCDC_OVR1CFG9_DSTKEY		(0x1 << 10)
++#define LCDC_OVR1CFG9_GA_OFFSET		16
++#define LCDC_OVR1CFG9_GA		(0xff << LCDC_OVR1CFG9_GA_OFFSET)
++
++#endif /* __MACH_ATMEL_HLCD_OVL_H__ */
+diff --git a/arch/arm/mach-at91/include/mach/atmel_hlcdfb.h b/arch/arm/mach-at91/include/mach/atmel_hlcdfb.h
+deleted file mode 100644
+index debb8ce..0000000
+--- a/arch/arm/mach-at91/include/mach/atmel_hlcdfb.h
++++ /dev/null
+@@ -1,868 +0,0 @@
+-/*
+- *  Header file for AT91 High end LCD Controller
+- *
+- *  Data structure and register user interface
+- *
+- *  Copyright (C) 2010 Atmel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PUROFFSETE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+- */
+-#ifndef __ATMEL_HLCD_H__
+-#define __ATMEL_HLCD_H__
+-
+-/* Lcdc hardware registers */
+-#define ATMEL_LCDC_LCDCFG0	0x0000
+-#define LCDC_LCDCFG0_CLKPOL		(0x1 << 0)
+-#define LCDC_LCDCFG0_CLKSEL		(0x1 << 2)
+-#define LCDC_LCDCFG0_CLKPWMSEL		(0x1 << 3)
+-#define LCDC_LCDCFG0_CGDISBASE		(0x1 << 8)
+-#define LCDC_LCDCFG0_CGDISOVR1		(0x1 << 9)
+-/* XXX: maybe this is 1 << 10? At least the LCD Interrupt registers
+- * use 10 while the documentation specifies 11.
+- */
+-#define LCDC_LCDCFG0_CGDISHEO		(0x1 << 11)
+-#define LCDC_LCDCFG0_CGDISHCR		(0x1 << 12)
+-#define LCDC_LCDCFG0_CLKDIV_OFFSET	16
+-#define LCDC_LCDCFG0_CLKDIV		(0xff << LCDC_LCDCFG0_CLKDIV_OFFSET)
+-
+-#define ATMEL_LCDC_LCDCFG1	0x0004
+-#define LCDC_LCDCFG1_HSPW_OFFSET	0
+-#define LCDC_LCDCFG1_HSPW		(0x3f << LCDC_LCDCFG1_HSPW_OFFSET)
+-#define LCDC_LCDCFG1_VSPW_OFFSET	16
+-#define LCDC_LCDCFG1_VSPW		(0x3f << LCDC_LCDCFG1_VSPW_OFFSET)
+-
+-#define ATMEL_LCDC_LCDCFG2	0x0008
+-#define LCDC_LCDCFG2_VFPW_OFFSET	0
+-#define LCDC_LCDCFG2_VFPW		(0x3f << LCDC_LCDCFG2_VFPW_OFFSET)
+-#define LCDC_LCDCFG2_VBPW_OFFSET	16
+-#define LCDC_LCDCFG2_VBPW		(0x3f << LCDC_LCDCFG2_VBPW_OFFSET)
+-
+-#define ATMEL_LCDC_LCDCFG3	0x000C
+-#define LCDC_LCDCFG3_HFPW_OFFSET	0
+-#define LCDC_LCDCFG3_HFPW		(0xff << LCDC_LCDCFG3_HFPW_OFFSET)
+-#define LCDC_LCDCFG3_HBPW_OFFSET	16
+-#define LCDC_LCDCFG3_HBPW		(0xff << LCDC_LCDCFG3_HBPW_OFFSET)
+-
+-#define ATMEL_LCDC_LCDCFG4	0x0010
+-#define LCDC_LCDCFG4_PPL_OFFSET		0
+-#define LCDC_LCDCFG4_PPL		(0x7ff << LCDC_LCDCFG4_PPL_OFFSET)
+-#define LCDC_LCDCFG4_RPF_OFFSET		16
+-#define LCDC_LCDCFG4_RPF		(0x7ff << LCDC_LCDCFG4_RPF_OFFSET)
+-
+-#define ATMEL_LCDC_LCDCFG5	0x0014
+-#define LCDC_LCDCFG5_HSPOL		(0x1 << 0)
+-#define LCDC_LCDCFG5_VSPOL		(0x1 << 1)
+-#define LCDC_LCDCFG5_VSPDLYS		(0x1 << 2)
+-#define LCDC_LCDCFG5_VSPDLYE		(0x1 << 3)
+-#define LCDC_LCDCFG5_DISPPOL		(0x1 << 4)
+-#define LCDC_LCDCFG5_SERIAL		(0x1 << 5)
+-#define LCDC_LCDCFG5_DITHER		(0x1 << 6)
+-#define LCDC_LCDCFG5_DISPDLY		(0x1 << 7)
+-#define LCDC_LCDCFG5_MODE_OFFSET	8
+-#define LCDC_LCDCFG5_MODE		(0x3 << LCDC_LCDCFG5_MODE_OFFSET)
+-#define		LCDC_LCDCFG5_MODE_OUTPUT_12BPP		(0x0 << 8)
+-#define		LCDC_LCDCFG5_MODE_OUTPUT_16BPP		(0x1 << 8)
+-#define		LCDC_LCDCFG5_MODE_OUTPUT_18BPP		(0x2 << 8)
+-#define		LCDC_LCDCFG5_MODE_OUTPUT_24BPP		(0x3 << 8)
+-#define LCDC_LCDCFG5_VSPSU		(0x1 << 12)
+-#define LCDC_LCDCFG5_VSPHO		(0x1 << 13)
+-#define LCDC_LCDCFG5_GUARDTIME_OFFSET	16
+-#define LCDC_LCDCFG5_GUARDTIME		(0x1f << LCDC_LCDCFG5_GUARDTIME_OFFSET)
+-
+-#define ATMEL_LCDC_LCDCFG6	0x0018
+-#define LCDC_LCDCFG6_PWMPS_OFFSET	0
+-#define LCDC_LCDCFG6_PWMPS		(0x7 << LCDC_LCDCFG6_PWMPS_OFFSET)
+-#define LCDC_LCDCFG6_PWMPOL		(0x1 << 4)
+-#define LCDC_LCDCFG6_PWMCVAL_OFFSET	8
+-#define LCDC_LCDCFG6_PWMCVAL		(0xff << LCDC_LCDCFG6_PWMCVAL_OFFSET)
+-
+-#define ATMEL_LCDC_LCDEN	0x0020
+-#define LCDC_LCDEN_CLKEN		(0x1 << 0)
+-#define LCDC_LCDEN_SYNCEN		(0x1 << 1)
+-#define LCDC_LCDEN_DISPEN		(0x1 << 2)
+-#define LCDC_LCDEN_PWMEN		(0x1 << 3)
+-
+-#define ATMEL_LCDC_LCDDIS	0x0024
+-#define LCDC_LCDDIS_CLKDIS		(0x1 << 0)
+-#define LCDC_LCDDIS_SYNCDIS		(0x1 << 1)
+-#define LCDC_LCDDIS_DISPDIS		(0x1 << 2)
+-#define LCDC_LCDDIS_PWMDIS		(0x1 << 3)
+-#define LCDC_LCDDIS_CLKRST		(0x1 << 8)
+-#define LCDC_LCDDIS_SYNCRST		(0x1 << 9)
+-#define LCDC_LCDDIS_DISPRST		(0x1 << 10)
+-#define LCDC_LCDDIS_PWMRST		(0x1 << 11)
+-
+-#define ATMEL_LCDC_LCDSR	0x0028
+-#define LCDC_LCDSR_CLKSTS		(0x1 << 0)
+-#define LCDC_LCDSR_LCDSTS		(0x1 << 1)
+-#define LCDC_LCDSR_DISPSTS		(0x1 << 2)
+-#define LCDC_LCDSR_PWMSTS		(0x1 << 3)
+-#define LCDC_LCDSR_SIPSTS		(0x1 << 4)
+-
+-#define ATMEL_LCDC_LCDIER	0x002C
+-#define LCDC_LCDIER_SOFIE		(0x1 << 0)
+-#define LCDC_LCDIER_DISIE		(0x1 << 1)
+-#define LCDC_LCDIER_DISPIE		(0x1 << 2)
+-#define LCDC_LCDIER_FIFOERRIE		(0x1 << 4)
+-#define LCDC_LCDIER_BASEIE		(0x1 << 8)
+-#define LCDC_LCDIER_OVR1IE		(0x1 << 9)
+-#define LCDC_LCDIER_HEOIE		(0x1 << 10)
+-#define LCDC_LCDIER_HCRIE		(0x1 << 12)
+-
+-#define ATMEL_LCDC_LCDIDR	0x0030
+-#define LCDC_LCDIDR_SOFID		(0x1 << 0)
+-#define LCDC_LCDIDR_DISID		(0x1 << 1)
+-#define LCDC_LCDIDR_DISPID		(0x1 << 2)
+-#define LCDC_LCDIDR_FIFOERRID		(0x1 << 4)
+-#define LCDC_LCDIDR_BASEID		(0x1 << 8)
+-#define LCDC_LCDIDR_OVR1ID		(0x1 << 9)
+-#define LCDC_LCDIDR_HEOID		(0x1 << 10)
+-#define LCDC_LCDIDR_HCRID		(0x1 << 12)
+-
+-#define ATMEL_LCDC_LCDIMR	0x0034
+-#define LCDC_LCDIMR_SOFIM		(0x1 << 0)
+-#define LCDC_LCDIMR_DISIM		(0x1 << 1)
+-#define LCDC_LCDIMR_DISPIM		(0x1 << 2)
+-#define LCDC_LCDIMR_FIFOERRIM		(0x1 << 4)
+-#define LCDC_LCDIMR_BASEIM		(0x1 << 8)
+-#define LCDC_LCDIMR_OVR1IM		(0x1 << 9)
+-#define LCDC_LCDIMR_HEOIM		(0x1 << 10)
+-#define LCDC_LCDIMR_HCRIM		(0x1 << 12)
+-
+-#define ATMEL_LCDC_LCDISR	0x0038
+-#define LCDC_LCDISR_SOF			(0x1 << 0)
+-#define LCDC_LCDISR_DIS			(0x1 << 1)
+-#define LCDC_LCDISR_DISP		(0x1 << 2)
+-#define LCDC_LCDISR_FIFOERR		(0x1 << 4)
+-#define LCDC_LCDISR_BASE		(0x1 << 8)
+-#define LCDC_LCDISR_OVR1		(0x1 << 9)
+-#define LCDC_LCDISR_HEO			(0x1 << 10)
+-#define LCDC_LCDISR_HCR			(0x1 << 12)
+-
+-#define ATMEL_LCDC_BASECHER	0x0040
+-#define LCDC_BASECHER_CHEN		(0x1 << 0)
+-#define LCDC_BASECHER_UPDATEEN		(0x1 << 1)
+-#define LCDC_BASECHER_A2QEN		(0x1 << 2)
+-
+-#define ATMEL_LCDC_BASECHDR	0x0044
+-#define LCDC_BASECHDR_CHDIS		(0x1 << 0)
+-#define LCDC_BASECHDR_CHRST		(0x1 << 8)
+-
+-#define ATMEL_LCDC_BASECHSR	0x0048
+-#define LCDC_BASECHSR_CHSR		(0x1 << 0)
+-#define LCDC_BASECHSR_UPDATESR		(0x1 << 1)
+-#define LCDC_BASECHSR_A2QSR		(0x1 << 2)
+-
+-#define ATMEL_LCDC_BASEIER	0x004C
+-#define LCDC_BASEIER_DMA		(0x1 << 2)
+-#define LCDC_BASEIER_DSCR		(0x1 << 3)
+-#define LCDC_BASEIER_ADD		(0x1 << 4)
+-#define LCDC_BASEIER_DONE		(0x1 << 5)
+-#define LCDC_BASEIER_OVR		(0x1 << 6)
+-
+-#define ATMEL_LCDC_BASEIDR	0x0050
+-#define LCDC_BASEIDR_DMA		(0x1 << 2)
+-#define LCDC_BASEIDR_DSCR		(0x1 << 3)
+-#define LCDC_BASEIDR_ADD		(0x1 << 4)
+-#define LCDC_BASEIDR_DONE		(0x1 << 5)
+-#define LCDC_BASEIDR_OVR		(0x1 << 6)
+-
+-#define ATMEL_LCDC_BASEIMR	0x0054
+-#define LCDC_BASEIMR_DMA		(0x1 << 2)
+-#define LCDC_BASEIMR_DSCR		(0x1 << 3)
+-#define LCDC_BASEIMR_ADD		(0x1 << 4)
+-#define LCDC_BASEIMR_DONE		(0x1 << 5)
+-#define LCDC_BASEIMR_OVR		(0x1 << 6)
+-
+-#define ATMEL_LCDC_BASEISR	0x0058
+-#define LCDC_BASEISR_DMA		(0x1 << 2)
+-#define LCDC_BASEISR_DSCR		(0x1 << 3)
+-#define LCDC_BASEISR_ADD		(0x1 << 4)
+-#define LCDC_BASEISR_DONE		(0x1 << 5)
+-#define LCDC_BASEISR_OVR		(0x1 << 6)
+-
+-#define ATMEL_LCDC_BASEHEAD	0x005C
+-
+-#define ATMEL_LCDC_BASEADDR	0x0060
+-
+-#define ATMEL_LCDC_BASECTRL	0x0064
+-#define LCDC_BASECTRL_DFETCH		(0x1 << 0)
+-#define LCDC_BASECTRL_LFETCH		(0x1 << 1)
+-#define LCDC_BASECTRL_DMAIEN		(0x1 << 2)
+-#define LCDC_BASECTRL_DSCRIEN		(0x1 << 3)
+-#define LCDC_BASECTRL_ADDIEN		(0x1 << 4)
+-#define LCDC_BASECTRL_DONEIEN		(0x1 << 5)
+-
+-#define ATMEL_LCDC_BASENEXT	0x0068
+-
+-#define ATMEL_LCDC_BASECFG0	0x006C
+-#define LCDC_BASECFG0_BLEN_OFFSET 4
+-#define LCDC_BASECFG0_BLEN		(0x3 << LCDC_BASECFG0_BLEN_OFFSET)
+-#define		LCDC_BASECFG0_BLEN_AHB_SINGLE		(0x0 << 4)
+-#define		LCDC_BASECFG0_BLEN_AHB_INCR4		(0x1 << 4)
+-#define		LCDC_BASECFG0_BLEN_AHB_INCR8		(0x2 << 4)
+-#define		LCDC_BASECFG0_BLEN_AHB_INCR16		(0x3 << 4)
+-#define LCDC_BASECFG0_DLBO		(0x1 << 8)
+-
+-#define ATMEL_LCDC_BASECFG1	0x0070
+-#define LCDC_BASECFG1_CLUTEN		(0x1 << 0)
+-#define LCDC_BASECFG1_RGBMODE_OFFSET	4
+-#define LCDC_BASECFG1_RGBMODE		(0xf << LCDC_BASECFG1_RGBMODE_OFFSET)
+-#define		LCDC_BASECFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
+-#define		LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
+-#define		LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
+-#define		LCDC_BASECFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
+-#define		LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
+-#define		LCDC_BASECFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
+-#define		LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
+-#define		LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
+-#define		LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
+-#define		LCDC_BASECFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
+-#define		LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
+-#define		LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
+-#define		LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
+-#define		LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
+-#define LCDC_BASECFG1_CLUTMODE_OFFSET	8
+-#define LCDC_BASECFG1_CLUTMODE		(0x3 << LCDC_BASECFG1_CLUTMODE_OFFSET)
+-#define		LCDC_BASECFG1_CLUTMODE_1BPP		(0x0 << 8)
+-#define		LCDC_BASECFG1_CLUTMODE_2BPP		(0x1 << 8)
+-#define		LCDC_BASECFG1_CLUTMODE_4BPP		(0x2 << 8)
+-#define		LCDC_BASECFG1_CLUTMODE_8BPP		(0x3 << 8)
+-
+-#define ATMEL_LCDC_BASECFG2	0x0074
+-
+-#define ATMEL_LCDC_BASECFG3	0x0078
+-#define LCDC_BASECFG3_BDEF_OFFSET	0
+-#define LCDC_BASECFG3_BDEF		(0xff << LCDC_BASECFG3_BDEF_OFFSET)
+-#define LCDC_BASECFG3_GDEF_OFFSET	8
+-#define LCDC_BASECFG3_GDEF		(0xff << LCDC_BASECFG3_GDEF_OFFSET)
+-#define LCDC_BASECFG3_RDEF_OFFSET	16
+-#define LCDC_BASECFG3_RDEF		(0xff << LCDC_BASECFG3_RDEF_OFFSET)
+-
+-#define ATMEL_LCDC_BASECFG4	0x007C
+-#define LCDC_BASECFG4_DMA		(0x1 << 8)
+-#define LCDC_BASECFG4_REP		(0x1 << 9)
+-
+-#define ATMEL_LCDC_OVRCHER1	0x0100
+-#define LCDC_OVRCHER1_CHEN		(0x1 << 0)
+-#define LCDC_OVRCHER1_UPDATEEN		(0x1 << 1)
+-#define LCDC_OVRCHER1_A2QEN		(0x1 << 2)
+-
+-#define ATMEL_LCDC_OVRCHDR1	0x0104
+-#define LCDC_OVRCHDR1_CHDIS		(0x1 << 0)
+-#define LCDC_OVRCHDR1_CHRST		(0x1 << 8)
+-
+-#define ATMEL_LCDC_OVRCHSR1	0x0108
+-#define LCDC_OVRCHSR1_CHSR		(0x1 << 0)
+-#define LCDC_OVRCHSR1_UPDATESR		(0x1 << 1)
+-#define LCDC_OVRCHSR1_A2QSR		(0x1 << 2)
+-
+-#define ATMEL_LCDC_OVRIER1	0x010C
+-#define LCDC_OVRIER1_DMA		(0x1 << 2)
+-#define LCDC_OVRIER1_DSCR		(0x1 << 3)
+-#define LCDC_OVRIER1_ADD		(0x1 << 4)
+-#define LCDC_OVRIER1_DONE		(0x1 << 5)
+-#define LCDC_OVRIER1_OVR		(0x1 << 6)
+-
+-#define ATMEL_LCDC_OVRIDR1	0x0110
+-#define LCDC_OVRIDR1_DMA		(0x1 << 2)
+-#define LCDC_OVRIDR1_DSCR		(0x1 << 3)
+-#define LCDC_OVRIDR1_ADD		(0x1 << 4)
+-#define LCDC_OVRIDR1_DONE		(0x1 << 5)
+-#define LCDC_OVRIDR1_OVR		(0x1 << 6)
+-
+-#define ATMEL_LCDC_OVRIMR1	0x0114
+-#define LCDC_OVRIMR1_DMA		(0x1 << 2)
+-#define LCDC_OVRIMR1_DSCR		(0x1 << 3)
+-#define LCDC_OVRIMR1_ADD		(0x1 << 4)
+-#define LCDC_OVRIMR1_DONE		(0x1 << 5)
+-#define LCDC_OVRIMR1_OVR		(0x1 << 6)
+-
+-#define ATMEL_LCDC_OVRISR1	0x0118
+-#define LCDC_OVRISR1_DMA		(0x1 << 2)
+-#define LCDC_OVRISR1_DSCR		(0x1 << 3)
+-#define LCDC_OVRISR1_ADD		(0x1 << 4)
+-#define LCDC_OVRISR1_DONE		(0x1 << 5)
+-#define LCDC_OVRISR1_OVR		(0x1 << 6)
+-
+-#define ATMEL_LCDC_OVRHEAD1	0x011C
+-
+-#define ATMEL_LCDC_OVRADDR1	0x0120
+-
+-#define ATMEL_LCDC_OVRCTRL1	0x0124
+-#define LCDC_OVRCTRL1_DFETCH		(0x1 << 0)
+-#define LCDC_OVRCTRL1_LFETCH		(0x1 << 1)
+-#define LCDC_OVRCTRL1_DMAIEN		(0x1 << 2)
+-#define LCDC_OVRCTRL1_DSCRIEN		(0x1 << 3)
+-#define LCDC_OVRCTRL1_ADDIEN		(0x1 << 4)
+-#define LCDC_OVRCTRL1_DONEIEN		(0x1 << 5)
+-
+-#define ATMEL_LCDC_OVRNEXT1	0x0128
+-
+-#define ATMEL_LCDC_OVR1CFG0	0x012C
+-#define LCDC_OVR1CFG0_BLEN_OFFSET	4
+-#define LCDC_OVR1CFG0_BLEN		(0x3 << LCDC_OVR1CFG0_BLEN_OFFSET)
+-#define		LCDC_OVR1CFG0_BLEN_AHB_SINGLE		(0x0 << 4)
+-#define		LCDC_OVR1CFG0_BLEN_AHB_INCR4		(0x1 << 4)
+-#define		LCDC_OVR1CFG0_BLEN_AHB_INCR8		(0x2 << 4)
+-#define		LCDC_OVR1CFG0_BLEN_AHB_INCR16		(0x3 << 4)
+-#define LCDC_OVR1CFG0_DLBO		(0x1 << 8)
+-#define LCDC_OVR1CFG0_ROTDIS		(0x1 << 12)
+-#define LCDC_OVR1CFG0_LOCKDIS		(0x1 << 13)
+-
+-#define ATMEL_LCDC_OVR1CFG1	0x0130
+-#define LCDC_OVR1CFG1_CLUTEN		(0x1 << 0)
+-#define LCDC_OVR1CFG1_RGBMODE_OFFSET	4
+-#define LCDC_OVR1CFG1_RGBMODE		(0xf << LCDC_OVR1CFG1_RGBMODE_OFFSET)
+-#define		LCDC_OVR1CFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
+-#define		LCDC_OVR1CFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
+-#define LCDC_OVR1CFG1_CLUTMODE_OFFSET	8
+-#define LCDC_OVR1CFG1_CLUTMODE		(0x3 << LCDC_OVR1CFG1_CLUTMODE_OFFSET)
+-#define		LCDC_OVR1CFG1_CLUTMODE_1BPP		(0x0 << 8)
+-#define		LCDC_OVR1CFG1_CLUTMODE_2BPP		(0x1 << 8)
+-#define		LCDC_OVR1CFG1_CLUTMODE_4BPP		(0x2 << 8)
+-#define		LCDC_OVR1CFG1_CLUTMODE_8BPP		(0x3 << 8)
+-
+-#define ATMEL_LCDC_OVR1CFG2	0x0134
+-#define LCDC_OVR1CFG2_XOFFSET_OFFSET	0
+-#define LCDC_OVR1CFG2_XOFFSET		(0x7ff << LCDC_OVR1CFG2_XOFFSET_OFFSET)
+-#define LCDC_OVR1CFG2_YOFFSET_OFFSET	16
+-#define LCDC_OVR1CFG2_YOFFSET		(0x7ff << LCDC_OVR1CFG2_YOFFSET_OFFSET)
+-
+-#define ATMEL_LCDC_OVR1CFG3	0x0138
+-#define LCDC_OVR1CFG3_XSIZE_OFFSET	0
+-#define LCDC_OVR1CFG3_XSIZE		(0x7ff << LCDC_OVR1CFG3_XSIZE_OFFSET)
+-#define LCDC_OVR1CFG3_YSIZE_OFFSET	16
+-#define LCDC_OVR1CFG3_YSIZE		(0x7ff << LCDC_OVR1CFG3_YSIZE_OFFSET)
+-
+-#define ATMEL_LCDC_OVR1CFG4	0x013C
+-
+-#define ATMEL_LCDC_OVR1CFG5	0x0140
+-
+-#define ATMEL_LCDC_OVR1CFG6	0x0144
+-#define LCDC_OVR1CFG6_BDEF_OFFSET	0
+-#define LCDC_OVR1CFG6_BDEF		(0xff << LCDC_OVR1CFG6_BDEF_OFFSET)
+-#define LCDC_OVR1CFG6_GDEF_OFFSET	8
+-#define LCDC_OVR1CFG6_GDEF		(0xff << LCDC_OVR1CFG6_GDEF_OFFSET)
+-#define LCDC_OVR1CFG6_RDEF_OFFSET	16
+-#define LCDC_OVR1CFG6_RDEF		(0xff << LCDC_OVR1CFG6_RDEF_OFFSET)
+-
+-#define ATMEL_LCDC_OVR1CFG7	0x0148
+-#define LCDC_OVR1CFG7_BKEY_OFFSET	0
+-#define LCDC_OVR1CFG7_BKEY		(0xff << LCDC_OVR1CFG7_BKEY_OFFSET)
+-#define LCDC_OVR1CFG7_GKEY_OFFSET	8
+-#define LCDC_OVR1CFG7_GKEY		(0xff << LCDC_OVR1CFG7_GKEY_OFFST)
+-#define LCDC_OVR1CFG7_RKEY_OFFSET	16
+-#define LCDC_OVR1CFG7_RKEY		(0xff << LCDC_OVR1CFG7_RKEY_OFFSET)
+-
+-#define ATMEL_LCDC_OVR1CFG8	0x014C
+-#define LCDC_OVR1CFG8_BMASK_OFFSET	0
+-#define LCDC_OVR1CFG8_BMASK		(0xff << LCDC_OVR1CFG8_BMASK_OFFSET)
+-#define LCDC_OVR1CFG8_GMASK_OFFSET	8
+-#define LCDC_OVR1CFG8_GMASK		(0xff << LCDC_OVR1CFG8_GMASK_OFFSET)
+-#define LCDC_OVR1CFG8_RMASK_OFFSET	16
+-#define LCDC_OVR1CFG8_RMASK		(0xff << LCDC_OVR1CFG8_RMASK_OFFSET)
+-
+-#define ATMEL_LCDC_OVR1CFG9	0x0150
+-#define LCDC_OVR1CFG9_CRKEY		(0x1 << 0)
+-#define LCDC_OVR1CFG9_INV		(0x1 << 1)
+-#define LCDC_OVR1CFG9_ITER2BL		(0x1 << 2)
+-#define LCDC_OVR1CFG9_ITER		(0x1 << 3)
+-#define LCDC_OVR1CFG9_REVALPHA		(0x1 << 4)
+-#define LCDC_OVR1CFG9_GAEN		(0x1 << 5)
+-#define LCDC_OVR1CFG9_LAEN		(0x1 << 6)
+-#define LCDC_OVR1CFG9_OVR		(0x1 << 7)
+-#define LCDC_OVR1CFG9_DMA		(0x1 << 8)
+-#define LCDC_OVR1CFG9_REP		(0x1 << 9)
+-#define LCDC_OVR1CFG9_DSTKEY		(0x1 << 10)
+-#define LCDC_OVR1CFG9_GA_OFFSET		16
+-#define LCDC_OVR1CFG9_GA		(0xff << LCDC_OVR1CFG9_GA_OFFSET)
+-
+-#define ATMEL_LCDC_HEOCHER	0x0280
+-#define LCDC_HEOCHER_CHEN		(0x1 << 0)
+-#define LCDC_HEOCHER_UPDATEEN		(0x1 << 1)
+-#define LCDC_HEOCHER_A2QEN		(0x1 << 2)
+-
+-#define ATMEL_LCDC_HEOCHDR	0x0284
+-#define LCDC_HEOCHDR_CHDIS		(0x1 << 0)
+-#define LCDC_HEOCHDR_CHRST		(0x1 << 8)
+-
+-#define ATMEL_LCDC_HEOCHSR	0x0288
+-#define LCDC_HEOCHSR_CHSR		(0x1 << 0)
+-#define LCDC_HEOCHSR_UPDATESR		(0x1 << 1)
+-#define LCDC_HEOCHSR_A2QSR		(0x1 << 2)
+-
+-#define ATMEL_LCDC_HEOIER	0x028C
+-#define LCDC_HEOIER_DMA			(0x1 << 2)
+-#define LCDC_HEOIER_DSCR		(0x1 << 3)
+-#define LCDC_HEOIER_ADD			(0x1 << 4)
+-#define LCDC_HEOIER_DONE		(0x1 << 5)
+-#define LCDC_HEOIER_OVR			(0x1 << 6)
+-#define LCDC_HEOIER_UDMA		(0x1 << 10)
+-#define LCDC_HEOIER_UDSCR		(0x1 << 11)
+-#define LCDC_HEOIER_UADD		(0x1 << 12)
+-#define LCDC_HEOIER_UDONE		(0x1 << 13)
+-#define LCDC_HEOIER_UOVR		(0x1 << 14)
+-#define LCDC_HEOIER_VDMA		(0x1 << 18)
+-#define LCDC_HEOIER_VDSCR		(0x1 << 19)
+-#define LCDC_HEOIER_VADD		(0x1 << 20)
+-#define LCDC_HEOIER_VDONE		(0x1 << 21)
+-#define LCDC_HEOIER_VOVR		(0x1 << 22)
+-
+-#define ATMEL_LCDC_HEOIDR	0x0290
+-#define LCDC_HEOIDR_DMA			(0x1 << 2)
+-#define LCDC_HEOIDR_DSCR		(0x1 << 3)
+-#define LCDC_HEOIDR_ADD			(0x1 << 4)
+-#define LCDC_HEOIDR_DONE		(0x1 << 5)
+-#define LCDC_HEOIDR_OVR			(0x1 << 6)
+-#define LCDC_HEOIDR_UDMA		(0x1 << 10)
+-#define LCDC_HEOIDR_UDSCR		(0x1 << 11)
+-#define LCDC_HEOIDR_UADD		(0x1 << 12)
+-#define LCDC_HEOIDR_UDONE		(0x1 << 13)
+-#define LCDC_HEOIDR_UOVR		(0x1 << 14)
+-#define LCDC_HEOIDR_VDMA		(0x1 << 18)
+-#define LCDC_HEOIDR_VDSCR		(0x1 << 19)
+-#define LCDC_HEOIDR_VADD		(0x1 << 20)
+-#define LCDC_HEOIDR_VDONE		(0x1 << 21)
+-#define LCDC_HEOIDR_VOVR		(0x1 << 22)
+-
+-#define ATMEL_LCDC_HEOIMR	0x0294
+-#define LCDC_HEOIMR_DMA			(0x1 << 2)
+-#define LCDC_HEOIMR_DSCR		(0x1 << 3)
+-#define LCDC_HEOIMR_ADD			(0x1 << 4)
+-#define LCDC_HEOIMR_DONE		(0x1 << 5)
+-#define LCDC_HEOIMR_OVR			(0x1 << 6)
+-#define LCDC_HEOIMR_UDMA		(0x1 << 10)
+-#define LCDC_HEOIMR_UDSCR		(0x1 << 11)
+-#define LCDC_HEOIMR_UADD		(0x1 << 12)
+-#define LCDC_HEOIMR_UDONE		(0x1 << 13)
+-#define LCDC_HEOIMR_UOVR		(0x1 << 14)
+-#define LCDC_HEOIMR_VDMA		(0x1 << 18)
+-#define LCDC_HEOIMR_VDSCR		(0x1 << 19)
+-#define LCDC_HEOIMR_VADD		(0x1 << 20)
+-#define LCDC_HEOIMR_VDONE		(0x1 << 21)
+-#define LCDC_HEOIMR_VOVR		(0x1 << 22)
+-
+-#define ATMEL_LCDC_HEOISR	0x0298
+-#define LCDC_HEOISR_DMA			(0x1 << 2)
+-#define LCDC_HEOISR_DSCR		(0x1 << 3)
+-#define LCDC_HEOISR_ADD			(0x1 << 4)
+-#define LCDC_HEOISR_DONE		(0x1 << 5)
+-#define LCDC_HEOISR_OVR			(0x1 << 6)
+-#define LCDC_HEOISR_UDMA		(0x1 << 10)
+-#define LCDC_HEOISR_UDSCR		(0x1 << 11)
+-#define LCDC_HEOISR_UADD		(0x1 << 12)
+-#define LCDC_HEOISR_UDONE		(0x1 << 13)
+-#define LCDC_HEOISR_UOVR		(0x1 << 14)
+-#define LCDC_HEOISR_VDMA		(0x1 << 18)
+-#define LCDC_HEOISR_VDSCR		(0x1 << 19)
+-#define LCDC_HEOISR_VADD		(0x1 << 20)
+-#define LCDC_HEOISR_VDONE		(0x1 << 21)
+-#define LCDC_HEOISR_VOVR		(0x1 << 22)
+-
+-#define ATMEL_LCDC_HEOHEAD	0x029C
+-
+-#define ATMEL_LCDC_HEOADDR	0x02A0
+-
+-#define ATMEL_LCDC_HEOCTRL	0x02A4
+-#define LCDC_HEOCTRL_DFETCH		(0x1 << 0)
+-#define LCDC_HEOCTRL_LFETCH		(0x1 << 1)
+-#define LCDC_HEOCTRL_DMAIEN		(0x1 << 2)
+-#define LCDC_HEOCTRL_DSCRIEN		(0x1 << 3)
+-#define LCDC_HEOCTRL_ADDIEN		(0x1 << 4)
+-#define LCDC_HEOCTRL_DONEIEN		(0x1 << 5)
+-
+-#define ATMEL_LCDC_HEONEXT	0x02A8
+-
+-#define ATMEL_LCDC_HEOUHEAD	0x02AC
+-
+-#define ATMEL_LCDC_HEOUADDR	0x02B0
+-
+-#define ATMEL_LCDC_HEOUCTRL	0x02B4
+-#define LCDC_HEOUCTRL_UDFETCH		(0x1 << 0)
+-#define LCDC_HEOUCTRL_UDMAIEN		(0x1 << 2)
+-#define LCDC_HEOUCTRL_UDSCRIEN		(0x1 << 3)
+-#define LCDC_HEOUCTRL_UADDIEN		(0x1 << 4)
+-#define LCDC_HEOUCTRL_UDONEIEN		(0x1 << 5)
+-
+-#define ATMEL_LCDC_HEOUNEXT	0x02B8
+-
+-#define ATMEL_LCDC_HEOVHEAD	0x02BC
+-
+-#define ATMEL_LCDC_HEOVADDR	0x02C0
+-
+-#define ATMEL_LCDC_HEOVCTRL	0x02C4
+-#define LCDC_HEOVCTRL_VDFETCH		(0x1 << 0)
+-#define LCDC_HEOVCTRL_VDMAIEN		(0x1 << 2)
+-#define LCDC_HEOVCTRL_VDSCRIEN		(0x1 << 3)
+-#define LCDC_HEOVCTRL_VADDIEN		(0x1 << 4)
+-#define LCDC_HEOVCTRL_VDONEIEN		(0x1 << 5)
+-
+-#define ATMEL_LCDC_HEOVNEXT	0x02C8
+-
+-#define ATMEL_LCDC_HEOCFG0	0x02CC
+-#define LCDC_HEOCFG0_BLEN_OFFSET	4
+-#define LCDC_HEOCFG0_BLEN		(0x3 << LCDC_HEOCFG0_BLEN_OFFSET)
+-#define		LCDC_HEOCFG0_BLEN_AHB_SINGLE		(0x0 << 4)
+-#define		LCDC_HEOCFG0_BLEN_AHB_INCR4		(0x1 << 4)
+-#define		LCDC_HEOCFG0_BLEN_AHB_INCR8		(0x2 << 4)
+-#define		LCDC_HEOCFG0_BLEN_AHB_INCR16		(0x3 << 4)
+-#define LCDC_HEOCFG0_BLENUV_OFFSET	6
+-#define LCDC_HEOCFG0_BLENUV		(0x3 << LCDC_HEOCFG0_BLENUV_OFFSET)
+-#define		LCDC_HEOCFG0_BLENUV_AHB_SINGLE		(0x0 << 6)
+-#define		LCDC_HEOCFG0_BLENUV_AHB_INCR4		(0x1 << 6)
+-#define		LCDC_HEOCFG0_BLENUV_AHB_INCR8		(0x2 << 6)
+-#define		LCDC_HEOCFG0_BLENUV_AHB_INCR16		(0x3 << 6)
+-#define LCDC_HEOCFG0_DLBO		(0x1 << 8)
+-#define LCDC_HEOCFG0_ROTDIS		(0x1 << 12)
+-#define LCDC_HEOCFG0_LOCKDIS		(0x1 << 13)
+-
+-#define ATMEL_LCDC_HEOCFG1	0x02D0
+-#define LCDC_HEOCFG1_CLUTEN		(0x1 << 0)
+-#define LCDC_HEOCFG1_YUVEN		(0x1 << 1)
+-#define LCDC_HEOCFG1_RGBMODE_OFFSET	4
+-#define LCDC_HEOCFG1_RGBMODE		(0xf << LCDC_HEOCFG1_RGBMODE_OFFSET)
+-#define		LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
+-#define		LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
+-#define LCDC_HEOCFG1_CLUTMODE_OFFSET	8
+-#define LCDC_HEOCFG1_CLUTMODE		(0x3 << LCDC_HEOCFG1_CLUTMODE_OFFSET)
+-#define		LCDC_HEOCFG1_CLUTMODE_1BPP		(0x0 << 8)
+-#define		LCDC_HEOCFG1_CLUTMODE_2BPP		(0x1 << 8)
+-#define		LCDC_HEOCFG1_CLUTMODE_4BPP		(0x2 << 8)
+-#define		LCDC_HEOCFG1_CLUTMODE_8BPP		(0x3 << 8)
+-#define LCDC_HEOCFG1_YUVMODE_OFFSET	12
+-#define LCDC_HEOCFG1_YUVMODE		(0xf << LCDC_HEOCFG1_YUVMODE_OFFSET)
+-#define		LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR	(0x0 << 12)
+-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0	(0x1 << 12)
+-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1	(0x2 << 12)
+-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2	(0x3 << 12)
+-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3	(0x4 << 12)
+-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR	(0x5 << 12)
+-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR	(0x6 << 12)
+-#define		LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR	(0x7 << 12)
+-#define		LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR	(0x8 << 12)
+-#define LCDC_HEOCFG1_YUV422ROT		(0x1 << 16)
+-#define LCDC_HEOCFG1_YUV422SWP		(0x1 << 17)
+-
+-#define ATMEL_LCDC_HEOCFG2	0x02D4
+-#define LCDC_HEOCFG2_XOFFSET_OFFSET	0
+-#define LCDC_HEOCFG2_XOFFSET		(0x7ff << LCDC_HEOCFG2_XOFFSET_OFFSET)
+-#define LCDC_HEOCFG2_YOFFSET_OFFSET	16
+-#define LCDC_HEOCFG2_YOFFSET		(0x7ff << LCDC_HEOCFG2_YOFFSET_OFFSET)
+-
+-#define ATMEL_LCDC_HEOCFG3	0x02D8
+-#define LCDC_HEOCFG3_XSIZE_OFFSET	0
+-#define LCDC_HEOCFG3_XSIZE		(0x7ff << LCDC_HEOCFG3_XSIZE_OFFSET)
+-#define LCDC_HEOCFG3_YSIZE_OFFSET	16
+-#define LCDC_HEOCFG3_YSIZE		(0x7ff << LCDC_HEOCFG3_YSIZE_OFFSET)
+-
+-#define ATMEL_LCDC_HEOCFG4	0x02DC
+-#define LCDC_HEOCFG4_XMEM_SIZE_OFFSET	0
+-#define LCDC_HEOCFG4_XMEM_SIZE		(0x7ff << LCDC_HEOCFG4_XMEM_SIZE_OFFSET)
+-#define LCDC_HEOCFG4_YMEM_SIZE_OFFSET	16
+-#define LCDC_HEOCFG4_YMEM_SIZE		(0x7ff << LCDC_HEOCFG4_YMEM_SIZE_OFFSET)
+-
+-#define ATMEL_LCDC_HEOCFG5	0x02E0
+-
+-#define ATMEL_LCDC_HEOCFG6	0x02E4
+-
+-#define ATMEL_LCDC_HEOCFG7	0x02E8
+-
+-#define ATMEL_LCDC_HEOCFG8	0x02EC
+-
+-#define ATMEL_LCDC_HEOCFG9	0x02F0
+-#define LCDC_HEOCFG9_BDEF_OFFSET	0
+-#define LCDC_HEOCFG9_BDEF		(0xff << LCDC_HEOCFG9_BDEF_OFFSET)
+-#define LCDC_HEOCFG9_GDEF_OFFSET	8
+-#define LCDC_HEOCFG9_GDEF		(0xff << LCDC_HEOCFG9_GDEF_OFFSET)
+-#define LCDC_HEOCFG9_RDEF_OFFSET	16
+-#define LCDC_HEOCFG9_RDEF		(0xff << LCDC_HEOCFG9_RDEF_OFFSET)
+-
+-#define ATMEL_LCDC_HEOCFG10	0x02F4
+-#define LCDC_HEOCFG10_BKEY_OFFSET	0
+-#define LCDC_HEOCFG10_BKEY		(0xff << LCDC_HEOCFG10_BKEY_OFFSET)
+-#define LCDC_HEOCFG10_GKEY_OFFSET	8
+-#define LCDC_HEOCFG10_GKEY		(0xff << LCDC_HEOCFG10_GKEY_OFFSET)
+-#define LCDC_HEOCFG10_RKEY_OFFSET	16
+-#define LCDC_HEOCFG10_RKEY		(0xff << LCDC_HEOCFG10_RKEY_OFFSET)
+-
+-#define ATMEL_LCDC_HEOCFG11	0x02F8
+-#define LCDC_HEOCFG11_BMASK_OFFSET	0
+-#define LCDC_HEOCFG11_BMASK		(0xff << LCDC_HEOCFG11_BMASK_OFFSET)
+-#define LCDC_HEOCFG11_GMASK_OFFSET	8
+-#define LCDC_HEOCFG11_GMASK		(0xff << LCDC_HEOCFG11_GMASK_OFFSET)
+-#define LCDC_HEOCFG11_RMASK_OFFSET	16
+-#define LCDC_HEOCFG11_RMASK		(0xff << LCDC_HEOCFG11_RMASK_OFFSET)
+-
+-#define ATMEL_LCDC_HEOCFG12	0x02FC
+-#define LCDC_HEOCFG12_CRKEY		(0x1 << 0)
+-#define LCDC_HEOCFG12_INV		(0x1 << 1)
+-#define LCDC_HEOCFG12_ITER2BL		(0x1 << 2)
+-#define LCDC_HEOCFG12_ITER		(0x1 << 3)
+-#define LCDC_HEOCFG12_REVALPHA		(0x1 << 4)
+-#define LCDC_HEOCFG12_GAEN		(0x1 << 5)
+-#define LCDC_HEOCFG12_LAEN		(0x1 << 6)
+-#define LCDC_HEOCFG12_OVR		(0x1 << 7)
+-#define LCDC_HEOCFG12_DMA		(0x1 << 8)
+-#define LCDC_HEOCFG12_REP		(0x1 << 9)
+-#define LCDC_HEOCFG12_DSTKEY		(0x1 << 10)
+-#define LCDC_HEOCFG12_VIDPRI		(0x1 << 12)
+-#define LCDC_HEOCFG12_GA_OFFSET		16
+-#define LCDC_HEOCFG12_GA		(0xff << LCDC_HEOCFG12_GA_OFFSET)
+-
+-#define ATMEL_LCDC_HEOCFG13	0x0300
+-#define LCDC_HEOCFG13_XFACTOR_OFFSET	0
+-#define LCDC_HEOCFG13_XFACTOR		(0x1fff << LCDC_HEOCFG13_XFACTOR_OFFSET)
+-#define LCDC_HEOCFG13_YFACTOR_OFFSET	16
+-#define LCDC_HEOCFG13_YFACTOR		(0x1fff << LCDC_HEOCFG13_YFACTOR_OFFSET)
+-#define LCDC_HEOCFG13_SCALEN		(0x1 << 31)
+-
+-#define ATMEL_LCDC_HEOCFG14	0x0304
+-#define LCDC_HEOCFG14_CSCRY_OFFSET	0
+-#define LCDC_HEOCFG14_CSCRY		(0x3ff << LCDC_HEOCFG14_CSCRY_OFFSET)
+-#define LCDC_HEOCFG14_CSCRU_OFFSET	10
+-#define LCDC_HEOCFG14_CSCRU		(0x3ff << LCDC_HEOCFG14_CSCRU_OFFSET)
+-#define LCDC_HEOCFG14_CSCRV_OFFSET	20
+-#define LCDC_HEOCFG14_CSCRV		(0x3ff << LCDC_HEOCFG14_CSCRV_OFFSET)
+-#define LCDC_HEOCFG14_CSCYOFF		(0x1 << 30)
+-
+-#define ATMEL_LCDC_HEOCFG15	0x0308
+-#define LCDC_HEOCFG15_CSCGY_OFFSET	0
+-#define LCDC_HEOCFG15_CSCGY		(0x3ff << LCDC_HEOCFG15_CSCGY_OFFSET)
+-#define LCDC_HEOCFG15_CSCGU_OFFSET	10
+-#define LCDC_HEOCFG15_CSCGU		(0x3ff << LCDC_HEOCFG15_CSCGU_OFFSET)
+-#define LCDC_HEOCFG15_CSCGV_OFFSET	20
+-#define LCDC_HEOCFG15_CSCGV		(0x3ff << LCDC_HEOCFG15_CSCGV_OFFSET)
+-#define LCDC_HEOCFG15_CSCUOFF		(0x1 << 30)
+-
+-#define ATMEL_LCDC_HEOCFG16	0x030C
+-#define LCDC_HEOCFG16_CSCBY_OFFSET	0
+-#define LCDC_HEOCFG16_CSCBY		(0x3ff << LCDC_HEOCFG16_CSCBY_OFFSET)
+-#define LCDC_HEOCFG16_CSCBU_OFFSET	10
+-#define LCDC_HEOCFG16_CSCBU		(0x3ff << LCDC_HEOCFG16_CSCBU_OFFSET)
+-#define LCDC_HEOCFG16_CSCBV_OFFSET	20
+-#define LCDC_HEOCFG16_CSCBV		(0x3ff << LCDC_HEOCFG16_CSCBV_OFFSET)
+-#define LCDC_HEOCFG16_CSCVOFF		(0x1 << 30)
+-
+-#define ATMEL_LCDC_HCRCHER	0x0340
+-#define LCDC_HCRCHER_CHEN		(0x1 << 0)
+-#define LCDC_HCRCHER_UPDATEEN		(0x1 << 1)
+-#define LCDC_HCRCHER_A2QEN		(0x1 << 2)
+-
+-#define ATMEL_LCDC_HCRCHDR	0x0344
+-#define LCDC_HCRCHDR_CHDIS		(0x1 << 0)
+-#define LCDC_HCRCHDR_CHRST		(0x1 << 8)
+-
+-#define ATMEL_LCDC_HCRCHSR	0x0348
+-#define LCDC_HCRCHSR_CHSR		(0x1 << 0)
+-#define LCDC_HCRCHSR_UPDATESR		(0x1 << 1)
+-#define LCDC_HCRCHSR_A2QSR		(0x1 << 2)
+-
+-#define ATMEL_LCDC_HCRIER	0x034C
+-#define LCDC_HCRIER_DMA			(0x1 << 2)
+-#define LCDC_HCRIER_DSCR		(0x1 << 3)
+-#define LCDC_HCRIER_ADD			(0x1 << 4)
+-#define LCDC_HCRIER_DONE		(0x1 << 5)
+-#define LCDC_HCRIER_OVR			(0x1 << 6)
+-
+-#define ATMEL_LCDC_HCRIDR	0x0350
+-#define LCDC_HCRIDR_DMA			(0x1 << 2)
+-#define LCDC_HCRIDR_DSCR		(0x1 << 3)
+-#define LCDC_HCRIDR_ADD			(0x1 << 4)
+-#define LCDC_HCRIDR_DONE		(0x1 << 5)
+-#define LCDC_HCRIDR_OVR			(0x1 << 6)
+-
+-#define ATMEL_LCDC_HCRIMR	0x0354
+-#define LCDC_HCRIMR_DMA			(0x1 << 2)
+-#define LCDC_HCRIMR_DSCR		(0x1 << 3)
+-#define LCDC_HCRIMR_ADD			(0x1 << 4)
+-#define LCDC_HCRIMR_DONE		(0x1 << 5)
+-#define LCDC_HCRIMR_OVR			(0x1 << 6)
+-
+-#define ATMEL_LCDC_HCRISR	0x0358
+-#define LCDC_HCRISR_DMA			(0x1 << 2)
+-#define LCDC_HCRISR_DSCR		(0x1 << 3)
+-#define LCDC_HCRISR_ADD			(0x1 << 4)
+-#define LCDC_HCRISR_DONE		(0x1 << 5)
+-#define LCDC_HCRISR_OVR			(0x1 << 6)
+-
+-#define ATMEL_LCDC_HCRHEAD	0x035C
+-
+-#define ATMEL_LCDC_HCRADDR	0x0360
+-
+-#define ATMEL_LCDC_HCRCTRL	0x0364
+-#define LCDC_HCRCTRL_DFETCH		(0x1 << 0)
+-#define LCDC_HCRCTRL_LFETCH		(0x1 << 1)
+-#define LCDC_HCRCTRL_DMAIEN		(0x1 << 2)
+-#define LCDC_HCRCTRL_DSCRIEN		(0x1 << 3)
+-#define LCDC_HCRCTRL_ADDIEN		(0x1 << 4)
+-#define LCDC_HCRCTRL_DONEIEN		(0x1 << 5)
+-
+-#define ATMEL_LCDC_HCRNEXT	0x0368
+-
+-#define ATMEL_LCDC_HCRCFG0	0x036C
+-#define LCDC_HCRCFG0_BLEN_OFFSET	4
+-#define LCDC_HCRCFG0_BLEN		(0x3 << LCDC_HCRCFG0_BLEN_OFFSET)
+-#define		LCDC_HCRCFG0_BLEN_AHB_SINGLE		(0x0 << 4)
+-#define		LCDC_HCRCFG0_BLEN_AHB_INCR4		(0x1 << 4)
+-#define		LCDC_HCRCFG0_BLEN_AHB_INCR8		(0x2 << 4)
+-#define		LCDC_HCRCFG0_BLEN_AHB_INCR16		(0x3 << 4)
+-#define LCDC_HCRCFG0_DLBO		(0x1 << 8)
+-
+-#define ATMEL_LCDC_HCRCFG1	0x0370
+-#define LCDC_HCRCFG1_CLUTEN		(0x1 << 0)
+-#define LCDC_HCRCFG1_RGBMODE_OFFSET	4
+-#define LCDC_HCRCFG1_RGBMODE		(0xf << LCDC_HCRCFG1_RGBMODE_OFFSET)
+-#define		LCDC_HCRCFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
+-#define		LCDC_HCRCFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
+-#define LCDC_HCRCFG1_CLUTMODE_OFFSET	8
+-#define LCDC_HCRCFG1_CLUTMODE		(0x3 << LCDC_HCRCFG1_CLUTMODE_OFFSET)
+-#define		LCDC_HCRCFG1_CLUTMODE_1BPP		(0x0 << 8)
+-#define		LCDC_HCRCFG1_CLUTMODE_2BPP		(0x1 << 8)
+-#define		LCDC_HCRCFG1_CLUTMODE_4BPP		(0x2 << 8)
+-#define		LCDC_HCRCFG1_CLUTMODE_8BPP		(0x3 << 8)
+-
+-#define ATMEL_LCDC_HCRCFG2	0x0374
+-#define LCDC_HCRCFG2_XOFFSET_OFFSET	0
+-#define LCDC_HCRCFG2_XOFFSET		(0x7ff << LCDC_HCRCFG2_XOFFSET_OFFSET)
+-#define LCDC_HCRCFG2_YOFFSET_OFFSET	16
+-#define LCDC_HCRCFG2_YOFFSET		(0x7ff << LCDC_HCRCFG2_YOFFSET_OFFSET)
+-
+-#define ATMEL_LCDC_HCRCFG3	0x0378
+-#define LCDC_HCRCFG3_XSIZE_OFFSET	0
+-#define LCDC_HCRCFG3_XSIZE		(0x7f << LCDC_HCRCFG3_XSIZE_OFFSET)
+-#define LCDC_HCRCFG3_YSIZE_OFFSET	16
+-#define LCDC_HCRCFG3_YSIZE		(0x7f << LCDC_HCRCFG3_YSIZE_OFFSET)
+-
+-#define ATMEL_LCDC_HCRCFG4	0x037C
+-
+-#define ATMEL_LCDC_HCRCFG6	0x0384
+-#define LCDC_HCRCFG6_BDEF_OFFSET	0
+-#define LCDC_HCRCFG6_BDEF		(0xff << LCDC_HCRCFG6_BDEF_OFFSET)
+-#define LCDC_HCRCFG6_GDEF_OFFSET	8
+-#define LCDC_HCRCFG6_GDEF		(0xff << LCDC_HCRCFG6_GDEF_OFFSET)
+-#define LCDC_HCRCFG6_RDEF_OFFSET	16
+-#define LCDC_HCRCFG6_RDEF		(0xff << LCDC_HCRCFG6_RDEF_OFFSET)
+-
+-#define ATMEL_LCDC_HCRCFG7	0x0388
+-#define LCDC_HCRCFG7_BKEY_OFFSET	0
+-#define LCDC_HCRCFG7_BKEY		(0xff << LCDC_HCRCFG7_BKEY_OFFSET)
+-#define LCDC_HCRCFG7_GKEY_OFFSET	8
+-#define LCDC_HCRCFG7_GKEY		(0xff << LCDC_HCRCFG7_GKEY_OFFSET)
+-#define LCDC_HCRCFG7_RKEY_OFFSET	16
+-#define LCDC_HCRCFG7_RKEY		(0xff << LCDC_HCRCFG7_RKEY_OFFSET)
+-
+-#define ATMEL_LCDC_HCRCFG8	0x038C
+-#define LCDC_HCRCFG8_BMASK_OFFSET	0
+-#define LCDC_HCRCFG8_BMASK		(0xff << LCDC_HCRCFG8_BMASK_OFFSET)
+-#define LCDC_HCRCFG8_GMASK_OFFSET	8
+-#define LCDC_HCRCFG8_GMASK		(0xff << LCDC_HCRCFG8_GMASK_OFFSET)
+-#define LCDC_HCRCFG8_RMASK_OFFSET	16
+-#define LCDC_HCRCFG8_RMASK		(0xff << LCDC_HCRCFG8_RMASK_OFFSET)
+-
+-#define ATMEL_LCDC_HCRCFG9	0x0390
+-#define LCDC_HCRCFG9_CRKEY		(0x1 << 0)
+-#define LCDC_HCRCFG9_INV		(0x1 << 1)
+-#define LCDC_HCRCFG9_ITER2BL		(0x1 << 2)
+-#define LCDC_HCRCFG9_ITER		(0x1 << 3)
+-#define LCDC_HCRCFG9_REVALPHA		(0x1 << 4)
+-#define LCDC_HCRCFG9_GAEN		(0x1 << 5)
+-#define LCDC_HCRCFG9_LAEN		(0x1 << 6)
+-#define LCDC_HCRCFG9_OVR		(0x1 << 7)
+-#define LCDC_HCRCFG9_DMA		(0x1 << 8)
+-#define LCDC_HCRCFG9_REP		(0x1 << 9)
+-#define LCDC_HCRCFG9_DSTKEY		(0x1 << 10)
+-#define LCDC_HCRCFG9_GA_OFFSET		16
+-#define LCDC_HCRCFG9_GA_Msk		(0xff << LCDC_HCRCFG9_GA_OFFSET)
+-
+-#define ATMEL_LCDC_BASECLUT	0x400
+-#define LCDC_BASECLUT_BCLUT_OFFSET	0
+-#define LCDC_BASECLUT_BCLUT		(0xff << LCDC_BASECLUT_BCLUT_OFFSET)
+-#define LCDC_BASECLUT_GCLUT_OFFSET	8
+-#define LCDC_BASECLUT_GCLUT		(0xff << LCDC_BASECLUT_GCLUT_OFFSET)
+-#define LCDC_BASECLUT_RCLUT_OFFSET	16
+-#define LCDC_BASECLUT_RCLUT		(0xff << LCDC_BASECLUT_RCLUT_OFFSET)
+-
+-#define ATMEL_LCDC_OVR1CLUT	0x800
+-#define LCDC_OVR1CLUT_BCLUT_OFFSET	0
+-#define LCDC_OVR1CLUT_BCLUT		(0xff << LCDC_OVR1CLUT_BCLUT_OFFSET)
+-#define LCDC_OVR1CLUT_GCLUT_OFFSET	8
+-#define LCDC_OVR1CLUT_GCLUT		(0xff << LCDC_OVR1CLUT_GCLUT_OFFSET)
+-#define LCDC_OVR1CLUT_RCLUT_OFFSET	16
+-#define LCDC_OVR1CLUT_RCLUT		(0xff << LCDC_OVR1CLUT_RCLUT_OFFSET)
+-#define LCDC_OVR1CLUT_ACLUT_OFFSET	24
+-#define LCDC_OVR1CLUT_ACLUT		(0xff << LCDC_OVR1CLUT_ACLUT_OFFSET)
+-
+-#define ATMEL_LCDC_HEOCLUT	0x1000
+-#define LCDC_HEOCLUT_BCLUT_OFFSET	0
+-#define LCDC_HEOCLUT_BCLUT		(0xff << LCDC_HEOCLUT_BCLUT_OFFSET)
+-#define LCDC_HEOCLUT_GCLUT_OFFSET	8
+-#define LCDC_HEOCLUT_GCLUT		(0xff << LCDC_HEOCLUT_GCLUT_OFFSET)
+-#define LCDC_HEOCLUT_RCLUT_OFFSET	16
+-#define LCDC_HEOCLUT_RCLUT		(0xff << LCDC_HEOCLUT_RCLUT_OFFSET)
+-#define LCDC_HEOCLUT_ACLUT_OFFSET	24
+-#define LCDC_HEOCLUT_ACLUT		(0xff << LCDC_HEOCLUT_ACLUT_OFFSET)
+-
+-#define ATMEL_LCDC_HCRCLUT	0x1400
+-#define LCDC_HCRCLUT_BCLUT_OFFSET	0
+-#define LCDC_HCRCLUT_BCLUT		(0xff << LCDC_HCRCLUT_BCLUT_OFFSET)
+-#define LCDC_HCRCLUT_GCLUT_OFFSET	8
+-#define LCDC_HCRCLUT_GCLUT		(0xff << LCDC_HCRCLUT_GCLUT_OFFSET)
+-#define LCDC_HCRCLUT_RCLUT_OFFSET	16
+-#define LCDC_HCRCLUT_RCLUT		(0xff << LCDC_HCRCLUT_RCLUT_OFFSET)
+-#define LCDC_HCRCLUT_ACLUT_OFFSET	24
+-#define LCDC_HCRCLUT_ACLUT		(0xff << LCDC_HCRCLUT_ACLUT_OFFSET)
+-
+-/* Base layer CLUT */
+-#define ATMEL_LCDC_LUT(n)	(0x0400 + ((n)*4))
+-
+-
+-#endif /* __ATMEL_HLCDC4_H__ */
+diff --git a/arch/arm/mach-at91/include/mach/atmel_lcdc.h b/arch/arm/mach-at91/include/mach/atmel_lcdc.h
+new file mode 100644
+index 0000000..248fed3
+--- /dev/null
++++ b/arch/arm/mach-at91/include/mach/atmel_lcdc.h
+@@ -0,0 +1,177 @@
++/*
++ *  Header file for AT91/AT32 LCD Controller
++ *
++ *  Data structure and register user interface
++ *
++ *  Copyright (C) 2007 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#ifndef __MACH_ATMEL_LCDC_H__
++#define __MACH_ATMEL_LCDC_H__
++
++#define ATMEL_LCDC_DMABADDR1	0x00
++#define ATMEL_LCDC_DMABADDR2	0x04
++#define ATMEL_LCDC_DMAFRMPT1	0x08
++#define ATMEL_LCDC_DMAFRMPT2	0x0c
++#define ATMEL_LCDC_DMAFRMADD1	0x10
++#define ATMEL_LCDC_DMAFRMADD2	0x14
++
++#define ATMEL_LCDC_DMAFRMCFG	0x18
++#define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
++#define	ATMEL_LCDC_BLENGTH_OFFSET	24
++#define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
++
++#define ATMEL_LCDC_DMACON	0x1c
++#define	ATMEL_LCDC_DMAEN	(0x1 << 0)
++#define	ATMEL_LCDC_DMARST	(0x1 << 1)
++#define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
++#define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
++#define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
++
++#define ATMEL_LCDC_DMA2DCFG	0x20
++#define		ATMEL_LCDC_ADDRINC_OFFSET	0
++#define		ATMEL_LCDC_ADDRINC		(0xffff)
++#define		ATMEL_LCDC_PIXELOFF_OFFSET	24
++#define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
++
++#define ATMEL_LCDC_LCDCON1	0x0800
++#define	ATMEL_LCDC_BYPASS	(1     <<  0)
++#define	ATMEL_LCDC_CLKVAL_OFFSET	12
++#define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
++#define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
++
++#define ATMEL_LCDC_LCDCON2	0x0804
++#define	ATMEL_LCDC_DISTYPE	(3 << 0)
++#define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
++#define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
++#define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
++#define	ATMEL_LCDC_SCANMOD	(1 << 2)
++#define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
++#define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
++#define	ATMEL_LCDC_IFWIDTH	(3 << 3)
++#define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
++#define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
++#define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
++#define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
++#define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
++#define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
++#define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
++#define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
++#define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
++#define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
++#define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
++#define	ATMEL_LCDC_INVVD	(1 << 8)
++#define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
++#define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
++#define	ATMEL_LCDC_INVFRAME	(1 << 9 )
++#define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
++#define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
++#define	ATMEL_LCDC_INVLINE	(1 << 10)
++#define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
++#define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
++#define	ATMEL_LCDC_INVCLK	(1 << 11)
++#define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
++#define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
++#define	ATMEL_LCDC_INVDVAL	(1 << 12)
++#define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
++#define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
++#define	ATMEL_LCDC_CLKMOD	(1 << 15)
++#define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
++#define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
++#define	ATMEL_LCDC_MEMOR	(1 << 31)
++#define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
++#define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
++
++#define ATMEL_LCDC_TIM1		0x0808
++#define	ATMEL_LCDC_VFP		(0xffU <<  0)
++#define	ATMEL_LCDC_VBP_OFFSET		8
++#define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
++#define	ATMEL_LCDC_VPW_OFFSET		16
++#define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
++#define	ATMEL_LCDC_VHDLY_OFFSET		24
++#define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
++
++#define ATMEL_LCDC_TIM2		0x080c
++#define	ATMEL_LCDC_HBP		(0xffU  <<  0)
++#define	ATMEL_LCDC_HPW_OFFSET		8
++#define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
++#define	ATMEL_LCDC_HFP_OFFSET		21
++#define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
++
++#define ATMEL_LCDC_LCDFRMCFG	0x0810
++#define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
++#define	ATMEL_LCDC_HOZVAL_OFFSET	21
++#define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
++
++#define ATMEL_LCDC_FIFO		0x0814
++#define	ATMEL_LCDC_FIFOTH	(0xffff)
++
++#define ATMEL_LCDC_MVAL		0x0818
++
++#define ATMEL_LCDC_DP1_2	0x081c
++#define ATMEL_LCDC_DP4_7	0x0820
++#define ATMEL_LCDC_DP3_5	0x0824
++#define ATMEL_LCDC_DP2_3	0x0828
++#define ATMEL_LCDC_DP5_7	0x082c
++#define ATMEL_LCDC_DP3_4	0x0830
++#define ATMEL_LCDC_DP4_5	0x0834
++#define ATMEL_LCDC_DP6_7	0x0838
++#define	ATMEL_LCDC_DP1_2_VAL	(0xff)
++#define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
++#define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
++#define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
++#define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
++#define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
++#define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
++#define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
++
++#define ATMEL_LCDC_PWRCON	0x083c
++#define	ATMEL_LCDC_PWR		(1    <<  0)
++#define	ATMEL_LCDC_GUARDT_OFFSET	1
++#define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
++#define	ATMEL_LCDC_BUSY		(1    << 31)
++
++#define ATMEL_LCDC_CONTRAST_CTR	0x0840
++#define	ATMEL_LCDC_PS		(3 << 0)
++#define		ATMEL_LCDC_PS_DIV1		(0 << 0)
++#define		ATMEL_LCDC_PS_DIV2		(1 << 0)
++#define		ATMEL_LCDC_PS_DIV4		(2 << 0)
++#define		ATMEL_LCDC_PS_DIV8		(3 << 0)
++#define	ATMEL_LCDC_POL		(1 << 2)
++#define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
++#define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
++#define	ATMEL_LCDC_ENA		(1 << 3)
++#define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
++#define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
++
++#define ATMEL_LCDC_CONTRAST_VAL	0x0844
++#define	ATMEL_LCDC_CVAL	(0xff)
++
++#define ATMEL_LCDC_IER		0x0848
++#define ATMEL_LCDC_IDR		0x084c
++#define ATMEL_LCDC_IMR		0x0850
++#define ATMEL_LCDC_ISR		0x0854
++#define ATMEL_LCDC_ICR		0x0858
++#define	ATMEL_LCDC_LNI		(1 << 0)
++#define	ATMEL_LCDC_LSTLNI	(1 << 1)
++#define	ATMEL_LCDC_EOFI		(1 << 2)
++#define	ATMEL_LCDC_UFLWI	(1 << 4)
++#define	ATMEL_LCDC_OWRI		(1 << 5)
++#define	ATMEL_LCDC_MERI		(1 << 6)
++
++#define ATMEL_LCDC_LUT		0x0c00
++
++#endif /* __MACH_ATMEL_LCDC_H__ */
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index 7a48e9c..8d7992c 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -19,8 +19,9 @@
+ 
+ #include <mach/board.h>
+ #include <mach/cpu.h>
++#include <mach/atmel_lcdc.h>
+ 
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ /* configurable parameters */
+ #define ATMEL_LCDC_CVAL_DEFAULT		0xc8
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+index 20a4e4f..060d41f 100644
+--- a/drivers/video/atmel_lcdfb_core.c
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -22,7 +22,7 @@
+ #include <mach/cpu.h>
+ #include <mach/gpio.h>
+ 
+-#include <video/atmel_lcdc.h>
++#include <video/atmel_lcdfb.h>
+ 
+ /* configurable parameters */
+ #define ATMEL_LCDC_CVAL_DEFAULT		0xc8
+diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
+deleted file mode 100644
+index 6031b5a..0000000
+--- a/include/video/atmel_lcdc.h
++++ /dev/null
+@@ -1,248 +0,0 @@
+-/*
+- *  Header file for AT91/AT32 LCD Controller
+- *
+- *  Data structure and register user interface
+- *
+- *  Copyright (C) 2007 Atmel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+- */
+-#ifndef __ATMEL_LCDC_H__
+-#define __ATMEL_LCDC_H__
+-
+-#include <linux/workqueue.h>
+-#include <linux/interrupt.h>
+-#include <linux/backlight.h>
+-
+-/* Way LCD wires are connected to the chip:
+- * Some Atmel chips use BGR color mode (instead of standard RGB)
+- * A swapped wiring onboard can bring to RGB mode.
+- */
+-#define ATMEL_LCDC_WIRING_BGR	0
+-#define ATMEL_LCDC_WIRING_RGB	1
+-#define ATMEL_LCDC_WIRING_RGB555	2
+-
+-#define ATMEL_LCDC_STOP_NOWAIT (1 << 0)
+-
+-extern void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo);
+-extern void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo);
+-extern int __atmel_lcdfb_probe(struct platform_device *pdev,
+-				struct atmel_lcdfb_devdata *devdata);
+-extern int __atmel_lcdfb_remove(struct platform_device *pdev);
+-
+-struct atmel_lcdfb_info;
+-
+-struct atmel_lcdfb_devdata {
+-	int (*setup_core)(struct fb_info *info);
+-	void (*start)(struct atmel_lcdfb_info *sinfo);
+-	void (*stop)(struct atmel_lcdfb_info *sinfo, u32 flags);
+-	irqreturn_t (*isr)(int irq, void *dev_id);
+-	void (*update_dma)(struct fb_info *info, struct fb_var_screeninfo *var);
+-	void (*init_contrast)(struct atmel_lcdfb_info *sinfo);
+-	void (*limit_screeninfo)(struct fb_var_screeninfo *var);
+-	const struct backlight_ops *bl_ops;
+-	int fbinfo_flags;
+-	u32 lut_base;
+-};
+-
+- /* LCD Controller info data structure, stored in device platform_data */
+-struct atmel_lcdfb_info {
+-	spinlock_t		lock;
+-	struct fb_info		*info;
+-	void __iomem		*mmio;
+-	int			irq_base;
+-	struct atmel_lcdfb_devdata *dev_data;
+-	struct work_struct	task;
+-
+-	unsigned int		guard_time;
+-	unsigned int 		smem_len;
+-	struct platform_device	*pdev;
+-	struct clk		*bus_clk;
+-	struct clk		*lcdc_clk;
+-
+-#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
+-	struct backlight_device	*backlight;
+-	u8			bl_power;
+-#endif
+-	bool			lcdcon_is_backlight;
+-	bool			lcdcon_pol_negative;
+-	bool			alpha_enabled;
+-	u8			saved_lcdcon;
+-
+-	u8			default_bpp;
+-	u8			lcd_wiring_mode;
+-	unsigned int		default_lcdcon2;
+-	unsigned int		default_dmacon;
+-	void (*atmel_lcdfb_power_control)(int on);
+-	struct fb_monspecs	*default_monspecs;
+-	u32			pseudo_palette[16];
+-};
+-
+-#define lcdc_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
+-#define lcdc_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
+-
+-#define ATMEL_LCDC_DMABADDR1	0x00
+-#define ATMEL_LCDC_DMABADDR2	0x04
+-#define ATMEL_LCDC_DMAFRMPT1	0x08
+-#define ATMEL_LCDC_DMAFRMPT2	0x0c
+-#define ATMEL_LCDC_DMAFRMADD1	0x10
+-#define ATMEL_LCDC_DMAFRMADD2	0x14
+-
+-#define ATMEL_LCDC_DMAFRMCFG	0x18
+-#define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
+-#define	ATMEL_LCDC_BLENGTH_OFFSET	24
+-#define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
+-
+-#define ATMEL_LCDC_DMACON	0x1c
+-#define	ATMEL_LCDC_DMAEN	(0x1 << 0)
+-#define	ATMEL_LCDC_DMARST	(0x1 << 1)
+-#define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
+-#define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
+-#define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
+-
+-#define ATMEL_LCDC_DMA2DCFG	0x20
+-#define		ATMEL_LCDC_ADDRINC_OFFSET	0
+-#define		ATMEL_LCDC_ADDRINC		(0xffff)
+-#define		ATMEL_LCDC_PIXELOFF_OFFSET	24
+-#define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
+-
+-#define ATMEL_LCDC_LCDCON1	0x0800
+-#define	ATMEL_LCDC_BYPASS	(1     <<  0)
+-#define	ATMEL_LCDC_CLKVAL_OFFSET	12
+-#define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
+-#define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
+-
+-#define ATMEL_LCDC_LCDCON2	0x0804
+-#define	ATMEL_LCDC_DISTYPE	(3 << 0)
+-#define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
+-#define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
+-#define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
+-#define	ATMEL_LCDC_SCANMOD	(1 << 2)
+-#define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
+-#define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
+-#define	ATMEL_LCDC_IFWIDTH	(3 << 3)
+-#define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
+-#define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
+-#define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
+-#define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
+-#define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
+-#define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
+-#define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
+-#define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
+-#define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
+-#define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
+-#define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
+-#define	ATMEL_LCDC_INVVD	(1 << 8)
+-#define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
+-#define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
+-#define	ATMEL_LCDC_INVFRAME	(1 << 9 )
+-#define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
+-#define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
+-#define	ATMEL_LCDC_INVLINE	(1 << 10)
+-#define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
+-#define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
+-#define	ATMEL_LCDC_INVCLK	(1 << 11)
+-#define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
+-#define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
+-#define	ATMEL_LCDC_INVDVAL	(1 << 12)
+-#define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
+-#define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
+-#define	ATMEL_LCDC_CLKMOD	(1 << 15)
+-#define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
+-#define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
+-#define	ATMEL_LCDC_MEMOR	(1 << 31)
+-#define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
+-#define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
+-
+-#define ATMEL_LCDC_TIM1		0x0808
+-#define	ATMEL_LCDC_VFP		(0xffU <<  0)
+-#define	ATMEL_LCDC_VBP_OFFSET		8
+-#define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
+-#define	ATMEL_LCDC_VPW_OFFSET		16
+-#define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
+-#define	ATMEL_LCDC_VHDLY_OFFSET		24
+-#define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
+-
+-#define ATMEL_LCDC_TIM2		0x080c
+-#define	ATMEL_LCDC_HBP		(0xffU  <<  0)
+-#define	ATMEL_LCDC_HPW_OFFSET		8
+-#define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
+-#define	ATMEL_LCDC_HFP_OFFSET		21
+-#define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
+-
+-#define ATMEL_LCDC_LCDFRMCFG	0x0810
+-#define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
+-#define	ATMEL_LCDC_HOZVAL_OFFSET	21
+-#define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
+-
+-#define ATMEL_LCDC_FIFO		0x0814
+-#define	ATMEL_LCDC_FIFOTH	(0xffff)
+-
+-#define ATMEL_LCDC_MVAL		0x0818
+-
+-#define ATMEL_LCDC_DP1_2	0x081c
+-#define ATMEL_LCDC_DP4_7	0x0820
+-#define ATMEL_LCDC_DP3_5	0x0824
+-#define ATMEL_LCDC_DP2_3	0x0828
+-#define ATMEL_LCDC_DP5_7	0x082c
+-#define ATMEL_LCDC_DP3_4	0x0830
+-#define ATMEL_LCDC_DP4_5	0x0834
+-#define ATMEL_LCDC_DP6_7	0x0838
+-#define	ATMEL_LCDC_DP1_2_VAL	(0xff)
+-#define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
+-#define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
+-#define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
+-#define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
+-#define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
+-#define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
+-#define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
+-
+-#define ATMEL_LCDC_PWRCON	0x083c
+-#define	ATMEL_LCDC_PWR		(1    <<  0)
+-#define	ATMEL_LCDC_GUARDT_OFFSET	1
+-#define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
+-#define	ATMEL_LCDC_BUSY		(1    << 31)
+-
+-#define ATMEL_LCDC_CONTRAST_CTR	0x0840
+-#define	ATMEL_LCDC_PS		(3 << 0)
+-#define		ATMEL_LCDC_PS_DIV1		(0 << 0)
+-#define		ATMEL_LCDC_PS_DIV2		(1 << 0)
+-#define		ATMEL_LCDC_PS_DIV4		(2 << 0)
+-#define		ATMEL_LCDC_PS_DIV8		(3 << 0)
+-#define	ATMEL_LCDC_POL		(1 << 2)
+-#define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
+-#define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
+-#define	ATMEL_LCDC_ENA		(1 << 3)
+-#define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
+-#define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
+-
+-#define ATMEL_LCDC_CONTRAST_VAL	0x0844
+-#define	ATMEL_LCDC_CVAL	(0xff)
+-
+-#define ATMEL_LCDC_IER		0x0848
+-#define ATMEL_LCDC_IDR		0x084c
+-#define ATMEL_LCDC_IMR		0x0850
+-#define ATMEL_LCDC_ISR		0x0854
+-#define ATMEL_LCDC_ICR		0x0858
+-#define	ATMEL_LCDC_LNI		(1 << 0)
+-#define	ATMEL_LCDC_LSTLNI	(1 << 1)
+-#define	ATMEL_LCDC_EOFI		(1 << 2)
+-#define	ATMEL_LCDC_UFLWI	(1 << 4)
+-#define	ATMEL_LCDC_OWRI		(1 << 5)
+-#define	ATMEL_LCDC_MERI		(1 << 6)
+-
+-#define ATMEL_LCDC_LUT		0x0c00
+-
+-#endif /* __ATMEL_LCDC_H__ */
+diff --git a/include/video/atmel_lcdfb.h b/include/video/atmel_lcdfb.h
+new file mode 100644
+index 0000000..3a0dfc7
+--- /dev/null
++++ b/include/video/atmel_lcdfb.h
+@@ -0,0 +1,100 @@
++/*
++ *  Header file for AT91/AT32 LCD Controller
++ *
++ *  Data structure and register user interface
++ *
++ *  Copyright (C) 2007 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#ifndef __ATMEL_LCDC_H__
++#define __ATMEL_LCDC_H__
++
++#include <linux/workqueue.h>
++#include <linux/interrupt.h>
++#include <linux/backlight.h>
++
++/* Way LCD wires are connected to the chip:
++ * Some Atmel chips use BGR color mode (instead of standard RGB)
++ * A swapped wiring onboard can bring to RGB mode.
++ */
++#define ATMEL_LCDC_WIRING_BGR	0
++#define ATMEL_LCDC_WIRING_RGB	1
++#define ATMEL_LCDC_WIRING_RGB555	2
++
++#define ATMEL_LCDC_STOP_NOWAIT (1 << 0)
++
++struct atmel_lcdfb_info;
++
++struct atmel_lcdfb_devdata {
++	int (*setup_core)(struct fb_info *info);
++	void (*start)(struct atmel_lcdfb_info *sinfo);
++	void (*stop)(struct atmel_lcdfb_info *sinfo, u32 flags);
++	irqreturn_t (*isr)(int irq, void *dev_id);
++	void (*update_dma)(struct fb_info *info, struct fb_var_screeninfo *var);
++	void (*init_contrast)(struct atmel_lcdfb_info *sinfo);
++	void (*limit_screeninfo)(struct fb_var_screeninfo *var);
++	const struct backlight_ops *bl_ops;
++	int fbinfo_flags;
++	u32 lut_base;
++	int dma_desc_size;
++};
++
++extern void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo);
++extern void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo);
++extern int __atmel_lcdfb_probe(struct platform_device *pdev,
++				struct atmel_lcdfb_devdata *devdata);
++extern int __atmel_lcdfb_remove(struct platform_device *pdev);
++
++ /* LCD Controller info data structure, stored in device platform_data */
++struct atmel_lcdfb_info {
++	spinlock_t		lock;
++	struct fb_info		*info;
++	void __iomem		*mmio;
++	int			irq_base;
++	struct atmel_lcdfb_devdata *dev_data;
++	struct work_struct	task;
++
++	void			*dma_desc;
++	dma_addr_t		dma_desc_phys;
++
++	unsigned int		guard_time;
++	unsigned int 		smem_len;
++	struct platform_device	*pdev;
++	struct clk		*bus_clk;
++	struct clk		*lcdc_clk;
++
++#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
++	struct backlight_device	*backlight;
++	u8			bl_power;
++#endif
++	bool			lcdcon_is_backlight;
++	bool			lcdcon_pol_negative;
++	bool			alpha_enabled;
++	u8			saved_lcdcon;
++
++	u8			default_bpp;
++	u8			lcd_wiring_mode;
++	unsigned int		default_lcdcon2;
++	unsigned int		default_dmacon;
++	void (*atmel_lcdfb_power_control)(int on);
++	struct fb_monspecs	*default_monspecs;
++	u32			pseudo_palette[16];
++};
++
++#define lcdc_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
++#define lcdc_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
++
++#endif /* __ATMEL_LCDC_H__ */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0082-video-atmel_hlcdfb-add-new-driver.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0082-video-atmel_hlcdfb-add-new-driver.patch
new file mode 100644
index 0000000..73f8a47
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0082-video-atmel_hlcdfb-add-new-driver.patch
@@ -0,0 +1,606 @@
+From 27ccf3bffa571397ccd64704334c60a0687bfdef Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Mon, 23 May 2011 15:36:52 +0200
+Subject: [PATCH 082/107] video: atmel_hlcdfb: add new driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/Kconfig            |    9 +
+ drivers/video/Makefile           |    1 +
+ drivers/video/atmel_hlcdfb.c     |  514 ++++++++++++++++++++++++++++++++++++++
+ drivers/video/atmel_lcdfb_core.c |   15 ++
+ 4 files changed, 539 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/atmel_hlcdfb.c
+
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index e6a8d8c..8b25a8e 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -1022,6 +1022,15 @@ config FB_ATMEL_STN
+ 
+ 	  If unsure, say N.
+ 
++config FB_ATMEL_HLCD
++	tristate "AT91 HLCD Controller support"
++	depends on FB && HAVE_FB_ATMEL
++	select FB_CFB_FILLRECT
++	select FB_CFB_COPYAREA
++	select FB_CFB_IMAGEBLIT
++	help
++	  This enables support for the AT91 HLCD Controller.
++
+ config FB_NVIDIA
+ 	tristate "nVidia Framebuffer Support"
+ 	depends on FB && PCI
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index e963559..2597768 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -92,6 +92,7 @@ obj-$(CONFIG_FB_SA1100)           += sa1100fb.o
+ obj-$(CONFIG_FB_HIT)              += hitfb.o
+ obj-$(CONFIG_FB_EPSON1355)	  += epson1355fb.o
+ obj-$(CONFIG_FB_ATMEL)		  += atmel_lcdfb.o atmel_lcdfb_core.o
++obj-$(CONFIG_FB_ATMEL_HLCD)	  += atmel_hlcdfb.o atmel_lcdfb_core.o
+ obj-$(CONFIG_FB_PVR2)             += pvr2fb.o
+ obj-$(CONFIG_FB_VOODOO1)          += sstfb.o
+ obj-$(CONFIG_FB_ARMCLCD)	  += amba-clcd.o
+diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
+new file mode 100644
+index 0000000..b772841
+--- /dev/null
++++ b/drivers/video/atmel_hlcdfb.c
+@@ -0,0 +1,514 @@
++/*
++ *  Driver for AT91/AT32 LCD Controller
++ *
++ *  Copyright (C) 2007 Atmel Corporation
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file COPYING in the main directory of this archive for
++ * more details.
++ */
++
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/backlight.h>
++#include <linux/fb.h>
++#include <linux/clk.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++
++#include <mach/board.h>
++#include <mach/cpu.h>
++#include <mach/atmel_hlcdc.h>
++#include <mach/atmel_hlcdc_ovl.h>
++
++#include <video/atmel_lcdfb.h>
++
++#define	ATMEL_LCDFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
++					 | FBINFO_PARTIAL_PAN_OK \
++					 | FBINFO_HWACCEL_YPAN)
++
++#define ATMEL_LCDC_CVAL_DEFAULT         0xc8
++
++struct atmel_hlcd_dma_desc {
++	u32	address;
++	u32	control;
++	u32	next;
++};
++
++static void atmel_hlcdfb_update_dma_base(struct fb_info *info,
++
++			       struct fb_var_screeninfo *var)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++	struct fb_fix_screeninfo *fix = &info->fix;
++	unsigned long dma_addr;
++	struct atmel_hlcd_dma_desc *desc;
++
++	dma_addr = (fix->smem_start + var->yoffset * fix->line_length
++		    + var->xoffset * var->bits_per_pixel / 8);
++
++	dma_addr &= ~3UL;
++
++	/* Setup the DMA descriptor, this descriptor will loop to itself */
++	desc = sinfo->dma_desc;
++
++	desc->address = dma_addr;
++	/* Disable DMA transfer interrupt & descriptor loaded interrupt. */
++	desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
++			| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
++	desc->next = sinfo->dma_desc_phys;
++
++	lcdc_writel(sinfo, ATMEL_LCDC_BASEADDR, dma_addr);
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECTRL, desc->control);
++	lcdc_writel(sinfo, ATMEL_LCDC_BASENEXT, sinfo->dma_desc_phys);
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECHER, LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN);
++}
++
++static void atmel_hlcdfb_update_dma_ovl(struct fb_info *info,
++			       struct fb_var_screeninfo *var)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++	struct fb_fix_screeninfo *fix = &info->fix;
++	unsigned long dma_addr;
++	struct atmel_hlcd_dma_desc *desc;
++
++	dma_addr = (fix->smem_start + var->yoffset * fix->line_length
++		    + var->xoffset * var->bits_per_pixel / 8);
++
++	dma_addr &= ~3UL;
++
++	/* Setup the DMA descriptor, this descriptor will loop to itself */
++	desc = sinfo->dma_desc;
++
++	desc->address = dma_addr;
++	/* Disable DMA transfer interrupt & descriptor loaded interrupt. */
++	desc->control = LCDC_OVRCTRL1_ADDIEN | LCDC_OVRCTRL1_DSCRIEN
++			| LCDC_OVRCTRL1_DMAIEN | LCDC_OVRCTRL1_DFETCH;
++	desc->next = sinfo->dma_desc_phys;
++
++	lcdc_writel(sinfo, ATMEL_LCDC_OVRADDR1, dma_addr);
++	lcdc_writel(sinfo, ATMEL_LCDC_OVRCTRL1, desc->control);
++	lcdc_writel(sinfo, ATMEL_LCDC_OVRNEXT1, sinfo->dma_desc_phys);
++	lcdc_writel(sinfo, ATMEL_LCDC_OVRCHER1, LCDC_OVRCHER1_CHEN | LCDC_OVRCHER1_UPDATEEN);
++}
++
++/* some bl->props field just changed */
++static int atmel_bl_update_status(struct backlight_device *bl)
++{
++	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
++	int power = sinfo->bl_power;
++	int brightness = bl->props.brightness;
++	u32 reg;
++
++	/* REVISIT there may be a meaningful difference between
++	 * fb_blank and power ... there seem to be some cases
++	 * this doesn't handle correctly.
++	 */
++	if (bl->props.fb_blank != sinfo->bl_power)
++		power = bl->props.fb_blank;
++	else if (bl->props.power != sinfo->bl_power)
++		power = bl->props.power;
++
++	if (brightness < 0 && power == FB_BLANK_UNBLANK)
++		brightness = lcdc_readl(sinfo, ATMEL_LCDC_LCDCFG6)
++			     >> LCDC_LCDCFG6_PWMCVAL_OFFSET;
++	else if (power != FB_BLANK_UNBLANK)
++		brightness = 0;
++
++	reg = lcdc_readl(sinfo, ATMEL_LCDC_LCDCFG6) & ~LCDC_LCDCFG6_PWMCVAL;
++	reg |= brightness << LCDC_LCDCFG6_PWMCVAL_OFFSET;
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG6, reg);
++
++	bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
++
++	return 0;
++}
++
++static int atmel_bl_get_brightness(struct backlight_device *bl)
++{
++	struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
++
++	return lcdc_readl(sinfo, ATMEL_LCDC_LCDCFG6) >> LCDC_LCDCFG6_PWMCVAL_OFFSET;
++}
++
++static const struct backlight_ops atmel_hlcdc_bl_ops = {
++	.update_status = atmel_bl_update_status,
++	.get_brightness = atmel_bl_get_brightness,
++};
++
++static void atmel_hlcdfb_init_contrast(struct atmel_lcdfb_info *sinfo)
++{
++	/* have some default contrast/backlight settings */
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG6, LCDC_LCDCFG6_PWMPOL |
++		(ATMEL_LCDC_CVAL_DEFAULT << LCDC_LCDCFG6_PWMCVAL_OFFSET));
++}
++
++void atmel_hlcdfb_start(struct atmel_lcdfb_info *sinfo)
++{
++	u32 value;
++
++	value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_CLKEN);
++	while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_CLKSTS))
++		msleep(1);
++	value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_SYNCEN);
++	while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_LCDSTS))
++		msleep(1);
++	value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_DISPEN);
++	while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_DISPSTS))
++		msleep(1);
++	value = lcdc_readl(sinfo, ATMEL_LCDC_LCDEN);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, value | LCDC_LCDEN_PWMEN);
++	while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_PWMSTS))
++		msleep(1);
++}
++
++static void atmel_hlcdfb_stop(struct atmel_lcdfb_info *sinfo, u32 flags)
++{
++	/* Disable DISP signal */
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_DISPDIS);
++	while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_DISPSTS))
++		msleep(1);
++	/* Disable synchronization */
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_SYNCDIS);
++	while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_LCDSTS))
++		msleep(1);
++	/* Disable pixel clock */
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_CLKDIS);
++	while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_CLKSTS))
++		msleep(1);
++	/* Disable PWM */
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_PWMDIS);
++	while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_PWMSTS))
++		msleep(1);
++
++	if (!(flags & ATMEL_LCDC_STOP_NOWAIT))
++		/* Wait for the end of DMA transfer */
++		while (!(lcdc_readl(sinfo, ATMEL_LCDC_BASEISR) & LCDC_BASEISR_DMA))
++			msleep(10);
++		//FIXME: OVL DMA?
++}
++
++static u32 atmel_hlcdfb_get_rgbmode(struct fb_info *info)
++{
++	u32 value = 0;
++
++	switch (info->var.bits_per_pixel) {
++	case 1:
++		value = LCDC_BASECFG1_CLUTMODE_1BPP | LCDC_BASECFG1_CLUTEN;
++		break;
++	case 2:
++		value = LCDC_BASECFG1_CLUTMODE_2BPP | LCDC_BASECFG1_CLUTEN;
++		break;
++	case 4:
++		value = LCDC_BASECFG1_CLUTMODE_4BPP | LCDC_BASECFG1_CLUTEN;
++		break;
++	case 8:
++		value = LCDC_BASECFG1_CLUTMODE_8BPP | LCDC_BASECFG1_CLUTEN;
++		break;
++	case 12:
++		value = LCDC_BASECFG1_RGBMODE_12BPP_RGB_444;
++		break;
++	case 16:
++		if (info->var.transp.offset)
++			value = LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444;
++		else
++			value = LCDC_BASECFG1_RGBMODE_16BPP_RGB_565;
++		break;
++	case 18:
++		value = LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED;
++		break;
++	case 24:
++		value = LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED;
++		break;
++	case 32:
++		value = LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888;
++		break;
++	default:
++		dev_err(info->device, "Cannot set video mode for %dbpp\n",
++			info->var.bits_per_pixel);
++		break;
++	}
++
++	return value;
++}
++
++static int atmel_hlcdfb_setup_core_base(struct fb_info *info)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++	unsigned long value;
++	unsigned long clk_value_khz;
++
++	dev_dbg(info->device, "%s:\n", __func__);
++	/* Set pixel clock */
++	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
++
++	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
++
++	if (value < 1) {
++		dev_notice(info->device, "using system clock as pixel clock\n");
++		value = LCDC_LCDCFG0_CLKPOL | LCDC_LCDCFG0_CLKPWMSEL | LCDC_LCDCFG0_CGDISBASE;
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG0, value);
++	} else {
++		info->var.pixclock = KHZ2PICOS(clk_value_khz / value);
++		dev_dbg(info->device, "  updated pixclk:     %lu KHz\n",
++				PICOS2KHZ(info->var.pixclock));
++		value = value - 2;
++		dev_dbg(info->device, "  * programming CLKDIV = 0x%08lx\n",
++					value);
++		value = (value << LCDC_LCDCFG0_CLKDIV_OFFSET)
++			| LCDC_LCDCFG0_CLKPOL
++			| LCDC_LCDCFG0_CGDISBASE;
++		lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG0, value);
++	}
++
++	/* Initialize control register 5 */
++	/* In 9x5, the default_lcdcon2 will use for LCDCFG5 */
++	value = sinfo->default_lcdcon2;
++	value |= (sinfo->guard_time << LCDC_LCDCFG5_GUARDTIME_OFFSET)
++		| LCDC_LCDCFG5_DISPDLY
++		| LCDC_LCDCFG5_VSPDLYS;
++
++	if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
++		value |= LCDC_LCDCFG5_HSPOL;
++	if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
++		value |= LCDC_LCDCFG5_VSPOL;
++
++	dev_dbg(info->device, "  * LCDC_LCDCFG5 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG5, value);
++
++	/* Vertical & Horizontal Timing */
++	value = (info->var.vsync_len - 1) << LCDC_LCDCFG1_VSPW_OFFSET;
++	value |= (info->var.hsync_len - 1) << LCDC_LCDCFG1_HSPW_OFFSET;
++	dev_dbg(info->device, "  * LCDC_LCDCFG1 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG1, value);
++
++	value = (info->var.lower_margin) << LCDC_LCDCFG2_VBPW_OFFSET;
++	value |= (info->var.upper_margin - 1) << LCDC_LCDCFG2_VFPW_OFFSET;
++	dev_dbg(info->device, "  * LCDC_LCDCFG2 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG2, value);
++
++	value = (info->var.right_margin - 1) << LCDC_LCDCFG3_HBPW_OFFSET;
++	value |= (info->var.left_margin - 1) << LCDC_LCDCFG3_HFPW_OFFSET;
++	dev_dbg(info->device, "  * LCDC_LCDCFG3 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG3, value);
++
++	/* Display size */
++	value = (info->var.yres - 1) << LCDC_LCDCFG4_RPF_OFFSET;
++	value |= (info->var.xres - 1) << LCDC_LCDCFG4_PPL_OFFSET;
++	dev_dbg(info->device, "  * LCDC_LCDCFG4 = %08lx\n", value);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG4, value);
++
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG0, LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG1, atmel_hlcdfb_get_rgbmode(info));
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG2, 0);
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG3, 0);	/* Default color */
++	lcdc_writel(sinfo, ATMEL_LCDC_BASECFG4, LCDC_BASECFG4_DMA);
++
++	/* Disable all interrupts */
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDIDR, ~0UL);
++	lcdc_writel(sinfo, ATMEL_LCDC_BASEIDR, ~0UL);
++	/* Enable BASE LAYER overflow interrupts, if want to enable DMA interrupt, also need set it at LCDC_BASECTRL reg */
++	lcdc_writel(sinfo, ATMEL_LCDC_BASEIER, LCDC_BASEIER_OVR);
++	//FIXME: Let video-driver register a callback
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDIER, LCDC_LCDIER_FIFOERRIE |
++				LCDC_LCDIER_BASEIE | LCDC_LCDIER_HEOIE);
++
++	return 0;
++}
++
++static int atmel_hlcdfb_setup_core_ovl(struct fb_info *info)
++{
++	struct atmel_lcdfb_info *sinfo = info->par;
++	u32 xpos, ypos, xres, yres, cfg9;
++
++	if (info->var.nonstd >> 31) {
++		xpos = (info->var.nonstd >> 10) & 0x3ff;
++		ypos = info->var.nonstd & 0x3ff;
++		xres = info->var.xres ? info->var.xres - 1 : 0;
++		yres = info->var.yres ? info->var.yres - 1 : 0;
++		cfg9 =  LCDC_OVR1CFG9_DMA | LCDC_OVR1CFG9_OVR |
++			LCDC_OVR1CFG9_ITER | LCDC_OVR1CFG9_ITER2BL |
++			LCDC_OVR1CFG9_REP;
++		if (info->var.transp.offset)
++			cfg9 |= LCDC_OVR1CFG9_LAEN;
++		else
++			cfg9 |= LCDC_OVR1CFG9_GAEN | LCDC_OVR1CFG9_GA;
++	} else {
++		xpos = ypos = yres = xres = cfg9 = 0;
++	}
++
++	lcdc_writel(sinfo, ATMEL_LCDC_OVR1CFG0,
++			LCDC_OVR1CFG0_BLEN_AHB_INCR4 | LCDC_OVR1CFG0_DLBO);
++	lcdc_writel(sinfo, ATMEL_LCDC_OVR1CFG1,
++			atmel_hlcdfb_get_rgbmode(info));
++	lcdc_writel(sinfo, ATMEL_LCDC_OVR1CFG2, xpos |
++			(ypos << LCDC_OVR1CFG2_YOFFSET_OFFSET));
++	lcdc_writel(sinfo, ATMEL_LCDC_OVR1CFG3, xres |
++			(yres << LCDC_OVR1CFG3_YSIZE_OFFSET));
++	lcdc_writel(sinfo, ATMEL_LCDC_OVR1CFG9, cfg9);
++
++	return 0;
++}
++static void atmelfb_limit_screeninfo(struct fb_var_screeninfo *var)
++{
++	/* Saturate vertical and horizontal timings at maximum values */
++	var->vsync_len = min_t(u32, var->vsync_len,
++			(LCDC_LCDCFG1_VSPW >> LCDC_LCDCFG1_VSPW_OFFSET) + 1);
++	var->upper_margin = min_t(u32, var->upper_margin,
++			(LCDC_LCDCFG2_VFPW >> LCDC_LCDCFG2_VFPW_OFFSET) + 1);
++	var->lower_margin = min_t(u32, var->lower_margin,
++			LCDC_LCDCFG2_VBPW >> LCDC_LCDCFG2_VBPW_OFFSET);
++	var->right_margin = min_t(u32, var->right_margin,
++			(LCDC_LCDCFG3_HBPW >> LCDC_LCDCFG3_HBPW_OFFSET) + 1);
++	var->hsync_len = min_t(u32, var->hsync_len,
++			(LCDC_LCDCFG1_HSPW >> LCDC_LCDCFG1_HSPW_OFFSET) + 1);
++	var->left_margin = min_t(u32, var->left_margin,
++			(LCDC_LCDCFG3_HFPW >> LCDC_LCDCFG3_HFPW_OFFSET) + 1);
++
++}
++
++static irqreturn_t atmel_hlcdfb_interrupt(int irq, void *dev_id)
++{
++	struct fb_info *info = dev_id;
++	struct atmel_lcdfb_info *sinfo = info->par;
++	u32 status, baselayer_status;
++
++	/* Check for error status via interrupt.*/
++	status = lcdc_readl(sinfo, ATMEL_LCDC_LCDISR);
++	if (status & LCDC_LCDISR_HEO)
++		return IRQ_NONE;
++
++	if (status & LCDC_LCDISR_FIFOERR)
++		dev_warn(info->device, "FIFO underflow %#x\n", status);
++
++	if (status & LCDC_LCDISR_BASE) {
++		/* Check base layer's overflow error. */
++		baselayer_status = lcdc_readl(sinfo, ATMEL_LCDC_BASEISR);
++
++		if (baselayer_status & LCDC_BASEISR_OVR)
++			dev_warn(info->device, "base layer overflow %#x\n",
++						baselayer_status);
++	}
++
++	return IRQ_HANDLED;
++}
++
++
++#ifdef CONFIG_PM
++
++static int atmel_hlcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
++{
++	struct fb_info *info = platform_get_drvdata(pdev);
++	struct atmel_lcdfb_info *sinfo = info->par;
++
++	/*
++	 * We don't want to handle interrupts while the clock is
++	 * stopped. It may take forever.
++	 */
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDIDR, ~0UL);
++	lcdc_writel(sinfo, ATMEL_LCDC_BASEIDR, ~0UL);
++
++	if (sinfo->atmel_lcdfb_power_control)
++		sinfo->atmel_lcdfb_power_control(0);
++
++	atmel_hlcdfb_stop(sinfo, 0);
++	atmel_lcdfb_stop_clock(sinfo);
++
++	return 0;
++}
++
++static int atmel_hlcdfb_resume(struct platform_device *pdev)
++{
++	struct fb_info *info = platform_get_drvdata(pdev);
++	struct atmel_lcdfb_info *sinfo = info->par;
++
++	atmel_lcdfb_start_clock(sinfo);
++	atmel_hlcdfb_start(sinfo);
++	if (sinfo->atmel_lcdfb_power_control)
++		sinfo->atmel_lcdfb_power_control(1);
++
++	/* Enable fifo error & BASE LAYER overflow interrupts */
++	lcdc_writel(sinfo, ATMEL_LCDC_BASEIER, LCDC_BASEIER_OVR);
++	lcdc_writel(sinfo, ATMEL_LCDC_LCDIER, LCDC_LCDIER_FIFOERRIE |
++				LCDC_LCDIER_BASEIE | LCDC_LCDIER_HEOIE);
++
++	return 0;
++}
++
++#else
++#define atmel_hlcdfb_suspend	NULL
++#define atmel_hlcdfb_resume	NULL
++#endif
++
++static struct atmel_lcdfb_devdata dev_data_base = {
++	.setup_core = atmel_hlcdfb_setup_core_base,
++	.start = atmel_hlcdfb_start,
++	.stop = atmel_hlcdfb_stop,
++	.isr = atmel_hlcdfb_interrupt,
++	.update_dma = atmel_hlcdfb_update_dma_base,
++	.bl_ops = &atmel_hlcdc_bl_ops,
++	.init_contrast = atmel_hlcdfb_init_contrast,
++	.limit_screeninfo = atmelfb_limit_screeninfo,
++	.fbinfo_flags = ATMEL_LCDFB_FBINFO_DEFAULT,
++	.lut_base = ATMEL_HLCDC_LUT,
++	.dma_desc_size = sizeof(struct atmel_hlcd_dma_desc),
++};
++
++static struct atmel_lcdfb_devdata dev_data_ovl = {
++	.setup_core = atmel_hlcdfb_setup_core_ovl,
++	.update_dma = atmel_hlcdfb_update_dma_ovl,
++	.limit_screeninfo = atmelfb_limit_screeninfo,
++	.fbinfo_flags = ATMEL_LCDFB_FBINFO_DEFAULT,
++	.lut_base = 0x800, //FIXME: add define
++	.dma_desc_size = sizeof(struct atmel_hlcd_dma_desc),
++};
++
++static const struct platform_device_id atmelfb_dev_table[] = {
++	{ "atmel_hlcdfb_base", (kernel_ulong_t)&dev_data_base },
++	{ "atmel_hlcdfb_ovl", (kernel_ulong_t)&dev_data_ovl },
++}
++MODULE_DEVICE_TABLE(platform, atmelfb_dev_table);
++
++static int __init atmel_hlcdfb_probe(struct platform_device *pdev)
++{
++	const struct platform_device_id *id = platform_get_device_id(pdev);
++
++	return __atmel_lcdfb_probe(pdev, (struct atmel_lcdfb_devdata *)id->driver_data);
++}
++static int __exit atmel_hlcdfb_remove(struct platform_device *pdev)
++{
++	return __atmel_lcdfb_remove(pdev);
++}
++
++static struct platform_driver atmel_hlcdfb_driver = {
++	.remove		= __exit_p(atmel_hlcdfb_remove),
++	.suspend	= atmel_hlcdfb_suspend,
++	.resume		= atmel_hlcdfb_resume,
++
++	.driver		= {
++		.name	= "atmel_hlcdfb",
++		.owner	= THIS_MODULE,
++	},
++	.id_table	= atmelfb_dev_table,
++};
++
++static int __init atmel_hlcdfb_init(void)
++{
++	return platform_driver_probe(&atmel_hlcdfb_driver, atmel_hlcdfb_probe);
++}
++module_init(atmel_hlcdfb_init);
++
++static void __exit atmel_hlcdfb_exit(void)
++{
++	platform_driver_unregister(&atmel_hlcdfb_driver);
++}
++module_exit(atmel_hlcdfb_exit);
++
++MODULE_DESCRIPTION("AT91 HLCD Controller framebuffer driver");
++MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com> "
++		"and Wolfram Sang <w.sang@pengutronix.de");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+index 060d41f..cd57361 100644
+--- a/drivers/video/atmel_lcdfb_core.c
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -90,6 +90,10 @@ static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
+ 
+ 	dma_free_writecombine(info->device, info->fix.smem_len,
+ 				info->screen_base, info->fix.smem_start);
++
++	if (sinfo->dev_data->dma_desc_size && sinfo->dma_desc)
++		dma_free_writecombine(info->device, sinfo->dev_data->dma_desc_size,
++						sinfo->dma_desc, sinfo->dma_desc_phys);
+ }
+ 
+ /**
+@@ -118,6 +122,17 @@ static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
+ 
+ 	memset(info->screen_base, 0, info->fix.smem_len);
+ 
++	if (sinfo->dev_data->dma_desc_size) {
++		sinfo->dma_desc = dma_alloc_writecombine(info->device,
++					sinfo->dev_data->dma_desc_size,
++					&(sinfo->dma_desc_phys), GFP_KERNEL);
++
++		if (!sinfo->dma_desc) {
++			dma_free_writecombine(info->device, info->fix.smem_len,
++						info->screen_base, info->fix.smem_start);
++			return -ENOMEM;
++		}
++	}
+ 	return 0;
+ }
+ 
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0083-arm-at91-sam9x5-use-new-hlcdc-driver.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0083-arm-at91-sam9x5-use-new-hlcdc-driver.patch
new file mode 100644
index 0000000..1327181
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0083-arm-at91-sam9x5-use-new-hlcdc-driver.patch
@@ -0,0 +1,30 @@
+From 094052d49cb1fedf9eabd0aa628f4bb52ad9e945 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Mon, 6 Jun 2011 22:04:17 +0200
+Subject: [PATCH 083/107] arm: at91: sam9x5: use new hlcdc-driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/mach-at91/at91sam9x5_devices.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
+index 36a192a..ee4278d 100644
+--- a/arch/arm/mach-at91/at91sam9x5_devices.c
++++ b/arch/arm/mach-at91/at91sam9x5_devices.c
+@@ -1024,7 +1024,7 @@ static struct resource lcdc_resources[] = {
+ };
+ 
+ static struct platform_device at91_lcdc_device = {
+-	.name		= "atmel_lcdfb",
++	.name		= "atmel_hlcdfb",
+ 	.id		= 0,
+ 	.dev		= {
+ 				.dma_mask		= &lcdc_dmamask,
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0084-arm-at91-sam9x5ek-use-16bpp-as-default-for-fb.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0084-arm-at91-sam9x5ek-use-16bpp-as-default-for-fb.patch
new file mode 100644
index 0000000..4f2acfc
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0084-arm-at91-sam9x5ek-use-16bpp-as-default-for-fb.patch
@@ -0,0 +1,34 @@
+From 279b0e3f969ace5f1cee3eca57610f300de47ec7 Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Mon, 6 Jun 2011 22:06:03 +0200
+Subject: [PATCH 084/107] arm: at91: sam9x5ek: use 16bpp as default for fb
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Also reserve enough memory for 32bpp.
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/mach-at91/board-sam9x5ek.c |    4 +++-
+ 1 files changed, 3 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-at91/board-sam9x5ek.c b/arch/arm/mach-at91/board-sam9x5ek.c
+index a005b69..54fd7cc 100644
+--- a/arch/arm/mach-at91/board-sam9x5ek.c
++++ b/arch/arm/mach-at91/board-sam9x5ek.c
+@@ -150,7 +150,9 @@ static struct fb_monspecs at91fb_default_monspecs = {
+ static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
+ 	.lcdcon_is_backlight		= true,
+ 	.alpha_enabled			= false,
+-	.default_bpp			= 24,
++	.default_bpp			= 16,
++	/* Reserve enough memory for 32bpp */
++	.smem_len			= 800 * 480 * 4,
+ 	/* In 9x5 default_lcdcon2 is used for LCDCFG5 */
+ 	.default_lcdcon2		= AT91SAM9X5_DEFAULT_LCDCFG5,
+ 	.default_monspecs		= &at91fb_default_monspecs,
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0085-create-platform-device-for-ovl1.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0085-create-platform-device-for-ovl1.patch
new file mode 100644
index 0000000..88fecd7
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0085-create-platform-device-for-ovl1.patch
@@ -0,0 +1,97 @@
+From 4d60230588345e54789b9d4b7e12bf7ba1a7fc9e Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Mon, 30 May 2011 15:02:53 +0200
+Subject: [PATCH 085/107] create platform device for ovl1
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+not-really-Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ arch/arm/mach-at91/at91sam9x5_devices.c |   45 ++++++++++++++++++++++++++-----
+ 1 files changed, 38 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
+index ee4278d..cd642e2 100644
+--- a/arch/arm/mach-at91/at91sam9x5_devices.c
++++ b/arch/arm/mach-at91/at91sam9x5_devices.c
+@@ -1010,29 +1010,59 @@ void __init at91_add_device_can(int id, struct at91_can_data *data) {}
+ static u64 lcdc_dmamask = DMA_BIT_MASK(32);
+ static struct atmel_lcdfb_info lcdc_data;
+ 
+-static struct resource lcdc_resources[] = {
++static struct resource lcdc_base_resources[] = {
+ 	[0] = {
+ 		.start	= AT91SAM9X5_BASE_LCDC,
+-		.end	= AT91SAM9X5_BASE_LCDC + SZ_16K - 1,
++		.end	= AT91SAM9X5_BASE_LCDC + 0xff,
+ 		.flags	= IORESOURCE_MEM,
+ 	},
+ 	[1] = {
++		.start	= AT91SAM9X5_BASE_LCDC + ATMEL_LCDC_BASECLUT,
++		.end	= AT91SAM9X5_BASE_LCDC + ATMEL_LCDC_BASECLUT + SZ_1K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[2] = {
+ 		.start	= AT91SAM9X5_ID_LCDC,
+ 		.end	= AT91SAM9X5_ID_LCDC,
+ 		.flags	= IORESOURCE_IRQ,
+ 	},
+ };
+ 
+-static struct platform_device at91_lcdc_device = {
+-	.name		= "atmel_hlcdfb",
++static struct platform_device at91_lcdc_base_device = {
++	.name		= "atmel_hlcdfb_base",
++	.id		= 0,
++	.dev		= {
++				.dma_mask		= &lcdc_dmamask,
++				.coherent_dma_mask	= DMA_BIT_MASK(32),
++				.platform_data		= &lcdc_data,
++	},
++	.resource	= lcdc_base_resources,
++	.num_resources	= ARRAY_SIZE(lcdc_base_resources),
++};
++
++static struct resource lcdc_ovl1_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_LCDC + 0x100,
++		.end	= AT91SAM9X5_BASE_LCDC + 0x27f,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_BASE_LCDC + ATMEL_LCDC_OVR1CLUT,
++		.end	= AT91SAM9X5_BASE_LCDC + ATMEL_LCDC_OVR1CLUT + SZ_1K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++};
++
++static struct platform_device at91_lcdc_ovl_device = {
++	.name		= "atmel_hlcdfb_ovl",
+ 	.id		= 0,
+ 	.dev		= {
+ 				.dma_mask		= &lcdc_dmamask,
+ 				.coherent_dma_mask	= DMA_BIT_MASK(32),
+ 				.platform_data		= &lcdc_data,
+ 	},
+-	.resource	= lcdc_resources,
+-	.num_resources	= ARRAY_SIZE(lcdc_resources),
++	.resource	= lcdc_ovl1_resources,
++	.num_resources	= ARRAY_SIZE(lcdc_ovl1_resources),
+ };
+ 
+ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
+@@ -1075,7 +1105,8 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
+ 	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD23 */
+ 
+ 	lcdc_data = *data;
+-	platform_device_register(&at91_lcdc_device);
++	platform_device_register(&at91_lcdc_base_device);
++	platform_device_register(&at91_lcdc_ovl_device);
+ }
+ #else
+ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0086-WIP-add-clut-resource.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0086-WIP-add-clut-resource.patch
new file mode 100644
index 0000000..de27e9d
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0086-WIP-add-clut-resource.patch
@@ -0,0 +1,167 @@
+From 6ee30e0b97801fb4a8dac9e9c4a1888e6f00514b Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Mon, 30 May 2011 17:04:35 +0200
+Subject: [PATCH 086/107] WIP: add clut resource
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Warning: will currently break old AT91-boards!
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/atmel_hlcdfb.c     |    2 --
+ drivers/video/atmel_lcdfb.c      |    1 -
+ drivers/video/atmel_lcdfb_core.c |   35 ++++++++++++++++++++++++++---------
+ include/video/atmel_lcdfb.h      |    2 +-
+ 4 files changed, 27 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
+index b772841..346bb80 100644
+--- a/drivers/video/atmel_hlcdfb.c
++++ b/drivers/video/atmel_hlcdfb.c
+@@ -454,7 +454,6 @@ static struct atmel_lcdfb_devdata dev_data_base = {
+ 	.init_contrast = atmel_hlcdfb_init_contrast,
+ 	.limit_screeninfo = atmelfb_limit_screeninfo,
+ 	.fbinfo_flags = ATMEL_LCDFB_FBINFO_DEFAULT,
+-	.lut_base = ATMEL_HLCDC_LUT,
+ 	.dma_desc_size = sizeof(struct atmel_hlcd_dma_desc),
+ };
+ 
+@@ -463,7 +462,6 @@ static struct atmel_lcdfb_devdata dev_data_ovl = {
+ 	.update_dma = atmel_hlcdfb_update_dma_ovl,
+ 	.limit_screeninfo = atmelfb_limit_screeninfo,
+ 	.fbinfo_flags = ATMEL_LCDFB_FBINFO_DEFAULT,
+-	.lut_base = 0x800, //FIXME: add define
+ 	.dma_desc_size = sizeof(struct atmel_hlcd_dma_desc),
+ };
+ 
+diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
+index 8d7992c..402cb24 100644
+--- a/drivers/video/atmel_lcdfb.c
++++ b/drivers/video/atmel_lcdfb.c
+@@ -399,7 +399,6 @@ static struct atmel_lcdfb_devdata dev_data = {
+ 	.init_contrast = atmel_lcdfb_init_contrast,
+ 	.limit_screeninfo = atmelfb_limit_screeninfo,
+ 	.fbinfo_flags = ATMEL_LCDFB_FBINFO_DEFAULT,
+-	.lut_base = ATMEL_LCDC_LUT,
+ };
+ 
+ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+index cd57361..89d974a 100644
+--- a/drivers/video/atmel_lcdfb_core.c
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -426,9 +426,7 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
+ 			 * TODO: intensity bit. Maybe something like
+ 			 *   ~(red[10] ^ green[10] ^ blue[10]) & 1
+ 			 */
+-
+-			lcdc_writel(sinfo, sinfo->dev_data->lut_base + regno * 4,
+-					val);
++			writel(val, sinfo->clut + regno * 4);
+ 			ret = 0;
+ 		}
+ 		break;
+@@ -436,8 +434,7 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
+ 	case FB_VISUAL_MONO01:
+ 		if (regno < 2) {
+ 			val = (regno == 0) ? 0x00 : 0x1F;
+-			lcdc_writel(sinfo, sinfo->dev_data->lut_base + regno * 4,
+-					val);
++			writel(val, sinfo->clut + regno * 4);
+ 			ret = 0;
+ 		}
+ 		break;
+@@ -553,7 +550,7 @@ int __atmel_lcdfb_probe(struct platform_device *pdev,
+ 	struct atmel_lcdfb_info *sinfo;
+ 	struct atmel_lcdfb_info *pdata_sinfo;
+ 	struct fb_videomode fbmode;
+-	struct resource *regs = NULL;
++	struct resource *regs = NULL, *clut = NULL;
+ 	struct resource *map = NULL;
+ 	int ret;
+ 
+@@ -628,11 +625,19 @@ int __atmel_lcdfb_probe(struct platform_device *pdev,
+ 		goto stop_clk;
+ 	}
+ 
++	clut = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	if (!clut) {
++		dev_err(dev, "clut resources unusable\n");
++		ret = -ENXIO;
++		goto stop_clk;
++	}
++
+ 	/* No error checking, some devices can do without IRQ */
+ 	sinfo->irq_base = platform_get_irq(pdev, 0);
+ 
+ 	/* Initialize video memory */
+-	map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	//FIXME: Fix LUTs for old platforms
++	map = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ 	if (map) {
+ 		/* use a pre-allocated memory buffer */
+ 		info->fix.smem_start = map->start;
+@@ -676,6 +681,17 @@ int __atmel_lcdfb_probe(struct platform_device *pdev,
+ 		goto release_mem;
+ 	}
+ 
++	//FIXME: proper request_region and cleanup
++	if (!request_mem_region(clut->start, resource_size(clut), pdev->name)) {
++		ret = -EBUSY;
++		goto unmap_mmio;
++	}
++	sinfo->clut = ioremap(clut->start, resource_size(clut));
++	if (!sinfo->clut) {
++		dev_err(dev, "cannot map CLUT\n");
++		goto unmap_mmio;
++	}
++
+ 	/* Initialize PWM for contrast or backlight ("off") */
+ 	if (sinfo->dev_data->init_contrast)
+ 		sinfo->dev_data->init_contrast(sinfo);
+@@ -688,7 +704,7 @@ int __atmel_lcdfb_probe(struct platform_device *pdev,
+ 				IRQF_SHARED, pdev->name, info);
+ 		if (ret) {
+ 			dev_err(dev, "request_irq failed: %d\n", ret);
+-			goto unmap_mmio;
++			goto clear_backlight;
+ 		}
+ 	}
+ 
+@@ -746,8 +762,9 @@ unregister_irqs:
+ 	cancel_work_sync(&sinfo->task);
+ 	if (sinfo->irq_base >= 0)
+ 		free_irq(sinfo->irq_base, info);
+-unmap_mmio:
++clear_backlight:
+ 	exit_backlight(sinfo);
++unmap_mmio:
+ 	iounmap(sinfo->mmio);
+ release_mem:
+  	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
+diff --git a/include/video/atmel_lcdfb.h b/include/video/atmel_lcdfb.h
+index 3a0dfc7..a9563b8 100644
+--- a/include/video/atmel_lcdfb.h
++++ b/include/video/atmel_lcdfb.h
+@@ -48,7 +48,6 @@ struct atmel_lcdfb_devdata {
+ 	void (*limit_screeninfo)(struct fb_var_screeninfo *var);
+ 	const struct backlight_ops *bl_ops;
+ 	int fbinfo_flags;
+-	u32 lut_base;
+ 	int dma_desc_size;
+ };
+ 
+@@ -63,6 +62,7 @@ struct atmel_lcdfb_info {
+ 	spinlock_t		lock;
+ 	struct fb_info		*info;
+ 	void __iomem		*mmio;
++	void __iomem		*clut;
+ 	int			irq_base;
+ 	struct atmel_lcdfb_devdata *dev_data;
+ 	struct work_struct	task;
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0087-video-atmel_lcdfb-add-error-msg-when-out-of-memory.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0087-video-atmel_lcdfb-add-error-msg-when-out-of-memory.patch
new file mode 100644
index 0000000..776b581
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0087-video-atmel_lcdfb-add-error-msg-when-out-of-memory.patch
@@ -0,0 +1,33 @@
+From 6d6df1c6bd82a56ad081ec305742c83f420db4bb Mon Sep 17 00:00:00 2001
+From: Wolfram Sang <w.sang@pengutronix.de>
+Date: Tue, 7 Jun 2011 12:58:36 +0200
+Subject: [PATCH 087/107] video: atmel_lcdfb: add error-msg when out of memory
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/atmel_lcdfb_core.c |    4 +++-
+ 1 files changed, 3 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
+index 89d974a..ff84234 100644
+--- a/drivers/video/atmel_lcdfb_core.c
++++ b/drivers/video/atmel_lcdfb_core.c
+@@ -221,8 +221,10 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
+ 	if (info->fix.smem_len) {
+ 		unsigned int smem_len = (var->xres_virtual * var->yres_virtual
+ 					 * ((var->bits_per_pixel + 7) / 8));
+-		if (smem_len > info->fix.smem_len)
++		if (smem_len > info->fix.smem_len) {
++			dev_err(dev, "not enough memory for this mode\n");
+ 			return -EINVAL;
++		}
+ 	}
+ 
+ 	/* Saturate vertical and horizontal timings at maximum values */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0088-Don-t-shortcut-vb2_reqbufs-in-case-the-format-change.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0088-Don-t-shortcut-vb2_reqbufs-in-case-the-format-change.patch
new file mode 100644
index 0000000..2136509
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0088-Don-t-shortcut-vb2_reqbufs-in-case-the-format-change.patch
@@ -0,0 +1,42 @@
+From e62cc3751425d342f13497be5877a380f4e8a5c9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Wed, 8 Jun 2011 11:17:02 +0200
+Subject: [PATCH 088/107] Don't shortcut vb2_reqbufs in case the format
+ changed
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Just checking for number of buffers and memory access method isn't
+enough because the format might have changed since the buffers were
+allocated and the new format might need bigger ones.
+
+This reverts commit 31901a078af29c33c736dcbf815656920e904632.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Forwarded: http://mid.gmane.org/1307525477-18491-1-git-send-email-u.kleine-koenig@pengutronix.de
+---
+ drivers/media/video/videobuf2-core.c |    7 -------
+ 1 files changed, 0 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/media/video/videobuf2-core.c b/drivers/media/video/videobuf2-core.c
+index 6ba1461..6489aa2 100644
+--- a/drivers/media/video/videobuf2-core.c
++++ b/drivers/media/video/videobuf2-core.c
+@@ -492,13 +492,6 @@ int vb2_reqbufs(struct vb2_queue *q, struct v4l2_requestbuffers *req)
+ 		return -EINVAL;
+ 	}
+ 
+-	/*
+-	 * If the same number of buffers and memory access method is requested
+-	 * then return immediately.
+-	 */
+-	if (q->memory == req->memory && req->count == q->num_buffers)
+-		return 0;
+-
+ 	if (req->count == 0 || q->num_buffers != 0 || q->memory != req->memory) {
+ 		/*
+ 		 * We already have buffers allocated, so first check if they
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0089-at91-video-change-atmel-lcdfb-driver-selection-mode.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0089-at91-video-change-atmel-lcdfb-driver-selection-mode.patch
new file mode 100644
index 0000000..d02a1f7
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0089-at91-video-change-atmel-lcdfb-driver-selection-mode.patch
@@ -0,0 +1,95 @@
+From 904d3f56a0667c0ea225ddc751bf4e5f19ec7ac1 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 9 Jun 2011 17:37:07 +0200
+Subject: [PATCH 089/107] at91: video: change atmel lcdfb driver selection
+ mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+LCD driver for AT91 chips is selected by a single entry in Kconfig.
+The new hlcdfb is only selected on supported platforms.
+
+Backlight is selected if needed.
+
+XXX/nfe: improve commit log, move backlight to a separate patch
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/video/Kconfig           |   13 ++++---------
+ drivers/video/Makefile          |    5 ++++-
+ drivers/video/backlight/Kconfig |    2 +-
+ 3 files changed, 9 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index 8b25a8e..aa423d2 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -8,6 +8,9 @@ menu "Graphics support"
+ config HAVE_FB_ATMEL
+ 	bool
+ 
++config FB_ATMEL_HLCD
++	bool
++
+ config HAVE_FB_IMX
+ 	bool
+ 
+@@ -1002,6 +1005,7 @@ config FB_ATMEL
+ 	select FB_CFB_FILLRECT
+ 	select FB_CFB_COPYAREA
+ 	select FB_CFB_IMAGEBLIT
++	select FB_ATMEL_HLCD if ARCH_AT91SAM9X5
+ 	help
+ 	  This enables support for the AT91/AT32 LCD Controller.
+ 
+@@ -1022,15 +1026,6 @@ config FB_ATMEL_STN
+ 
+ 	  If unsure, say N.
+ 
+-config FB_ATMEL_HLCD
+-	tristate "AT91 HLCD Controller support"
+-	depends on FB && HAVE_FB_ATMEL
+-	select FB_CFB_FILLRECT
+-	select FB_CFB_COPYAREA
+-	select FB_CFB_IMAGEBLIT
+-	help
+-	  This enables support for the AT91 HLCD Controller.
+-
+ config FB_NVIDIA
+ 	tristate "nVidia Framebuffer Support"
+ 	depends on FB && PCI
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index 2597768..ea6c5a3 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -91,8 +91,11 @@ obj-$(CONFIG_FB_EP93XX)		  += ep93xx-fb.o
+ obj-$(CONFIG_FB_SA1100)           += sa1100fb.o
+ obj-$(CONFIG_FB_HIT)              += hitfb.o
+ obj-$(CONFIG_FB_EPSON1355)	  += epson1355fb.o
++ifdef CONFIG_FB_ATMEL_HLCD
++obj-y				  += atmel_hlcdfb.o atmel_lcdfb_core.o
++else
+ obj-$(CONFIG_FB_ATMEL)		  += atmel_lcdfb.o atmel_lcdfb_core.o
+-obj-$(CONFIG_FB_ATMEL_HLCD)	  += atmel_hlcdfb.o atmel_lcdfb_core.o
++endif
+ obj-$(CONFIG_FB_PVR2)             += pvr2fb.o
+ obj-$(CONFIG_FB_VOODOO1)          += sstfb.o
+ obj-$(CONFIG_FB_ARMCLCD)	  += amba-clcd.o
+diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
+index 0c9373b..ffd9fef 100644
+--- a/drivers/video/backlight/Kconfig
++++ b/drivers/video/backlight/Kconfig
+@@ -137,7 +137,7 @@ if BACKLIGHT_CLASS_DEVICE
+ config BACKLIGHT_ATMEL_LCDC
+ 	bool "Atmel LCDC Contrast-as-Backlight control"
+ 	depends on FB_ATMEL
+-	default y if MACH_SAM9261EK || MACH_SAM9G10EK || MACH_SAM9263EK
++	default y if MACH_SAM9261EK || MACH_SAM9G10EK || MACH_SAM9263EK || MACH_AT91SAM9X5EK
+ 	help
+ 	  This provides a backlight control internal to the Atmel LCDC
+ 	  driver.  If the LCD "contrast control" on your board is wired
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0090-sound-atmel_ssc_dai-add-a-missing-space-to-an-error-.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0090-sound-atmel_ssc_dai-add-a-missing-space-to-an-error-.patch
new file mode 100644
index 0000000..48e5d4f
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0090-sound-atmel_ssc_dai-add-a-missing-space-to-an-error-.patch
@@ -0,0 +1,35 @@
+From 238c10baa2393d20f2f1b905a08ddd15f0fb3c25 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Fri, 10 Jun 2011 00:37:28 +0200
+Subject: [PATCH 090/107] sound/atmel_ssc_dai: add a missing space to an error
+ message
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Acked-by: Liam Girdwood <lrg@ti.com>
+Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Applied-Upstream: v3.1, commit:2f2b3cf1dddf9
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ sound/soc/atmel/atmel_ssc_dai.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/sound/soc/atmel/atmel_ssc_dai.c b/sound/soc/atmel/atmel_ssc_dai.c
+index 43cce80..8c89514 100644
+--- a/sound/soc/atmel/atmel_ssc_dai.c
++++ b/sound/soc/atmel/atmel_ssc_dai.c
+@@ -405,7 +405,7 @@ static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
+ 	if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S
+ 		&& bits > 16) {
+ 		printk(KERN_WARNING
+-				"atmel_ssc_dai: sample size %d"
++				"atmel_ssc_dai: sample size %d "
+ 				"is too large for I2S\n", bits);
+ 		return -EINVAL;
+ 	}
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0091-at91-add-Atmel-Image-Sensor-Interface-ISI-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0091-at91-add-Atmel-Image-Sensor-Interface-ISI-support.patch
new file mode 100644
index 0000000..a7221fb
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0091-at91-add-Atmel-Image-Sensor-Interface-ISI-support.patch
@@ -0,0 +1,1233 @@
+From 3cc75ebabf66c90f0a7f99600c4d30d6069103d6 Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Wed, 8 Jun 2011 14:53:52 +0800
+Subject: [PATCH 091/107] at91: add Atmel Image Sensor Interface (ISI) support
+
+This patch is to enable Atmel Image Sensor Interface (ISI) driver support.
+- Using soc-camera framework with videobuf2 dma-contig allocator
+- Supporting video streaming of YUV packed format
+- Tested on AT91SAM9M10G45-EK with OV2640
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+---
+ drivers/media/video/Kconfig     |    8 +
+ drivers/media/video/Makefile    |    1 +
+ drivers/media/video/atmel-isi.c | 1048 +++++++++++++++++++++++++++++++++++++++
+ include/media/atmel-isi.h       |  119 +++++
+ 4 files changed, 1176 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/media/video/atmel-isi.c
+ create mode 100644 include/media/atmel-isi.h
+
+diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
+index c937e4d..a301a69 100644
+--- a/drivers/media/video/Kconfig
++++ b/drivers/media/video/Kconfig
+@@ -888,6 +888,14 @@ config VIDEO_MX3
+ 	---help---
+ 	  This is a v4l2 driver for the i.MX3x Camera Sensor Interface
+ 
++config VIDEO_ATMEL_ISI
++	tristate "ATMEL Image Sensor Interface (ISI) support"
++	depends on VIDEO_DEV && SOC_CAMERA && ARCH_AT91
++	select VIDEOBUF2_DMA_CONTIG
++	---help---
++	  This module makes the ATMEL Image Sensor Interface available
++	  as a v4l2 device.
++
+ config VIDEO_PXA27x
+ 	tristate "PXA27x Quick Capture Interface driver"
+ 	depends on VIDEO_DEV && PXA27x && SOC_CAMERA
+diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
+index 5a7620d..f9f8f12 100644
+--- a/drivers/media/video/Makefile
++++ b/drivers/media/video/Makefile
+@@ -166,6 +166,7 @@ obj-$(CONFIG_VIDEO_SH_MOBILE_CSI2)	+= sh_mobile_csi2.o
+ obj-$(CONFIG_VIDEO_SH_MOBILE_CEU)	+= sh_mobile_ceu_camera.o
+ obj-$(CONFIG_VIDEO_OMAP1)		+= omap1_camera.o
+ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) 	+= s5p-fimc/
++obj-$(CONFIG_VIDEO_ATMEL_ISI)		+= atmel-isi.o
+ 
+ obj-$(CONFIG_ARCH_DAVINCI)		+= davinci/
+ 
+diff --git a/drivers/media/video/atmel-isi.c b/drivers/media/video/atmel-isi.c
+new file mode 100644
+index 0000000..4742c28
+--- /dev/null
++++ b/drivers/media/video/atmel-isi.c
+@@ -0,0 +1,1048 @@
++/*
++ * Copyright (c) 2011 Atmel Corporation
++ * Josh Wu, <josh.wu@atmel.com>
++ *
++ * Based on previous work by Lars Haring, <lars.haring@atmel.com>
++ * and Sedji Gaouaou
++ * Based on the bttv driver for Bt848 with respective copyright holders
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/completion.h>
++#include <linux/delay.h>
++#include <linux/fs.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++
++#include <media/atmel-isi.h>
++#include <media/soc_camera.h>
++#include <media/soc_mediabus.h>
++#include <media/videobuf2-dma-contig.h>
++
++#define MAX_BUFFER_NUM			32
++#define MAX_SUPPORT_WIDTH		2048
++#define MAX_SUPPORT_HEIGHT		2048
++#define VID_LIMIT_BYTES			(16 * 1024 * 1024)
++#define MIN_FRAME_RATE			15
++#define FRAME_INTERVAL_MILLI_SEC	(1000 / MIN_FRAME_RATE)
++
++/* ISI states */
++enum {
++	ISI_STATE_IDLE = 0,
++	ISI_STATE_READY,
++	ISI_STATE_WAIT_SOF,
++};
++
++/* Frame buffer descriptor */
++struct fbd {
++	/* Physical address of the frame buffer */
++	u32 fb_address;
++	/* DMA Control Register(only in HISI2) */
++	u32 dma_ctrl;
++	/* Physical address of the next fbd */
++	u32 next_fbd_address;
++};
++
++static void set_dma_ctrl(struct fbd *fb_desc, u32 ctrl)
++{
++	fb_desc->dma_ctrl = ctrl;
++}
++
++struct isi_dma_desc {
++	struct list_head list;
++	struct fbd *p_fbd;
++	u32 fbd_phys;
++};
++
++/* Frame buffer data */
++struct frame_buffer {
++	struct vb2_buffer vb;
++	struct isi_dma_desc *p_dma_desc;
++	struct list_head list;
++};
++
++struct atmel_isi {
++	/* Protects the access of variables shared with the ISR */
++	spinlock_t			lock;
++	void __iomem			*regs;
++
++	int				sequence;
++	/* State of the ISI module in capturing mode */
++	int				state;
++
++	/* Wait queue for waiting for SOF */
++	wait_queue_head_t		vsync_wq;
++
++	struct vb2_alloc_ctx		*alloc_ctx;
++
++	/* Allocate descriptors for dma buffer use */
++	struct fbd			*p_fb_descriptors;
++	u32				fb_descriptors_phys;
++	struct				list_head dma_desc_head;
++	struct isi_dma_desc		dma_desc[MAX_BUFFER_NUM];
++
++	struct completion		complete;
++	struct clk			*pclk;
++	unsigned int			irq;
++
++	struct isi_platform_data	*pdata;
++
++	struct list_head		video_buffer_list;
++	struct frame_buffer		*active;
++
++	struct soc_camera_device	*icd;
++	struct soc_camera_host		soc_host;
++};
++
++static void isi_writel(struct atmel_isi *isi, u32 reg, u32 val)
++{
++	writel(val, isi->regs + reg);
++}
++static u32 isi_readl(struct atmel_isi *isi, u32 reg)
++{
++	return readl(isi->regs + reg);
++}
++
++static int configure_geometry(struct atmel_isi *isi, u32 width,
++			u32 height, enum v4l2_mbus_pixelcode code)
++{
++	u32 cfg2, cr;
++
++	switch (code) {
++	/* YUV, including grey */
++	case V4L2_MBUS_FMT_Y8_1X8:
++		cr = ISI_CFG2_GRAYSCALE;
++		break;
++	case V4L2_MBUS_FMT_UYVY8_2X8:
++		cr = ISI_CFG2_YCC_SWAP_MODE_3;
++		break;
++	case V4L2_MBUS_FMT_VYUY8_2X8:
++		cr = ISI_CFG2_YCC_SWAP_MODE_2;
++		break;
++	case V4L2_MBUS_FMT_YUYV8_2X8:
++		cr = ISI_CFG2_YCC_SWAP_MODE_1;
++		break;
++	case V4L2_MBUS_FMT_YVYU8_2X8:
++		cr = ISI_CFG2_YCC_SWAP_DEFAULT;
++		break;
++	/* RGB, TODO */
++	default:
++		return -EINVAL;
++	}
++
++	isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
++
++	cfg2 = isi_readl(isi, ISI_CFG2);
++	cfg2 |= cr;
++	/* Set width */
++	cfg2 &= ~(ISI_CFG2_IM_HSIZE_MASK);
++	cfg2 |= ((width - 1) << ISI_CFG2_IM_HSIZE_OFFSET) &
++			ISI_CFG2_IM_HSIZE_MASK;
++	/* Set height */
++	cfg2 &= ~(ISI_CFG2_IM_VSIZE_MASK);
++	cfg2 |= ((height - 1) << ISI_CFG2_IM_VSIZE_OFFSET)
++			& ISI_CFG2_IM_VSIZE_MASK;
++	isi_writel(isi, ISI_CFG2, cfg2);
++
++	return 0;
++}
++
++static irqreturn_t atmel_isi_handle_streaming(struct atmel_isi *isi)
++{
++	if (isi->active) {
++		struct vb2_buffer *vb = &isi->active->vb;
++		struct frame_buffer *buf = isi->active;
++
++		list_del_init(&buf->list);
++		do_gettimeofday(&vb->v4l2_buf.timestamp);
++		vb->v4l2_buf.sequence = isi->sequence++;
++		vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
++	}
++
++	if (list_empty(&isi->video_buffer_list)) {
++		isi->active = NULL;
++	} else {
++		/* start next dma frame. */
++		isi->active = list_entry(isi->video_buffer_list.next,
++					struct frame_buffer, list);
++		isi_writel(isi, ISI_DMA_C_DSCR,
++			isi->active->p_dma_desc->fbd_phys);
++		isi_writel(isi, ISI_DMA_C_CTRL,
++			ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
++		isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
++	}
++	return IRQ_HANDLED;
++}
++
++/* ISI interrupt service routine */
++static irqreturn_t isi_interrupt(int irq, void *dev_id)
++{
++	struct atmel_isi *isi = dev_id;
++	u32 status, mask, pending;
++	irqreturn_t ret = IRQ_NONE;
++
++	spin_lock(&isi->lock);
++
++	status = isi_readl(isi, ISI_STATUS);
++	mask = isi_readl(isi, ISI_INTMASK);
++	pending = status & mask;
++
++	if (pending & ISI_CTRL_SRST) {
++		complete(&isi->complete);
++		isi_writel(isi, ISI_INTDIS, ISI_CTRL_SRST);
++		ret = IRQ_HANDLED;
++	} else if (pending & ISI_CTRL_DIS) {
++		complete(&isi->complete);
++		isi_writel(isi, ISI_INTDIS, ISI_CTRL_DIS);
++		ret = IRQ_HANDLED;
++	} else {
++		if ((pending & ISI_SR_VSYNC) &&
++				(isi->state == ISI_STATE_IDLE)) {
++			isi->state = ISI_STATE_READY;
++			wake_up_interruptible(&isi->vsync_wq);
++			ret = IRQ_HANDLED;
++		}
++		if (likely(pending & ISI_SR_CXFR_DONE))
++			ret = atmel_isi_handle_streaming(isi);
++	}
++
++	spin_unlock(&isi->lock);
++	return ret;
++}
++
++#define	WAIT_ISI_RESET		1
++#define	WAIT_ISI_DISABLE	0
++static int atmel_isi_wait_status(struct atmel_isi *isi, int wait_reset)
++{
++	unsigned long timeout;
++	/*
++	 * The reset or disable will only succeed if we have a
++	 * pixel clock from the camera.
++	 */
++	init_completion(&isi->complete);
++
++	if (wait_reset) {
++		isi_writel(isi, ISI_INTEN, ISI_CTRL_SRST);
++		isi_writel(isi, ISI_CTRL, ISI_CTRL_SRST);
++	} else {
++		isi_writel(isi, ISI_INTEN, ISI_CTRL_DIS);
++		isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
++	}
++
++	timeout = wait_for_completion_timeout(&isi->complete,
++			msecs_to_jiffies(100));
++	if (timeout == 0)
++		return -ETIMEDOUT;
++
++	return 0;
++}
++
++/* ------------------------------------------------------------------
++	Videobuf operations
++   ------------------------------------------------------------------*/
++static int queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
++				unsigned int *nplanes, unsigned long sizes[],
++				void *alloc_ctxs[])
++{
++	struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
++	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
++	struct atmel_isi *isi = ici->priv;
++	unsigned long size;
++	int ret, bytes_per_line;
++
++	/* Reset ISI */
++	ret = atmel_isi_wait_status(isi, WAIT_ISI_RESET);
++	if (ret < 0) {
++		dev_err(icd->dev.parent, "Reset ISI timed out\n");
++		return ret;
++	}
++	/* Disable all interrupts */
++	isi_writel(isi, ISI_INTDIS, ~0UL);
++
++	bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
++						icd->current_fmt->host_fmt);
++
++	if (bytes_per_line < 0)
++		return bytes_per_line;
++
++	size = bytes_per_line * icd->user_height;
++
++	if (!*nbuffers || *nbuffers > MAX_BUFFER_NUM)
++		*nbuffers = MAX_BUFFER_NUM;
++
++	if (size * *nbuffers > VID_LIMIT_BYTES)
++		*nbuffers = VID_LIMIT_BYTES / size;
++
++	*nplanes = 1;
++	sizes[0] = size;
++	alloc_ctxs[0] = isi->alloc_ctx;
++
++	isi->sequence = 0;
++	isi->active = NULL;
++
++	dev_dbg(icd->dev.parent, "%s, count=%d, size=%ld\n", __func__,
++		*nbuffers, size);
++
++	return 0;
++}
++
++static int buffer_init(struct vb2_buffer *vb)
++{
++	struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
++
++	buf->p_dma_desc = NULL;
++	INIT_LIST_HEAD(&buf->list);
++
++	return 0;
++}
++
++static int buffer_prepare(struct vb2_buffer *vb)
++{
++	struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
++	struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
++	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
++	struct atmel_isi *isi = ici->priv;
++	unsigned long size;
++	struct isi_dma_desc *desc;
++	int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
++						icd->current_fmt->host_fmt);
++
++	if (bytes_per_line < 0)
++		return bytes_per_line;
++
++	size = bytes_per_line * icd->user_height;
++
++	if (vb2_plane_size(vb, 0) < size) {
++		dev_err(icd->dev.parent, "%s data will not fit into plane (%lu < %lu)\n",
++				__func__, vb2_plane_size(vb, 0), size);
++		return -EINVAL;
++	}
++
++	vb2_set_plane_payload(&buf->vb, 0, size);
++
++	if (!buf->p_dma_desc) {
++		if (list_empty(&isi->dma_desc_head)) {
++			dev_err(icd->dev.parent, "Not enough dma descriptors.\n");
++			return -EINVAL;
++		} else {
++			/* Get an available descriptor */
++			desc = list_entry(isi->dma_desc_head.next,
++						struct isi_dma_desc, list);
++			/* Delete the descriptor since now it is used */
++			list_del_init(&desc->list);
++
++			/* Initialize the dma descriptor */
++			desc->p_fbd->fb_address =
++					vb2_dma_contig_plane_paddr(vb, 0);
++			desc->p_fbd->next_fbd_address = 0;
++			set_dma_ctrl(desc->p_fbd, ISI_DMA_CTRL_WB);
++
++			buf->p_dma_desc = desc;
++		}
++	}
++	return 0;
++}
++
++static void buffer_cleanup(struct vb2_buffer *vb)
++{
++	struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
++	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
++	struct atmel_isi *isi = ici->priv;
++	struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
++
++	/* This descriptor is available now and we add to head list */
++	if (buf->p_dma_desc)
++		list_add(&buf->p_dma_desc->list, &isi->dma_desc_head);
++}
++
++static void start_dma(struct atmel_isi *isi, struct frame_buffer *buffer)
++{
++	u32 ctrl, cfg1;
++
++	cfg1 = isi_readl(isi, ISI_CFG1);
++	/* Enable irq: cxfr for the codec path, pxfr for the preview path */
++	isi_writel(isi, ISI_INTEN,
++			ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
++
++	/* Check if already in a frame */
++	if (isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) {
++		dev_err(isi->icd->dev.parent, "Already in frame handling.\n");
++		return;
++	}
++
++	isi_writel(isi, ISI_DMA_C_DSCR, buffer->p_dma_desc->fbd_phys);
++	isi_writel(isi, ISI_DMA_C_CTRL, ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
++	isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
++
++	/* Enable linked list */
++	cfg1 |= isi->pdata->frate | ISI_CFG1_DISCR;
++
++	/* Enable codec path and ISI */
++	ctrl = ISI_CTRL_CDC | ISI_CTRL_EN;
++	isi_writel(isi, ISI_CTRL, ctrl);
++	isi_writel(isi, ISI_CFG1, cfg1);
++}
++
++static void buffer_queue(struct vb2_buffer *vb)
++{
++	struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
++	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
++	struct atmel_isi *isi = ici->priv;
++	struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
++	unsigned long flags = 0;
++
++	spin_lock_irqsave(&isi->lock, flags);
++	list_add_tail(&buf->list, &isi->video_buffer_list);
++
++	if (isi->active == NULL) {
++		isi->active = buf;
++		start_dma(isi, buf);
++	}
++	spin_unlock_irqrestore(&isi->lock, flags);
++}
++
++static int start_streaming(struct vb2_queue *vq)
++{
++	struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
++	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
++	struct atmel_isi *isi = ici->priv;
++
++	u32 sr = 0;
++	int ret;
++
++	spin_lock_irq(&isi->lock);
++	isi->state = ISI_STATE_IDLE;
++	/* Clear any pending SOF interrupt */
++	sr = isi_readl(isi, ISI_STATUS);
++	/* Enable VSYNC interrupt for SOF */
++	isi_writel(isi, ISI_INTEN, ISI_SR_VSYNC);
++	isi_writel(isi, ISI_CTRL, ISI_CTRL_EN);
++	spin_unlock_irq(&isi->lock);
++
++	dev_dbg(icd->dev.parent, "Waiting for SOF\n");
++	ret = wait_event_interruptible(isi->vsync_wq,
++				       isi->state != ISI_STATE_IDLE);
++	if (ret)
++		return ret;
++
++	if (isi->state != ISI_STATE_READY)
++		return -EIO;
++
++	spin_lock_irq(&isi->lock);
++	isi->state = ISI_STATE_WAIT_SOF;
++	isi_writel(isi, ISI_INTDIS, ISI_SR_VSYNC);
++	spin_unlock_irq(&isi->lock);
++
++	return 0;
++}
++
++/* abort streaming and wait for last buffer */
++static int stop_streaming(struct vb2_queue *vq)
++{
++	struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
++	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
++	struct atmel_isi *isi = ici->priv;
++	struct frame_buffer *buf, *node;
++	int ret = 0;
++	unsigned long timeout;
++
++	spin_lock_irq(&isi->lock);
++	isi->active = NULL;
++	/* Release all active buffers */
++	list_for_each_entry_safe(buf, node, &isi->video_buffer_list, list) {
++		list_del_init(&buf->list);
++		vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
++	}
++	spin_unlock_irq(&isi->lock);
++
++	timeout = jiffies + FRAME_INTERVAL_MILLI_SEC * HZ;
++	/* Wait until the end of the current frame. */
++	while ((isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) &&
++			time_before(jiffies, timeout))
++		msleep(1);
++
++	if (time_after(jiffies, timeout)) {
++		dev_err(icd->dev.parent,
++			"Timeout waiting for finishing codec request\n");
++		return -ETIMEDOUT;
++	}
++
++	/* Disable interrupts */
++	isi_writel(isi, ISI_INTDIS,
++			ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
++
++	/* Disable ISI and wait for it is done */
++	ret = atmel_isi_wait_status(isi, WAIT_ISI_DISABLE);
++	if (ret < 0)
++		dev_err(icd->dev.parent, "Disable ISI timed out\n");
++
++	return ret;
++}
++
++static struct vb2_ops isi_video_qops = {
++	.queue_setup		= queue_setup,
++	.buf_init		= buffer_init,
++	.buf_prepare		= buffer_prepare,
++	.buf_cleanup		= buffer_cleanup,
++	.buf_queue		= buffer_queue,
++	.start_streaming	= start_streaming,
++	.stop_streaming		= stop_streaming,
++	.wait_prepare		= soc_camera_unlock,
++	.wait_finish		= soc_camera_lock,
++};
++
++/* ------------------------------------------------------------------
++	SOC camera operations for the device
++   ------------------------------------------------------------------*/
++static int isi_camera_init_videobuf(struct vb2_queue *q,
++				     struct soc_camera_device *icd)
++{
++	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	q->io_modes = VB2_MMAP;
++	q->drv_priv = icd;
++	q->buf_struct_size = sizeof(struct frame_buffer);
++	q->ops = &isi_video_qops;
++	q->mem_ops = &vb2_dma_contig_memops;
++
++	return vb2_queue_init(q);
++}
++
++static int isi_camera_set_fmt(struct soc_camera_device *icd,
++			      struct v4l2_format *f)
++{
++	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
++	struct atmel_isi *isi = ici->priv;
++	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
++	const struct soc_camera_format_xlate *xlate;
++	struct v4l2_pix_format *pix = &f->fmt.pix;
++	struct v4l2_mbus_framefmt mf;
++	int ret;
++
++	xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
++	if (!xlate) {
++		dev_warn(icd->dev.parent, "Format %x not found\n",
++			 pix->pixelformat);
++		return -EINVAL;
++	}
++
++	dev_dbg(icd->dev.parent, "Plan to set format %dx%d\n",
++			pix->width, pix->height);
++
++	mf.width	= pix->width;
++	mf.height	= pix->height;
++	mf.field	= pix->field;
++	mf.colorspace	= pix->colorspace;
++	mf.code		= xlate->code;
++
++	ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
++	if (ret < 0)
++		return ret;
++
++	if (mf.code != xlate->code)
++		return -EINVAL;
++
++	ret = configure_geometry(isi, pix->width, pix->height, xlate->code);
++	if (ret < 0)
++		return ret;
++
++	pix->width		= mf.width;
++	pix->height		= mf.height;
++	pix->field		= mf.field;
++	pix->colorspace		= mf.colorspace;
++	icd->current_fmt	= xlate;
++
++	dev_dbg(icd->dev.parent, "Finally set format %dx%d\n",
++		pix->width, pix->height);
++
++	return ret;
++}
++
++static int isi_camera_try_fmt(struct soc_camera_device *icd,
++			      struct v4l2_format *f)
++{
++	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
++	const struct soc_camera_format_xlate *xlate;
++	struct v4l2_pix_format *pix = &f->fmt.pix;
++	struct v4l2_mbus_framefmt mf;
++	u32 pixfmt = pix->pixelformat;
++	int ret;
++
++	xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
++	if (pixfmt && !xlate) {
++		dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
++		return -EINVAL;
++	}
++
++	/* limit to Atmel ISI hardware capabilities */
++	if (pix->height > MAX_SUPPORT_HEIGHT)
++		pix->height = MAX_SUPPORT_HEIGHT;
++	if (pix->width > MAX_SUPPORT_WIDTH)
++		pix->width = MAX_SUPPORT_WIDTH;
++
++	/* limit to sensor capabilities */
++	mf.width	= pix->width;
++	mf.height	= pix->height;
++	mf.field	= pix->field;
++	mf.colorspace	= pix->colorspace;
++	mf.code		= xlate->code;
++
++	ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
++	if (ret < 0)
++		return ret;
++
++	pix->width	= mf.width;
++	pix->height	= mf.height;
++	pix->colorspace	= mf.colorspace;
++
++	switch (mf.field) {
++	case V4L2_FIELD_ANY:
++		pix->field = V4L2_FIELD_NONE;
++		break;
++	case V4L2_FIELD_NONE:
++		break;
++	default:
++		dev_err(icd->dev.parent, "Field type %d unsupported.\n",
++			mf.field);
++		ret = -EINVAL;
++	}
++
++	return ret;
++}
++
++static const struct soc_mbus_pixelfmt isi_camera_formats[] = {
++	{
++		.fourcc			= V4L2_PIX_FMT_YUYV,
++		.name			= "Packed YUV422 16 bit",
++		.bits_per_sample	= 8,
++		.packing		= SOC_MBUS_PACKING_2X8_PADHI,
++		.order			= SOC_MBUS_ORDER_LE,
++	},
++};
++
++/* This will be corrected as we get more formats */
++static bool isi_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
++{
++	return	fmt->packing == SOC_MBUS_PACKING_NONE ||
++		(fmt->bits_per_sample == 8 &&
++		 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
++		(fmt->bits_per_sample > 8 &&
++		 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
++}
++
++static unsigned long make_bus_param(struct atmel_isi *isi)
++{
++	unsigned long flags;
++	/*
++	 * Platform specified synchronization and pixel clock polarities are
++	 * only a recommendation and are only used during probing. Atmel ISI
++	 * camera interface only works in master mode, i.e., uses HSYNC and
++	 * VSYNC signals from the sensor
++	 */
++	flags = SOCAM_MASTER |
++		SOCAM_HSYNC_ACTIVE_HIGH |
++		SOCAM_HSYNC_ACTIVE_LOW |
++		SOCAM_VSYNC_ACTIVE_HIGH |
++		SOCAM_VSYNC_ACTIVE_LOW |
++		SOCAM_PCLK_SAMPLE_RISING |
++		SOCAM_PCLK_SAMPLE_FALLING |
++		SOCAM_DATA_ACTIVE_HIGH;
++
++	if (isi->pdata->data_width_flags & ISI_DATAWIDTH_10)
++		flags |= SOCAM_DATAWIDTH_10;
++
++	if (isi->pdata->data_width_flags & ISI_DATAWIDTH_8)
++		flags |= SOCAM_DATAWIDTH_8;
++
++	if (flags & SOCAM_DATAWIDTH_MASK)
++		return flags;
++
++	return 0;
++}
++
++static int isi_camera_try_bus_param(struct soc_camera_device *icd,
++				    unsigned char buswidth)
++{
++	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
++	struct atmel_isi *isi = ici->priv;
++	unsigned long camera_flags;
++	int ret;
++
++	camera_flags = icd->ops->query_bus_param(icd);
++	ret = soc_camera_bus_param_compatible(camera_flags,
++					make_bus_param(isi));
++	if (!ret)
++		return -EINVAL;
++	return 0;
++}
++
++
++static int isi_camera_get_formats(struct soc_camera_device *icd,
++				  unsigned int idx,
++				  struct soc_camera_format_xlate *xlate)
++{
++	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
++	int formats = 0, ret;
++	/* sensor format */
++	enum v4l2_mbus_pixelcode code;
++	/* soc camera host format */
++	const struct soc_mbus_pixelfmt *fmt;
++
++	ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
++	if (ret < 0)
++		/* No more formats */
++		return 0;
++
++	fmt = soc_mbus_get_fmtdesc(code);
++	if (!fmt) {
++		dev_err(icd->dev.parent,
++			"Invalid format code #%u: %d\n", idx, code);
++		return 0;
++	}
++
++	/* This also checks support for the requested bits-per-sample */
++	ret = isi_camera_try_bus_param(icd, fmt->bits_per_sample);
++	if (ret < 0) {
++		dev_err(icd->dev.parent,
++			"Fail to try the bus parameters.\n");
++		return 0;
++	}
++
++	switch (code) {
++	case V4L2_MBUS_FMT_UYVY8_2X8:
++	case V4L2_MBUS_FMT_VYUY8_2X8:
++	case V4L2_MBUS_FMT_YUYV8_2X8:
++	case V4L2_MBUS_FMT_YVYU8_2X8:
++		formats++;
++		if (xlate) {
++			xlate->host_fmt	= &isi_camera_formats[0];
++			xlate->code	= code;
++			xlate++;
++			dev_dbg(icd->dev.parent, "Providing format %s using code %d\n",
++				isi_camera_formats[0].name, code);
++		}
++		break;
++	default:
++		if (!isi_camera_packing_supported(fmt))
++			return 0;
++		if (xlate)
++			dev_dbg(icd->dev.parent,
++				"Providing format %s in pass-through mode\n",
++				fmt->name);
++	}
++
++	/* Generic pass-through */
++	formats++;
++	if (xlate) {
++		xlate->host_fmt	= fmt;
++		xlate->code	= code;
++		xlate++;
++	}
++
++	return formats;
++}
++
++/* Called with .video_lock held */
++static int isi_camera_add_device(struct soc_camera_device *icd)
++{
++	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
++	struct atmel_isi *isi = ici->priv;
++	int ret;
++
++	if (isi->icd)
++		return -EBUSY;
++
++	ret = clk_enable(isi->pclk);
++	if (ret)
++		return ret;
++
++	isi->icd = icd;
++	dev_dbg(icd->dev.parent, "Atmel ISI Camera driver attached to camera %d\n",
++		 icd->devnum);
++	return 0;
++}
++/* Called with .video_lock held */
++static void isi_camera_remove_device(struct soc_camera_device *icd)
++{
++	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
++	struct atmel_isi *isi = ici->priv;
++
++	BUG_ON(icd != isi->icd);
++
++	clk_disable(isi->pclk);
++	isi->icd = NULL;
++
++	dev_dbg(icd->dev.parent, "Atmel ISI Camera driver detached from camera %d\n",
++		 icd->devnum);
++}
++
++static unsigned int isi_camera_poll(struct file *file, poll_table *pt)
++{
++	struct soc_camera_device *icd = file->private_data;
++
++	return vb2_poll(&icd->vb2_vidq, file, pt);
++}
++
++static int isi_camera_querycap(struct soc_camera_host *ici,
++			       struct v4l2_capability *cap)
++{
++	strcpy(cap->driver, "atmel-isi");
++	strcpy(cap->card, "Atmel Image Sensor Interface");
++	cap->capabilities = (V4L2_CAP_VIDEO_CAPTURE |
++				V4L2_CAP_STREAMING);
++	return 0;
++}
++
++static int isi_camera_set_bus_param(struct soc_camera_device *icd, u32 pixfmt)
++{
++	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
++	struct atmel_isi *isi = ici->priv;
++	unsigned long bus_flags, camera_flags, common_flags;
++	int ret;
++	u32 cfg1 = 0;
++
++	camera_flags = icd->ops->query_bus_param(icd);
++
++	bus_flags = make_bus_param(isi);
++	common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
++	dev_dbg(icd->dev.parent, "Flags cam: 0x%lx host: 0x%lx common: 0x%lx\n",
++		camera_flags, bus_flags, common_flags);
++	if (!common_flags)
++		return -EINVAL;
++
++	/* Make choises, based on platform preferences */
++	if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
++	    (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
++		if (isi->pdata->hsync_act_low)
++			common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
++		else
++			common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
++	}
++
++	if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
++	    (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
++		if (isi->pdata->vsync_act_low)
++			common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
++		else
++			common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
++	}
++
++	if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
++	    (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
++		if (isi->pdata->pclk_act_falling)
++			common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
++		else
++			common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
++	}
++
++	ret = icd->ops->set_bus_param(icd, common_flags);
++	if (ret < 0) {
++		dev_dbg(icd->dev.parent, "Camera set_bus_param(%lx) returned %d\n",
++			common_flags, ret);
++		return ret;
++	}
++
++	/* set bus param for ISI */
++	if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
++		cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW;
++	if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
++		cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW;
++	if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
++		cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING;
++
++	if (isi->pdata->has_emb_sync)
++		cfg1 |= ISI_CFG1_EMB_SYNC;
++	if (isi->pdata->isi_full_mode)
++		cfg1 |= ISI_CFG1_FULL_MODE;
++
++	isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
++	isi_writel(isi, ISI_CFG1, cfg1);
++
++	return 0;
++}
++
++static struct soc_camera_host_ops isi_soc_camera_host_ops = {
++	.owner		= THIS_MODULE,
++	.add		= isi_camera_add_device,
++	.remove		= isi_camera_remove_device,
++	.set_fmt	= isi_camera_set_fmt,
++	.try_fmt	= isi_camera_try_fmt,
++	.get_formats	= isi_camera_get_formats,
++	.init_videobuf2	= isi_camera_init_videobuf,
++	.poll		= isi_camera_poll,
++	.querycap	= isi_camera_querycap,
++	.set_bus_param	= isi_camera_set_bus_param,
++};
++
++/* -----------------------------------------------------------------------*/
++static int __devexit atmel_isi_remove(struct platform_device *pdev)
++{
++	struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
++	struct atmel_isi *isi = container_of(soc_host,
++					struct atmel_isi, soc_host);
++
++	free_irq(isi->irq, isi);
++	soc_camera_host_unregister(soc_host);
++	vb2_dma_contig_cleanup_ctx(isi->alloc_ctx);
++	dma_free_coherent(&pdev->dev,
++			sizeof(struct fbd) * MAX_BUFFER_NUM,
++			isi->p_fb_descriptors,
++			isi->fb_descriptors_phys);
++
++	iounmap(isi->regs);
++	clk_put(isi->pclk);
++	kfree(isi);
++
++	return 0;
++}
++
++static int __devinit atmel_isi_probe(struct platform_device *pdev)
++{
++	unsigned int irq;
++	struct atmel_isi *isi;
++	struct clk *pclk;
++	struct resource *regs;
++	int ret, i;
++	struct device *dev = &pdev->dev;
++	struct soc_camera_host *soc_host;
++	struct isi_platform_data *pdata;
++
++	pdata = dev->platform_data;
++	if (!pdata || !pdata->data_width_flags) {
++		dev_err(&pdev->dev,
++			"No config available for Atmel ISI\n");
++		return -EINVAL;
++	}
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!regs)
++		return -ENXIO;
++
++	pclk = clk_get(&pdev->dev, "isi_clk");
++	if (IS_ERR(pclk))
++		return PTR_ERR(pclk);
++
++	isi = kzalloc(sizeof(struct atmel_isi), GFP_KERNEL);
++	if (!isi) {
++		ret = -ENOMEM;
++		dev_err(&pdev->dev, "Can't allocate interface!\n");
++		goto err_alloc_isi;
++	}
++
++	isi->pclk = pclk;
++	isi->pdata = pdata;
++	isi->active = NULL;
++	spin_lock_init(&isi->lock);
++	init_waitqueue_head(&isi->vsync_wq);
++	INIT_LIST_HEAD(&isi->video_buffer_list);
++	INIT_LIST_HEAD(&isi->dma_desc_head);
++
++	isi->p_fb_descriptors = dma_alloc_coherent(&pdev->dev,
++				sizeof(struct fbd) * MAX_BUFFER_NUM,
++				&isi->fb_descriptors_phys,
++				GFP_KERNEL);
++	if (!isi->p_fb_descriptors) {
++		ret = -ENOMEM;
++		dev_err(&pdev->dev, "Can't allocate descriptors!\n");
++		goto err_alloc_descriptors;
++	}
++
++	for (i = 0; i < MAX_BUFFER_NUM; i++) {
++		isi->dma_desc[i].p_fbd = isi->p_fb_descriptors + i;
++		isi->dma_desc[i].fbd_phys = isi->fb_descriptors_phys +
++					i * sizeof(struct fbd);
++		list_add(&isi->dma_desc[i].list, &isi->dma_desc_head);
++	}
++
++	isi->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
++	if (IS_ERR(isi->alloc_ctx)) {
++		ret = PTR_ERR(isi->alloc_ctx);
++		goto err_alloc_ctx;
++	}
++
++	isi->regs = ioremap(regs->start, resource_size(regs));
++	if (!isi->regs) {
++		ret = -ENOMEM;
++		goto err_ioremap;
++	}
++
++	isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0) {
++		ret = irq;
++		goto err_req_irq;
++	}
++
++	ret = request_irq(irq, isi_interrupt, 0, "isi", isi);
++	if (ret) {
++		dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
++		goto err_req_irq;
++	}
++	isi->irq = irq;
++
++	soc_host		= &isi->soc_host;
++	soc_host->drv_name	= "isi-camera";
++	soc_host->ops		= &isi_soc_camera_host_ops;
++	soc_host->priv		= isi;
++	soc_host->v4l2_dev.dev	= &pdev->dev;
++	soc_host->nr		= pdev->id;
++
++	ret = soc_camera_host_register(soc_host);
++	if (ret) {
++		dev_err(&pdev->dev, "Unable to register soc camera host\n");
++		goto err_register_soc_camera_host;
++	}
++	return 0;
++
++err_register_soc_camera_host:
++	free_irq(isi->irq, isi);
++err_req_irq:
++	iounmap(isi->regs);
++err_ioremap:
++	vb2_dma_contig_cleanup_ctx(isi->alloc_ctx);
++err_alloc_ctx:
++	dma_free_coherent(&pdev->dev,
++			sizeof(struct fbd) * MAX_BUFFER_NUM,
++			isi->p_fb_descriptors,
++			isi->fb_descriptors_phys);
++err_alloc_descriptors:
++	kfree(isi);
++err_alloc_isi:
++	clk_put(isi->pclk);
++
++	return ret;
++}
++
++static struct platform_driver atmel_isi_driver = {
++	.probe		= atmel_isi_probe,
++	.remove		= __devexit_p(atmel_isi_remove),
++	.driver		= {
++		.name = "atmel_isi",
++		.owner = THIS_MODULE,
++	},
++};
++
++static int __init atmel_isi_init_module(void)
++{
++	return  platform_driver_probe(&atmel_isi_driver, &atmel_isi_probe);
++}
++
++static void __exit atmel_isi_exit(void)
++{
++	platform_driver_unregister(&atmel_isi_driver);
++}
++module_init(atmel_isi_init_module);
++module_exit(atmel_isi_exit);
++
++MODULE_AUTHOR("Josh Wu <josh.wu@atmel.com>");
++MODULE_DESCRIPTION("The V4L2 driver for Atmel Linux");
++MODULE_LICENSE("GPL");
++MODULE_SUPPORTED_DEVICE("video");
+diff --git a/include/media/atmel-isi.h b/include/media/atmel-isi.h
+new file mode 100644
+index 0000000..26cece5
+--- /dev/null
++++ b/include/media/atmel-isi.h
+@@ -0,0 +1,119 @@
++/*
++ * Register definitions for the Atmel Image Sensor Interface.
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * Josh Wu, <josh.wu@atmel.com>
++ *
++ * Based on previous work by Lars Haring, <lars.haring@atmel.com>
++ * and Sedji Gaouaou
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __ATMEL_ISI_H__
++#define __ATMEL_ISI_H__
++
++#include <linux/types.h>
++
++/* ISI_V2 register offsets */
++#define ISI_CFG1				0x0000
++#define ISI_CFG2				0x0004
++#define ISI_PSIZE				0x0008
++#define ISI_PDECF				0x000c
++#define ISI_Y2R_SET0				0x0010
++#define ISI_Y2R_SET1				0x0014
++#define ISI_R2Y_SET0				0x0018
++#define ISI_R2Y_SET1				0x001C
++#define ISI_R2Y_SET2				0x0020
++#define ISI_CTRL				0x0024
++#define ISI_STATUS				0x0028
++#define ISI_INTEN				0x002C
++#define ISI_INTDIS				0x0030
++#define ISI_INTMASK				0x0034
++#define ISI_DMA_CHER				0x0038
++#define ISI_DMA_CHDR				0x003C
++#define ISI_DMA_CHSR				0x0040
++#define ISI_DMA_P_ADDR				0x0044
++#define ISI_DMA_P_CTRL				0x0048
++#define ISI_DMA_P_DSCR				0x004C
++#define ISI_DMA_C_ADDR				0x0050
++#define ISI_DMA_C_CTRL				0x0054
++#define ISI_DMA_C_DSCR				0x0058
++
++/* Bitfields in CFG1 */
++#define ISI_CFG1_HSYNC_POL_ACTIVE_LOW		(1 << 2)
++#define ISI_CFG1_VSYNC_POL_ACTIVE_LOW		(1 << 3)
++#define ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING	(1 << 4)
++#define ISI_CFG1_EMB_SYNC			(1 << 6)
++#define ISI_CFG1_CRC_SYNC			(1 << 7)
++/* Constants for FRATE(ISI_V2) */
++#define		ISI_CFG1_FRATE_CAPTURE_ALL	(0 << 8)
++#define		ISI_CFG1_FRATE_DIV_2		(1 << 8)
++#define		ISI_CFG1_FRATE_DIV_3		(2 << 8)
++#define		ISI_CFG1_FRATE_DIV_4		(3 << 8)
++#define		ISI_CFG1_FRATE_DIV_5		(4 << 8)
++#define		ISI_CFG1_FRATE_DIV_6		(5 << 8)
++#define		ISI_CFG1_FRATE_DIV_7		(6 << 8)
++#define		ISI_CFG1_FRATE_DIV_8		(7 << 8)
++#define ISI_CFG1_DISCR				(1 << 11)
++#define ISI_CFG1_FULL_MODE			(1 << 12)
++
++/* Bitfields in CFG2 */
++#define ISI_CFG2_GRAYSCALE			(1 << 13)
++/* Constants for YCC_SWAP(ISI_V2) */
++#define		ISI_CFG2_YCC_SWAP_DEFAULT	(0 << 28)
++#define		ISI_CFG2_YCC_SWAP_MODE_1	(1 << 28)
++#define		ISI_CFG2_YCC_SWAP_MODE_2	(2 << 28)
++#define		ISI_CFG2_YCC_SWAP_MODE_3	(3 << 28)
++#define ISI_CFG2_IM_VSIZE_OFFSET		0
++#define ISI_CFG2_IM_HSIZE_OFFSET		16
++#define ISI_CFG2_IM_VSIZE_MASK		(0x7FF << ISI_CFG2_IM_VSIZE_OFFSET)
++#define ISI_CFG2_IM_HSIZE_MASK		(0x7FF << ISI_CFG2_IM_HSIZE_OFFSET)
++
++/* Bitfields in CTRL */
++/* Also using in SR(ISI_V2) */
++#define ISI_CTRL_EN				(1 << 0)
++#define ISI_CTRL_CDC				(1 << 8)
++/* Also using in SR/IER/IDR/IMR(ISI_V2) */
++#define ISI_CTRL_DIS				(1 << 1)
++#define ISI_CTRL_SRST				(1 << 2)
++
++/* Bitfields in SR */
++#define ISI_SR_SIP				(1 << 19)
++/* Also using in SR/IER/IDR/IMR */
++#define ISI_SR_VSYNC				(1 << 10)
++#define ISI_SR_PXFR_DONE			(1 << 16)
++#define ISI_SR_CXFR_DONE			(1 << 17)
++#define ISI_SR_P_OVR				(1 << 24)
++#define ISI_SR_C_OVR				(1 << 25)
++#define ISI_SR_CRC_ERR				(1 << 26)
++#define ISI_SR_FR_OVR				(1 << 27)
++
++/* Bitfields in DMA_C_CTRL & in DMA_P_CTRL */
++#define ISI_DMA_CTRL_FETCH			(1 << 0)
++#define ISI_DMA_CTRL_WB				(1 << 1)
++#define ISI_DMA_CTRL_IEN			(1 << 2)
++#define ISI_DMA_CTRL_DONE			(1 << 3)
++
++/* Bitfields in DMA_CHSR/CHER/CHDR */
++#define ISI_DMA_CHSR_P_CH			(1 << 0)
++#define ISI_DMA_CHSR_C_CH			(1 << 1)
++
++/* Definition for isi_platform_data */
++#define ISI_DATAWIDTH_8				0x01
++#define ISI_DATAWIDTH_10			0x02
++
++struct isi_platform_data {
++	u8 has_emb_sync;
++	u8 emb_crc_sync;
++	u8 hsync_act_low;
++	u8 vsync_act_low;
++	u8 pclk_act_falling;
++	u8 isi_full_mode;
++	u32 data_width_flags;
++	/* Using for ISI_CFG1 */
++	u32 frate;
++};
++
++#endif /* __ATMEL_ISI_H__ */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0092-add-isi-support-in-board-files.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0092-add-isi-support-in-board-files.patch
new file mode 100644
index 0000000..a1b4d02
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0092-add-isi-support-in-board-files.patch
@@ -0,0 +1,238 @@
+From d904f14ba47c08d0b73de77b5066ecad7bec8953 Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Fri, 27 May 2011 18:26:15 +0800
+Subject: [PATCH 092/107] add isi support in board files.
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+---
+ arch/arm/mach-at91/at91sam9g45_devices.c |   66 ++++++++++++++++++++
+ arch/arm/mach-at91/board-sam9m10g45ek.c  |   97 ++++++++++++++++++++++++++++++
+ arch/arm/mach-at91/include/mach/board.h  |    3 +-
+ 3 files changed, 165 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
+index f40b254..c9a61ff 100644
+--- a/arch/arm/mach-at91/at91sam9g45_devices.c
++++ b/arch/arm/mach-at91/at91sam9g45_devices.c
+@@ -29,6 +29,8 @@
+ #include <mach/at_hdmac.h>
+ #include <mach/atmel-mci.h>
+ 
++#include <media/atmel-isi.h>
++
+ #include "generic.h"
+ 
+ 
+@@ -873,6 +875,70 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
+ void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
+ #endif
+ 
++/* --------------------------------------------------------------------
++ *  Image Sensor Interface
++ * -------------------------------------------------------------------- */
++#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
++static u64 isi_dmamask = DMA_BIT_MASK(32);
++static struct isi_platform_data isi_data;
++
++struct resource isi_resources[] = {
++	[0] = {
++		.start	= AT91SAM9G45_BASE_ISI,
++		.end	= AT91SAM9G45_BASE_ISI + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9G45_ID_ISI,
++		.end	= AT91SAM9G45_ID_ISI,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9g45_isi_device = {
++	.name		= "atmel_isi",
++	.id		= 0,
++	.dev		= {
++			.dma_mask		= &isi_dmamask,
++			.coherent_dma_mask	= DMA_BIT_MASK(32),
++			.platform_data		= &isi_data,
++	},
++	.resource	= isi_resources,
++	.num_resources	= ARRAY_SIZE(isi_resources),
++};
++
++void __init at91_add_device_isi(struct isi_platform_data * data)
++{
++	struct platform_device *pdev;
++
++	if (!data)
++		return;
++	isi_data = *data;
++
++	at91_set_A_periph(AT91_PIN_PB20, 0);	/* ISI_D0 */
++	at91_set_A_periph(AT91_PIN_PB21, 0);	/* ISI_D1 */
++	at91_set_A_periph(AT91_PIN_PB22, 0);	/* ISI_D2 */
++	at91_set_A_periph(AT91_PIN_PB23, 0);	/* ISI_D3 */
++	at91_set_A_periph(AT91_PIN_PB24, 0);	/* ISI_D4 */
++	at91_set_A_periph(AT91_PIN_PB25, 0);	/* ISI_D5 */
++	at91_set_A_periph(AT91_PIN_PB26, 0);	/* ISI_D6 */
++	at91_set_A_periph(AT91_PIN_PB27, 0);	/* ISI_D7 */
++	at91_set_A_periph(AT91_PIN_PB28, 0);	/* ISI_PCK */
++	at91_set_A_periph(AT91_PIN_PB30, 0);	/* ISI_HSYNC */
++	at91_set_A_periph(AT91_PIN_PB29, 0);	/* ISI_VSYNC */
++	at91_set_B_periph(AT91_PIN_PB31, 0);	/* ISI_MCK (PCK1) */
++	at91_set_B_periph(AT91_PIN_PB8, 0);	/* ISI_PD8 */
++	at91_set_B_periph(AT91_PIN_PB9, 0);	/* ISI_PD9 */
++	at91_set_B_periph(AT91_PIN_PB10, 0);	/* ISI_PD10 */
++	at91_set_B_periph(AT91_PIN_PB11, 0);	/* ISI_PD11 */
++
++	pdev = &at91sam9g45_isi_device;
++	platform_device_register(pdev);
++}
++#else
++void __init at91_add_device_isi(struct isi_platform_data * data) { }
++#endif
++
+ 
+ /* --------------------------------------------------------------------
+  *  LCD Controller
+diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
+index b2b1a8b..6fb7ce9 100644
+--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
++++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
+@@ -25,9 +25,12 @@
+ #include <linux/leds.h>
+ #include <linux/clk.h>
+ #include <linux/atmel-mci.h>
++#include <linux/delay.h>
+ 
+ #include <mach/hardware.h>
+ #include <video/atmel_lcdfb.h>
++#include <media/soc_camera.h>
++#include <media/atmel-isi.h>
+ 
+ #include <asm/setup.h>
+ #include <asm/mach-types.h>
+@@ -195,6 +198,95 @@ static void __init ek_add_device_nand(void)
+ 	at91_add_device_nand(&ek_nand_data);
+ }
+ 
++/*
++ *  ISI
++ */
++#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
++static struct isi_platform_data __initdata isi_data = {
++	.frate		= ISI_CFG1_FRATE_CAPTURE_ALL,
++	.has_emb_sync	= 0,
++	.emb_crc_sync = 0,
++	.hsync_act_low = 0,
++	.vsync_act_low = 0,
++	.pclk_act_falling = 0,
++	/* to use codec and preview path simultaneously */
++	.isi_full_mode = 1,
++	.data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
++};
++
++static void __init isi_set_clk(void)
++{
++	struct clk *pck1;
++	struct clk *plla;
++
++	pck1 = clk_get(NULL, "pck1");
++	plla = clk_get(NULL, "plla");
++
++	clk_set_parent(pck1, plla);
++	clk_set_rate(pck1, 25000000);
++	clk_enable(pck1);
++}
++#else
++static void __init isi_set_clk(void) {}
++
++static struct isi_platform_data __initdata isi_data;
++#endif
++
++/*
++ * soc-camera OV2640
++ */
++#if defined(CONFIG_SOC_CAMERA_OV2640)
++static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
++{
++	/* ISI board for ek using default 8-bits connection */
++	return SOCAM_DATAWIDTH_8;
++}
++
++static int i2c_camera_power(struct device *dev, int on)
++{
++	/* enable or disable the camera */
++	pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
++	at91_set_gpio_output(AT91_PIN_PD13, on ? 0 : 1);
++
++	if (!on)
++		goto out;
++
++	/* If enabled, give a reset impulse */
++	at91_set_gpio_output(AT91_PIN_PD12, 0);
++	msleep(20);
++	at91_set_gpio_output(AT91_PIN_PD12, 1);
++	msleep(100);
++
++out:
++	return 0;
++}
++
++static struct i2c_board_info i2c_camera = {
++	I2C_BOARD_INFO("ov2640", 0x30),
++};
++
++static struct soc_camera_link iclink_ov2640 = {
++	.bus_id		= 0,
++	.board_info	= &i2c_camera,
++	.i2c_adapter_id	= 0,
++	.power		= i2c_camera_power,
++	.query_bus_param	= isi_camera_query_bus_param,
++};
++
++static struct platform_device isi_ov2640 = {
++	.name	= "soc-camera-pdrv",
++	.id	= 0,
++	.dev	= {
++		.platform_data = &iclink_ov2640,
++	},
++};
++
++static struct platform_device *devices[] __initdata = {
++	&isi_ov2640,
++};
++#else
++static struct platform_device *devices[] __initdata = {};
++#endif
+ 
+ /*
+  * LCD Controller
+@@ -410,6 +502,11 @@ static void __init ek_board_init(void)
+ 	ek_add_device_nand();
+ 	/* I2C */
+ 	at91_add_device_i2c(0, NULL, 0);
++	/* ISI */
++	platform_add_devices(devices, ARRAY_SIZE(devices));
++	isi_set_clk();
++	at91_add_device_isi(&isi_data);
++
+ 	/* LCD Controller */
+ 	at91_add_device_lcdc(&ek_lcdc_data);
+ 	/* Touch Screen */
+diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
+index 42412d5..cf8d780 100644
+--- a/arch/arm/mach-at91/include/mach/board.h
++++ b/arch/arm/mach-at91/include/mach/board.h
+@@ -188,7 +188,8 @@ extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
+ extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
+ 
+  /* ISI */
+-extern void __init at91_add_device_isi(void);
++struct isi_platform_data;
++extern void __init at91_add_device_isi(struct isi_platform_data *data);
+ 
+  /* Touchscreen Controller */
+ struct at91_tsadcc_data {
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0093-media-at91-add-dumb-set_parm.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0093-media-at91-add-dumb-set_parm.patch
new file mode 100644
index 0000000..1f0b313
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0093-media-at91-add-dumb-set_parm.patch
@@ -0,0 +1,40 @@
+From 81827465ea87d7ad20dcb9f8abb7393af6333a5d Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Fri, 10 Jun 2011 17:21:28 +0200
+Subject: [PATCH 093/107] [media] at91: add dumb set_parm()
+
+Add dumb set_parm() function to struct soc_camera_host_ops.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ drivers/media/video/atmel-isi.c |    7 +++++++
+ 1 files changed, 7 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/media/video/atmel-isi.c b/drivers/media/video/atmel-isi.c
+index 4742c28..b7a0a20 100644
+--- a/drivers/media/video/atmel-isi.c
++++ b/drivers/media/video/atmel-isi.c
+@@ -868,6 +868,12 @@ static int isi_camera_set_bus_param(struct soc_camera_device *icd, u32 pixfmt)
+ 	return 0;
+ }
+ 
++
++static int isi_camera_set_parm(struct soc_camera_device *icd, struct v4l2_streamparm *parm)
++{
++	return 0;
++}
++
+ static struct soc_camera_host_ops isi_soc_camera_host_ops = {
+ 	.owner		= THIS_MODULE,
+ 	.add		= isi_camera_add_device,
+@@ -879,6 +885,7 @@ static struct soc_camera_host_ops isi_soc_camera_host_ops = {
+ 	.poll		= isi_camera_poll,
+ 	.querycap	= isi_camera_querycap,
+ 	.set_bus_param	= isi_camera_set_bus_param,
++	.set_parm	= isi_camera_set_parm,
+ };
+ 
+ /* -----------------------------------------------------------------------*/
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0094-AT91-5series-add-ISI-device-and-board-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0094-AT91-5series-add-ISI-device-and-board-support.patch
new file mode 100644
index 0000000..1118a09
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0094-AT91-5series-add-ISI-device-and-board-support.patch
@@ -0,0 +1,232 @@
+From 07827ad93d921e852712a2f7f6b1d480c04c133c Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Fri, 10 Jun 2011 17:23:45 +0200
+Subject: [PATCH 094/107] AT91: 5series: add ISI device and board support
+
+New ISI / media SoC camera interface with ov2640 image sensor support.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ arch/arm/mach-at91/at91sam9x5_devices.c |   67 ++++++++++++++++++++
+ arch/arm/mach-at91/board-sam9x5ek.c     |  103 ++++++++++++++++++++++++++++++-
+ 2 files changed, 169 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
+index cd642e2..4cafa1c 100644
+--- a/arch/arm/mach-at91/at91sam9x5_devices.c
++++ b/arch/arm/mach-at91/at91sam9x5_devices.c
+@@ -30,6 +30,8 @@
+ #include <mach/at_hdmac.h>
+ #include <mach/atmel-mci.h>
+ 
++#include <media/atmel-isi.h>
++
+ #include "generic.h"
+ 
+ /* --------------------------------------------------------------------
+@@ -931,6 +933,71 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
+ #endif
+ 
++/* --------------------------------------------------------------------
++ *  Image Sensor Interface
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
++static u64 isi_dmamask = DMA_BIT_MASK(32);
++static struct isi_platform_data isi_data;
++
++struct resource isi_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_BASE_ISI,
++		.end	= AT91SAM9X5_BASE_ISI + SZ_16K - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_ISI,
++		.end	= AT91SAM9X5_ID_ISI,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_isi_device = {
++	.name		= "atmel_isi",
++	.id		= 0,
++	.dev		= {
++			.dma_mask		= &isi_dmamask,
++			.coherent_dma_mask	= DMA_BIT_MASK(32),
++			.platform_data		= &isi_data,
++	},
++	.resource	= isi_resources,
++	.num_resources	= ARRAY_SIZE(isi_resources),
++};
++
++void __init at91_add_device_isi(struct isi_platform_data *data)
++{
++	struct platform_device *pdev;
++
++	if (!data)
++		return;
++
++	at91_set_B_periph(AT91_PIN_PC0, 0);	/* ISI_D0 */
++	at91_set_B_periph(AT91_PIN_PC1, 0);	/* ISI_D1 */
++	at91_set_B_periph(AT91_PIN_PC2, 0);	/* ISI_D2 */
++	at91_set_B_periph(AT91_PIN_PC3, 0);	/* ISI_D3 */
++	at91_set_B_periph(AT91_PIN_PC4, 0);	/* ISI_D4 */
++	at91_set_B_periph(AT91_PIN_PC5, 0);	/* ISI_D5 */
++	at91_set_B_periph(AT91_PIN_PC6, 0);	/* ISI_D6 */
++	at91_set_B_periph(AT91_PIN_PC7, 0);	/* ISI_D7 */
++	at91_set_B_periph(AT91_PIN_PC12, 0);	/* ISI_PCK */
++	at91_set_B_periph(AT91_PIN_PC14, 0);	/* ISI_HSYNC */
++	at91_set_B_periph(AT91_PIN_PC13, 0);	/* ISI_VSYNC */
++	at91_set_C_periph(AT91_PIN_PC15, 0);	/* ISI_MCK (using PCK0 as clock) */
++	at91_set_B_periph(AT91_PIN_PC8, 0);	/* ISI_PD8 */
++	at91_set_B_periph(AT91_PIN_PC9, 0);	/* ISI_PD9 */
++	at91_set_B_periph(AT91_PIN_PC10, 0);	/* ISI_PD10 */
++	at91_set_B_periph(AT91_PIN_PC11, 0);	/* ISI_PD11 */
++
++	pdev = &at91sam9x5_isi_device;
++
++	isi_data = *data;
++	platform_device_register(pdev);
++}
++#else
++void __init at91_add_device_isi(struct isi_platform_data *data) {}
++#endif
+ 
+ /* --------------------------------------------------------------------
+  * CAN Controllers
+diff --git a/arch/arm/mach-at91/board-sam9x5ek.c b/arch/arm/mach-at91/board-sam9x5ek.c
+index 54fd7cc..826bb6e 100644
+--- a/arch/arm/mach-at91/board-sam9x5ek.c
++++ b/arch/arm/mach-at91/board-sam9x5ek.c
+@@ -22,9 +22,12 @@
+ #include <linux/input.h>
+ #include <linux/leds.h>
+ #include <linux/clk.h>
++#include <linux/delay.h>
+ #include <mach/cpu.h>
+ 
+ #include <video/atmel_lcdfb.h>
++#include <media/soc_camera.h>
++#include <media/atmel-isi.h>
+ 
+ #include <asm/setup.h>
+ #include <asm/mach-types.h>
+@@ -110,6 +113,95 @@ static struct mci_platform_data __initdata mci1_data = {
+ 	},
+ };
+ 
++/*
++ *  ISI
++ */
++#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
++static struct isi_platform_data __initdata isi_data = {
++	.frate		= ISI_CFG1_FRATE_CAPTURE_ALL,
++	.has_emb_sync	= 0,
++	.emb_crc_sync = 0,
++	.hsync_act_low = 0,
++	.vsync_act_low = 0,
++	.pclk_act_falling = 0,
++	/* to use codec and preview path simultaneously */
++	.isi_full_mode = 1,
++	.data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
++};
++
++static void __init isi_set_clk(void)
++{
++	struct clk *pck0;
++	struct clk *plla;
++
++	pck0 = clk_get(NULL, "pck0");
++	plla = clk_get(NULL, "plla");
++
++	clk_set_parent(pck0, plla);
++	/* for the sensor ov9655: 10< Fclk < 48, Fclk typ = 24MHz */
++	clk_set_rate(pck0, 25000000);
++	clk_enable(pck0);
++}
++#else
++static void __init isi_set_clk(void) {}
++static struct isi_platform_data __initdata isi_data;
++#endif
++
++/*
++ * soc-camera OV2640
++ */
++#if defined(CONFIG_SOC_CAMERA_OV2640)
++static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
++{
++	/* ISI board for ek using default 8-bits connection */
++	return SOCAM_DATAWIDTH_8;
++}
++
++static int i2c_camera_power(struct device *dev, int on)
++{
++	/* enable or disable the camera */
++	pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
++	at91_set_gpio_output(AT91_PIN_PA13, on ? 0 : 1);
++
++	if (!on)
++		goto out;
++
++	/* If enabled, give a reset impulse */
++	at91_set_gpio_output(AT91_PIN_PA7, 0);
++	msleep(20);
++	at91_set_gpio_output(AT91_PIN_PA7, 1);
++	msleep(100);
++
++out:
++	return 0;
++}
++
++static struct i2c_board_info i2c_camera = {
++	I2C_BOARD_INFO("ov2640", 0x30),
++};
++
++static struct soc_camera_link iclink_ov2640 = {
++	.bus_id		= 0,
++	.board_info	= &i2c_camera,
++	.i2c_adapter_id	= 0,
++	.power		= i2c_camera_power,
++	.query_bus_param	= isi_camera_query_bus_param,
++};
++
++static struct platform_device isi_ov2640 = {
++	.name	= "soc-camera-pdrv",
++	.id	= 0,
++	.dev	= {
++		.platform_data = &iclink_ov2640,
++	},
++};
++
++static struct platform_device *soc_camera_devices[] __initdata = {
++	&isi_ov2640,
++};
++#else
++static struct platform_device *soc_camera_devices[] __initdata = {};
++#endif
+ 
+ /*
+  * LCD Controller
+@@ -314,7 +406,16 @@ static void __init ek_board_init(void)
+ 		at91_add_device_i2c(0,
+ 				ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
+ 
+-	if (!cpu_is_at91sam9g25() && !cpu_is_at91sam9x25()) {
++	if (cpu_is_at91sam9g25()) {
++		/* ISI */
++		/* NOTE: PCK0 provides ISI_MCK to the ISI module.
++		   ISI's PWD pin conflict with MCI1_CK due the hardware design.
++		 */
++		platform_add_devices(soc_camera_devices,
++					ARRAY_SIZE(soc_camera_devices));
++		isi_set_clk();
++		at91_add_device_isi(&isi_data);
++	} else if (!cpu_is_at91sam9x25()) {
+ 		/* LCD Controller */
+ 		at91_add_device_lcdc(&ek_lcdc_data);
+ 		/* Touch Screen */
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0095-AT91-board-remove-not-needed-comments.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0095-AT91-board-remove-not-needed-comments.patch
new file mode 100644
index 0000000..1b3c43c
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0095-AT91-board-remove-not-needed-comments.patch
@@ -0,0 +1,47 @@
+From b2267ebc8cb722d8bb403da097cf2649616f8f62 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Fri, 10 Jun 2011 18:01:57 +0200
+Subject: [PATCH 095/107] AT91: board: remove not needed comments
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ arch/arm/mach-at91/board-sam9x5cm.c |    1 -
+ arch/arm/mach-at91/board-sam9x5ek.c |    3 +--
+ 2 files changed, 1 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-at91/board-sam9x5cm.c b/arch/arm/mach-at91/board-sam9x5cm.c
+index 53d8046..a5f8f3d 100644
+--- a/arch/arm/mach-at91/board-sam9x5cm.c
++++ b/arch/arm/mach-at91/board-sam9x5cm.c
+@@ -228,7 +228,6 @@ void __init cm_board_init(u32 *cm_config)
+ 	/* LEDs */
+ 	at91_gpio_leds(cm_leds, ARRAY_SIZE(cm_leds));
+ 
+-	/* TODO Remove: only for debugging */
+ 	if (cm_is_revA())
+ 		printk(KERN_CRIT "AT91: CM rev A\n");
+ 	else
+diff --git a/arch/arm/mach-at91/board-sam9x5ek.c b/arch/arm/mach-at91/board-sam9x5ek.c
+index 826bb6e..4f64903 100644
+--- a/arch/arm/mach-at91/board-sam9x5ek.c
++++ b/arch/arm/mach-at91/board-sam9x5ek.c
+@@ -433,7 +433,7 @@ static void __init ek_board_init(void)
+ #endif
+ 
+ 	if (cpu_is_at91sam9x25() || cpu_is_at91sam9x35())
+-		/* XXX: this conflicts with usart.1 */
++		/* this conflicts with usart.1 */
+ 		at91_add_device_can(1, NULL);
+ 
+ 	/* Push Buttons */
+@@ -443,7 +443,6 @@ static void __init ek_board_init(void)
+ 	/* SSC (for WM8731) */
+ 	at91_add_device_ssc(AT91SAM9X5_ID_SSC, ATMEL_SSC_TX | ATMEL_SSC_RX);
+ 
+-	/* TODO Remove: only for debugging */
+ 	if (ek_is_revA())
+ 		printk(KERN_CRIT "AT91: EK rev A\n");
+ 	else
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0096-AT91-5series-update-defconfig.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0096-AT91-5series-update-defconfig.patch
new file mode 100644
index 0000000..81d4fc7
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0096-AT91-5series-update-defconfig.patch
@@ -0,0 +1,266 @@
+From 63d2c71154c342c3a2e20828fc21e6d424e8fc67 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Fri, 10 Jun 2011 18:06:12 +0200
+Subject: [PATCH 096/107] AT91: 5series: update defconfig
+
+- ISI and V4L2 media/video
+- UBI / UBIFS
+- update driver support (sd/mmc, sound)
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ arch/arm/configs/at91sam9x5ek_defconfig |  130 +++++++++++++++++++++----------
+ 1 files changed, 89 insertions(+), 41 deletions(-)
+
+diff --git a/arch/arm/configs/at91sam9x5ek_defconfig b/arch/arm/configs/at91sam9x5ek_defconfig
+index 1b455fc..48af066 100644
+--- a/arch/arm/configs/at91sam9x5ek_defconfig
++++ b/arch/arm/configs/at91sam9x5ek_defconfig
+@@ -1,14 +1,14 @@
+ CONFIG_EXPERIMENTAL=y
++# CONFIG_LOCALVERSION_AUTO is not set
+ # CONFIG_SWAP is not set
+ CONFIG_SYSVIPC=y
+ CONFIG_POSIX_MQUEUE=y
+ CONFIG_LOG_BUF_SHIFT=14
+-# CONFIG_UTS_NS is not set
+-# CONFIG_IPC_NS is not set
+-# CONFIG_USER_NS is not set
+-# CONFIG_PID_NS is not set
+-# CONFIG_NET_NS is not set
+ CONFIG_BLK_DEV_INITRD=y
++CONFIG_RD_BZIP2=y
++CONFIG_RD_LZMA=y
++CONFIG_RD_LZO=y
++CONFIG_EMBEDDED=y
+ CONFIG_SLAB=y
+ CONFIG_MODULES=y
+ CONFIG_MODULE_UNLOAD=y
+@@ -28,7 +28,8 @@ CONFIG_LEDS_CPU=y
+ CONFIG_UACCESS_WITH_MEMCPY=y
+ CONFIG_ZBOOT_ROM_TEXT=0x0
+ CONFIG_ZBOOT_ROM_BSS=0x0
+-CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,8000000 root=/dev/ram0 rw mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data)"
++CONFIG_CMDLINE="console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:at91sam9x5ek-rootfs"
++CONFIG_AUTO_ZRELADDR=y
+ CONFIG_FPE_NWFPE=y
+ # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+ CONFIG_NET=y
+@@ -37,33 +38,20 @@ CONFIG_UNIX=y
+ CONFIG_INET=y
+ CONFIG_IP_MULTICAST=y
+ CONFIG_IP_ADVANCED_ROUTER=y
+-CONFIG_IP_PNP=y
+-CONFIG_IP_PNP_DHCP=y
+ # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+ # CONFIG_INET_XFRM_MODE_TUNNEL is not set
+ # CONFIG_INET_XFRM_MODE_BEET is not set
+ # CONFIG_INET_LRO is not set
+ # CONFIG_IPV6 is not set
+ CONFIG_NETFILTER=y
+-CONFIG_NETFILTER_NETLINK_QUEUE=m
+-CONFIG_NETFILTER_NETLINK_LOG=m
++# CONFIG_NETFILTER_ADVANCED is not set
+ CONFIG_NF_CONNTRACK=y
+-CONFIG_NF_CONNTRACK_MARK=y
+-CONFIG_NF_CONNTRACK_FTP=m
+-CONFIG_NF_CT_NETLINK=m
+ CONFIG_NF_CONNTRACK_IPV4=y
+ CONFIG_IP_NF_IPTABLES=y
+ CONFIG_IP_NF_FILTER=y
+-CONFIG_IP_NF_TARGET_REJECT=m
+-CONFIG_IP_NF_TARGET_LOG=m
+-CONFIG_IP_NF_TARGET_ULOG=m
+ CONFIG_NF_NAT=y
+ CONFIG_IP_NF_TARGET_MASQUERADE=y
+-CONFIG_IP_NF_TARGET_NETMAP=y
+-CONFIG_IP_NF_TARGET_REDIRECT=y
+-CONFIG_IP_NF_RAW=m
+-CONFIG_IP_NF_ARPTABLES=m
+-CONFIG_BRIDGE=y
++CONFIG_BRIDGE=m
+ CONFIG_VLAN_8021Q=m
+ CONFIG_NET_SCHED=y
+ CONFIG_NET_SCH_CBQ=m
+@@ -76,7 +64,9 @@ CONFIG_CAN_RAW=y
+ CONFIG_CAN_DEV=y
+ CONFIG_CAN_CALC_BITTIMING=y
+ CONFIG_CAN_AT91=y
+-# CONFIG_WIRELESS is not set
++CONFIG_CFG80211=y
++CONFIG_LIB80211=y
++CONFIG_MAC80211=y
+ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+ # CONFIG_STANDALONE is not set
+ # CONFIG_PREVENT_FIRMWARE_BUILD is not set
+@@ -87,15 +77,16 @@ CONFIG_MTD_PARTITIONS=y
+ CONFIG_MTD_CMDLINE_PARTS=y
+ CONFIG_MTD_CHAR=y
+ CONFIG_MTD_BLOCK=y
+-CONFIG_MTD_M25P80=y
+ CONFIG_MTD_NAND=y
+ CONFIG_MTD_NAND_ATMEL=y
++CONFIG_MTD_UBI=y
+ CONFIG_BLK_DEV_LOOP=y
+ CONFIG_BLK_DEV_RAM=y
+ CONFIG_BLK_DEV_RAM_COUNT=4
+ CONFIG_BLK_DEV_RAM_SIZE=8192
+ CONFIG_MISC_DEVICES=y
+ CONFIG_ATMEL_TCLIB=y
++CONFIG_ATMEL_SSC=y
+ CONFIG_SCSI=y
+ CONFIG_BLK_DEV_SD=y
+ CONFIG_SCSI_MULTI_LUN=y
+@@ -107,32 +98,89 @@ CONFIG_NET_ETHERNET=y
+ CONFIG_MACB=y
+ # CONFIG_NETDEV_1000 is not set
+ # CONFIG_NETDEV_10000 is not set
+-# CONFIG_WLAN is not set
+-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+-CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
+-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
++CONFIG_LIBERTAS_THINFIRM=m
++CONFIG_LIBERTAS_THINFIRM_USB=m
++CONFIG_AT76C50X_USB=m
++CONFIG_USB_ZD1201=m
++CONFIG_RTL8187=m
++CONFIG_ATH_COMMON=m
++CONFIG_ATH9K_HTC=m
++CONFIG_AR9170_USB=m
++CONFIG_CARL9170=m
++CONFIG_B43=m
++CONFIG_B43_SDIO=y
++CONFIG_B43_PHY_N=y
++CONFIG_LIBERTAS=m
++CONFIG_LIBERTAS_USB=m
++CONFIG_LIBERTAS_SDIO=m
++CONFIG_LIBERTAS_SPI=m
++CONFIG_RT2X00=m
++CONFIG_RT2500USB=m
++CONFIG_RT73USB=m
++CONFIG_RT2800USB=m
++CONFIG_RT2800USB_RT33XX=y
++CONFIG_RT2800USB_RT35XX=y
++CONFIG_RT2800USB_UNKNOWN=y
++CONFIG_RTL8192CU=m
++CONFIG_WL1251=m
++CONFIG_WL1251_SDIO=m
++CONFIG_WL12XX_MENU=m
++CONFIG_WL12XX=m
++CONFIG_WL12XX_SDIO=m
++CONFIG_ZD1211RW=m
++# CONFIG_INPUT_MOUSEDEV is not set
+ CONFIG_INPUT_EVDEV=y
+ # CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_QT1070=y
+ CONFIG_KEYBOARD_GPIO=y
+ # CONFIG_INPUT_MOUSE is not set
+ CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+ CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
+ CONFIG_LEGACY_PTY_COUNT=8
+ CONFIG_SERIAL_ATMEL=y
+ CONFIG_SERIAL_ATMEL_CONSOLE=y
+ CONFIG_HW_RANDOM=y
++CONFIG_I2C=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_GPIO=y
+ CONFIG_SPI=y
+ CONFIG_SPI_ATMEL=y
+ CONFIG_GPIO_SYSFS=y
+ # CONFIG_HWMON is not set
+ # CONFIG_MFD_SUPPORT is not set
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_CONTROLLER=y
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2_SUBDEV_API=y
++CONFIG_VIDEO_AT91SAM9X5=y
++CONFIG_VIDEO_FIXED_MINOR_RANGES=y
++CONFIG_SOC_CAMERA=y
++CONFIG_SOC_CAMERA_OV2640=y
++CONFIG_VIDEO_ATMEL_ISI=y
++# CONFIG_V4L_USB_DRIVERS is not set
++CONFIG_VIDEO_AT91SAM9X5=y
++# CONFIG_RADIO_ADAPTERS is not set
+ CONFIG_FB=y
+ CONFIG_FB_ATMEL=y
+ CONFIG_BACKLIGHT_LCD_SUPPORT=y
+ # CONFIG_LCD_CLASS_DEVICE is not set
+ CONFIG_BACKLIGHT_CLASS_DEVICE=y
+ CONFIG_BACKLIGHT_ATMEL_LCDC=y
+-# CONFIG_BACKLIGHT_GENERIC is not set
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_SEQUENCER=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++# CONFIG_SND_SUPPORT_OLD_API is not set
++# CONFIG_SND_DRIVERS is not set
++# CONFIG_SND_ARM is not set
++# CONFIG_SND_SPI is not set
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=y
++CONFIG_SND_ATMEL_SOC=y
++CONFIG_SND_AT91_SOC_SAM9X5_WM8731=y
+ CONFIG_USB=y
+ # CONFIG_USB_DEVICE_CLASS is not set
+ CONFIG_USB_EHCI_HCD=y
+@@ -148,6 +196,10 @@ CONFIG_USB_G_SERIAL=m
+ CONFIG_USB_CDC_COMPOSITE=m
+ CONFIG_USB_G_MULTI=m
+ CONFIG_USB_G_MULTI_CDC=y
++CONFIG_MMC=y
++# CONFIG_MMC_BLOCK_BOUNCE is not set
++CONFIG_MMC_ATMELMCI=y
++CONFIG_MMC_ATMELMCI_DMA=y
+ CONFIG_NEW_LEDS=y
+ CONFIG_LEDS_CLASS=y
+ CONFIG_LEDS_GPIO=y
+@@ -162,34 +214,30 @@ CONFIG_AT_HDMAC=y
+ CONFIG_DMATEST=m
+ CONFIG_UIO=y
+ CONFIG_UIO_PDRV=m
+-CONFIG_UIO_PDRV_GENIRQ=y
++CONFIG_UIO_PDRV_GENIRQ=m
+ CONFIG_EXT2_FS=y
++CONFIG_FANOTIFY=y
+ CONFIG_MSDOS_FS=y
+ CONFIG_VFAT_FS=y
+ CONFIG_TMPFS=y
+ CONFIG_JFFS2_FS=y
+ CONFIG_JFFS2_SUMMARY=y
+-CONFIG_LOGFS=m
+-CONFIG_CRAMFS=y
++CONFIG_UBIFS_FS=y
++CONFIG_UBIFS_FS_XATTR=y
++CONFIG_UBIFS_FS_ADVANCED_COMPR=y
++CONFIG_CRAMFS=m
+ CONFIG_SQUASHFS=m
+ CONFIG_NFS_FS=y
+ CONFIG_NFS_V3=y
+ CONFIG_NFS_V4=y
+-CONFIG_ROOT_NFS=y
+ CONFIG_NLS_CODEPAGE_437=y
+ CONFIG_NLS_CODEPAGE_850=y
+ CONFIG_NLS_ISO8859_1=y
+ CONFIG_NLS_ISO8859_15=y
+ CONFIG_NLS_UTF8=y
+-# CONFIG_ENABLE_WARN_DEPRECATED is not set
+ CONFIG_DEBUG_FS=y
+-CONFIG_DEBUG_KERNEL=y
+-CONFIG_LOCKUP_DETECTOR=y
+-CONFIG_DETECT_HUNG_TASK=y
+-CONFIG_PROVE_LOCKING=y
+-CONFIG_DEBUG_SPINLOCK_SLEEP=y
+-CONFIG_DEBUG_INFO=y
+-# CONFIG_FTRACE is not set
+-# CONFIG_ARM_UNWIND is not set
+ CONFIG_DEBUG_USER=y
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_MD5=y
++CONFIG_CRYPTO_DES=y
+ # CONFIG_CRYPTO_HW is not set
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0097-AT91-input-atmel_tsadcc-rework-irq-infrastructure-an.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0097-AT91-input-atmel_tsadcc-rework-irq-infrastructure-an.patch
new file mode 100644
index 0000000..dc1df4f
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0097-AT91-input-atmel_tsadcc-rework-irq-infrastructure-an.patch
@@ -0,0 +1,191 @@
+From 562108acaa9c456611ec27d708c33d0d3e6a299e Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Thu, 16 Jun 2011 19:24:04 +0200
+Subject: [PATCH 097/107] AT91/input: atmel_tsadcc: rework irq infrastructure
+ and parameters
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ arch/arm/mach-at91/board-sam9x5ek.c      |   10 +---
+ drivers/input/touchscreen/atmel_tsadcc.c |   70 +++++++++++++++++-------------
+ 2 files changed, 43 insertions(+), 37 deletions(-)
+
+diff --git a/arch/arm/mach-at91/board-sam9x5ek.c b/arch/arm/mach-at91/board-sam9x5ek.c
+index 4f64903..4626a42 100644
+--- a/arch/arm/mach-at91/board-sam9x5ek.c
++++ b/arch/arm/mach-at91/board-sam9x5ek.c
+@@ -261,13 +261,9 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data;
+  */
+ static struct at91_tsadcc_data ek_tsadcc_data = {
+ 	.adc_clock		= 300000,
+-	/*
+-	 * XXX: ukl: disable averaging for now at it's broken without a hardware
+-	 * change
+-	 */
+-	.filtering_average	= 0x00,	/* averages 2^filtering_average ADC conversions */
+-	.pendet_debounce	= 0x0d,
+-	.pendet_sensitivity	= 0x03,
++	.filtering_average	= 0x03,	/* averages 2^filtering_average ADC conversions */
++	.pendet_debounce	= 0x08,
++	.pendet_sensitivity	= 0x02,	/* 2 = set to default */
+ 	.ts_sample_hold_time	= 0x0a,
+ };
+ 
+diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c
+index 9c3b330..5209df0 100644
+--- a/drivers/input/touchscreen/atmel_tsadcc.c
++++ b/drivers/input/touchscreen/atmel_tsadcc.c
+@@ -30,6 +30,7 @@
+ #define cpu_has_9x5_adc() (cpu_is_at91sam9x5())
+ 
+ #define ADC_DEFAULT_CLOCK	100000
++#define ZTHRESHOLD		3200
+ 
+ struct atmel_tsadcc {
+ 	struct input_dev	*input;
+@@ -39,7 +40,6 @@ struct atmel_tsadcc {
+ 	unsigned int		prev_absx;
+ 	unsigned int		prev_absy;
+ 	unsigned int		prev_absz;
+-	unsigned char		bufferedmeasure;
+ };
+ 
+ static void __iomem		*tsc_base;
+@@ -62,6 +62,7 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ {
+ 	struct atmel_tsadcc	*ts_dev = (struct atmel_tsadcc *)dev;
+ 	struct input_dev	*input_dev = ts_dev->input;
++	struct at91_tsadcc_data *pdata = input_dev->dev.parent->platform_data;
+ 
+ 	unsigned int status;
+ 	unsigned int reg;
+@@ -76,7 +77,7 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 		/* Contact lost */
+ 		if (cpu_has_9x5_adc()) {
+ 			/* 9X5 using TSMR to set PENDBC time */
+-			reg = atmel_tsadcc_read(ATMEL_TSADCC_TSMR) | ATMEL_TSADCC_PENDBC;
++			reg = atmel_tsadcc_read(ATMEL_TSADCC_TSMR) | ((pdata->pendet_debounce << 28) & ATMEL_TSADCC_PENDBC);
+ 			atmel_tsadcc_write(ATMEL_TSADCC_TSMR, reg);
+ 		} else {
+ 			reg = atmel_tsadcc_read(ATMEL_TSADCC_MR) | ATMEL_TSADCC_PENDBC;
+@@ -88,7 +89,6 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 		atmel_tsadcc_write(ATMEL_TSADCC_IER, ATMEL_TSADCC_PENCNT);
+ 
+ 		input_report_key(input_dev, BTN_TOUCH, 0);
+-		ts_dev->bufferedmeasure = 0;
+ 		input_sync(input_dev);
+ 
+ 	} else if (status & ATMEL_TSADCC_PENCNT) {
+@@ -118,27 +118,20 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 	} else if ((status & ATMEL_TSADCC_CONVERSION_END) == ATMEL_TSADCC_CONVERSION_END) {
+ 		/* Conversion finished */
+ 
+-		if (ts_dev->bufferedmeasure) {
+-			/* Last measurement is always discarded, since it can
+-			 * be erroneous.
+-			 * Always report previous measurement */
+-			dev_dbg(&input_dev->dev,
+-					"x = %d, y = %d, pressure = %d\n",
+-					ts_dev->prev_absx, ts_dev->prev_absy,
+-					ts_dev->prev_absz);
+-			input_report_abs(input_dev, ABS_X, ts_dev->prev_absx);
+-			input_report_abs(input_dev, ABS_Y, ts_dev->prev_absy);
+-			input_report_key(input_dev, BTN_TOUCH, 1);
+-			if (cpu_has_9x5_adc())
+-				input_report_abs(input_dev, ABS_PRESSURE, ts_dev->prev_absz);
+-			input_sync(input_dev);
+-		} else
+-			ts_dev->bufferedmeasure = 1;
+-
+-		/* Now make new measurement */
++		/* make new measurement */
+ 		if (cpu_has_9x5_adc()) {
+-			ts_dev->prev_absx = atmel_tsadcc_read(ATMEL_TSADCC_XPOSR) & 0xffff;
+-			ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_YPOSR) & 0xffff;
++			unsigned int xscale, yscale;
++
++			/* calculate position */
++			reg = atmel_tsadcc_read(ATMEL_TSADCC_XPOSR);
++			ts_dev->prev_absx = (reg & ATMEL_TSADCC_XPOS) << 10;
++			xscale = (reg & ATMEL_TSADCC_XSCALE) >> 16;
++			ts_dev->prev_absx /= xscale ? xscale: 1;
++
++			reg = atmel_tsadcc_read(ATMEL_TSADCC_YPOSR);
++			ts_dev->prev_absy = (reg & ATMEL_TSADCC_YPOS) << 10;
++			yscale = (reg & ATMEL_TSADCC_YSCALE) >> 16;
++			ts_dev->prev_absy /= yscale ? yscale: 1 << 10;
+ 
+ 			/* calculate the pressure */
+ 			reg = atmel_tsadcc_read(ATMEL_TSADCC_PRESSR);
+@@ -157,6 +150,23 @@ static irqreturn_t atmel_tsadcc_interrupt(int irq, void *dev)
+ 			ts_dev->prev_absy = atmel_tsadcc_read(ATMEL_TSADCC_CDR1) << 10;
+ 			ts_dev->prev_absy /= atmel_tsadcc_read(ATMEL_TSADCC_CDR0);
+ 		}
++
++		/* report measurement to input layer */
++		if (ts_dev->prev_absz < ZTHRESHOLD) {
++			dev_dbg(&input_dev->dev,
++					"x = %d, y = %d, pressure = %d\n",
++					ts_dev->prev_absx, ts_dev->prev_absy,
++					ts_dev->prev_absz);
++			input_report_abs(input_dev, ABS_X, ts_dev->prev_absx);
++			input_report_abs(input_dev, ABS_Y, ts_dev->prev_absy);
++			if (cpu_has_9x5_adc())
++				input_report_abs(input_dev, ABS_PRESSURE, ts_dev->prev_absz);
++			input_report_key(input_dev, BTN_TOUCH, 1);
++			input_sync(input_dev);
++		} else {
++			dev_dbg(&input_dev->dev,
++					"pressure too low: not reporting\n");
++		}
+ 	}
+ 
+ 	return IRQ_HANDLED;
+@@ -233,7 +243,6 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	ts_dev->input = input_dev;
+-	ts_dev->bufferedmeasure = 0;
+ 
+ 	snprintf(ts_dev->phys, sizeof(ts_dev->phys),
+ 		 "%s/input0", dev_name(&pdev->dev));
+@@ -275,10 +284,10 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
+ 	dev_info(&pdev->dev, "Prescaler is set at: %d\n", prsc);
+ 
+ 	if (cpu_has_9x5_adc()) {
+-		reg = 	((0x01 << 5) & ATMEL_TSADCC_SLEEP)	|	/* Sleep Mode */
+-			((0x01 << 6) & ATMEL_TSADCC_FWUP)	|	/* Fast Wake Up */
++		reg = 	((0x00 << 5) & ATMEL_TSADCC_SLEEP)	|	/* no Sleep Mode */
++			((0x00 << 6) & ATMEL_TSADCC_FWUP)	|	/* no Fast Wake Up needed */
+ 			(prsc << 8)				|
+-			((0x8 << 16) & ATMEL_TSADCC_STARTUP)	|
++			((0x4 << 16) & ATMEL_TSADCC_STARTUP)	|
+ 			((pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TRACKTIM);
+ 	} else {
+ 		reg = ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE		|
+@@ -296,10 +305,10 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
+ 	if (cpu_has_9x5_adc()) {
+ 		atmel_tsadcc_write(ATMEL_TSADCC_TSMR,
+ 					ATMEL_TSADCC_TSMODE_4WIRE_PRESS	|
+-					(pdata->filtering_average << 4)	|	/* Touchscreen average */
++					((pdata->filtering_average << 4) & ATMEL_TSADCC_TSAV) |	/* Touchscreen average */
+ 					ATMEL_TSADCC_NOTSDMA		|
+ 					ATMEL_TSADCC_PENDET_ENA		|
+-					(pdata->pendet_debounce << 28)	|
++					((pdata->pendet_debounce << 28) & ATMEL_TSADCC_PENDBC) |
+ 					(0x3 << 8));				/* Touchscreen freq */
+ 	} else {
+ 		atmel_tsadcc_write(ATMEL_TSADCC_TSR,
+@@ -312,7 +321,8 @@ static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
+ 	 * option only available on ES2 and higher
+ 	 */
+ 	if (cpu_has_9x5_adc()) {
+-		atmel_tsadcc_write(ATMEL_TSADCC_ACR, pdata->pendet_sensitivity);
++		if (pdata->pendet_sensitivity <= ATMEL_TSADCC_PENDET_SENSITIVITY)
++			atmel_tsadcc_write(ATMEL_TSADCC_ACR, pdata->pendet_sensitivity);
+ 	}
+ 
+ 	atmel_tsadcc_read(ATMEL_TSADCC_SR);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0098-5series-Update-LCD-timings-to-avoid-flickering.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0098-5series-Update-LCD-timings-to-avoid-flickering.patch
new file mode 100644
index 0000000..6abef90
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0098-5series-Update-LCD-timings-to-avoid-flickering.patch
@@ -0,0 +1,33 @@
+From 4d939804a14dc62b4096486c8e3ab20c14976f15 Mon Sep 17 00:00:00 2001
+From: Patrice Vilchez <patrice.vilchez@atmel.com>
+Date: Mon, 20 Jun 2011 13:39:37 +0200
+Subject: [PATCH 098/107] 5series: Update LCD timings to avoid flickering
+
+Timings changed according to FoxLink LCD datasheet.
+
+Signed-off-by: Patrice Vilchez <patrice.vilchez@atmel.com>
+---
+ arch/arm/mach-at91/board-sam9x5ek.c |    6 +++---
+ 1 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-at91/board-sam9x5ek.c b/arch/arm/mach-at91/board-sam9x5ek.c
+index 4626a42..ce801ee 100644
+--- a/arch/arm/mach-at91/board-sam9x5ek.c
++++ b/arch/arm/mach-at91/board-sam9x5ek.c
+@@ -212,10 +212,10 @@ static struct fb_videomode at91_tft_vga_modes[] = {
+ 		.name           = "LG",
+ 		.refresh	= 60,
+ 		.xres		= 800,		.yres		= 480,
+-		.pixclock	= KHZ2PICOS(22223),
++		.pixclock	= KHZ2PICOS(33260),
+ 
+-		.left_margin	= 64,		.right_margin	= 64,
+-		.upper_margin	= 22,		.lower_margin	= 21,
++		.left_margin	= 88,		.right_margin	= 168,
++		.upper_margin	= 8,		.lower_margin	= 37,
+ 		.hsync_len	= 128,		.vsync_len	= 2,
+ 
+ 		.sync		= 0,
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0099-atmel_lcdfb-change-pixel-clock-ratio-calculation.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0099-atmel_lcdfb-change-pixel-clock-ratio-calculation.patch
new file mode 100644
index 0000000..0950f88
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0099-atmel_lcdfb-change-pixel-clock-ratio-calculation.patch
@@ -0,0 +1,31 @@
+From 335ac3c48f86475d261504d9fed3dd3cb728a804 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Fri, 24 Jun 2011 13:03:29 +0200
+Subject: [PATCH 099/107] atmel_lcdfb: change pixel clock ratio calculation
+
+DIV_ROUND_UP() was used to calculate the pixel clock divider
+in atmel_hlcdfb_setup_core_base().
+But this rounding was producing a bigger divider each time it was called.
+We replace by DIV_ROUND_CLOSEST() to calculate it.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ drivers/video/atmel_hlcdfb.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
+index 346bb80..fde9009 100644
+--- a/drivers/video/atmel_hlcdfb.c
++++ b/drivers/video/atmel_hlcdfb.c
+@@ -246,7 +246,7 @@ static int atmel_hlcdfb_setup_core_base(struct fb_info *info)
+ 	/* Set pixel clock */
+ 	clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+ 
+-	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
++	value = DIV_ROUND_CLOSEST(clk_value_khz, PICOS2KHZ(info->var.pixclock));
+ 
+ 	if (value < 1) {
+ 		dev_notice(info->device, "using system clock as pixel clock\n");
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0100-MTD-atmel_nand_pmecc-fix-warning-about-uninitialized.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0100-MTD-atmel_nand_pmecc-fix-warning-about-uninitialized.patch
new file mode 100644
index 0000000..f220350
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0100-MTD-atmel_nand_pmecc-fix-warning-about-uninitialized.patch
@@ -0,0 +1,27 @@
+From 06cfbe5a6d459d57415606e3034749d41b133e47 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 28 Jun 2011 15:37:21 +0200
+Subject: [PATCH 100/107] MTD: atmel_nand_pmecc: fix warning about
+ uninitialized variable
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ drivers/mtd/nand/atmel_nand_pmecc.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/mtd/nand/atmel_nand_pmecc.c b/drivers/mtd/nand/atmel_nand_pmecc.c
+index 3230666..289e4a5 100644
+--- a/drivers/mtd/nand/atmel_nand_pmecc.c
++++ b/drivers/mtd/nand/atmel_nand_pmecc.c
+@@ -494,7 +494,7 @@ static void atmel_nand_pmecc_write_page(struct mtd_info *mtd,
+ 
+ static void atmel_init_pmecc(struct mtd_info *mtd)
+ {
+-	uint32_t val;
++	uint32_t val = 0;
+ 	struct nand_chip *nand_chip = mtd->priv;
+ 	struct atmel_nand_host *host = nand_chip->priv;
+ 	struct nand_ecclayout *ecc_layout;
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0101-MTD-atmel_nand-fix-wrong-use-of-0-as-NULL.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0101-MTD-atmel_nand-fix-wrong-use-of-0-as-NULL.patch
new file mode 100644
index 0000000..a131811
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0101-MTD-atmel_nand-fix-wrong-use-of-0-as-NULL.patch
@@ -0,0 +1,29 @@
+From bbb862609be395eed477794daf28cec8ec9c1b73 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 28 Jun 2011 16:03:24 +0200
+Subject: [PATCH 101/107] MTD: atmel_nand: fix wrong use of 0 as NULL
+
+Fixing this error:
+atmel_nand.c:718:20: warning: Using plain integer as NULL pointer
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ drivers/mtd/nand/atmel_nand.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index c4e07be..9f990b9 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -715,7 +715,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 
+ 		dma_cap_zero(mask);
+ 		dma_cap_set(DMA_MEMCPY, mask);
+-		host->dma_chan = dma_request_channel(mask, 0, NULL);
++		host->dma_chan = dma_request_channel(mask, NULL, NULL);
+ 		if (!host->dma_chan) {
+ 			dev_err(host->dev, "Failed to request DMA channel\n");
+ 			use_dma = 0;
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0102-ASoC-wm8731-active-bit-and-OSC-management.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0102-ASoC-wm8731-active-bit-and-OSC-management.patch
new file mode 100644
index 0000000..d40140c
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0102-ASoC-wm8731-active-bit-and-OSC-management.patch
@@ -0,0 +1,98 @@
+From e53520aa1f4e3c6d59e224b57d2b80326c6e30b6 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 5 Jul 2011 11:08:43 +0200
+Subject: [PATCH 102/107] ASoC: wm8731: active bit and OSC management
+
+Is a merge of several updates from ASoC:
+- remove the OSC special management: now OSC deal with it in 2.6.39
+- adding "Manage WM8731 ACTIVE bit as a supply widget" patch from Mark Brown
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ sound/soc/codecs/wm8731.c |   34 ++++------------------------------
+ 1 files changed, 4 insertions(+), 30 deletions(-)
+
+diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c
+index ec176b6..1af0548 100644
+--- a/sound/soc/codecs/wm8731.c
++++ b/sound/soc/codecs/wm8731.c
+@@ -175,6 +175,7 @@ static const struct snd_kcontrol_new wm8731_input_mux_controls =
+ SOC_DAPM_ENUM("Input Select", wm8731_insel_enum);
+ 
+ static const struct snd_soc_dapm_widget wm8731_dapm_widgets[] = {
++SND_SOC_DAPM_SUPPLY("ACTIVE",WM8731_ACTIVE, 0, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("OSC", WM8731_PWR, 5, 1, NULL, 0),
+ SND_SOC_DAPM_MIXER("Output Mixer", WM8731_PWR, 4, 1,
+ 	&wm8731_output_mixer_controls[0],
+@@ -204,6 +205,8 @@ static int wm8731_check_osc(struct snd_soc_dapm_widget *source,
+ static const struct snd_soc_dapm_route intercon[] = {
+ 	{"DAC", NULL, "OSC", wm8731_check_osc},
+ 	{"ADC", NULL, "OSC", wm8731_check_osc},
++	{"DAC", NULL, "ACTIVE"},
++	{"ADC", NULL, "ACTIVE"},
+ 
+ 	/* output mixer */
+ 	{"Output Mixer", "Line Bypass Switch", "Line Input"},
+@@ -326,29 +329,6 @@ static int wm8731_hw_params(struct snd_pcm_substream *substream,
+ 	return 0;
+ }
+ 
+-static int wm8731_pcm_prepare(struct snd_pcm_substream *substream,
+-			      struct snd_soc_dai *dai)
+-{
+-	struct snd_soc_codec *codec = dai->codec;
+-
+-	/* set active */
+-	snd_soc_write(codec, WM8731_ACTIVE, 0x0001);
+-
+-	return 0;
+-}
+-
+-static void wm8731_shutdown(struct snd_pcm_substream *substream,
+-			    struct snd_soc_dai *dai)
+-{
+-	struct snd_soc_codec *codec = dai->codec;
+-
+-	/* deactivate */
+-	if (!codec->active) {
+-		udelay(50);
+-		snd_soc_write(codec, WM8731_ACTIVE, 0x0);
+-	}
+-}
+-
+ static int wm8731_mute(struct snd_soc_dai *dai, int mute)
+ {
+ 	struct snd_soc_codec *codec = dai->codec;
+@@ -491,9 +471,7 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec,
+ 		snd_soc_write(codec, WM8731_PWR, reg | 0x0040);
+ 		break;
+ 	case SND_SOC_BIAS_OFF:
+-		snd_soc_write(codec, WM8731_ACTIVE, 0x0);
+-		/* standby: keep crystal oscillator enabled */
+-		snd_soc_write(codec, WM8731_PWR, 0x00df);
++		snd_soc_write(codec, WM8731_PWR, 0xffff);
+ 		regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies),
+ 				       wm8731->supplies);
+ 		break;
+@@ -508,9 +486,7 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec,
+ 	SNDRV_PCM_FMTBIT_S24_LE)
+ 
+ static struct snd_soc_dai_ops wm8731_dai_ops = {
+-	.prepare	= wm8731_pcm_prepare,
+ 	.hw_params	= wm8731_hw_params,
+-	.shutdown	= wm8731_shutdown,
+ 	.digital_mute	= wm8731_mute,
+ 	.set_sysclk	= wm8731_set_dai_sysclk,
+ 	.set_fmt	= wm8731_set_dai_fmt,
+@@ -545,8 +521,6 @@ static int wm8731_suspend(struct snd_soc_codec *codec, pm_message_t state)
+ static int wm8731_resume(struct snd_soc_codec *codec)
+ {
+ 	wm8731_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+-	if (codec->active)
+-		snd_soc_write(codec, WM8731_ACTIVE, 0x0001);
+ 
+ 	return 0;
+ }
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0103-AT91-at91sam9x5-add-can-clocks-to-9x25-chip.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0103-AT91-at91sam9x5-add-can-clocks-to-9x25-chip.patch
new file mode 100644
index 0000000..78d638b
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0103-AT91-at91sam9x5-add-can-clocks-to-9x25-chip.patch
@@ -0,0 +1,27 @@
+From 27e57621faa944f78e07acd48b9ec4b6fc0611eb Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 5 Jul 2011 17:21:11 +0200
+Subject: [PATCH 103/107] AT91: at91sam9x5: add can clocks to 9x25 chip
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ arch/arm/mach-at91/at91sam9x5.c |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
+index de456e6..c1b071b 100644
+--- a/arch/arm/mach-at91/at91sam9x5.c
++++ b/arch/arm/mach-at91/at91sam9x5.c
+@@ -294,7 +294,8 @@ static void __init at91sam9x5_register_clocks(void)
+ 	if (cpu_is_at91sam9x25())
+ 		clk_register(&macb1_clk);
+ 
+-	if (cpu_is_at91sam9x35()) {
++	if (cpu_is_at91sam9x25()
++	|| cpu_is_at91sam9x35()) {
+ 		clk_register(&can0_clk);
+ 		clk_register(&can1_clk);
+ 	}
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0104-AT91-LCD-include-remove-not-needed-comment.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0104-AT91-LCD-include-remove-not-needed-comment.patch
new file mode 100644
index 0000000..1ce9695
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0104-AT91-LCD-include-remove-not-needed-comment.patch
@@ -0,0 +1,27 @@
+From 73a398fad996d19d50cf61dfdaf9b96c3f62634f Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Wed, 6 Jul 2011 15:29:39 +0200
+Subject: [PATCH 104/107] AT91: LCD include: remove not needed comment
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ arch/arm/mach-at91/include/mach/atmel_hlcdc.h |    3 ---
+ 1 files changed, 0 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-at91/include/mach/atmel_hlcdc.h b/arch/arm/mach-at91/include/mach/atmel_hlcdc.h
+index 0b26f27..24b38d1 100644
+--- a/arch/arm/mach-at91/include/mach/atmel_hlcdc.h
++++ b/arch/arm/mach-at91/include/mach/atmel_hlcdc.h
+@@ -29,9 +29,6 @@
+ #define LCDC_LCDCFG0_CLKPWMSEL		(0x1 << 3)
+ #define LCDC_LCDCFG0_CGDISBASE		(0x1 << 8)
+ #define LCDC_LCDCFG0_CGDISOVR1		(0x1 << 9)
+-/* XXX: maybe this is 1 << 10? At least the LCD Interrupt registers
+- * use 10 while the documentation specifies 11.
+- */
+ #define LCDC_LCDCFG0_CGDISHEO		(0x1 << 11)
+ #define LCDC_LCDCFG0_CGDISHCR		(0x1 << 12)
+ #define LCDC_LCDCFG0_CLKDIV_OFFSET	16
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0105-AT91-5series-fix-SPI0-MCI1-ISI-pins-conflicts-in-boa.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0105-AT91-5series-fix-SPI0-MCI1-ISI-pins-conflicts-in-boa.patch
new file mode 100644
index 0000000..a5b6866
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0105-AT91-5series-fix-SPI0-MCI1-ISI-pins-conflicts-in-boa.patch
@@ -0,0 +1,102 @@
+From 518000b8060b353c9b303e20d43efc3cdac1bc59 Mon Sep 17 00:00:00 2001
+From: Elen Song <elen.song@atmel.com>
+Date: Thu, 18 Aug 2011 09:34:51 +0800
+Subject: [PATCH 105/107] AT91: 5series: fix SPI0/MCI1/ISI pins conflicts in
+ board file
+
+ISI's PWD pin confilct with MCI1_CK and SPI0_CK due to hardware design.
+This cause spi flash can not work while ISI is enable. Do not add ISI device
+while SPI0 is enable, and do not add MCI1 while SPI0 or ISI is enable.
+Add print conflict information.
+
+Signed-off-by: Elen Song <elen.song@atmel.com>
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ arch/arm/mach-at91/board-sam9x5ek.c |   40 ++++++++++++++++++++++++++++-------
+ 1 files changed, 32 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/mach-at91/board-sam9x5ek.c b/arch/arm/mach-at91/board-sam9x5ek.c
+index ce801ee..ea49a23 100644
+--- a/arch/arm/mach-at91/board-sam9x5ek.c
++++ b/arch/arm/mach-at91/board-sam9x5ek.c
+@@ -376,6 +376,8 @@ static void __init ek_board_configure_pins(void)
+ static void __init ek_board_init(void)
+ {
+ 	u32 cm_config;
++	int i;
++	bool config_isi_enabled = false;
+ 
+ 	cm_board_init(&cm_config);
+ 	ek_board_configure_pins();
+@@ -389,11 +391,8 @@ static void __init ek_board_init(void)
+ 	/* Ethernet */
+ 	at91_add_device_eth(0, &ek_macb0_data);
+ 	at91_add_device_eth(1, &ek_macb1_data);
+-	/* MMC */
++	/* MMC0 */
+ 	at91_add_device_mci(0, &mci0_data);
+-	/* Conflict between SPI0 and MCI1 pins */
+-	if (!(cm_config & CM_CONFIG_SPI0_ENABLE))
+-		at91_add_device_mci(1, &mci1_data);
+ 	/* I2C */
+ 	if (cm_config & CM_CONFIG_I2C0_ENABLE)
+ 		i2c_register_board_info(0,
+@@ -405,12 +404,22 @@ static void __init ek_board_init(void)
+ 	if (cpu_is_at91sam9g25()) {
+ 		/* ISI */
+ 		/* NOTE: PCK0 provides ISI_MCK to the ISI module.
+-		   ISI's PWD pin conflict with MCI1_CK due the hardware design.
++		 * ISI's PWD pin (PA13) conflicts with MCI1_CK, and SPI0_SPCK
++		 * due to hardware design.
++		 * Do not add ISI device if SPI0 is enabled.
+ 		 */
+-		platform_add_devices(soc_camera_devices,
++		 if (!(cm_config & CM_CONFIG_SPI0_ENABLE)) {
++			platform_add_devices(soc_camera_devices,
+ 					ARRAY_SIZE(soc_camera_devices));
+-		isi_set_clk();
+-		at91_add_device_isi(&isi_data);
++			isi_set_clk();
++			at91_add_device_isi(&isi_data);
++			for (i = 0; i < ARRAY_SIZE(soc_camera_devices); i++) {
++				if (soc_camera_devices[i]->name != NULL) {
++					config_isi_enabled = true;
++					break;
++				}
++			}
++		 }
+ 	} else if (!cpu_is_at91sam9x25()) {
+ 		/* LCD Controller */
+ 		at91_add_device_lcdc(&ek_lcdc_data);
+@@ -418,6 +427,13 @@ static void __init ek_board_init(void)
+ 		at91_add_device_tsadcc(&ek_tsadcc_data);
+ 	}
+ 
++	/* MMC1 */
++	/* Conflict between SPI0, MCI1 and ISI pins.
++	 * add MCI1 only if SPI0 and ISI are both disabled.
++	 */
++	if (!(cm_config & CM_CONFIG_SPI0_ENABLE) && !config_isi_enabled)
++		at91_add_device_mci(1, &mci1_data);
++
+ #if 0
+ 	if (cpu_is_at91sam9x25() || cpu_is_at91sam9x35())
+ 		/*
+@@ -443,6 +459,14 @@ static void __init ek_board_init(void)
+ 		printk(KERN_CRIT "AT91: EK rev A\n");
+ 	else
+ 		printk(KERN_CRIT "AT91: EK rev B and higher\n");
++
++	/* print conflict information */
++	if (cm_config & CM_CONFIG_SPI0_ENABLE)
++		printk(KERN_CRIT
++			"AT91: SPI0 conflicts with MCI1 and ISI, disable MCI1 and ISI\n");
++	else if (config_isi_enabled)
++		printk(KERN_CRIT
++			"AT91: ISI conficts with MCI1, disable MCI1\n");
+ }
+ 
+ MACHINE_START(AT91SAM9X5EK, "Atmel AT91SAM9X5-EK")
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0106-PMECC-Fix-bug-incorrect-register-address-for-remaind.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0106-PMECC-Fix-bug-incorrect-register-address-for-remaind.patch
new file mode 100644
index 0000000..187ba53
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0106-PMECC-Fix-bug-incorrect-register-address-for-remaind.patch
@@ -0,0 +1,27 @@
+From f689b25f100349903741cfd59cb17ca828a46eef Mon Sep 17 00:00:00 2001
+From: Hong Xu <hong.xu@atmel.com>
+Date: Thu, 3 Nov 2011 14:17:38 +0800
+Subject: [PATCH 106/107] PMECC: Fix bug: incorrect register address for
+ remainder register
+
+Signed-off-by: Hong Xu <hong.xu@atmel.com>
+---
+ drivers/mtd/nand/atmel_nand.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index 9f990b9..60dc6c9 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -77,7 +77,7 @@ module_param(on_flash_bbt, int, 0);
+ 	__raw_readb((addr) + ATMEL_PMECC_ECCx + ((sector) * 0x40) + (n))
+ 
+ #define pmecc_readl_rem(addr, sector, n) \
+-	__raw_readl((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + (n))
++	__raw_readl((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4))
+ 
+ #define pmerrloc_readl(addr, reg) \
+ 	__raw_readl((addr) + ATMEL_PMERRLOC_##reg)
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0107-ARM-at91-add-smd-device-definition.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0107-ARM-at91-add-smd-device-definition.patch
new file mode 100644
index 0000000..537a5d9
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0107-ARM-at91-add-smd-device-definition.patch
@@ -0,0 +1,112 @@
+From 7a4491817bc1a0b816722e937cdba81f41980a01 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue, 8 Nov 2011 17:27:20 +0100
+Subject: [PATCH 107/107] ARM: at91: add smd device definition
+
+This patch adds SMD definition and DMA interface in device file.
+The EK board contains a SmartDAA so we register the SMD interface
+from that board file.
+
+Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ arch/arm/mach-at91/at91sam9x5_devices.c |   54 +++++++++++++++++++++++++++++++
+ arch/arm/mach-at91/board-sam9x5ek.c     |    3 ++
+ arch/arm/mach-at91/include/mach/board.h |    3 ++
+ 3 files changed, 60 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
+index 4cafa1c..cee42dc 100644
+--- a/arch/arm/mach-at91/at91sam9x5_devices.c
++++ b/arch/arm/mach-at91/at91sam9x5_devices.c
+@@ -1469,6 +1469,60 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)
+ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
+ #endif
+ 
++/* --------------------------------------------------------------------
++ *  SMD
++ * -------------------------------------------------------------------- */
++
++static u64 smd_dmamask = DMA_BIT_MASK(32);
++static struct at_dma_slave smd_dmadata;
++
++static struct resource smd_resources[] = {
++	[0] = {
++		.start	= AT91SAM9X5_SMD_BASE,
++		.end	= AT91SAM9X5_SMD_BASE + SZ_512 - 1,
++		.flags	= IORESOURCE_MEM,
++	},
++	[1] = {
++		.start	= AT91SAM9X5_ID_SMD,
++		.end	= AT91SAM9X5_ID_SMD,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device at91sam9x5_smd_device = {
++	.name	= "atmel_smd",
++	.id	= -1,
++	.dev	= {
++		.dma_mask = &smd_dmamask,
++		.coherent_dma_mask = DMA_BIT_MASK(32),
++		.platform_data = &smd_dmadata,
++	},
++	.resource	= smd_resources,
++	.num_resources	= ARRAY_SIZE(smd_resources),
++};
++
++void __init at91_add_device_smd(void)
++{
++#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
++	struct at_dma_slave *atslave;
++
++	atslave = kzalloc(sizeof(struct at_dma_slave), GFP_KERNEL);
++
++	/* DMA slave channel configuration */
++	atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
++	atslave->cfg = ATC_FIFOCFG_HALFFIFO
++			| ATC_SRC_H2SEL_HW
++			| ATC_DST_H2SEL_HW;
++	atslave->ctrla = ATC_SCSIZE_4 | ATC_DCSIZE_4;
++	atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_SMD_RX)
++			| ATC_DST_PER(AT_DMA_ID_SMD_TX);
++	atslave->dma_dev = &at_hdmac1_device.dev;
++
++	smd_dmadata = *atslave;
++#endif
++
++	platform_device_register(&at91sam9x5_smd_device);
++}
+ 
+ /* --------------------------------------------------------------------
+  *  UART
+diff --git a/arch/arm/mach-at91/board-sam9x5ek.c b/arch/arm/mach-at91/board-sam9x5ek.c
+index ea49a23..8c06040 100644
+--- a/arch/arm/mach-at91/board-sam9x5ek.c
++++ b/arch/arm/mach-at91/board-sam9x5ek.c
+@@ -455,6 +455,9 @@ static void __init ek_board_init(void)
+ 	/* SSC (for WM8731) */
+ 	at91_add_device_ssc(AT91SAM9X5_ID_SSC, ATMEL_SSC_TX | ATMEL_SSC_RX);
+ 
++	/* SMD */
++	at91_add_device_smd();
++
+ 	if (ek_is_revA())
+ 		printk(KERN_CRIT "AT91: EK rev A\n");
+ 	else
+diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
+index cf8d780..04dcec1 100644
+--- a/arch/arm/mach-at91/include/mach/board.h
++++ b/arch/arm/mach-at91/include/mach/board.h
+@@ -211,6 +211,9 @@ extern void __init at91_add_device_can(int id, struct at91_can_data *data);
+ extern void __init at91_add_device_can(struct at91_can_data *data);
+ #endif
+ 
++ /* SMD */
++extern void __init at91_add_device_smd(void);
++
+  /* LEDs */
+ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
+ extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
+-- 
+1.7.5.4
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0001-Revert-MTD-atmel_nand-Add-PMECC-controller-support.patch b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0001-Revert-MTD-atmel_nand-Add-PMECC-controller-support.patch
new file mode 100644
index 0000000..e83822b
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0001-Revert-MTD-atmel_nand-Add-PMECC-controller-support.patch
@@ -0,0 +1,1177 @@
+From 0bc01b4e2b487f7ca9d15e3e05c9da68ed7d62b4 Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Wed, 26 Dec 2012 11:46:00 +0800
+Subject: [PATCH 1/9] Revert "MTD: atmel_nand: Add PMECC controller support"
+
+This reverts commit f3b6daeff4340b90ce98966871fbbdd3e1249578.
+
+prepare to use mainline PMECC patch.
+
+Conflicts:
+
+	drivers/mtd/nand/atmel_nand_pmecc.c
+
+Conflicts:
+
+	drivers/mtd/nand/atmel_nand.c
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+---
+ drivers/mtd/nand/Kconfig            |   17 -
+ drivers/mtd/nand/atmel_nand.c       |  236 ++++--------
+ drivers/mtd/nand/atmel_nand_ecc.h   |   84 -----
+ drivers/mtd/nand/atmel_nand_pmecc.c |  674 -----------------------------------
+ 4 files changed, 64 insertions(+), 947 deletions(-)
+ delete mode 100644 drivers/mtd/nand/atmel_nand_pmecc.c
+
+diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
+index b7b870c..edec457 100644
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -371,23 +371,6 @@ config MTD_NAND_ATMEL_ECC_HW
+ 
+ 	  If unsure, say Y
+ 
+-config MTD_NAND_ATMEL_PMECC_HW
+-	bool "Programmable Hardware ECC (BCH code)"
+-	depends on ARCH_AT91SAM9X5
+-	help
+-	  Use Programmable Hardware ECC controller.
+-
+-	  The PMECC Controller is a programmable binary BCH (Bose, Chaudhuri
+-	  and Hocquenghem) encoder/decoder. This controller can be used to
+-	  generate redundancy information for both SLC and MLC NAND Flash
+-	  devices.
+-
+-	  NB : hardware and software ECC schemes are incompatible.
+-	  If you switch from one to another, you'll have to erase your
+-	  mtd partition.
+-
+-	  If unsure, say Y
+-
+ config MTD_NAND_ATMEL_ECC_SOFT
+ 	bool "Software ECC"
+ 	help
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index 60dc6c9..12de424 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -15,8 +15,6 @@
+  *     		(u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
+  *     (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+  *
+- *  Add PMECC support for AT91SAM9X5 Series
+- *     (C) Copyright 2011 ATMEL, Hong Xu
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+@@ -38,9 +36,7 @@
+ #include <mach/board.h>
+ #include <mach/cpu.h>
+ 
+-#if defined(CONFIG_MTD_NAND_ATMEL_ECC_HW)
+-#define hard_ecc	1
+-#elif defined(CONFIG_MTD_NAND_ATMEL_PMECC_HW)
++#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
+ #define hard_ecc	1
+ #else
+ #define hard_ecc	0
+@@ -55,8 +51,6 @@
+ static int use_dma = 1;
+ module_param(use_dma, int, 0);
+ 
+-#define NB_ERROR_MAX  25
+-
+ static int on_flash_bbt = 0;
+ module_param(on_flash_bbt, int, 0);
+ 
+@@ -66,38 +60,8 @@ module_param(on_flash_bbt, int, 0);
+ #define ecc_writel(add, reg, value)			\
+ 	__raw_writel((value), add + ATMEL_ECC_##reg)
+ 
+-/* Register access macros for PMECC */
+-#define pmecc_readl(addr, reg) \
+-	__raw_readl((addr) + ATMEL_PMECC_##reg)
+-
+-#define pmecc_writel(addr, reg, value) \
+-	__raw_writel((value), (addr) + ATMEL_PMECC_##reg)
+-
+-#define pmecc_readb_ecc(addr, sector, n) \
+-	__raw_readb((addr) + ATMEL_PMECC_ECCx + ((sector) * 0x40) + (n))
+-
+-#define pmecc_readl_rem(addr, sector, n) \
+-	__raw_readl((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4))
+-
+-#define pmerrloc_readl(addr, reg) \
+-	__raw_readl((addr) + ATMEL_PMERRLOC_##reg)
+-
+-#define pmerrloc_writel(addr, reg, value) \
+-	__raw_writel((value), (addr) + ATMEL_PMERRLOC_##reg)
+-
+-#define pmerrloc_writel_sigma(addr, n, value) \
+-	__raw_writel((value), (addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
+-
+-#define pmerrloc_readl_sigma(addr, n) \
+-	__raw_readl((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
+-
+-#define pmerrloc_readl_el(addr, n) \
+-	__raw_readl((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
++#include "atmel_nand_ecc.h"	/* Hardware ECC registers */
+ 
+-/* Include Hardware ECC registers */
+-#include "atmel_nand_ecc.h"
+-
+-#if defined(CONFIG_MTD_NAND_ATMEL_ECC_HW)
+ /* oob layout for large page size
+  * bad block info is on bytes 0 and 1
+  * the bytes have to be consecutives to avoid
+@@ -123,7 +87,6 @@ static struct nand_ecclayout atmel_oobinfo_small = {
+ 		{6, 10}
+ 	},
+ };
+-#endif
+ 
+ struct atmel_nand_host {
+ 	struct nand_chip	nand_chip;
+@@ -136,45 +99,11 @@ struct atmel_nand_host {
+ 
+ 	struct completion	comp;
+ 	struct dma_chan		*dma_chan;
+-
+-#if defined(CONFIG_MTD_NAND_ATMEL_PMECC_HW)
+-	void __iomem		*pmerrloc_base;
+-	void __iomem		*rom_base;
+-	/* defines the error correcting capability */
+-	int tt;
+-	/* The number of ecc bytes for one sector */
+-	int ecc_bytes_per_sector;
+-	/* degree of the remainders, GF(2**mm) */
+-	int mm;
+-	/* length of codeword, nn=2**mm -1 */
+-	int nn;
+-	/* sector number per page */
+-	int sector_number;
+-	/* sector size in bytes */
+-	int sector_size;
+-
+-	/* PMECC lookup table for alpha_to and index_of */
+-	int16_t *alpha_to;
+-	int16_t *index_of;
+-
+-	int16_t partial_syn[100];
+-	int16_t si[100];
+-	/* Sigma table */
+-	int16_t smu[NB_ERROR_MAX + 2][2 * NB_ERROR_MAX + 1];
+-	/** polynomal order */
+-	int16_t lmu[NB_ERROR_MAX + 1];
+-	uint8_t ecc_table[42 * 8];
+-#endif
+ };
+ 
+-#if defined(CONFIG_MTD_NAND_ATMEL_PMECC_HW)
+-#include "atmel_nand_pmecc.c"
+-#endif
+-
+ static int cpu_has_dma(void)
+ {
+-	return cpu_is_at91sam9rl() || cpu_is_at91sam9g45()
+-	       || cpu_is_at91sam9x5();
++	return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
+ }
+ 
+ /*
+@@ -355,7 +284,6 @@ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+ 	memcpy(chip->IO_ADDR_W, (void *)pbuf, len);
+ }
+ 
+-#if defined(CONFIG_MTD_NAND_ATMEL_ECC_HW)
+ /*
+  * Calculate HW ECC
+  *
+@@ -542,84 +470,6 @@ static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
+ 	}
+ }
+ 
+-static int __init atmel_nand_init_params(struct platform_device *pdev,
+-					 struct atmel_nand_host *host)
+-{
+-	struct resource *regs;
+-	struct nand_chip *nand_chip;
+-	struct mtd_info *mtd;
+-
+-	nand_chip = &host->nand_chip;
+-	mtd = &host->mtd;
+-
+-	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+-	if (!regs && hard_ecc) {
+-		dev_err(host->dev, "atmel_nand: can't get I/O resource "
+-				"regs\nFalling back on software ECC\n");
+-	}
+-
+-	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
+-	if (no_ecc)
+-		nand_chip->ecc.mode = NAND_ECC_NONE;
+-	if (hard_ecc && regs) {
+-		host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
+-		if (host->ecc == NULL) {
+-			printk(KERN_ERR "atmel_nand: ioremap failed\n");
+-			goto err_ecc_ioremap;
+-		}
+-
+-		nand_chip->ecc.mode = NAND_ECC_HW;
+-		nand_chip->ecc.calculate = atmel_nand_calculate;
+-		nand_chip->ecc.correct = atmel_nand_correct;
+-		nand_chip->ecc.hwctl = atmel_nand_hwctl;
+-		nand_chip->ecc.read_page = atmel_nand_read_page;
+-		nand_chip->ecc.bytes = 4;
+-	}
+-
+-	if (nand_chip->ecc.mode == NAND_ECC_HW) {
+-		/* ECC is calculated for the whole page (1 step) */
+-		nand_chip->ecc.size = mtd->writesize;
+-
+-		/* set ECC page size and oob layout */
+-		switch (mtd->writesize) {
+-		case 512:
+-			nand_chip->ecc.layout = &atmel_oobinfo_small;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
+-			break;
+-		case 1024:
+-			nand_chip->ecc.layout = &atmel_oobinfo_large;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
+-			break;
+-		case 2048:
+-			nand_chip->ecc.layout = &atmel_oobinfo_large;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
+-			break;
+-		case 4096:
+-			nand_chip->ecc.layout = &atmel_oobinfo_large;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
+-			break;
+-		default:
+-			/* page size not handled by HW ECC */
+-			/* switching back to soft ECC */
+-			nand_chip->ecc.mode = NAND_ECC_SOFT;
+-			nand_chip->ecc.calculate = NULL;
+-			nand_chip->ecc.correct = NULL;
+-			nand_chip->ecc.hwctl = NULL;
+-			nand_chip->ecc.read_page = NULL;
+-			nand_chip->ecc.postpad = 0;
+-			nand_chip->ecc.prepad = 0;
+-			nand_chip->ecc.bytes = 0;
+-			break;
+-		}
+-	}
+-
+-	return 0;
+-
+-err_ecc_ioremap:
+-	return -EIO;
+-}
+-#endif
+-
+ #ifdef CONFIG_MTD_CMDLINE_PARTS
+ static const char *part_probes[] = { "cmdlinepart", NULL };
+ #endif
+@@ -632,8 +482,9 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 	struct atmel_nand_host *host;
+ 	struct mtd_info *mtd;
+ 	struct nand_chip *nand_chip;
++	struct resource *regs;
+ 	struct resource *mem;
+-	int res = 0;
++	int res;
+ 
+ #ifdef CONFIG_MTD_PARTITIONS
+ 	struct mtd_partition *partitions = NULL;
+@@ -679,9 +530,29 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 	if (host->board->rdy_pin)
+ 		nand_chip->dev_ready = atmel_nand_device_ready;
+ 
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	if (!regs && hard_ecc) {
++		printk(KERN_ERR "atmel_nand: can't get I/O resource "
++				"regs\nFalling back on software ECC\n");
++	}
++
+ 	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
+ 	if (no_ecc)
+ 		nand_chip->ecc.mode = NAND_ECC_NONE;
++	if (hard_ecc && regs) {
++		host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
++		if (host->ecc == NULL) {
++			printk(KERN_ERR "atmel_nand: ioremap failed\n");
++			res = -EIO;
++			goto err_ecc_ioremap;
++		}
++		nand_chip->ecc.mode = NAND_ECC_HW;
++		nand_chip->ecc.calculate = atmel_nand_calculate;
++		nand_chip->ecc.correct = atmel_nand_correct;
++		nand_chip->ecc.hwctl = atmel_nand_hwctl;
++		nand_chip->ecc.read_page = atmel_nand_read_page;
++		nand_chip->ecc.bytes = 4;
++	}
+ 
+ 	nand_chip->chip_delay = 20;		/* 20us command delay time */
+ 
+@@ -733,13 +604,42 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 		goto err_scan_ident;
+ 	}
+ 
+-#if defined(CONFIG_MTD_NAND_ATMEL_ECC_HW)
+-	res = atmel_nand_init_params(pdev, host);
+-#elif defined(CONFIG_MTD_NAND_ATMEL_PMECC_HW)
+-	res = atmel_pmecc_init_params(pdev, host);
+-#endif
+-	if (res != 0)
+-		goto err;
++	if (nand_chip->ecc.mode == NAND_ECC_HW) {
++		/* ECC is calculated for the whole page (1 step) */
++		nand_chip->ecc.size = mtd->writesize;
++
++		/* set ECC page size and oob layout */
++		switch (mtd->writesize) {
++		case 512:
++			nand_chip->ecc.layout = &atmel_oobinfo_small;
++			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
++			break;
++		case 1024:
++			nand_chip->ecc.layout = &atmel_oobinfo_large;
++			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
++			break;
++		case 2048:
++			nand_chip->ecc.layout = &atmel_oobinfo_large;
++			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
++			break;
++		case 4096:
++			nand_chip->ecc.layout = &atmel_oobinfo_large;
++			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
++			break;
++		default:
++			/* page size not handled by HW ECC */
++			/* switching back to soft ECC */
++			nand_chip->ecc.mode = NAND_ECC_SOFT;
++			nand_chip->ecc.calculate = NULL;
++			nand_chip->ecc.correct = NULL;
++			nand_chip->ecc.hwctl = NULL;
++			nand_chip->ecc.read_page = NULL;
++			nand_chip->ecc.postpad = 0;
++			nand_chip->ecc.prepad = 0;
++			nand_chip->ecc.bytes = 0;
++			break;
++		}
++	}
+ 
+ 	/* second phase scan */
+ 	if (nand_scan_tail(mtd)) {
+@@ -771,7 +671,6 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 	if (!res)
+ 		return res;
+ 
+-err:
+ #ifdef CONFIG_MTD_PARTITIONS
+ err_no_partitions:
+ #endif
+@@ -783,6 +682,9 @@ err_no_card:
+ 	platform_set_drvdata(pdev, NULL);
+ 	if (host->dma_chan)
+ 		dma_release_channel(host->dma_chan);
++	if (host->ecc)
++		iounmap(host->ecc);
++err_ecc_ioremap:
+ 	iounmap(host->io_base);
+ err_nand_ioremap:
+ 	kfree(host);
+@@ -801,16 +703,6 @@ static int __exit atmel_nand_remove(struct platform_device *pdev)
+ 
+ 	atmel_nand_disable(host);
+ 
+-#if defined(CONFIG_MTD_NAND_ATMEL_PMECC_HW)
+-	if (cpu_has_pmecc())
+-			pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
+-	if (host->pmerrloc_base) {
+-		pmerrloc_writel(host->pmerrloc_base, ELDIS, 0xffffffff);
+-		iounmap(host->pmerrloc_base);
+-	}
+-	if (host->rom_base)
+-		iounmap(host->rom_base);
+-#endif
+ 	if (host->ecc)
+ 		iounmap(host->ecc);
+ 
+diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
+index 6e0e2f3..578c776 100644
+--- a/drivers/mtd/nand/atmel_nand_ecc.h
++++ b/drivers/mtd/nand/atmel_nand_ecc.h
+@@ -36,88 +36,4 @@
+ #define ATMEL_ECC_NPR		0x10			/* NParity register */
+ #define		ATMEL_ECC_NPARITY	(0xffff << 0)		/* NParity */
+ 
+-/* PMECC Register Definitions */
+-#define ATMEL_PMECC_CFG			0x000	/* Configuration Register */
+-#define		PMECC_CFG_BCH_ERR2		(0 << 0)
+-#define		PMECC_CFG_BCH_ERR4		(1 << 0)
+-#define		PMECC_CFG_BCH_ERR8		(2 << 0)
+-#define		PMECC_CFG_BCH_ERR12		(3 << 0)
+-#define		PMECC_CFG_BCH_ERR24		(4 << 0)
+-
+-#define		PMECC_CFG_SECTOR512		(0 << 4)
+-#define		PMECC_CFG_SECTOR1024		(1 << 4)
+-
+-#define		PMECC_CFG_PAGE_1SECTOR		(0 << 8)
+-#define		PMECC_CFG_PAGE_2SECTORS		(1 << 8)
+-#define		PMECC_CFG_PAGE_4SECTORS		(2 << 8)
+-#define		PMECC_CFG_PAGE_8SECTORS		(3 << 8)
+-
+-#define		PMECC_CFG_READ_OP		(0 << 12)
+-#define		PMECC_CFG_WRITE_OP		(1 << 12)
+-
+-#define		PMECC_CFG_SPARE_ENABLE		(1 << 16)
+-#define		PMECC_CFG_SPARE_DISABLE		(0 << 16)
+-
+-#define		PMECC_CFG_AUTO_ENABLE		(1 << 20)
+-#define		PMECC_CFG_AUTO_DISABLE		(0 << 20)
+-
+-#define ATMEL_PMECC_SAREA		0x004	/* Spare area size */
+-#define ATMEL_PMECC_SADDR		0x008	/* PMECC starting address */
+-#define ATMEL_PMECC_EADDR		0x00c	/* PMECC ending address */
+-#define ATMEL_PMECC_CLK			0x010	/* PMECC clock control */
+-#define		PMECC_CLK_133MHZ		(2 << 0)
+-
+-#define ATMEL_PMECC_CTRL		0x014	/* PMECC control register */
+-#define		PMECC_CTRL_RST			(1 << 0)
+-#define		PMECC_CTRL_DATA			(1 << 1)
+-#define		PMECC_CTRL_USER			(1 << 2)
+-#define		PMECC_CTRL_ENABLE		(1 << 4)
+-#define		PMECC_CTRL_DISABLE		(1 << 5)
+-
+-#define ATMEL_PMECC_SR			0x018	/* PMECC status register */
+-#define		PMECC_SR_BUSY			(1 << 0)
+-#define		PMECC_SR_ENABLE			(1 << 4)
+-
+-#define ATMEL_PMECC_IER			0x01c	/* PMECC interrupt enable */
+-#define		PMECC_IER_ENABLE		(1 << 0)
+-#define ATMEL_PMECC_IDR			0x020	/* PMECC interrupt disable */
+-#define		PMECC_IER_DISABLE		(1 << 0)
+-#define ATMEL_PMECC_IMR			0x024	/* PMECC interrupt mask */
+-#define		PMECC_IER_MASK			(1 << 0)
+-#define ATMEL_PMECC_ISR			0x028	/* PMECC interrupt status */
+-#define ATMEL_PMECC_ECCx		0x040	/* PMECC ECC x */
+-#define ATMEL_PMECC_REMx		0x240	/* PMECC REM x */
+-
+-/* PMERRLOC Register Definitions */
+-#define ATMEL_PMERRLOC_ELCFG		0x000	/* Error location config */
+-#define		PMERRLOC_ELCFG_SECTOR_512	(0 << 0)
+-#define		PMERRLOC_ELCFG_SECTOR_1024	(1 << 0)
+-#define		PMERRLOC_ELCFG_NUM_ERRORS(n)	((n) << 16)
+-
+-#define ATMEL_PMERRLOC_ELPRIM		0x004	/* Error location primitive */
+-#define ATMEL_PMERRLOC_ELEN		0x008	/* Error location enable */
+-#define ATMEL_PMERRLOC_ELDIS		0x00c	/* Error location disable */
+-#define		PMERRLOC_DISABLE		(1 << 0)
+-
+-#define ATMEL_PMERRLOC_ELSR		0x010	/* Error location status */
+-#define		PMERRLOC_ELSR_BUSY		(1 << 0)
+-#define ATMEL_PMERRLOC_ELIER		0x014	/* Error location int enable */
+-#define ATMEL_PMERRLOC_ELIDR		0x018	/* Error location int disable */
+-#define ATMEL_PMERRLOC_ELIMR		0x01c	/* Error location int mask */
+-#define ATMEL_PMERRLOC_ELISR		0x020	/* Error location int status */
+-#define		PMERRLOC_ERR_NUM_MASK		(0x1f << 8)
+-#define		PMERRLOC_CALC_DONE		(1 << 0)
+-#define ATMEL_PMERRLOC_SIGMAx		0x028	/* Error location SIGMA x */
+-#define ATMEL_PMERRLOC_ELx		0x08c	/* Error location x */
+-
+-/* Galois field dimension */
+-#define GF_DIMENSION_13			13
+-#define GF_DIMENSION_14			14
+-
+-#define PMECC_LOOKUP_TABLE_SIZE_512	0x2000
+-#define PMECC_LOOKUP_TABLE_SIZE_1024	0x4000
+-
+-#define PMECC_LOOKUP_TABLE_OFFSET_512	0x8000
+-#define PMECC_LOOKUP_TABLE_OFFSET_1024	0x10000
+-
+ #endif
+diff --git a/drivers/mtd/nand/atmel_nand_pmecc.c b/drivers/mtd/nand/atmel_nand_pmecc.c
+deleted file mode 100644
+index 289e4a5..0000000
+--- a/drivers/mtd/nand/atmel_nand_pmecc.c
++++ /dev/null
+@@ -1,674 +0,0 @@
+-/*
+- * (C) Copyright 2011 ATMEL, Hong Xu
+- *
+- * PMECC related definitions and routines
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- */
+-
+-static struct nand_ecclayout pmecc_oobinfo_2048 = {
+-	.eccbytes = 16,
+-	.eccpos = { 48, 49, 50, 51, 52, 53, 54, 55,
+-		    56, 57, 58, 59, 60, 61, 62, 63
+-		  },
+-	.oobfree = {
+-		{2, 46},
+-	},
+-};
+-
+-static int cpu_has_pmecc(void)
+-{
+-	return cpu_is_at91sam9x5();
+-}
+-
+-static int16_t *pmecc_get_alpha_to(struct atmel_nand_host *host)
+-{
+-	int16_t *p;
+-
+-	if (cpu_is_at91sam9x5()) {
+-		if (host->sector_size == 512) {
+-			p = (int16_t *)((u32)host->rom_base +
+-				PMECC_LOOKUP_TABLE_OFFSET_512);
+-			return p + PMECC_LOOKUP_TABLE_SIZE_512;
+-		} else {
+-			p = (int16_t *)((u32)host->rom_base +
+-				PMECC_LOOKUP_TABLE_OFFSET_1024);
+-			return p + PMECC_LOOKUP_TABLE_SIZE_1024;
+-		}
+-	}
+-
+-	return NULL;
+-}
+-
+-static int16_t *pmecc_get_index_of(struct atmel_nand_host *host)
+-{
+-	int16_t *p = (int16_t *)host->rom_base;
+-
+-	if (cpu_is_at91sam9x5()) {
+-		if (host->sector_size == 512)
+-			p = (int16_t *)((u32)host->rom_base +
+-				PMECC_LOOKUP_TABLE_OFFSET_512);
+-		else
+-			p = (int16_t *)((u32)host->rom_base +
+-				PMECC_LOOKUP_TABLE_OFFSET_1024);
+-
+-		return p;
+-	}
+-
+-	return NULL;
+-}
+-
+-static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
+-{
+-	int i;
+-	uint32_t value;
+-	struct nand_chip *nand_chip = mtd->priv;
+-	struct atmel_nand_host *host = nand_chip->priv;
+-
+-	/* Fill odd syndromes */
+-	for (i = 0; i < host->tt; i++) {
+-		value = pmecc_readl_rem(host->ecc, sector, i / 2);
+-		if (i % 2 == 0)
+-			host->partial_syn[(2 * i) + 1] = value & 0xffff;
+-		else
+-			host->partial_syn[(2 * i) + 1] = (value & 0xffff0000)
+-							  >> 16;
+-	}
+-}
+-
+-static void pmecc_substitute(struct mtd_info *mtd)
+-{
+-	int i, j;
+-	struct nand_chip *nand_chip = mtd->priv;
+-	struct atmel_nand_host *host = nand_chip->priv;
+-	int16_t *si;
+-	int16_t *partial_syn = host->partial_syn;
+-	int16_t *alpha_to = host->alpha_to;
+-	int16_t *index_of = host->index_of;
+-
+-	/* si[] is a table that holds the current syndrome value,
+-	 * an element of that table belongs to the field
+-	 */
+-	si = host->si;
+-
+-	for (i = 1; i < 2 * NB_ERROR_MAX; i++)
+-		si[i] = 0;
+-
+-	/* Computation 2t syndromes based on S(x) */
+-	/* Odd syndromes */
+-	for (i = 1; i <= 2 * host->tt - 1; i = i + 2) {
+-		si[i] = 0;
+-		for (j = 0; j < host->mm; j++) {
+-			if (partial_syn[i] & ((unsigned short)0x1 << j))
+-				si[i] = alpha_to[(i * j)] ^ si[i];
+-		}
+-	}
+-	/* Even syndrome = (Odd syndrome) ** 2 */
+-	for (i = 2; i <= 2 * host->tt; i = i + 2) {
+-		j = i / 2;
+-		if (si[j] == 0)
+-			si[i] = 0;
+-		else
+-			si[i] = alpha_to[(2 * index_of[si[j]]) % host->nn];
+-	}
+-
+-	return;
+-}
+-
+-static void pmecc_get_sigma(struct mtd_info *mtd)
+-{
+-	int i, j, k;
+-	struct nand_chip *nand_chip = mtd->priv;
+-	struct atmel_nand_host *host = nand_chip->priv;
+-	uint32_t dmu_0_count, tmp;
+-	int16_t *lmu = host->lmu;
+-	int16_t *si = host->si;
+-	int16_t tt = host->tt;
+-	int16_t *index_of = host->index_of;
+-
+-	/* mu          */
+-	int mu[NB_ERROR_MAX + 1];
+-
+-	/* discrepancy */
+-	int dmu[NB_ERROR_MAX + 1];
+-
+-	/* delta order   */
+-	int delta[NB_ERROR_MAX + 1];
+-
+-	/* index of largest delta */
+-	int ro;
+-	int largest;
+-	int diff;
+-
+-	dmu_0_count = 0;
+-
+-	/* First Row */
+-
+-	/* Mu */
+-	mu[0] = -1;
+-
+-	/* Actually -1/2 */
+-	/* Sigma(x) set to 1 */
+-	for (i = 0; i < 2 * NB_ERROR_MAX + 1; i++)
+-		host->smu[0][i] = 0;
+-
+-	host->smu[0][0] = 1;
+-
+-	/* discrepancy set to 1 */
+-	dmu[0] = 1;
+-	/* polynom order set to 0 */
+-	lmu[0] = 0;
+-	/* delta set to -1 */
+-	delta[0]  = (mu[0] * 2 - lmu[0]) >> 1;
+-
+-	/* Second Row */
+-
+-	/* Mu */
+-	mu[1]  = 0;
+-	/* Sigma(x) set to 1 */
+-	for (i = 0; i < (2 * NB_ERROR_MAX + 1); i++)
+-		host->smu[1][i] = 0;
+-
+-	host->smu[1][0] = 1;
+-
+-	/* discrepancy set to S1 */
+-	dmu[1] = si[1];
+-
+-	/* polynom order set to 0 */
+-	lmu[1] = 0;
+-
+-	/* delta set to 0 */
+-	delta[1]  = (mu[1] * 2 - lmu[1]) >> 1;
+-
+-	/* Init the Sigma(x) last row */
+-	for (i = 0; i < (2 * NB_ERROR_MAX + 1); i++)
+-		host->smu[tt + 1][i] = 0;
+-
+-	for (i = 1; i <= tt; i++) {
+-		mu[i+1] = i << 1;
+-		/* Begin Computing Sigma (Mu+1) and L(mu) */
+-		/* check if discrepancy is set to 0 */
+-		if (dmu[i] == 0) {
+-			dmu_0_count++;
+-
+-			if ((tt - (lmu[i] >> 1) - 1) & 0x1)
+-				tmp = ((tt - (lmu[i] >> 1) - 1) / 2) + 2;
+-			else
+-				tmp = ((tt - (lmu[i] >> 1) - 1) / 2) + 1;
+-
+-			if (dmu_0_count == tmp) {
+-				for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
+-					host->smu[tt + 1][j] = host->smu[i][j];
+-
+-				lmu[tt + 1] = lmu[i];
+-				return;
+-			}
+-
+-			/* copy polynom */
+-			for (j = 0; j <= lmu[i] >> 1; j++)
+-				host->smu[i + 1][j] = host->smu[i][j];
+-
+-			/* copy previous polynom order to the next */
+-			lmu[i + 1] = lmu[i];
+-		} else {
+-			ro = 0;
+-			largest = -1;
+-			/* find largest delta with dmu != 0 */
+-			for (j = 0; j < i; j++) {
+-				if ((dmu[j]) && (delta[j] > largest)) {
+-					largest = delta[j];
+-					ro = j;
+-				}
+-			}
+-
+-			/* compute difference */
+-			diff = (mu[i] - mu[ro]);
+-
+-			/* Compute degree of the new smu polynomial */
+-			if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
+-				lmu[i + 1] = lmu[i];
+-			else
+-				lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
+-
+-			/* Init smu[i+1] with 0 */
+-			for (k = 0; k < (2 * NB_ERROR_MAX + 1); k++)
+-				host->smu[i+1][k] = 0;
+-
+-			/* Compute smu[i+1] */
+-			for (k = 0; k <= lmu[ro] >> 1; k++) {
+-				if (!(host->smu[ro][k] && dmu[i]))
+-					continue;
+-
+-				tmp = host->index_of[dmu[i]] + (host->nn -
+-				       host->index_of[dmu[ro]]) +
+-				      host->index_of[host->smu[ro][k]];
+-				host->smu[i + 1][k + diff] =
+-					host->alpha_to[tmp % host->nn];
+-			}
+-
+-			for (k = 0; k <= lmu[i] >> 1; k++)
+-				host->smu[i + 1][k] ^= host->smu[i][k];
+-		}
+-
+-		/* End Computing Sigma (Mu+1) and L(mu) */
+-		/* In either case compute delta */
+-		delta[i + 1]  = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
+-
+-		/* Do not compute discrepancy for the last iteration */
+-		if (i >= tt)
+-			continue;
+-
+-		for (k = 0 ; k <= (lmu[i + 1] >> 1); k++) {
+-			tmp = 2 * (i - 1);
+-			if (k == 0)
+-				dmu[i + 1] = si[tmp + 3];
+-			else if (host->smu[i+1][k] && si[tmp + 3 - k]) {
+-				tmp = index_of[host->smu[i + 1][k]] +
+-				      index_of[si[2 * (i - 1) + 3 - k]];
+-				tmp %= host->nn;
+-				dmu[i + 1] = host->alpha_to[tmp] ^ dmu[i + 1];
+-			}
+-		}
+-	}
+-
+-	return;
+-}
+-
+-
+-static int pmecc_err_location(struct mtd_info *mtd)
+-{
+-	int i;
+-	/* number of error */
+-	int err_nbr;
+-	/* number of roots */
+-	int roots_nbr;
+-	int gf_dimension;
+-	uint32_t val;
+-	struct nand_chip *nand_chip = mtd->priv;
+-	struct atmel_nand_host *host = nand_chip->priv;
+-
+-	if (host->sector_size == 512)
+-		gf_dimension = GF_DIMENSION_13;
+-	else
+-		gf_dimension = GF_DIMENSION_14;
+-
+-	/* Disable PMECC Error Location IP */
+-	pmerrloc_writel(host->pmerrloc_base, ELDIS, 0xffffffff);
+-	err_nbr = 0;
+-
+-	for (i = 0; i <= host->lmu[host->tt + 1] >> 1; i++) {
+-		pmerrloc_writel_sigma(host->pmerrloc_base, i,
+-				      host->smu[host->tt + 1][i]);
+-		err_nbr++;
+-	}
+-
+-	val = pmerrloc_readl(host->pmerrloc_base, ELCFG);
+-	val |= ((err_nbr - 1) << 16);
+-	pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
+-
+-	pmerrloc_writel(host->pmerrloc_base, ELEN,
+-			host->sector_size * 8 + gf_dimension * host->tt);
+-
+-	while (!(pmerrloc_readl(host->pmerrloc_base, ELISR)
+-		 & PMERRLOC_CALC_DONE))
+-		cpu_relax();
+-
+-	roots_nbr = (pmerrloc_readl(host->pmerrloc_base, ELISR)
+-		      & PMERRLOC_ERR_NUM_MASK) >> 8;
+-
+-	/* Number of roots == degree of smu hence <= tt */
+-	if (roots_nbr == host->lmu[host->tt + 1] >> 1)
+-		return err_nbr - 1;
+-
+-	/* Number of roots does not match the degree of smu
+-	 * unable to correct error */
+-	return -1;
+-}
+-
+-static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf,
+-		int extra_bytes, int err_nbr)
+-{
+-	int i = 0;
+-	int byte_pos, bit_pos;
+-	int sector_size, ecc_size;
+-	uint32_t tmp;
+-	struct nand_chip *nand_chip = mtd->priv;
+-	struct atmel_nand_host *host = nand_chip->priv;
+-
+-	sector_size = host->sector_size;
+-	/* Get number of ECC bytes */
+-	ecc_size = nand_chip->ecc.bytes;
+-
+-	while (err_nbr) {
+-		byte_pos = (pmerrloc_readl_el(host->pmerrloc_base, i) - 1) / 8;
+-		bit_pos = (pmerrloc_readl_el(host->pmerrloc_base, i) - 1) % 8;
+-		dev_dbg(host->dev, "bad : %02x: byte_pos: %d, bit_pos: %d\n",
+-			*(buf + byte_pos), byte_pos, bit_pos);
+-
+-		if (byte_pos < (sector_size + extra_bytes)) {
+-			tmp = sector_size + pmecc_readl(host->ecc, SADDR);
+-			if (byte_pos < tmp) {
+-				if (*(buf + byte_pos) & (1 << bit_pos))
+-					*(buf + byte_pos) &=
+-						(0xFF ^ (1 << bit_pos));
+-				else
+-					*(buf + byte_pos) |= (1 << bit_pos);
+-			} else {
+-				if (*(buf + byte_pos + ecc_size) &
+-				     (1 << bit_pos))
+-					*(buf + byte_pos + ecc_size) &=
+-						(0xFF ^ (1 << bit_pos));
+-				else
+-					*(buf + byte_pos + ecc_size) |=
+-						(1 << bit_pos);
+-			}
+-		}
+-		dev_dbg(host->dev, "corr: %02x\n", *(buf + byte_pos));
+-		i++;
+-		err_nbr--;
+-	}
+-
+-	return;
+-}
+-
+-static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
+-	u8 *ecc)
+-{
+-	int i, err_nbr;
+-	uint8_t *buf_pos;
+-	struct nand_chip *nand_chip = mtd->priv;
+-	int eccbytes = nand_chip->ecc.bytes;
+-	struct atmel_nand_host *host = nand_chip->priv;
+-
+-	for (i = 0; i < eccbytes; i++)
+-		if (ecc[i] != 0xff)
+-			break;
+-	/* Erased page, return OK */
+-	if (i == eccbytes)
+-		return 0;
+-
+-	pmerrloc_writel(host->pmerrloc_base, ELCFG,
+-			(host->sector_size == 512) ? 0 : 1);
+-
+-	i = 0;
+-	while (i < host->sector_number) {
+-		err_nbr = 0;
+-		if (pmecc_stat & 0x1) {
+-			buf_pos = buf + i * host->sector_size;
+-
+-			pmecc_gen_syndrome(mtd, i);
+-			pmecc_substitute(mtd);
+-			pmecc_get_sigma(mtd);
+-
+-			err_nbr = pmecc_err_location(mtd);
+-			if (err_nbr == -1) {
+-				dev_err(host->dev, "Too many error.\n");
+-				mtd->ecc_stats.failed++;
+-				return -EFAULT;
+-			} else {
+-				dev_dbg(host->dev,  "Correct bits...\n");
+-				pmecc_correct_data(mtd, buf_pos, 0, err_nbr);
+-				mtd->ecc_stats.corrected += err_nbr;
+-			}
+-		}
+-		i++;
+-		pmecc_stat >>= 1;
+-	}
+-
+-	return 0;
+-}
+-
+-static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
+-		struct nand_chip *chip, uint8_t *buf, int32_t page)
+-{
+-	struct atmel_nand_host *host = chip->priv;
+-	int eccsize = chip->ecc.size;
+-	uint32_t *eccpos = chip->ecc.layout->eccpos;
+-	int err = 0, stat;
+-	int timeout = 10;
+-	uint8_t *oob = chip->oob_poi;
+-
+-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
+-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
+-	pmecc_writel(host->ecc, CFG, (pmecc_readl(host->ecc, CFG)
+-		     & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
+-
+-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
+-
+-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
+-
+-	chip->read_buf(mtd, buf, eccsize);
+-	chip->read_buf(mtd, oob, mtd->oobsize);
+-
+-	while ((pmecc_readl(host->ecc, SR) & PMECC_SR_BUSY) && (timeout-- > 0))
+-		cpu_relax();
+-
+-	stat = pmecc_readl(host->ecc, ISR);
+-
+-	if (stat != 0) {
+-		if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]))
+-			err = -1;
+-	}
+-
+-	return err;
+-}
+-
+-static void atmel_nand_pmecc_write_page(struct mtd_info *mtd,
+-		struct nand_chip *chip, const uint8_t *buf)
+-{
+-	int i, j;
+-	int timeout = 10;
+-	struct atmel_nand_host *host = chip->priv;
+-	uint32_t *eccpos = chip->ecc.layout->eccpos;
+-
+-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
+-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
+-
+-	pmecc_writel(host->ecc, CFG, (pmecc_readl(host->ecc, CFG) |
+-		PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
+-
+-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
+-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
+-
+-	chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
+-
+-	while ((pmecc_readl(host->ecc, SR) & PMECC_SR_BUSY) && (timeout-- > 0))
+-		cpu_relax();
+-
+-	for (i = 0; i < host->sector_number; i++) {
+-		for (j = 0; j < host->ecc_bytes_per_sector; j++) {
+-			int pos;
+-
+-			pos = i * host->ecc_bytes_per_sector + j;
+-			chip->oob_poi[eccpos[pos]] =
+-				pmecc_readb_ecc(host->ecc, i, j);
+-		}
+-	}
+-	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+-
+-	return;
+-}
+-
+-static void atmel_init_pmecc(struct mtd_info *mtd)
+-{
+-	uint32_t val = 0;
+-	struct nand_chip *nand_chip = mtd->priv;
+-	struct atmel_nand_host *host = nand_chip->priv;
+-	struct nand_ecclayout *ecc_layout;
+-
+-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
+-	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
+-
+-	switch (host->tt) {
+-	case 2:
+-		val = PMECC_CFG_BCH_ERR2;
+-		break;
+-	case 4:
+-		val = PMECC_CFG_BCH_ERR4;
+-		break;
+-	case 8:
+-		val = PMECC_CFG_BCH_ERR8;
+-		break;
+-	case 12:
+-		val = PMECC_CFG_BCH_ERR12;
+-		break;
+-	case 24:
+-		val = PMECC_CFG_BCH_ERR24;
+-		break;
+-	}
+-
+-	if (host->sector_size == 512)
+-		val |= PMECC_CFG_SECTOR512;
+-	else if (host->sector_size == 1024)
+-		val |= PMECC_CFG_SECTOR1024;
+-
+-	switch (host->sector_number) {
+-	case 1:
+-		val |= PMECC_CFG_PAGE_1SECTOR;
+-		break;
+-	case 2:
+-		val |= PMECC_CFG_PAGE_2SECTORS;
+-		break;
+-	case 4:
+-		val |= PMECC_CFG_PAGE_4SECTORS;
+-		break;
+-	case 8:
+-		val |= PMECC_CFG_PAGE_8SECTORS;
+-		break;
+-	}
+-
+-	val |= PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
+-		| PMECC_CFG_AUTO_DISABLE;
+-	pmecc_writel(host->ecc, CFG, val);
+-
+-	ecc_layout = nand_chip->ecc.layout;
+-	pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
+-	pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
+-	pmecc_writel(host->ecc, EADDR,
+-			ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
+-	pmecc_writel(host->ecc, CLK, PMECC_CLK_133MHZ);
+-	pmecc_writel(host->ecc, IDR, 0xff);
+-
+-	val = pmecc_readl(host->ecc, CTRL);
+-	val |= PMECC_CTRL_ENABLE;
+-	pmecc_writel(host->ecc, CTRL, val);
+-}
+-
+-static int __init atmel_pmecc_init_params(struct platform_device *pdev,
+-					 struct atmel_nand_host *host)
+-{
+-	struct resource *regs;
+-	struct resource *regs_pmerr, *regs_rom;
+-	struct nand_chip *nand_chip;
+-	struct mtd_info *mtd;
+-	int res;
+-
+-	printk(KERN_ERR "atmel_pmecc_init_params\n");
+-
+-	nand_chip = &host->nand_chip;
+-	mtd = &host->mtd;
+-
+-	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+-	if (!regs && hard_ecc) {
+-		dev_warn(host->dev, "Can't get I/O resource regs\nFalling "
+-				"back on software ECC\n");
+-	}
+-
+-	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
+-	if (no_ecc)
+-		nand_chip->ecc.mode = NAND_ECC_NONE;
+-	if (hard_ecc && regs) {
+-		host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
+-		if (host->ecc == NULL) {
+-			printk(KERN_ERR "atmel_nand: ioremap failed\n");
+-			res = -EIO;
+-			goto err_pmecc_ioremap;
+-		}
+-
+-		regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM,
+-						   2);
+-		regs_rom = platform_get_resource(pdev, IORESOURCE_MEM,
+-						 3);
+-		if (regs_pmerr && regs_rom) {
+-			host->pmerrloc_base = ioremap(regs_pmerr->start,
+-			regs_pmerr->end - regs_pmerr->start + 1);
+-			host->rom_base = ioremap(regs_rom->start,
+-				regs_rom->end - regs_rom->start + 1);
+-
+-			if (host->pmerrloc_base && host->rom_base) {
+-				nand_chip->ecc.mode = NAND_ECC_HW;
+-				nand_chip->ecc.read_page =
+-					atmel_nand_pmecc_read_page;
+-				nand_chip->ecc.write_page =
+-					atmel_nand_pmecc_write_page;
+-			} else {
+-				dev_err(host->dev, "Can not get I/O resource"
+-				" for HW PMECC controller!\n");
+-				goto err_pmloc_remap;
+-			}
+-		}
+-
+-		if (nand_chip->ecc.mode != NAND_ECC_HW)
+-			printk(KERN_ERR "atmel_nand: Can not get I/O resource"
+-				" for HW ECC Rolling back to software ECC\n");
+-	}
+-
+-	if (nand_chip->ecc.mode == NAND_ECC_HW) {
+-		/* ECC is calculated for the whole page (1 step) */
+-		nand_chip->ecc.size = mtd->writesize;
+-
+-		/* set ECC page size and oob layout */
+-		switch (mtd->writesize) {
+-		case 2048:
+-			nand_chip->ecc.bytes = 16;
+-			nand_chip->ecc.steps = 1;
+-			nand_chip->ecc.layout = &pmecc_oobinfo_2048;
+-			host->mm = GF_DIMENSION_13;
+-			host->nn = (1 << host->mm) - 1;
+-			/* 2-bits correction */
+-			host->tt = 2;
+-			host->sector_size = 512;
+-			host->sector_number = mtd->writesize /
+-					      host->sector_size;
+-			host->ecc_bytes_per_sector = 4;
+-			host->alpha_to = pmecc_get_alpha_to(host);
+-			host->index_of = pmecc_get_index_of(host);
+-			break;
+-		case 512:
+-		case 1024:
+-		case 4096:
+-			/* TODO */
+-			dev_warn(host->dev, "Only 2048 page size is currently"
+-				"supported, Rolling back to software ECC\n");
+-		default:
+-			/* page size not handled by HW ECC */
+-			/* switching back to soft ECC */
+-			nand_chip->ecc.mode = NAND_ECC_SOFT;
+-			nand_chip->ecc.calculate = NULL;
+-			nand_chip->ecc.correct = NULL;
+-			nand_chip->ecc.hwctl = NULL;
+-			nand_chip->ecc.read_page = NULL;
+-			nand_chip->ecc.postpad = 0;
+-			nand_chip->ecc.prepad = 0;
+-			nand_chip->ecc.bytes = 0;
+-			break;
+-		}
+-	}
+-
+-	/* Initialize PMECC core if applicable */
+-	if ((nand_chip->ecc.mode == NAND_ECC_HW) && cpu_has_pmecc())
+-		atmel_init_pmecc(mtd);
+-
+-	return 0;
+-err_pmloc_remap:
+-	iounmap(host->ecc);
+-	if (host->pmerrloc_base)
+-		iounmap(host->pmerrloc_base);
+-	if (host->rom_base)
+-		iounmap(host->rom_base);
+-err_pmecc_ioremap:
+-	return -EIO;
+-}
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0002-Revert-MTD-atmel_nand-optimize-read-write-buffer-fun.patch b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0002-Revert-MTD-atmel_nand-optimize-read-write-buffer-fun.patch
new file mode 100644
index 0000000..ab52355
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0002-Revert-MTD-atmel_nand-optimize-read-write-buffer-fun.patch
@@ -0,0 +1,126 @@
+From 1ac5f32e63677a56f72e353b8f53447f63763852 Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Tue, 25 Dec 2012 16:06:15 +0800
+Subject: [PATCH 2/9] Revert "MTD: atmel_nand: optimize read/write buffer
+ functions"
+
+This reverts commit 6ddc4f41327a2782c63817dc8b94dd92edad8352.
+
+In mainline this commit is also reverted. see:
+
+500823195d0c9eec2a4637484f30cc93ec633d4a (Revert "mtd: atmel_nand: optimize read/write buffer functions")
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+---
+ drivers/mtd/nand/atmel_nand.c |   71 ++++++++++++++++++++++++-----------------
+ 1 file changed, 41 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index 12de424..9657532 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -159,6 +159,37 @@ static int atmel_nand_device_ready(struct mtd_info *mtd)
+                 !!host->board->rdy_pin_active_low;
+ }
+ 
++/*
++ * Minimal-overhead PIO for data access.
++ */
++static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
++{
++	struct nand_chip	*nand_chip = mtd->priv;
++
++	__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
++}
++
++static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
++{
++	struct nand_chip	*nand_chip = mtd->priv;
++
++	__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
++}
++
++static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
++{
++	struct nand_chip	*nand_chip = mtd->priv;
++
++	__raw_writesb(nand_chip->IO_ADDR_W, buf, len);
++}
++
++static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
++{
++	struct nand_chip	*nand_chip = mtd->priv;
++
++	__raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
++}
++
+ static void dma_complete_func(void *completion)
+ {
+ 	complete(completion);
+@@ -235,53 +266,33 @@ err_buf:
+ static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+ {
+ 	struct nand_chip *chip = mtd->priv;
+-	u32 align;
+-	u8 *pbuf;
++	struct atmel_nand_host *host = chip->priv;
+ 
+ 	if (use_dma && len > mtd->oobsize)
+ 		/* only use DMA for bigger than oob size: better performances */
+ 		if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
+ 			return;
+ 
+-	/* if no DMA operation possible, use PIO */
+-	pbuf = buf;
+-	align = 0x03 & ((unsigned)pbuf);
+-
+-	if (align) {
+-		u32 align_len = 4 - align;
+-
+-		/* non aligned buffer: re-align to next word boundary */
+-		ioread8_rep(chip->IO_ADDR_R, pbuf, align_len);
+-		pbuf += align_len;
+-		len -= align_len;
+-	}
+-	memcpy((void *)pbuf, chip->IO_ADDR_R, len);
++	if (host->board->bus_width_16)
++		atmel_read_buf16(mtd, buf, len);
++	else
++		atmel_read_buf8(mtd, buf, len);
+ }
+ 
+ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+ {
+ 	struct nand_chip *chip = mtd->priv;
+-	u32 align;
+-	const u8 *pbuf;
++	struct atmel_nand_host *host = chip->priv;
+ 
+ 	if (use_dma && len > mtd->oobsize)
+ 		/* only use DMA for bigger than oob size: better performances */
+ 		if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
+ 			return;
+ 
+-	/* if no DMA operation possible, use PIO */
+-	pbuf = buf;
+-	align = 0x03 & ((unsigned)pbuf);
+-
+-	if (align) {
+-		u32 align_len = 4 - align;
+-
+-		/* non aligned buffer: re-align to next word boundary */
+-		iowrite8_rep(chip->IO_ADDR_W, pbuf, align_len);
+-		pbuf += align_len;
+-		len -= align_len;
+-	}
+-	memcpy(chip->IO_ADDR_W, (void *)pbuf, len);
++	if (host->board->bus_width_16)
++		atmel_write_buf16(mtd, buf, len);
++	else
++		atmel_write_buf8(mtd, buf, len);
+ }
+ 
+ /*
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0003-mtd-at91-extract-hw-ecc-initialization-to-one-functi.patch b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0003-mtd-at91-extract-hw-ecc-initialization-to-one-functi.patch
new file mode 100644
index 0000000..91fd6f9
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0003-mtd-at91-extract-hw-ecc-initialization-to-one-functi.patch
@@ -0,0 +1,229 @@
+From 029192ec7ea78adaee41f14dd86dab768d56b172 Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Mon, 25 Jun 2012 18:07:43 +0800
+Subject: [PATCH 3/9] mtd: at91: extract hw ecc initialization to one function
+
+This patch moves hw ecc initialization code to one function.
+
+Signed-off-by: Hong Xu <hong.xu@atmel.com>
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
+Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
+
+port to 2.6.39
+
+Conflicts:
+
+	drivers/mtd/nand/atmel_nand.c
+---
+ arch/arm/mach-at91/include/mach/board.h |    1 +
+ drivers/mtd/nand/atmel_nand.c           |  140 +++++++++++++++----------------
+ 2 files changed, 67 insertions(+), 74 deletions(-)
+
+diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
+index 04dcec1..392a7b3 100644
+--- a/arch/arm/mach-at91/include/mach/board.h
++++ b/arch/arm/mach-at91/include/mach/board.h
+@@ -117,6 +117,7 @@ struct atmel_nand_data {
+ 	u8		cle;		/* address line number connected to CLE */
+ 	u8		bus_width_16;	/* buswidth is 16 bit */
+ 	u8		bus_on_d0;	/* pins of data bus are connected to D0~D15 */
++	u8		ecc_mode;	/* can be NAND_ECC_HW/SOFT/NONE */
+ 	struct mtd_partition* (*partition_info)(int, int*);
+ };
+ extern void __init at91_add_device_nand(struct atmel_nand_data *data);
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index 9657532..d34d7f9 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -36,18 +36,6 @@
+ #include <mach/board.h>
+ #include <mach/cpu.h>
+ 
+-#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
+-#define hard_ecc	1
+-#else
+-#define hard_ecc	0
+-#endif
+-
+-#ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
+-#define no_ecc		1
+-#else
+-#define no_ecc		0
+-#endif
+-
+ static int use_dma = 1;
+ module_param(use_dma, int, 0);
+ 
+@@ -485,6 +473,65 @@ static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
+ static const char *part_probes[] = { "cmdlinepart", NULL };
+ #endif
+ 
++static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
++					 struct atmel_nand_host *host)
++{
++	struct mtd_info *mtd = &host->mtd;
++	struct nand_chip *nand_chip = &host->nand_chip;
++	struct resource		*regs;
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	if (!regs) {
++		dev_err(host->dev,
++			"Can't get I/O resource regs, use software ECC\n");
++		nand_chip->ecc.mode = NAND_ECC_SOFT;
++		return 0;
++	}
++
++	host->ecc = ioremap(regs->start, resource_size(regs));
++	if (host->ecc == NULL) {
++		dev_err(host->dev, "ioremap failed\n");
++		return -EIO;
++	}
++
++	/* ECC is calculated for the whole page (1 step) */
++	nand_chip->ecc.size = mtd->writesize;
++
++	/* set ECC page size and oob layout */
++	switch (mtd->writesize) {
++	case 512:
++		nand_chip->ecc.layout = &atmel_oobinfo_small;
++		ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
++		break;
++	case 1024:
++		nand_chip->ecc.layout = &atmel_oobinfo_large;
++		ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
++		break;
++	case 2048:
++		nand_chip->ecc.layout = &atmel_oobinfo_large;
++		ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
++		break;
++	case 4096:
++		nand_chip->ecc.layout = &atmel_oobinfo_large;
++		ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
++		break;
++	default:
++		/* page size not handled by HW ECC */
++		/* switching back to soft ECC */
++		nand_chip->ecc.mode = NAND_ECC_SOFT;
++		return 0;
++	}
++
++	/* set up for HW ECC */
++	nand_chip->ecc.calculate = atmel_nand_calculate;
++	nand_chip->ecc.correct = atmel_nand_correct;
++	nand_chip->ecc.hwctl = atmel_nand_hwctl;
++	nand_chip->ecc.read_page = atmel_nand_read_page;
++	nand_chip->ecc.bytes = 4;
++
++	return 0;
++}
++
+ /*
+  * Probe for the NAND device.
+  */
+@@ -493,7 +540,6 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 	struct atmel_nand_host *host;
+ 	struct mtd_info *mtd;
+ 	struct nand_chip *nand_chip;
+-	struct resource *regs;
+ 	struct resource *mem;
+ 	int res;
+ 
+@@ -541,30 +587,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 	if (host->board->rdy_pin)
+ 		nand_chip->dev_ready = atmel_nand_device_ready;
+ 
+-	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+-	if (!regs && hard_ecc) {
+-		printk(KERN_ERR "atmel_nand: can't get I/O resource "
+-				"regs\nFalling back on software ECC\n");
+-	}
+-
+-	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
+-	if (no_ecc)
+-		nand_chip->ecc.mode = NAND_ECC_NONE;
+-	if (hard_ecc && regs) {
+-		host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
+-		if (host->ecc == NULL) {
+-			printk(KERN_ERR "atmel_nand: ioremap failed\n");
+-			res = -EIO;
+-			goto err_ecc_ioremap;
+-		}
+-		nand_chip->ecc.mode = NAND_ECC_HW;
+-		nand_chip->ecc.calculate = atmel_nand_calculate;
+-		nand_chip->ecc.correct = atmel_nand_correct;
+-		nand_chip->ecc.hwctl = atmel_nand_hwctl;
+-		nand_chip->ecc.read_page = atmel_nand_read_page;
+-		nand_chip->ecc.bytes = 4;
+-	}
+-
++	nand_chip->ecc.mode = host->board->ecc_mode;
+ 	nand_chip->chip_delay = 20;		/* 20us command delay time */
+ 
+ 	if (host->board->bus_width_16)	/* 16-bit bus width */
+@@ -616,40 +639,9 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	if (nand_chip->ecc.mode == NAND_ECC_HW) {
+-		/* ECC is calculated for the whole page (1 step) */
+-		nand_chip->ecc.size = mtd->writesize;
+-
+-		/* set ECC page size and oob layout */
+-		switch (mtd->writesize) {
+-		case 512:
+-			nand_chip->ecc.layout = &atmel_oobinfo_small;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
+-			break;
+-		case 1024:
+-			nand_chip->ecc.layout = &atmel_oobinfo_large;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
+-			break;
+-		case 2048:
+-			nand_chip->ecc.layout = &atmel_oobinfo_large;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
+-			break;
+-		case 4096:
+-			nand_chip->ecc.layout = &atmel_oobinfo_large;
+-			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
+-			break;
+-		default:
+-			/* page size not handled by HW ECC */
+-			/* switching back to soft ECC */
+-			nand_chip->ecc.mode = NAND_ECC_SOFT;
+-			nand_chip->ecc.calculate = NULL;
+-			nand_chip->ecc.correct = NULL;
+-			nand_chip->ecc.hwctl = NULL;
+-			nand_chip->ecc.read_page = NULL;
+-			nand_chip->ecc.postpad = 0;
+-			nand_chip->ecc.prepad = 0;
+-			nand_chip->ecc.bytes = 0;
+-			break;
+-		}
++		res = atmel_hw_nand_init_params(pdev, host);
++		if (res != 0)
++			goto err_hw_ecc;
+ 	}
+ 
+ 	/* second phase scan */
+@@ -687,15 +679,15 @@ err_no_partitions:
+ #endif
+ 	nand_release(mtd);
+ err_scan_tail:
++	if (host->ecc)
++		iounmap(host->ecc);
++err_hw_ecc:
+ err_scan_ident:
+ err_no_card:
+ 	atmel_nand_disable(host);
+ 	platform_set_drvdata(pdev, NULL);
+ 	if (host->dma_chan)
+ 		dma_release_channel(host->dma_chan);
+-	if (host->ecc)
+-		iounmap(host->ecc);
+-err_ecc_ioremap:
+ 	iounmap(host->io_base);
+ err_nand_ioremap:
+ 	kfree(host);
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0004-atmel_nand-add-PMECC-parameters-in-nand-structure.patch b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0004-atmel_nand-add-PMECC-parameters-in-nand-structure.patch
new file mode 100644
index 0000000..03bd6e1
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0004-atmel_nand-add-PMECC-parameters-in-nand-structure.patch
@@ -0,0 +1,30 @@
+From 0a42dbd4e968606801aa1292cb43e6835382a19f Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Tue, 25 Dec 2012 17:32:58 +0800
+Subject: [PATCH 4/9] atmel_nand: add PMECC parameters in nand structure.
+
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+---
+ drivers/mtd/nand/atmel_nand.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index d34d7f9..fbe0b11 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -87,6 +87,11 @@ struct atmel_nand_host {
+ 
+ 	struct completion	comp;
+ 	struct dma_chan		*dma_chan;
++
++	bool			has_pmecc;
++	u8			pmecc_corr_cap;
++	u16			pmecc_sector_size;
++	u32			pmecc_lookup_table_offset;
+ };
+ 
+ static int cpu_has_dma(void)
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0005-mtd-at91-atmel_nand-add-Programmable-Multibit-ECC-co.patch b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0005-mtd-at91-atmel_nand-add-Programmable-Multibit-ECC-co.patch
new file mode 100644
index 0000000..0ed9119
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0005-mtd-at91-atmel_nand-add-Programmable-Multibit-ECC-co.patch
@@ -0,0 +1,980 @@
+From 548e5f480ba7799d694cc450473405bca6c2814c Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Fri, 29 Jun 2012 17:47:55 +0800
+Subject: [PATCH 5/9] mtd: at91: atmel_nand: add Programmable Multibit ECC
+ controller support
+
+The Programmable Multibit ECC (PMECC) controller is a programmable binary
+BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller
+can be used to support both SLC and MLC NAND Flash devices. It supports to
+generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data.
+
+To use PMECC in this driver, the user needs to set the address and size of
+PMECC, PMECC error location controllers and ROM. And also needs to pass the
+correction capability, the sector size and ROM lookup table offsets via dt.
+
+This driver has been tested on AT91SAM9X5-EK and AT91SAM9N12-EK with JFFS2,
+YAFFS2, UBIFS and mtd-utils.
+
+Signed-off-by: Hong Xu <hong.xu@atmel.com>
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+Tested-by: Richard Genoud <richard.genoud@gmail.com>
+Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
+Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
+---
+ drivers/mtd/nand/atmel_nand.c     |  757 ++++++++++++++++++++++++++++++++++++-
+ drivers/mtd/nand/atmel_nand_ecc.h |  114 +++++-
+ 2 files changed, 864 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index fbe0b11..a6fa5c1 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -1,20 +1,22 @@
+ /*
+- *  Copyright (C) 2003 Rick Bronson
++ *  Copyright © 2003 Rick Bronson
+  *
+  *  Derived from drivers/mtd/nand/autcpu12.c
+- *	 Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
++ *	 Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
+  *
+  *  Derived from drivers/mtd/spia.c
+- *	 Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
++ *	 Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
+  *
+  *
+  *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
+- *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
++ *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
+  *
+  *     Derived from Das U-Boot source code
+  *     		(u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
+- *     (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
++ *     © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+  *
++ *  Add Programmable Multibit ECC support for various AT91 SoC
++ *     © Copyright 2012 ATMEL, Hong Xu
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+@@ -92,8 +94,31 @@ struct atmel_nand_host {
+ 	u8			pmecc_corr_cap;
+ 	u16			pmecc_sector_size;
+ 	u32			pmecc_lookup_table_offset;
++
++	int			pmecc_bytes_per_sector;
++	int			pmecc_sector_number;
++	int			pmecc_degree;	/* Degree of remainders */
++	int			pmecc_cw_len;	/* Length of codeword */
++
++	void __iomem		*pmerrloc_base;
++	void __iomem		*pmecc_rom_base;
++
++	/* lookup table for alpha_to and index_of */
++	void __iomem		*pmecc_alpha_to;
++	void __iomem		*pmecc_index_of;
++
++	/* data for pmecc computation */
++	int16_t			*pmecc_partial_syn;
++	int16_t			*pmecc_si;
++	int16_t			*pmecc_smu;	/* Sigma table */
++	int16_t			*pmecc_lmu;	/* polynomal order */
++	int			*pmecc_mu;
++	int			*pmecc_dmu;
++	int			*pmecc_delta;
+ };
+ 
++static struct nand_ecclayout atmel_pmecc_oobinfo;
++
+ static int cpu_has_dma(void)
+ {
+ 	return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
+@@ -289,6 +314,703 @@ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+ }
+ 
+ /*
++ * Return number of ecc bytes per sector according to sector size and
++ * correction capability
++ *
++ * Following table shows what at91 PMECC supported:
++ * Correction Capability	Sector_512_bytes	Sector_1024_bytes
++ * =====================	================	=================
++ *                2-bits                 4-bytes                  4-bytes
++ *                4-bits                 7-bytes                  7-bytes
++ *                8-bits                13-bytes                 14-bytes
++ *               12-bits                20-bytes                 21-bytes
++ *               24-bits                39-bytes                 42-bytes
++ */
++static int __devinit pmecc_get_ecc_bytes(int cap, int sector_size)
++{
++	int m = 12 + sector_size / 512;
++	return (m * cap + 7) / 8;
++}
++
++static void __devinit pmecc_config_ecc_layout(struct nand_ecclayout *layout,
++	int oobsize, int ecc_len)
++{
++	int i;
++
++	layout->eccbytes = ecc_len;
++
++	/* ECC will occupy the last ecc_len bytes continuously */
++	for (i = 0; i < ecc_len; i++)
++		layout->eccpos[i] = oobsize - ecc_len + i;
++
++	layout->oobfree[0].offset = 2;
++	layout->oobfree[0].length =
++		oobsize - ecc_len - layout->oobfree[0].offset;
++}
++
++static void __devinit __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
++{
++	int table_size;
++
++	table_size = host->pmecc_sector_size == 512 ?
++		PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
++
++	return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
++			table_size * sizeof(int16_t);
++}
++
++static void pmecc_data_free(struct atmel_nand_host *host)
++{
++	kfree(host->pmecc_partial_syn);
++	kfree(host->pmecc_si);
++	kfree(host->pmecc_lmu);
++	kfree(host->pmecc_smu);
++	kfree(host->pmecc_mu);
++	kfree(host->pmecc_dmu);
++	kfree(host->pmecc_delta);
++}
++
++static int __devinit pmecc_data_alloc(struct atmel_nand_host *host)
++{
++	const int cap = host->pmecc_corr_cap;
++
++	host->pmecc_partial_syn = kzalloc((2 * cap + 1) * sizeof(int16_t),
++					GFP_KERNEL);
++	host->pmecc_si = kzalloc((2 * cap + 1) * sizeof(int16_t), GFP_KERNEL);
++	host->pmecc_lmu = kzalloc((cap + 1) * sizeof(int16_t), GFP_KERNEL);
++	host->pmecc_smu = kzalloc((cap + 2) * (2 * cap + 1) * sizeof(int16_t),
++					GFP_KERNEL);
++	host->pmecc_mu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
++	host->pmecc_dmu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
++	host->pmecc_delta = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
++
++	if (host->pmecc_partial_syn &&
++			host->pmecc_si &&
++			host->pmecc_lmu &&
++			host->pmecc_smu &&
++			host->pmecc_mu &&
++			host->pmecc_dmu &&
++			host->pmecc_delta)
++		return 0;
++
++	/* error happened */
++	pmecc_data_free(host);
++	return -ENOMEM;
++}
++
++static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
++{
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++	int i;
++	uint32_t value;
++
++	/* Fill odd syndromes */
++	for (i = 0; i < host->pmecc_corr_cap; i++) {
++		value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
++		if (i & 1)
++			value >>= 16;
++		value &= 0xffff;
++		host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
++	}
++}
++
++static void pmecc_substitute(struct mtd_info *mtd)
++{
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++	int16_t __iomem *alpha_to = host->pmecc_alpha_to;
++	int16_t __iomem *index_of = host->pmecc_index_of;
++	int16_t *partial_syn = host->pmecc_partial_syn;
++	const int cap = host->pmecc_corr_cap;
++	int16_t *si;
++	int i, j;
++
++	/* si[] is a table that holds the current syndrome value,
++	 * an element of that table belongs to the field
++	 */
++	si = host->pmecc_si;
++
++	memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
++
++	/* Computation 2t syndromes based on S(x) */
++	/* Odd syndromes */
++	for (i = 1; i < 2 * cap; i += 2) {
++		for (j = 0; j < host->pmecc_degree; j++) {
++			if (partial_syn[i] & ((unsigned short)0x1 << j))
++				si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
++		}
++	}
++	/* Even syndrome = (Odd syndrome) ** 2 */
++	for (i = 2, j = 1; j <= cap; i = ++j << 1) {
++		if (si[j] == 0) {
++			si[i] = 0;
++		} else {
++			int16_t tmp;
++
++			tmp = readw_relaxed(index_of + si[j]);
++			tmp = (tmp * 2) % host->pmecc_cw_len;
++			si[i] = readw_relaxed(alpha_to + tmp);
++		}
++	}
++
++	return;
++}
++
++static void pmecc_get_sigma(struct mtd_info *mtd)
++{
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++
++	int16_t *lmu = host->pmecc_lmu;
++	int16_t *si = host->pmecc_si;
++	int *mu = host->pmecc_mu;
++	int *dmu = host->pmecc_dmu;	/* Discrepancy */
++	int *delta = host->pmecc_delta; /* Delta order */
++	int cw_len = host->pmecc_cw_len;
++	const int16_t cap = host->pmecc_corr_cap;
++	const int num = 2 * cap + 1;
++	int16_t __iomem	*index_of = host->pmecc_index_of;
++	int16_t __iomem	*alpha_to = host->pmecc_alpha_to;
++	int i, j, k;
++	uint32_t dmu_0_count, tmp;
++	int16_t *smu = host->pmecc_smu;
++
++	/* index of largest delta */
++	int ro;
++	int largest;
++	int diff;
++
++	dmu_0_count = 0;
++
++	/* First Row */
++
++	/* Mu */
++	mu[0] = -1;
++
++	memset(smu, 0, sizeof(int16_t) * num);
++	smu[0] = 1;
++
++	/* discrepancy set to 1 */
++	dmu[0] = 1;
++	/* polynom order set to 0 */
++	lmu[0] = 0;
++	delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
++
++	/* Second Row */
++
++	/* Mu */
++	mu[1] = 0;
++	/* Sigma(x) set to 1 */
++	memset(&smu[num], 0, sizeof(int16_t) * num);
++	smu[num] = 1;
++
++	/* discrepancy set to S1 */
++	dmu[1] = si[1];
++
++	/* polynom order set to 0 */
++	lmu[1] = 0;
++
++	delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
++
++	/* Init the Sigma(x) last row */
++	memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
++
++	for (i = 1; i <= cap; i++) {
++		mu[i + 1] = i << 1;
++		/* Begin Computing Sigma (Mu+1) and L(mu) */
++		/* check if discrepancy is set to 0 */
++		if (dmu[i] == 0) {
++			dmu_0_count++;
++
++			tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
++			if ((cap - (lmu[i] >> 1) - 1) & 0x1)
++				tmp += 2;
++			else
++				tmp += 1;
++
++			if (dmu_0_count == tmp) {
++				for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
++					smu[(cap + 1) * num + j] =
++							smu[i * num + j];
++
++				lmu[cap + 1] = lmu[i];
++				return;
++			}
++
++			/* copy polynom */
++			for (j = 0; j <= lmu[i] >> 1; j++)
++				smu[(i + 1) * num + j] = smu[i * num + j];
++
++			/* copy previous polynom order to the next */
++			lmu[i + 1] = lmu[i];
++		} else {
++			ro = 0;
++			largest = -1;
++			/* find largest delta with dmu != 0 */
++			for (j = 0; j < i; j++) {
++				if ((dmu[j]) && (delta[j] > largest)) {
++					largest = delta[j];
++					ro = j;
++				}
++			}
++
++			/* compute difference */
++			diff = (mu[i] - mu[ro]);
++
++			/* Compute degree of the new smu polynomial */
++			if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
++				lmu[i + 1] = lmu[i];
++			else
++				lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
++
++			/* Init smu[i+1] with 0 */
++			for (k = 0; k < num; k++)
++				smu[(i + 1) * num + k] = 0;
++
++			/* Compute smu[i+1] */
++			for (k = 0; k <= lmu[ro] >> 1; k++) {
++				int16_t a, b, c;
++
++				if (!(smu[ro * num + k] && dmu[i]))
++					continue;
++				a = readw_relaxed(index_of + dmu[i]);
++				b = readw_relaxed(index_of + dmu[ro]);
++				c = readw_relaxed(index_of + smu[ro * num + k]);
++				tmp = a + (cw_len - b) + c;
++				a = readw_relaxed(alpha_to + tmp % cw_len);
++				smu[(i + 1) * num + (k + diff)] = a;
++			}
++
++			for (k = 0; k <= lmu[i] >> 1; k++)
++				smu[(i + 1) * num + k] ^= smu[i * num + k];
++		}
++
++		/* End Computing Sigma (Mu+1) and L(mu) */
++		/* In either case compute delta */
++		delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
++
++		/* Do not compute discrepancy for the last iteration */
++		if (i >= cap)
++			continue;
++
++		for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
++			tmp = 2 * (i - 1);
++			if (k == 0) {
++				dmu[i + 1] = si[tmp + 3];
++			} else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
++				int16_t a, b, c;
++				a = readw_relaxed(index_of +
++						smu[(i + 1) * num + k]);
++				b = si[2 * (i - 1) + 3 - k];
++				c = readw_relaxed(index_of + b);
++				tmp = a + c;
++				tmp %= cw_len;
++				dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
++					dmu[i + 1];
++			}
++		}
++	}
++
++	return;
++}
++
++static int pmecc_err_location(struct mtd_info *mtd)
++{
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++	unsigned long end_time;
++	const int cap = host->pmecc_corr_cap;
++	const int num = 2 * cap + 1;
++	int sector_size = host->pmecc_sector_size;
++	int err_nbr = 0;	/* number of error */
++	int roots_nbr;		/* number of roots */
++	int i;
++	uint32_t val;
++	int16_t *smu = host->pmecc_smu;
++
++	pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
++
++	for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
++		pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
++				      smu[(cap + 1) * num + i]);
++		err_nbr++;
++	}
++
++	val = (err_nbr - 1) << 16;
++	if (sector_size == 1024)
++		val |= 1;
++
++	pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
++	pmerrloc_writel(host->pmerrloc_base, ELEN,
++			sector_size * 8 + host->pmecc_degree * cap);
++
++	end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
++	while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
++		 & PMERRLOC_CALC_DONE)) {
++		if (unlikely(time_after(jiffies, end_time))) {
++			dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
++			return -1;
++		}
++		cpu_relax();
++	}
++
++	roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
++		& PMERRLOC_ERR_NUM_MASK) >> 8;
++	/* Number of roots == degree of smu hence <= cap */
++	if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
++		return err_nbr - 1;
++
++	/* Number of roots does not match the degree of smu
++	 * unable to correct error */
++	return -1;
++}
++
++static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
++		int sector_num, int extra_bytes, int err_nbr)
++{
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++	int i = 0;
++	int byte_pos, bit_pos, sector_size, pos;
++	uint32_t tmp;
++	uint8_t err_byte;
++
++	sector_size = host->pmecc_sector_size;
++
++	while (err_nbr) {
++		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
++		byte_pos = tmp / 8;
++		bit_pos  = tmp % 8;
++
++		if (byte_pos >= (sector_size + extra_bytes))
++			BUG();	/* should never happen */
++
++		if (byte_pos < sector_size) {
++			err_byte = *(buf + byte_pos);
++			*(buf + byte_pos) ^= (1 << bit_pos);
++
++			pos = sector_num * host->pmecc_sector_size + byte_pos;
++			dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
++				pos, bit_pos, err_byte, *(buf + byte_pos));
++		} else {
++			/* Bit flip in OOB area */
++			tmp = sector_num * host->pmecc_bytes_per_sector
++					+ (byte_pos - sector_size);
++			err_byte = ecc[tmp];
++			ecc[tmp] ^= (1 << bit_pos);
++
++			pos = tmp + nand_chip->ecc.layout->eccpos[0];
++			dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
++				pos, bit_pos, err_byte, ecc[tmp]);
++		}
++
++		i++;
++		err_nbr--;
++	}
++
++	return;
++}
++
++static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
++	u8 *ecc)
++{
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++	int i, err_nbr, eccbytes;
++	uint8_t *buf_pos;
++
++	eccbytes = nand_chip->ecc.bytes;
++	for (i = 0; i < eccbytes; i++)
++		if (ecc[i] != 0xff)
++			goto normal_check;
++	/* Erased page, return OK */
++	return 0;
++
++normal_check:
++	for (i = 0; i < host->pmecc_sector_number; i++) {
++		err_nbr = 0;
++		if (pmecc_stat & 0x1) {
++			buf_pos = buf + i * host->pmecc_sector_size;
++
++			pmecc_gen_syndrome(mtd, i);
++			pmecc_substitute(mtd);
++			pmecc_get_sigma(mtd);
++
++			err_nbr = pmecc_err_location(mtd);
++			if (err_nbr == -1) {
++				dev_err(host->dev, "PMECC: Too many errors\n");
++				mtd->ecc_stats.failed++;
++				return -EIO;
++			} else {
++				pmecc_correct_data(mtd, buf_pos, ecc, i,
++					host->pmecc_bytes_per_sector, err_nbr);
++				mtd->ecc_stats.corrected += err_nbr;
++			}
++		}
++		pmecc_stat >>= 1;
++	}
++
++	return 0;
++}
++
++static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
++	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
++{
++	struct atmel_nand_host *host = chip->priv;
++	int eccsize = chip->ecc.size;
++	uint8_t *oob = chip->oob_poi;
++	uint32_t *eccpos = chip->ecc.layout->eccpos;
++	uint32_t stat;
++	unsigned long end_time;
++
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
++	pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG)
++		& ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
++
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
++
++	chip->read_buf(mtd, buf, eccsize);
++	chip->read_buf(mtd, oob, mtd->oobsize);
++
++	end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
++	while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
++		if (unlikely(time_after(jiffies, end_time))) {
++			dev_err(host->dev, "PMECC: Timeout to get error status.\n");
++			return -EIO;
++		}
++		cpu_relax();
++	}
++
++	stat = pmecc_readl_relaxed(host->ecc, ISR);
++	if (stat != 0)
++		if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
++			return -EIO;
++
++	return 0;
++}
++
++static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
++		struct nand_chip *chip, const uint8_t *buf, int oob_required)
++{
++	struct atmel_nand_host *host = chip->priv;
++	uint32_t *eccpos = chip->ecc.layout->eccpos;
++	int i, j;
++	unsigned long end_time;
++
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
++
++	pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) |
++		PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
++
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
++
++	chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
++
++	end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
++	while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
++		if (unlikely(time_after(jiffies, end_time))) {
++			dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
++			return -EIO;
++		}
++		cpu_relax();
++	}
++
++	for (i = 0; i < host->pmecc_sector_number; i++) {
++		for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
++			int pos;
++
++			pos = i * host->pmecc_bytes_per_sector + j;
++			chip->oob_poi[eccpos[pos]] =
++				pmecc_readb_ecc_relaxed(host->ecc, i, j);
++		}
++	}
++	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
++
++	return 0;
++}
++
++static void atmel_pmecc_core_init(struct mtd_info *mtd)
++{
++	struct nand_chip *nand_chip = mtd->priv;
++	struct atmel_nand_host *host = nand_chip->priv;
++	uint32_t val = 0;
++	struct nand_ecclayout *ecc_layout;
++
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
++
++	switch (host->pmecc_corr_cap) {
++	case 2:
++		val = PMECC_CFG_BCH_ERR2;
++		break;
++	case 4:
++		val = PMECC_CFG_BCH_ERR4;
++		break;
++	case 8:
++		val = PMECC_CFG_BCH_ERR8;
++		break;
++	case 12:
++		val = PMECC_CFG_BCH_ERR12;
++		break;
++	case 24:
++		val = PMECC_CFG_BCH_ERR24;
++		break;
++	}
++
++	if (host->pmecc_sector_size == 512)
++		val |= PMECC_CFG_SECTOR512;
++	else if (host->pmecc_sector_size == 1024)
++		val |= PMECC_CFG_SECTOR1024;
++
++	switch (host->pmecc_sector_number) {
++	case 1:
++		val |= PMECC_CFG_PAGE_1SECTOR;
++		break;
++	case 2:
++		val |= PMECC_CFG_PAGE_2SECTORS;
++		break;
++	case 4:
++		val |= PMECC_CFG_PAGE_4SECTORS;
++		break;
++	case 8:
++		val |= PMECC_CFG_PAGE_8SECTORS;
++		break;
++	}
++
++	val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
++		| PMECC_CFG_AUTO_DISABLE);
++	pmecc_writel(host->ecc, CFG, val);
++
++	ecc_layout = nand_chip->ecc.layout;
++	pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
++	pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
++	pmecc_writel(host->ecc, EADDR,
++			ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
++	/* See datasheet about PMECC Clock Control Register */
++	pmecc_writel(host->ecc, CLK, 2);
++	pmecc_writel(host->ecc, IDR, 0xff);
++	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
++}
++
++static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
++					 struct atmel_nand_host *host)
++{
++	struct mtd_info *mtd = &host->mtd;
++	struct nand_chip *nand_chip = &host->nand_chip;
++	struct resource *regs, *regs_pmerr, *regs_rom;
++	int cap, sector_size, err_no;
++
++	cap = host->pmecc_corr_cap;
++	sector_size = host->pmecc_sector_size;
++	dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
++		 cap, sector_size);
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	if (!regs) {
++		dev_warn(host->dev,
++			"Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
++		nand_chip->ecc.mode = NAND_ECC_SOFT;
++		return 0;
++	}
++
++	host->ecc = ioremap(regs->start, resource_size(regs));
++	if (host->ecc == NULL) {
++		dev_err(host->dev, "ioremap failed\n");
++		err_no = -EIO;
++		goto err_pmecc_ioremap;
++	}
++
++	regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
++	regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
++	if (regs_pmerr && regs_rom) {
++		host->pmerrloc_base = ioremap(regs_pmerr->start,
++			resource_size(regs_pmerr));
++		host->pmecc_rom_base = ioremap(regs_rom->start,
++			resource_size(regs_rom));
++	}
++
++	if (!host->pmerrloc_base || !host->pmecc_rom_base) {
++		dev_err(host->dev,
++			"Can not get I/O resource for PMECC ERRLOC controller or ROM!\n");
++		err_no = -EIO;
++		goto err_pmloc_ioremap;
++	}
++
++	/* ECC is calculated for the whole page (1 step) */
++	nand_chip->ecc.size = mtd->writesize;
++
++	/* set ECC page size and oob layout */
++	switch (mtd->writesize) {
++	case 2048:
++		host->pmecc_degree = PMECC_GF_DIMENSION_13;
++		host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
++		host->pmecc_sector_number = mtd->writesize / sector_size;
++		host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
++			cap, sector_size);
++		host->pmecc_alpha_to = pmecc_get_alpha_to(host);
++		host->pmecc_index_of = host->pmecc_rom_base +
++			host->pmecc_lookup_table_offset;
++
++		nand_chip->ecc.steps = 1;
++		nand_chip->ecc.strength = cap;
++		nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
++				       host->pmecc_sector_number;
++		if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
++			dev_err(host->dev, "No room for ECC bytes\n");
++			err_no = -EINVAL;
++			goto err_no_ecc_room;
++		}
++		pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
++					mtd->oobsize,
++					nand_chip->ecc.bytes);
++		nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
++		break;
++	case 512:
++	case 1024:
++	case 4096:
++		/* TODO */
++		dev_warn(host->dev,
++			"Unsupported page size for PMECC, use Software ECC\n");
++	default:
++		/* page size not handled by HW ECC */
++		/* switching back to soft ECC */
++		nand_chip->ecc.mode = NAND_ECC_SOFT;
++		return 0;
++	}
++
++	/* Allocate data for PMECC computation */
++	err_no = pmecc_data_alloc(host);
++	if (err_no) {
++		dev_err(host->dev,
++				"Cannot allocate memory for PMECC computation!\n");
++		goto err_pmecc_data_alloc;
++	}
++
++	nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
++	nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
++
++	atmel_pmecc_core_init(mtd);
++
++	return 0;
++
++err_pmecc_data_alloc:
++err_no_ecc_room:
++err_pmloc_ioremap:
++	iounmap(host->ecc);
++	if (host->pmerrloc_base)
++		iounmap(host->pmerrloc_base);
++	if (host->pmecc_rom_base)
++		iounmap(host->pmecc_rom_base);
++err_pmecc_ioremap:
++	return err_no;
++}
++
++/*
+  * Calculate HW ECC
+  *
+  * function called after a write
+@@ -644,7 +1366,11 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	if (nand_chip->ecc.mode == NAND_ECC_HW) {
+-		res = atmel_hw_nand_init_params(pdev, host);
++		if (host->has_pmecc)
++			res = atmel_pmecc_nand_init_params(pdev, host);
++		else
++			res = atmel_hw_nand_init_params(pdev, host);
++
+ 		if (res != 0)
+ 			goto err_hw_ecc;
+ 	}
+@@ -684,8 +1410,16 @@ err_no_partitions:
+ #endif
+ 	nand_release(mtd);
+ err_scan_tail:
++	if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
++		pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
++		pmecc_data_free(host);
++	}
+ 	if (host->ecc)
+ 		iounmap(host->ecc);
++	if (host->pmerrloc_base)
++		iounmap(host->pmerrloc_base);
++	if (host->pmecc_rom_base)
++		iounmap(host->pmecc_rom_base);
+ err_hw_ecc:
+ err_scan_ident:
+ err_no_card:
+@@ -711,8 +1445,19 @@ static int __exit atmel_nand_remove(struct platform_device *pdev)
+ 
+ 	atmel_nand_disable(host);
+ 
++	if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
++		pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
++		pmerrloc_writel(host->pmerrloc_base, ELDIS,
++				PMERRLOC_DISABLE);
++		pmecc_data_free(host);
++	}
++
+ 	if (host->ecc)
+ 		iounmap(host->ecc);
++	if (host->pmecc_rom_base)
++		iounmap(host->pmecc_rom_base);
++	if (host->pmerrloc_base)
++		iounmap(host->pmerrloc_base);
+ 
+ 	if (host->dma_chan)
+ 		dma_release_channel(host->dma_chan);
+diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
+index 578c776..8a1e9a6 100644
+--- a/drivers/mtd/nand/atmel_nand_ecc.h
++++ b/drivers/mtd/nand/atmel_nand_ecc.h
+@@ -3,7 +3,7 @@
+  * Based on AT91SAM9260 datasheet revision B.
+  *
+  * Copyright (C) 2007 Andrew Victor
+- * Copyright (C) 2007 Atmel Corporation.
++ * Copyright (C) 2007 - 2012 Atmel Corporation.
+  *
+  * This program is free software; you can redistribute it and/or modify it
+  * under the terms of the GNU General Public License as published by the
+@@ -36,4 +36,116 @@
+ #define ATMEL_ECC_NPR		0x10			/* NParity register */
+ #define		ATMEL_ECC_NPARITY	(0xffff << 0)		/* NParity */
+ 
++/* PMECC Register Definitions */
++#define ATMEL_PMECC_CFG			0x000	/* Configuration Register */
++#define		PMECC_CFG_BCH_ERR2		(0 << 0)
++#define		PMECC_CFG_BCH_ERR4		(1 << 0)
++#define		PMECC_CFG_BCH_ERR8		(2 << 0)
++#define		PMECC_CFG_BCH_ERR12		(3 << 0)
++#define		PMECC_CFG_BCH_ERR24		(4 << 0)
++
++#define		PMECC_CFG_SECTOR512		(0 << 4)
++#define		PMECC_CFG_SECTOR1024		(1 << 4)
++
++#define		PMECC_CFG_PAGE_1SECTOR		(0 << 8)
++#define		PMECC_CFG_PAGE_2SECTORS		(1 << 8)
++#define		PMECC_CFG_PAGE_4SECTORS		(2 << 8)
++#define		PMECC_CFG_PAGE_8SECTORS		(3 << 8)
++
++#define		PMECC_CFG_READ_OP		(0 << 12)
++#define		PMECC_CFG_WRITE_OP		(1 << 12)
++
++#define		PMECC_CFG_SPARE_ENABLE		(1 << 16)
++#define		PMECC_CFG_SPARE_DISABLE		(0 << 16)
++
++#define		PMECC_CFG_AUTO_ENABLE		(1 << 20)
++#define		PMECC_CFG_AUTO_DISABLE		(0 << 20)
++
++#define ATMEL_PMECC_SAREA		0x004	/* Spare area size */
++#define ATMEL_PMECC_SADDR		0x008	/* PMECC starting address */
++#define ATMEL_PMECC_EADDR		0x00c	/* PMECC ending address */
++#define ATMEL_PMECC_CLK			0x010	/* PMECC clock control */
++#define		PMECC_CLK_133MHZ		(2 << 0)
++
++#define ATMEL_PMECC_CTRL		0x014	/* PMECC control register */
++#define		PMECC_CTRL_RST			(1 << 0)
++#define		PMECC_CTRL_DATA			(1 << 1)
++#define		PMECC_CTRL_USER			(1 << 2)
++#define		PMECC_CTRL_ENABLE		(1 << 4)
++#define		PMECC_CTRL_DISABLE		(1 << 5)
++
++#define ATMEL_PMECC_SR			0x018	/* PMECC status register */
++#define		PMECC_SR_BUSY			(1 << 0)
++#define		PMECC_SR_ENABLE			(1 << 4)
++
++#define ATMEL_PMECC_IER			0x01c	/* PMECC interrupt enable */
++#define		PMECC_IER_ENABLE		(1 << 0)
++#define ATMEL_PMECC_IDR			0x020	/* PMECC interrupt disable */
++#define		PMECC_IER_DISABLE		(1 << 0)
++#define ATMEL_PMECC_IMR			0x024	/* PMECC interrupt mask */
++#define		PMECC_IER_MASK			(1 << 0)
++#define ATMEL_PMECC_ISR			0x028	/* PMECC interrupt status */
++#define ATMEL_PMECC_ECCx		0x040	/* PMECC ECC x */
++#define ATMEL_PMECC_REMx		0x240	/* PMECC REM x */
++
++/* PMERRLOC Register Definitions */
++#define ATMEL_PMERRLOC_ELCFG		0x000	/* Error location config */
++#define		PMERRLOC_ELCFG_SECTOR_512	(0 << 0)
++#define		PMERRLOC_ELCFG_SECTOR_1024	(1 << 0)
++#define		PMERRLOC_ELCFG_NUM_ERRORS(n)	((n) << 16)
++
++#define ATMEL_PMERRLOC_ELPRIM		0x004	/* Error location primitive */
++#define ATMEL_PMERRLOC_ELEN		0x008	/* Error location enable */
++#define ATMEL_PMERRLOC_ELDIS		0x00c	/* Error location disable */
++#define		PMERRLOC_DISABLE		(1 << 0)
++
++#define ATMEL_PMERRLOC_ELSR		0x010	/* Error location status */
++#define		PMERRLOC_ELSR_BUSY		(1 << 0)
++#define ATMEL_PMERRLOC_ELIER		0x014	/* Error location int enable */
++#define ATMEL_PMERRLOC_ELIDR		0x018	/* Error location int disable */
++#define ATMEL_PMERRLOC_ELIMR		0x01c	/* Error location int mask */
++#define ATMEL_PMERRLOC_ELISR		0x020	/* Error location int status */
++#define		PMERRLOC_ERR_NUM_MASK		(0x1f << 8)
++#define		PMERRLOC_CALC_DONE		(1 << 0)
++#define ATMEL_PMERRLOC_SIGMAx		0x028	/* Error location SIGMA x */
++#define ATMEL_PMERRLOC_ELx		0x08c	/* Error location x */
++
++/* Register access macros for PMECC */
++#define pmecc_readl_relaxed(addr, reg) \
++	readl_relaxed((addr) + ATMEL_PMECC_##reg)
++
++#define pmecc_writel(addr, reg, value) \
++	writel((value), (addr) + ATMEL_PMECC_##reg)
++
++#define pmecc_readb_ecc_relaxed(addr, sector, n) \
++	readb_relaxed((addr) + ATMEL_PMECC_ECCx + ((sector) * 0x40) + (n))
++
++#define pmecc_readl_rem_relaxed(addr, sector, n) \
++	readl_relaxed((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4))
++
++#define pmerrloc_readl_relaxed(addr, reg) \
++	readl_relaxed((addr) + ATMEL_PMERRLOC_##reg)
++
++#define pmerrloc_writel(addr, reg, value) \
++	writel((value), (addr) + ATMEL_PMERRLOC_##reg)
++
++#define pmerrloc_writel_sigma_relaxed(addr, n, value) \
++	writel_relaxed((value), (addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
++
++#define pmerrloc_readl_sigma_relaxed(addr, n) \
++	readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
++
++#define pmerrloc_readl_el_relaxed(addr, n) \
++	readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
++
++/* Galois field dimension */
++#define PMECC_GF_DIMENSION_13			13
++#define PMECC_GF_DIMENSION_14			14
++
++#define PMECC_LOOKUP_TABLE_SIZE_512		0x2000
++#define PMECC_LOOKUP_TABLE_SIZE_1024		0x4000
++
++/* Time out value for reading PMECC status register */
++#define PMECC_MAX_TIMEOUT_MS			100
++
+ #endif
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0006-atmel_nand-port-to-2.6.39.-modify-function-definitio.patch b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0006-atmel_nand-port-to-2.6.39.-modify-function-definitio.patch
new file mode 100644
index 0000000..f2fa778
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0006-atmel_nand-port-to-2.6.39.-modify-function-definitio.patch
@@ -0,0 +1,65 @@
+From 1cf98919781b2ff8047a16b28778a59ef65570e6 Mon Sep 17 00:00:00 2001
+From: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Fri, 21 Sep 2012 15:49:29 +0200
+Subject: [PATCH 6/9] atmel_nand: port to 2.6.39. modify function definition
+ of read_page()/write_page() and remove ecc.strength.
+
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+---
+ drivers/mtd/nand/atmel_nand.c |   11 +++++------
+ 1 file changed, 5 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index a6fa5c1..8483d29 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -755,7 +755,7 @@ normal_check:
+ }
+ 
+ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
+-	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
++	struct nand_chip *chip, uint8_t *buf, int page)
+ {
+ 	struct atmel_nand_host *host = chip->priv;
+ 	int eccsize = chip->ecc.size;
+@@ -792,8 +792,8 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
+ 	return 0;
+ }
+ 
+-static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
+-		struct nand_chip *chip, const uint8_t *buf, int oob_required)
++static void atmel_nand_pmecc_write_page(struct mtd_info *mtd,
++		struct nand_chip *chip, const uint8_t *buf)
+ {
+ 	struct atmel_nand_host *host = chip->priv;
+ 	uint32_t *eccpos = chip->ecc.layout->eccpos;
+@@ -815,7 +815,7 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
+ 	while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
+ 		if (unlikely(time_after(jiffies, end_time))) {
+ 			dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
+-			return -EIO;
++			return;
+ 		}
+ 		cpu_relax();
+ 	}
+@@ -831,7 +831,7 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
+ 	}
+ 	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+ 
+-	return 0;
++	return;
+ }
+ 
+ static void atmel_pmecc_core_init(struct mtd_info *mtd)
+@@ -957,7 +957,6 @@ static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
+ 			host->pmecc_lookup_table_offset;
+ 
+ 		nand_chip->ecc.steps = 1;
+-		nand_chip->ecc.strength = cap;
+ 		nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
+ 				       host->pmecc_sector_number;
+ 		if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0007-atmel_nand-pass-the-pmecc-parameter-from-board-file-.patch b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0007-atmel_nand-pass-the-pmecc-parameter-from-board-file-.patch
new file mode 100644
index 0000000..2d7536e
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0007-atmel_nand-pass-the-pmecc-parameter-from-board-file-.patch
@@ -0,0 +1,86 @@
+From e7e9c9948a0dfac51cb88426f73001763ea79322 Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Wed, 26 Dec 2012 16:10:27 +0800
+Subject: [PATCH 7/9] atmel_nand: pass the pmecc parameter from board file to
+ driver.
+
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+---
+ arch/arm/mach-at91/include/mach/board.h |    4 ++++
+ drivers/mtd/nand/atmel_nand.c           |   37 +++++++++++++++++++++++++++++++
+ 2 files changed, 41 insertions(+)
+
+diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
+index 392a7b3..8c25c35 100644
+--- a/arch/arm/mach-at91/include/mach/board.h
++++ b/arch/arm/mach-at91/include/mach/board.h
+@@ -118,6 +118,10 @@ struct atmel_nand_data {
+ 	u8		bus_width_16;	/* buswidth is 16 bit */
+ 	u8		bus_on_d0;	/* pins of data bus are connected to D0~D15 */
+ 	u8		ecc_mode;	/* can be NAND_ECC_HW/SOFT/NONE */
++	bool		has_pmecc;	/* use pmecc or not */
++	u8		pmecc_corr_cap;	/* pmecc ecc bits, can be 2, 4, 8, 12, 24 */
++	u16		pmecc_sector_size;	/* can be 512 or 1024 */
++	u32		pmecc_lookup_table_offset;	/* offset in ROM */
+ 	struct mtd_partition* (*partition_info)(int, int*);
+ };
+ extern void __init at91_add_device_nand(struct atmel_nand_data *data);
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index 8483d29..f381f03 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -1314,6 +1314,42 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
+ 		nand_chip->dev_ready = atmel_nand_device_ready;
+ 
+ 	nand_chip->ecc.mode = host->board->ecc_mode;
++
++	/* Initialize HW ECC parameters */
++	host->has_pmecc = host->board->has_pmecc;
++	host->pmecc_corr_cap = host->board->pmecc_corr_cap;
++	host->pmecc_sector_size = host->board->pmecc_sector_size;
++	host->pmecc_lookup_table_offset =
++		host->board->pmecc_lookup_table_offset;
++
++	/* sanity check for the pmecc parameters */
++	if (nand_chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) {
++		res = 0;
++		if (host->pmecc_corr_cap != 2 && host->pmecc_corr_cap != 4 &&
++				host->pmecc_corr_cap != 8 &&
++				host->pmecc_corr_cap != 12 &&
++				host->pmecc_corr_cap != 24) {
++			dev_err(host->dev, "Invalid PMECC correction bits: %d! Only support 2, 4, 8, 12, 24.\n",
++					host->pmecc_corr_cap);
++			res = -EINVAL;
++		}
++
++		if (host->pmecc_sector_size != 512 &&
++				host->pmecc_sector_size != 1024) {
++			dev_err(host->dev, "Invalid PMECC sector size: %d! Only support 512 and 1024.\n",
++				host->pmecc_sector_size);
++			res = -EINVAL;
++		}
++
++		if (!host->pmecc_lookup_table_offset) {
++			dev_err(host->dev, "Invalid PMECC lookup table offset.\n");
++			res = -EINVAL;
++		}
++
++		if (res == -EINVAL)
++			goto err_bad_pmecc;
++	}
++
+ 	nand_chip->chip_delay = 20;		/* 20us command delay time */
+ 
+ 	if (host->board->bus_width_16)	/* 16-bit bus width */
+@@ -1426,6 +1462,7 @@ err_no_card:
+ 	platform_set_drvdata(pdev, NULL);
+ 	if (host->dma_chan)
+ 		dma_release_channel(host->dma_chan);
++err_bad_pmecc:
+ 	iounmap(host->io_base);
+ err_nand_ioremap:
+ 	kfree(host);
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0008-atmel_nand-9x5ek-enable-PMECC-in-9x5ek-board.patch b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0008-atmel_nand-9x5ek-enable-PMECC-in-9x5ek-board.patch
new file mode 100644
index 0000000..57627bd
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0008-atmel_nand-9x5ek-enable-PMECC-in-9x5ek-board.patch
@@ -0,0 +1,38 @@
+From a012c64fa08e8f334edb944b4810f58cef3382d6 Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Mon, 25 Jun 2012 18:07:43 +0800
+Subject: [PATCH 8/9] atmel_nand: 9x5ek: enable PMECC in 9x5ek board.
+
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+---
+ arch/arm/mach-at91/board-sam9x5cm.c |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/mach-at91/board-sam9x5cm.c b/arch/arm/mach-at91/board-sam9x5cm.c
+index a5f8f3d..3a78876 100644
+--- a/arch/arm/mach-at91/board-sam9x5cm.c
++++ b/arch/arm/mach-at91/board-sam9x5cm.c
+@@ -14,6 +14,7 @@
+ #include <linux/init.h>
+ #include <linux/mm.h>
+ #include <linux/module.h>
++#include <linux/mtd/nand.h>
+ #include <linux/platform_device.h>
+ #include <linux/spi/flash.h>
+ #include <linux/spi/spi.h>
+@@ -132,6 +133,11 @@ static struct atmel_nand_data __initdata cm_nand_data = {
+ 	.ale		= 21,
+ 	.cle		= 22,
+ 	.enable_pin	= AT91_PIN_PD4,
++	.ecc_mode	= NAND_ECC_HW,
++	.has_pmecc	= 1,
++	.pmecc_corr_cap	= 2,
++	.pmecc_sector_size = 512,
++	.pmecc_lookup_table_offset = 0x8000,
+ 	.partition_info	= nand_partitions,
+ #if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+ 	.bus_width_16	= 1,
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0009-atmel_nand-enable-dma-for-9x5ek.patch b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0009-atmel_nand-enable-dma-for-9x5ek.patch
new file mode 100644
index 0000000..29f0ae0
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0009-atmel_nand-enable-dma-for-9x5ek.patch
@@ -0,0 +1,28 @@
+From cc9b17713c8ae2cd06fb7b371f688ae33506e4a0 Mon Sep 17 00:00:00 2001
+From: Josh Wu <josh.wu@atmel.com>
+Date: Wed, 26 Dec 2012 16:03:42 +0800
+Subject: [PATCH 9/9] atmel_nand: enable dma for 9x5ek.
+
+
+Signed-off-by: Josh Wu <josh.wu@atmel.com>
+---
+ drivers/mtd/nand/atmel_nand.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
+index f381f03..73d20f2 100644
+--- a/drivers/mtd/nand/atmel_nand.c
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -121,7 +121,8 @@ static struct nand_ecclayout atmel_pmecc_oobinfo;
+ 
+ static int cpu_has_dma(void)
+ {
+-	return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
++	return cpu_is_at91sam9rl() || cpu_is_at91sam9g45()
++		|| cpu_is_at91sam9x5();
+ }
+ 
+ /*
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.32.3-at25.patch b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.32.3-at25.patch
new file mode 100644
index 0000000..3aa9096
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.32.3-at25.patch
@@ -0,0 +1,37 @@
+diff -uprN -X linux-2.6.32.3/Documentation/dontdiff linux-2.6.32.3-vanilla/drivers/misc/eeprom/at25.c linux-2.6.32.3/drivers/misc/eeprom/at25.c
+--- linux-2.6.32.3-vanilla/drivers/misc/eeprom/at25.c	2010-01-06 17:07:45.000000000 -0600
++++ linux-2.6.32.3/drivers/misc/eeprom/at25.c	2010-10-27 11:05:36.000000000 -0500
+@@ -147,6 +147,7 @@ at25_ee_write(struct at25_data *at25, co
+ 	unsigned		written = 0;
+ 	unsigned		buf_size;
+ 	u8			*bounce;
++	int			a8;
+ 
+ 	if (unlikely(off >= at25->bin.size))
+ 		return -EFBIG;
+@@ -163,6 +164,11 @@ at25_ee_write(struct at25_data *at25, co
+ 	if (!bounce)
+ 		return -ENOMEM;
+ 
++	if (!strcmp(at25->chip.name, "at25040b"))
++		a8 = 1;
++	else
++		a8 = 0;
++
+ 	/* For write, rollover is within the page ... so we write at
+ 	 * most one page, then manually roll over to the next page.
+ 	 */
+@@ -183,6 +189,13 @@ at25_ee_write(struct at25_data *at25, co
+ 			break;
+ 		}
+ 
++		if (a8) {
++			if (offset & BIT(8))
++				bounce[0] |= BIT(3);
++			else
++				bounce[0] &= ~BIT(3);
++		}
++
+ 		/* 8/16/24-bit address is written MSB first */
+ 		switch (at25->addrlen) {
+ 		default:	/* case 3 */
diff --git a/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.32.3-atmel_spi.patch b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.32.3-atmel_spi.patch
new file mode 100644
index 0000000..a7b87b3
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.32.3-atmel_spi.patch
@@ -0,0 +1,12 @@
+diff -uprN -X linux-2.6.32.3/Documentation/dontdiff linux-2.6.32.3-vanilla/drivers/spi/atmel_spi.c linux-2.6.32.3/drivers/spi/atmel_spi.c
+--- linux-2.6.32.3-vanilla/drivers/spi/atmel_spi.c	2010-01-06 17:07:45.000000000 -0600
++++ linux-2.6.32.3/drivers/spi/atmel_spi.c	2010-09-08 13:38:52.000000000 -0500
+@@ -768,7 +768,7 @@ static int __init atmel_spi_probe(struct
+ 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+ 
+ 	master->bus_num = pdev->id;
+-	master->num_chipselect = 4;
++	master->num_chipselect = 7;
+ 	master->setup = atmel_spi_setup;
+ 	master->transfer = atmel_spi_transfer;
+ 	master->cleanup = atmel_spi_cleanup;
diff --git a/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.32.3-option-telit.patch b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.32.3-option-telit.patch
new file mode 100644
index 0000000..db0283d
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.32.3-option-telit.patch
@@ -0,0 +1,23 @@
+diff  linux-2.6.32.3.orig/drivers/usb/serial/option.c linux-2.6.32.3/drivers/usb/serial/option.c
+--- linux-2.6.32.3.orig/drivers/usb/serial/option.c
++++ linux-2.6.32.3/drivers/usb/serial/option.c
+@@ -293,6 +293,9 @@ static int  option_resume(struct usb_serial *serial);
+ #define TELIT_VENDOR_ID				0x1bc7
+ #define TELIT_PRODUCT_UC864E			0x1003
+ #define TELIT_PRODUCT_UC864G			0x1004
++#define TELIT_PRODUCT_CC864_DUAL       0x1005
++#define TELIT_PRODUCT_CC864_SINGLE     0x1006
++#define TELIT_PRODUCT_DE910_DUAL       0x1010
+ 
+ /* ZTE PRODUCTS */
+ #define ZTE_VENDOR_ID				0x19d2
+@@ -523,6 +526,9 @@ static struct usb_device_id option_ids[] = {
+ 	{ USB_DEVICE(MAXON_VENDOR_ID, 0x6280) }, /* BP3-USB & BP3-EXT HSDPA */
+ 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_UC864E) },
+ 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_UC864G) },
++	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_CC864_DUAL) },
++	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_CC864_SINGLE) },
++	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_DE910_DUAL) },
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_MF622, 0xff, 0xff, 0xff) }, /* ZTE WCDMA products */
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0002, 0xff, 0xff, 0xff) },
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0003, 0xff, 0xff, 0xff) },
diff --git a/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.35.14-at91-gpio-pullup.patch b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.35.14-at91-gpio-pullup.patch
new file mode 100644
index 0000000..d967838
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.35.14-at91-gpio-pullup.patch
@@ -0,0 +1,43 @@
+Index: linux-2.6.35/arch/arm/mach-at91/gpio.c
+===================================================================
+--- linux-2.6.35.orig/arch/arm/mach-at91/gpio.c	2011-09-27 14:36:06.587267689 -0500
++++ linux-2.6.35/arch/arm/mach-at91/gpio.c	2011-09-27 14:42:50.997576753 -0500
+@@ -202,6 +202,26 @@
+ }
+ EXPORT_SYMBOL(at91_set_gpio_output);
+ 
++/*
++ * configure pin for output and enable/disable pullup
++ */
++int __init_or_module at91_set_gpio_output_with_pullup(unsigned pin, int value, int use_pullup)
++{
++	void __iomem	*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	if (!pio)
++		return -EINVAL;
++
++	__raw_writel(mask, pio + PIO_IDR);
++	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
++	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
++	__raw_writel(mask, pio + PIO_OER);
++	__raw_writel(mask, pio + PIO_PER);
++	return 0;
++}
++EXPORT_SYMBOL(at91_set_gpio_output_with_pullup);
++
+ 
+ /*
+  * enable/disable the glitch filter; mostly used with IRQ handling.
+Index: linux-2.6.35/arch/arm/mach-at91/include/mach/gpio.h
+===================================================================
+--- linux-2.6.35.orig/arch/arm/mach-at91/include/mach/gpio.h
++++ linux-2.6.35/arch/arm/mach-at91/include/mach/gpio.h
+@@ -194,6 +194,7 @@ extern int __init_or_module at91_set_A_p
+ extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
+ extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
+ extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
++extern int __init_or_module at91_set_gpio_output_with_pullup(unsigned pin, int value, int use_pullup);
+ extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
+ extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
+ 
diff --git a/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.35.14-option-zte.patch b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.35.14-option-zte.patch
new file mode 100644
index 0000000..776c7ee
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.35.14-option-zte.patch
@@ -0,0 +1,12 @@
+Index: linux-2.6.35/drivers/usb/serial/option.c
+===================================================================
+--- linux-2.6.35.orig/drivers/usb/serial/option.c
++++ linux-2.6.35/drivers/usb/serial/option.c
+@@ -889,6 +889,7 @@ static const struct usb_device_id option
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0141, 0xff, 0xff, 0xff) },
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x2002, 0xff, 0xff, 0xff) },
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x2003, 0xff, 0xff, 0xff) },
++	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xffe8, 0xff, 0xff, 0xff) }, // MC2718
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_CDMA_TECH, 0xff, 0xff, 0xff) },
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AC8710, 0xff, 0xff, 0xff) },
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AC2726, 0xff, 0xff, 0xff) },
diff --git a/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.38-sierra-1.7.40.patch b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.38-sierra-1.7.40.patch
new file mode 100644
index 0000000..6e55adf
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.38-sierra-1.7.40.patch
@@ -0,0 +1,1556 @@
+Index: linux-2.6.39.4/drivers/net/usb/sierra_net.c
+===================================================================
+--- linux-2.6.39.4.orig/drivers/net/usb/sierra_net.c	2012-02-27 15:37:27.810465204 -0600
++++ linux-2.6.39.4/drivers/net/usb/sierra_net.c	2011-09-22 17:05:46.000000000 -0500
+@@ -1,7 +1,7 @@
+ /*
+  * USB-to-WWAN Driver for Sierra Wireless modems
+  *
+- * Copyright (C) 2008, 2009, 2010 Paxton Smith, Matthew Safar, Rory Filer
++ * Copyright (C) 2008 - 2011 Paxton Smith, Matthew Safar, Rory Filer
+  *                          <linux@sierrawireless.com>
+  *
+  * Portions of this based on the cdc_ether driver by David Brownell (2003-2005)
+@@ -25,13 +25,17 @@
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+  */
+ 
+-#define DRIVER_VERSION "v.2.0"
++#define DRIVER_VERSION "v.3.2"
+ #define DRIVER_AUTHOR "Paxton Smith, Matthew Safar, Rory Filer"
+ #define DRIVER_DESC "USB-to-WWAN Driver for Sierra Wireless modems"
+ static const char driver_name[] = "sierra_net";
+ 
+ /* if defined debug messages enabled */
+ /*#define	DEBUG*/
++/* more debug messages */
++/*#define	VERBOSE*/
++/* Uncomment to force power level set to auto when attaching a device */
++/*#define POWER_LEVEL_AUTO*/
+ 
+ #include <linux/module.h>
+ #include <linux/etherdevice.h>
+@@ -48,6 +52,7 @@
+ 
+ #define SWI_USB_REQUEST_GET_FW_ATTR	0x06
+ #define SWI_GET_FW_ATTR_MASK		0x08
++#define SWI_GET_FW_ATTR_APM			0x2
+ 
+ /* atomic counter partially included in MAC address to make sure 2 devices
+  * do not end up with the same MAC - concept breaks in case of > 255 ifaces
+@@ -68,6 +73,11 @@
+  */
+ #define SIERRA_NET_USBCTL_BUF_LEN	1024
+ 
++/* The SIERRA_NET_RX_URB_SZ defines the receive urb size
++ * for optimal throughput.
++ */
++#define SIERRA_NET_RX_URB_SZ		1540
++
+ /* list of interface numbers - used for constructing interface lists */
+ struct sierra_net_iface_info {
+ 	const u32 infolen;	/* number of interface numbers on list */
+@@ -139,6 +149,7 @@
+ #define SIERRA_NET_SESSION_IDLE       0x00
+ /* LSI Link types */
+ #define SIERRA_NET_AS_LINK_TYPE_IPv4  0x00
++#define SIERRA_NET_AS_LINK_TYPE_IPv6  0x02
+ 
+ struct lsi_umts {
+ 	u8 protocol;
+@@ -200,10 +211,11 @@
+ 	dev->data[0] = (unsigned long)priv;
+ }
+ 
+-/* is packet IPv4 */
++/* is packet IP */
+ static inline int is_ip(struct sk_buff *skb)
+ {
+-	return skb->protocol == cpu_to_be16(ETH_P_IP);
++	return ((skb->protocol == cpu_to_be16(ETH_P_IP)) ||
++			(skb->protocol == cpu_to_be16(ETH_P_IPV6)));
+ }
+ 
+ /*
+@@ -312,6 +324,24 @@
+ /*----------------------------------------------------------------------------*
+  *                              END HIP                                       *
+  *----------------------------------------------------------------------------*/
++/* This should come out before going to kernel.org */
++static void sierra_net_printk_buf(u8 *buf, u16 len)
++{
++#ifdef VERBOSE
++	u16 i;
++	u16 k;
++
++	for (i = k = 0; i < len / 4; i++, k += 4) {
++		printk(KERN_DEBUG "%02x%02x%02x%02x ",
++			buf[k+0], buf[k+1], buf[k+2], buf[k+3]);
++	}
++
++	for (; k < len;  k++)
++		printk(KERN_DEBUG "%02x", buf[k]);
++
++	printk("\n");
++#endif
++}
+ 
+ static int sierra_net_send_cmd(struct usbnet *dev,
+ 		u8 *cmd, int cmdlen, const char * cmd_name)
+@@ -319,10 +349,12 @@
+ 	struct sierra_net_data *priv = sierra_net_get_private(dev);
+ 	int  status;
+ 
++	usb_autopm_get_interface(dev->intf);
+ 	status = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
+ 			USB_CDC_SEND_ENCAPSULATED_COMMAND,
+ 			USB_DIR_OUT|USB_TYPE_CLASS|USB_RECIP_INTERFACE,	0,
+ 			priv->ifnum, cmd, cmdlen, USB_CTRL_SET_TIMEOUT);
++	usb_autopm_put_interface(dev->intf);
+ 
+ 	if (status != cmdlen && status != -ENODEV)
+ 		netdev_err(dev->net, "Submit %s failed %d\n", cmd_name, status);
+@@ -339,8 +371,17 @@
+ 
+ 	status = sierra_net_send_cmd(dev, priv->sync_msg,
+ 			sizeof(priv->sync_msg), "SYNC");
++    return status;
++}
+ 
+-	return status;
++static void sierra_net_send_shutdown(struct usbnet *dev)
++{
++	struct sierra_net_data *priv = sierra_net_get_private(dev);
++
++	dev_dbg(&dev->udev->dev, "%s", __func__);
++
++	sierra_net_send_cmd(dev, priv->shdwn_msg,
++			sizeof(priv->shdwn_msg), "Shutdown");
+ }
+ 
+ static void sierra_net_set_ctx_index(struct sierra_net_data *priv, u8 ctx_ix)
+@@ -354,7 +395,7 @@
+ 
+ static inline int sierra_net_is_valid_addrlen(u8 len)
+ {
+-	return len == sizeof(struct in_addr);
++	return (len == sizeof(struct in_addr));
+ }
+ 
+ static int sierra_net_parse_lsi(struct usbnet *dev, char *data, int datalen)
+@@ -383,10 +424,11 @@
+ 	}
+ 
+ 	/* Validate the link type */
+-	if (lsi->link_type != SIERRA_NET_AS_LINK_TYPE_IPv4) {
+-		netdev_err(dev->net, "Link type unsupported: 0x%02x\n",
++	if ((lsi->link_type != SIERRA_NET_AS_LINK_TYPE_IPv4) &&
++		(lsi->link_type != SIERRA_NET_AS_LINK_TYPE_IPv6)) {
++		netdev_err(dev->net, "Link unavailable: 0x%02x",
+ 			lsi->link_type);
+-		return -1;
++		return 0;
+ 	}
+ 
+ 	/* Validate the coverage */
+@@ -474,13 +516,15 @@
+ 			return;
+ 		}
+ 		ifnum = priv->ifnum;
++		usb_autopm_get_interface(dev->intf);
+ 		len = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
+ 				USB_CDC_GET_ENCAPSULATED_RESPONSE,
+ 				USB_DIR_IN|USB_TYPE_CLASS|USB_RECIP_INTERFACE,
+ 				0, ifnum, buf, SIERRA_NET_USBCTL_BUF_LEN,
+ 				USB_CTRL_SET_TIMEOUT);
++		usb_autopm_put_interface(dev->intf);
+ 
+-		if (len < 0) {
++		if (unlikely(len < 0)) {
+ 			netdev_err(dev->net,
+ 				"usb_control_msg failed, status %d\n", len);
+ 		} else {
+@@ -488,6 +532,7 @@
+ 
+ 			dev_dbg(&dev->udev->dev, "%s: Received status message,"
+ 				" %04x bytes", __func__, len);
++			sierra_net_printk_buf(buf, len);
+ 
+ 			err = parse_hip(buf, len, &hh);
+ 			if (err) {
+@@ -534,7 +579,10 @@
+ 					"extmsgid 0x%04x\n", hh.extmsgid.word);
+ 				break;
+ 			case SIERRA_NET_HIP_RCGI:
+-				/* Ignored */
++				/* Ignored. It is a firmware
++				 * workaround to solve a  Windows driver bug and
++				 * may be removed in the future. 
++				 */
+ 				break;
+ 			default:
+ 				netdev_err(dev->net, "Unrecognized HIP msg, "
+@@ -561,7 +609,10 @@
+ 	struct sierra_net_data *priv = sierra_net_get_private(dev);
+ 
+ 	set_bit(work, &priv->kevent_flags);
+-	schedule_work(&priv->sierra_net_kevent);
++	if (!schedule_work(&priv->sierra_net_kevent))
++		dev_dbg(&dev->udev->dev, "sierra_net_kevent %d may have been dropped", work);
++	else
++		dev_dbg(&dev->udev->dev, "sierra_net_kevent %d scheduled", work);
+ }
+ 
+ /*
+@@ -581,6 +632,7 @@
+ 	struct usb_cdc_notification *event;
+ 
+ 	dev_dbg(&dev->udev->dev, "%s", __func__);
++	sierra_net_printk_buf(urb->transfer_buffer, urb->actual_length);
+ 
+ 	if (urb->actual_length < sizeof *event)
+ 		return;
+@@ -661,6 +713,7 @@
+ 	if (!attrdata)
+ 		return -ENOMEM;
+ 
++	usb_autopm_get_interface(dev->intf);
+ 	result = usb_control_msg(
+ 			dev->udev,
+ 			usb_rcvctrlpipe(dev->udev, 0),
+@@ -672,6 +725,7 @@
+ 			attrdata,	/* char *data */
+ 			sizeof(*attrdata),		/* __u16 size */
+ 			USB_CTRL_SET_TIMEOUT);	/* int timeout */
++	usb_autopm_put_interface(dev->intf);
+ 
+ 	if (result < 0) {
+ 		kfree(attrdata);
+@@ -684,6 +738,12 @@
+ 	return result;
+ }
+ 
++static int sierra_net_manage_power(struct usbnet *dev, int on)
++{
++	dev->intf->needs_remote_wakeup = on;
++	return 0;
++}
++
+ /*
+  * collects the bulk endpoints, the status endpoint.
+  */
+@@ -735,6 +795,10 @@
+ 
+ 	priv->usbnet = dev;
+ 	priv->ifnum = ifacenum;
++	/* override change_mtu with our own routine - need to bound check */
++	/* replace structure to our own structure where we have our own
++	 *  routine - need to bound check
++	 */
+ 	dev->net->netdev_ops = &sierra_net_device_ops;
+ 
+ 	/* change MAC addr to include, ifacenum, and to be unique */
+@@ -761,6 +825,7 @@
+ 
+ 	/* Set up the netdev */
+ 	dev->net->flags |= IFF_NOARP;
++	dev->net->flags |= IFF_MULTICAST;
+ 	dev->net->ethtool_ops = &sierra_net_ethtool_ops;
+ 	netif_carrier_off(dev->net);
+ 
+@@ -773,11 +838,23 @@
+ 
+ 	/* Only need to do this once */
+ 	init_timer(&priv->sync_timer);
+-
+ 	/* verify fw attributes */
+ 	status = sierra_net_get_fw_attr(dev, &fwattr);
+-	dev_dbg(&dev->udev->dev, "Fw attr: %x\n", fwattr);
+-
++	dev_dbg(&dev->udev->dev, "Fw attr: %x\n", fwattr); 
++	if (status == sizeof(fwattr) && (fwattr & SWI_GET_FW_ATTR_APM)) {
++/******************************************************************************* 
++ * If you want the default /sys/bus/usb/devices/.../.../power/level to be forced
++ * to auto, the following needs to be compiled in.
++ */ 
++#ifdef POWER_LEVEL_AUTO
++		/* make power level default be 'auto' */
++		dev_dbg(&dev->udev->dev, "Enabling APM");
++		usb_enable_autosuspend(dev->udev);
++#endif
++	} else {
++		dev_info(&intf->dev, "Disabling APM - not supported");
++		usb_disable_autosuspend(dev->udev);
++	}
+ 	/* test whether firmware supports DHCP */
+ 	if (!(status == sizeof(fwattr) && (fwattr & SWI_GET_FW_ATTR_MASK))) {
+ 		/* found incompatible firmware version */
+@@ -789,33 +866,45 @@
+ 	/* prepare sync message from template */
+ 	memcpy(priv->sync_msg, sync_tmplate, sizeof(priv->sync_msg));
+ 
++	return 0;
++}
++
++static void sierra_net_unbind(struct usbnet *dev, struct usb_interface *intf)
++{
++	struct sierra_net_data *priv = sierra_net_get_private(dev);
++
++	dev_dbg(&dev->udev->dev, "%s", __func__);
++
++	sierra_net_set_private(dev, NULL);
++
++	kfree(priv);
++}
++
++static int sierra_net_open(struct usbnet *dev)
++{
++	dev_dbg(&dev->udev->dev, "%s", __func__);
++
+ 	/* initiate the sync sequence */
+ 	sierra_net_dosync(dev);
+ 
+ 	return 0;
+ }
+ 
+-static void sierra_net_unbind(struct usbnet *dev, struct usb_interface *intf)
++static int sierra_net_stop(struct usbnet *dev)
+ {
+-	int status;
+ 	struct sierra_net_data *priv = sierra_net_get_private(dev);
+ 
+ 	dev_dbg(&dev->udev->dev, "%s", __func__);
+ 
+-	/* kill the timer and work */
++	/* Kill the timer then flush the work queue */
+ 	del_timer_sync(&priv->sync_timer);
++
+ 	cancel_work_sync(&priv->sierra_net_kevent);
+ 
+ 	/* tell modem we are going away */
+-	status = sierra_net_send_cmd(dev, priv->shdwn_msg,
+-			sizeof(priv->shdwn_msg), "Shutdown");
+-	if (status < 0)
+-		netdev_err(dev->net,
+-			"usb_control_msg failed, status %d\n", status);
+-
+-	sierra_net_set_private(dev, NULL);
++	sierra_net_send_shutdown(dev);
+ 
+-	kfree(priv);
++	return 0;
+ }
+ 
+ static struct sk_buff *sierra_net_skb_clone(struct usbnet *dev,
+@@ -847,9 +936,13 @@
+ 	int err;
+ 	struct hip_hdr  hh;
+ 	struct sk_buff *new_skb;
++	struct ethhdr *eth;
++	struct iphdr *ip;
+ 
+ 	dev_dbg(&dev->udev->dev, "%s", __func__);
+ 
++	sierra_net_printk_buf(skb->data, skb->len);
++
+ 	/* could contain multiple packets */
+ 	while (likely(skb->len)) {
+ 		err = parse_hip(skb->data, skb->len, &hh);
+@@ -879,6 +972,12 @@
+ 		memcpy(skb->data, sierra_net_get_private(dev)->ethr_hdr_tmpl,
+ 			ETH_HLEN);
+ 
++		ip = (struct iphdr *)((char *)skb->data + ETH_HLEN);
++		if(ip->version == 6) {
++			eth = (struct ethhdr *)skb->data;
++			eth->h_proto = cpu_to_be16(ETH_P_IPV6);
++		}
++
+ 		/* Last packet in batch handled by usbnet */
+ 		if (hh.payload_len.word == skb->len)
+ 			return 1;
+@@ -923,6 +1022,8 @@
+ 				}
+ 			}
+ 			build_hip(skb->data, len, priv);
++
++            sierra_net_printk_buf(skb->data, skb->len);
+ 			return skb;
+ 		} else {
+ 			/*
+@@ -942,16 +1043,24 @@
+ 	return NULL;
+ }
+ 
++static int sierra_net_reset_resume(struct usb_interface *intf)
++{
++	struct usbnet	*dev = usb_get_intfdata(intf);
++	netdev_err(dev->net, "%s\n", __func__);
++	return usbnet_resume(intf);
++}
++
+ static const u8 sierra_net_ifnum_list[] = { 7, 10, 11 };
+-static const struct sierra_net_info_data sierra_net_info_data_68A3 = {
+-	.rx_urb_size = 8 * 1024,
++static const struct sierra_net_info_data sierra_net_info_data_direct_ip = {
++	/* .rx_urb_size = 8 * 1024, */
++	.rx_urb_size = SIERRA_NET_RX_URB_SZ,
+ 	.whitelist = {
+ 		.infolen = ARRAY_SIZE(sierra_net_ifnum_list),
+ 		.ifaceinfo = sierra_net_ifnum_list
+ 	}
+ };
+ 
+-static const struct driver_info sierra_net_info_68A3 = {
++static const struct driver_info sierra_net_info_direct_ip = {
+ 	.description = "Sierra Wireless USB-to-WWAN Modem",
+ 	.flags = FLAG_WWAN | FLAG_SEND_ZLP,
+ 	.bind = sierra_net_bind,
+@@ -959,12 +1068,21 @@
+ 	.status = sierra_net_status,
+ 	.rx_fixup = sierra_net_rx_fixup,
+ 	.tx_fixup = sierra_net_tx_fixup,
+-	.data = (unsigned long)&sierra_net_info_data_68A3,
++	.manage_power = sierra_net_manage_power,
++	.stop = sierra_net_stop,
++	.check_connect = sierra_net_open,
++	.data = (unsigned long)&sierra_net_info_data_direct_ip,
+ };
+ 
+ static const struct usb_device_id products[] = {
+-	{USB_DEVICE(0x1199, 0x68A3), /* Sierra Wireless USB-to-WWAN modem */
+-	.driver_info = (unsigned long) &sierra_net_info_68A3},
++	{USB_DEVICE(0x1199, 0x68A3), /* Sierra Wireless Direct IP modem */
++	.driver_info = (unsigned long) &sierra_net_info_direct_ip},
++	{USB_DEVICE(0xF3D, 0x68A3), /* AT&T Direct IP modem */
++	.driver_info = (unsigned long) &sierra_net_info_direct_ip},
++	{USB_DEVICE(0x1199, 0x68AA), /* Sierra Wireless Direct IP LTE modem */
++	.driver_info = (unsigned long) &sierra_net_info_direct_ip},
++	{USB_DEVICE(0xF3D, 0x68AA), /* AT&T Direct IP LTE modem */
++	.driver_info = (unsigned long) &sierra_net_info_direct_ip},
+ 
+ 	{}, /* last item */
+ };
+@@ -978,7 +1096,9 @@
+ 	.disconnect = usbnet_disconnect,
+ 	.suspend = usbnet_suspend,
+ 	.resume = usbnet_resume,
++	.reset_resume = sierra_net_reset_resume,
+ 	.no_dynamic_id = 1,
++	.supports_autosuspend = 1,
+ };
+ 
+ static int __init sierra_net_init(void)
+Index: linux-2.6.39.4/drivers/usb/serial/sierra.c
+===================================================================
+--- linux-2.6.39.4.orig/drivers/usb/serial/sierra.c	2012-02-27 15:38:01.519215085 -0600
++++ linux-2.6.39.4/drivers/usb/serial/sierra.c	2011-09-22 17:05:46.000000000 -0500
+@@ -3,7 +3,7 @@
+ 
+   Copyright (C) 2006, 2007, 2008  Kevin Lloyd <klloyd@sierrawireless.com>,
+ 
+-  Copyright (C) 2008, 2009  Elina Pasheva, Matthew Safar, Rory Filer
++  Copyright (C) 2008 - 2011  Elina Pasheva, Matthew Safar, Rory Filer
+ 			<linux@sierrawireless.com>
+ 
+   IMPORTANT DISCLAIMER: This driver is not commercially supported by
+@@ -17,8 +17,12 @@
+   Whom based his on the Keyspan driver by Hugh Blemings <hugh@blemings.org>
+ */
+ /* Uncomment to log function calls */
+-/* #define DEBUG */
+-#define DRIVER_VERSION "v.1.7.16"
++/*#define DEBUG*/
++/* Uncomment to force power level set to auto when attaching a device */
++/*#define POWER_LEVEL_AUTO*/
++
++/* Sierra driver - kernel 2.6.38 */
++#define DRIVER_VERSION "v.1.7.40"
+ #define DRIVER_AUTHOR "Kevin Lloyd, Elina Pasheva, Matthew Safar, Rory Filer"
+ #define DRIVER_DESC "USB Driver for Sierra Wireless USB modems"
+ 
+@@ -31,9 +35,13 @@
+ #include <linux/module.h>
+ #include <linux/usb.h>
+ #include <linux/usb/serial.h>
++#include <asm/unaligned.h>
+ 
+ #define SWIMS_USB_REQUEST_SetPower	0x00
++#define SWIMS_USB_REQUEST_GetFwAttr	0x06
+ #define SWIMS_USB_REQUEST_SetNmea	0x07
++#define USB_REQUEST_TYPE_CLASS		0xA1
++#define USB_REQUEST_IFACE		0x20
+ 
+ #define N_IN_URB_HM	8
+ #define N_OUT_URB_HM	64
+@@ -46,19 +54,47 @@
+    allocations > PAGE_SIZE and the number of packets in a page
+    is an integer 512 is the largest possible packet on EHCI */
+ 
++#define SWI_FW_ATTR_PM_MASK		0x02
++/* PORTION_LEN defines the length of device attribute buffer */
++#define PORTION_LEN			4096
++
+ static int debug;
+ static int nmea;
+ 
++/* sysfs attributes */
++static int sierra_create_sysfs_attrs(struct usb_serial_port *port);
++static int sierra_remove_sysfs_attrs(struct usb_serial_port *port);
++
+ /* Used in interface blacklisting */
+ struct sierra_iface_info {
+ 	const u32 infolen;	/* number of interface numbers on blacklist */
+ 	const u8  *ifaceinfo;	/* pointer to the array holding the numbers */
+ };
+ 
++/* per interface statistics */
++struct sierra_intf_stats {
++	atomic_t	rx_bytes;		/* received bytes */
++	atomic_t	indat_cb_cnt;		/* indat callback count */
++	atomic_t	indat_cb_fail;		/* indat cb with error */
++
++	atomic_t	tx_bytes;		/* transmitted bytes */
++	atomic_t	write_cnt;		/* no. of writes */
++	atomic_t	write_err;		/* no. of failed writes */
++
++	atomic_t	delayed_writes;		/* no. of delayed writes */
++	atomic_t	delayed_write_err;	/* no. of delayed write errs */
++
++	atomic_t	outdat_cb_cnt;		/* outdat callback count */
++	atomic_t	outdat_cb_fail;		/* outdat cb with error */
++
++};
++
+ struct sierra_intf_private {
+ 	spinlock_t susp_lock;
+ 	unsigned int suspended:1;
+ 	int in_flight;
++
++	struct sierra_intf_stats stats;
+ };
+ 
+ static int sierra_set_power_state(struct usb_device *udev, __u16 swiState)
+@@ -91,6 +127,38 @@
+ 	return result;
+ }
+ 
++static int sierra_get_fw_attr(struct usb_device *udev, u16 *data)
++{
++	int result;
++	u16 *attrdata;
++
++	dev_dbg(&udev->dev, "%s\n", __func__);
++
++	attrdata = kmalloc(sizeof(*attrdata), GFP_KERNEL);
++	if (!attrdata)
++		return -ENOMEM;
++
++	result = usb_control_msg(udev,
++				usb_rcvctrlpipe(udev, 0),
++				SWIMS_USB_REQUEST_GetFwAttr,  /* __u8 request*/
++				USB_TYPE_VENDOR | USB_DIR_IN, /* request type*/
++				0x0000,			/* __u16 value       */
++				0x0000,			/* __u16 index       */
++				attrdata,		/* void *data        */
++				sizeof(*attrdata),	/* _u16 size         */
++				USB_CTRL_SET_TIMEOUT);	/* in timeout        */
++
++	if (result < 0) {
++		kfree(attrdata);
++		return -EIO;
++	}
++
++	*data = *attrdata;
++
++	kfree(attrdata);
++	return result;
++}
++
+ static int sierra_calc_num_ports(struct usb_serial *serial)
+ {
+ 	int num_ports = 0;
+@@ -150,7 +218,6 @@
+ 	int interface;
+ 	struct usb_interface *p_interface;
+ 	struct usb_host_interface *p_host_interface;
+-	dev_dbg(&serial->dev->dev, "%s\n", __func__);
+ 
+ 	/* Get the interface structure pointer from the serial struct */
+ 	p_interface = serial->interface;
+@@ -159,8 +226,7 @@
+ 	p_host_interface = p_interface->cur_altsetting;
+ 
+ 	/* read the interface descriptor for this active altsetting
+-	 * to find out the interface number we are on
+-	*/
++	 * to find out the interface number we are on */
+ 	interface = p_host_interface->desc.bInterfaceNumber;
+ 
+ 	return interface;
+@@ -171,7 +237,7 @@
+ {
+ 	int result = 0;
+ 	struct usb_device *udev;
+-	struct sierra_intf_private *data;
++	struct sierra_intf_private *intfdata;
+ 	u8 ifnum;
+ 
+ 	udev = serial->dev;
+@@ -185,7 +251,9 @@
+ 	if (serial->interface->num_altsetting == 2) {
+ 		dev_dbg(&udev->dev, "Selecting alt setting for interface %d\n",
+ 			ifnum);
+-		/* We know the alternate setting is 1 for the MC8785 */
++		/* We know the alternate setting is for composite USB interface
++		 * modems
++		 */
+ 		usb_set_interface(udev, ifnum, 1);
+ 	}
+ 
+@@ -199,10 +267,11 @@
+ 		return -ENODEV;
+ 	}
+ 
+-	data = serial->private = kzalloc(sizeof(struct sierra_intf_private), GFP_KERNEL);
+-	if (!data)
++	intfdata = serial->private = kzalloc(sizeof(struct sierra_intf_private),
++						GFP_KERNEL);
++	if (!intfdata)
+ 		return -ENOMEM;
+-	spin_lock_init(&data->susp_lock);
++	spin_lock_init(&intfdata->susp_lock);
+ 
+ 	return result;
+ }
+@@ -223,15 +292,15 @@
+ /* 'blacklist' of interfaces not served by this driver */
+ static const u8 direct_ip_non_serial_ifaces[] = { 7, 8, 9, 10, 11 };
+ static const struct sierra_iface_info direct_ip_interface_blacklist = {
+-	.infolen = ARRAY_SIZE(direct_ip_non_serial_ifaces),
++	.infolen = ARRAY_SIZE( direct_ip_non_serial_ifaces ),
+ 	.ifaceinfo = direct_ip_non_serial_ifaces,
+ };
+ 
+-static const struct usb_device_id id_table[] = {
++static const struct usb_device_id id_table [] = {
+ 	{ USB_DEVICE(0x0F3D, 0x0112) }, /* Airprime/Sierra PC 5220 */
+ 	{ USB_DEVICE(0x03F0, 0x1B1D) },	/* HP ev2200 a.k.a MC5720 */
+-	{ USB_DEVICE(0x03F0, 0x211D) }, /* HP ev2210 a.k.a MC5725 */
+ 	{ USB_DEVICE(0x03F0, 0x1E1D) },	/* HP hs2300 a.k.a MC8775 */
++	{ USB_DEVICE(0x03F0, 0x211D) }, /* HP ev2210 a.k.a MC5725 */
+ 
+ 	{ USB_DEVICE(0x1199, 0x0017) },	/* Sierra Wireless EM5625 */
+ 	{ USB_DEVICE(0x1199, 0x0018) },	/* Sierra Wireless MC5720 */
+@@ -245,7 +314,10 @@
+ 	{ USB_DEVICE(0x1199, 0x0021) },	/* Sierra Wireless AirCard 597E */
+ 	{ USB_DEVICE(0x1199, 0x0112) }, /* Sierra Wireless AirCard 580 */
+ 	{ USB_DEVICE(0x1199, 0x0120) },	/* Sierra Wireless USB Dongle 595U */
+-	{ USB_DEVICE(0x1199, 0x0301) },	/* Sierra Wireless USB Dongle 250U */
++	{ USB_DEVICE(0x1199, 0x0301) },	/* Sierra Wireless USB Dongle 250U/3G */
++	/* Sierra Wireless MC5728 */
++	{ USB_DEVICE_AND_INTERFACE_INFO(0x1199, 0x0400, 0xFF, 0xFF, 0xFF) },
++
+ 	/* Sierra Wireless C597 */
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(0x1199, 0x0023, 0xFF, 0xFF, 0xFF) },
+ 	/* Sierra Wireless T598 */
+@@ -253,7 +325,7 @@
+ 	{ USB_DEVICE(0x1199, 0x0026) }, /* Sierra Wireless T11 */
+ 	{ USB_DEVICE(0x1199, 0x0027) }, /* Sierra Wireless AC402 */
+ 	{ USB_DEVICE(0x1199, 0x0028) }, /* Sierra Wireless MC5728 */
+-	{ USB_DEVICE(0x1199, 0x0029) }, /* Sierra Wireless Device */
++	{ USB_DEVICE(0x114F, 0x6000) }, /* Sierra Wireless Q26 Elite */
+ 
+ 	{ USB_DEVICE(0x1199, 0x6802) },	/* Sierra Wireless MC8755 */
+ 	{ USB_DEVICE(0x1199, 0x6803) },	/* Sierra Wireless MC8765 */
+@@ -277,7 +349,7 @@
+ 	{ USB_DEVICE(0x1199, 0x683A) },	/* Sierra Wireless MC8785 */
+ 	{ USB_DEVICE(0x1199, 0x683B) },	/* Sierra Wireless MC8785 Composite */
+ 	/* Sierra Wireless MC8790, MC8791, MC8792 Composite */
+-	{ USB_DEVICE(0x1199, 0x683C) },
++	{ USB_DEVICE(0x1199, 0x683C) },	
+ 	{ USB_DEVICE(0x1199, 0x683D) },	/* Sierra Wireless MC8791 Composite */
+ 	/* Sierra Wireless MC8790, MC8791, MC8792 */
+ 	{ USB_DEVICE(0x1199, 0x683E) },
+@@ -298,22 +370,34 @@
+ 	/* Sierra Wireless HSPA Non-Composite Device */
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(0x1199, 0x6892, 0xFF, 0xFF, 0xFF)},
+ 	{ USB_DEVICE(0x1199, 0x6893) },	/* Sierra Wireless Device */
+-	{ USB_DEVICE(0x1199, 0x68A3), 	/* Sierra Wireless Direct IP modems */
+-	  .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist
++	/* Sierra Wireless Direct IP modems */
++	{ USB_DEVICE_AND_INTERFACE_INFO(0x1199, 0x68A3, 0xFF, 0xFF, 0xFF),
++	  .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist 
+ 	},
+-	{ USB_DEVICE(0x0f3d, 0x68A3), 	/* Airprime/Sierra Wireless Direct IP modems */
+-	  .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist
++	/* AT&T Direct IP modems */
++	{ USB_DEVICE_AND_INTERFACE_INFO(0x0F3D, 0x68A3, 0xFF, 0xFF, 0xFF),
++	  .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist 
+ 	},
+-       { USB_DEVICE(0x413C, 0x08133) }, /* Dell Computer Corp. Wireless 5720 VZW Mobile Broadband (EVDO Rev-A) Minicard GPS Port */
++	/* Sierra Wireless Direct IP LTE modems */
++	{ USB_DEVICE_AND_INTERFACE_INFO(0x1199, 0x68AA, 0xFF, 0xFF, 0xFF),
++	  .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist 
++	},
++	/* AT&T Direct IP LTE modems */
++	{ USB_DEVICE_AND_INTERFACE_INFO(0x0F3D, 0x68AA, 0xFF, 0xFF, 0xFF),
++	  .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist 
++	},
++	/* Wireless 5720 VZW Mobile Broadband (EVDO Rev-A) Minicard GPS Port */
++	{ USB_DEVICE(0x413C, 0x8133) },
+ 
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(usb, id_table);
+ 
+-
++/* per port private data */
+ struct sierra_port_private {
+ 	spinlock_t lock;	/* lock the structure */
+ 	int outstanding_urbs;	/* number of out urbs in flight */
++
+ 	struct usb_anchor active;
+ 	struct usb_anchor delayed;
+ 
+@@ -335,7 +419,7 @@
+ static int sierra_send_setup(struct usb_serial_port *port)
+ {
+ 	struct usb_serial *serial = port->serial;
+-	struct sierra_port_private *portdata;
++	struct sierra_port_private *portdata = usb_get_serial_port_data(port);
+ 	__u16 interface = 0;
+ 	int val = 0;
+ 	int do_send = 0;
+@@ -343,8 +427,6 @@
+ 
+ 	dev_dbg(&port->dev, "%s\n", __func__);
+ 
+-	portdata = usb_get_serial_port_data(port);
+-
+ 	if (portdata->dtr_state)
+ 		val |= 0x01;
+ 	if (portdata->rts_state)
+@@ -376,10 +458,7 @@
+ 	if (!do_send)
+ 		return 0;
+ 
+-	retval = usb_autopm_get_interface(serial->interface);
+-	if (retval < 0)
+-		return retval;
+-
++	usb_autopm_get_interface(serial->interface);
+ 	retval = usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
+ 		0x22, 0x21, val, interface, NULL, 0, USB_CTRL_SET_TIMEOUT);
+ 	usb_autopm_put_interface(serial->interface);
+@@ -395,7 +474,7 @@
+ 	sierra_send_setup(port);
+ }
+ 
+-static int sierra_tiocmget(struct tty_struct *tty)
++static int sierra_tiocmget(struct tty_struct *tty, struct file *file)
+ {
+ 	struct usb_serial_port *port = tty->driver_data;
+ 	unsigned int value;
+@@ -414,7 +493,7 @@
+ 	return value;
+ }
+ 
+-static int sierra_tiocmset(struct tty_struct *tty,
++static int sierra_tiocmset(struct tty_struct *tty, struct file *file,
+ 			unsigned int set, unsigned int clear)
+ {
+ 	struct usb_serial_port *port = tty->driver_data;
+@@ -440,11 +519,77 @@
+ 	if (urb) {
+ 		port =  urb->context;
+ 		dev_dbg(&port->dev, "%s: %p\n", __func__, urb);
+-		kfree(urb->transfer_buffer);
+ 		usb_free_urb(urb);
+ 	}
+ }
+ 
++/* Sysfs Attributes */
++
++static ssize_t show_suspend_status(struct device *dev,
++	struct device_attribute *attr, char *buf)
++{
++	struct usb_serial_port *port;
++	struct sierra_port_private *portdata;
++	struct sierra_intf_private *intfdata;
++	unsigned long flags;
++	unsigned int flag_suspended = 0;
++
++	port = to_usb_serial_port(dev);
++	portdata = usb_get_serial_port_data(port);
++	intfdata = port->serial->private;
++
++	spin_lock_irqsave(&intfdata->susp_lock, flags);
++	flag_suspended = intfdata->suspended;
++	spin_unlock_irqrestore(&intfdata->susp_lock, flags);
++
++	return snprintf(buf, PORTION_LEN, "%i\n", flag_suspended);
++}
++
++static ssize_t show_stats(struct device *dev,
++	struct device_attribute *attr, char *buf)
++{
++	struct usb_serial_port *port;
++	struct sierra_intf_private *intfdata;
++
++	port = to_usb_serial_port(dev);
++	intfdata = port->serial->private;
++
++	return snprintf(buf, PORTION_LEN,
++		"rx: %i B\tindat: %i\tindat err: %i\n"
++		"tx: %i B\toutdat: %i\toutdat err: %i\n"
++		"writes: %i\t\twrite err: %i\n"
++		"delayed writes: %i\tdelayed write err: %i\n",
++		atomic_read(&intfdata->stats.rx_bytes),	atomic_read(&intfdata->stats.indat_cb_cnt), atomic_read(&intfdata->stats.indat_cb_fail),
++		atomic_read(&intfdata->stats.tx_bytes), atomic_read(&intfdata->stats.outdat_cb_cnt), atomic_read(&intfdata->stats.outdat_cb_fail),
++		atomic_read(&intfdata->stats.write_cnt), atomic_read(&intfdata->stats.write_err),
++		atomic_read(&intfdata->stats.delayed_writes), atomic_read(&intfdata->stats.delayed_write_err)
++	);
++}
++
++/* Read only suspend status */
++static DEVICE_ATTR(suspend_status, S_IWUSR | S_IRUGO, show_suspend_status,
++							NULL);
++
++/* Read only statistics */
++static DEVICE_ATTR(stats, S_IWUSR | S_IRUGO, show_stats, NULL);
++
++static int sierra_create_sysfs_attrs(struct usb_serial_port *port)
++{
++	int result = 0;
++
++	result = device_create_file(&port->dev, &dev_attr_stats);
++	if (unlikely (result < 0)) 
++		return result;
++	return device_create_file(&port->dev, &dev_attr_suspend_status);
++}
++
++static int sierra_remove_sysfs_attrs(struct usb_serial_port *port)
++{
++	device_remove_file(&port->dev, &dev_attr_stats);
++	device_remove_file(&port->dev, &dev_attr_suspend_status);
++	return 0;
++}
++
+ static void sierra_outdat_callback(struct urb *urb)
+ {
+ 	struct usb_serial_port *port = urb->context;
+@@ -455,16 +600,20 @@
+ 	dev_dbg(&port->dev, "%s - port %d\n", __func__, port->number);
+ 	intfdata = port->serial->private;
+ 
+-	/* free up the transfer buffer, as usb_free_urb() does not do this */
+-	kfree(urb->transfer_buffer);
+ 	usb_autopm_put_interface_async(port->serial->interface);
+-	if (status)
++
++	atomic_inc(&intfdata->stats.outdat_cb_cnt);
++
++	if (status) {
+ 		dev_dbg(&port->dev, "%s - nonzero write bulk status "
+ 		    "received: %d\n", __func__, status);
++		atomic_inc(&intfdata->stats.outdat_cb_fail);
++	}
+ 
+ 	spin_lock(&portdata->lock);
+ 	--portdata->outstanding_urbs;
+ 	spin_unlock(&portdata->lock);
++
+ 	spin_lock(&intfdata->susp_lock);
+ 	--intfdata->in_flight;
+ 	spin_unlock(&intfdata->susp_lock);
+@@ -473,10 +622,11 @@
+ }
+ 
+ /* Write */
+-static int sierra_write(struct tty_struct *tty, struct usb_serial_port *port,
+-					const unsigned char *buf, int count)
++static int sierra_write(struct tty_struct *tty, 
++			struct usb_serial_port *port,
++			const unsigned char *buf, int count)
+ {
+-	struct sierra_port_private *portdata;
++	struct sierra_port_private *portdata = usb_get_serial_port_data(port);
+ 	struct sierra_intf_private *intfdata;
+ 	struct usb_serial *serial = port->serial;
+ 	unsigned long flags;
+@@ -489,46 +639,49 @@
+ 	if (count == 0)
+ 		return 0;
+ 
+-	portdata = usb_get_serial_port_data(port);
++	dev_dbg(&port->dev, "%s: write (%zu bytes)\n", __func__, writesize);
++
+ 	intfdata = serial->private;
+ 
+-	dev_dbg(&port->dev, "%s: write (%zd bytes)\n", __func__, writesize);
+ 	spin_lock_irqsave(&portdata->lock, flags);
+-	dev_dbg(&port->dev, "%s - outstanding_urbs: %d\n", __func__,
+-		portdata->outstanding_urbs);
+ 	if (portdata->outstanding_urbs > portdata->num_out_urbs) {
+ 		spin_unlock_irqrestore(&portdata->lock, flags);
+ 		dev_dbg(&port->dev, "%s - write limit hit\n", __func__);
+ 		return 0;
+ 	}
+ 	portdata->outstanding_urbs++;
+-	dev_dbg(&port->dev, "%s - 1, outstanding_urbs: %d\n", __func__,
+-		portdata->outstanding_urbs);
+ 	spin_unlock_irqrestore(&portdata->lock, flags);
+ 
+ 	retval = usb_autopm_get_interface_async(serial->interface);
+-	if (retval < 0) {
++	if (unlikely(retval < 0)) {
+ 		spin_lock_irqsave(&portdata->lock, flags);
+ 		portdata->outstanding_urbs--;
+ 		spin_unlock_irqrestore(&portdata->lock, flags);
+-		goto error_simple;
++		return retval;
+ 	}
+ 
+ 	buffer = kmalloc(writesize, GFP_ATOMIC);
+ 	if (!buffer) {
+ 		dev_err(&port->dev, "out of memory\n");
+-		retval = -ENOMEM;
+-		goto error_no_buffer;
++		spin_lock_irqsave(&portdata->lock, flags);
++		--portdata->outstanding_urbs;
++		spin_unlock_irqrestore(&portdata->lock, flags);
++		usb_autopm_put_interface_async(serial->interface);
++		return -ENOMEM;
+ 	}
+ 
+ 	urb = usb_alloc_urb(0, GFP_ATOMIC);
+ 	if (!urb) {
+ 		dev_err(&port->dev, "no more free urbs\n");
+-		retval = -ENOMEM;
+-		goto error_no_urb;
++		kfree(buffer);
++		spin_lock_irqsave(&portdata->lock, flags);
++		--portdata->outstanding_urbs;
++		spin_unlock_irqrestore(&portdata->lock, flags);
++		usb_autopm_put_interface_async(serial->interface);
++		return -ENOMEM;
+ 	}
+ 
+-	memcpy(buffer, buf, writesize);
++	memcpy(buffer, buf, writesize); 
+ 
+ 	usb_serial_debug_data(debug, &port->dev, __func__, writesize, buffer);
+ 
+@@ -537,69 +690,73 @@
+ 					  port->bulk_out_endpointAddress),
+ 			  buffer, writesize, sierra_outdat_callback, port);
+ 
+-	/* Handle the need to send a zero length packet */
+-	urb->transfer_flags |= URB_ZERO_PACKET;
++	/* Handle the need to send a zero length packet and release the
++	 * transfer buffer
++	 */
++	urb->transfer_flags |= (URB_ZERO_PACKET | URB_FREE_BUFFER);
+ 
+ 	spin_lock_irqsave(&intfdata->susp_lock, flags);
+ 
+ 	if (intfdata->suspended) {
+ 		usb_anchor_urb(urb, &portdata->delayed);
+ 		spin_unlock_irqrestore(&intfdata->susp_lock, flags);
+-		goto skip_power;
+-	} else {
+-		usb_anchor_urb(urb, &portdata->active);
++		/* release our reference to this urb, the USB core will 
++		 * eventually free it entirely */
++		usb_free_urb(urb);
++		return writesize;
+ 	}
++	usb_anchor_urb(urb, &portdata->active);
++
+ 	/* send it down the pipe */
+ 	retval = usb_submit_urb(urb, GFP_ATOMIC);
+ 	if (retval) {
+ 		usb_unanchor_urb(urb);
+ 		spin_unlock_irqrestore(&intfdata->susp_lock, flags);
++
+ 		dev_err(&port->dev, "%s - usb_submit_urb(write bulk) failed "
+ 			"with status = %d\n", __func__, retval);
+-		goto error;
++		usb_free_urb(urb);
++		spin_lock_irqsave(&portdata->lock, flags);
++		--portdata->outstanding_urbs;
++		spin_unlock_irqrestore(&portdata->lock, flags);
++		usb_autopm_put_interface_async(serial->interface);
++		atomic_inc(&intfdata->stats.write_err);
++		return retval;
+ 	} else {
+ 		intfdata->in_flight++;
+ 		spin_unlock_irqrestore(&intfdata->susp_lock, flags);
++		atomic_inc(&intfdata->stats.write_cnt);
++		atomic_add(writesize, &intfdata->stats.tx_bytes);
+ 	}
+-
+-skip_power:
+-	/* we are done with this urb, so let the host driver
+-	 * really free it when it is finished with it */
+-	usb_free_urb(urb);
++	/* release our reference to this urb, the USB core will eventually
++	 * free it entirely */
++	usb_free_urb(urb); 
+ 
+ 	return writesize;
+-error:
+-	usb_free_urb(urb);
+-error_no_urb:
+-	kfree(buffer);
+-error_no_buffer:
+-	spin_lock_irqsave(&portdata->lock, flags);
+-	--portdata->outstanding_urbs;
+-	dev_dbg(&port->dev, "%s - 2. outstanding_urbs: %d\n", __func__,
+-		portdata->outstanding_urbs);
+-	spin_unlock_irqrestore(&portdata->lock, flags);
+-	usb_autopm_put_interface_async(serial->interface);
+-error_simple:
+-	return retval;
+ }
+ 
+ static void sierra_indat_callback(struct urb *urb)
+ {
+ 	int err;
+ 	int endpoint;
+-	struct usb_serial_port *port;
++	struct usb_serial_port *port = urb->context;
+ 	struct tty_struct *tty;
++	struct sierra_intf_private *intfdata;
+ 	unsigned char *data = urb->transfer_buffer;
+ 	int status = urb->status;
+ 
+ 	endpoint = usb_pipeendpoint(urb->pipe);
+-	port = urb->context;
+ 
+ 	dev_dbg(&port->dev, "%s: %p\n", __func__, urb);
+ 
++	intfdata = port->serial->private;
++
++	atomic_inc(&intfdata->stats.indat_cb_cnt); /* indat calls */
++
+ 	if (status) {
+ 		dev_dbg(&port->dev, "%s: nonzero status: %d on"
+ 			" endpoint %02x\n", __func__, status, endpoint);
++		atomic_inc(&intfdata->stats.indat_cb_fail); /* indat fails */
+ 	} else {
+ 		if (urb->actual_length) {
+ 			tty = tty_port_tty_get(&port->port);
+@@ -609,6 +766,10 @@
+ 				tty_flip_buffer_push(tty);
+ 
+ 				tty_kref_put(tty);
++				/* tty invalid after this point */
++				/* rx'd bytes */
++				atomic_add(urb->actual_length,
++				&intfdata->stats.rx_bytes);
+ 				usb_serial_debug_data(debug, &port->dev,
+ 					__func__, urb->actual_length, data);
+ 			}
+@@ -619,13 +780,15 @@
+ 	}
+ 
+ 	/* Resubmit urb so we continue receiving */
+-	if (status != -ESHUTDOWN && status != -EPERM) {
++	if (status != -ESHUTDOWN && status != -ENOENT && status != -ENODEV) {
+ 		usb_mark_last_busy(port->serial->dev);
+ 		err = usb_submit_urb(urb, GFP_ATOMIC);
+-		if (err && err != -EPERM)
++		if (err && err != -ENODEV)
+ 			dev_err(&port->dev, "resubmit read urb failed."
+ 				"(%d)\n", err);
+ 	}
++
++	return;
+ }
+ 
+ static void sierra_instat_callback(struct urb *urb)
+@@ -636,31 +799,29 @@
+ 	struct sierra_port_private *portdata = usb_get_serial_port_data(port);
+ 	struct usb_serial *serial = port->serial;
+ 
+-	dev_dbg(&port->dev, "%s: urb %p port %p has data %p\n", __func__,
+-		urb, port, portdata);
++	dev_dbg(&port->dev, "%s: %p\n", __func__, urb);
+ 
+ 	if (status == 0) {
+ 		struct usb_ctrlrequest *req_pkt =
+ 				(struct usb_ctrlrequest *)urb->transfer_buffer;
+ 
+-		if (!req_pkt) {
+-			dev_dbg(&port->dev, "%s: NULL req_pkt\n",
+-				__func__);
+-			return;
+-		}
+-		if ((req_pkt->bRequestType == 0xA1) &&
+-				(req_pkt->bRequest == 0x20)) {
++		const u16 *sigp = (u16 *)(req_pkt + 1);
++		/* usb_ctrlrequest we parsed is followed by two bytes of data
++		 * make sure we received that many bytes
++		 */
++		if (urb->actual_length >= sizeof(*req_pkt) + sizeof(*sigp) &&
++			req_pkt->bRequestType == USB_REQUEST_TYPE_CLASS && 
++			req_pkt->bRequest == USB_REQUEST_IFACE) {
+ 			int old_dcd_state;
+-			unsigned char signals = *((unsigned char *)
+-					urb->transfer_buffer +
+-					sizeof(struct usb_ctrlrequest));
++			const u16 signals = get_unaligned_le16(sigp);
+ 			struct tty_struct *tty;
+ 
+-			dev_dbg(&port->dev, "%s: signal x%x\n", __func__,
++			dev_dbg(&port->dev, "%s: signal 0x%x\n", __func__,
+ 				signals);
+ 
+ 			old_dcd_state = portdata->dcd_state;
+-			portdata->cts_state = 1;
++			/* Note: CTS from modem is in reverse logic! */
++			portdata->cts_state = ((signals & 0x100) ? 0 : 1);
+ 			portdata->dcd_state = ((signals & 0x01) ? 1 : 0);
+ 			portdata->dsr_state = ((signals & 0x02) ? 1 : 0);
+ 			portdata->ri_state = ((signals & 0x08) ? 1 : 0);
+@@ -671,19 +832,19 @@
+ 				tty_hangup(tty);
+ 			tty_kref_put(tty);
+ 		} else {
+-			dev_dbg(&port->dev, "%s: type %x req %x\n",
+-				__func__, req_pkt->bRequestType,
+-				req_pkt->bRequest);
++			/* dump the data we don't understand to log */
++			usb_serial_debug_data(1, &port->dev, __func__,
++				urb->actual_length, urb->transfer_buffer);
+ 		}
+ 	} else
+ 		dev_dbg(&port->dev, "%s: error %d\n", __func__, status);
+ 
+ 	/* Resubmit urb so we continue receiving IRQ data */
+-	if (status != -ESHUTDOWN && status != -ENOENT) {
++	if (status != -ESHUTDOWN && status != -ENOENT && status != -ENODEV) {
+ 		usb_mark_last_busy(serial->dev);
+ 		urb->dev = serial->dev;
+ 		err = usb_submit_urb(urb, GFP_ATOMIC);
+-		if (err && err != -EPERM)
++		if (err && err != -ENODEV)
+ 			dev_err(&port->dev, "%s: resubmit intr urb "
+ 				"failed. (%d)\n", __func__, err);
+ 	}
+@@ -694,20 +855,21 @@
+ 	struct usb_serial_port *port = tty->driver_data;
+ 	struct sierra_port_private *portdata = usb_get_serial_port_data(port);
+ 	unsigned long flags;
++	int retval;
+ 
+ 	dev_dbg(&port->dev, "%s - port %d\n", __func__, port->number);
+ 
+ 	/* try to give a good number back based on if we have any free urbs at
+ 	 * this point in time */
++	retval = MAX_TRANSFER;
++
+ 	spin_lock_irqsave(&portdata->lock, flags);
+-	if (portdata->outstanding_urbs > (portdata->num_out_urbs * 2) / 3) {
+-		spin_unlock_irqrestore(&portdata->lock, flags);
+-		dev_dbg(&port->dev, "%s - write limit hit\n", __func__);
+-		return 0;
++	if (portdata->outstanding_urbs >= portdata->num_out_urbs) {
++		retval = 0;
+ 	}
+ 	spin_unlock_irqrestore(&portdata->lock, flags);
+ 
+-	return 2048;
++	return retval;
+ }
+ 
+ static void sierra_stop_rx_urbs(struct usb_serial_port *port)
+@@ -734,6 +896,7 @@
+ 		urb = portdata->in_urbs[i];
+ 		if (!urb)
+ 			continue;
++		urb->transfer_flags |= URB_FREE_BUFFER;
+ 		err = usb_submit_urb(urb, mem_flags);
+ 		if (err) {
+ 			dev_err(&port->dev, "%s: submit urb failed: %d\n",
+@@ -795,38 +958,31 @@
+ 
+ 	return urb;
+ }
+-
+ static void sierra_close(struct usb_serial_port *port)
+ {
+ 	int i;
++	struct urb	*urb;
+ 	struct usb_serial *serial = port->serial;
+ 	struct sierra_port_private *portdata;
+ 	struct sierra_intf_private *intfdata = port->serial->private;
+ 
+-
+ 	dev_dbg(&port->dev, "%s\n", __func__);
+ 	portdata = usb_get_serial_port_data(port);
+ 
+ 	portdata->rts_state = 0;
+ 	portdata->dtr_state = 0;
+ 
++	usb_autopm_get_interface(serial->interface);
++
+ 	if (serial->dev) {
+ 		mutex_lock(&serial->disc_mutex);
+-		if (!serial->disconnected) {
+-			serial->interface->needs_remote_wakeup = 0;
+-			/* odd error handling due to pm counters */
+-			if (!usb_autopm_get_interface(serial->interface))
+-				sierra_send_setup(port);
+-			else
+-				usb_autopm_get_interface_no_resume(serial->interface);
+-				
+-		}
++		if (!serial->disconnected)
++			sierra_send_setup(port);
+ 		mutex_unlock(&serial->disc_mutex);
+ 		spin_lock_irq(&intfdata->susp_lock);
+ 		portdata->opened = 0;
+ 		spin_unlock_irq(&intfdata->susp_lock);
+ 
+-
+ 		/* Stop reading urbs */
+ 		sierra_stop_rx_urbs(port);
+ 		/* .. and release them */
+@@ -834,6 +990,14 @@
+ 			sierra_release_urb(portdata->in_urbs[i]);
+ 			portdata->in_urbs[i] = NULL;
+ 		}
++		while((urb = usb_get_from_anchor(&portdata->delayed))) {
++			sierra_release_urb(urb);
++			usb_autopm_put_interface(serial->interface);
++		}
++		/* wait for active to finish */
++		usb_wait_anchor_empty_timeout(&portdata->active, 500);
++		usb_kill_anchored_urbs(&portdata->active);
++
+ 	}
+ }
+ 
+@@ -867,18 +1031,41 @@
+ 	usb_clear_halt(serial->dev,
+ 			usb_sndbulkpipe(serial->dev, endpoint) | USB_DIR_IN);
+ 
++	/* reset outstanding out urbs counter */
++	spin_lock_irq(&portdata->lock);
++	portdata->outstanding_urbs = 0;
++	spin_unlock_irq(&portdata->lock);
++
+ 	err = sierra_submit_rx_urbs(port, GFP_KERNEL);
+ 	if (err) {
+-		/* get rid of everything as in close */
+-		sierra_close(port);
+-		/* restore balance for autopm */
+-		if (!serial->disconnected)
++		/* do everything as in close() but do not call close() because
++		 * usbserial calls sierra_open() with mutex taken;
++		 * then if we call sierra_close() inside sierra_open() we
++		 * violate 'no nested mutexes' kernel condition
++		 */
++		portdata->rts_state = 0;
++		portdata->dtr_state = 0;
++		usb_autopm_get_interface(serial->interface);
++		/* Stop reading urbs */
++		sierra_stop_rx_urbs(port);
++		/* .. and release them */
++		for (i = 0; i < portdata->num_in_urbs; i++) {
++			sierra_release_urb(portdata->in_urbs[i]);
++			portdata->in_urbs[i] = NULL;
++		}
++		while((urb = usb_get_from_anchor(&portdata->delayed))) {
++			sierra_release_urb(urb);
+ 			usb_autopm_put_interface(serial->interface);
++		}
++		/* wait for active to finish */
++		usb_wait_anchor_empty_timeout(&portdata->active, 500);
++		usb_kill_anchored_urbs(&portdata->active);
++		/* restore balance for autopm */
++		usb_autopm_put_interface(serial->interface);
+ 		return err;
+ 	}
+ 	sierra_send_setup(port);
+ 
+-	serial->interface->needs_remote_wakeup = 1;
+ 	spin_lock_irq(&intfdata->susp_lock);
+ 	portdata->opened = 1;
+ 	spin_unlock_irq(&intfdata->susp_lock);
+@@ -887,7 +1074,6 @@
+ 	return 0;
+ }
+ 
+-
+ static void sierra_dtr_rts(struct usb_serial_port *port, int on)
+ {
+ 	struct usb_serial *serial = port->serial;
+@@ -907,11 +1093,13 @@
+ 
+ static int sierra_startup(struct usb_serial *serial)
+ {
+-	struct usb_serial_port *port;
+-	struct sierra_port_private *portdata;
++	struct usb_serial_port *port = NULL;
++	struct sierra_port_private *portdata = NULL;
+ 	struct sierra_iface_info *himemoryp = NULL;
+ 	int i;
+ 	u8 ifnum;
++	u16 fw_attr;
++	int result;
+ 
+ 	dev_dbg(&serial->dev->dev, "%s\n", __func__);
+ 
+@@ -922,19 +1110,30 @@
+ 	if (nmea)
+ 		sierra_vsc_set_nmea(serial->dev, 1);
+ 
+-	/* Now setup per port private data */
+-	for (i = 0; i < serial->num_ports; i++) {
+-		port = serial->port[i];
+-		portdata = kzalloc(sizeof(*portdata), GFP_KERNEL);
++	if (serial->num_ports) {
++		/* Note: One big piece of memory is allocated for all ports 
++		 * private data in one shot. This memory is split into equal 
++		 * pieces for each port. 
++		 */
++		portdata = (struct sierra_port_private *)kzalloc
++			(sizeof(*portdata) * serial->num_ports, GFP_KERNEL);
+ 		if (!portdata) {
+-			dev_dbg(&port->dev, "%s: kmalloc for "
+-				"sierra_port_private (%d) failed!\n",
+-				__func__, i);
++			dev_dbg(&serial->dev->dev, "%s: No memory!\n", __func__);
+ 			return -ENOMEM;
+ 		}
++	}
++
++	/* Now setup per port private data */
++	for (i = 0; i < serial->num_ports; i++, portdata++) {
++		port = serial->port[i];
++		/* Initialize selected members of private data because these
++		 * may be referred to right away */
+ 		spin_lock_init(&portdata->lock);
+ 		init_usb_anchor(&portdata->active);
+ 		init_usb_anchor(&portdata->delayed);
++
++		portdata->cts_state = 1;
++
+ 		ifnum = i;
+ 		/* Assume low memory requirements */
+ 		portdata->num_out_urbs = N_OUT_URB;
+@@ -959,12 +1158,29 @@
+ 				portdata->num_in_urbs  = N_IN_URB_HM;
+ 			}
+ 		}
+-		dev_dbg(&serial->dev->dev,
++		dev_dbg(&serial->dev->dev, 
+ 			"Memory usage (urbs) interface #%d, in=%d, out=%d\n",
+ 			ifnum,portdata->num_in_urbs, portdata->num_out_urbs );
+ 		/* Set the port private data pointer */
+ 		usb_set_serial_port_data(port, portdata);
+ 	}
++	serial->interface->needs_remote_wakeup = 1;
++
++	result = sierra_get_fw_attr(serial->dev, &fw_attr);
++	if (result == sizeof(fw_attr) && (fw_attr & SWI_FW_ATTR_PM_MASK) ) {
++		dev_info(&serial->dev->dev,
++			"APM supported, enabling autosuspend.\n");
++/******************************************************************************* 
++ * If you want the default /sys/bus/usb/devices/.../.../power/level to be forced
++ * to auto, the following needs to be compiled in.
++ */ 
++#ifdef POWER_LEVEL_AUTO
++		/* make power level default be 'auto' */
++		usb_enable_autosuspend(serial->dev);
++#endif
++	} else {
++		usb_disable_autosuspend(serial->dev);
++	}
+ 
+ 	return 0;
+ }
+@@ -973,19 +1189,29 @@
+ {
+ 	int i;
+ 	struct usb_serial_port *port;
+-	struct sierra_port_private *portdata;
++	struct sierra_intf_private *intfdata = serial->private;
+ 
+ 	dev_dbg(&serial->dev->dev, "%s\n", __func__);
+ 
++	if (serial->num_ports > 0) {
++		port = serial->port[0];
++		if (port)
++			/* Note: The entire piece of memory that was allocated 
++			 * in the startup routine can be released by passing
++			 * a pointer to the beginning of the piece.
++			 * This address corresponds to the address of the chunk
++			 * that was given to port 0.
++		 	 */
++			kfree(usb_get_serial_port_data(port));
++	}
++
+ 	for (i = 0; i < serial->num_ports; ++i) {
+ 		port = serial->port[i];
+ 		if (!port)
+ 			continue;
+-		portdata = usb_get_serial_port_data(port);
+-		if (!portdata)
+-			continue;
+-		kfree(portdata);
++		usb_set_serial_port_data(port, NULL);
+ 	}
++	kfree(intfdata);
+ }
+ 
+ #ifdef CONFIG_PM
+@@ -1007,21 +1233,21 @@
+ static int sierra_suspend(struct usb_serial *serial, pm_message_t message)
+ {
+ 	struct sierra_intf_private *intfdata;
+-	int b;
+ 
+-	if (message.event & PM_EVENT_AUTO) {
+-		intfdata = serial->private;
+-		spin_lock_irq(&intfdata->susp_lock);
+-		b = intfdata->in_flight;
++	dev_dbg(&serial->dev->dev, "%s\n", __func__);
++
++	intfdata = serial->private;
++	spin_lock_irq(&intfdata->susp_lock);
+ 
+-		if (b) {
++	if (message.event & PM_EVENT_AUTO) {
++		if (intfdata->in_flight) {
+ 			spin_unlock_irq(&intfdata->susp_lock);
+ 			return -EBUSY;
+-		} else {
+-			intfdata->suspended = 1;
+-			spin_unlock_irq(&intfdata->susp_lock);
+ 		}
+ 	}
++	intfdata->suspended = 1;
++	spin_unlock_irq(&intfdata->susp_lock);
++
+ 	stop_read_write_urbs(serial);
+ 
+ 	return 0;
+@@ -1035,22 +1261,35 @@
+ 	struct urb *urb;
+ 	int ec = 0;
+ 	int i, err;
++	int len;
++	int failed_submits;
+ 
++	dev_dbg(&serial->dev->dev, "%s\n", __func__);
++	
+ 	spin_lock_irq(&intfdata->susp_lock);
+ 	for (i = 0; i < serial->num_ports; i++) {
+ 		port = serial->port[i];
+ 		portdata = usb_get_serial_port_data(port);
+-
++		failed_submits = 0;
+ 		while ((urb = usb_get_from_anchor(&portdata->delayed))) {
+ 			usb_anchor_urb(urb, &portdata->active);
+ 			intfdata->in_flight++;
++			len = urb->transfer_buffer_length;
+ 			err = usb_submit_urb(urb, GFP_ATOMIC);
+ 			if (err < 0) {
+ 				intfdata->in_flight--;
+ 				usb_unanchor_urb(urb);
+-				usb_scuttle_anchored_urbs(&portdata->delayed);
+-				break;
++				failed_submits++;
++				atomic_inc(&intfdata->stats.delayed_write_err);
++				/* fix pm_usage_cnt */
++				usb_autopm_put_interface_async(
++					port->serial->interface);
++			} else {
++				atomic_inc(&intfdata->stats.delayed_writes);
++				atomic_add(len, &intfdata->stats.tx_bytes);
+ 			}
++			/* release urb - usb_get_from_anchor increased kref */
++			usb_free_urb(urb);
+ 		}
+ 
+ 		if (portdata->opened) {
+@@ -1058,12 +1297,24 @@
+ 			if (err)
+ 				ec++;
+ 		}
++		if (failed_submits) {
++			/* fix outstanding_urbs counter */
++			spin_lock(&portdata->lock); /* assuming irq disabled */
++			portdata->outstanding_urbs -= failed_submits;
++			spin_unlock(&portdata->lock);
++			/* unblock a writer */
++			usb_serial_port_softint(port);
++		}
+ 	}
+ 	intfdata->suspended = 0;
+ 	spin_unlock_irq(&intfdata->susp_lock);
+ 
+ 	return ec ? -EIO : 0;
+ }
++#else
++#define sierra_suspend NULL
++#define sierra_resume NULL
++#endif
+ 
+ static int sierra_reset_resume(struct usb_interface *intf)
+ {
+@@ -1071,11 +1322,6 @@
+ 	dev_err(&serial->dev->dev, "%s\n", __func__);
+ 	return usb_serial_resume(intf);
+ }
+-#else
+-#define sierra_suspend NULL
+-#define sierra_resume NULL
+-#define sierra_reset_resume NULL
+-#endif
+ 
+ static struct usb_driver sierra_driver = {
+ 	.name       = "sierra",
+@@ -1085,10 +1331,12 @@
+ 	.resume     = usb_serial_resume,
+ 	.reset_resume = sierra_reset_resume,
+ 	.id_table   = id_table,
+-	.no_dynamic_id = 	1,
+-	.supports_autosuspend =	1,
++
++	.no_dynamic_id        =	1,
++	.supports_autosuspend = 1,
+ };
+ 
++
+ static struct usb_serial_driver sierra_device = {
+ 	.driver = {
+ 		.owner =	THIS_MODULE,
+@@ -1109,9 +1357,12 @@
+ 	.tiocmset          = sierra_tiocmset,
+ 	.attach            = sierra_startup,
+ 	.release           = sierra_release,
+-	.suspend	   = sierra_suspend,
+-	.resume		   = sierra_resume,
++	.port_probe        = sierra_create_sysfs_attrs,
++	.port_remove       = sierra_remove_sysfs_attrs,
++	.suspend           = sierra_suspend,
++	.resume            = sierra_resume,
+ 	.read_int_callback = sierra_instat_callback,
++
+ };
+ 
+ /* Functions used by new usb-serial code. */
+@@ -1122,7 +1373,6 @@
+ 	if (retval)
+ 		goto failed_device_register;
+ 
+-
+ 	retval = usb_register(&sierra_driver);
+ 	if (retval)
+ 		goto failed_driver_register;
diff --git a/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39-at91-atmel-serial-uart0-rx-timer.patch b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39-at91-atmel-serial-uart0-rx-timer.patch
new file mode 100644
index 0000000..e482c78
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39-at91-atmel-serial-uart0-rx-timer.patch
@@ -0,0 +1,36 @@
+Index: linux-2.6.39.4/drivers/tty/serial/atmel_serial.c
+===================================================================
+--- linux-2.6.39.4.orig/drivers/tty/serial/atmel_serial.c	2013-03-05 11:13:21.334104152 -0600
++++ linux-2.6.39.4/drivers/tty/serial/atmel_serial.c	2013-03-05 11:13:42.299860530 -0600
+@@ -1510,7 +1510,14 @@
+ 			UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
+ 	} else if (atmel_use_dma_rx(port)) {
+ 		/* set UART timeout */
++#ifdef CONFIG_ARCH_AT91SAM9X5
++		/* DBGU, UART0, UART1 don't support RX TIMEOUT */
++		if (port->line == 0 ||
++			port->mapbase == AT91SAM9X5_BASE_UART0 ||
++			port->mapbase == AT91SAM9X5_BASE_UART1) {
++#else
+ 		if (port->line == 0) {
++#endif
+ 			setup_timer(&atmel_port->uart_timer,
+ 					atmel_uart_timer_callback,
+ 					(unsigned long)port);
+@@ -1585,8 +1592,15 @@
+ 
+ 	if (atmel_use_dma_rx(port)) {
+ 		atmel_rx_dma_release(atmel_port);
+-		if (port->line == 0)
++#ifdef CONFIG_ARCH_AT91SAM9X5
++		if (port->line == 0 ||
++			port->mapbase == AT91SAM9X5_BASE_UART0 ||
++			port->mapbase == AT91SAM9X5_BASE_UART1) {
++#else
++		if (port->line == 0) {
++#endif
+ 			del_timer_sync(&atmel_port->uart_timer);
++		}
+ 	}
+ 	if (atmel_use_dma_tx(port))
+ 		atmel_tx_dma_release(atmel_port);
diff --git a/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-at91sam9260-reset.patch b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-at91sam9260-reset.patch
new file mode 100644
index 0000000..af63d5c
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-at91sam9260-reset.patch
@@ -0,0 +1,26 @@
+Index: linux-2.6.39.4/arch/arm/mach-at91/at91sam9260.c
+===================================================================
+--- linux-2.6.39.4.orig/arch/arm/mach-at91/at91sam9260.c	2012-09-17 16:25:08.248303296 -0500
++++ linux-2.6.39.4/arch/arm/mach-at91/at91sam9260.c	2012-09-17 16:25:45.316033835 -0500
+@@ -310,6 +310,11 @@
+ 	iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
+ }
+ 
++static void at91sam9260_reset(void)
++{
++	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
++}
++
+ void __init at91sam9260_initialize(unsigned long main_clock)
+ {
+ 	/* Map peripherals */
+@@ -322,7 +327,8 @@
+ 	else
+ 		iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
+ 
+-	at91_arch_reset = at91sam9_alt_reset;
++	// jjg: use old reset routine, alt reset is not reliable
++	at91_arch_reset = at91sam9260_reset;
+ 	pm_power_off = at91sam9260_poweroff;
+ 	at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
+ 			| (1 << AT91SAM9260_ID_IRQ2);
diff --git a/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-atmel_serial_disable_hwhs.patch b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-atmel_serial_disable_hwhs.patch
new file mode 100644
index 0000000..88fd8d5
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-atmel_serial_disable_hwhs.patch
@@ -0,0 +1,32 @@
+Revert commit 8e706c4d0dab214c625a2df84a0ca69a76bae65d in linux-2.6:
+  avr32: add hardware handshake support to atmel_serial
+
+Reverting commit since it breaks hardware flow control for at91sam9g20
+
+diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
+index 9d948bc..b659f2c 100644
+--- a/drivers/tty/serial/atmel_serial.c
++++ b/drivers/tty/serial/atmel_serial.c
+@@ -1020,8 +1020,7 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
+ 
+ 	/* Get current mode register */
+ 	mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
+-					| ATMEL_US_NBSTOP | ATMEL_US_PAR
+-					| ATMEL_US_USMODE);
++					| ATMEL_US_NBSTOP | ATMEL_US_PAR);
+ 
+ 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
+ 	quot = uart_get_divisor(port, baud);
+@@ -1066,12 +1065,6 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
+ 	} else
+ 		mode |= ATMEL_US_PAR_NONE;
+ 
+-	/* hardware handshake (RTS/CTS) */
+-	if (termios->c_cflag & CRTSCTS)
+-		mode |= ATMEL_US_USMODE_HWHS;
+-	else
+-		mode |= ATMEL_US_USMODE_NORMAL;
+-
+ 	spin_lock_irqsave(&port->lock, flags);
+ 
+ 	port->read_status_mask = ATMEL_US_OVRE;
diff --git a/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-ledtrig-netdev.patch b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-ledtrig-netdev.patch
new file mode 100644
index 0000000..ab4c91b
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-ledtrig-netdev.patch
@@ -0,0 +1,488 @@
+Index: linux-2.6.39.4/drivers/leds/Kconfig
+===================================================================
+--- linux-2.6.39.4.orig/drivers/leds/Kconfig	2011-08-03 14:43:28.000000000 -0500
++++ linux-2.6.39.4/drivers/leds/Kconfig	2012-12-18 13:27:23.579027264 -0600
+@@ -417,6 +417,13 @@
+ 	  load average.
+ 	  If unsure, say Y.
+ 
++config LEDS_TRIGGER_NETDEV
++	tristate "LED Network Device Trigger"
++	depends on LEDS_TRIGGERS
++	help
++	  This allows LEDs to be controlled by Network Device activity.
++	  If unsure, say Y.
++
+ config LEDS_TRIGGER_BACKLIGHT
+ 	tristate "LED backlight Trigger"
+ 	depends on LEDS_TRIGGERS
+Index: linux-2.6.39.4/drivers/leds/Makefile
+===================================================================
+--- linux-2.6.39.4.orig/drivers/leds/Makefile	2011-08-03 14:43:28.000000000 -0500
++++ linux-2.6.39.4/drivers/leds/Makefile	2012-12-18 13:27:23.579027264 -0600
+@@ -50,6 +50,7 @@
+ obj-$(CONFIG_LEDS_TRIGGER_TIMER)	+= ledtrig-timer.o
+ obj-$(CONFIG_LEDS_TRIGGER_IDE_DISK)	+= ledtrig-ide-disk.o
+ obj-$(CONFIG_LEDS_TRIGGER_HEARTBEAT)	+= ledtrig-heartbeat.o
++obj-$(CONFIG_LEDS_TRIGGER_NETDEV)	+= ledtrig-netdev.o
+ obj-$(CONFIG_LEDS_TRIGGER_BACKLIGHT)	+= ledtrig-backlight.o
+ obj-$(CONFIG_LEDS_TRIGGER_GPIO)		+= ledtrig-gpio.o
+ obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON)	+= ledtrig-default-on.o
+Index: linux-2.6.39.4/drivers/leds/ledtrig-netdev.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.39.4/drivers/leds/ledtrig-netdev.c	2012-12-18 14:40:30.078735442 -0600
+@@ -0,0 +1,453 @@
++/*
++ * LED Kernel Netdev Trigger
++ *
++ * Toggles the LED to reflect the link and traffic state of a named net device
++ *
++ * Copyright 2007 Oliver Jowett <oliver@opencloud.com>
++ *
++ * Derived from ledtrig-timer.c which is:
++ *  Copyright 2005-2006 Openedhand Ltd.
++ *  Author: Richard Purdie <rpurdie@openedhand.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/jiffies.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/spinlock.h>
++#include <linux/device.h>
++#include <linux/sysdev.h>
++#include <linux/netdevice.h>
++#include <linux/timer.h>
++#include <linux/ctype.h>
++#include <linux/leds.h>
++#include <linux/version.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
++#include <net/net_namespace.h>
++#endif
++
++#include "leds.h"
++
++/*
++ * Configurable sysfs attributes:
++ *
++ * device_name - network device name to monitor
++ *
++ * interval - duration of LED blink, in milliseconds
++ *
++ * mode - either "none" (LED is off) or a space separated list of one or more of:
++ *   link: LED's normal state reflects whether the link is up (has carrier) or not
++ *   tx:   LED blinks on transmitted data
++ *   rx:   LED blinks on receive data
++ *
++ * Some suggestions:
++ *
++ *  Simple link status LED:
++ *  $ echo netdev >someled/trigger
++ *  $ echo eth0 >someled/device_name
++ *  $ echo link >someled/mode
++ *
++ *  Ethernet-style link/activity LED:
++ *  $ echo netdev >someled/trigger
++ *  $ echo eth0 >someled/device_name
++ *  $ echo "link tx rx" >someled/mode
++ *
++ *  Modem-style tx/rx LEDs:
++ *  $ echo netdev >led1/trigger
++ *  $ echo ppp0 >led1/device_name
++ *  $ echo tx >led1/mode
++ *  $ echo netdev >led2/trigger
++ *  $ echo ppp0 >led2/device_name
++ *  $ echo rx >led2/mode
++ *
++ */
++
++#define MODE_LINK 1
++#define MODE_TX   2
++#define MODE_RX   4
++
++struct led_netdev_data {
++	rwlock_t lock;
++
++	struct timer_list timer;
++	struct notifier_block notifier;
++
++	struct led_classdev *led_cdev;
++	struct net_device *net_dev;
++
++	char device_name[IFNAMSIZ];
++	unsigned interval;
++	unsigned mode;
++	unsigned link_up;
++	unsigned last_activity;
++};
++
++static void set_baseline_state(struct led_netdev_data *trigger_data)
++{
++	if ((trigger_data->mode & MODE_LINK) != 0 && trigger_data->link_up)
++		led_set_brightness(trigger_data->led_cdev, LED_FULL);
++	else
++		led_set_brightness(trigger_data->led_cdev, LED_OFF);
++
++	if ((trigger_data->mode & (MODE_TX | MODE_RX)) != 0 && trigger_data->link_up)
++		mod_timer(&trigger_data->timer, jiffies + trigger_data->interval);
++	else
++		del_timer(&trigger_data->timer);
++}
++
++static ssize_t led_device_name_show(struct device *dev,
++				    struct device_attribute *attr, char *buf)
++{
++	struct led_classdev *led_cdev = dev_get_drvdata(dev);
++	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
++
++	read_lock(&trigger_data->lock);
++	sprintf(buf, "%s\n", trigger_data->device_name);
++	read_unlock(&trigger_data->lock);
++
++	return strlen(buf) + 1;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
++extern struct net init_net;
++#endif
++
++static ssize_t led_device_name_store(struct device *dev,
++				     struct device_attribute *attr, const char *buf, size_t size)
++{
++	struct led_classdev *led_cdev = dev_get_drvdata(dev);
++	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
++
++	if (size < 0 || size >= IFNAMSIZ)
++		return -EINVAL;
++
++	write_lock(&trigger_data->lock);
++
++	strcpy(trigger_data->device_name, buf);
++	if (size > 0 && trigger_data->device_name[size-1] == '\n')
++		trigger_data->device_name[size-1] = 0;
++
++	if (trigger_data->device_name[0] != 0) {
++		/* check for existing device to update from */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
++		trigger_data->net_dev = dev_get_by_name(&init_net, trigger_data->device_name);
++#else
++		trigger_data->net_dev = dev_get_by_name(trigger_data->device_name);
++#endif
++		if (trigger_data->net_dev != NULL)
++			trigger_data->link_up = (dev_get_flags(trigger_data->net_dev) & IFF_LOWER_UP) != 0;
++		set_baseline_state(trigger_data); /* updates LEDs, may start timers */
++	}
++
++	write_unlock(&trigger_data->lock);
++	return size;
++}
++
++static DEVICE_ATTR(device_name, 0644, led_device_name_show, led_device_name_store);
++
++static ssize_t led_mode_show(struct device *dev,
++			     struct device_attribute *attr, char *buf)
++{
++	struct led_classdev *led_cdev = dev_get_drvdata(dev);
++	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
++
++	read_lock(&trigger_data->lock);
++
++	if (trigger_data->mode == 0) {
++		strcpy(buf, "none\n");
++	} else {
++		if (trigger_data->mode & MODE_LINK)
++			strcat(buf, "link ");
++		if (trigger_data->mode & MODE_TX)
++			strcat(buf, "tx ");
++		if (trigger_data->mode & MODE_RX)
++			strcat(buf, "rx ");
++		strcat(buf, "\n");
++	}
++
++	read_unlock(&trigger_data->lock);
++
++	return strlen(buf)+1;
++}
++
++static ssize_t led_mode_store(struct device *dev,
++			      struct device_attribute *attr, const char *buf, size_t size)
++{
++	struct led_classdev *led_cdev = dev_get_drvdata(dev);
++	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
++	char copybuf[1024];
++	int new_mode = -1;
++	char *p, *token;
++
++	/* take a copy since we don't want to trash the inbound buffer when using strsep */
++	strncpy(copybuf, buf, sizeof(copybuf));
++	copybuf[1023] = 0;
++	p = copybuf;
++
++	while ((token = strsep(&p, " \t\n")) != NULL) {
++		if (!*token)
++			continue;
++
++		if (new_mode == -1)
++			new_mode = 0;
++
++		if (!strcmp(token, "none"))
++			new_mode = 0;
++		else if (!strcmp(token, "tx"))
++			new_mode |= MODE_TX;
++		else if (!strcmp(token, "rx"))
++			new_mode |= MODE_RX;
++		else if (!strcmp(token, "link"))
++			new_mode |= MODE_LINK;
++		else
++			return -EINVAL;
++	}
++
++	if (new_mode == -1)
++		return -EINVAL;
++
++	write_lock(&trigger_data->lock);
++	trigger_data->mode = new_mode;
++	set_baseline_state(trigger_data);
++	write_unlock(&trigger_data->lock);
++
++	return size;
++}
++
++static DEVICE_ATTR(mode, 0644, led_mode_show, led_mode_store);
++
++static ssize_t led_interval_show(struct device *dev,
++				 struct device_attribute *attr, char *buf)
++{
++	struct led_classdev *led_cdev = dev_get_drvdata(dev);
++	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
++
++	read_lock(&trigger_data->lock);
++	sprintf(buf, "%u\n", jiffies_to_msecs(trigger_data->interval));
++	read_unlock(&trigger_data->lock);
++
++	return strlen(buf) + 1;
++}
++
++static ssize_t led_interval_store(struct device *dev,
++				  struct device_attribute *attr, const char *buf, size_t size)
++{
++	struct led_classdev *led_cdev = dev_get_drvdata(dev);
++	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
++	int ret = -EINVAL;
++	char *after;
++	unsigned long value = simple_strtoul(buf, &after, 10);
++	size_t count = after - buf;
++
++	if (*after && isspace(*after))
++		count++;
++
++	/* impose some basic bounds on the timer interval */
++	if (count == size && value >= 5 && value <= 10000) {
++		write_lock(&trigger_data->lock);
++		trigger_data->interval = msecs_to_jiffies(value);
++		set_baseline_state(trigger_data); // resets timer
++		write_unlock(&trigger_data->lock);
++		ret = count;
++	}
++
++	return ret;
++}
++
++static DEVICE_ATTR(interval, 0644, led_interval_show, led_interval_store);
++
++static int netdev_trig_notify(struct notifier_block *nb,
++			      unsigned long evt,
++			      void *dv)
++{
++	struct net_device *dev = dv;
++	struct led_netdev_data *trigger_data = container_of(nb, struct led_netdev_data, notifier);
++
++	if (evt != NETDEV_UP && evt != NETDEV_DOWN && evt != NETDEV_CHANGE && evt != NETDEV_REGISTER && evt != NETDEV_UNREGISTER)
++		return NOTIFY_DONE;
++
++	write_lock(&trigger_data->lock);
++
++	if (strcmp(dev->name, trigger_data->device_name))
++		goto done;
++
++	if (evt == NETDEV_REGISTER) {
++		if (trigger_data->net_dev != NULL)
++			dev_put(trigger_data->net_dev);
++		dev_hold(dev);
++		trigger_data->net_dev = dev;
++		trigger_data->link_up = 0;
++		goto done;
++	}
++
++	if (evt == NETDEV_UNREGISTER && trigger_data->net_dev != NULL) {
++		dev_put(trigger_data->net_dev);
++		trigger_data->net_dev = NULL;
++		goto done;
++	}
++
++	/* UP / DOWN / CHANGE */
++
++	trigger_data->link_up = (evt != NETDEV_DOWN && netif_carrier_ok(dev));
++	set_baseline_state(trigger_data);
++
++done:
++	write_unlock(&trigger_data->lock);
++	return NOTIFY_DONE;
++}
++
++/* here's the real work! */
++static void netdev_trig_timer(unsigned long arg)
++{
++	struct led_netdev_data *trigger_data = (struct led_netdev_data *)arg;
++	unsigned new_activity;
++	
++	struct rtnl_link_stats64 *dev_stats;
++	struct rtnl_link_stats64 temp;
++
++	write_lock(&trigger_data->lock);
++
++	if (!trigger_data->link_up || !trigger_data->net_dev || (trigger_data->mode & (MODE_TX | MODE_RX)) == 0) {
++		/* we don't need to do timer work, just reflect link state. */
++		led_set_brightness(trigger_data->led_cdev, ((trigger_data->mode & MODE_LINK) != 0 && trigger_data->link_up) ? LED_FULL : LED_OFF);
++		goto no_restart;
++	}
++
++	dev_stats = dev_get_stats(trigger_data->net_dev, &temp);
++	new_activity =
++		((trigger_data->mode & MODE_TX) ? dev_stats->tx_packets : 0) +
++		((trigger_data->mode & MODE_RX) ? dev_stats->rx_packets : 0);
++
++	if (trigger_data->mode & MODE_LINK) {
++		/* base state is ON (link present) */
++		/* if there's no link, we don't get this far and the LED is off */
++
++		/* OFF -> ON always */
++		/* ON -> OFF on activity */
++		if (trigger_data->led_cdev->brightness == LED_OFF) {
++			led_set_brightness(trigger_data->led_cdev, LED_FULL);
++		} else if (trigger_data->last_activity != new_activity) {
++			led_set_brightness(trigger_data->led_cdev, LED_OFF);
++		}
++	} else {
++		/* base state is OFF */
++		/* ON -> OFF always */
++		/* OFF -> ON on activity */
++		if (trigger_data->led_cdev->brightness == LED_FULL) {
++			led_set_brightness(trigger_data->led_cdev, LED_OFF);
++		} else if (trigger_data->last_activity != new_activity) {
++			led_set_brightness(trigger_data->led_cdev, LED_FULL);
++		}
++	}
++
++	trigger_data->last_activity = new_activity;
++	mod_timer(&trigger_data->timer, jiffies + trigger_data->interval);
++
++no_restart:
++	write_unlock(&trigger_data->lock);
++}
++
++static void netdev_trig_activate(struct led_classdev *led_cdev)
++{
++	struct led_netdev_data *trigger_data;
++	int rc;
++
++	trigger_data = kzalloc(sizeof(struct led_netdev_data), GFP_KERNEL);
++	if (!trigger_data)
++		return;
++
++	rwlock_init(&trigger_data->lock);
++
++	trigger_data->notifier.notifier_call = netdev_trig_notify;
++	trigger_data->notifier.priority = 10;
++
++	setup_timer(&trigger_data->timer, netdev_trig_timer, (unsigned long) trigger_data);
++
++	trigger_data->led_cdev = led_cdev;
++	trigger_data->net_dev = NULL;
++	trigger_data->device_name[0] = 0;
++
++	trigger_data->mode = 0;
++	trigger_data->interval = msecs_to_jiffies(50);
++	trigger_data->link_up = 0;
++	trigger_data->last_activity = 0;
++
++	led_cdev->trigger_data = trigger_data;
++
++	rc = device_create_file(led_cdev->dev, &dev_attr_device_name);
++	if (rc)
++		goto err_out;
++	rc = device_create_file(led_cdev->dev, &dev_attr_mode);
++	if (rc)
++		goto err_out_device_name;
++	rc = device_create_file(led_cdev->dev, &dev_attr_interval);
++	if (rc)
++		goto err_out_mode;
++
++	register_netdevice_notifier(&trigger_data->notifier);
++	return;
++
++err_out_mode:
++	device_remove_file(led_cdev->dev, &dev_attr_mode);
++err_out_device_name:
++	device_remove_file(led_cdev->dev, &dev_attr_device_name);
++err_out:
++	led_cdev->trigger_data = NULL;
++	kfree(trigger_data);
++}
++
++static void netdev_trig_deactivate(struct led_classdev *led_cdev)
++{
++	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
++
++	if (trigger_data) {
++		unregister_netdevice_notifier(&trigger_data->notifier);
++
++		device_remove_file(led_cdev->dev, &dev_attr_device_name);
++		device_remove_file(led_cdev->dev, &dev_attr_mode);
++		device_remove_file(led_cdev->dev, &dev_attr_interval);
++
++		write_lock(&trigger_data->lock);
++
++		if (trigger_data->net_dev) {
++			dev_put(trigger_data->net_dev);
++			trigger_data->net_dev = NULL;
++		}
++
++		write_unlock(&trigger_data->lock);
++
++		del_timer_sync(&trigger_data->timer);
++
++		kfree(trigger_data);
++	}
++}
++
++static struct led_trigger netdev_led_trigger = {
++	.name     = "netdev",
++	.activate = netdev_trig_activate,
++	.deactivate = netdev_trig_deactivate,
++};
++
++static int __init netdev_trig_init(void)
++{
++	return led_trigger_register(&netdev_led_trigger);
++}
++
++static void __exit netdev_trig_exit(void)
++{
++	led_trigger_unregister(&netdev_led_trigger);
++}
++
++module_init(netdev_trig_init);
++module_exit(netdev_trig_exit);
++
++MODULE_AUTHOR("Oliver Jowett <oliver@opencloud.com>");
++MODULE_DESCRIPTION("Netdev LED trigger");
++MODULE_LICENSE("GPL");
diff --git a/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-option-telit.patch b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-option-telit.patch
new file mode 100644
index 0000000..0a4baa1
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-option-telit.patch
@@ -0,0 +1,43 @@
+From 7204cf584836c24b4b06e4ad4a8e6bb8ea84908e Mon Sep 17 00:00:00 2001
+From: Daniele Palmas <dnlplm@gmail.com>
+Date: Wed, 29 Feb 2012 15:32:05 +0100
+Subject: [PATCH] USB: option driver: adding support for Telit CC864-SINGLE,
+ CC864-DUAL and DE910-DUAL modems
+
+Adding PID for Telit CC864-SINGLE, CC864-DUAL and DE910-DUAL
+modems
+
+Signed-off-by: Daniele Palmas <dnlplm@gmail.com>
+Cc: stable <stable@vger.kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/usb/serial/option.c |    6 ++++++
+ 1 files changed, 6 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
+index 005511b..f9b11fb 100644
+--- a/drivers/usb/serial/option.c
++++ b/drivers/usb/serial/option.c
+@@ -307,6 +307,9 @@ static void option_instat_callback(struct urb *urb);
+ #define TELIT_VENDOR_ID				0x1bc7
+ #define TELIT_PRODUCT_UC864E			0x1003
+ #define TELIT_PRODUCT_UC864G			0x1004
++#define TELIT_PRODUCT_CC864_DUAL		0x1005
++#define TELIT_PRODUCT_CC864_SINGLE		0x1006
++#define TELIT_PRODUCT_DE910_DUAL		0x1010
+ 
+ /* ZTE PRODUCTS */
+ #define ZTE_VENDOR_ID				0x19d2
+@@ -771,6 +774,9 @@ static const struct usb_device_id option_ids[] = {
+ 	{ USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6008) },
+ 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_UC864E) },
+ 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_UC864G) },
++	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_CC864_DUAL) },
++	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_CC864_SINGLE) },
++	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_DE910_DUAL) },
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_MF622, 0xff, 0xff, 0xff) }, /* ZTE WCDMA products */
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0002, 0xff, 0xff, 0xff),
+ 		.driver_info = (kernel_ulong_t)&net_intf1_blacklist },
+-- 
+1.7.7.6
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/defconfig b/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/defconfig
new file mode 100644
index 0000000..a3e1956
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/defconfig
@@ -0,0 +1,2295 @@
+#
+# Automatically generated make config: don't edit
+# Linux/arm 2.6.39.4 Kernel Configuration
+# Mon Sep 10 13:10:13 2012
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_VECTORS_BASE=0xffff0000
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+CONFIG_HAVE_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HAVE_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_SHOW=y
+# CONFIG_SPARSE_IRQ is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_PREEMPT_RCU=y
+# CONFIG_TINY_RCU is not set
+# CONFIG_TINY_PREEMPT_RCU is not set
+CONFIG_PREEMPT_RCU=y
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_NS is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CPUSETS is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_RESOURCE_COUNTERS is not set
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_BLK_CGROUP=y
+# CONFIG_DEBUG_BLK_CGROUP is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EXPERT is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_THROTTLING is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CFQ_GROUP_IOSCHED is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS4 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_VT8500 is not set
+CONFIG_HAVE_AT91_DATAFLASH_CARD=y
+CONFIG_HAVE_NAND_ATMEL_BUSWIDTH_16=y
+CONFIG_HAVE_AT91_USART3=y
+CONFIG_HAVE_AT91_USART4=y
+CONFIG_HAVE_AT91_USART5=y
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9G10 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+CONFIG_ARCH_AT91SAM9G20=y
+# CONFIG_ARCH_AT91SAM9G45 is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT572D940HF is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9G20 Board Type
+#
+CONFIG_MACH_AT91SAM9G20EK=y
+# CONFIG_MACH_AT91SAM9G20EK_2MMC is not set
+# CONFIG_MACH_CPU9G20 is not set
+# CONFIG_MACH_ACMENETUSFOXG20 is not set
+# CONFIG_MACH_PORTUXG20 is not set
+# CONFIG_MACH_STAMP9G20 is not set
+# CONFIG_MACH_PCONTROL_G20 is not set
+# CONFIG_MACH_GSIA18S is not set
+
+#
+# AT91SAM9260/AT91SAM9G20 boards
+#
+# CONFIG_MACH_SNAPPER_9260 is not set
+
+#
+# AT91 Board Options
+#
+CONFIG_MTD_AT91_DATAFLASH_CARD=y
+# CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16 is not set
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_SLOW_CLOCK=y
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+# CONFIG_GPIO_PCA953X is not set
+
+#
+# System MMU
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_USE_DOMAINS=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" quiet "
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_AUTO_ZRELADDR is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+# CONFIG_PM_RUNTIME is not set
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_NET_IPGRE=y
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+# CONFIG_DEFAULT_CUBIC is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+# CONFIG_NF_CT_PROTO_DCCP is not set
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+# CONFIG_NF_CONNTRACK_IRC is not set
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+# CONFIG_NF_CONNTRACK_SNMP is not set
+# CONFIG_NF_CONNTRACK_PPTP is not set
+# CONFIG_NF_CONNTRACK_SANE is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+# CONFIG_NF_CONNTRACK_TFTP is not set
+# CONFIG_NF_CT_NETLINK is not set
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_CONNMARK=y
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+# CONFIG_NETFILTER_XT_TARGET_HL is not set
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+CONFIG_NETFILTER_XT_MATCH_HL=y
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_SET is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=y
+# CONFIG_IP_NF_MATCH_AH is not set
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_NF_NAT_FTP=y
+# CONFIG_NF_NAT_IRC is not set
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+CONFIG_NF_NAT_H323=y
+# CONFIG_NF_NAT_SIP is not set
+CONFIG_IP_NF_MANGLE=y
+# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+# CONFIG_IP_NF_TARGET_ECN is not set
+# CONFIG_IP_NF_TARGET_TTL is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+# CONFIG_SCTP_HMAC_MD5 is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_BATMAN_ADV is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_ATH3K is not set
+CONFIG_BT_HCIUART_LL=y
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=m
+CONFIG_NL80211_TESTMODE=y
+CONFIG_CFG80211_DEVELOPER_WARNINGS=y
+CONFIG_CFG80211_REG_DEBUG=y
+# CONFIG_CFG80211_DEFAULT_PS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+CONFIG_MTD_M25P80=y
+# CONFIG_M25PXX_USE_FAST_READ is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+# CONFIG_ICS932S401 is not set
+CONFIG_ATMEL_SSC=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_HAVE_NET_MACB=y
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BCM63XX_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_FTMAC100 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_STMMAC_ETH is not set
+CONFIG_NETDEV_10000=y
+CONFIG_WLAN=y
+CONFIG_LIBERTAS_THINFIRM=m
+# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_AT76C50X_USB=m
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+# CONFIG_MAC80211_HWSIM is not set
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_HTC=m
+CONFIG_AR9170_USB=m
+CONFIG_AR9170_LEDS=y
+# CONFIG_CARL9170 is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_B43LEGACY_DMA_AND_PIO_MODE is not set
+# CONFIG_B43LEGACY_DMA_MODE is not set
+# CONFIG_B43LEGACY_PIO_MODE is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IWM is not set
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+# CONFIG_LIBERTAS_SDIO is not set
+# CONFIG_LIBERTAS_SPI is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_MESH is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+# CONFIG_RT2800USB_RT33XX is not set
+# CONFIG_RT2800USB_RT35XX is not set
+# CONFIG_RT2800USB_UNKNOWN is not set
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_HT=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+# CONFIG_RTL8192CU is not set
+# CONFIG_WL1251 is not set
+CONFIG_WL12XX_MENU=m
+CONFIG_WL12XX=m
+# CONFIG_WL12XX_HT is not set
+# CONFIG_WL12XX_SPI is not set
+CONFIG_WL12XX_SDIO=m
+# CONFIG_WL12XX_SDIO_TEST is not set
+CONFIG_WL12XX_PLATFORM_DATA=y
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+# CONFIG_USB_NET_CDC_EEM is not set
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=m
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+CONFIG_USB_SIERRA_NET=m
+# CONFIG_USB_VL600 is not set
+# CONFIG_WAN is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPTP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_HVC_DCC is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_BASIC_MMIO is not set
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9X_WATCHDOG=y
+# CONFIG_MAX63XX_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_RC_CORE=y
+CONFIG_LIRC=y
+# CONFIG_RC_MAP is not set
+# CONFIG_IR_NEC_DECODER is not set
+# CONFIG_IR_RC5_DECODER is not set
+# CONFIG_IR_RC6_DECODER is not set
+# CONFIG_IR_JVC_DECODER is not set
+# CONFIG_IR_SONY_DECODER is not set
+CONFIG_IR_RC5_SZ_DECODER=y
+CONFIG_IR_LIRC_CODEC=y
+# CONFIG_IR_IMON is not set
+# CONFIG_IR_MCEUSB is not set
+# CONFIG_IR_STREAMZAP is not set
+# CONFIG_RC_LOOPBACK is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=m
+
+#
+# Audio decoders
+#
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+
+#
+# RDS decoders
+#
+
+#
+# Video decoders
+#
+CONFIG_VIDEO_MT9V011=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_TVP5150=m
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_CX25840=m
+
+#
+# MPEG video encoders
+#
+CONFIG_VIDEO_CX2341X=m
+
+#
+# Video encoders
+#
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_TIMBERDALE is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+CONFIG_USB_M5602=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_GL860=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+# CONFIG_USB_GSPCA_KONICA is not set
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+# CONFIG_USB_GSPCA_NW80X is not set
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ905C=m
+# CONFIG_USB_GSPCA_SQ930X is not set
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_USBVISION=m
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_FB_CARMINE_DRAM_EVAL is not set
+# CONFIG_CARMINE_DRAM_CUSTOM is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_APPLE=m
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_WACOM is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SAMBA is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
+CONFIG_USB_SERIAL_ZIO=m
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+CONFIG_USB_SEVSEG=m
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+CONFIG_USB_LCD=m
+CONFIG_USB_LED=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_FUSB300 is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA_U2O is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_CI13XXX_PCI is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_EG20T is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_G_NCM is not set
+CONFIG_USB_GADGETFS=m
+# CONFIG_USB_FUNCTIONFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_MASS_STORAGE is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_NOKIA is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=m
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AT91=m
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_NFC_DEVICES is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_DRV_AT91SAM9_RTT=0
+CONFIG_RTC_DRV_AT91SAM9_GPBR=0
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+# CONFIG_LIS3L02DQ_BUF_RING_SW is not set
+# CONFIG_MACH_NO_WESTBRIDGE is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_EARLY_PRINTK is not set
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=m
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI2=m
+CONFIG_CRYPTO_AEAD2=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=m
+CONFIG_CRYPTO_HASH2=m
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=m
+CONFIG_CRYPTO_PCOMP2=m
+CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_MANAGER2=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=m
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_AVERAGE=y
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/linux-2.6.39.4-at91-mci-clock-debug.patch b/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/linux-2.6.39.4-at91-mci-clock-debug.patch
new file mode 100644
index 0000000..2554386
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/linux-2.6.39.4-at91-mci-clock-debug.patch
@@ -0,0 +1,14 @@
+Index: linux-2.6.39.4/drivers/mmc/host/at91_mci.c
+===================================================================
+--- linux-2.6.39.4.orig/drivers/mmc/host/at91_mci.c	2012-09-10 14:29:38.217293988 -0500
++++ linux-2.6.39.4/drivers/mmc/host/at91_mci.c	2012-09-10 14:41:35.352414089 -0500
+@@ -724,7 +724,8 @@
+ 		else
+ 			clkdiv = (at91_master_clock / ios->clock) / 2;
+ 
+-		pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
++		pr_info("MMC: requested clock: %ld\n", ios->clock);
++		pr_info("MMC: clkdiv = %d. mcck = %ld\n", clkdiv,
+ 			at91_master_clock / (2 * (clkdiv + 1)));
+ 	}
+ 	if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/linux-2.6.39.4-mach-at91-mt100eocg-pcie-dk.patch b/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/linux-2.6.39.4-mach-at91-mt100eocg-pcie-dk.patch
new file mode 100644
index 0000000..36da1a2
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/linux-2.6.39.4-mach-at91-mt100eocg-pcie-dk.patch
@@ -0,0 +1,406 @@
+Index: linux-2.6.39.4/arch/arm/mach-at91/at91sam9260_devices.c
+===================================================================
+--- linux-2.6.39.4.orig/arch/arm/mach-at91/at91sam9260_devices.c	2011-08-03 14:43:28.000000000 -0500
++++ linux-2.6.39.4/arch/arm/mach-at91/at91sam9260_devices.c	2012-09-10 12:33:08.656010481 -0500
+@@ -183,9 +183,9 @@
+ 		at91_set_B_periph(AT91_PIN_PA25, 0);	/* ERX2 */
+ 		at91_set_B_periph(AT91_PIN_PA26, 0);	/* ERX3 */
+ 		at91_set_B_periph(AT91_PIN_PA27, 0);	/* ERXCK */
+-		at91_set_B_periph(AT91_PIN_PA23, 0);	/* ETX2 */
+-		at91_set_B_periph(AT91_PIN_PA24, 0);	/* ETX3 */
+-		at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
++		at91_set_B_periph(AT91_PIN_PA10, 0);	/* ETX2 */
++		at91_set_B_periph(AT91_PIN_PA11, 0);	/* ETX3  */
++		/*at91_set_B_periph(AT91_PIN_PA22, 0);*/	/* ETXER */
+ 	}
+ 
+ 	eth_data = *data;
+@@ -571,7 +571,15 @@
+ 	.num_resources	= ARRAY_SIZE(spi1_resources),
+ };
+ 
+-static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
++static const unsigned spi1_standard_cs[7] = {
++	AT91_PIN_PB21,  // CS0 - external pin SPI_CS7
++	AT91_PIN_PC5,   // CS1 - GP output
++	AT91_PIN_PC4,   // CS2 - temp sensor
++	AT91_PIN_PC6,   // CS3 - unused/floating
++	AT91_PIN_PB12,  // CS4 - GP input
++	AT91_PIN_PB13,  // CS5 - external pin SPI_CS5
++	AT91_PIN_PB16   // CS6 - external pin SPI_CS6
++};
+ 
+ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+ {
+Index: linux-2.6.39.4/arch/arm/mach-at91/board-sam9g20ek.c
+===================================================================
+--- linux-2.6.39.4.orig/arch/arm/mach-at91/board-sam9g20ek.c	2011-08-03 14:43:28.000000000 -0500
++++ linux-2.6.39.4/arch/arm/mach-at91/board-sam9g20ek.c	2012-09-10 12:37:02.306005503 -0500
+@@ -30,6 +30,12 @@
+ #include <linux/regulator/machine.h>
+ #include <linux/regulator/fixed.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/i2c/at24.h>
++#include <linux/spi/eeprom.h>
++#include <linux/spi/flash.h>
++#include <linux/delay.h>
++#include <mach/at91_rtt.h>
++#include <linux/wl12xx.h>
+ 
+ #include <mach/hardware.h>
+ #include <asm/setup.h>
+@@ -59,9 +65,14 @@
+ 	return machine_is_at91sam9g20ek_2mmc() || (system_rev & HAVE_2MMC);
+ }
+ 
++#define WL12XX_ENABLE_PIN AT91_PIN_PB7
++
++static int i2c_present;
+ 
+ static void __init ek_map_io(void)
+ {
++	int tmp;
++
+ 	/* Initialize processor: 18.432 MHz crystal */
+ 	at91sam9260_initialize(18432000);
+ 
+@@ -76,12 +87,55 @@
+ 	/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+ 	at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+ 
++	/*
++	 * Reset any initiated i2c data transfers?
++	 */
++	at91_set_gpio_input(AT91_PIN_PA23, 0);
++	at91_set_gpio_output(AT91_PIN_PA24, 0);
++	for (tmp = 0; tmp < 11; tmp++) {
++		at91_set_gpio_value(AT91_PIN_PA24, 0);
++		udelay(20);
++		at91_set_gpio_value(AT91_PIN_PA24, 1);
++		udelay(20);
++	}
++	at91_set_gpio_input(AT91_PIN_PA24, 0);
++
++	/*
++	 * PA24 and PA23 are used as ID pins on MTCBA/MTCDP-0.0 and I2C pins on MTCDP-1.0.
++	 *
++	 *   MTCBA Rev. B: 0x01, C: 0x02, D: 0x03
++	 *   MTCDP Rev. A reads as 0x00 with TWCK and TWD pulled high
++	 *
++	 */
++	tmp = !at91_get_gpio_value(AT91_PIN_PA24) << 1 | !at91_get_gpio_value(AT91_PIN_PA23);
++
++	i2c_present = !tmp;
++
++	/*
++	 * The GPS receiver is either at US2 on MTCBA/MTCDP-0.0 and US3 on MTCDP-1.0.
++	 */
++	if (i2c_present) {
++		at91_register_uart(AT91SAM9260_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
++		printk(KERN_INFO "sam9g20: i2c available\n");
++	} else {
++		at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
++		printk(KERN_INFO "sam9g20: i2c not available\n");
++	}
++
+ 	/* set serial console to ttyS0 (ie, DBGU) */
+ 	at91_set_serial_console(0);
+ }
+ 
+ static void __init ek_init_irq(void)
+ {
++	/*
++	 * Ensure RTT interrupts are disabled
++	 */ 
++	u32 mr;
++	mr = __raw_readl(AT91_VA_BASE_SYS + AT91_RTT + AT91_RTT_MR);
++	__raw_writel(mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN),
++			AT91_VA_BASE_SYS + AT91_RTT + AT91_RTT_MR);
++
+ 	at91sam9260_init_interrupts(NULL);
+ }
+ 
+@@ -97,10 +151,37 @@
+  * USB Device port
+  */
+ static struct at91_udc_data __initdata ek_udc_data = {
+-	.vbus_pin	= AT91_PIN_PC5,
+-	.pullup_pin	= 0,		/* pull-up driven by UDC */
++	.vbus_pin	= AT91_PIN_PC12,
++	.pullup_pin	= 0,			/* pull-up driven by UDC */
++};
++
++
++#define MTS_EXT_AT25_TEST		0
++#if MTS_EXT_AT25_TEST
++static struct spi_eeprom at25040b = {
++	.byte_len	= SZ_4K / 8,
++	.name		= "at25040b",
++	.page_size	= 8,
++	.flags		= EE_ADDR1,
++};
++#endif
++
++#define MTS_EXT_STT25_TEST		0
++#if MTS_EXT_STT25_TEST
++static struct mtd_partition m25_partitions[] = {
++	{
++		.name	= "flash",
++		.offset	= 0x00000000,
++		.size	= MTDPART_SIZ_FULL,
++	},
+ };
+ 
++static struct flash_platform_data m25_spi_flash_data = {
++	.type		= "sst25vf080b",
++	.nr_parts	= ARRAY_SIZE(m25_partitions),
++	.parts		= m25_partitions,
++};
++#endif
+ 
+ /*
+  * SPI devices.
+@@ -122,6 +203,54 @@
+ 	},
+ #endif
+ #endif
++	{
++		.modalias	= "mts-io-sout",
++		.chip_select	= 0,
++		.bus_num	= 1,
++	},
++	{
++		.modalias	= "mts-io-board-temp",
++		.chip_select	= 2,
++		.bus_num	= 1,
++	},
++	{
++		.modalias	= "mts-io-dout",
++		.chip_select	= 1,
++		.bus_num	= 1,
++	},
++	{
++		.modalias	= "mts-io-din",
++		.chip_select	= 4,
++		.bus_num	= 1,
++	},
++#if MTS_EXT_AT25_TEST
++	{
++		.modalias	= "at25",
++		.platform_data	= &at25040b,
++		.max_speed_hz	= 20 * 1000 * 1000,
++		.bus_num	= 1,
++		.chip_select	= 5,
++		.mode		= SPI_MODE_0,
++	},
++	{
++		.modalias	= "at25",
++		.platform_data	= &at25040b,
++		.max_speed_hz	= 20 * 1000 * 1000,
++		.bus_num	= 1,
++		.chip_select	= 6,
++		.mode		= SPI_MODE_0,
++	},
++#endif
++#if MTS_EXT_STT25_TEST
++	{
++		.modalias	= "m25p80",
++		.platform_data	= &m25_spi_flash_data,
++		.irq		= NO_IRQ,
++		.max_speed_hz	= 33 * 1000 * 1000,
++		.bus_num	= 1,
++		.chip_select	= 5,
++	},
++#endif
+ };
+ 
+ 
+@@ -130,7 +259,7 @@
+  */
+ static struct at91_eth_data __initdata ek_macb_data = {
+ 	.phy_irq_pin	= AT91_PIN_PA7,
+-	.is_rmii	= 1,
++	.is_rmii	= 0,
+ };
+ 
+ static void __init ek_add_device_macb(void)
+@@ -146,18 +275,48 @@
+  */
+ static struct mtd_partition __initdata ek_nand_partition[] = {
+ 	{
+-		.name   = "Bootstrap",
+-		.offset = 0,
+-		.size   = 4 * SZ_1M,
++		.name	= "MTNCG-NANDFlash",
++		.offset	= 0,
++		.size	= 256*1024*1024,
++	},
++	{
++		.name	= "AT91Bootstrap",
++		.offset	= 0,
++		.size	= 128*1024,
++	},
++	{
++		.name	= "UBoot",
++		.offset	= 128*1024,
++		.size	= 256*1024,
++	},
++	{
++		.name	= "UBoot Config",
++		.offset	= 384*1024,
++		.size	= 128*1024,
++	},
++	{
++		.name	= "UBoot Redundant Config",
++		.offset	= 512*1024,
++		.size	= 128*1024,
++	},
++	{
++		.name	= "uImage",
++		.offset	= 640*1024,
++		.size	= 59*128*1024,
++	},
++	{
++		.name	= "Config",
++		.offset	= 64*128*1024,
++		.size	= 64*128*1024,
+ 	},
+ 	{
+-		.name	= "Partition 1",
+-		.offset	= MTDPART_OFS_NXTBLK,
+-		.size	= 60 * SZ_1M,
++		.name	= "Oem Config",
++		.offset	= 128*128*1024,
++		.size	= 64*128*1024,
+ 	},
+ 	{
+-		.name	= "Partition 2",
+-		.offset	= MTDPART_OFS_NXTBLK,
++		.name	= "Rootfs",
++		.offset	= 192*128*1024,
+ 		.size	= MTDPART_SIZ_FULL,
+ 	},
+ };
+@@ -228,10 +387,11 @@
+ 
+ };
+ #else
++/* MT100ECOG-PCIE-DK: SDIO for WLAN */
+ static struct at91_mmc_data __initdata ek_mmc_data = {
+ 	.slot_b		= 1,	/* Only one slot so use slot B */
+ 	.wire4		= 1,
+-	.det_pin	= AT91_PIN_PC9,
++	.det_pin	= AT91_PIN_PB20,
+ };
+ #endif
+ 
+@@ -252,15 +412,10 @@
+  * LEDs
+  */
+ static struct gpio_led ek_leds[] = {
+-	{	/* "bottom" led, green, userled1 to be defined */
+-		.name			= "ds5",
+-		.gpio			= AT91_PIN_PA6,
++	{	/* "status" led, green */
++		.name			= "status",
++		.gpio			= AT91_PIN_PA30,
+ 		.active_low		= 1,
+-		.default_trigger	= "none",
+-	},
+-	{	/* "power" led, yellow */
+-		.name			= "ds1",
+-		.gpio			= AT91_PIN_PA9,
+ 		.default_trigger	= "heartbeat",
+ 	}
+ };
+@@ -363,16 +518,60 @@
+ static void __init ek_add_regulators(void) {}
+ #endif
+ 
++uint8_t mts_id_eeprom[512];
++
++EXPORT_SYMBOL(mts_id_eeprom);
++
++static void mts_id_eeprom_load(struct memory_accessor *macc, void *context)
++{
++	int tmp;
++
++	memset(mts_id_eeprom, 0, sizeof(mts_id_eeprom));
++
++	tmp = macc->read(macc, mts_id_eeprom, 0, sizeof(mts_id_eeprom));
++	if (tmp != sizeof(mts_id_eeprom)) {
++		printk(KERN_ERR "sam9g20: id eeprom read failed: %d\n", tmp);
++	} else {
++		printk(KERN_INFO "sam9g20: read %d bytes from id eeprom\n", tmp);
++	}
++}
++
++static struct at24_platform_data at24c04_data = {
++	.byte_len	= SZ_4K / 8,
++	.page_size	= 16,
++	.setup		= mts_id_eeprom_load,
++};
++
+ 
+ static struct i2c_board_info __initdata ek_i2c_devices[] = {
+-        {
+-                I2C_BOARD_INFO("24c512", 0x50)
+-        },
+-        {
+-                I2C_BOARD_INFO("wm8731", 0x1b)
+-        },
++	{
++		I2C_BOARD_INFO("24c04", 0x56),
++		.platform_data = &at24c04_data,
++	},
+ };
+ 
++/* MT100EOCG-PCIE-DK: WL12XX support */
++static void wl12xx_enable(int enable)
++{
++	if (enable) {
++       	 	at91_set_gpio_output_with_pullup(WL12XX_ENABLE_PIN, 0, 0);
++       	 	msleep(10);
++        	at91_set_gpio_output_with_pullup(WL12XX_ENABLE_PIN, 1, 0);
++        	msleep(100);
++                printk(KERN_INFO "WLAN Enabled\n");
++        }
++        else {
++       	 	at91_set_gpio_output_with_pullup(WL12XX_ENABLE_PIN, 0, 0);
++       	 	msleep(10);
++                printk(KERN_INFO "WLAN Disabled\n");
++        }
++};
++
++static struct wl12xx_platform_data at91_wl12xx_wlan_data __initdata = {
++	.irq = AT91_PIN_PB19,
++	.board_ref_clock = WL12XX_REFCLOCK_38,
++	.set_power = wl12xx_enable,
++};
+ 
+ static void __init ek_board_init(void)
+ {
+@@ -401,7 +600,22 @@
+ 	/* PCK0 provides MCLK to the WM8731 */
+ 	at91_set_B_periph(AT91_PIN_PC1, 0);
+ 	/* SSC (for WM8731) */
+-	at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
++	/* at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); */
++
++	/* MT100ECOG-PCIE-DK
++	 * configure the WLAN_IRQ for input
++	 */
++	at91_set_gpio_input(at91_wl12xx_wlan_data.irq, 0);
++	at91_set_deglitch(at91_wl12xx_wlan_data.irq, 1);
++
++	if (wl12xx_set_platform_data(&at91_wl12xx_wlan_data))
++		pr_err("error setting wl12xx data\n");
++
++	/* configure WLAN_EN as output and enable chip */
++	at91_set_gpio_output_with_pullup(WL12XX_ENABLE_PIN, 0, 0);
++	mdelay(10);
++	at91_set_gpio_output_with_pullup(WL12XX_ENABLE_PIN, 1, 0);
++	mdelay(100);
+ }
+ 
+ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/linux-2.6.39.4-mmc-core-maxclock.patch b/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/linux-2.6.39.4-mmc-core-maxclock.patch
new file mode 100644
index 0000000..9f8303a
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mt100eocg-pcie-dk/linux-2.6.39.4-mmc-core-maxclock.patch
@@ -0,0 +1,28 @@
+Index: linux-2.6.39.4/drivers/mmc/core/core.c
+===================================================================
+--- linux-2.6.39.4.orig/drivers/mmc/core/core.c	2011-08-03 14:43:28.000000000 -0500
++++ linux-2.6.39.4/drivers/mmc/core/core.c	2012-09-12 10:45:57.246686939 -0500
+@@ -46,7 +46,10 @@
+  * So we allow it it to be disabled.
+  */
+ int use_spi_crc = 1;
++/* MTPCIE: default max clock to 13MHz */
++int max_clock = 13000000;
+ module_param(use_spi_crc, bool, 0);
++module_param(max_clock, int, 0);
+ 
+ /*
+  * We normally treat cards as removed during suspend if they are not
+@@ -628,6 +631,12 @@
+ 
+ 	if (ios->clock > 0)
+ 		mmc_set_ungated(host);
++
++	if (max_clock > 0 && ios->clock > max_clock) {
++		ios->clock = max_clock;
++		printk("mmc: forcing clock to %u\n", ios->clock);
++	}
++
+ 	host->ops->set_ios(host, ios);
+ }
+ 
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/defconfig b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/defconfig
new file mode 100644
index 0000000..0afdbee
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/defconfig
@@ -0,0 +1,2328 @@
+#
+# Automatically generated make config: don't edit
+# Linux/arm 2.6.39.4 Kernel Configuration
+# Tue Feb 12 17:21:58 2013
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_VECTORS_BASE=0xffff0000
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+CONFIG_HAVE_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HAVE_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_SHOW=y
+# CONFIG_SPARSE_IRQ is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TINY_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_NS is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CPUSETS is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_RESOURCE_COUNTERS is not set
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_BLK_CGROUP=y
+# CONFIG_DEBUG_BLK_CGROUP is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_THROTTLING is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CFQ_GROUP_IOSCHED is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS4 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_VT8500 is not set
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9G10 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91SAM9G20 is not set
+# CONFIG_ARCH_AT91SAM9G45 is not set
+CONFIG_ARCH_AT91SAM9X5=y
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT572D940HF is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9x5 Series Board Type
+#
+CONFIG_MACH_AT91SAM9X5EK=y
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_SLOW_CLOCK=y
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_GPIO_PCA953X is not set
+
+#
+# System MMU
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_USE_DOMAINS=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_LEDS=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+# CONFIG_SECCOMP is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" quiet "
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_AUTO_ZRELADDR=y
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+# CONFIG_PM_RUNTIME is not set
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_NET_IPGRE=y
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+# CONFIG_NF_CT_PROTO_DCCP is not set
+CONFIG_NF_CT_PROTO_GRE=y
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+# CONFIG_NF_CONNTRACK_IRC is not set
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+# CONFIG_NF_CONNTRACK_SNMP is not set
+CONFIG_NF_CONNTRACK_PPTP=y
+# CONFIG_NF_CONNTRACK_SANE is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+# CONFIG_NF_CONNTRACK_TFTP is not set
+# CONFIG_NF_CT_NETLINK is not set
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_CONNMARK=y
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+# CONFIG_NETFILTER_XT_TARGET_HL is not set
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+CONFIG_NETFILTER_XT_MATCH_HL=y
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+CONFIG_NETFILTER_XT_MATCH_RECENT=y
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_SET is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=y
+# CONFIG_IP_NF_MATCH_AH is not set
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_FTP=y
+# CONFIG_NF_NAT_IRC is not set
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+# CONFIG_NF_NAT_SIP is not set
+CONFIG_IP_NF_MANGLE=y
+# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+# CONFIG_IP_NF_TARGET_ECN is not set
+# CONFIG_IP_NF_TARGET_TTL is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_L2TP=y
+# CONFIG_L2TP_V3 is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFB is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=m
+# CONFIG_BT_HCIUART_H4 is not set
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_ATH3K is not set
+CONFIG_BT_HCIUART_LL=y
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_ATH3K is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_HAS_RC=y
+# CONFIG_MAC80211_RC_PID is not set
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+CONFIG_ATMEL_TCB_CLKSRC_32BIT=y
+# CONFIG_ICS932S401 is not set
+CONFIG_ATMEL_SSC=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_HAVE_NET_MACB=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BCM63XX_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_FTMAC100 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_AT76C50X_USB=m
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+# CONFIG_MAC80211_HWSIM is not set
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_HTC=m
+# CONFIG_AR9170_USB is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IWM is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_P54_COMMON is not set
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+# CONFIG_RT2800USB_UNKNOWN is not set
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_HT=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+CONFIG_RTL8192C_COMMON=m
+# CONFIG_WL1251 is not set
+CONFIG_WL12XX_MENU=m
+CONFIG_WL12XX=m
+# CONFIG_WL12XX_HT is not set
+# CONFIG_WL12XX_SPI is not set
+CONFIG_WL12XX_SDIO=m
+CONFIG_WL12XX_SDIO_TEST=m
+CONFIG_WL12XX_PLATFORM_DATA=y
+# CONFIG_ZD1211RW is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+# CONFIG_WAN is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPTP is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_DMA=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_HVC_DCC is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_ATMEL_DMA=y
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_BASIC_MMIO is not set
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9X_WATCHDOG=y
+# CONFIG_MAX63XX_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=m
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_AT91SAM9X5 is not set
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+
+#
+# Audio decoders
+#
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+
+#
+# RDS decoders
+#
+
+#
+# Video decoders
+#
+CONFIG_VIDEO_SAA711X=m
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_CX25840=m
+
+#
+# MPEG video encoders
+#
+CONFIG_VIDEO_CX2341X=m
+
+#
+# Video encoders
+#
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_TIMBERDALE is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+CONFIG_USB_M5602=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_GL860=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+# CONFIG_USB_GSPCA_KONICA is not set
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+# CONFIG_USB_GSPCA_NW80X is not set
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ905C=m
+# CONFIG_USB_GSPCA_SQ930X is not set
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_USBVISION=m
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
+
+#
+# Graphics support
+#
+CONFIG_HAVE_FB_ATMEL=y
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+# CONFIG_HID_PID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_WACOM is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+# CONFIG_USB_SERIAL_SAFE is not set
+CONFIG_USB_SERIAL_SAMBA=m
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
+CONFIG_USB_SERIAL_ZIO=m
+CONFIG_USB_SERIAL_SSU100=m
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+CONFIG_USB_SEVSEG=m
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+CONFIG_USB_LCD=m
+CONFIG_USB_LED=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+CONFIG_USB_CYTHERM=m
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_USB_ATMEL_USBA=m
+# CONFIG_USB_GADGET_FUSB300 is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA_U2O is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+# CONFIG_USB_G_NCM is not set
+CONFIG_USB_GADGETFS=m
+# CONFIG_USB_FUNCTIONFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+CONFIG_MMC_ATMELMCI=m
+# CONFIG_MMC_ATMELMCI_DMA is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_NETDEV=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_NFC_DEVICES is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91RM9200=y
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+# CONFIG_DW_DMAC is not set
+CONFIG_AT_HDMAC=y
+# CONFIG_TIMB_DMA is not set
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_CEPH_FS is not set
+CONFIG_CIFS=y
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_EARLY_PRINTK is not set
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+# CONFIG_CRYPTO_CAMELLIA is not set
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SALSA20=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_AVERAGE=y
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-at91sam9_wdt-10second-timeout.patch b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-at91sam9_wdt-10second-timeout.patch
new file mode 100644
index 0000000..90c906c
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-at91sam9_wdt-10second-timeout.patch
@@ -0,0 +1,14 @@
+Index: linux-2.6.39.4/drivers/watchdog/at91sam9_wdt.c
+===================================================================
+--- linux-2.6.39.4.orig/drivers/watchdog/at91sam9_wdt.c	2013-01-16 14:33:37.565560189 -0600
++++ linux-2.6.39.4/drivers/watchdog/at91sam9_wdt.c	2013-01-16 14:34:26.531727425 -0600
+@@ -43,7 +43,8 @@
+ #define ticks_to_ms(t)	(((t + 1) * 1000) >> 8)
+ 
+ /* Hardware timeout in seconds */
+-#define WDT_HW_TIMEOUT 2
++/* MTR: use longer timeout */
++#define WDT_HW_TIMEOUT 10
+ 
+ /* Timer heartbeat (500ms) */
+ #define WDT_TIMEOUT	(HZ/2)
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-at91sam9x5-extreset.patch b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-at91sam9x5-extreset.patch
new file mode 100644
index 0000000..31b7441
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-at91sam9x5-extreset.patch
@@ -0,0 +1,16 @@
+Index: linux-2.6.39.4/arch/arm/mach-at91/at91sam9x5.c
+===================================================================
+--- linux-2.6.39.4.orig/arch/arm/mach-at91/at91sam9x5.c	2012-06-25 17:00:27.060489533 -0500
++++ linux-2.6.39.4/arch/arm/mach-at91/at91sam9x5.c	2012-06-25 17:00:33.051404086 -0500
+@@ -330,7 +330,10 @@
+ 
+ static void at91sam9x5_reset(void)
+ {
+-	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
++	// MTR: generate an external reset (assert the NRST pin) on soft reset
++	// set reset duration to 125 ms --> set ERSTL to 0xb (0xb = 11 = 2^12 slow clock cycles = 4096 clocks = 125 ms)
++	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | (0xb << 8));
++	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST | AT91_RSTC_EXTRST);
+ }
+ 
+ static void at91sam9x5_poweroff(void)
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-atmel-mci-force-detect.patch b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-atmel-mci-force-detect.patch
new file mode 100644
index 0000000..d59a7cc
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-atmel-mci-force-detect.patch
@@ -0,0 +1,30 @@
+Index: linux-2.6.39.4/drivers/mmc/host/atmel-mci.c
+===================================================================
+--- linux-2.6.39.4.orig/drivers/mmc/host/atmel-mci.c	2012-05-10 11:44:02.069173755 -0500
++++ linux-2.6.39.4/drivers/mmc/host/atmel-mci.c	2012-05-11 11:21:42.119198300 -0500
+@@ -1059,6 +1059,10 @@
+ 		dev_dbg(&mmc->class_dev, "card is %spresent\n",
+ 				present ? "" : "not ");
+ 	}
++	else {
++		// jjg - assume card is present if detect pin is unset
++		present = 1;
++	}
+ 
+ 	return present;
+ }
+@@ -1655,8 +1659,12 @@
+ 		}
+ 	}
+ 
+-	if (!gpio_is_valid(slot->detect_pin))
+-		mmc->caps |= MMC_CAP_NEEDS_POLL;
++	// jjg - if detect pin isn't set, don't poll -- just assume device
++	// is there and mark it non-removable
++	if (!gpio_is_valid(slot->detect_pin)) {
++		dev_info(&host->pdev->dev,"No detect pin, marking non-removable and assuming device is present\n");
++		mmc->caps |= MMC_CAP_NONREMOVABLE;
++	}
+ 
+ 	if (gpio_is_valid(slot->wp_pin)) {
+ 		if (gpio_request(slot->wp_pin, "mmc_wp")) {
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-atmel-mci-module-alias.patch b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-atmel-mci-module-alias.patch
new file mode 100644
index 0000000..8081bb9
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-atmel-mci-module-alias.patch
@@ -0,0 +1,9 @@
+Index: linux-2.6.39.4/drivers/mmc/host/atmel-mci.c
+===================================================================
+--- linux-2.6.39.4.orig/drivers/mmc/host/atmel-mci.c	2013-03-08 10:25:21.024073265 -0600
++++ linux-2.6.39.4/drivers/mmc/host/atmel-mci.c	2013-03-08 10:25:25.523819243 -0600
+@@ -1973,3 +1973,4 @@
+ MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
+ MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
+ MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:atmel_mci");
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-cdc-acm-ignore-exar-devices.patch b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-cdc-acm-ignore-exar-devices.patch
new file mode 100644
index 0000000..5f9d8f7
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-cdc-acm-ignore-exar-devices.patch
@@ -0,0 +1,45 @@
+Index: linux-2.6.39.4/drivers/usb/class/cdc-acm.c
+===================================================================
+--- linux-2.6.39.4.orig/drivers/usb/class/cdc-acm.c	2013-02-19 09:22:57.860051682 -0600
++++ linux-2.6.39.4/drivers/usb/class/cdc-acm.c	2013-02-19 09:30:35.274209660 -0600
+@@ -963,6 +963,12 @@
+ 		goto skip_normal_probe;
+ 	}
+ 
++	/* ignore devices we don't want to support */
++	if (quirks == IGNORE_DEVICE) {
++		dev_dbg(&intf->dev, "Ignoring device\n");
++		return -ENODEV;
++	}
++
+ 	/* normal probing*/
+ 	if (!buffer) {
+ 		dev_err(&intf->dev, "Weird descriptor references\n");
+@@ -1633,6 +1639,18 @@
+ 	.driver_info = NO_DATA_INTERFACE,
+ 	},
+ 
++	/* Ignore Exar XR21V141X usb serial chips
++	 * This elminates conflicting with the Exar vizzini driver */
++	{ USB_DEVICE(0x04e2, 0x1410),
++	.driver_info = IGNORE_DEVICE,
++	},
++	{ USB_DEVICE(0x04e2, 0x1412),
++	.driver_info = IGNORE_DEVICE,
++	},
++	{ USB_DEVICE(0x04e2, 0x1414),
++	.driver_info = IGNORE_DEVICE,
++	},
++
+ 	/* control interfaces without any protocol set */
+ 	{ USB_INTERFACE_INFO(USB_CLASS_COMM, USB_CDC_SUBCLASS_ACM,
+ 		USB_CDC_PROTO_NONE) },
+Index: linux-2.6.39.4/drivers/usb/class/cdc-acm.h
+===================================================================
+--- linux-2.6.39.4.orig/drivers/usb/class/cdc-acm.h	2013-02-19 09:22:54.860050647 -0600
++++ linux-2.6.39.4/drivers/usb/class/cdc-acm.h	2013-02-19 09:24:00.856126438 -0600
+@@ -138,3 +138,4 @@
+ #define NO_CAP_LINE			4
+ #define NOT_A_MODEM			8
+ #define NO_DATA_INTERFACE		16
++#define IGNORE_DEVICE			32
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-macb-force-link.patch b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-macb-force-link.patch
new file mode 100644
index 0000000..2ef39a9
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-macb-force-link.patch
@@ -0,0 +1,87 @@
+Index: linux-2.6.39.4/drivers/net/macb.c
+===================================================================
+--- linux-2.6.39.4.orig/drivers/net/macb.c	2011-08-03 14:43:28.000000000 -0500
++++ linux-2.6.39.4/drivers/net/macb.c	2013-03-12 15:31:34.710687318 -0500
+@@ -193,7 +193,9 @@
+ 	struct eth_platform_data *pdata;
+ 	int ret;
+ 
+-	phydev = phy_find_first(bp->mii_bus);
++	// MTR2: use phy 5
++	//phydev = phy_find_first(bp->mii_bus);
++	phydev = bp->mii_bus->phy_map[5];
+ 	if (!phydev) {
+ 		printk (KERN_ERR "%s: no PHY found\n", dev->name);
+ 		return -1;
+@@ -203,14 +205,19 @@
+ 	/* TODO : add pin_irq */
+ 
+ 	/* attach the mac to the phy */
+-	ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
++	// MTR2: attach directly to phy and set link state ourselves
++	//ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
++	phy_attach(dev, dev_name(&phydev->dev), 0,
+ 				 pdata && pdata->is_rmii ?
+ 				 PHY_INTERFACE_MODE_RMII :
+ 				 PHY_INTERFACE_MODE_MII);
++
++	/*
+ 	if (ret) {
+ 		printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
+ 		return ret;
+ 	}
++	*/
+ 
+ 	/* mask with MAC supported features */
+ 	phydev->supported &= PHY_BASIC_FEATURES;
+@@ -942,6 +949,7 @@
+ {
+ 	struct macb *bp = netdev_priv(dev);
+ 	int err;
++	unsigned long flags;
+ 
+ 	dev_dbg(&bp->pdev->dev, "open\n");
+ 
+@@ -966,8 +974,19 @@
+ 	macb_init_hw(bp);
+ 
+ 	/* schedule a link state check */
+-	phy_start(bp->phy_dev);
++	// MTR2: disable link updates
++	//phy_start(bp->phy_dev);
++
++	// MTR2: force link up, 100MB, full duplex
++	printk(KERN_INFO "macb: forcing link to 100, full\n");
++	bp->phy_dev->link = 1;
++	bp->phy_dev->speed = SPEED_100;
++	bp->phy_dev->duplex = 1;
++	macb_handle_link_change(bp->dev);
+ 
++	spin_lock_irqsave(&bp->lock, flags);
++	netif_carrier_on(dev);
++	spin_unlock_irqrestore(&bp->lock, flags);
+ 	netif_start_queue(dev);
+ 
+ 	return 0;
+@@ -981,8 +1000,19 @@
+ 	netif_stop_queue(dev);
+ 	napi_disable(&bp->napi);
+ 
+-	if (bp->phy_dev)
+-		phy_stop(bp->phy_dev);
++	// MTR2: disabled since we didn't call phy_start
++	//if (bp->phy_dev)
++	//	phy_stop(bp->phy_dev);
++
++	// MTR2: set link down manually
++	if (bp->phy_dev) {
++		printk(KERN_INFO "macb: forcing link down\n");
++		bp->phy_dev->link = 0;
++		bp->phy_dev->speed = 0;
++		bp->phy_dev->duplex = -1;
++	}
++
++	macb_handle_link_change(bp->dev);
+ 
+ 	spin_lock_irqsave(&bp->lock, flags);
+ 	macb_reset_hw(bp);
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-mach-at91-mtocgd3.patch b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-mach-at91-mtocgd3.patch
new file mode 100644
index 0000000..6fd737b
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-mach-at91-mtocgd3.patch
@@ -0,0 +1,425 @@
+Index: linux-2.6.39.4/arch/arm/mach-at91/board-sam9x5cm.c
+===================================================================
+--- linux-2.6.39.4.orig/arch/arm/mach-at91/board-sam9x5cm.c	2013-03-07 17:07:04.793136604 -0600
++++ linux-2.6.39.4/arch/arm/mach-at91/board-sam9x5cm.c	2013-03-07 17:07:04.793136604 -0600
+@@ -18,6 +18,9 @@
+ #include <linux/platform_device.h>
+ #include <linux/spi/flash.h>
+ #include <linux/spi/spi.h>
++#include <linux/spi/eeprom.h>
++#include <linux/i2c/at24.h>
++#include <linux/delay.h>
+ #include <linux/fb.h>
+ #include <linux/gpio_keys.h>
+ #include <linux/input.h>
+@@ -103,6 +106,11 @@
+ 		.irq            = -1,
+ 	},
+ #endif
++	{
++		.modalias = "mts-io-board-temp",
++		.chip_select = 1,
++		.bus_num = 1,
++	},
+ #endif
+ };
+ 
+@@ -111,13 +119,48 @@
+  */
+ static struct mtd_partition __initdata cm_nand_partition[] = {
+ 	{
+-		.name	= "Partition 1",
++		.name	= "NANDFlash",
++		.offset	= 0,
++		.size	= 256*1024*1024,
++	},
++	{
++		.name	= "AT91Bootstrap",
+ 		.offset	= 0,
+-		.size	= SZ_64M,
++		.size	= 256*1024,
++	},
++	{
++		.name	= "UBoot",
++		.offset	= 256*1024,
++		.size	= 512*1024,
++	},
++	{
++		.name	= "UBoot Config",
++		.offset	= 768*1024,
++		.size	= 640*1024,
++	},
++	{
++		.name	= "UBoot Redundant Config",
++		.offset	= 1408*1024,
++		.size	= 640*1024,
+ 	},
+ 	{
+-		.name	= "Partition 2",
+-		.offset	= MTDPART_OFS_NXTBLK,
++		.name	= "uImage",
++		.offset	= 2*1024*1024,
++		.size	= 6*1024*1024,
++	},
++	{
++		.name	= "Config",
++		.offset	= 8*1024*1024,
++		.size	= 8*1024*1024,
++	},
++	{
++		.name	= "Oem Config",
++		.offset	= 16*1024*1024,
++		.size	= 8*1024*1024,
++	},
++	{
++		.name	= "Rootfs",
++		.offset	= 24*1024*1024,
+ 		.size	= MTDPART_SIZ_FULL,
+ 	},
+ };
+@@ -135,7 +178,8 @@
+ 	.enable_pin	= AT91_PIN_PD4,
+ 	.ecc_mode	= NAND_ECC_HW,
+ 	.has_pmecc	= 1,
+-	.pmecc_corr_cap	= 2,
++// MTOCGD3: 4-bit PMECC
++	.pmecc_corr_cap	= 4,
+ 	.pmecc_sector_size = 512,
+ 	.pmecc_lookup_table_offset = 0x8000,
+ 	.partition_info	= nand_partitions,
+@@ -170,7 +214,13 @@
+ 	else
+ 		cm_nand_smc_config.mode |= AT91_SMC_DBW_8;
+ 
++	// MTOCGD3 Rev A
++	cm_nand_data.bus_on_d0 = 1;
++	cm_nand_data.rdy_pin = AT91_PIN_PC31;
++
++	// MTOCGD3: disable
+ 	/* revision of board modify NAND wiring */
++	/*
+ 	if (cm_is_revA()) {
+ 		cm_nand_data.bus_on_d0 = 1;
+ 		cm_nand_data.rdy_pin = AT91_PIN_PD6;
+@@ -178,6 +228,7 @@
+ 		cm_nand_data.bus_on_d0 = 0;
+ 		cm_nand_data.rdy_pin = AT91_PIN_PD5;
+ 	}
++	*/
+ 
+ 	/* configure chip-select 3 (NAND) */
+ 	sam9_smc_configure(3, &cm_nand_smc_config);
+@@ -189,25 +240,71 @@
+  * LEDs
+  */
+ static struct gpio_led cm_leds[] = {
+-	{	/* "left" led, blue, userled1 */
+-		.name			= "d1",
+-		.gpio			= AT91_PIN_PB18,
++	{	/* default status LED */
++		.name			= "led-a",
++		.gpio			= AT91_PIN_PA24,
++		.active_low		= 1,
+ 		.default_trigger	= "heartbeat",
+ 	},
+-	{	/* "right" led, red, userled2 */
+-		.name			= "d2",
+-		.gpio			= AT91_PIN_PD21,
+-		.active_low		= 1,
+-		.default_trigger	= "mmc0",
++	{
++		.name			= "led-b",
++		.gpio			= AT91_PIN_PA29,
++		.active_low		= 1
++	},
++	{
++		.name			= "led-c",
++		.gpio			= AT91_PIN_PA25,
++		.active_low		= 1
++	},
++	{
++		.name			= "led-d",
++		.gpio			= AT91_PIN_PA26,
++		.active_low		= 1
++	},
++	{
++		.name			= "led-e",
++		.gpio			= AT91_PIN_PA27,
++		.active_low		= 1
++	},
++	{
++		.name			= "led-f",
++		.gpio			= AT91_PIN_PA28,
++		.active_low		= 1
+ 	},
+ };
+ 
++
++uint8_t mts_id_eeprom[512];
++
++EXPORT_SYMBOL(mts_id_eeprom);
++
++static void mts_id_eeprom_load(struct memory_accessor *macc, void *context)
++{
++	int tmp;
++
++	memset(mts_id_eeprom, 0, sizeof(mts_id_eeprom));
++
++	tmp = macc->read(macc, mts_id_eeprom, 0, sizeof(mts_id_eeprom));
++	if (tmp != sizeof(mts_id_eeprom)) {
++		printk(KERN_ERR "sam9x5: id eeprom read failed: %d\n", tmp);
++	} else {
++		printk(KERN_INFO "sam9x5: read %d bytes from id eeprom\n", tmp);
++	}
++}
++
++static struct at24_platform_data at24c04_data = {
++	.byte_len	= SZ_4K / 8,
++	.page_size	= 16,
++	.setup		= mts_id_eeprom_load,
++};
++
+ /*
+  * I2C Devices
+  */
+ static struct i2c_board_info __initdata cm_i2c_devices[] = {
+ 	{
+-		I2C_BOARD_INFO("24c512", 0x50)
++		I2C_BOARD_INFO("24c04", 0x56),
++		.platform_data = &at24c04_data,
+ 	},
+ };
+ 
+@@ -234,8 +331,12 @@
+ 	/* LEDs */
+ 	at91_gpio_leds(cm_leds, ARRAY_SIZE(cm_leds));
+ 
++	printk(KERN_CRIT "AT91: MTOCGD3 board\n");
++
++	/* MTOCGD3: disable
+ 	if (cm_is_revA())
+ 		printk(KERN_CRIT "AT91: CM rev A\n");
+ 	else
+ 		printk(KERN_CRIT "AT91: CM rev B and higher\n");
++	*/
+ }
+Index: linux-2.6.39.4/arch/arm/mach-at91/board-sam9x5ek.c
+===================================================================
+--- linux-2.6.39.4.orig/arch/arm/mach-at91/board-sam9x5ek.c	2013-03-07 17:07:03.293174822 -0600
++++ linux-2.6.39.4/arch/arm/mach-at91/board-sam9x5ek.c	2013-03-08 10:11:42.653155621 -0600
+@@ -23,6 +23,7 @@
+ #include <linux/leds.h>
+ #include <linux/clk.h>
+ #include <linux/delay.h>
++#include <linux/wl12xx.h>
+ #include <mach/cpu.h>
+ 
+ #include <video/atmel_lcdfb.h>
+@@ -53,12 +54,10 @@
+ 	/* Initialize processor and DBGU */
+ 	cm_map_io();
+ 
+-	/* USART0 on ttyS1. (Rx, Tx) */
+-	at91_register_uart(AT91SAM9X5_ID_USART0, 1, 0);
+-	/* USART1 on ttyS2. (Rx, Tx) */
+-	at91_register_uart(AT91SAM9X5_ID_USART1, 2, 0);
+-	/* USART2 on ttyS3. (Rx, Tx) */
+-	at91_register_uart(AT91SAM9X5_ID_USART2, 3, 0);
++	// MTOCGD3: GPS on UART0 as ttyS1 with Rx/Tx only
++	at91_register_uart(AT91SAM9X5_ID_UART0, 1, 0);
++	// MTOCGD3 Rev A: Daughter card serial on USART1 as ttyS2 with RTS/CTS
++	at91_register_uart(AT91SAM9X5_ID_USART1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+ }
+ 
+ /*
+@@ -89,34 +88,65 @@
+  * MACB Ethernet devices
+  */
+ static struct at91_eth_data __initdata ek_macb0_data = {
+-	.is_rmii	= 1,
++	.is_rmii	= 0,
++	.phy_irq_pin	= 0,
+ };
+ 
++/* MTOCGD3: no macb1
+ static struct at91_eth_data __initdata ek_macb1_data = {
+ 	.phy_irq_pin	= AT91_PIN_PC26,
+ 	.is_rmii	= 1,
+ };
++*/
+ 
+ 
+ /*
+  * MCI (SD/MMC)
+  */
+-/* mci0 detect_pin is revision dependent */
++// MTOCGD3: MCI0 is BT/Wifi
+ static struct mci_platform_data __initdata mci0_data = {
+ 	.slot[0] = {
+ 		.bus_width	= 4,
++		.detect_pin	= -1,
+ 		.wp_pin		= -1,
+ 	},
+ };
+ 
++// MTOCGD3: MCI1 is SD card slot
+ static struct mci_platform_data __initdata mci1_data = {
+ 	.slot[0] = {
+ 		.bus_width	= 4,
+-		.detect_pin	= AT91_PIN_PD14,
+-		.wp_pin		= -1,
++		.detect_pin	= AT91_PIN_PA1,
++		.wp_pin		= AT91_PIN_PA0,
+ 	},
+ };
+ 
++// MTR: Wi-fi
++static void wl12xx_enable(int poweron)
++{
++	if (poweron) {
++		at91_set_gpio_output_with_pullup(AT91_PIN_PC1, 0, 0);
++		msleep(10);
++		at91_set_gpio_output_with_pullup(AT91_PIN_PC1, 1, 0);
++		msleep(100);
++		printk(KERN_INFO "sam9x5: WLAN Enabled\n");
++	}
++	else {
++		at91_set_gpio_output_with_pullup(AT91_PIN_PC1, 0, 0);
++		msleep(10);
++		printk(KERN_INFO "sam9x5: WLAN Disabled\n");
++	}
++};
++
++// MTR: Wi-fi
++struct wl12xx_platform_data mtr_wlan_data  __initdata = {
++	.irq = AT91_PIN_PC2,
++	/* ref clock is 38.4 MHz */
++	.board_ref_clock = WL12XX_REFCLOCK_38,
++	/* toggles the WLAN_ENABLE pin */
++	.set_power = wl12xx_enable,
++};
++
+ /*
+  *  ISI
+  */
+@@ -326,9 +356,11 @@
+  * I2C Devices
+  */
+ static struct i2c_board_info __initdata ek_i2c_devices[] = {
++#if 0
+ 	{
+ 		I2C_BOARD_INFO("wm8731", 0x1a)
+ 	},
++#endif
+ #if defined(CONFIG_KEYBOARD_QT1070)
+ 	{
+ 		I2C_BOARD_INFO("qt1070", 0x1b),
+@@ -384,18 +416,24 @@
+ 	bool config_isi_enabled = false;
+ 
+ 	cm_board_init(&cm_config);
+-	ek_board_configure_pins();
++	// MTOCGD3: disable
++	//ek_board_configure_pins();
+ 	/* Serial */
+ 	at91_add_device_serial();
+ 	/* USB HS Host */
+ 	at91_add_device_usbh_ohci(&ek_usbh_fs_data);
+ 	at91_add_device_usbh_ehci(&ek_usbh_hs_data);
+ 	/* USB HS Device */
++	// MTOCGD3: set usb device vcc pin
++	ek_usba_udc_data.vbus_pin = AT91_PIN_PC7;
+ 	at91_add_device_usba(&ek_usba_udc_data);
+ 	/* Ethernet */
+ 	at91_add_device_eth(0, &ek_macb0_data);
++	/* MTOCGD3: no macb1
+ 	at91_add_device_eth(1, &ek_macb1_data);
++	*/
+ 	/* MMC0 */
++	// MTOCGD3: MCI0 for BT/Wifi
+ 	at91_add_device_mci(0, &mci0_data);
+ 	/* I2C */
+ 	if (cm_config & CM_CONFIG_I2C0_ENABLE)
+@@ -405,6 +443,18 @@
+ 		at91_add_device_i2c(0,
+ 				ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
+ 
++	// MTOCGD3: Wi-fi
++	at91_set_gpio_input(mtr_wlan_data.irq, 0);
++	at91_set_deglitch(mtr_wlan_data.irq, 1);
++
++	if (wl12xx_set_platform_data(&mtr_wlan_data))
++		pr_err("error setting wl12xx data\n");
++
++	// MTOCGD3: enable wl1271 chip so it is detected by SDIO scan on start up
++	wl12xx_enable(1);
++
++/* MTOCGD3: no LCD */
++#if 0
+ 	if (cpu_is_at91sam9g25()) {
+ 		/* ISI */
+ 		/* NOTE: PCK0 provides ISI_MCK to the ISI module.
+@@ -430,13 +480,10 @@
+ 		/* Touch Screen */
+ 		at91_add_device_tsadcc(&ek_tsadcc_data);
+ 	}
++#endif
+ 
+-	/* MMC1 */
+-	/* Conflict between SPI0, MCI1 and ISI pins.
+-	 * add MCI1 only if SPI0 and ISI are both disabled.
+-	 */
+-	if (!(cm_config & CM_CONFIG_SPI0_ENABLE) && !config_isi_enabled)
+-		at91_add_device_mci(1, &mci1_data);
++	// MTOCGD3: MCI1 to SD Card
++	at91_add_device_mci(1, &mci1_data);
+ 
+ #if 0
+ 	if (cpu_is_at91sam9x25() || cpu_is_at91sam9x35())
+@@ -448,6 +495,8 @@
+ 		at91_add_device_can(0, NULL);
+ #endif
+ 
++/* MTOCGD3: disable things we don't have */
++#if 0
+ 	if (cpu_is_at91sam9x25() || cpu_is_at91sam9x35())
+ 		/* this conflicts with usart.1 */
+ 		at91_add_device_can(1, NULL);
+@@ -474,6 +523,9 @@
+ 	else if (config_isi_enabled)
+ 		printk(KERN_CRIT
+ 			"AT91: ISI conficts with MCI1, disable MCI1\n");
++#endif
++
++	printk(KERN_CRIT "AT91: MTOCGD3 board EK init\n");
+ }
+ 
+ MACHINE_START(AT91SAM9X5EK, "Atmel AT91SAM9X5-EK")
+Index: linux-2.6.39.4/arch/arm/mach-at91/at91sam9x5_devices.c
+===================================================================
+--- linux-2.6.39.4.orig/arch/arm/mach-at91/at91sam9x5_devices.c	2013-03-07 17:07:03.793204785 -0600
++++ linux-2.6.39.4/arch/arm/mach-at91/at91sam9x5_devices.c	2013-03-07 17:07:04.793136604 -0600
+@@ -543,11 +543,11 @@
+ #endif
+ 
+ 	/* input/irq */
+-	if (data->slot[0].detect_pin) {
++	if (data->slot[0].detect_pin > 0) {
+ 		at91_set_gpio_input(data->slot[0].detect_pin, 1);
+ 		at91_set_deglitch(data->slot[0].detect_pin, 1);
+ 	}
+-	if (data->slot[0].wp_pin)
++	if (data->slot[0].wp_pin > 0)
+ 		at91_set_gpio_input(data->slot[0].wp_pin, 1);
+ 
+ 	if (mmc_id == 0) {		/* MCI0 */
+@@ -849,7 +849,8 @@
+ 	.num_resources	= ARRAY_SIZE(spi1_resources),
+ };
+ 
+-static const unsigned spi1_standard_cs[4] = { AT91_PIN_PA8, AT91_PIN_PA0, AT91_PIN_PA31, AT91_PIN_PA30 };
++// MTOCGD3: SPI1 chip selects on pins SPI1_NCS1 to SPI1_NCS5
++static const unsigned spi1_standard_cs[5] = { AT91_PIN_PC15, AT91_PIN_PC16, AT91_PIN_PC17, AT91_PIN_PC18, AT91_PIN_PC19 };
+ 
+ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+ {
diff --git a/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-wl12xx-sdio-irq.patch b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-wl12xx-sdio-irq.patch
new file mode 100644
index 0000000..6c1abcd
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-wl12xx-sdio-irq.patch
@@ -0,0 +1,15 @@
+Index: linux-2.6.39.4/drivers/net/wireless/wl12xx/sdio.c
+===================================================================
+--- linux-2.6.39.4.orig/drivers/net/wireless/wl12xx/sdio.c	2012-05-10 11:49:16.349486059 -0500
++++ linux-2.6.39.4/drivers/net/wireless/wl12xx/sdio.c	2012-05-10 16:36:15.009543390 -0500
+@@ -241,7 +242,9 @@
+ 	wl->ref_clock = wlan_data->board_ref_clock;
+ 
+ 	ret = request_threaded_irq(wl->irq, wl1271_hardirq, wl1271_irq,
+-				   IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
++// MTR: use rising edge interrupts, level doesn't work
++//				   IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
++				   IRQF_TRIGGER_RISING,
+ 				   DRIVER_NAME, wl);
+ 	if (ret < 0) {
+ 		wl1271_error("request_irq() failed: %d", ret);
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0001-DMA-AT91-Get-residual-bytes-in-dma-buffer.patch b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0001-DMA-AT91-Get-residual-bytes-in-dma-buffer.patch
new file mode 100644
index 0000000..7843ccb
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0001-DMA-AT91-Get-residual-bytes-in-dma-buffer.patch
@@ -0,0 +1,327 @@
+From 4af81f1015ac481cb900a27867a83a93924f3599 Mon Sep 17 00:00:00 2001
+From: Elen Song <elen.song@atmel.com>
+Date: Tue, 11 Dec 2012 18:24:48 +0800
+Subject: [PATCH 01/10] DMA: AT91: Get residual bytes in dma buffer
+
+Add support for returning the residue for current transfer cookie by
+reading the transfered buffer size(BTSIZE) in CTRLA register.
+
+For a single buffer cookie, the descriptor length minus BTSIZE
+can get the residue.
+
+For a lli cookie, remain_desc will record remain descriptor length
+when last descriptor finish, the remain_desc minus BTSIZE can get the
+current residue.
+
+If the cookie has completed successfully, the residue will be zero.
+If the cookie is in progress or the channel is paused, it will be
+the number of bytes yet to be transferred.If get residue error,
+the cookie will be turn into error status.
+
+Signed-off-by: Elen Song <elen.song@atmel.com>
+---
+ drivers/dma/at_hdmac.c      |  157 +++++++++++++++++++++++++++++++++++++------
+ drivers/dma/at_hdmac_regs.h |    5 ++
+ 2 files changed, 143 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
+index f793804..22739de 100644
+--- a/drivers/dma/at_hdmac.c
++++ b/drivers/dma/at_hdmac.c
+@@ -23,6 +23,7 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/slab.h>
++#include <linux/jiffies.h>
+ 
+ #include "at_hdmac_regs.h"
+ 
+@@ -39,6 +40,8 @@
+ #define	ATC_DEFAULT_CTRLA	(0)
+ #define	ATC_DEFAULT_CTRLB	(ATC_SIF(MEM_IF) | ATC_DIF(MEM_IF))
+ 
++/* DMA timeout (10ms)*/
++#define DMA_TIMEOUT		10
+ /*
+  * Initial number of descriptors to allocate for each channel. This could
+  * be increased during dma usage.
+@@ -51,6 +54,8 @@ MODULE_PARM_DESC(init_nr_desc_per_channel,
+ 
+ /* prototypes */
+ static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx);
++static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
++			unsigned long arg);
+ 
+ 
+ /*----------------------------------------------------------------------*/
+@@ -229,6 +234,111 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
+ 	vdbg_dump_regs(atchan);
+ }
+ 
++/*
++ * atc_get_current_descriptors -
++ * locate the descriptor which equal to physical address in DSCR
++ * @atchan: the channel we want to start
++ * @dscr_addr: physical descriptor address in DSCR
++ */
++static struct at_desc *atc_get_current_descriptors(struct at_dma_chan *atchan,
++							u32 dscr_addr)
++{
++	struct at_desc  *desc, *_desc, *child, *desc_cur = NULL;
++
++	list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) {
++
++		if (desc->lli.dscr == dscr_addr) {
++			desc_cur = desc;
++			break;
++		}
++
++		list_for_each_entry(child, &desc->tx_list, desc_node) {
++
++			if (child->lli.dscr == dscr_addr) {
++				desc_cur = child;
++				break;
++			}
++		}
++	}
++
++	return desc_cur;
++}
++
++/*
++ * atc_get_bytes_left -
++ * Get the number of bytes residue in dma buffer,
++ * the channel should be paused when calling this
++ * @chan: the channel we want to start
++ */
++static int atc_get_bytes_left(struct dma_chan *chan)
++{
++	struct at_dma_chan      *atchan = to_at_dma_chan(chan);
++	struct at_dma           *atdma = to_at_dma(chan->device);
++	int	chan_id = atchan->chan_common.chan_id;
++	struct at_desc *desc_first = atc_first_active(atchan);
++	struct at_desc *desc_cur;
++	int ret = 0, count = 0;
++	unsigned long timeout = jiffies + msecs_to_jiffies(DMA_TIMEOUT);
++
++	/*
++	 * Initialize necessary values in the first time.
++	 * remain_desc record remain desc length.
++	 */
++	if (atchan->remain_desc == 0)
++		/* First descriptor embedds the transaction length */
++		atchan->remain_desc = desc_first->len;
++
++start:
++	/* Channel should be paused before get residue */
++	if (!test_bit(ATC_IS_PAUSED, &atchan->status))
++		atc_control(chan, DMA_PAUSE, 0);
++	/*
++	 * This happens when current descriptor transfer complete.
++	 * The residual buffer size should reduce current descriptor length.
++	 */
++	if (unlikely(test_bit(ATC_IS_BTC, &atchan->status))) {
++		clear_bit(ATC_IS_BTC, &atchan->status);
++		desc_cur = atc_get_current_descriptors(atchan,
++						channel_readl(atchan, DSCR));
++		if (!desc_cur) {
++			ret = -EINVAL;
++			goto out;
++		}
++		atchan->remain_desc -= (desc_cur->lli.ctrla & ATC_BTSIZE_MAX)
++						<< (desc_first->tx_buswidth);
++		if (atchan->remain_desc < 0) {
++			ret = -EINVAL;
++			goto out;
++		} else
++			ret = atchan->remain_desc;
++	} else {
++		/*
++		 * Get residual bytes when current
++		 * descriptor transfer in progress.
++		 */
++		count = (channel_readl(atchan, CTRLA) & ATC_BTSIZE_MAX)
++				<< (desc_first->tx_buswidth);
++		ret = atchan->remain_desc - count;
++	}
++	/*
++	 * Check fifo empty in pre-determined time, if not,
++	 * restart a new taskelt to finish remain task.
++	 */
++	if (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id))) {
++		if (time_before(jiffies, timeout)) {
++			goto start;
++		} else {
++			dev_vdbg(chan2dev(chan), "fifo is not empty, restart a new tasklet\n");
++			tasklet_schedule(&atchan->tasklet);
++		}
++	}
++out:
++	if (test_bit(ATC_IS_PAUSED, &atchan->status))
++		atc_control(chan, DMA_RESUME, 0);
++
++	return ret;
++}
++
+ /**
+  * atc_chain_complete - finish work for one transaction chain
+  * @atchan: channel we work on
+@@ -492,6 +602,8 @@ static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
+ 					/* Give information to tasklet */
+ 					set_bit(ATC_IS_ERROR, &atchan->status);
+ 				}
++				if (pending & AT_DMA_BTC(i))
++					set_bit(ATC_IS_BTC, &atchan->status);
+ 				tasklet_schedule(&atchan->tasklet);
+ 				ret = IRQ_HANDLED;
+ 			}
+@@ -621,6 +733,7 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+ 	/* First descriptor of the chain embedds additional information */
+ 	first->txd.cookie = -EBUSY;
+ 	first->len = len;
++	first->tx_buswidth = src_width;
+ 
+ 	/* set end-of-link to the last link descriptor of list*/
+ 	set_desc_eol(desc);
+@@ -770,6 +883,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
+ 	/* First descriptor of the chain embedds additional information */
+ 	first->txd.cookie = -EBUSY;
+ 	first->len = total_len;
++	first->tx_buswidth = reg_width;
+ 
+ 	/* first link descriptor of list is responsible of flags */
+ 	first->txd.flags = flags; /* client is in control of this ack */
+@@ -892,6 +1006,7 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+ 	/* First descriptor of the chain embedds additional information */
+ 	first->txd.cookie = -EBUSY;
+ 	first->len = buf_len;
++	first->tx_buswidth = reg_width;
+ 
+ 	return &first->txd;
+ 
+@@ -1015,41 +1130,43 @@ atc_tx_status(struct dma_chan *chan,
+ 		dma_cookie_t cookie,
+ 		struct dma_tx_state *txstate)
+ {
+-	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
++	struct at_dma_chan      *atchan = to_at_dma_chan(chan);
+ 	dma_cookie_t		last_used;
+ 	dma_cookie_t		last_complete;
+ 	unsigned long		flags;
+ 	enum dma_status		ret;
++	int bytes = 0;
+ 
+-	spin_lock_irqsave(&atchan->lock, flags);
+ 
+ 	last_complete = atchan->completed_cookie;
+ 	last_used = chan->cookie;
+ 
+ 	ret = dma_async_is_complete(cookie, last_complete, last_used);
+-	if (ret != DMA_SUCCESS) {
+-		atc_cleanup_descriptors(atchan);
+ 
+-		last_complete = atchan->completed_cookie;
+-		last_used = chan->cookie;
++	if (ret == DMA_SUCCESS)
++		return ret;
++	/*
++	 * There's no point calculating the residue if there's
++	 * no txstate to store the value.
++	 */
++	if (!txstate)
++		return DMA_ERROR;
+ 
+-		ret = dma_async_is_complete(cookie, last_complete, last_used);
+-	}
++	spin_lock_irqsave(&atchan->lock, flags);
+ 
+-	spin_unlock_irqrestore(&atchan->lock, flags);
++	/*  Get number of bytes left in the active transactions */
++	bytes = atc_get_bytes_left(chan);
+ 
+-	if (ret != DMA_SUCCESS)
+-		dma_set_tx_state(txstate, last_complete, last_used,
+-			atc_first_active(atchan)->len);
+-	else
+-		dma_set_tx_state(txstate, last_complete, last_used, 0);
++	spin_unlock_irqrestore(&atchan->lock, flags);
+ 
+-	if (test_bit(ATC_IS_PAUSED, &atchan->status))
+-		ret = DMA_PAUSED;
++	if (unlikely(bytes < 0)) {
++		dev_vdbg(chan2dev(chan), "get residual bytes error\n");
++		return DMA_ERROR;
++	} else
++		dma_set_tx_state(txstate, last_complete, last_used, bytes);
+ 
+-	dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n",
+-		 ret, cookie, last_complete ? last_complete : 0,
+-		 last_used ? last_used : 0);
++	dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n",
++		 ret, cookie, bytes);
+ 
+ 	return ret;
+ }
+@@ -1135,6 +1252,7 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
+ 
+ 	spin_lock_irqsave(&atchan->lock, flags);
+ 	atchan->descs_allocated = i;
++	atchan->remain_desc = 0;
+ 	list_splice(&tmp_list, &atchan->free_list);
+ 	atchan->completed_cookie = chan->cookie = 1;
+ 	spin_unlock_irqrestore(&atchan->lock, flags);
+@@ -1177,6 +1295,7 @@ static void atc_free_chan_resources(struct dma_chan *chan)
+ 	list_splice_init(&atchan->free_list, &list);
+ 	atchan->descs_allocated = 0;
+ 	atchan->status = 0;
++	atchan->remain_desc = 0;
+ 
+ 	dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
+ }
+diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
+index a29c698..e819051 100644
+--- a/drivers/dma/at_hdmac_regs.h
++++ b/drivers/dma/at_hdmac_regs.h
+@@ -161,6 +161,7 @@ struct at_lli {
+  * @txd: support for the async_tx api
+  * @desc_node: node on the channed descriptors list
+  * @len: total transaction bytecount
++ * @tx_buswidth: transmit buswidth
+  */
+ struct at_desc {
+ 	/* FIRST values the hardware uses */
+@@ -171,6 +172,7 @@ struct at_desc {
+ 	struct dma_async_tx_descriptor	txd;
+ 	struct list_head		desc_node;
+ 	size_t				len;
++	u32                             tx_buswidth;
+ };
+ 
+ static inline struct at_desc *
+@@ -190,6 +192,7 @@ txd_to_at_desc(struct dma_async_tx_descriptor *txd)
+ enum atc_status {
+ 	ATC_IS_ERROR = 0,
+ 	ATC_IS_PAUSED = 1,
++	ATC_IS_BTC = 2,
+ 	ATC_IS_CYCLIC = 24,
+ };
+ 
+@@ -205,6 +208,7 @@ enum atc_status {
+  * @save_cfg: configuration register that is saved on suspend/resume cycle
+  * @save_dscr: for cyclic operations, preserve next descriptor address in
+  *             the cyclic list on suspend/resume cycle
++ * @save_len: to record dma buffer length
+  * @lock: serializes enqueue/dequeue operations to descriptors lists
+  * @completed_cookie: identifier for the most recently completed operation
+  * @active_list: list of descriptors dmaengine is being running on
+@@ -221,6 +225,7 @@ struct at_dma_chan {
+ 	struct tasklet_struct	tasklet;
+ 	u32			save_cfg;
+ 	u32			save_dscr;
++	int			remain_desc;
+ 
+ 	spinlock_t		lock;
+ 
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0002-Serial-Configure-DMAC-configuration-register-for-usa.patch b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0002-Serial-Configure-DMAC-configuration-register-for-usa.patch
new file mode 100644
index 0000000..f1a3411
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0002-Serial-Configure-DMAC-configuration-register-for-usa.patch
@@ -0,0 +1,73 @@
+From 38a9a2980b7497a5d892fb1ce9247c114cf17cdf Mon Sep 17 00:00:00 2001
+From: Elen Song <elen.song@atmel.com>
+Date: Fri, 6 Jul 2012 13:35:40 +0800
+Subject: [PATCH 02/10] Serial: Configure DMAC configuration register for
+ usart 0
+
+Configure DMAC_CFG to enable lli for uart0
+enable uart0 dma rx
+
+Signed-off-by: Elen Song <elen.song@atmel.com>
+---
+ arch/arm/mach-at91/at91sam9x5_devices.c |   25 ++++++++++++++++++++++++-
+ arch/arm/mach-at91/include/mach/board.h |    1 +
+ 2 files changed, 25 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
+index cee42dc..048d86a 100644
+--- a/arch/arm/mach-at91/at91sam9x5_devices.c
++++ b/arch/arm/mach-at91/at91sam9x5_devices.c
+@@ -1583,7 +1583,7 @@ static struct resource usart0_resources[] = {
+ 
+ static struct atmel_uart_data usart0_data = {
+ 	.use_dma_tx	= 1,
+-	.use_dma_rx	= 0,				/* doesn't support */
++	.use_dma_rx	= 1,
+ };
+ 
+ static u64 usart0_dmamask = DMA_BIT_MASK(32);
+@@ -1905,6 +1905,29 @@ void __init at91_add_device_serial(void)
+ 
+ 				pdata->dma_tx_slave = atslave;
+ 			}
++
++			if (pdata->use_dma_rx) {
++				struct at_dma_slave *arslave;
++
++				arslave = kzalloc(sizeof(struct at_dma_slave),
++					GFP_KERNEL);
++
++				/* DMA slave channel configuration */
++				if (peripheral_id == AT91SAM9X5_ID_USART0
++				    || peripheral_id == AT91SAM9X5_ID_USART1
++				    || peripheral_id == AT91SAM9X5_ID_UART0)
++					arslave->dma_dev = &at_hdmac0_device.dev;
++				else
++					arslave->dma_dev = &at_hdmac1_device.dev;
++
++				arslave->reg_width = DW_DMA_SLAVE_WIDTH_8BIT;
++				arslave->cfg = ATC_FIFOCFG_ENOUGHSPACE
++						| ATC_SRC_H2SEL_HW
++						| ATC_DST_H2SEL_SW
++						| AT_DMA_ID_USART0_RX; /*ATC_SRC_PER(peripheral_id);*/
++
++				pdata->dma_rx_slave = arslave;
++			}
+ #endif
+ 			platform_device_register(at91_usarts[i]);
+ 		}
+diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
+index 04dcec1..681688c 100644
+--- a/arch/arm/mach-at91/include/mach/board.h
++++ b/arch/arm/mach-at91/include/mach/board.h
+@@ -149,6 +149,7 @@ struct atmel_uart_data {
+ 	short			use_dma_rx;	/* use receive DMA? */
+ 	void __iomem		*regs;		/* virt. base address, if any */
+ 	struct at_dma_slave	*dma_tx_slave;
++	struct at_dma_slave	*dma_rx_slave;
+ 	struct serial_rs485	rs485;		/* rs485 settings */
+ };
+ extern void __init at91_add_device_serial(void);
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0003-Configure-peripheral-id-and-enable-basic-usart.patch b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0003-Configure-peripheral-id-and-enable-basic-usart.patch
new file mode 100644
index 0000000..75e95d9
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0003-Configure-peripheral-id-and-enable-basic-usart.patch
@@ -0,0 +1,153 @@
+From 42b8165988e2f601c8a5c0076710bb41d6f154c2 Mon Sep 17 00:00:00 2001
+From: Elen Song <elen.song@atmel.com>
+Date: Mon, 22 Oct 2012 17:48:03 +0800
+Subject: [PATCH 03/10] Configure peripheral id and enable basic usart
+
+enable basic usart(usart0,1,2) on 9x5serial
+to register more usart, add code in board-sam9x5ek.c
+for example, to add AT91SAM9X5_ID_UART0
+you can add it in ek_map_io:at91_register_uart(AT91SAM9X5_ID_UART0, 3, 0)
+
+pay attention to some board do not have uart,
+we should not register them.
+
+Signed-off-by: Elen Song <elen.song@atmel.com>
+---
+ arch/arm/mach-at91/at91sam9x5_devices.c      |   60 ++++++++++++++++++++++++--
+ arch/arm/mach-at91/board-sam9x5ek.c          |    4 ++
+ arch/arm/mach-at91/include/mach/at91sam9x5.h |    4 ++
+ 3 files changed, 64 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
+index 048d86a..26ecf47 100644
+--- a/arch/arm/mach-at91/at91sam9x5_devices.c
++++ b/arch/arm/mach-at91/at91sam9x5_devices.c
+@@ -1875,6 +1875,51 @@ void __init at91_set_serial_console(unsigned portnr)
+ 		atmel_default_console_device = at91_usarts[portnr];
+ }
+ 
++static int at91_set_peripheral_id(unsigned int id, unsigned int direction)
++{
++	unsigned int dst, src;
++	switch (id) {
++	case 0:     /* DBGU */
++		dst = AT_DMA_ID_DBGU_TX;
++		src = AT_DMA_ID_DBGU_RX;
++		break;
++	case AT91SAM9X5_ID_USART0:
++		dst = AT_DMA_ID_USART0_TX;
++		src = AT_DMA_ID_USART0_RX;
++		break;
++	case AT91SAM9X5_ID_USART1:
++		dst = AT_DMA_ID_USART1_TX;
++		src = AT_DMA_ID_USART1_RX;
++		break;
++	case AT91SAM9X5_ID_USART2:
++		dst = AT_DMA_ID_USART2_TX;
++		src = AT_DMA_ID_USART2_RX;
++		break;
++	case AT91SAM9X5_ID_USART3:
++		dst = AT_DMA_ID_USART3_TX;
++		src = AT_DMA_ID_USART3_RX;
++		break;
++	case AT91SAM9X5_ID_UART0:
++		dst = AT_DMA_ID_UART0_TX;
++		src = AT_DMA_ID_UART0_RX;
++		break;
++	case AT91SAM9X5_ID_UART1:
++		dst = AT_DMA_ID_UART1_TX;
++		src = AT_DMA_ID_UART1_RX;
++		break;
++	default:
++		printk(KERN_ERR "usart %d unsupport!\n", id);
++		break;
++	}
++
++	if (direction == AT_DMA_TX)
++		return dst << 4;
++	if (direction == AT_DMA_RX)
++		return src;
++
++	return -EINVAL;
++}
++
+ void __init at91_add_device_serial(void)
+ {
+ 	int i;
+@@ -1887,8 +1932,10 @@ void __init at91_add_device_serial(void)
+ 
+ 			if (pdata->use_dma_tx) {
+ 				struct at_dma_slave	*atslave;
+-
++				int dst;
+ 				atslave = kzalloc(sizeof(struct at_dma_slave), GFP_KERNEL);
++				dst = at91_set_peripheral_id(peripheral_id,
++								AT_DMA_TX);
+ 
+ 				/* DMA slave channel configuration */
+ 				if (peripheral_id == AT91SAM9X5_ID_USART0
+@@ -1901,14 +1948,16 @@ void __init at91_add_device_serial(void)
+ 				atslave->reg_width = DW_DMA_SLAVE_WIDTH_8BIT;
+ 				atslave->cfg = ATC_FIFOCFG_HALFFIFO
+ 						| ATC_SRC_H2SEL_SW | ATC_DST_H2SEL_HW
+-						| (AT_DMA_ID_USART0_TX << 4); /*ATC_DST_PER(peripheral_id);*/
++						| dst;
++						/*ATC_DST_PER(peripheral_id);*/
++
+ 
+ 				pdata->dma_tx_slave = atslave;
+ 			}
+ 
+ 			if (pdata->use_dma_rx) {
+ 				struct at_dma_slave *arslave;
+-
++				int src;
+ 				arslave = kzalloc(sizeof(struct at_dma_slave),
+ 					GFP_KERNEL);
+ 
+@@ -1921,10 +1970,13 @@ void __init at91_add_device_serial(void)
+ 					arslave->dma_dev = &at_hdmac1_device.dev;
+ 
+ 				arslave->reg_width = DW_DMA_SLAVE_WIDTH_8BIT;
++				src = at91_set_peripheral_id(peripheral_id,
++								AT_DMA_RX);
+ 				arslave->cfg = ATC_FIFOCFG_ENOUGHSPACE
+ 						| ATC_SRC_H2SEL_HW
+ 						| ATC_DST_H2SEL_SW
+-						| AT_DMA_ID_USART0_RX; /*ATC_SRC_PER(peripheral_id);*/
++						| src;
++						/*ATC_SRC_PER(peripheral_id);*/
+ 
+ 				pdata->dma_rx_slave = arslave;
+ 			}
+diff --git a/arch/arm/mach-at91/board-sam9x5ek.c b/arch/arm/mach-at91/board-sam9x5ek.c
+index 8c06040..cf72adb 100644
+--- a/arch/arm/mach-at91/board-sam9x5ek.c
++++ b/arch/arm/mach-at91/board-sam9x5ek.c
+@@ -55,6 +55,10 @@ static void __init ek_map_io(void)
+ 
+ 	/* USART0 on ttyS1. (Rx, Tx) */
+ 	at91_register_uart(AT91SAM9X5_ID_USART0, 1, 0);
++	/* USART1 on ttyS2. (Rx, Tx) */
++	at91_register_uart(AT91SAM9X5_ID_USART1, 2, 0);
++	/* USART2 on ttyS3. (Rx, Tx) */
++	at91_register_uart(AT91SAM9X5_ID_USART2, 3, 0);
+ }
+ 
+ /*
+diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
+index 1219b32..529cbc3 100644
+--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
++++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
+@@ -176,4 +176,8 @@
+ #define AT_DMA_ID_USART3_TX	14
+ #define AT_DMA_ID_USART3_RX	15
+ 
++/* DMA peripheral_id direction */
++#define AT_DMA_TX      0
++#define AT_DMA_RX      1
++
+ #endif
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0004-Serial-Enable-Serial-cyclic-DMA-transfer.patch b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0004-Serial-Enable-Serial-cyclic-DMA-transfer.patch
new file mode 100644
index 0000000..4cba1b2
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0004-Serial-Enable-Serial-cyclic-DMA-transfer.patch
@@ -0,0 +1,399 @@
+From 29a3f150b069754fb4318e1a44f91f51f94fccf2 Mon Sep 17 00:00:00 2001
+From: Elen Song <elen.song@atmel.com>
+Date: Tue, 11 Dec 2012 18:38:55 +0800
+Subject: [PATCH 04/10] Serial: Enable Serial cyclic DMA transfer
+
+request a dma channle for serial rx,
+the channel is defined to be used for dma cyclic transfer,
+atmel_allocate_desc will allocate a cycle dma transfer after request channel,
+enable uart timeout in startup stage,
+when data successful receive, during the transfer interval,
+it will call timeout handler,
+the timeout handler will check the residual value,
+and insert the receive data into framework.
+
+Signed-off-by: Elen Song <elen.song@atmel.com>
+---
+ drivers/tty/serial/atmel_serial.c |  261 ++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 257 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
+index 205e496..b990594 100644
+--- a/drivers/tty/serial/atmel_serial.c
++++ b/drivers/tty/serial/atmel_serial.c
+@@ -130,7 +130,7 @@ struct atmel_uart_char {
+ 	u16		ch;
+ };
+ 
+-#define ATMEL_SERIAL_RINGSIZE 1024
++#define ATMEL_SERIAL_RINGSIZE 4096
+ 
+ /*
+  * We wrap our port structure around the generic uart_port.
+@@ -150,13 +150,19 @@ struct atmel_uart_port {
+ 	struct atmel_dma_buffer	pdc_tx;		/* PDC transmitter */
+ 
+ 	spinlock_t			lock_tx;	/* port lock */
++	spinlock_t			lock_rx;	/* port lock */
+ 	struct dma_chan			*chan_tx;
++	struct dma_chan			*chan_rx;
+ 	struct dma_async_tx_descriptor	*desc_tx;
++	struct dma_async_tx_descriptor	*desc_rx;
+ 	dma_cookie_t			cookie_tx;
++	dma_cookie_t			cookie_rx;
+ 
+ 	signed int			xmit_head;
+ 	struct scatterlist		sg_tx;
++	struct scatterlist		sg_rx;
+ 	unsigned int			sg_len_tx;
++	unsigned int			sg_len_rx;
+ 
+ 	struct tasklet_struct	tasklet;
+ 	unsigned int		irq_status;
+@@ -213,13 +219,24 @@ static bool atmel_use_dma_tx(struct uart_port *port)
+ 
+ 	return atmel_port->use_dma_tx;
+ }
++
++static bool atmel_use_dma_rx(struct uart_port *port)
++{
++	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++
++	return atmel_port->use_dma_rx;
++}
+ #else
+ static bool atmel_use_dma_tx(struct uart_port *port)
+ {
+ 	return false;
+ }
+-#endif
+ 
++static bool atmel_use_dma_rx(struct uart_port *port)
++{
++	return false;
++}
++#endif
+ /* Enable or disable the rs485 support */
+ void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
+ {
+@@ -605,16 +622,38 @@ static void atmel_dma_tx_complete(void *arg)
+ 	spin_unlock_irqrestore(&port->lock, flags);
+ }
+ 
++
++static void atmel_dma_rx_complete(void *arg)
++{
++	struct uart_port *port = arg;
++	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++
++	tasklet_schedule(&atmel_port->tasklet);
++}
++
+ static void atmel_tx_dma_release(struct atmel_uart_port *atmel_port)
+ {
+ 	struct dma_chan *chan = atmel_port->chan_tx;
+ 
+ 	atmel_port->chan_tx = NULL;
+ 	atmel_port->cookie_tx = -EINVAL;
++}
++
++static void atmel_rx_dma_release(struct atmel_uart_port *atmel_port)
++{
++	struct dma_chan *chan = atmel_port->chan_rx;
++	struct uart_port *port = &(atmel_port->uart);
++
+ 	if (chan) {
+ 		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+ 		dma_release_channel(chan);
++		dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
++				DMA_FROM_DEVICE);
+ 	}
++
++	atmel_port->desc_rx = NULL;
++	atmel_port->chan_rx = NULL;
++	atmel_port->cookie_rx = -EINVAL;
+ }
+ 
+ /*
+@@ -700,6 +739,79 @@ static void atmel_tx_dma(struct uart_port *port)
+ 		uart_write_wakeup(port);
+ }
+ 
++static void atmel_rx_dma_flip_buffer(struct uart_port *port,
++				char *buf, size_t count)
++{
++	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++	struct tty_struct *tty = port->state->port.tty;
++
++	dma_sync_sg_for_cpu(port->dev,
++				&atmel_port->sg_rx,
++				1,
++				DMA_FROM_DEVICE);
++
++	tty_insert_flip_string(tty, buf, count);
++
++	dma_sync_sg_for_device(port->dev,
++				&atmel_port->sg_rx,
++				1,
++				DMA_FROM_DEVICE);
++	/*
++	 * Drop the lock here since it might end up calling
++	 * uart_start(), which takes the lock.
++	 */
++	spin_unlock(&port->lock);
++	tty_flip_buffer_push(tty);
++	spin_lock(&port->lock);
++}
++
++
++static void atmel_rx_from_dma(struct uart_port *port)
++{
++	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++	struct circ_buf *ring = &atmel_port->rx_ring;
++	struct dma_chan *chan = atmel_port->chan_rx;
++	struct dma_tx_state state;
++	enum dma_status dmastat;
++	size_t pending, count;
++
++
++	/* Reset the UART timeout early so that we don't miss one */
++	UART_PUT_CR(port, ATMEL_US_STTTO);
++	dmastat = chan->device->device_tx_status(chan,
++						atmel_port->cookie_rx,
++						&state);
++	/* Restart a new tasklet if DMA status is error */
++	if (dmastat == DMA_ERROR) {
++		dev_dbg(port->dev, "Get residue error, restart tasklet\n");
++		UART_PUT_IER(port, ATMEL_US_TIMEOUT);
++		tasklet_schedule(&atmel_port->tasklet);
++		return;
++	}
++	/* current transfer size should no larger than dma buffer */
++	pending = sg_dma_len(&atmel_port->sg_rx) - state.residue;
++	BUG_ON(pending > sg_dma_len(&atmel_port->sg_rx));
++
++	/*
++	 * This will take the chars we have so far,
++	 * ring->head will record the transfer size, only new bytes come
++	 * will insert into the framework.
++	 */
++	if (pending > ring->head) {
++		count = pending - ring->head;
++
++		atmel_rx_dma_flip_buffer(port, ring->buf + ring->head, count);
++
++		ring->head += count;
++		if (ring->head == sg_dma_len(&atmel_port->sg_rx))
++			ring->head = 0;
++
++		port->icount.rx += count;
++	}
++
++	UART_PUT_IER(port, ATMEL_US_TIMEOUT);
++}
++
+ static bool filter(struct dma_chan *chan, void *slave)
+ {
+ 	struct	at_dma_slave		*sl = slave;
+@@ -767,11 +879,87 @@ static void atmel_tx_request_dma(struct atmel_uart_port *atmel_port)
+ 		atmel_port->xmit_head = -1;
+ 	}
+ }
++
++static void atmel_rx_request_dma(struct atmel_uart_port *atmel_port)
++{
++	struct uart_port	*port;
++	struct atmel_uart_data	*pdata;
++	dma_cap_mask_t		mask;
++	struct dma_chan		*chan = NULL;
++	struct circ_buf *ring = &atmel_port->rx_ring;
++
++	if (atmel_port == NULL)
++		return;
++
++	port = &(atmel_port->uart);
++	pdata = (struct atmel_uart_data *)port->private_data;
++
++	if (!pdata)
++		goto chan_err;
++
++	dma_cap_zero(mask);
++	dma_cap_set(DMA_CYCLIC, mask);
++
++	if (atmel_use_dma_rx(port) && pdata->dma_rx_slave) {
++		pdata->dma_rx_slave->rx_reg = port->mapbase + ATMEL_US_RHR;
++		chan = dma_request_channel(mask, filter, pdata->dma_rx_slave);
++		if (chan == NULL)
++			goto chan_err;
++		dev_dbg(port->dev, "%s: RX: got channel %d\n",
++			__func__,
++			chan->chan_id);
++	}
++
++	if (chan) {
++		int nent;
++
++		spin_lock_init(&atmel_port->lock_rx);
++		atmel_port->chan_rx = chan;
++
++		sg_init_table(&atmel_port->sg_rx, 1);
++		/* UART circular tx buffer is an aligned page. */
++		BUG_ON((int)ring->buf & ~PAGE_MASK);
++		sg_set_page(&atmel_port->sg_rx,
++				virt_to_page(ring->buf),
++				ATMEL_SERIAL_RINGSIZE,
++				(int)ring->buf & ~PAGE_MASK);
++				nent = dma_map_sg(port->dev,
++				&atmel_port->sg_rx,
++				1,
++				DMA_FROM_DEVICE);
++
++		if (!nent)
++			dev_dbg(port->dev, "need to release resource of dma\n");
++		else
++			dev_dbg(port->dev, "%s: mapped %d@%p to %x\n",
++				__func__,
++				sg_dma_len(&atmel_port->sg_rx),
++				ring->buf,
++				sg_dma_address(&atmel_port->sg_rx));
++
++		atmel_port->sg_len_rx = nent;
++
++		ring->head = 0;
++		ring->tail = 0;
++	}
++
++	return;
++
++chan_err:
++	dev_err(port->dev, "RX channel not available, switch to pio\n");
++	atmel_port->use_dma_rx = 0;
++	atmel_rx_dma_release(atmel_port);
++	return;
++}
+ #else
+ static void atmel_dma_tx_complete(void *arg) {}
++static void atmel_dma_rx_complete(void *arg) {}
+ static void atmel_tx_dma_release(struct atmel_uart_port *atmel_port) {}
++static void atmel_rx_dma_release(struct atmel_uart_port *atmel_port) {}
+ static void atmel_tx_dma(struct uart_port *port) {}
++static void atmel_rx_from_dma(struct uart_port *port) {}
+ static void atmel_tx_request_dma(struct atmel_uart_port *atmel_port) {}
++static void atmel_rx_request_dma(struct atmel_uart_port *atmel_port) {}
+ #endif
+ 
+ /*
+@@ -801,6 +989,17 @@ atmel_handle_receive(struct uart_port *port, unsigned int pending)
+ 			atmel_pdc_rxerr(port, pending);
+ 	}
+ 
++	if (atmel_use_dma_rx(port)) {
++		if (pending & ATMEL_US_TIMEOUT) {
++			UART_PUT_IDR(port, ATMEL_US_TIMEOUT);
++			tasklet_schedule(&atmel_port->tasklet);
++	}
++
++		if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
++				ATMEL_US_FRAME | ATMEL_US_PARE))
++			atmel_pdc_rxerr(port, pending);
++	}
++
+ 	/* Interrupt receive */
+ 	if (pending & ATMEL_US_RXRDY)
+ 		atmel_rx_chars(port);
+@@ -1105,12 +1304,55 @@ static void atmel_tasklet_func(unsigned long data)
+ 
+ 	if (atmel_use_pdc_rx(port))
+ 		atmel_rx_from_pdc(port);
++	else if (atmel_use_dma_rx(port))
++		atmel_rx_from_dma(port);
+ 	else
+ 		atmel_rx_from_ring(port);
+ 
+ 	spin_unlock(&port->lock);
+ }
+ 
++static int atmel_allocate_desc(struct uart_port *port)
++{
++	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++	struct dma_async_tx_descriptor *desc;
++	struct dma_chan *chan = atmel_port->chan_rx;
++
++	if (!chan) {
++		dev_err(port->dev, "No channel available\n");
++		goto err_dma;
++	}
++	/*
++	 * Prepare a cyclic dma transfer, assign 2 descriptors,
++	 * each one is half ring buffer size
++	 */
++	desc = chan->device->device_prep_dma_cyclic(chan,
++			sg_dma_address(&atmel_port->sg_rx),
++			sg_dma_len(&atmel_port->sg_rx),
++			sg_dma_len(&atmel_port->sg_rx)/2,
++			DMA_FROM_DEVICE);
++
++	desc->callback = atmel_dma_rx_complete;
++	desc->callback_param = port;
++	atmel_port->desc_rx = desc;
++	atmel_port->cookie_rx = dmaengine_submit(desc);
++
++	async_tx_ack(atmel_port->desc_rx);
++
++	if (dma_submit_error(atmel_port->cookie_rx)) {
++		dev_err(port->dev, "Failed submitting Rx DMA descriptor\n");
++		goto err_dma;
++	}
++
++	return 0;
++
++err_dma:
++	dev_warn(port->dev, "Switch to PIO\n");
++	atmel_port->use_dma_rx = 0;
++	atmel_rx_dma_release(atmel_port);
++	return -EINVAL;
++}
++
+ /*
+  * Perform initialization and enable port for reception
+  */
+@@ -1191,6 +1433,10 @@ static int atmel_startup(struct uart_port *port)
+ 	if (atmel_use_dma_tx(port))
+ 		atmel_tx_request_dma(atmel_port);
+ 
++	if (atmel_use_dma_rx(port)) {
++		atmel_rx_request_dma(atmel_port);
++		atmel_allocate_desc(port);
++	}
+ 	/*
+ 	 * If there is a specific "open" function (to register
+ 	 * control line interrupts)
+@@ -1222,6 +1468,12 @@ static int atmel_startup(struct uart_port *port)
+ 		UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
+ 		/* enable PDC controller */
+ 		UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
++	} else if (atmel_use_dma_rx(port)) {
++		/* set UART timeout */
++		UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
++		UART_PUT_CR(port, ATMEL_US_STTTO);
++
++		UART_PUT_IER(port, ATMEL_US_TIMEOUT);
+ 	} else {
+ 		/* enable receive only */
+ 		UART_PUT_IER(port, ATMEL_US_RXRDY);
+@@ -1267,9 +1519,10 @@ static void atmel_shutdown(struct uart_port *port)
+ 				 DMA_TO_DEVICE);
+ 	}
+ 
+-	if (atmel_use_dma_tx(port)) {
++	if (atmel_use_dma_rx(port))
++		atmel_rx_dma_release(atmel_port);
++	if (atmel_use_dma_tx(port))
+ 		atmel_tx_dma_release(atmel_port);
+-	}
+ 	/*
+ 	 * Disable all interrupts, port and break condition.
+ 	 */
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0005-Serial-AT91-Refine-tx-dma.patch b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0005-Serial-AT91-Refine-tx-dma.patch
new file mode 100644
index 0000000..7360893
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0005-Serial-AT91-Refine-tx-dma.patch
@@ -0,0 +1,167 @@
+From a5e9545cb6f9e171d8f015c661b9c8d7a84567e5 Mon Sep 17 00:00:00 2001
+From: Elen Song <elen.song@atmel.com>
+Date: Tue, 11 Dec 2012 18:44:45 +0800
+Subject: [PATCH 05/10] Serial: AT91: Refine tx dma
+
+remove useless part,
+refine tx request dma, swith to pio if channel is busy,
+refine tx dma, remove useless lock, terminate dma will transaction complete
+
+Signed-off-by: Elen Song <elen.song@atmel.com>
+---
+ drivers/tty/serial/atmel_serial.c |   60 ++++++++++++++++++-------------------
+ 1 file changed, 30 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
+index b990594..9013e6f 100644
+--- a/drivers/tty/serial/atmel_serial.c
++++ b/drivers/tty/serial/atmel_serial.c
+@@ -158,7 +158,6 @@ struct atmel_uart_port {
+ 	dma_cookie_t			cookie_tx;
+ 	dma_cookie_t			cookie_rx;
+ 
+-	signed int			xmit_head;
+ 	struct scatterlist		sg_tx;
+ 	struct scatterlist		sg_rx;
+ 	unsigned int			sg_len_tx;
+@@ -596,10 +595,14 @@ static void atmel_dma_tx_complete(void *arg)
+ 	struct atmel_uart_port *atmel_port = arg;
+ 	struct uart_port *port = &atmel_port->uart;
+ 	struct circ_buf *xmit = &port->state->xmit;
++	struct dma_chan *chan = atmel_port->chan_tx;
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&port->lock, flags);
+ 
++	if (chan)
++		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
++
+ 	xmit->tail += sg_dma_len(&atmel_port->sg_tx);
+ 	xmit->tail &= UART_XMIT_SIZE - 1;
+ 
+@@ -634,7 +637,16 @@ static void atmel_dma_rx_complete(void *arg)
+ static void atmel_tx_dma_release(struct atmel_uart_port *atmel_port)
+ {
+ 	struct dma_chan *chan = atmel_port->chan_tx;
++	struct uart_port *port = &(atmel_port->uart);
++
++	if (chan) {
++		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
++		dma_release_channel(chan);
++		dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
++				DMA_TO_DEVICE);
++	}
+ 
++	atmel_port->desc_tx = NULL;
+ 	atmel_port->chan_tx = NULL;
+ 	atmel_port->cookie_tx = -EINVAL;
+ }
+@@ -667,13 +679,9 @@ static void atmel_tx_dma(struct uart_port *port)
+ 	struct dma_async_tx_descriptor *desc;
+ 	struct scatterlist *sg = &atmel_port->sg_tx;
+ 
+-	spin_lock_irq(&atmel_port->lock_tx);
+ 	/* Make sure we have an idle channel */
+-	if (atmel_port->desc_tx != NULL) {
+-		spin_lock_irq(&atmel_port->lock_tx);
++	if (atmel_port->desc_tx != NULL)
+ 		return;
+-	}
+-	spin_unlock_irq(&atmel_port->lock_tx);
+ 
+ 	if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
+ 		/*
+@@ -683,23 +691,10 @@ static void atmel_tx_dma(struct uart_port *port)
+ 		 * transmit till the end, and then the rest. Take the port lock to get a
+ 		 * consistent xmit buffer state.
+ 		 */
+-		spin_lock_irq(&port->lock);
+-		if (atmel_port->xmit_head != -1) {
+-			if (atmel_port->xmit_head != xmit->head) {
+-				atmel_port->xmit_head = xmit->head;
+-			} else {
+-				spin_unlock_irq(&port->lock);
+-				return;
+-			}
+-		} else {
+-			atmel_port->xmit_head = xmit->head;
+-		}
+-
+ 		sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
+ 		sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1))
+ 							+ sg->offset;
+ 		sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
+-		spin_unlock_irq(&port->lock);
+ 
+ 		BUG_ON(!sg_dma_len(sg));
+ 
+@@ -707,22 +702,18 @@ static void atmel_tx_dma(struct uart_port *port)
+ 				sg, atmel_port->sg_len_tx, DMA_TO_DEVICE,
+ 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ 		if (!desc) {
+-			spin_unlock_irq(&port->lock);
+-			printk (KERN_ERR "#### Error! Failed to send via dma!\n");
++			dev_err(port->dev, "Error! Failed to send via dma!\n");
+ 			return;
+ 		}
+ 
+ 		dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
+ 
+-		spin_lock_irq(&port->lock);
+ 		atmel_port->desc_tx = desc;
+ 		desc->callback = atmel_dma_tx_complete;
+ 		desc->callback_param = atmel_port;
+-		spin_unlock_irq(&port->lock);
+ 		atmel_port->cookie_tx = desc->tx_submit(desc);
+ 		if (atmel_port->cookie_tx < 0) {
+ 			dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
+-			/* switch to PIO */
+ 			atmel_tx_dma_release(atmel_port);
+ 			return;
+ 		}
+@@ -837,10 +828,8 @@ static void atmel_tx_request_dma(struct atmel_uart_port *atmel_port)
+ 	port = &(atmel_port->uart);
+ 	pdata = (struct atmel_uart_data *)port->private_data;
+ 
+-	if (!pdata) {
+-		dev_notice(port->dev, "DMA not available, using PIO\n");
+-		return;
+-	}
++	if (!pdata)
++		goto chan_err;
+ 
+ 	dma_cap_zero(mask);
+ 	dma_cap_set(DMA_SLAVE, mask);
+@@ -848,7 +837,11 @@ static void atmel_tx_request_dma(struct atmel_uart_port *atmel_port)
+ 	if (atmel_use_dma_tx(port) && pdata->dma_tx_slave) {
+ 		pdata->dma_tx_slave->tx_reg = port->mapbase + ATMEL_US_THR;
+ 		chan = dma_request_channel(mask, filter, pdata->dma_tx_slave);
+-		dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
++		if (chan == NULL)
++			goto chan_err;
++		dev_dbg(port->dev, "%s: TX: got channel %d\n",
++			__func__,
++			chan->chan_id);
+ 	}
+ 
+ 	if (chan) {
+@@ -876,8 +869,15 @@ static void atmel_tx_request_dma(struct atmel_uart_port *atmel_port)
+ 				sg_dma_address(&atmel_port->sg_tx));
+ 
+ 		atmel_port->sg_len_tx = nent;
+-		atmel_port->xmit_head = -1;
+ 	}
++
++	return;
++
++chan_err:
++	dev_err(port->dev, "TX channel not available, switch to pio\n");
++	atmel_port->use_dma_tx = 0;
++	atmel_tx_dma_release(atmel_port);
++	return;
+ }
+ 
+ static void atmel_rx_request_dma(struct atmel_uart_port *atmel_port)
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0006-Serial-AT91-refine-error-handler-in-probe-stage.patch b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0006-Serial-AT91-refine-error-handler-in-probe-stage.patch
new file mode 100644
index 0000000..b3581e3
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0006-Serial-AT91-refine-error-handler-in-probe-stage.patch
@@ -0,0 +1,70 @@
+From f4009ec3887c79e58f43c7c6010ae174d73ee662 Mon Sep 17 00:00:00 2001
+From: Elen Song <elen.song@atmel.com>
+Date: Tue, 11 Dec 2012 18:46:33 +0800
+Subject: [PATCH 06/10] Serial: AT91: refine error handler in probe stage
+
+Signed-off-by: Elen Song <elen.song@atmel.com>
+---
+ drivers/tty/serial/atmel_serial.c |   32 +++++++++++++++++++-------------
+ 1 file changed, 19 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
+index 9013e6f..65b2bb4 100644
+--- a/drivers/tty/serial/atmel_serial.c
++++ b/drivers/tty/serial/atmel_serial.c
+@@ -1390,15 +1390,10 @@ static int atmel_startup(struct uart_port *port)
+ 
+ 			pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
+ 			if (pdc->buf == NULL) {
+-				if (i != 0) {
+-					dma_unmap_single(port->dev,
+-						atmel_port->pdc_rx[0].dma_addr,
+-						PDC_BUFFER_SIZE,
+-						DMA_FROM_DEVICE);
+-					kfree(atmel_port->pdc_rx[0].buf);
+-				}
+-				free_irq(port->irq, port);
+-				return -ENOMEM;
++				retval = -ENOMEM;
++				if (i != 0)
++					goto err_second_pdc_buffer;
++				goto err_pdc_buffer;
+ 			}
+ 			pdc->dma_addr = dma_map_single(port->dev,
+ 						       pdc->buf,
+@@ -1443,10 +1438,8 @@ static int atmel_startup(struct uart_port *port)
+ 	 */
+ 	if (atmel_open_hook) {
+ 		retval = atmel_open_hook(port);
+-		if (retval) {
+-			free_irq(port->irq, port);
+-			return retval;
+-		}
++		if (retval)
++			goto err_open_hook;
+ 	}
+ 
+ 	/* Save current CSR for comparison in atmel_tasklet_func() */
+@@ -1480,6 +1473,19 @@ static int atmel_startup(struct uart_port *port)
+ 	}
+ 
+ 	return 0;
++
++err_open_hook:
++err_second_pdc_buffer:
++	if (atmel_use_pdc_rx(port)) {
++		dma_unmap_single(port->dev,
++			atmel_port->pdc_rx[0].dma_addr,
++			PDC_BUFFER_SIZE,
++			DMA_FROM_DEVICE);
++		kfree(atmel_port->pdc_rx[0].buf);
++	}
++err_pdc_buffer:
++	free_irq(port->irq, port);
++	return retval;
+ }
+ 
+ /*
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0007-Serial-AT91-Add-dma-support-for-rs485-and-iso7816.patch b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0007-Serial-AT91-Add-dma-support-for-rs485-and-iso7816.patch
new file mode 100644
index 0000000..07b4508
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0007-Serial-AT91-Add-dma-support-for-rs485-and-iso7816.patch
@@ -0,0 +1,71 @@
+From df26bc6eeb017f49b0fee9a149f0f2e1d5a22cd6 Mon Sep 17 00:00:00 2001
+From: Elen Song <elen.song@atmel.com>
+Date: Tue, 6 Nov 2012 16:57:39 +0800
+Subject: [PATCH 07/10] Serial: AT91: Add dma support for rs485 and iso7816
+
+Add dma defination is atmel_start_tx, atmel_start_rx, atmel_stop_rx
+
+Signed-off-by: Elen Song <elen.song@atmel.com>
+---
+ drivers/tty/serial/atmel_serial.c |   19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
+index 65b2bb4..0133698 100644
+--- a/drivers/tty/serial/atmel_serial.c
++++ b/drivers/tty/serial/atmel_serial.c
+@@ -406,6 +406,11 @@ static void atmel_start_tx(struct uart_port *port)
+ 		UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
+ 	}
+ 
++	if (atmel_use_dma_tx(port)) {
++		if (atmel_port->rs485.flags & SER_RS485_ENABLED)
++			atmel_stop_rx(port);
++	}
++
+ 	/* Enable interrupts */
+ 	UART_PUT_IER(port, atmel_port->tx_done_mask);
+ }
+@@ -415,6 +420,9 @@ static void atmel_start_tx(struct uart_port *port)
+  */
+ static void atmel_start_rx(struct uart_port *port)
+ {
++	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++	struct dma_chan *chan = atmel_port->chan_rx;
++
+ 	UART_PUT_CR(port, ATMEL_US_RSTSTA);  /* reset status and receiver */
+ 
+ 	if (atmel_use_pdc_rx(port)) {
+@@ -422,6 +430,10 @@ static void atmel_start_rx(struct uart_port *port)
+ 		UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
+ 			port->read_status_mask);
+ 		UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
++	} else if (atmel_use_dma_rx(port)) {
++		/* resume dma transfer */
++		if (chan)
++			chan->device->device_control(chan, DMA_RESUME, 0);
+ 	} else {
+ 		UART_PUT_IER(port, ATMEL_US_RXRDY);
+ 	}
+@@ -432,11 +444,18 @@ static void atmel_start_rx(struct uart_port *port)
+  */
+ static void atmel_stop_rx(struct uart_port *port)
+ {
++	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++	struct dma_chan *chan = atmel_port->chan_rx;
++
+ 	if (atmel_use_pdc_rx(port)) {
+ 		/* disable PDC receive */
+ 		UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
+ 		UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
+ 			port->read_status_mask);
++	} else if (atmel_use_dma_rx(port)) {
++		/* pause dma transfer */
++		if (chan)
++			chan->device->device_control(chan, DMA_PAUSE, 0);
+ 	} else {
+ 		UART_PUT_IDR(port, ATMEL_US_RXRDY);
+ 	}
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0008-Serial-AT91-remove-tx-dma-issue-pending.patch b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0008-Serial-AT91-remove-tx-dma-issue-pending.patch
new file mode 100644
index 0000000..edbf595
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0008-Serial-AT91-remove-tx-dma-issue-pending.patch
@@ -0,0 +1,32 @@
+From dd70a9fe2c0576be5cd6ee63d2d179bdbd164425 Mon Sep 17 00:00:00 2001
+From: Elen Song <elen.song@atmel.com>
+Date: Tue, 11 Dec 2012 18:59:50 +0800
+Subject: [PATCH 08/10] Serial: AT91: remove tx dma issue pending
+
+issue pending will cause dma complete callback execute if tx dma interrupt comes,
+when next tx interrupt happend before last dma complete callback,
+it will enable dma again, but the last dma assume dma is already closed,
+it will crash that driver found dma is enable when transaction finished.
+remove dma issue pending.
+
+Signed-off-by: Elen Song <elen.song@atmel.com>
+---
+ drivers/tty/serial/atmel_serial.c |    2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
+index 0133698..d253566 100644
+--- a/drivers/tty/serial/atmel_serial.c
++++ b/drivers/tty/serial/atmel_serial.c
+@@ -736,8 +736,6 @@ static void atmel_tx_dma(struct uart_port *port)
+ 			atmel_tx_dma_release(atmel_port);
+ 			return;
+ 		}
+-
+-		dma_async_issue_pending(chan);
+ 	} else {
+ 		if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
+ 			/* DMA done, stop TX, start RX for RS485 */
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0009-Serial-AT91-Fix-DBGU-peripheral_id-wrong.patch b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0009-Serial-AT91-Fix-DBGU-peripheral_id-wrong.patch
new file mode 100644
index 0000000..63bb912
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0009-Serial-AT91-Fix-DBGU-peripheral_id-wrong.patch
@@ -0,0 +1,37 @@
+From 871a2b4a6974b7eba9da88bad95309d7555bd4db Mon Sep 17 00:00:00 2001
+From: Elen Song <elen.song@atmel.com>
+Date: Fri, 25 Jan 2013 16:15:17 +0800
+Subject: [PATCH 09/10] Serial:AT91: Fix DBGU peripheral_id wrong
+
+also fix warning.
+
+Signed-off-by: Elen Song <elen.song@atmel.com>
+---
+ arch/arm/mach-at91/at91sam9x5_devices.c |    4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
+index 26ecf47..c1e402d 100644
+--- a/arch/arm/mach-at91/at91sam9x5_devices.c
++++ b/arch/arm/mach-at91/at91sam9x5_devices.c
+@@ -1879,7 +1879,7 @@ static int at91_set_peripheral_id(unsigned int id, unsigned int direction)
+ {
+ 	unsigned int dst, src;
+ 	switch (id) {
+-	case 0:     /* DBGU */
++	case AT91_ID_SYS:     /* DBGU */
+ 		dst = AT_DMA_ID_DBGU_TX;
+ 		src = AT_DMA_ID_DBGU_RX;
+ 		break;
+@@ -1908,6 +1908,8 @@ static int at91_set_peripheral_id(unsigned int id, unsigned int direction)
+ 		src = AT_DMA_ID_UART1_RX;
+ 		break;
+ 	default:
++		dst = 0;
++		src = 0;
+ 		printk(KERN_ERR "usart %d unsupport!\n", id);
+ 		break;
+ 	}
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0010-serial-at91-Make-DBGU-support-dma-and-pdc-transfer.patch b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0010-serial-at91-Make-DBGU-support-dma-and-pdc-transfer.patch
new file mode 100644
index 0000000..faf6098
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0010-serial-at91-Make-DBGU-support-dma-and-pdc-transfer.patch
@@ -0,0 +1,183 @@
+From fd599168c0ebe37de73d2c6b1aac1399cd373cc6 Mon Sep 17 00:00:00 2001
+From: Elen Song <elen.song@atmel.com>
+Date: Fri, 25 Jan 2013 16:25:12 +0800
+Subject: [PATCH 10/10] serial:at91: Make DBGU support dma and pdc transfer
+
+Because the DBGU lack of receive timeout register, so we use a timer to trigger data receive.
+The DBGU physical address has been map to virtual address by mmu,
+so we use dbgu_resources to save DBGU physical address.
+
+Signed-off-by: Elen Song <elen.song@atmel.com>
+---
+ arch/arm/mach-at91/at91sam9x5_devices.c |    9 +++-
+ drivers/tty/serial/atmel_serial.c       |   72 +++++++++++++++++++++++++------
+ 2 files changed, 66 insertions(+), 15 deletions(-)
+
+diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
+index c1e402d..88d0ca4 100644
+--- a/arch/arm/mach-at91/at91sam9x5_devices.c
++++ b/arch/arm/mach-at91/at91sam9x5_devices.c
+@@ -1540,11 +1540,16 @@ static struct resource dbgu_resources[] = {
+ 		.end	= AT91_ID_SYS,
+ 		.flags	= IORESOURCE_IRQ,
+ 	},
++	[2] = {
++		.start  = AT91_BASE_SYS + AT91_DBGU,
++		.end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
++		.flags  = IORESOURCE_MEM,
++	},
+ };
+ 
+ static struct atmel_uart_data dbgu_data = {
+-	.use_dma_tx	= 0,
+-	.use_dma_rx	= 0,
++	.use_dma_tx	= 1,
++	.use_dma_rx	= 1,
+ 	.regs		= (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
+ };
+ 
+diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
+index d253566..72610c8b 100644
+--- a/drivers/tty/serial/atmel_serial.c
++++ b/drivers/tty/serial/atmel_serial.c
+@@ -39,6 +39,7 @@
+ #include <linux/atmel_pdc.h>
+ #include <linux/atmel_serial.h>
+ #include <linux/uaccess.h>
++#include <linux/timer.h>
+ 
+ #include <asm/io.h>
+ #include <asm/ioctls.h>
+@@ -171,6 +172,8 @@ struct atmel_uart_port {
+ 
+ 	struct serial_rs485	rs485;		/* rs485 settings */
+ 	unsigned int		tx_done_mask;
++	struct timer_list	uart_timer;	/* dbgu timer */
++	resource_size_t		dbgu_phybase;	/* dbgu physical address */
+ };
+ 
+ static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
+@@ -852,7 +855,12 @@ static void atmel_tx_request_dma(struct atmel_uart_port *atmel_port)
+ 	dma_cap_set(DMA_SLAVE, mask);
+ 
+ 	if (atmel_use_dma_tx(port) && pdata->dma_tx_slave) {
+-		pdata->dma_tx_slave->tx_reg = port->mapbase + ATMEL_US_THR;
++		if (port->line == 0)
++			pdata->dma_tx_slave->tx_reg = atmel_port->dbgu_phybase
++							+ ATMEL_US_THR;
++		else
++			pdata->dma_tx_slave->tx_reg = port->mapbase
++							+ ATMEL_US_THR;
+ 		chan = dma_request_channel(mask, filter, pdata->dma_tx_slave);
+ 		if (chan == NULL)
+ 			goto chan_err;
+@@ -918,7 +926,12 @@ static void atmel_rx_request_dma(struct atmel_uart_port *atmel_port)
+ 	dma_cap_set(DMA_CYCLIC, mask);
+ 
+ 	if (atmel_use_dma_rx(port) && pdata->dma_rx_slave) {
+-		pdata->dma_rx_slave->rx_reg = port->mapbase + ATMEL_US_RHR;
++		if (port->line == 0)
++			pdata->dma_rx_slave->rx_reg = atmel_port->dbgu_phybase
++							+ ATMEL_US_RHR;
++		else
++			pdata->dma_rx_slave->rx_reg = port->mapbase
++							+ ATMEL_US_RHR;
+ 		chan = dma_request_channel(mask, filter, pdata->dma_rx_slave);
+ 		if (chan == NULL)
+ 			goto chan_err;
+@@ -1370,6 +1383,15 @@ err_dma:
+ 	return -EINVAL;
+ }
+ 
++static void atmel_uart_timer_callback(unsigned long data)
++{
++	struct uart_port *port = (void *)data;
++	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++
++	tasklet_schedule(&atmel_port->tasklet);
++	mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
++}
++
+ /*
+  * Perform initialization and enable port for reception
+  */
+@@ -1472,18 +1494,34 @@ static int atmel_startup(struct uart_port *port)
+ 
+ 	if (atmel_use_pdc_rx(port)) {
+ 		/* set UART timeout */
+-		UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
+-		UART_PUT_CR(port, ATMEL_US_STTTO);
+-
+-		UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
+-		/* enable PDC controller */
+-		UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
++		if (port->line == 0) {
++			setup_timer(&atmel_port->uart_timer,
++					atmel_uart_timer_callback,
++					(unsigned long)port);
++			mod_timer(&atmel_port->uart_timer,
++					jiffies + uart_poll_timeout(port));
++		} else {
++			UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
++			UART_PUT_CR(port, ATMEL_US_STTTO);
++
++			UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
++		}
++			/* enable PDC controller */
++			UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
+ 	} else if (atmel_use_dma_rx(port)) {
+ 		/* set UART timeout */
+-		UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
+-		UART_PUT_CR(port, ATMEL_US_STTTO);
+-
+-		UART_PUT_IER(port, ATMEL_US_TIMEOUT);
++		if (port->line == 0) {
++			setup_timer(&atmel_port->uart_timer,
++					atmel_uart_timer_callback,
++					(unsigned long)port);
++			mod_timer(&atmel_port->uart_timer,
++					jiffies + uart_poll_timeout(port));
++		} else {
++			UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
++			UART_PUT_CR(port, ATMEL_US_STTTO);
++
++			UART_PUT_IER(port, ATMEL_US_TIMEOUT);
++		}
+ 	} else {
+ 		/* enable receive only */
+ 		UART_PUT_IER(port, ATMEL_US_RXRDY);
+@@ -1532,6 +1570,9 @@ static void atmel_shutdown(struct uart_port *port)
+ 					 DMA_FROM_DEVICE);
+ 			kfree(pdc->buf);
+ 		}
++
++		if (port->line == 0)
++			del_timer_sync(&atmel_port->uart_timer);
+ 	}
+ 	if (atmel_use_pdc_tx(port)) {
+ 		struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
+@@ -1542,8 +1583,11 @@ static void atmel_shutdown(struct uart_port *port)
+ 				 DMA_TO_DEVICE);
+ 	}
+ 
+-	if (atmel_use_dma_rx(port))
++	if (atmel_use_dma_rx(port)) {
+ 		atmel_rx_dma_release(atmel_port);
++		if (port->line == 0)
++			del_timer_sync(&atmel_port->uart_timer);
++	}
+ 	if (atmel_use_dma_tx(port))
+ 		atmel_tx_dma_release(atmel_port);
+ 	/*
+@@ -1945,6 +1989,8 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
+ 	port->mapbase	= pdev->resource[0].start;
+ 	port->irq	= pdev->resource[1].start;
+ 	port->private_data	= data;
++	if (port->line == 0)
++		atmel_port->dbgu_phybase = pdev->resource[2].start;
+ 
+ 	tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
+ 			(unsigned long)port);
+-- 
+1.7.9.5
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/Change-log.txt b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/Change-log.txt
new file mode 100644
index 0000000..d14313c
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/Change-log.txt
@@ -0,0 +1,30 @@
+
+ The rc3 release patch :1st
+
+The rc4 release patch fix:
+1) 	lots of garbled characters showing up
+
+The rc5 release patch fix:
+1)	Tx have CRC error.
+2)	Both TX and RX can use 460800bps to transfer.
+
+
+The rc6 release patch fix:
+1)	RTS/CTS switch will sometimes crashes in tx dma
+2)	460k may sometimes crashes  while change rx ring buffer size.
+?	
+
+The rc7 release patch fix:
+1) 	add bascic usart support
+
+The rc8 release patch fix:
+1) 	shutdown crash
+2) 	polling empty flag
+2) 	switching to pio when dma failed
+
+The rc9 release patch fix:
+1)	tx may crash when transfer in high baudrate
+
+The 1.0 release patch add:
+1)	DBGU dma and PDC support
+
diff --git a/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/how to apply.txt b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/how to apply.txt
new file mode 100644
index 0000000..8542bd1
--- /dev/null
+++ b/multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/how to apply.txt
@@ -0,0 +1,16 @@
+How to apply patch

+

+1. get source code from official site, if you have already gotten one, just skip to point 2.

+

+please refer to:

+http://www.at91.com/linux4sam/bin/view/Linux4SAM/SAM9x5Page#Linux4SAM_AT91SAM9x5_Experimenta

+

+2. apply uart patch:

+

+cd linux-2.6.39

+for p in serial_dma_rx_at91sam9x5_rc3/*.patch ; do patch -p1 < $p; done

+

+if you use git, you can also apply them by:

+

+git am 0001-DMA....and so on.

+

diff --git a/multitech/recipes/linux/linux_2.6.35.bbappend b/multitech/recipes/linux/linux_2.6.35.bbappend
index f23665d..f56e8d0 100644
--- a/multitech/recipes/linux/linux_2.6.35.bbappend
+++ b/multitech/recipes/linux/linux_2.6.35.bbappend
@@ -1,7 +1,7 @@
 FILESEXTRA := "${THISDIR}"
 FILESPATHBASE =. "${FILESEXTRA}:"
 
-PR .= ".corecdp9"
+PR .= ".corecdp12"
 STABLEV = "14"
 
 SRC_URI_mtcdp = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-${PV}.tar.bz2;name=kernel \
@@ -15,7 +15,6 @@ SRC_URI_mtcdp = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-${PV}.tar.bz2;n
                     file://linux-2.6.32.3-atmel_serial_disable_hwhs.patch \
                     file://linux-2.6.35.14-option-zte.patch \
                     file://linux-2.6.32.3-option-telit.patch \
-                    file://linux-2.6.35-at91sam9g20-reset.patch \
                     "
 
 SRC_URI_mt100eocg = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-${PV}.tar.bz2;name=kernel \
@@ -29,7 +28,6 @@ SRC_URI_mt100eocg = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-${PV}.tar.b
                             file://linux-2.6.32.3-atmel_serial_disable_hwhs.patch \
                             file://linux-2.6.35.14-option-zte.patch \
                             file://linux-2.6.32.3-option-telit.patch \
-                            file://linux-2.6.35-at91sam9g20-reset.patch \
                             "
 
 # work around firmware/Makefile issue with make 3.82
diff --git a/multitech/recipes/linux/linux_2.6.39.4.bb b/multitech/recipes/linux/linux_2.6.39.4.bb
new file mode 100644
index 0000000..67c5640
--- /dev/null
+++ b/multitech/recipes/linux/linux_2.6.39.4.bb
@@ -0,0 +1,181 @@
+require recipes/linux/linux.inc
+
+# PR is set by MACHINE_KERNEL_PR in machine config
+
+SRC_URI = " \
+    ${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-${PV}.tar.bz2;name=kernel \
+    "
+
+# 2.6.39-at91 patches from ftp://ftp.linux4sam.org/pub/linux/2.6.39-at91
+AT91SAM9X5_PATCHES = " \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0001-dmaengine-at_hdmac-modify-way-to-use-interrupts.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0002-dmaengine-at_hdmac-add-cyclic-DMA-operation-support.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0003-dmaengine-at_hdmac-debug-information-sg_len-for-prep.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0004-dmaengine-at_hdmac-remove-channel-status-testing-in-.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0005-dmaengine-at_hdmac-specialize-AHB-interfaces-to-opti.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0006-dmaengine-AT91SAM9X5-has-a-Atmel-AHB-DMA-engine.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0007-rtc-at91-workaround-for-5series-ES-chips.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0008-rtc-AT91SAM9X5-has-an-at91_rtc.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0009-ARM-at91-overall-definition-add-5series-support.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0010-ARM-at91-PMC-header-add-5series-support.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0011-ARM-at91-clock-add-5series-chip-family-support.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0012-ARM-at91-AT91SAM9x5-processors-and-EK-board-support.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0013-ARM-at91-provide-defconfig-for-at91sam9x5ek.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0014-usb-AT91SAM9X5-has-EHCI.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0015-ARM-at91-pio-add-new-PIO3a-features.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0016-usb-AT91SAM9X5-has-a-atmel_usba_udc-device.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0017-clocksource-tcb-add-support-for-32-bit-mode.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0018-mmc-atmel-mci-add-support-for-ARCH_AT91SAM9X5.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0019-serial-atmel-convert-to-use-dma-engine.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0020-video-atmel_lcdfb-add-support-for-AT91SAM9x5.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0021-video-atmel_lcdfb-The-output-bpp-should-not-change-a.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0022-input-atmel_tsadcc-add-support-for-ARCH_AT91SAM9X5.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0023-input-atmel_tsadcc-add-touch-screen-pressure-measure.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0024-input-atmel_tsadcc-enable-touchscreen-averaging-and-.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0025-input-atmel_tsadcc-add-ACR-register-and-change-trigg.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0026-MTD-atmel_nand-Add-PMECC-controller-support.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0027-MTD-atmel_nand-optimize-read-write-buffer-functions.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0028-spi-atmel_spi-trivial-change-some-comments.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0029-spi-atmel_spi-add-physical-base-address.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0030-spi-atmel_spi-call-unmapping-on-transfers-buffers.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0031-spi-atmel_spi-status-information-passed-through-cont.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0032-spi-atmel_spi-add-flag-to-controller-data-for-lock-o.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0033-spi-atmel_spi-add-dmaengine-support.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0034-net-can-allow-CAN_AT91-on-AT91SAM9X5.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0035-Input-qt1070-Add-MODULE_DEVICE_TABLE.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0036-Input-qt1070-trivial-fix-CHANGE-line-typo.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0037-Input-qt1070-add-power-management-suspend-resume.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0038-dmaengine-at_hdmac-clear-channel-status-on-channel-r.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0039-dmaengine-at_hdmac-set-residue-as-total-len-in-atc_t.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0040-dmaengine-at_hdmac-implement-pause-and-resume-in-atc.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0041-dmaengine-at_hdmac-pause-no-need-to-wait-for-FIFO-em.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0042-dmaengine-at_hdmac-replace-spin_lock-with-irqsave-va.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0043-dmaengine-at_hdmac-improve-power-management-routines.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0044-sound-atmel-pcm-trivial-typo-in-debug-comment.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0045-sound-atmel-pcm-trivial-typo-in-atmel_pcm_dma_params.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0046-dmaengine-at_hdmac-add-slave-config-operation.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0047-SPI-m25p80-add-serial-flash-IDs.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0048-sound-wm8731-rework-power-management.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0049-atmel-ssc-add-phybase-in-device-structure.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0050-atmel-ssc-dmaengine-usage-switch-depending-on-cpu.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0051-sound-atmel_ssc_dai-fix-ssc-error-path.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0052-sound-atmel_ssc_dai-atmel-pmc-adapt-to-dmaengine-usa.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0053-sound-sam9x5_wm8731-machine-driver-for-at91sam9x5-wm.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0054-mtd-atmel_nand-do-not-scream-while-using-PIO-instead.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0055-MMC-PM-suspend-resume-in-atmel-mci.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0056-ASoc-wm8731-fix-wm8731_check_osc-connected-condition.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0057-ASoc-sam9g20_wm8731-use-the-proper-SYSCKL-value.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0058-sound-atmel_ssc_dai-PM-actually-stopping-clock-on-su.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0059-ARM-at91-sam9x5-increase-CONSISTENT_DMA_SIZE.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0060-SPI-atmel_spi-add-bit-in-mode-register-to-prevent-ov.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0061-media-at91sam9x5-video-new-driver-for-the-high-end-o.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0062-can-at91_can-don-t-align-struct-definitions.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0063-can-at91_can-fix-comment-about-priv-tx_next.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0064-can-at91_can-don-t-copy-data-to-rx-ed-RTR-frames.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0065-can-at91_can-let-get_tx_-functions-return-unsigned-i.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0066-can-at91_can-directly-define-AT91_MB_RX_LAST.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0067-can-at91_can-rename-AT91_MB_RX_MASK-to-AT91_IRQ_MB_R.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0068-can-at91_can-convert-derived-mailbox-constants-into-.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0069-can-at91_can-add-id_table-and-convert-prime-mailbox-.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0070-can-at91_can-register-mb0-sysfs-entry-only-on-at91sa.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0071-can-at91_can-add-support-for-the-AT91SAM9X5-SOCs.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0072-media-V4L-videobuf2-memops-use-pr_debug-for-debug-me.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0073-video-atmelfb-initially-split-atmelfb-into-a-driver-.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0074-video-atmelfb-refactor-core-setup.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0075-video-atmelfb-refactor-start-stop.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0076-video-atmelfb-refactor-isr.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0077-video-atmelfb-refactor-backlight-routines.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0078-video-atmelfb-refactor-dma_update.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0079-video-atmelfb-refactor-LUT.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0080-video-atmelfb-refactor-limit_screeninfo.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0081-arm-at91-refactor-lcdc-includes.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0082-video-atmel_hlcdfb-add-new-driver.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0083-arm-at91-sam9x5-use-new-hlcdc-driver.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0084-arm-at91-sam9x5ek-use-16bpp-as-default-for-fb.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0085-create-platform-device-for-ovl1.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0086-WIP-add-clut-resource.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0087-video-atmel_lcdfb-add-error-msg-when-out-of-memory.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0088-Don-t-shortcut-vb2_reqbufs-in-case-the-format-change.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0089-at91-video-change-atmel-lcdfb-driver-selection-mode.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0090-sound-atmel_ssc_dai-add-a-missing-space-to-an-error-.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0091-at91-add-Atmel-Image-Sensor-Interface-ISI-support.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0092-add-isi-support-in-board-files.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0093-media-at91-add-dumb-set_parm.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0094-AT91-5series-add-ISI-device-and-board-support.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0095-AT91-board-remove-not-needed-comments.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0096-AT91-5series-update-defconfig.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0097-AT91-input-atmel_tsadcc-rework-irq-infrastructure-an.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0098-5series-Update-LCD-timings-to-avoid-flickering.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0099-atmel_lcdfb-change-pixel-clock-ratio-calculation.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0100-MTD-atmel_nand_pmecc-fix-warning-about-uninitialized.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0101-MTD-atmel_nand-fix-wrong-use-of-0-as-NULL.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0102-ASoC-wm8731-active-bit-and-OSC-management.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0103-AT91-at91sam9x5-add-can-clocks-to-9x25-chip.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0104-AT91-LCD-include-remove-not-needed-comment.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0105-AT91-5series-fix-SPI0-MCI1-ISI-pins-conflicts-in-boa.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0106-PMECC-Fix-bug-incorrect-register-address-for-remaind.patch \
+    file://2.6.39-at91-exp.2/2.6.39-at91-exp.2-0107-ARM-at91-add-smd-device-definition.patch \
+    file://serial_dma_rx_at91sam9x5_1.0/0001-DMA-AT91-Get-residual-bytes-in-dma-buffer.patch \
+    file://serial_dma_rx_at91sam9x5_1.0/0002-Serial-Configure-DMAC-configuration-register-for-usa.patch \
+    file://serial_dma_rx_at91sam9x5_1.0/0003-Configure-peripheral-id-and-enable-basic-usart.patch \
+    file://serial_dma_rx_at91sam9x5_1.0/0004-Serial-Enable-Serial-cyclic-DMA-transfer.patch \
+    file://serial_dma_rx_at91sam9x5_1.0/0005-Serial-AT91-Refine-tx-dma.patch \
+    file://serial_dma_rx_at91sam9x5_1.0/0006-Serial-AT91-refine-error-handler-in-probe-stage.patch \
+    file://serial_dma_rx_at91sam9x5_1.0/0007-Serial-AT91-Add-dma-support-for-rs485-and-iso7816.patch \
+    file://serial_dma_rx_at91sam9x5_1.0/0008-Serial-AT91-remove-tx-dma-issue-pending.patch \
+    file://serial_dma_rx_at91sam9x5_1.0/0009-Serial-AT91-Fix-DBGU-peripheral_id-wrong.patch \
+    file://serial_dma_rx_at91sam9x5_1.0/0010-serial-at91-Make-DBGU-support-dma-and-pdc-transfer.patch \
+    file://9x5_pmecc_2639/0001-Revert-MTD-atmel_nand-Add-PMECC-controller-support.patch \
+    file://9x5_pmecc_2639/0002-Revert-MTD-atmel_nand-optimize-read-write-buffer-fun.patch \
+    file://9x5_pmecc_2639/0003-mtd-at91-extract-hw-ecc-initialization-to-one-functi.patch \
+    file://9x5_pmecc_2639/0004-atmel_nand-add-PMECC-parameters-in-nand-structure.patch \
+    file://9x5_pmecc_2639/0005-mtd-at91-atmel_nand-add-Programmable-Multibit-ECC-co.patch \
+    file://9x5_pmecc_2639/0006-atmel_nand-port-to-2.6.39.-modify-function-definitio.patch \
+    file://9x5_pmecc_2639/0007-atmel_nand-pass-the-pmecc-parameter-from-board-file-.patch \
+    file://9x5_pmecc_2639/0008-atmel_nand-9x5ek-enable-PMECC-in-9x5ek-board.patch \
+    file://9x5_pmecc_2639/0009-atmel_nand-enable-dma-for-9x5ek.patch \
+    file://linux-2.6.39-at91-atmel-serial-uart0-rx-timer.patch \
+    "
+
+SRC_URI_append_mtocgd3 = " \
+                    ${AT91SAM9X5_PATCHES} \
+                    file://defconfig \
+                    file://linux-2.6.39.4-mach-at91-mtocgd3.patch \
+                    file://linux-2.6.39.4-macb-force-link.patch \
+                    file://linux-2.6.39.4-ledtrig-netdev.patch \
+                    file://linux-2.6.39.4-at91sam9x5-extreset.patch \
+                    file://linux-2.6.39.4-atmel-mci-force-detect.patch \
+                    file://linux-2.6.39.4-atmel-mci-module-alias.patch \
+                    file://linux-2.6.39.4-wl12xx-sdio-irq.patch \
+                    file://linux-2.6.35.14-at91-gpio-pullup.patch \
+                    file://linux-2.6.32.3-atmel_spi.patch \
+                    file://linux-2.6.32.3-at25.patch \
+                    file://linux-2.6.39.4-atmel_serial_disable_hwhs.patch \
+                    file://linux-2.6.39.4-at91sam9_wdt-10second-timeout.patch \
+                    file://linux-2.6.35.14-option-zte.patch \
+                    file://linux-2.6.39.4-option-telit.patch \
+                    file://linux-2.6.38-sierra-1.7.40.patch \
+                    file://linux-2.6.39.4-cdc-acm-ignore-exar-devices.patch \
+                    "
+
+SRC_URI_append_mt100eocg-pcie-dk = "file://defconfig \
+                            file://linux-2.6.39.4-at91sam9260-reset.patch \
+                            file://linux-2.6.39.4-mach-at91-mt100eocg-pcie-dk.patch \
+                            file://linux-2.6.35.14-at91-gpio-pullup.patch \
+                            file://linux-2.6.32.3-atmel_spi.patch \
+                            file://linux-2.6.32.3-at25.patch \
+                            file://linux-2.6.35.14-option-zte.patch \
+                            file://linux-2.6.38-sierra-1.7.40.patch \
+                            file://linux-2.6.32.3-option-telit.patch \
+                            file://linux-2.6.39.4-mmc-core-maxclock.patch \
+                            file://linux-2.6.39.4-at91-mci-clock-debug.patch \
+                            "
+
+SRC_URI[kernel.md5sum] = "a17c748c2070168f1e784e9605ca043d"
+SRC_URI[kernel.sha256sum] = "d26e44eedbb4bf63f84754bd21640c5d4fee9010320781a5b66c7d2106941183"
+
+# add missing crypto headers
+sysroot_stage_all_append() {
+    kerneldir=${SYSROOT_DESTDIR}${STAGING_KERNEL_DIR}
+    cp -fR include/crypto* $kerneldir/include/
+}
diff --git a/multitech/recipes/meta-java-fixes/icedtea6-native-1.8.11/icedtea-jdk-avoid-cdef-collision.patch b/multitech/recipes/meta-java-fixes/icedtea6-native-1.8.11/icedtea-jdk-avoid-cdef-collision.patch
new file mode 100644
index 0000000..023ce4d
--- /dev/null
+++ b/multitech/recipes/meta-java-fixes/icedtea6-native-1.8.11/icedtea-jdk-avoid-cdef-collision.patch
@@ -0,0 +1,203 @@
+Fixes collisions with standard namespace
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+Upstream-Status: Backport
+
+Index: openjdk/hotspot/src/share/vm/opto/addnode.cpp
+===================================================================
+--- openjdk/hotspot/src/share/vm/opto/addnode.cpp	2010-02-16 19:11:09.000000000 -0800
++++ openjdk/hotspot/src/share/vm/opto/addnode.cpp	2012-07-30 15:54:25.999551792 -0700
+@@ -27,8 +27,6 @@
+ #include "incls/_precompiled.incl"
+ #include "incls/_addnode.cpp.incl"
+ 
+-#define MAXFLOAT        ((float)3.40282346638528860e+38)
+-
+ // Classic Add functionality.  This covers all the usual 'add' behaviors for
+ // an algebraic ring.  Add-integer, add-float, add-double, and binary-or are
+ // all inherited from this class.  The various identity values are supplied
+Index: openjdk/hotspot/src/share/vm/prims/jniCheck.cpp
+===================================================================
+--- openjdk/hotspot/src/share/vm/prims/jniCheck.cpp	2010-02-16 19:11:10.000000000 -0800
++++ openjdk/hotspot/src/share/vm/prims/jniCheck.cpp	2012-07-30 16:05:20.779549364 -0700
+@@ -80,7 +80,7 @@
+     if (env != xenv) {                                                   \
+       NativeReportJNIFatalError(thr, warn_wrong_jnienv);                 \
+     }                                                                    \
+-    __ENTRY(result_type, header, thr)
++    VM_ENTRY_BASE(result_type, header, thr)
+ 
+ 
+ #define UNCHECKED() (unchecked_jni_NativeInterface)
+Index: openjdk/hotspot/src/share/vm/prims/jvmtiEnter.xsl
+===================================================================
+--- openjdk/hotspot/src/share/vm/prims/jvmtiEnter.xsl	2010-02-16 19:11:10.000000000 -0800
++++ openjdk/hotspot/src/share/vm/prims/jvmtiEnter.xsl	2012-07-30 16:03:50.491550815 -0700
+@@ -424,7 +424,7 @@
+     <xsl:value-of select="$space"/>
+     <xsl:text>ThreadInVMfromNative __tiv(current_thread);</xsl:text>
+     <xsl:value-of select="$space"/>
+-    <xsl:text>__ENTRY(jvmtiError, </xsl:text>
++    <xsl:text>VM_ENTRY_BASE(jvmtiError, </xsl:text>
+     <xsl:apply-templates select="." mode="functionid"/>
+     <xsl:text> , current_thread)</xsl:text>
+     <xsl:value-of select="$space"/>
+Index: openjdk/hotspot/src/share/vm/prims/jvmtiEnv.cpp
+===================================================================
+--- openjdk/hotspot/src/share/vm/prims/jvmtiEnv.cpp	2010-02-16 19:11:10.000000000 -0800
++++ openjdk/hotspot/src/share/vm/prims/jvmtiEnv.cpp	2012-07-30 16:04:03.683550594 -0700
+@@ -126,7 +126,7 @@
+     // from native so as to resolve the jthread.
+ 
+     ThreadInVMfromNative __tiv(current_thread);
+-    __ENTRY(jvmtiError, JvmtiEnv::GetThreadLocalStorage , current_thread)
++    VM_ENTRY_BASE(jvmtiError, JvmtiEnv::GetThreadLocalStorage , current_thread)
+     debug_only(VMNativeEntryWrapper __vew;)
+ 
+     oop thread_oop = JNIHandles::resolve_external_guard(thread);
+Index: openjdk/hotspot/src/share/vm/prims/jvmtiExport.cpp
+===================================================================
+--- openjdk/hotspot/src/share/vm/prims/jvmtiExport.cpp	2010-02-16 19:11:10.000000000 -0800
++++ openjdk/hotspot/src/share/vm/prims/jvmtiExport.cpp	2012-07-30 15:59:43.175550785 -0700
+@@ -345,7 +345,7 @@
+     JavaThread* current_thread = (JavaThread*) ThreadLocalStorage::thread();
+     // transition code: native to VM
+     ThreadInVMfromNative __tiv(current_thread);
+-    __ENTRY(jvmtiEnv*, JvmtiExport::get_jvmti_interface, current_thread)
++    VM_ENTRY_BASE(jvmtiEnv*, JvmtiExport::get_jvmti_interface, current_thread)
+     debug_only(VMNativeEntryWrapper __vew;)
+ 
+     JvmtiEnv *jvmti_env = JvmtiEnv::create_a_jvmti(version);
+Index: openjdk/hotspot/src/share/vm/runtime/interfaceSupport.hpp
+===================================================================
+--- openjdk/hotspot/src/share/vm/runtime/interfaceSupport.hpp	2010-02-16 19:11:10.000000000 -0800
++++ openjdk/hotspot/src/share/vm/runtime/interfaceSupport.hpp	2012-07-30 16:36:53.391544578 -0700
+@@ -46,7 +46,7 @@
+   }
+ };
+ 
+-// InterfaceSupport provides functionality used by the __LEAF and __ENTRY
++// InterfaceSupport provides functionality used by the VM_LEAF_BASE and VM_ENTRY_BASE
+ // macros. These macros are used to guard entry points into the VM and
+ // perform checks upon leave of the VM.
+ 
+@@ -391,7 +391,7 @@
+ 
+ // LEAF routines do not lock, GC or throw exceptions
+ 
+-#define __LEAF(result_type, header)                                  \
++#define VM_LEAF_BASE(result_type, header)                                  \
+   TRACE_CALL(result_type, header)                                    \
+   debug_only(NoHandleMark __hm;)                                     \
+   /* begin of body */
+@@ -399,7 +399,7 @@
+ 
+ // ENTRY routines may lock, GC and throw exceptions
+ 
+-#define __ENTRY(result_type, header, thread)                         \
++#define VM_ENTRY_BASE(result_type, header, thread)                         \
+   TRACE_CALL(result_type, header)                                    \
+   HandleMarkCleaner __hm(thread);                                    \
+   Thread* THREAD = thread;                                           \
+@@ -421,20 +421,20 @@
+ #define IRT_ENTRY(result_type, header)                               \
+   result_type header {                                               \
+     ThreadInVMfromJava __tiv(thread);                                \
+-    __ENTRY(result_type, header, thread)                             \
++    VM_ENTRY_BASE(result_type, header, thread)                             \
+     debug_only(VMEntryWrapper __vew;)
+ 
+ 
+ #define IRT_LEAF(result_type, header)                                \
+   result_type header {                                               \
+-    __LEAF(result_type, header)                                      \
++    VM_LEAF_BASE(result_type, header)                                      \
+     debug_only(No_Safepoint_Verifier __nspv(true);)
+ 
+ 
+ #define IRT_ENTRY_NO_ASYNC(result_type, header)                      \
+   result_type header {                                               \
+     ThreadInVMfromJavaNoAsyncException __tiv(thread);                \
+-    __ENTRY(result_type, header, thread)                             \
++    VM_ENTRY_BASE(result_type, header, thread)                             \
+     debug_only(VMEntryWrapper __vew;)
+ 
+ // Another special case for nmethod_entry_point so the nmethod that the
+@@ -445,7 +445,7 @@
+   result_type header {                                               \
+     nmethodLocker _nmlock(nm);                                       \
+     ThreadInVMfromJavaNoAsyncException __tiv(thread);                                \
+-    __ENTRY(result_type, header, thread)
++    VM_ENTRY_BASE(result_type, header, thread)
+ 
+ #define IRT_END }
+ 
+@@ -455,20 +455,20 @@
+ #define JRT_ENTRY(result_type, header)                               \
+   result_type header {                                               \
+     ThreadInVMfromJava __tiv(thread);                                \
+-    __ENTRY(result_type, header, thread)                             \
++    VM_ENTRY_BASE(result_type, header, thread)                             \
+     debug_only(VMEntryWrapper __vew;)
+ 
+ 
+ #define JRT_LEAF(result_type, header)                                \
+   result_type header {                                               \
+-  __LEAF(result_type, header)                                        \
++  VM_LEAF_BASE(result_type, header)                                        \
+   debug_only(JRT_Leaf_Verifier __jlv;)
+ 
+ 
+ #define JRT_ENTRY_NO_ASYNC(result_type, header)                      \
+   result_type header {                                               \
+     ThreadInVMfromJavaNoAsyncException __tiv(thread);                \
+-    __ENTRY(result_type, header, thread)                             \
++    VM_ENTRY_BASE(result_type, header, thread)                             \
+     debug_only(VMEntryWrapper __vew;)
+ 
+ // Same as JRT Entry but allows for return value after the safepoint
+@@ -501,7 +501,7 @@
+     assert( !VerifyJNIEnvThread || (thread == Thread::current()), "JNIEnv is only valid in same thread"); \
+     ThreadInVMfromNative __tiv(thread);                              \
+     debug_only(VMNativeEntryWrapper __vew;)                          \
+-    __ENTRY(result_type, header, thread)
++    VM_ENTRY_BASE(result_type, header, thread)
+ 
+ 
+ // Ensure that the VMNativeEntryWrapper constructor, which can cause
+@@ -521,7 +521,7 @@
+   result_type JNICALL header {                                \
+     JavaThread* thread=JavaThread::thread_from_jni_environment(env); \
+     assert( !VerifyJNIEnvThread || (thread == Thread::current()), "JNIEnv is only valid in same thread"); \
+-    __LEAF(result_type, header)
++    VM_LEAF_BASE(result_type, header)
+ 
+ 
+ // Close the routine and the extern "C"
+@@ -537,7 +537,7 @@
+     JavaThread* thread=JavaThread::thread_from_jni_environment(env); \
+     ThreadInVMfromNative __tiv(thread);                              \
+     debug_only(VMNativeEntryWrapper __vew;)                          \
+-    __ENTRY(result_type, header, thread)
++    VM_ENTRY_BASE(result_type, header, thread)
+ 
+ 
+ #define JVM_ENTRY_NO_ENV(result_type, header)                        \
+@@ -546,7 +546,7 @@
+     JavaThread* thread = (JavaThread*)ThreadLocalStorage::thread();  \
+     ThreadInVMfromNative __tiv(thread);                              \
+     debug_only(VMNativeEntryWrapper __vew;)                          \
+-    __ENTRY(result_type, header, thread)
++    VM_ENTRY_BASE(result_type, header, thread)
+ 
+ 
+ #define JVM_QUICK_ENTRY(result_type, header)                         \
+@@ -562,7 +562,7 @@
+ extern "C" {                                                         \
+   result_type JNICALL header {                                       \
+     VM_Exit::block_if_vm_exited();                                   \
+-    __LEAF(result_type, header)
++    VM_LEAF_BASE(result_type, header)
+ 
+ 
+ #define JVM_END } }
diff --git a/multitech/recipes/meta-java-fixes/icedtea6-native_1.8.11.bbappend b/multitech/recipes/meta-java-fixes/icedtea6-native_1.8.11.bbappend
new file mode 100644
index 0000000..24e779d
--- /dev/null
+++ b/multitech/recipes/meta-java-fixes/icedtea6-native_1.8.11.bbappend
@@ -0,0 +1,7 @@
+FILESEXTRA := "${THISDIR}"
+FILESPATHBASE =. "${FILESEXTRA}:"
+
+PR .= ".corecdp1"
+
+SRC_URI += "file://icedtea-jdk-avoid-cdef-collision.patch;apply=no"
+DISTRIBUTION_PATCHES += "patches/icedtea-jdk-avoid-cdef-collision.patch"
diff --git a/multitech/recipes/multitech/config/ppp/peers/gsm b/multitech/recipes/multitech/config/ppp/peers/gsm
index f17fcff..d23957e 100644
--- a/multitech/recipes/multitech/config/ppp/peers/gsm
+++ b/multitech/recipes/multitech/config/ppp/peers/gsm
@@ -3,7 +3,7 @@ linkname ppp0
 defaultroute
 replacedefaultroute
 usepeerdns
-ipcp-max-failure 4
+ipcp-max-failure 10
 ipcp-restart 10
 noauth
 crtscts
diff --git a/multitech/recipes/multitech/config_1.0.bb b/multitech/recipes/multitech/config_1.0.bb
index 20b5de4..8d3ee99 100644
--- a/multitech/recipes/multitech/config_1.0.bb
+++ b/multitech/recipes/multitech/config_1.0.bb
@@ -1,7 +1,7 @@
 DESCRIPTION = "Provides default system config files and /var/config fs"
 SECTION = "base"
 LICENSE = "GPL"
-PR = "r14"
+PR = "r15"
 
 inherit update-rc.d
 
diff --git a/multitech/recipes/multitech/mts-id-eeprom.inc b/multitech/recipes/multitech/mts-id-eeprom.inc
new file mode 100644
index 0000000..17e8a6a
--- /dev/null
+++ b/multitech/recipes/multitech/mts-id-eeprom.inc
@@ -0,0 +1,14 @@
+DESCRIPTION = "ID EEPROM tool for MTCDP"
+HOMEPAGE = "http://www.multitech.net/"
+SECTION = "console/utils"
+PRIORITY = "optional"
+LICENSE = "GPL"
+INC_PR = "r0"
+DEPENDS = "mts-io"
+
+SRC_URI = "git://git.multitech.net/mts-id-eeprom.git;protocol=git;tag=${PV}"
+S = "${WORKDIR}/git"
+
+inherit autotools
+
+PARALLEL_MAKE = ""
diff --git a/multitech/recipes/multitech/mts-id-eeprom_0.0.1.bb b/multitech/recipes/multitech/mts-id-eeprom_0.0.1.bb
index 8a3a310..ccf3521 100644
--- a/multitech/recipes/multitech/mts-id-eeprom_0.0.1.bb
+++ b/multitech/recipes/multitech/mts-id-eeprom_0.0.1.bb
@@ -1,14 +1,3 @@
-DESCRIPTION = "ID EEPROM tool for MTCDP"
-HOMEPAGE = "http://www.multitech.net/"
-SECTION = "console/utils"
-PRIORITY = "optional"
-LICENSE = "GPL"
-PR = "r0"
-DEPENDS = "mts-io"
+require mts-id-eeprom.inc
 
-SRC_URI = "git://git.multitech.net/mts-id-eeprom.git;protocol=git;tag=${PV}"
-S = "${WORKDIR}/git"
-
-inherit autotools
-
-PARALLEL_MAKE = ""
+PR = "${INC_PR}.0"
diff --git a/multitech/recipes/multitech/mts-id-eeprom_0.1.0.bb b/multitech/recipes/multitech/mts-id-eeprom_0.1.0.bb
new file mode 100644
index 0000000..ccf3521
--- /dev/null
+++ b/multitech/recipes/multitech/mts-id-eeprom_0.1.0.bb
@@ -0,0 +1,3 @@
+require mts-id-eeprom.inc
+
+PR = "${INC_PR}.0"
diff --git a/multitech/recipes/multitech/mts-io/mt100eocg-pcie-dk/mts-io.init b/multitech/recipes/multitech/mts-io/mt100eocg-pcie-dk/mts-io.init
new file mode 100644
index 0000000..7c285ec
--- /dev/null
+++ b/multitech/recipes/multitech/mts-io/mt100eocg-pcie-dk/mts-io.init
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+case $1 in
+  start)
+    echo "Loading mts-io module"
+    modprobe mts_io
+    # reset module if MTPCIE-X was not detected
+    if ! lsusb | grep -q 'ID 1bc7:'; then
+      echo "Restarting radio"
+      radio-reset-h5
+    fi
+    ;;
+
+  stop)
+    echo "Unloading mts-io module"
+    modprobe -r mts_io
+    ;;
+
+  *)
+    echo "Usage: $0 {start|stop}"
+    exit 2
+    ;;
+esac
+
+
diff --git a/multitech/recipes/multitech/mts-io/mt100eocg-pcie-dk/radio-reset-h5 b/multitech/recipes/multitech/mts-io/mt100eocg-pcie-dk/radio-reset-h5
new file mode 100755
index 0000000..02e43d8
--- /dev/null
+++ b/multitech/recipes/multitech/mts-io/mt100eocg-pcie-dk/radio-reset-h5
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+# This script works around an H5 radio quirk by disabling USB and 
+# waiting for the radio to power up before re-enabling it.  Note that
+# this will disable all USB devices connected to the USB host controller
+# until the reset is finished.  USB device port is not affected.
+
+pin="gpo3"
+
+rmmod ohci_hcd
+# toggle onoff pin
+mts-io-sysfs store $pin 1
+usleep 200000
+mts-io-sysfs store $pin 0
+sleep 15
+modprobe ohci_hcd
diff --git a/multitech/recipes/multitech/mts-io/mts-io-0.6.0-pcieh5.patch b/multitech/recipes/multitech/mts-io/mts-io-0.6.0-pcieh5.patch
new file mode 100644
index 0000000..714f33c
--- /dev/null
+++ b/multitech/recipes/multitech/mts-io/mts-io-0.6.0-pcieh5.patch
@@ -0,0 +1,84 @@
+--- a/mts-io.c	2013-04-08 13:11:16.845089948 -0500
++++ b/mts_io.c	2013-04-09 11:16:57.892482724 -0500
+@@ -349,21 +349,23 @@
+ 		.use_pullup = 0,
+ 		.active_low = 1,
+ 	},
++	// MTPCIE-H5: Wifi and BT enable pins
++	// (was TXD1 and DTR1) (PB17 and PB7 are tied together)
+ 	{
+-		.name = "TXD1",
+-		.pin = AT91_PIN_PB17,
+-		.direction = GPIO_DIR_INPUT,
++		.name = "WLAN_EN",
++		.attr_name = "wlan-enabled",
++		.pin = AT91_PIN_PB7,
++		.direction = GPIO_DIR_OUTPUT,
+ 		.output_value = 0,
+ 		.use_pullup = 0,
+ 	},
+ 	{
+-		.name = "DTR1",
+-		.attr_name = "extserial-dtr",
++		.name = "BT_EN",
++		.attr_name = "bt-enabled",
+ 		.pin = AT91_PIN_PB18,
+-		.direction = GPIO_DIR_INPUT,
++		.direction = GPIO_DIR_OUTPUT,
+ 		.output_value = 0,
+ 		.use_pullup = 0,
+-		.active_low = 1,
+ 	},
+ 	{
+ 		.name = "DCD1",
+@@ -374,6 +376,8 @@
+ 		.use_pullup = 0,
+ 		.active_low = 1,
+ 	},
++	// PCIE-H5 GPIO11 used for WLAN_IRQ
++#if 0
+ 	{
+ 		.name = "GPIO11",
+ 		.attr_name = "gpio11",
+@@ -382,6 +386,7 @@
+ 		.output_value = 1,
+ 		.use_pullup = 1,
+ 	},
++#endif
+ 	{
+ 		.name = "GPIO12",
+ 		.attr_name = "gpio12",
+@@ -1904,13 +1909,13 @@
+ 	mts_attr_show_gpio_pin, mts_attr_store_radio_reset_telit);
+ 
+ static struct attribute *mt100eocg_platform_attributes[] = {
+-	&dev_attr_extserial_dtr.attr,
+ 	&dev_attr_extserial_dcd_gpio.attr,
+ 	&dev_attr_rsersrc.attr,
+ 	&dev_attr_radio_reset.attr,
+ 	&dev_attr_eth0_enabled.attr,
+-	&dev_attr_gpio11.attr,
+ 	&dev_attr_gpio12.attr,
++	&dev_attr_bt_enabled.attr,
++	&dev_attr_wlan_enabled.attr,
+ 
+ 	&dev_attr_gpo1.attr,
+ 	&dev_attr_gpo2.attr,
+@@ -2134,7 +2139,7 @@
+ 		return tmp;
+ 	}
+ 
+-	spi_dout_value = 0x00;
++	spi_dout_value = 0xFF;	// 0x00
+ 	spi_writen(spi, &spi_dout_value, 1);
+ 
+ 	spi_dout_dev = spi;
+@@ -2267,6 +2272,8 @@
+ 		mts_product_id = MTCDP_E1_DK_0_0;
+ 		log_info("detected board %s", HW_VERSION_MTCDP_0_0);
+ 	} else if (strncmp(id_eeprom.product_id, PRODUCT_ID_MT100EOCG, strlen(PRODUCT_ID_MT100EOCG)) == 0) {
++		DEVICE_CAPA_SET(id_eeprom.capa, CAPA_WIFI);
++		DEVICE_CAPA_SET(id_eeprom.capa, CAPA_BLUETOOTH);
+ 		attr_group = &mt100eocg_platform_attribute_group;
+ 		gpio_pins = gpio_pins_mt100eocg_0_0;
+ 		mts_product_id = MT100EOCG_0_0;
diff --git a/multitech/recipes/multitech/mts-io/mts-io-pcieh5.patch b/multitech/recipes/multitech/mts-io/mts-io-pcieh5.patch
new file mode 100644
index 0000000..15a1e28
--- /dev/null
+++ b/multitech/recipes/multitech/mts-io/mts-io-pcieh5.patch
@@ -0,0 +1,226 @@
+Index: io-module/mts_io.c
+===================================================================
+--- io-module.orig/mts_io.c
++++ io-module/mts_io.c
+@@ -317,17 +317,19 @@ static struct gpio_pin gpio_pins_mt100eo
+ 		.output_value = 1,
+ 		.use_pullup = 0,
+ 	},
++	// MTPCIE-H5: Wifi and BT enable pins 
++	// (was TXD1 and DTR1) (PB17 and PB7 are tied together)
+ 	{
+-		.name = "TXD1",
+-		.pin = AT91_PIN_PB17,
+-		.direction = GPIO_DIR_INPUT,
++		.name = "WLAN_EN",
++		.pin = AT91_PIN_PB7,
++		.direction = GPIO_DIR_OUTPUT,
+ 		.output_value = 0,
+ 		.use_pullup = 0,
+ 	},
+ 	{
+-		.name = "DTR1",
++		.name = "BT_EN",
+ 		.pin = AT91_PIN_PB18,
+-		.direction = GPIO_DIR_INPUT,
++		.direction = GPIO_DIR_OUTPUT,
+ 		.output_value = 0,
+ 		.use_pullup = 0,
+ 	},
+@@ -338,6 +340,8 @@ static struct gpio_pin gpio_pins_mt100eo
+ 		.output_value = 1,
+ 		.use_pullup = 0,
+ 	},
++	// PCIE-H5 GPIO11 used for WLAN_IRQ
++#if 0
+ 	{
+ 		.name = "GPIO11",
+ 		.pin = AT91_PIN_PB19,
+@@ -345,6 +349,7 @@ static struct gpio_pin gpio_pins_mt100eo
+ 		.output_value = 1,
+ 		.use_pullup = 1,
+ 	},
++#endif
+ 	{
+ 		.name = "GPIO12",
+ 		.pin = AT91_PIN_PB20,
+@@ -400,6 +405,13 @@ static int mts_id_eeprom_load(void)
+ 		mts_product_id = MTCDP_E1_DK_1_0;
+ 	}
+ 
++	// PCIE-H5 hard-coded to EOCG
++	gpio_pins = gpio_pins_mt100eocg_0_0;
++	mts_product_id = MT100EOCG_0_0;
++	DEVICE_CAPA_SET(id_eeprom.capa, CAPA_GPS);
++	DEVICE_CAPA_SET(id_eeprom.capa, CAPA_DIN);
++	DEVICE_CAPA_SET(id_eeprom.capa, CAPA_DOUT);
++
+ 	log_info("sizeof: %lu", (unsigned long) sizeof(struct mts_id_eeprom_layout));
+ 	log_info("vendor-id: %.32s", id_eeprom.vendor_id);
+ 	log_info("product-id: %.32s",  id_eeprom.product_id);
+@@ -1976,6 +1988,100 @@ static ssize_t mts_attr_store_cd(struct 
+ 	return count;
+ }
+ 
++static ssize_t mts_attr_show_bt_enabled(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int value;
++	struct gpio_pin *pin = gpio_pin_by_name("BT_EN");
++
++	if (!pin) {
++		return -ENODEV;
++	}
++
++	mutex_lock(&mts_io_mutex);
++
++	value = at91_get_gpio_value(pin->pin);
++
++	mutex_unlock(&mts_io_mutex);
++
++	if (value < 0) {
++		return value;
++	}
++
++	return sprintf(buf, "%d\n", value);
++}
++
++static ssize_t mts_attr_store_bt_enabled(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t count)
++{
++	int value;
++	int err;
++	struct gpio_pin *pin = gpio_pin_by_name("BT_EN");
++
++	if (!pin) {
++		return -ENODEV;
++	}
++
++	if (sscanf(buf, "%i", &value) != 1) {
++		return -EINVAL;
++	}
++
++	mutex_lock(&mts_io_mutex);
++
++	err = at91_set_gpio_value(pin->pin, value);
++
++	mutex_unlock(&mts_io_mutex);
++
++	return count;
++}
++
++static ssize_t mts_attr_show_wlan_enabled(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int value;
++	struct gpio_pin *pin = gpio_pin_by_name("WLAN_EN");
++
++	if (!pin) {
++		return -ENODEV;
++	}
++
++	mutex_lock(&mts_io_mutex);
++
++	value = at91_get_gpio_value(pin->pin);
++
++	mutex_unlock(&mts_io_mutex);
++
++	if (value < 0) {
++		return value;
++	}
++
++	return sprintf(buf, "%d\n", value);
++}
++
++static ssize_t mts_attr_store_wlan_enabled(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t count)
++{
++	int value;
++	int err;
++	struct gpio_pin *pin = gpio_pin_by_name("WLAN_EN");
++
++	if (!pin) {
++		return -ENODEV;
++	}
++
++	if (sscanf(buf, "%i", &value) != 1) {
++		return -EINVAL;
++	}
++
++	mutex_lock(&mts_io_mutex);
++
++	err = at91_set_gpio_value(pin->pin, value);
++
++	mutex_unlock(&mts_io_mutex);
++
++	return count;
++}
++
+ 
+ static struct device_attribute dev_attr_gpo1 = {
+ 	.attr = {
+@@ -2137,6 +2243,24 @@ static struct device_attribute dev_attr_
+ 	.store = mts_attr_store_gpio12,
+ };
+ 
++static struct device_attribute dev_attr_bt_enabled = {
++	.attr = {
++		.name = "bt-enabled",
++		.mode = MTS_ATTR_MODE_RW,
++	},
++	.show = mts_attr_show_bt_enabled,
++	.store = mts_attr_store_bt_enabled,
++};
++
++static struct device_attribute dev_attr_wlan_enabled = {
++	.attr = {
++		.name = "wlan-enabled",
++		.mode = MTS_ATTR_MODE_RW,
++	},
++	.show = mts_attr_show_wlan_enabled,
++	.store = mts_attr_store_wlan_enabled,
++};
++
+ static struct device_attribute dev_attr_rsersrc = {
+ 	.attr = {
+ 		.name = "rsersrc",
+@@ -2157,13 +2281,13 @@ static struct device_attribute dev_attr_
+ 
+ 
+ static struct attribute *mt100eocg_platform_attributes[] = {
+-	&dev_attr_extserial_dtr.attr,
+ 	&dev_attr_extserial_cd.attr,
+ 	&dev_attr_rsersrc.attr,
+ 	&dev_attr_radio_reset.attr,
+ 	&dev_attr_eth0_enabled.attr,
+-	&dev_attr_gpio11.attr,
+ 	&dev_attr_gpio12.attr,
++	&dev_attr_bt_enabled.attr,
++	&dev_attr_wlan_enabled.attr,
+ 
+ 	&dev_attr_gpo1.attr,
+ 	&dev_attr_gpo2.attr,
+@@ -2323,7 +2447,7 @@ static int __devinit mts_spi_dout_probe(
+ 		return tmp;
+ 	}
+ 
+-	spi_dout_value = 0x00;
++	spi_dout_value = 0xFF;	// 0x00;
+ 	spi_writen(spi, &spi_dout_value, 1);
+ 
+ 	spi_dout_dev = spi;
+@@ -2521,11 +2645,14 @@ static int __init mts_io_init(void)
+ 
+ 	if ( mts_product_id == MT100EOCG_0_0 ) {
+ 		//Set open drain for GPIO11 and GPIO12 using multi drive
++	// PCIE-H5 GPIO11 used for WLAN_IRQ
++#if 0
+ 		pin = gpio_pin_by_name("GPIO11");
+ 		if (pin) {
+ 			log_info("Set open drain for GPIO11");
+ 			at91_set_multi_drive(pin->pin, true);
+ 		}
++#endif
+ 		pin = gpio_pin_by_name("GPIO12");
+ 		if (pin) {
+ 			log_info("Set open drain for GPIO12");
diff --git a/multitech/recipes/multitech/mts-io_0.5.1.bb b/multitech/recipes/multitech/mts-io_0.5.1.bb
index f903020..2ddf14c 100644
--- a/multitech/recipes/multitech/mts-io_0.5.1.bb
+++ b/multitech/recipes/multitech/mts-io_0.5.1.bb
@@ -1,3 +1,5 @@
 require mts-io.inc
 
-PR = "${INC_PR}.0"
+PR = "${INC_PR}.1"
+
+SRC_URI_append_mt100eocg-pcie-dk = " file://mts-io-pcieh5.patch"
diff --git a/multitech/recipes/multitech/mts-io_0.6.0.bb b/multitech/recipes/multitech/mts-io_0.6.0.bb
new file mode 100644
index 0000000..03590f6
--- /dev/null
+++ b/multitech/recipes/multitech/mts-io_0.6.0.bb
@@ -0,0 +1,14 @@
+require mts-io.inc
+
+SRCREV="531db3c06b8ca00b2038adfa407c5681d8416734"
+
+SRC_URI = " \
+    file://mts-io.init \
+    file://radio-reset-h5 \
+    git://git.multitech.net/cdp-io-controller.git;protocol=git;branch=master;tag=${SRCREV} \
+"
+
+SRC_URI_append_mt100eocg-pcie-dk = " file://mts-io-0.6.0-pcieh5.patch"
+
+LOCAL_PR = "${INC_PR}.14"
+MACHINE_KERNEL_PR_append = "${LOCAL_PR}"
diff --git a/multitech/recipes/sysvinit/sysvinit/sysvinit-2.86-define_enoioctlcmd.patch b/multitech/recipes/sysvinit/sysvinit/sysvinit-2.86-define_enoioctlcmd.patch
new file mode 100644
index 0000000..49255bf
--- /dev/null
+++ b/multitech/recipes/sysvinit/sysvinit/sysvinit-2.86-define_enoioctlcmd.patch
@@ -0,0 +1,14 @@
+Index: sysvinit-2.86/src/bootlogd.c
+===================================================================
+--- sysvinit-2.86.orig/src/bootlogd.c	2013-01-24 14:18:49.561303519 -0600
++++ sysvinit-2.86/src/bootlogd.c	2013-01-24 14:18:52.061303680 -0600
+@@ -228,6 +228,9 @@
+ 	}
+ 
+ #ifdef TIOCGDEV
++# ifndef  ENOIOCTLCMD
++#  define ENOIOCTLCMD	515
++# endif
+ 	if (ioctl(0, TIOCGDEV, &kdev) == 0)
+ 		return findtty(res, rlen, (dev_t)kdev);
+ 	if (errno != ENOIOCTLCMD) return -1;
diff --git a/multitech/recipes/sysvinit/sysvinit_2.86.bbappend b/multitech/recipes/sysvinit/sysvinit_2.86.bbappend
index bc4d4ac..096349c 100644
--- a/multitech/recipes/sysvinit/sysvinit_2.86.bbappend
+++ b/multitech/recipes/sysvinit/sysvinit_2.86.bbappend
@@ -1,2 +1,6 @@
 FILESEXTRA := "${THISDIR}"
 FILESPATHBASE =. "${FILESEXTRA}:"
+
+PR .= ".corecdp1"
+
+SRC_URI += "file://sysvinit-2.86-define_enoioctlcmd.patch"
diff --git a/multitech/recipes/ti/ti-wifi-utils_git.bbappend b/multitech/recipes/ti/ti-wifi-utils_git.bbappend
new file mode 100644
index 0000000..790257a
--- /dev/null
+++ b/multitech/recipes/ti/ti-wifi-utils_git.bbappend
@@ -0,0 +1,3 @@
+PV = "0.2"
+SRCREV = "05dc3b63f0a710c83c89755ffdd9e9c5f8aab5c4"
+SRC_URI = "git://github.com/TI-OpenLink/ti-utils.git;protocol=git"
diff --git a/multitech/recipes/u-boot/u-boot-1.3.4/mt100eocg-pcie-dk/fw_env.config b/multitech/recipes/u-boot/u-boot-1.3.4/mt100eocg-pcie-dk/fw_env.config
new file mode 100644
index 0000000..41b9605
--- /dev/null
+++ b/multitech/recipes/u-boot/u-boot-1.3.4/mt100eocg-pcie-dk/fw_env.config
@@ -0,0 +1,7 @@
+# Configuration file for fw_{printenv,setenv} utility.
+# Up to two entries are valid, in this case the redundant
+# environment sector is assumed present.
+
+# MTD device name	Device offset	Env. size	Flash sector size
+/dev/mtd3		0x0000		0x20000		0x20000
+/dev/mtd4		0x0000		0x20000		0x20000
diff --git a/multitech/recipes/u-boot/u-boot-1.3.4/mt100eocg-pcie-dk/u-boot-1.3.4-mts.patch b/multitech/recipes/u-boot/u-boot-1.3.4/mt100eocg-pcie-dk/u-boot-1.3.4-mts.patch
new file mode 100644
index 0000000..4d05ba3
--- /dev/null
+++ b/multitech/recipes/u-boot/u-boot-1.3.4/mt100eocg-pcie-dk/u-boot-1.3.4-mts.patch
@@ -0,0 +1,3298 @@
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9260ek/at91sam9260ek.c u-boot-1.3.4/board/atmel/at91sam9260ek/at91sam9260ek.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9260ek/at91sam9260ek.c	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/board/atmel/at91sam9260ek/at91sam9260ek.c	2010-03-25 16:45:59.000000000 -0500
+@@ -125,6 +125,8 @@ static void at91sam9260ek_spi_hw_init(vo
+ #ifdef CONFIG_MACB
+ static void at91sam9260ek_macb_hw_init(void)
+ {
++	unsigned long rstc;
++	
+ 	/* Enable clock */
+ 	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+ 
+@@ -147,6 +149,8 @@ static void at91sam9260ek_macb_hw_init(v
+ 	       pin_to_mask(AT91_PIN_PA28),
+ 	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+ 
++	rstc = at91_sys_read(AT91_RSTC_MR);
++	
+ 	/* Need to reset PHY -> 500ms reset */
+ 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ 				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
+@@ -159,9 +163,8 @@ static void at91sam9260ek_macb_hw_init(v
+ 
+ 	/* Restore NRST value */
+ 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+-				     (AT91_RSTC_ERSTL & (0x0 << 8)) |
++				     (rstc) |
+ 				     AT91_RSTC_URSTEN);
+-
+ 	/* Re-enable pull-up */
+ 	writel(pin_to_mask(AT91_PIN_PA14) |
+ 	       pin_to_mask(AT91_PIN_PA15) |
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9263ek/at91sam9263ek.c u-boot-1.3.4/board/atmel/at91sam9263ek/at91sam9263ek.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9263ek/at91sam9263ek.c	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/board/atmel/at91sam9263ek/at91sam9263ek.c	2010-03-25 16:45:59.000000000 -0500
+@@ -128,6 +128,8 @@ static void at91sam9263ek_spi_hw_init(vo
+ #ifdef CONFIG_MACB
+ static void at91sam9263ek_macb_hw_init(void)
+ {
++	unsigned long rstc;
++	
+ 	/* Enable clock */
+ 	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+ 
+@@ -145,6 +147,8 @@ static void at91sam9263ek_macb_hw_init(v
+ 	       pin_to_mask(AT91_PIN_PE26),
+ 	       pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
+ 
++	rstc = at91_sys_read(AT91_RSTC_MR);
++	
+ 	/* Need to reset PHY -> 500ms reset */
+ 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ 				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
+@@ -157,7 +161,7 @@ static void at91sam9263ek_macb_hw_init(v
+ 
+ 	/* Restore NRST value */
+ 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+-				     (AT91_RSTC_ERSTL & (0x0 << 8)) |
++				     (rstc) |
+ 				     AT91_RSTC_URSTEN);
+ 
+ 	/* Re-enable pull-up */
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/at91sam9g10ek.c u-boot-1.3.4/board/atmel/at91sam9g10ek/at91sam9g10ek.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/at91sam9g10ek.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g10ek/at91sam9g10ek.c	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,281 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/at91sam9261.h>
++#include <asm/arch/at91sam9261_matrix.h>
++#include <asm/arch/at91sam9_smc.h>
++#include <asm/arch/at91_pmc.h>
++#include <asm/arch/at91_rstc.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/io.h>
++#include <lcd.h>
++#include <atmel_lcdc.h>
++#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
++#include <net.h>
++#endif
++
++DECLARE_GLOBAL_DATA_PTR;
++
++/* ------------------------------------------------------------------------- */
++/*
++ * Miscelaneous platform dependent initialisations
++ */
++
++static void at91sam9g10ek_serial_hw_init(void)
++{
++#ifdef CONFIG_USART0
++	at91_set_A_periph(AT91_PIN_PC8, 1);		/* TXD0 */
++	at91_set_A_periph(AT91_PIN_PC9, 0);		/* RXD0 */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
++#endif
++
++#ifdef CONFIG_USART1
++	at91_set_A_periph(AT91_PIN_PC12, 1);		/* TXD1 */
++	at91_set_A_periph(AT91_PIN_PC13, 0);		/* RXD1 */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
++#endif
++
++#ifdef CONFIG_USART2
++	at91_set_A_periph(AT91_PIN_PC14, 1);		/* TXD2 */
++	at91_set_A_periph(AT91_PIN_PC15, 0);		/* RXD2 */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
++#endif
++
++#ifdef CONFIG_USART3	/* DBGU */
++	at91_set_A_periph(AT91_PIN_PA9, 0);		/* DRXD */
++	at91_set_A_periph(AT91_PIN_PA10, 1);		/* DTXD */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
++#endif
++}
++
++#ifdef CONFIG_CMD_NAND
++static void at91sam9g10ek_nand_hw_init(void)
++{
++	unsigned long csa;
++
++	/* Enable CS3 */
++	csa = at91_sys_read(AT91_MATRIX_EBICSA);
++	at91_sys_write(AT91_MATRIX_EBICSA,
++		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
++
++	/* Configure SMC CS3 for NAND/SmartMedia */
++	at91_sys_write(AT91_SMC_SETUP(3),
++			/*
++		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
++		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
++			   */
++		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
++		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
++	at91_sys_write(AT91_SMC_PULSE(3),
++			/*
++		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
++		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
++			   */
++		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) |
++		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7));
++	at91_sys_write(AT91_SMC_CYCLE(3),
++			/*
++		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
++			   */
++		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
++	at91_sys_write(AT91_SMC_MODE(3),
++		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
++		       AT91_SMC_EXNWMODE_DISABLE |
++#ifdef CFG_NAND_DBW_16
++		       AT91_SMC_DBW_16 |
++#else /* CFG_NAND_DBW_8 */
++		       AT91_SMC_DBW_8 |
++#endif
++		       AT91_SMC_TDF_(2));
++
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
++
++	/* Configure RDY/BSY */
++	at91_set_gpio_input(AT91_PIN_PC15, 1);
++
++	/* Enable NandFlash */
++	at91_set_gpio_output(AT91_PIN_PC14, 1);
++
++	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
++	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
++}
++#endif
++
++#ifdef CONFIG_HAS_DATAFLASH
++static void at91sam9g10ek_spi_hw_init(void)
++{
++	at91_set_A_periph(AT91_PIN_PA3, 0);	/* SPI0_NPCS0 */
++
++	at91_set_A_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
++	at91_set_A_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
++	at91_set_A_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
++
++	/* Enable clock */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
++}
++#endif
++
++#ifdef CONFIG_DRIVER_DM9000
++static void at91sam9g10ek_dm9000_hw_init(void)
++{
++	/* Configure SMC CS2 for DM9000 */
++	/*
++	at91_sys_write(AT91_SMC_SETUP(2),
++		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
++		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
++	at91_sys_write(AT91_SMC_PULSE(2),
++		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
++		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
++	at91_sys_write(AT91_SMC_CYCLE(2),
++		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
++	*/
++	at91_sys_write(AT91_SMC_SETUP(2),
++		       AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(0) |
++		       AT91_SMC_NRDSETUP_(3) | AT91_SMC_NCS_RDSETUP_(0));
++	at91_sys_write(AT91_SMC_PULSE(2),
++		       AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(8) |
++		       AT91_SMC_NRDPULSE_(6) | AT91_SMC_NCS_RDPULSE_(8));
++	at91_sys_write(AT91_SMC_CYCLE(2),
++		       AT91_SMC_NWECYCLE_(20) | AT91_SMC_NRDCYCLE_(20));
++	at91_sys_write(AT91_SMC_MODE(2),
++		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
++		       AT91_SMC_EXNWMODE_DISABLE |
++		       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
++		       AT91_SMC_TDF_(1));
++
++	/* Configure Reset signal as output */
++	at91_set_gpio_output(AT91_PIN_PC10, 0);
++
++	/* Configure Interrupt pin as input, no pull-up */
++	at91_set_gpio_input(AT91_PIN_PC11, 0);
++}
++#endif
++
++#ifdef CONFIG_LCD
++vidinfo_t panel_info = {
++	vl_col:		240,
++	vl_row:		320,
++	vl_clk:		4965000,
++	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
++			ATMEL_LCDC_INVFRAME_INVERTED,
++	vl_bpix:	3,
++	vl_tft:		1,
++	vl_hsync_len:	5,
++	vl_left_margin:	1,
++	vl_right_margin:33,
++	vl_vsync_len:	1,
++	vl_upper_margin:1,
++	vl_lower_margin:0,
++	mmio:		AT91SAM9261_LCDC_BASE,
++};
++
++void lcd_enable(void)
++{
++	at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
++}
++
++void lcd_disable(void)
++{
++	at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
++}
++
++static void at91sam9g10ek_lcd_hw_init(void)
++{
++	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
++	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
++	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
++	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
++	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
++	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
++	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
++	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
++	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
++	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
++	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
++	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
++	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
++	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
++	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
++	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
++	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
++	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
++	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
++	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
++	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
++	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
++
++	at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
++
++	/* gd->fb_base = AT91SAM9261_SRAM_BASE; */
++	gd->fb_base = 0x23E00000;
++
++}
++#endif
++
++int board_init(void)
++{
++	/* Enable Ctrlc */
++	console_init_f();
++
++	/* arch number of AT91SAM9G10EK-Board */
++	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
++	/* adress of boot parameters */
++	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
++
++	at91sam9g10ek_serial_hw_init();
++#ifdef CONFIG_CMD_NAND
++	at91sam9g10ek_nand_hw_init();
++#endif
++#ifdef CONFIG_HAS_DATAFLASH
++	at91sam9g10ek_spi_hw_init();
++#endif
++#ifdef CONFIG_DRIVER_DM9000
++	at91sam9g10ek_dm9000_hw_init();
++#endif
++#ifdef CONFIG_LCD
++	at91sam9g10ek_lcd_hw_init();
++#endif
++	return 0;
++}
++
++int dram_init(void)
++{
++	gd->bd->bi_dram[0].start = PHYS_SDRAM;
++	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
++	return 0;
++}
++
++#ifdef CONFIG_RESET_PHY_R
++void reset_phy(void)
++{
++#ifdef CONFIG_DRIVER_DM9000
++	/*
++	 * Initialize ethernet HW addr prior to starting Linux,
++	 * needed for nfsroot
++	 */
++	eth_init(gd->bd);
++#endif
++}
++#endif
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/config.mk u-boot-1.3.4/board/atmel/at91sam9g10ek/config.mk
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/config.mk	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g10ek/config.mk	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1 @@
++TEXT_BASE = 0x23f00000
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/led.c u-boot-1.3.4/board/atmel/at91sam9g10ek/led.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/led.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g10ek/led.c	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,78 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/at91sam9261.h>
++#include <asm/arch/at91_pmc.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/io.h>
++
++#define	RED_LED		AT91_PIN_PA23	/* this is the power led */
++#define	GREEN_LED	AT91_PIN_PA13	/* this is the user1 led */
++#define	YELLOW_LED	AT91_PIN_PA14	/* this is the user2 led */
++
++void red_LED_on(void)
++{
++	at91_set_gpio_value(RED_LED, 1);
++}
++
++void red_LED_off(void)
++{
++	at91_set_gpio_value(RED_LED, 0);
++}
++
++void green_LED_on(void)
++{
++	at91_set_gpio_value(GREEN_LED, 0);
++}
++
++void green_LED_off(void)
++{
++	at91_set_gpio_value(GREEN_LED, 1);
++}
++
++void yellow_LED_on(void)
++{
++	at91_set_gpio_value(YELLOW_LED, 0);
++}
++
++void yellow_LED_off(void)
++{
++	at91_set_gpio_value(YELLOW_LED, 1);
++}
++
++
++void coloured_LED_init(void)
++{
++	/* Enable clock */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
++
++	at91_set_gpio_output(RED_LED, 1);
++	at91_set_gpio_output(GREEN_LED, 1);
++	at91_set_gpio_output(YELLOW_LED, 1);
++
++	at91_set_gpio_value(RED_LED, 0);
++	at91_set_gpio_value(GREEN_LED, 1);
++	at91_set_gpio_value(YELLOW_LED, 1);
++}
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/Makefile u-boot-1.3.4/board/atmel/at91sam9g10ek/Makefile
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/Makefile	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g10ek/Makefile	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,57 @@
++#
++# (C) Copyright 2003-2008
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# (C) Copyright 2008
++# Stelian Pop <stelian.pop@leadtechdesign.com>
++# Lead Tech Design <www.leadtechdesign.com>
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).a
++
++COBJS-y += at91sam9g10ek.o
++COBJS-y += led.o
++COBJS-y	+= partition.o
++COBJS-$(CONFIG_CMD_NAND) += nand.o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS-y))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++clean:
++	rm -f $(SOBJS) $(OBJS)
++
++distclean:	clean
++	rm -f $(LIB) core *.bak $(obj).depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/nand.c u-boot-1.3.4/board/atmel/at91sam9g10ek/nand.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/nand.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g10ek/nand.c	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,79 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/at91sam9261.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/at91_pio.h>
++
++#include <nand.h>
++
++/*
++ *	hardware specific access to control-lines
++ */
++#define	MASK_ALE	(1 << 22)	/* our ALE is AD22 */
++#define	MASK_CLE	(1 << 21)	/* our CLE is AD21 */
++
++static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
++{
++	struct nand_chip *this = mtd->priv;
++	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
++
++	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
++	switch (cmd) {
++	case NAND_CTL_SETCLE:
++		IO_ADDR_W |= MASK_CLE;
++		break;
++	case NAND_CTL_SETALE:
++		IO_ADDR_W |= MASK_ALE;
++		break;
++	case NAND_CTL_CLRNCE:
++		at91_set_gpio_value(AT91_PIN_PC14, 1);
++		break;
++	case NAND_CTL_SETNCE:
++		at91_set_gpio_value(AT91_PIN_PC14, 0);
++		break;
++	}
++	this->IO_ADDR_W = (void *) IO_ADDR_W;
++}
++
++static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
++{
++	return at91_get_gpio_value(AT91_PIN_PC15);
++}
++
++int board_nand_init(struct nand_chip *nand)
++{
++	nand->eccmode = NAND_ECC_SOFT;
++#ifdef CFG_NAND_DBW_16
++	nand->options = NAND_BUSWIDTH_16;
++#endif
++	nand->hwcontrol = at91sam9261ek_nand_hwcontrol;
++	nand->dev_ready = at91sam9261ek_nand_ready;
++	nand->chip_delay = 20;
++
++	return 0;
++}
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/partition.c u-boot-1.3.4/board/atmel/at91sam9g10ek/partition.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g10ek/partition.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g10ek/partition.c	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,40 @@
++/*
++ * (C) Copyright 2008
++ * Ulf Samuelsson <ulf@atmel.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++#include <common.h>
++#include <config.h>
++#include <asm/hardware.h>
++#include <dataflash.h>
++
++AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
++
++struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
++	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
++	{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}
++};
++
++/*define the area offsets*/
++dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
++	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
++	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
++	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
++	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
++	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
++};
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/at91sam9g20ek.c u-boot-1.3.4/board/atmel/at91sam9g20ek/at91sam9g20ek.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/at91sam9g20ek.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g20ek/at91sam9g20ek.c	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,258 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/at91sam9260.h>
++#include <asm/arch/at91sam9260_matrix.h>
++#include <asm/arch/at91sam9_smc.h>
++#include <asm/arch/at91_pmc.h>
++#include <asm/arch/at91_rstc.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/io.h>
++#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
++#include <net.h>
++#endif
++
++DECLARE_GLOBAL_DATA_PTR;
++
++/* ------------------------------------------------------------------------- */
++/*
++ * Miscelaneous platform dependent initialisations
++ */
++
++static void at91sam9g20ek_serial_hw_init(void)
++{
++#ifdef CONFIG_USART0
++	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD0 */
++	at91_set_A_periph(AT91_PIN_PB5, 0);		/* RXD0 */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
++#endif
++
++#ifdef CONFIG_USART1
++	at91_set_A_periph(AT91_PIN_PB6, 1);		/* TXD1 */
++	at91_set_A_periph(AT91_PIN_PB7, 0);		/* RXD1 */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
++#endif
++
++#ifdef CONFIG_USART2
++	at91_set_A_periph(AT91_PIN_PB8, 1);		/* TXD2 */
++	at91_set_A_periph(AT91_PIN_PB9, 0);		/* RXD2 */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
++#endif
++
++#ifdef CONFIG_USART3	/* DBGU */
++	at91_set_A_periph(AT91_PIN_PB14, 0);		/* DRXD */
++	at91_set_A_periph(AT91_PIN_PB15, 1);		/* DTXD */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
++#endif
++}
++
++#ifdef CONFIG_CMD_NAND
++static void at91sam9g20ek_nand_hw_init(void)
++{
++	unsigned long csa;
++
++	/* Enable CS3 */
++	csa = at91_sys_read(AT91_MATRIX_EBICSA);
++	at91_sys_write(AT91_MATRIX_EBICSA,
++		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
++
++	/* Configure SMC CS3 for NAND/SmartMedia */
++	at91_sys_write(AT91_SMC_SETUP(3),
++		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
++		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
++	at91_sys_write(AT91_SMC_PULSE(3),
++		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
++		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(3));
++	at91_sys_write(AT91_SMC_CYCLE(3),
++		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
++	at91_sys_write(AT91_SMC_MODE(3),
++		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
++		       AT91_SMC_EXNWMODE_DISABLE |
++#ifdef CFG_NAND_DBW_16
++		       AT91_SMC_DBW_16 |
++#else /* CFG_NAND_DBW_8 */
++		       AT91_SMC_DBW_8 |
++#endif
++		       AT91_SMC_TDF_(3));
++
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
++
++	/* Configure RDY/BSY */
++	at91_set_gpio_input(AT91_PIN_PC13, 1);
++
++	/* Enable NandFlash */
++	at91_set_gpio_output(AT91_PIN_PC14, 1);
++}
++#endif
++
++#ifdef CONFIG_HAS_DATAFLASH
++static void at91sam9g20ek_spi_hw_init(void)
++{
++	at91_set_A_periph(AT91_PIN_PA3, 0);	/* SPI0_NPCS0 */
++	at91_set_B_periph(AT91_PIN_PC11, 0);	/* SPI0_NPCS1 */
++
++	at91_set_A_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
++	at91_set_A_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
++	at91_set_A_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
++
++	/* Enable clock */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
++}
++#endif
++
++#ifdef CONFIG_MACB
++static void at91sam9g20ek_macb_hw_init(void)
++{
++	unsigned long rstc;
++	
++	/* Enable clock */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
++
++	/*
++	 * Disable pull-up on:
++	 *	RXDV (PA17) => PHY normal mode (not Test mode)
++	 *	ERX0 (PA14) => PHY ADDR0
++	 *	ERX1 (PA15) => PHY ADDR1
++	 *	ERX2 (PA25) => PHY ADDR2
++	 *	ERX3 (PA26) => PHY ADDR3
++	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
++	 *
++	 * PHY has internal pull-down
++	 */
++	writel(pin_to_mask(AT91_PIN_PA14) |
++	       pin_to_mask(AT91_PIN_PA15) |
++	       pin_to_mask(AT91_PIN_PA17) |
++	       pin_to_mask(AT91_PIN_PA25) |
++	       pin_to_mask(AT91_PIN_PA26) |
++	       pin_to_mask(AT91_PIN_PA28),
++	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
++
++	rstc = at91_sys_read(AT91_RSTC_MR);
++
++	/* Need to reset PHY -> 500ms reset */
++	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
++				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
++				     AT91_RSTC_URSTEN);
++
++	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
++
++	/* Wait for end hardware reset */
++	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
++
++	/* Restore NRST value */
++	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
++				     (rstc) |
++				     AT91_RSTC_URSTEN);
++
++	/* Re-enable pull-up */
++	writel(pin_to_mask(AT91_PIN_PA14) |
++	       pin_to_mask(AT91_PIN_PA15) |
++	       pin_to_mask(AT91_PIN_PA17) |
++	       pin_to_mask(AT91_PIN_PA25) |
++	       pin_to_mask(AT91_PIN_PA26) |
++	       pin_to_mask(AT91_PIN_PA28),
++	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
++
++	at91_set_A_periph(AT91_PIN_PA19, 0);	/* ETXCK_EREFCK */
++	at91_set_A_periph(AT91_PIN_PA17, 0);	/* ERXDV */
++	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ERX0 */
++	at91_set_A_periph(AT91_PIN_PA15, 0);	/* ERX1 */
++	at91_set_A_periph(AT91_PIN_PA18, 0);	/* ERXER */
++	at91_set_A_periph(AT91_PIN_PA16, 0);	/* ETXEN */
++	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ETX0 */
++	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ETX1 */
++	at91_set_A_periph(AT91_PIN_PA21, 0);	/* EMDIO */
++	at91_set_A_periph(AT91_PIN_PA20, 0);	/* EMDC */
++
++#ifndef CONFIG_RMII
++	at91_set_B_periph(AT91_PIN_PA28, 0);	/* ECRS */
++	at91_set_B_periph(AT91_PIN_PA29, 0);	/* ECOL */
++	at91_set_B_periph(AT91_PIN_PA25, 0);	/* ERX2 */
++	at91_set_B_periph(AT91_PIN_PA26, 0);	/* ERX3 */
++	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ERXCK */
++#if defined(CONFIG_AT91SAM9G20EK) || defined(CONFIG_AT91SAM9G20EK_2MMC)
++	/*
++	 * use PA10, PA11 for ETX2, ETX3.
++	 * PA23 and PA24 are for TWI EEPROM
++	 */
++	at91_set_B_periph(AT91_PIN_PA10, 0);    /* ETX2 */
++	at91_set_B_periph(AT91_PIN_PA11, 0);    /* ETX3 */
++#else
++	at91_set_B_periph(AT91_PIN_PA23, 0);    /* ETX2 */
++	at91_set_B_periph(AT91_PIN_PA24, 0);    /* ETX3 */
++#endif
++	at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
++#endif
++
++}
++#endif
++
++int board_init(void)
++{
++	/* Enable Ctrlc */
++	console_init_f();
++
++	/* arch number of AT91SAM9G20EK-Board */
++#ifdef	CONFIG_AT91SAM9G20EK_2MMC
++	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK_2MMC;
++#else
++	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK;
++#endif
++	/* adress of boot parameters */
++	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
++
++	at91sam9g20ek_serial_hw_init();
++#ifdef CONFIG_CMD_NAND
++	at91sam9g20ek_nand_hw_init();
++#endif
++#ifdef CONFIG_HAS_DATAFLASH
++	at91sam9g20ek_spi_hw_init();
++#endif
++#ifdef CONFIG_MACB
++	at91sam9g20ek_macb_hw_init();
++#endif
++
++	return 0;
++}
++
++int dram_init(void)
++{
++	gd->bd->bi_dram[0].start = PHYS_SDRAM;
++	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
++	return 0;
++}
++
++#ifdef CONFIG_RESET_PHY_R
++void reset_phy(void)
++{
++#ifdef CONFIG_MACB
++	/*
++	 * Initialize ethernet HW addr prior to starting Linux,
++	 * needed for nfsroot
++	 */
++	eth_init(gd->bd);
++#endif
++}
++#endif
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/config.mk u-boot-1.3.4/board/atmel/at91sam9g20ek/config.mk
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/config.mk	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g20ek/config.mk	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1 @@
++TEXT_BASE = 0x23f00000
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/led.c u-boot-1.3.4/board/atmel/at91sam9g20ek/led.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/led.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g20ek/led.c	2010-03-25 18:48:37.000000000 -0500
+@@ -0,0 +1,69 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/at91sam9260.h>
++#include <asm/arch/at91_pmc.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/io.h>
++
++#ifdef	CONFIG_AT91SAM9G20EK_2MMC
++#define	RED_LED		AT91_PIN_PB31	/* this is the power led */
++#define	GREEN_LED	AT91_PIN_PB30	/* this is the user led */
++#else
++#define	RED_LED		AT91_PIN_PA31	/* this is the power led */
++#define	GREEN_LED	AT91_PIN_PA30	/* this is the user led */
++#endif
++
++void red_LED_on(void)
++{
++	at91_set_gpio_value(RED_LED, 1);
++}
++
++void red_LED_off(void)
++{
++	at91_set_gpio_value(RED_LED, 0);
++}
++
++void green_LED_on(void)
++{
++	at91_set_gpio_value(GREEN_LED, 0);
++}
++
++void green_LED_off(void)
++{
++	at91_set_gpio_value(GREEN_LED, 1);
++}
++
++void coloured_LED_init(void)
++{
++	/* Enable clock */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
++
++	at91_set_gpio_output(RED_LED, 1);
++	at91_set_gpio_output(GREEN_LED, 1);
++
++	at91_set_gpio_value(RED_LED, 0);
++	at91_set_gpio_value(GREEN_LED, 1);
++}
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/Makefile u-boot-1.3.4/board/atmel/at91sam9g20ek/Makefile
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/Makefile	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g20ek/Makefile	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,57 @@
++#
++# (C) Copyright 2003-2008
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# (C) Copyright 2008
++# Stelian Pop <stelian.pop@leadtechdesign.com>
++# Lead Tech Design <www.leadtechdesign.com>
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).a
++
++COBJS-y	+= at91sam9g20ek.o
++COBJS-y	+= led.o
++COBJS-y	+= partition.o
++COBJS-$(CONFIG_CMD_NAND) += nand.o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS-y))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++clean:
++	rm -f $(SOBJS) $(OBJS)
++
++distclean:	clean
++	rm -f $(LIB) core *.bak $(obj).depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/nand.c u-boot-1.3.4/board/atmel/at91sam9g20ek/nand.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/nand.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g20ek/nand.c	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,79 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/at91sam9260.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/at91_pio.h>
++
++#include <nand.h>
++
++/*
++ *	hardware specific access to control-lines
++ */
++#define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
++#define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
++
++static void at91sam9g20ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
++{
++	struct nand_chip *this = mtd->priv;
++	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
++
++	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
++	switch (cmd) {
++	case NAND_CTL_SETCLE:
++		IO_ADDR_W |= MASK_CLE;
++		break;
++	case NAND_CTL_SETALE:
++		IO_ADDR_W |= MASK_ALE;
++		break;
++	case NAND_CTL_CLRNCE:
++		at91_set_gpio_value(AT91_PIN_PC14, 1);
++		break;
++	case NAND_CTL_SETNCE:
++		at91_set_gpio_value(AT91_PIN_PC14, 0);
++		break;
++	}
++	this->IO_ADDR_W = (void *) IO_ADDR_W;
++}
++
++static int at91sam9g20ek_nand_ready(struct mtd_info *mtd)
++{
++	return at91_get_gpio_value(AT91_PIN_PC13);
++}
++
++int board_nand_init(struct nand_chip *nand)
++{
++	nand->eccmode = NAND_ECC_SOFT;
++#ifdef CFG_NAND_DBW_16
++	nand->options = NAND_BUSWIDTH_16;
++#endif
++	nand->hwcontrol = at91sam9g20ek_nand_hwcontrol;
++	nand->dev_ready = at91sam9g20ek_nand_ready;
++	nand->chip_delay = 20;
++
++	return 0;
++}
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/partition.c u-boot-1.3.4/board/atmel/at91sam9g20ek/partition.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9g20ek/partition.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9g20ek/partition.c	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,40 @@
++/*
++ * (C) Copyright 2008
++ * Ulf Samuelsson <ulf@atmel.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++#include <common.h>
++#include <config.h>
++#include <asm/hardware.h>
++#include <dataflash.h>
++
++AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
++
++struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
++	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
++	{CFG_DATAFLASH_LOGIC_ADDR_CS1, 1}
++};
++
++/*define the area offsets*/
++dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
++	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
++	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
++	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
++	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
++	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
++};
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c u-boot-1.3.4/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,324 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/sizes.h>
++#include <asm/arch/at91sam9g45.h>
++#include <asm/arch/at91sam9g45_matrix.h>
++#include <asm/arch/at91sam9_smc.h>
++#include <asm/arch/at91_pmc.h>
++#include <asm/arch/at91_rstc.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/io.h>
++#include <lcd.h>
++#include <atmel_lcdc.h>
++#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
++#include <net.h>
++#endif
++
++DECLARE_GLOBAL_DATA_PTR;
++
++/* ------------------------------------------------------------------------- */
++/*
++ * Miscelaneous platform dependent initialisations
++ */
++
++static void at91samm10g45ek_serial_hw_init(void)
++{
++#ifdef CONFIG_USART0
++	at91_set_A_periph(AT91_PIN_PB19, 1);	/* TXD0 */
++	at91_set_A_periph(AT91_PIN_PB18, 0);	/* RXD0 */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0);
++#endif
++
++#ifdef CONFIG_USART1
++	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD1 */
++	at91_set_A_periph(AT91_PIN_PB5, 0);		/* RXD1 */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1);
++#endif
++
++#ifdef CONFIG_USART2
++	at91_set_A_periph(AT91_PIN_PD6, 1);		/* TXD2 */
++	at91_set_A_periph(AT91_PIN_PD7, 0);		/* RXD2 */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2);
++#endif
++
++#ifdef CONFIG_USART3	/* DBGU */
++	at91_set_A_periph(AT91_PIN_PB12, 0);	/* DRXD */
++	at91_set_A_periph(AT91_PIN_PB13, 1);	/* DTXD */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
++#endif
++}
++
++#ifdef CONFIG_CMD_NAND
++static void at91samm10g45ek_nand_hw_init(void)
++{
++	unsigned long csa;
++
++	/* Enable CS3 */
++	csa = at91_sys_read(AT91_MATRIX_EBICSA);
++	at91_sys_write(AT91_MATRIX_EBICSA,
++		       csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
++
++	/* Configure SMC CS3 for NAND/SmartMedia */
++	at91_sys_write(AT91_SMC_SETUP(3),
++		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
++		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
++	at91_sys_write(AT91_SMC_PULSE(3),
++		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
++		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
++	at91_sys_write(AT91_SMC_CYCLE(3),
++		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
++	at91_sys_write(AT91_SMC_MODE(3),
++		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
++		       AT91_SMC_EXNWMODE_DISABLE |
++#ifdef CFG_NAND_DBW_16
++		       AT91_SMC_DBW_16 |
++#else /* CFG_NAND_DBW_8 */
++		       AT91_SMC_DBW_8 |
++#endif
++		       AT91_SMC_TDF_(3));
++
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
++
++	/* Configure RDY/BSY */
++	at91_set_gpio_input(AT91_PIN_PC8, 1);
++
++	/* Enable NandFlash */
++	at91_set_gpio_output(AT91_PIN_PC14, 1);
++}
++#endif
++
++#ifdef CONFIG_HAS_DATAFLASH
++static void at91samm10g45ek_spi_hw_init(void)
++{
++	at91_set_B_periph(AT91_PIN_PB3, 0);	/* SPI0_NPCS0 */
++
++	at91_set_B_periph(AT91_PIN_PB0, 0);	/* SPI0_MISO */
++	at91_set_B_periph(AT91_PIN_PB1, 0);	/* SPI0_MOSI */
++	at91_set_B_periph(AT91_PIN_PB2, 0);	/* SPI0_SPCK */
++
++	/* Enable clock */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0);
++}
++#endif
++
++#ifdef CONFIG_MACB
++static void at91samm10g45ek_macb_hw_init(void)
++{
++	unsigned long rstc;
++
++	/* Enable clock */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
++
++	/*
++	 * Disable pull-up on:
++	 *	RXDV (PA15) => PHY normal mode (not Test mode)
++	 * 	ERX0 (PA12) => PHY ADDR0
++	 *	ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
++	 *
++	 * PHY has internal pull-down
++	 */
++	writel(pin_to_mask(AT91_PIN_PA15) |
++	       pin_to_mask(AT91_PIN_PA12) |
++	       pin_to_mask(AT91_PIN_PA13),
++	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
++
++	rstc = at91_sys_read(AT91_RSTC_MR);
++
++	/* Need to reset PHY -> 500ms reset */
++	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
++				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
++				     AT91_RSTC_URSTEN);
++
++	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
++
++	/* Wait for end hardware reset */
++	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
++
++	/* Restore NRST value */
++	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
++				     (rstc) |
++				     AT91_RSTC_URSTEN);
++
++	/* Re-enable pull-up */
++	writel(pin_to_mask(AT91_PIN_PA15) |
++	       pin_to_mask(AT91_PIN_PA12) |
++	       pin_to_mask(AT91_PIN_PA13),
++	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
++
++	at91_set_A_periph(AT91_PIN_PA17, 0);	/* ETXCK_EREFCK */
++	at91_set_A_periph(AT91_PIN_PA15, 0);	/* ERXDV */
++	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ERX0 */
++	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ERX1 */
++	at91_set_A_periph(AT91_PIN_PA16, 0);	/* ERXER */
++	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ETXEN */
++	at91_set_A_periph(AT91_PIN_PA10, 0);	/* ETX0 */
++	at91_set_A_periph(AT91_PIN_PA11, 0);	/* ETX1 */
++	at91_set_A_periph(AT91_PIN_PA19, 0);	/* EMDIO */
++	at91_set_A_periph(AT91_PIN_PA18, 0);	/* EMDC */
++
++#ifndef CONFIG_RMII
++	at91_set_B_periph(AT91_PIN_PA29, 0);	/* ECRS */
++	at91_set_B_periph(AT91_PIN_PA30, 0);	/* ECOL */
++	at91_set_B_periph(AT91_PIN_PA8,  0);	/* ERX2 */
++	at91_set_B_periph(AT91_PIN_PA9,  0);	/* ERX3 */
++	at91_set_B_periph(AT91_PIN_PA28, 0);	/* ERXCK */
++	at91_set_B_periph(AT91_PIN_PA6,  0);	/* ETX2 */
++	at91_set_B_periph(AT91_PIN_PA7,  0);	/* ETX3 */
++	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ETXER */
++#endif
++
++}
++#endif
++
++#ifdef CONFIG_LCD
++vidinfo_t panel_info = {
++	vl_col:		480,
++	vl_row:		272,
++	vl_clk:		125000,
++	vl_sync:	ATMEL_LCDC_INVLINE_NORMAL |
++			ATMEL_LCDC_INVFRAME_NORMAL,
++	vl_bpix:	3,
++	vl_tft:		1,
++	vl_hsync_len:	41,
++	vl_left_margin:	2,
++	vl_right_margin:2,
++	vl_vsync_len:	1,
++	vl_upper_margin:2,
++	vl_lower_margin:2,
++	mmio:		AT91SAM9G45_LCDC_BASE,
++};
++
++void lcd_enable(void)
++{
++	at91_set_gpio_value(AT91_PIN_PE6, 1);  /* power up */
++}
++
++void lcd_disable(void)
++{
++	at91_set_gpio_value(AT91_PIN_PE6, 0);  /* power down */
++}
++
++static void at91samm10g45ek_lcd_hw_init(void)
++{
++	at91_set_A_periph(AT91_PIN_PE0, 0);		/* LCDDPWR */
++
++	at91_set_A_periph(AT91_PIN_PE4, 0);		/* LCDHSYNC */
++	at91_set_A_periph(AT91_PIN_PE5, 0);		/* LCDDOTCK */
++	
++	at91_set_gpio_input(AT91_PIN_PE6, 0);	/* LCDDEN */
++
++	at91_set_A_periph(AT91_PIN_PE7, 0);		/* LCDD0 */
++	at91_set_A_periph(AT91_PIN_PE8, 0);		/* LCDD1 */
++	at91_set_A_periph(AT91_PIN_PE9, 0);		/* LCDD2 */
++	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
++	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
++	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
++	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
++	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
++	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
++	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
++	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
++	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
++	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
++	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
++	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
++	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
++	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
++	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
++	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
++	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
++	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
++	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
++	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
++	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
++
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
++
++	gd->fb_base = AT91SAM9G45_SRAM_BASE;
++}
++#endif
++
++#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
++extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
++
++int board_eth_init(bd_t *bis)
++{
++	macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00);
++}
++#endif
++
++int board_init(void)
++{
++	/* Enable Ctrlc */
++	console_init_f();
++
++	/* arch number of AT91SAM9M10G45EK-Board */
++#ifdef CONFIG_AT91SAM9M10G45EK
++	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
++#elif defined CONFIG_AT91SAM9G45EKES
++	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
++#elif defined CONFIG_AT91SAM9M10EKES
++	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10EKES;
++#endif
++	/* adress of boot parameters */
++	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
++
++	at91samm10g45ek_serial_hw_init();
++#ifdef CONFIG_CMD_NAND
++	at91samm10g45ek_nand_hw_init();
++#endif
++#ifdef CONFIG_HAS_DATAFLASH
++	at91samm10g45ek_spi_hw_init();
++#endif
++#ifdef CONFIG_MACB
++	at91samm10g45ek_macb_hw_init();
++#endif
++
++#ifdef CONFIG_LCD
++	at91samm10g45ek_lcd_hw_init();
++#endif
++	return 0;
++}
++
++int dram_init(void)
++{
++	gd->bd->bi_dram[0].start = PHYS_SDRAM;
++	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
++	return 0;
++}
++
++#ifdef CONFIG_RESET_PHY_R
++void reset_phy(void)
++{
++#ifdef CONFIG_MACB
++	/*
++	 * Initialize ethernet HW addr prior to starting Linux,
++	 * needed for nfsroot
++	 */
++	eth_init(gd->bd);
++#endif
++}
++#endif
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/config.mk u-boot-1.3.4/board/atmel/at91sam9m10g45ek/config.mk
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/config.mk	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9m10g45ek/config.mk	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1 @@
++TEXT_BASE = 0x73f00000
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/led.c u-boot-1.3.4/board/atmel/at91sam9m10g45ek/led.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/led.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9m10g45ek/led.c	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,64 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/at91sam9g45.h>
++#include <asm/arch/at91_pmc.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/io.h>
++
++#define	RED_LED		AT91_PIN_PD31	/* this is the user1 led */
++#define	GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
++
++void red_LED_on(void)
++{
++	at91_set_gpio_value(RED_LED, 1);
++}
++
++void red_LED_off(void)
++{
++	at91_set_gpio_value(RED_LED, 0);
++}
++
++void green_LED_on(void)
++{
++	at91_set_gpio_value(GREEN_LED, 0);
++}
++
++void green_LED_off(void)
++{
++	at91_set_gpio_value(GREEN_LED, 1);
++}
++
++void coloured_LED_init(void)
++{
++	/* Enable clock */
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
++
++	at91_set_gpio_output(RED_LED, 1);
++	at91_set_gpio_output(GREEN_LED, 1);
++
++	at91_set_gpio_value(RED_LED, 0);
++	at91_set_gpio_value(GREEN_LED, 1);
++}
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/Makefile u-boot-1.3.4/board/atmel/at91sam9m10g45ek/Makefile
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/Makefile	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9m10g45ek/Makefile	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,57 @@
++#
++# (C) Copyright 2003-2008
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# (C) Copyright 2008
++# Stelian Pop <stelian.pop@leadtechdesign.com>
++# Lead Tech Design <www.leadtechdesign.com>
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).a
++
++COBJS-y += at91sam9m10g45ek.o
++COBJS-y += led.o
++COBJS-y	+= partition.o
++COBJS-$(CONFIG_CMD_NAND) += nand.o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS-y))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++clean:
++	rm -f $(SOBJS) $(OBJS)
++
++distclean:	clean
++	rm -f $(LIB) core *.bak $(obj).depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/nand.c u-boot-1.3.4/board/atmel/at91sam9m10g45ek/nand.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/nand.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9m10g45ek/nand.c	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,79 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/at91sam9g45.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/at91_pio.h>
++
++#include <nand.h>
++
++/*
++ *	hardware specific access to control-lines
++ */
++#define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
++#define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
++
++static void at91samm10g45ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
++{
++	struct nand_chip *this = mtd->priv;
++	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
++
++	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
++	switch (cmd) {
++	case NAND_CTL_SETCLE:
++		IO_ADDR_W |= MASK_CLE;
++		break;
++	case NAND_CTL_SETALE:
++		IO_ADDR_W |= MASK_ALE;
++		break;
++	case NAND_CTL_CLRNCE:
++		at91_set_gpio_value(AT91_PIN_PC14, 1);
++		break;
++	case NAND_CTL_SETNCE:
++		at91_set_gpio_value(AT91_PIN_PC14, 0);
++		break;
++	}
++	this->IO_ADDR_W = (void *) IO_ADDR_W;
++}
++
++static int at91samm10g45ek_nand_ready(struct mtd_info *mtd)
++{
++	return at91_get_gpio_value(AT91_PIN_PC8);
++}
++
++int board_nand_init(struct nand_chip *nand)
++{
++	nand->eccmode = NAND_ECC_SOFT;
++#ifdef CFG_NAND_DBW_16
++	nand->options = NAND_BUSWIDTH_16;
++#endif
++	nand->hwcontrol = at91samm10g45ek_nand_hwcontrol;
++	nand->dev_ready = at91samm10g45ek_nand_ready;
++	nand->chip_delay = 20;
++
++	return 0;
++}
+diff -uprN u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/partition.c u-boot-1.3.4/board/atmel/at91sam9m10g45ek/partition.c
+--- u-boot-1.3.4-vanilla/board/atmel/at91sam9m10g45ek/partition.c	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/board/atmel/at91sam9m10g45ek/partition.c	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,39 @@
++/*
++ * (C) Copyright 2008
++ * Ulf Samuelsson <ulf@atmel.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++#include <common.h>
++#include <config.h>
++#include <asm/hardware.h>
++#include <dataflash.h>
++
++AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
++
++struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
++	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
++};
++
++/*define the area offsets*/
++dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
++	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
++	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
++	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
++	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
++	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
++};
+diff -uprN u-boot-1.3.4-vanilla/cpu/arm926ejs/at91sam9/usb.c u-boot-1.3.4/cpu/arm926ejs/at91sam9/usb.c
+--- u-boot-1.3.4-vanilla/cpu/arm926ejs/at91sam9/usb.c	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/cpu/arm926ejs/at91sam9/usb.c	2010-03-25 16:45:59.000000000 -0500
+@@ -33,7 +33,7 @@ int usb_cpu_init(void)
+ {
+ 	/* Enable USB host clock. */
+ 	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP);
+-#ifdef CONFIG_AT91SAM9261
++#if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
+ 	at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP | AT91_PMC_HCK0);
+ #else
+ 	at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP);
+@@ -46,7 +46,7 @@ int usb_cpu_stop(void)
+ {
+ 	/* Disable USB host clock. */
+ 	at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP);
+-#ifdef CONFIG_AT91SAM9261
++#if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
+ 	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_HCK0);
+ #else
+ 	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP);
+diff -uprN u-boot-1.3.4-vanilla/doc/README.at91 u-boot-1.3.4/doc/README.at91
+--- u-boot-1.3.4-vanilla/doc/README.at91	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/doc/README.at91	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,88 @@
++Atmel AT91 Evaluation kits
++
++http://atmel.com/dyn/products/tools.asp?family_id=605#1443
++
++------------------------------------------------------------------------------
++AT91SAM9260EK
++------------------------------------------------------------------------------
++
++Memory map
++	0x20000000 - 23FFFFFF	SDRAM (64 MB)
++	0xC0000000 - Cxxxxxxx	Atmel Dataflash card (J13)
++	0xD0000000 - Dxxxxxxx	Soldered Atmel Dataflash 
++
++Environment variables
++
++	U-Boot environment variables can be stored at different places:
++		- Dataflash on SPI chip select 1 (default)
++		- Dataflash on SPI chip select 0 (dataflash card)
++		- Nand flash.
++
++	You can choose your storage location at config step (here for at91sam9260ek) :
++		make at91sam9260ek_config		- use data flash (spi cs1) (default)
++	  	make at91sam9260ek_nandflash_config	- use nand flash 
++  		make at91sam9260ek_dataflash_cs0_config	- use data flash (spi cs0)
++	  	make at91sam9260ek_dataflash_cs1_config	- use data flash (spi cs1)
++
++
++------------------------------------------------------------------------------
++AT91SAM9261EK
++------------------------------------------------------------------------------
++
++Memory map
++	0x20000000 - 23FFFFFF	SDRAM (64 MB)
++	0xC0000000 - Cxxxxxxx	Soldered Atmel Dataflash 
++	0xD0000000 - Dxxxxxxx	Atmel Dataflash card (J22)
++
++Environment variables
++
++	U-Boot environment variables can be stored at different places:
++		- Dataflash on SPI chip select 0 (default)
++		- Dataflash on SPI chip select 3 (dataflash card)
++		- Nand flash.
++
++	You can choose your storage location at config step (here for at91sam9260ek) :
++		make at91sam9261ek_config		- use data flash (spi cs0) (default)
++	  	make at91sam9261ek_nandflash_config	- use nand flash 
++  		make at91sam9261ek_dataflash_cs0_config	- use data flash (spi cs0)
++	  	make at91sam9261ek_dataflash_cs3_config	- use data flash (spi cs3)
++
++
++------------------------------------------------------------------------------
++AT91SAM9263EK
++------------------------------------------------------------------------------
++
++Memory map
++	0x20000000 - 23FFFFFF	SDRAM (64 MB)
++	0xC0000000 - Cxxxxxxx	Atmel Dataflash card (J9)
++
++Environment variables
++
++	U-Boot environment variables can be stored at different places:
++		- Dataflash on SPI chip select 0 (dataflash card)
++		- Nand flash.
++
++	You can choose your storage location at config step (here for at91sam9260ek) :
++		make at91sam9263ek_config		- use data flash (spi cs0) (default)
++	  	make at91sam9263ek_nandflash_config	- use nand flash 
++	  	make at91sam9263ek_dataflash_cs0_config	- use data flash (spi cs0)
++
++
++------------------------------------------------------------------------------
++AT91SAM9RLEK
++------------------------------------------------------------------------------
++
++Memory map
++	0x20000000 - 23FFFFFF	SDRAM (64 MB)
++	0xC0000000 - Cxxxxxxx	Soldered Atmel Dataflash
++
++Environment variables
++
++	U-Boot environment variables can be stored at different places:
++		- Dataflash on SPI chip select 0
++		- Nand flash.
++
++	You can choose your storage location at config step (here for at91sam9260ek) :
++		make at91sam9263ek_config		- use data flash (spi cs0) (default)
++	  	make at91sam9263ek_nandflash_config	- use nand flash 
++	  	make at91sam9263ek_dataflash_cs0_config	- use data flash (spi cs0)
+diff -uprN u-boot-1.3.4-vanilla/drivers/net/macb.c u-boot-1.3.4/drivers/net/macb.c
+--- u-boot-1.3.4-vanilla/drivers/net/macb.c	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/drivers/net/macb.c	2010-05-04 14:32:15.000000000 -0500
+@@ -55,7 +55,7 @@
+ #define CFG_MACB_RX_RING_SIZE		(CFG_MACB_RX_BUFFER_SIZE / 128)
+ #define CFG_MACB_TX_RING_SIZE		16
+ #define CFG_MACB_TX_TIMEOUT		1000
+-#define CFG_MACB_AUTONEG_TIMEOUT	5000000
++#define CFG_MACB_AUTONEG_TIMEOUT	3000000
+ 
+ struct macb_dma_desc {
+ 	u32	addr;
+@@ -290,11 +290,12 @@ static int macb_recv(struct eth_device *
+ 	return 0;
+ }
+ 
+-static void macb_phy_reset(struct macb_device *macb)
++static u16 macb_phy_reset(struct macb_device *macb)
+ {
+ 	struct eth_device *netdev = &macb->netdev;
+ 	int i;
+-	u16 status, adv;
++	u16 status = 0;
++	u16 adv;
+ 
+ 	adv = ADVERTISE_CSMA | ADVERTISE_ALL;
+ 	macb_mdio_write(macb, MII_ADVERTISE, adv);
+@@ -314,6 +315,8 @@ static void macb_phy_reset(struct macb_d
+ 	else
+ 		printf("%s: Autonegotiation timed out (status=0x%04x)\n",
+ 		       netdev->name, status);
++
++	return status;
+ }
+ 
+ static int macb_phy_init(struct macb_device *macb)
+@@ -334,14 +337,7 @@ static int macb_phy_init(struct macb_dev
+ 	status = macb_mdio_read(macb, MII_BMSR);
+ 	if (!(status & BMSR_LSTATUS)) {
+ 		/* Try to re-negotiate if we don't have link already. */
+-		macb_phy_reset(macb);
+-
+-		for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
+-			status = macb_mdio_read(macb, MII_BMSR);
+-			if (status & BMSR_LSTATUS)
+-				break;
+-			udelay(100);
+-		}
++		status = macb_phy_reset(macb);
+ 	}
+ 
+ 	if (!(status & BMSR_LSTATUS)) {
+@@ -414,18 +410,16 @@ static int macb_init(struct eth_device *
+ 
+ 	/* choose RMII or MII mode. This depends on the board */
+ #ifdef CONFIG_RMII
+-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
+-    defined(CONFIG_AT91SAM9263)
+-	macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
+-#else
++#if defined(CONFIG_AVR32)
+ 	macb_writel(macb, USRIO, 0);
+-#endif
+ #else
+-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
+-    defined(CONFIG_AT91SAM9263)
+-	macb_writel(macb, USRIO, MACB_BIT(CLKEN));
++	macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
++#endif
+ #else
++#if defined(CONFIG_AVR32)
+ 	macb_writel(macb, USRIO, MACB_BIT(MII));
++#else
++	macb_writel(macb, USRIO, MACB_BIT(CLKEN));
+ #endif
+ #endif /* CONFIG_RMII */
+ 
+diff -uprN u-boot-1.3.4-vanilla/include/asm-arm/arch-at91sam9/at91sam9g45.h u-boot-1.3.4/include/asm-arm/arch-at91sam9/at91sam9g45.h
+--- u-boot-1.3.4-vanilla/include/asm-arm/arch-at91sam9/at91sam9g45.h	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/include/asm-arm/arch-at91sam9/at91sam9g45.h	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,135 @@
++/*
++ * Chip-specific header file for the AT91SAM9M1x family
++ *
++ *  Copyright (C) 2008 Atmel Corporation.
++ *
++ * Common definitions.
++ * Based on AT91SAM9G45 preliminary datasheet.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91SAM9G45_H
++#define AT91SAM9G45_H
++
++/*
++ * Peripheral identifiers/interrupts.
++ */
++#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
++#define AT91_ID_SYS		1	/* System Controller Interrupt */
++#define AT91SAM9G45_ID_PIOA	2	/* Parallel I/O Controller A */
++#define AT91SAM9G45_ID_PIOB	3	/* Parallel I/O Controller B */
++#define AT91SAM9G45_ID_PIOC	4	/* Parallel I/O Controller C */
++#define AT91SAM9G45_ID_PIODE	5	/* Parallel I/O Controller D and E */
++#define AT91SAM9G45_ID_TRNG	6	/* True Random Number Generator */
++#define AT91SAM9G45_ID_US0	7	/* USART 0 */
++#define AT91SAM9G45_ID_US1	8	/* USART 1 */
++#define AT91SAM9G45_ID_US2	9	/* USART 2 */
++#define AT91SAM9G45_ID_US3	10	/* USART 3 */
++#define AT91SAM9G45_ID_MCI0	11	/* High Speed Multimedia Card Interface 0 */
++#define AT91SAM9G45_ID_TWI0	12	/* Two-Wire Interface 0 */
++#define AT91SAM9G45_ID_TWI1	13	/* Two-Wire Interface 1 */
++#define AT91SAM9G45_ID_SPI0	14	/* Serial Peripheral Interface 0 */
++#define AT91SAM9G45_ID_SPI1	15	/* Serial Peripheral Interface 1 */
++#define AT91SAM9G45_ID_SSC0	16	/* Synchronous Serial Controller 0 */
++#define AT91SAM9G45_ID_SSC1	17	/* Synchronous Serial Controller 1 */
++#define AT91SAM9G45_ID_TCB	18	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
++#define AT91SAM9G45_ID_PWMC	19	/* Pulse Width Modulation Controller */
++#define AT91SAM9G45_ID_TSC	20	/* Touch Screen ADC Controller */
++#define AT91SAM9G45_ID_DMA	21	/* DMA Controller */
++#define AT91SAM9G45_ID_UHPHS	22	/* USB Host High Speed */
++#define AT91SAM9G45_ID_LCDC	23	/* LCD Controller */
++#define AT91SAM9G45_ID_AC97C	24	/* AC97 Controller */
++#define AT91SAM9G45_ID_EMAC	25	/* Ethernet MAC */
++#define AT91SAM9G45_ID_ISI	26	/* Image Sensor Interface */
++#define AT91SAM9G45_ID_UDPHS	27	/* USB Device High Speed */
++#define AT91SAM9G45_ID_AESTDESSHA 28	/* AES + T-DES + SHA */
++#define AT91SAM9G45_ID_MCI1	29	/* High Speed Multimedia Card Interface 1 */
++#define AT91SAM9G45_ID_VDEC	30	/* Video Decoder */
++#define AT91SAM9G45_ID_IRQ0	31	/* Advanced Interrupt Controller */
++
++/*
++ * User Peripheral physical base addresses.
++ */
++#define AT91SAM9G45_BASE_UDPHS		0xfff78000
++#define AT91SAM9G45_BASE_TC0		0xfff7c000
++#define AT91SAM9G45_BASE_TC1		0xfff7c040
++#define AT91SAM9G45_BASE_TC2		0xfff7c080
++#define AT91SAM9G45_BASE_MCI0		0xfff80000
++#define AT91SAM9G45_BASE_TWI0		0xfff84000
++#define AT91SAM9G45_BASE_TWI1		0xfff88000
++#define AT91SAM9G45_BASE_US0		0xfff8c000
++#define AT91SAM9G45_BASE_US1		0xfff90000
++#define AT91SAM9G45_BASE_US2		0xfff94000
++#define AT91SAM9G45_BASE_US3		0xfff98000
++#define AT91SAM9G45_BASE_SSC0		0xfff9c000
++#define AT91SAM9G45_BASE_SSC1		0xfffa0000
++#define AT91SAM9G45_BASE_SPI0		0xfffa4000
++#define AT91SAM9G45_BASE_SPI1		0xfffa8000
++#define AT91SAM9G45_BASE_AC97C		0xfffac000
++#define AT91SAM9G45_BASE_TSC		0xfffb0000
++#define AT91SAM9G45_BASE_ISI		0xfffb4000
++#define AT91SAM9G45_BASE_PWMC		0xfffb8000
++#define AT91SAM9G45_BASE_EMAC		0xfffbc000
++#define AT91SAM9G45_BASE_AES		0xfffc0000
++#define AT91SAM9G45_BASE_TDES		0xfffc4000
++#define AT91SAM9G45_BASE_SHA		0xfffc8000
++#define AT91SAM9G45_BASE_TRNG		0xfffcc000
++#define AT91SAM9G45_BASE_MCI1		0xfffd0000
++#define AT91SAM9G45_BASE_TC3		0xfffd4000
++#define AT91SAM9G45_BASE_TC4		0xfffd4040
++#define AT91SAM9G45_BASE_TC5		0xfffd4080
++#define AT91_BASE_SYS			0xffffe200
++
++/*
++ * System Peripherals (offset from AT91_BASE_SYS)
++ */
++#define AT91_ECC	(0xffffe200 - AT91_BASE_SYS)
++#define AT91_DDRSDRC1	(0xffffe400 - AT91_BASE_SYS)
++#define AT91_DDRSDRC0	(0xffffe600 - AT91_BASE_SYS)
++#define AT91_SMC	(0xffffe800 - AT91_BASE_SYS)
++#define AT91_MATRIX	(0xffffea00 - AT91_BASE_SYS)
++#define AT91_DMA	(0xffffec00 - AT91_BASE_SYS)
++#define AT91_DBGU	(0xffffee00 - AT91_BASE_SYS)
++#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
++#define AT91_PIOA	(0xfffff200 - AT91_BASE_SYS)
++#define AT91_PIOB	(0xfffff400 - AT91_BASE_SYS)
++#define AT91_PIOC	(0xfffff600 - AT91_BASE_SYS)
++#define AT91_PIOD	(0xfffff800 - AT91_BASE_SYS)
++#define AT91_PIOE	(0xfffffa00 - AT91_BASE_SYS)
++#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
++#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
++#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
++#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
++#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
++#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
++#define AT91_GPBR	(0xfffffd60 - AT91_BASE_SYS)
++#define AT91_RTC	(0xfffffdb0 - AT91_BASE_SYS)
++
++#define AT91_USART0	AT91SAM9G45_BASE_US0
++#define AT91_USART1	AT91SAM9G45_BASE_US1
++#define AT91_USART2	AT91SAM9G45_BASE_US2
++#define AT91_USART3	AT91SAM9G45_BASE_US3
++
++/*
++ * Internal Memory.
++ */
++#define AT91SAM9G45_SRAM_BASE	0x00300000	/* Internal SRAM base address */
++#define AT91SAM9G45_SRAM_SIZE	SZ_64K		/* Internal SRAM size (64Kb) */
++
++#define AT91SAM9G45_ROM_BASE	0x00400000	/* Internal ROM base address */
++#define AT91SAM9G45_ROM_SIZE	SZ_64K		/* Internal ROM size (64Kb) */
++
++#define AT91SAM9G45_LCDC_BASE	0x00500000	/* LCD Controller */
++#define AT91SAM9G45_UDPHS_FIFO	0x00600000	/* USB Device HS controller */
++#define AT91SAM9G45_HCI_BASE	0x00700000	/* USB Host controller (OHCI) */
++#define AT91SAM9G45_EHCI_BASE	0x00800000	/* USB Host controller (EHCI) */
++#define AT91SAM9G45_VDEC_BASE	0x00900000	/* Video Decoder Controller */
++
++#define CONFIG_DRAM_BASE	AT91_CHIPSELECT_6
++
++
++#endif
+diff -uprN u-boot-1.3.4-vanilla/include/asm-arm/arch-at91sam9/at91sam9g45_matrix.h u-boot-1.3.4/include/asm-arm/arch-at91sam9/at91sam9g45_matrix.h
+--- u-boot-1.3.4-vanilla/include/asm-arm/arch-at91sam9/at91sam9g45_matrix.h	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/include/asm-arm/arch-at91sam9/at91sam9g45_matrix.h	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,153 @@
++/*
++ * Matrix-centric header file for the AT91SAM9M1x family
++ *
++ *  Copyright (C) 2008 Atmel Corporation.
++ *
++ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
++ * Based on AT91SAM9G45 preliminary datasheet.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91SAM9G45_MATRIX_H
++#define AT91SAM9G45_MATRIX_H
++
++#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
++#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
++#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
++#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
++#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
++#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
++#define AT91_MATRIX_MCFG6	(AT91_MATRIX + 0x18)	/* Master Configuration Register 6 */
++#define AT91_MATRIX_MCFG7	(AT91_MATRIX + 0x1C)	/* Master Configuration Register 7 */
++#define AT91_MATRIX_MCFG8	(AT91_MATRIX + 0x20)	/* Master Configuration Register 8 */
++#define AT91_MATRIX_MCFG9	(AT91_MATRIX + 0x24)	/* Master Configuration Register 9 */
++#define AT91_MATRIX_MCFG10	(AT91_MATRIX + 0x28)	/* Master Configuration Register 10 */
++#define AT91_MATRIX_MCFG11	(AT91_MATRIX + 0x2C)	/* Master Configuration Register 11 */
++#define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
++#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
++#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
++#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
++#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
++#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
++#define			AT91_MATRIX_ULBT_THIRTYTWO	(5 << 0)
++#define			AT91_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
++#define			AT91_MATRIX_ULBT_128		(7 << 0)
++
++#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
++#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
++#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
++#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
++#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
++#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration Register 5 */
++#define AT91_MATRIX_SCFG6	(AT91_MATRIX + 0x58)	/* Slave Configuration Register 6 */
++#define AT91_MATRIX_SCFG7	(AT91_MATRIX + 0x5C)	/* Slave Configuration Register 7 */
++#define		AT91_MATRIX_SLOT_CYCLE		(0x1ff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
++#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
++#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
++#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
++#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
++#define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
++
++#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
++#define AT91_MATRIX_PRBS0	(AT91_MATRIX + 0x84)	/* Priority Register B for Slave 0 */
++#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
++#define AT91_MATRIX_PRBS1	(AT91_MATRIX + 0x8C)	/* Priority Register B for Slave 1 */
++#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
++#define AT91_MATRIX_PRBS2	(AT91_MATRIX + 0x94)	/* Priority Register B for Slave 2 */
++#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
++#define AT91_MATRIX_PRBS3	(AT91_MATRIX + 0x9C)	/* Priority Register B for Slave 3 */
++#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
++#define AT91_MATRIX_PRBS4	(AT91_MATRIX + 0xA4)	/* Priority Register B for Slave 4 */
++#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
++#define AT91_MATRIX_PRBS5	(AT91_MATRIX + 0xAC)	/* Priority Register B for Slave 5 */
++#define AT91_MATRIX_PRAS6	(AT91_MATRIX + 0xB0)	/* Priority Register A for Slave 6 */
++#define AT91_MATRIX_PRBS6	(AT91_MATRIX + 0xB4)	/* Priority Register B for Slave 6 */
++#define AT91_MATRIX_PRAS7	(AT91_MATRIX + 0xB8)	/* Priority Register A for Slave 7 */
++#define AT91_MATRIX_PRBS7	(AT91_MATRIX + 0xBC)	/* Priority Register B for Slave 7 */
++#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
++#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
++#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
++#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
++#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
++#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
++#define		AT91_MATRIX_M6PR		(3 << 24)	/* Master 6 Priority */
++#define		AT91_MATRIX_M7PR		(3 << 28)	/* Master 7 Priority */
++#define		AT91_MATRIX_M8PR		(3 << 0)	/* Master 8 Priority (in Register B) */
++#define		AT91_MATRIX_M9PR		(3 << 4)	/* Master 9 Priority (in Register B) */
++#define		AT91_MATRIX_M10PR		(3 << 8)	/* Master 10 Priority (in Register B) */
++#define		AT91_MATRIX_M11PR		(3 << 12)	/* Master 11 Priority (in Register B) */
++
++#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
++#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
++#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
++#define		AT91_MATRIX_RCB2		(1 << 2)
++#define		AT91_MATRIX_RCB3		(1 << 3)
++#define		AT91_MATRIX_RCB4		(1 << 4)
++#define		AT91_MATRIX_RCB5		(1 << 5)
++#define		AT91_MATRIX_RCB6		(1 << 6)
++#define		AT91_MATRIX_RCB7		(1 << 7)
++#define		AT91_MATRIX_RCB8		(1 << 8)
++#define		AT91_MATRIX_RCB9		(1 << 9)
++#define		AT91_MATRIX_RCB10		(1 << 10)
++#define		AT91_MATRIX_RCB11		(1 << 11)
++
++#define AT91_MATRIX_TCMR	(AT91_MATRIX + 0x110)	/* TCM Configuration Register */
++#define		AT91_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
++#define			AT91_MATRIX_ITCM_0		(0 << 0)
++#define			AT91_MATRIX_ITCM_32		(6 << 0)
++#define		AT91_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled memory block */
++#define			AT91_MATRIX_DTCM_0		(0 << 4)
++#define			AT91_MATRIX_DTCM_32		(6 << 4)
++#define			AT91_MATRIX_DTCM_64		(7 << 4)
++#define		AT91_MATRIX_TCM_NWS		(0x1 << 11)	/* Wait state TCM register */
++#define			AT91_MATRIX_TCM_NO_WS		(0x0 << 11)
++#define			AT91_MATRIX_TCM_ONE_WS		(0x1 << 11)
++
++#define AT91_MATRIX_VIDEO	(AT91_MATRIX + 0x118)	/* Video Mode Configuration Register */
++#define		AT91C_VDEC_SEL			(0x1 <<  0) /* Video Mode Selection */
++#define			AT91C_VDEC_SEL_OFF		(0 << 0)
++#define			AT91C_VDEC_SEL_ON		(1 << 0)
++
++#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x128)	/* EBI Chip Select Assignment Register */
++#define		AT91_MATRIX_EBI_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
++#define			AT91_MATRIX_EBI_CS1A_SMC		(0 << 1)
++#define			AT91_MATRIX_EBI_CS1A_SDRAMC		(1 << 1)
++#define		AT91_MATRIX_EBI_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
++#define			AT91_MATRIX_EBI_CS3A_SMC		(0 << 3)
++#define			AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA	(1 << 3)
++#define		AT91_MATRIX_EBI_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
++#define			AT91_MATRIX_EBI_CS4A_SMC		(0 << 4)
++#define			AT91_MATRIX_EBI_CS4A_SMC_CF0		(1 << 4)
++#define		AT91_MATRIX_EBI_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
++#define			AT91_MATRIX_EBI_CS5A_SMC		(0 << 5)
++#define			AT91_MATRIX_EBI_CS5A_SMC_CF1		(1 << 5)
++#define		AT91_MATRIX_EBI_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
++#define			AT91_MATRIX_EBI_DBPU_ON			(0 << 8)
++#define			AT91_MATRIX_EBI_DBPU_OFF		(1 << 8)
++#define		AT91_MATRIX_EBI_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
++#define			AT91_MATRIX_EBI_VDDIOMSEL_1_8V		(0 << 16)
++#define			AT91_MATRIX_EBI_VDDIOMSEL_3_3V		(1 << 16)
++#define		AT91_MATRIX_EBI_EBI_IOSR	(1 << 17)	/* EBI I/O slew rate selection */
++#define			AT91_MATRIX_EBI_EBI_IOSR_REDUCED	(0 << 17)
++#define			AT91_MATRIX_EBI_EBI_IOSR_NORMAL		(1 << 17)
++#define		AT91_MATRIX_EBI_DDR_IOSR	(1 << 18)	/* DDR2 dedicated port I/O slew rate selection */
++#define			AT91_MATRIX_EBI_DDR_IOSR_REDUCED	(0 << 18)
++#define			AT91_MATRIX_EBI_DDR_IOSR_NORMAL		(1 << 18)
++
++#define AT91_MATRIX_WPMR	(AT91_MATRIX + 0x1E4)	/* Write Protect Mode Register */
++#define		AT91_MATRIX_WPMR_WPEN		(1 << 0)	/* Write Protect ENable */
++#define			AT91_MATRIX_WPMR_WP_WPDIS		(0 << 0)
++#define			AT91_MATRIX_WPMR_WP_WPEN		(1 << 0)
++#define		AT91_MATRIX_WPMR_WPKEY		(0xFFFFFF << 8)	/* Write Protect KEY */
++
++#define AT91_MATRIX_WPSR	(AT91_MATRIX + 0x1E8)	/* Write Protect Status Register */
++#define		AT91_MATRIX_WPSR_WPVS		(1 << 0)	/* Write Protect Violation Status */
++#define			AT91_MATRIX_WPSR_NO_WPV		(0 << 0)
++#define			AT91_MATRIX_WPSR_WPV		(1 << 0)
++#define		AT91_MATRIX_WPSR_WPVSRC		(0xFFFF << 8)	/* Write Protect Violation Source */
++
++#endif
+diff -uprN u-boot-1.3.4-vanilla/include/asm-arm/arch-at91sam9/hardware.h u-boot-1.3.4/include/asm-arm/arch-at91sam9/hardware.h
+--- u-boot-1.3.4-vanilla/include/asm-arm/arch-at91sam9/hardware.h	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/include/asm-arm/arch-at91sam9/hardware.h	2010-03-25 16:45:59.000000000 -0500
+@@ -18,13 +18,13 @@
+ 
+ #if defined(CONFIG_AT91RM9200)
+ #include <asm/arch/at91rm9200.h>
+-#elif defined(CONFIG_AT91SAM9260)
++#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+ #include <asm/arch/at91sam9260.h>
+ #define AT91_BASE_EMAC	AT91SAM9260_BASE_EMAC
+ #define AT91_BASE_SPI	AT91SAM9260_BASE_SPI0
+ #define AT91_ID_UHP	AT91SAM9260_ID_UHP
+ #define AT91_PMC_UHP	AT91SAM926x_PMC_UHP
+-#elif defined(CONFIG_AT91SAM9261)
++#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
+ #include <asm/arch/at91sam9261.h>
+ #define AT91_BASE_SPI	AT91SAM9261_BASE_SPI0
+ #define AT91_ID_UHP	AT91SAM9261_ID_UHP
+@@ -39,6 +39,12 @@
+ #include <asm/arch/at91sam9rl.h>
+ #define AT91_BASE_SPI	AT91SAM9RL_BASE_SPI
+ #define AT91_ID_UHP	AT91SAM9RL_ID_UHP
++#elif defined(CONFIG_AT91SAM9G45)
++#include <asm/arch/at91sam9g45.h>
++#define AT91_BASE_EMAC  AT91SAM9G45_BASE_EMAC
++#define AT91_BASE_SPI   AT91SAM9G45_BASE_SPI0
++#define AT91_ID_UHP     AT91SAM9G45_ID_UHPHS
++#define AT91_PMC_UHP    AT91SAM926x_PMC_UHP
+ #elif defined(CONFIG_AT91CAP9)
+ #include <asm/arch/at91cap9.h>
+ #define AT91_BASE_EMAC	AT91CAP9_BASE_EMAC
+diff -uprN u-boot-1.3.4-vanilla/include/asm-arm/mach-types.h u-boot-1.3.4/include/asm-arm/mach-types.h
+--- u-boot-1.3.4-vanilla/include/asm-arm/mach-types.h	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/include/asm-arm/mach-types.h	2010-03-25 16:45:59.000000000 -0500
+@@ -1595,7 +1595,13 @@ extern unsigned int __machine_arch_type;
+ #define MACH_TYPE_P300                 1602
+ #define MACH_TYPE_XDACOMET             1603
+ #define MACH_TYPE_DEXFLEX2             1604
++#define MACH_TYPE_AT91SAM9G20EK        1624
+ #define MACH_TYPE_SFFSDR               1657
++#define MACH_TYPE_AT91SAM9M10G45EK     1830
++#define MACH_TYPE_AT91SAM9G10EK        2159
++#define MACH_TYPE_AT91SAM9G45EKES      2212
++#define MACH_TYPE_AT91SAM9G20EK_2MMC   2288
++#define MACH_TYPE_AT91SAM9M10EKES      2509
+ 
+ #ifdef CONFIG_ARCH_EBSA110
+ # ifdef machine_arch_type
+@@ -11701,6 +11707,18 @@ extern unsigned int __machine_arch_type;
+ # define machine_is_at91sam9261ek()	(0)
+ #endif
+ 
++#ifdef CONFIG_MACH_AT91SAM9G10EK
++# ifdef machine_arch_type
++#  undef machine_arch_type
++#  define machine_arch_type    __machine_arch_type
++# else
++#  define machine_arch_type    MACH_TYPE_AT91SAM9G10EK
++# endif
++# define machine_is_at91sam9g10ek()    (machine_arch_type == MACH_TYPE_AT91SAM9G10EK)
++#else
++# define machine_is_at91sam9g10ek()    (0)
++#endif
++
+ #ifdef CONFIG_MACH_LOFT
+ # ifdef machine_arch_type
+ #  undef machine_arch_type
+@@ -20605,6 +20623,69 @@ extern unsigned int __machine_arch_type;
+ # define machine_is_dexflex2()	(0)
+ #endif
+ 
++#ifdef CONFIG_MACH_AT91SAM9G20EK
++# ifdef machine_arch_type
++#  undef machine_arch_type
++#  define machine_arch_type __machine_arch_type
++# else
++#  define machine_arch_type MACH_TYPE_AT91SAM9G20EK
++# endif
++# define machine_is_at91sam9g20ek() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK)
++#else
++# define machine_is_at91sam9g20ek() (0)
++#endif
++
++
++#ifdef CONFIG_MACH_AT91SAM9M10G45EK
++# ifdef machine_arch_type
++#  undef machine_arch_type
++#  define machine_arch_type __machine_arch_type
++# else
++#  define machine_arch_type MACH_TYPE_AT91SAM9M10G45EK
++# endif
++# define machine_is_at91sam9m10g45ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK)
++#else
++# define machine_is_at91sam9m10g45ek() (0)
++#endif
++
++#ifdef CONFIG_MACH_AT91SAM9G45EKES
++# ifdef machine_arch_type
++#  undef machine_arch_type
++#  define machine_arch_type	__machine_arch_type
++# else
++#  define machine_arch_type	MACH_TYPE_AT91SAM9G45EKES
++# endif
++# define machine_is_at91sam9g45ekes()	(machine_arch_type == MACH_TYPE_AT91SAM9G45EKES)
++#else
++# define machine_is_at91sam9g45ekes()	(0)
++#endif
++
++#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC
++# ifdef machine_arch_type
++#  undef machine_arch_type
++#  define machine_arch_type	__machine_arch_type
++# else
++#  define machine_arch_type	MACH_TYPE_AT91SAM9G20EK_2MMC
++# endif
++# define machine_is_at91sam9g20ek_2mmc()	(machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC)
++#else
++# define machine_is_at91sam9g20ek_2mmc()	(0)
++#endif
++
++#ifdef CONFIG_MACH_AT91SAM9M10EKES
++# ifdef machine_arch_type
++#  undef machine_arch_type
++#  define machine_arch_type	__machine_arch_type
++# else
++#  define machine_arch_type	MACH_TYPE_AT91SAM9M10EKES
++# endif
++# define machine_is_at91sam9m10ekes()	(machine_arch_type == MACH_TYPE_AT91SAM9M10EKES)
++#else
++# define machine_is_at91sam9m10ekes()	(0)
++#endif
++
++
++
+ /*
+  * These have not yet been registered
+  */
+diff -uprN u-boot-1.3.4-vanilla/include/configs/at91sam9260ek.h u-boot-1.3.4/include/configs/at91sam9260ek.h
+--- u-boot-1.3.4-vanilla/include/configs/at91sam9260ek.h	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/include/configs/at91sam9260ek.h	2010-03-25 16:45:59.000000000 -0500
+@@ -127,10 +127,6 @@
+ #define CFG_MEMTEST_START		PHYS_SDRAM
+ #define CFG_MEMTEST_END			0x23e00000
+ 
+-#undef CFG_USE_DATAFLASH_CS0
+-#define CFG_USE_DATAFLASH_CS1		1
+-#undef CFG_USE_NANDFLASH
+-
+ #ifdef CFG_USE_DATAFLASH_CS0
+ 
+ /* bootstrap + u-boot + env + linux in dataflash on CS0 */
+diff -uprN u-boot-1.3.4-vanilla/include/configs/at91sam9261ek.h u-boot-1.3.4/include/configs/at91sam9261ek.h
+--- u-boot-1.3.4-vanilla/include/configs/at91sam9261ek.h	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/include/configs/at91sam9261ek.h	2010-03-25 16:45:59.000000000 -0500
+@@ -142,9 +142,6 @@
+ #define CFG_MEMTEST_START		PHYS_SDRAM
+ #define CFG_MEMTEST_END			0x23e00000
+ 
+-#define CFG_USE_DATAFLASH_CS0		1
+-#undef CFG_USE_NANDFLASH
+-
+ #ifdef CFG_USE_DATAFLASH_CS0
+ 
+ /* bootstrap + u-boot + env + linux in dataflash on CS0 */
+@@ -159,6 +156,20 @@
+ 				"mtdparts=at91_nand:-(root) "		\
+ 				"rw rootfstype=jffs2"
+ 
++#elif CFG_USE_DATAFLASH_CS3
++
++/* bootstrap + u-boot + env + linux in dataflash on CS3 */
++#define CFG_ENV_IS_IN_DATAFLASH	1
++#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
++#define CFG_ENV_OFFSET		0x4200
++#define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS3 + CFG_ENV_OFFSET)
++#define CFG_ENV_SIZE		0x4200
++#define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
++#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
++				"root=/dev/mtdblock0 "			\
++				"mtdparts=at91_nand:-(root) "		\
++				"rw rootfstype=jffs2"
++
+ #else /* CFG_USE_NANDFLASH */
+ 
+ /* bootstrap + u-boot + env + linux in nandflash */
+diff -uprN u-boot-1.3.4-vanilla/include/configs/at91sam9263ek.h u-boot-1.3.4/include/configs/at91sam9263ek.h
+--- u-boot-1.3.4-vanilla/include/configs/at91sam9263ek.h	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/include/configs/at91sam9263ek.h	2010-03-25 16:45:59.000000000 -0500
+@@ -148,9 +148,6 @@
+ #define CFG_MEMTEST_START		PHYS_SDRAM
+ #define CFG_MEMTEST_END			0x23e00000
+ 
+-#define CFG_USE_DATAFLASH		1
+-#undef CFG_USE_NANDFLASH
+-
+ #ifdef CFG_USE_DATAFLASH
+ 
+ /* bootstrap + u-boot + env + linux in dataflash on CS0 */
+diff -uprN u-boot-1.3.4-vanilla/include/configs/at91sam9g10ek.h u-boot-1.3.4/include/configs/at91sam9g10ek.h
+--- u-boot-1.3.4-vanilla/include/configs/at91sam9g10ek.h	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/include/configs/at91sam9g10ek.h	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,213 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * Configuation settings for the AT91SAM9G10EK board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/* ARM asynchronous clock */
++#define AT91_CPU_NAME		"AT91SAM9G10"
++#define AT91_MAIN_CLOCK		266000000	/* from 18.432 MHz crystal */
++#define AT91_MASTER_CLOCK	133000000	/* peripheral = main / 2 */
++#define CFG_HZ			1000000		/* 1us resolution */
++
++#define AT91_SLOW_CLOCK		32768	/* slow clock */
++
++#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
++#define CONFIG_AT91SAM9G10	1	/* It's an Atmel AT91SAM9G10 SoC*/
++#define CONFIG_AT91SAM9G10EK	1	/* on an AT91SAM9G10EK Board	*/
++#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
++
++#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_INITRD_TAG	1
++
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SKIP_RELOCATE_UBOOT
++
++/*
++ * Hardware drivers
++ */
++#define CONFIG_ATMEL_USART	1
++#undef CONFIG_USART0
++#undef CONFIG_USART1
++#undef CONFIG_USART2
++#define CONFIG_USART3		1	/* USART 3 is DBGU */
++
++/* LCD */
++#define CONFIG_LCD			1
++#define LCD_BPP				LCD_COLOR8
++#define CONFIG_LCD_LOGO			1
++#undef LCD_TEST_PATTERN
++#define CONFIG_LCD_INFO			1
++#define CONFIG_LCD_INFO_BELOW_LOGO	1
++#define CFG_WHITE_ON_BLACK		1
++#define CONFIG_ATMEL_LCD		1
++/* #define CONFIG_ATMEL_LCD_BGR555		1 */
++#define CFG_CONSOLE_IS_IN_ENV		1
++
++#define CONFIG_BOOTDELAY	3
++
++/*
++ * BOOTP options
++ */
++#define CONFIG_BOOTP_BOOTFILESIZE	1
++#define CONFIG_BOOTP_BOOTPATH		1
++#define CONFIG_BOOTP_GATEWAY		1
++#define CONFIG_BOOTP_HOSTNAME		1
++
++/*
++ * Command line configuration.
++ */
++#include <config_cmd_default.h>
++#undef CONFIG_CMD_BDI
++#undef CONFIG_CMD_IMI
++#undef CONFIG_CMD_AUTOSCRIPT
++#undef CONFIG_CMD_FPGA
++#undef CONFIG_CMD_LOADS
++#undef CONFIG_CMD_IMLS
++
++#define CONFIG_CMD_PING		1
++#define CONFIG_CMD_DHCP		1
++#define CONFIG_CMD_NAND		1
++#define CONFIG_CMD_USB		1
++
++/* SDRAM */
++#define CONFIG_NR_DRAM_BANKS		1
++#define PHYS_SDRAM			0x20000000
++#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */
++
++/* DataFlash */
++#define CONFIG_HAS_DATAFLASH		1
++#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
++#define CFG_MAX_DATAFLASH_BANKS		2
++#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
++#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */
++#define AT91_SPI_CLK			15000000
++#define DATAFLASH_TCSS			(0x1a << 16)
++#define DATAFLASH_TCHS			(0x1 << 24)
++
++/* NAND flash */
++#define NAND_MAX_CHIPS			1
++#define CFG_MAX_NAND_DEVICE		1
++#define CFG_NAND_BASE			0x40000000
++#define CFG_NAND_DBW_8			1
++
++/* NOR flash - no real flash on this board */
++#define CFG_NO_FLASH			1
++
++/* Ethernet */
++#define CONFIG_DRIVER_DM9000		1
++#define CONFIG_DM9000_BASE		0x30000000
++#define DM9000_IO			CONFIG_DM9000_BASE
++#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
++#define CONFIG_DM9000_USE_16BIT		1
++#define CONFIG_NET_RETRY_COUNT		20
++#define CONFIG_RESET_PHY_R		1
++
++/* USB */
++#define CONFIG_USB_OHCI_NEW		1
++#define LITTLEENDIAN			1
++#define CONFIG_DOS_PARTITION		1
++#define CFG_USB_OHCI_CPU_INIT		1
++#define CFG_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9G10_UHP_BASE */
++#define CFG_USB_OHCI_SLOT_NAME		"at91sam9g10"
++#define CFG_USB_OHCI_MAX_ROOT_PORTS	2
++#define CONFIG_USB_STORAGE		1
++
++#define CFG_LOAD_ADDR			0x22000000	/* load address */
++
++#define CFG_MEMTEST_START		PHYS_SDRAM
++#define CFG_MEMTEST_END			0x23e00000
++
++#ifdef CFG_USE_DATAFLASH_CS0
++
++/* bootstrap + u-boot + env + linux in dataflash on CS0 */
++#define CFG_ENV_IS_IN_DATAFLASH	1
++#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
++#define CFG_ENV_OFFSET		0x4200
++#define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
++#define CFG_ENV_SIZE		0x4200
++#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
++#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
++				"root=/dev/mtdblock0 "			\
++				"mtdparts=at91_nand:-(root) "		\
++				"rw rootfstype=jffs2"
++
++#elif CFG_USE_DATAFLASH_CS3
++
++/* bootstrap + u-boot + env + linux in dataflash on CS3 */
++#define CFG_ENV_IS_IN_DATAFLASH	1
++#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
++#define CFG_ENV_OFFSET		0x4200
++#define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS3 + CFG_ENV_OFFSET)
++#define CFG_ENV_SIZE		0x4200
++#define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
++#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
++				"root=/dev/mtdblock0 "			\
++				"mtdparts=at91_nand:-(root) "		\
++				"rw rootfstype=jffs2"
++
++#else /* CFG_USE_NANDFLASH */
++
++/* bootstrap + u-boot + env + linux in nandflash */
++#define CFG_ENV_IS_IN_NAND	1
++#define CFG_ENV_OFFSET		0x60000
++#define CFG_ENV_OFFSET_REDUND	0x80000
++#define CFG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
++#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
++#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
++				"root=/dev/mtdblock5 "			\
++				"mtdparts=at91_nand:128k(bootstrap)ro,"	\
++				"256k(uboot)ro,128k(env1)ro,"		\
++				"128k(env2)ro,2M(linux),-(root) "	\
++				"rw rootfstype=jffs2"
++
++#endif
++
++#define CONFIG_BAUDRATE		115200
++#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
++
++#define CFG_PROMPT		"U-Boot> "
++#define CFG_CBSIZE		256
++#define CFG_MAXARGS		16
++#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
++#define CFG_LONGHELP		1
++#define CONFIG_CMDLINE_EDITING	1
++
++#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN		ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
++#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
++
++#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
++
++#ifdef CONFIG_USE_IRQ
++#error CONFIG_USE_IRQ not supported
++#endif
++
++#endif
+diff -uprN u-boot-1.3.4-vanilla/include/configs/at91sam9g20ek.h u-boot-1.3.4/include/configs/at91sam9g20ek.h
+--- u-boot-1.3.4-vanilla/include/configs/at91sam9g20ek.h	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/include/configs/at91sam9g20ek.h	2010-05-04 13:55:32.000000000 -0500
+@@ -0,0 +1,212 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * Configuation settings for the AT91SAM9G20EK board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/* ARM asynchronous clock */
++#define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
++#define AT91_MASTER_CLOCK	132096000	/* PLLA = main * 43 / 6 */
++#define CFG_HZ			1000000		/* 1us resolution */
++
++#define AT91_SLOW_CLOCK		32768	/* slow clock */
++
++#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
++#define CONFIG_AT91SAM9G20	1	/* It's an Atmel AT91SAM9G20 SoC*/
++#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
++
++#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_INITRD_TAG	1
++
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SKIP_RELOCATE_UBOOT
++
++/*
++ * Hardware drivers
++ */
++#define CONFIG_ATMEL_USART	1
++#undef CONFIG_USART0
++#undef CONFIG_USART1
++#undef CONFIG_USART2
++#define CONFIG_USART3		1	/* USART 3 is DBGU */
++
++#define CONFIG_BOOTDELAY	1
++
++/*
++ * BOOTP options
++ */
++#define CONFIG_BOOTP_BOOTFILESIZE	1
++#define CONFIG_BOOTP_BOOTPATH		1
++#define CONFIG_BOOTP_GATEWAY		1
++#define CONFIG_BOOTP_HOSTNAME		1
++
++/*
++ * Command line configuration.
++ */
++#include <config_cmd_default.h>
++#undef CONFIG_CMD_BDI
++#undef CONFIG_CMD_IMI
++#undef CONFIG_CMD_AUTOSCRIPT
++#undef CONFIG_CMD_FPGA
++#undef CONFIG_CMD_LOADS
++#undef CONFIG_CMD_IMLS
++
++#define CONFIG_CMD_PING		1
++#define CONFIG_CMD_DHCP		1
++#define CONFIG_CMD_NAND		1
++#define CONFIG_CMD_USB		1
++
++/* SDRAM */
++#define CONFIG_NR_DRAM_BANKS		1
++#define PHYS_SDRAM			0x20000000
++#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */
++
++/* DataFlash */
++#define CONFIG_HAS_DATAFLASH		1
++#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
++#define CFG_MAX_DATAFLASH_BANKS		2
++#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
++#define CFG_DATAFLASH_LOGIC_ADDR_CS1	0xD0000000	/* CS1 */
++#define AT91_SPI_CLK			15000000
++#define DATAFLASH_TCSS			(0x22 << 16)
++#define DATAFLASH_TCHS			(0x1 << 24)
++
++/* NAND flash */
++#define NAND_MAX_CHIPS			1
++#define CFG_MAX_NAND_DEVICE		1
++#define CFG_NAND_BASE			0x40000000
++#define CFG_NAND_DBW_8			1
++
++/* NOR flash - no real flash on this board */
++#define CFG_NO_FLASH			1
++
++/* Ethernet */
++#define CONFIG_NET			1
++#define CONFIG_MACB			1
++#define CONFIG_MII			1
++#define CONFIG_NET_MULTI		1
++#define CONFIG_NET_RETRY_COUNT		20
++#define CONFIG_RESET_PHY_R		1
++
++/* USB */
++#define CONFIG_USB_OHCI_NEW		1
++#define LITTLEENDIAN			1
++#define CONFIG_DOS_PARTITION		1
++#define CFG_USB_OHCI_CPU_INIT		1
++#define CFG_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9G20_UHP_BASE */
++#define CFG_USB_OHCI_SLOT_NAME		"at91sam9g20"
++#define CFG_USB_OHCI_MAX_ROOT_PORTS	2
++#define CONFIG_USB_STORAGE		1
++
++#define CFG_LOAD_ADDR			0x22000000	/* load address */
++
++#define CFG_MEMTEST_START		PHYS_SDRAM
++#define CFG_MEMTEST_END			0x23e00000
++
++#ifdef CFG_USE_DATAFLASH_CS0
++
++/* bootstrap + u-boot + env + linux in dataflash on CS0 */
++#define CFG_ENV_IS_IN_DATAFLASH	1
++#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
++#define CFG_ENV_OFFSET		0x4200
++#define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
++#define CFG_ENV_SIZE		0x4200
++#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
++#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
++				"root=/dev/mtdblock0 "			\
++				"mtdparts=at91_nand:-(root) "		\
++				"rw rootfstype=jffs2"
++
++#elif CFG_USE_DATAFLASH_CS1
++
++/* bootstrap + u-boot + env + linux in dataflash on CS1 */
++#define CFG_ENV_IS_IN_DATAFLASH	1
++#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
++#define CFG_ENV_OFFSET		0x4200
++#define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET)
++#define CFG_ENV_SIZE		0x4200
++#define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
++#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
++				"root=/dev/mtdblock0 "			\
++				"mtdparts=at91_nand:-(root) "		\
++				"rw rootfstype=jffs2"
++
++#else /* CFG_USE_NANDFLASH */
++
++/* bootstrap + u-boot + env + linux in nandflash */
++#define CFG_ENV_IS_IN_NAND	1
++#define CFG_ENV_OFFSET		0x60000
++#define CFG_ENV_OFFSET_REDUND	0x80000
++#define CFG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
++#define CONFIG_BOOTCOMMAND	"nboot.jffs2 ${loadaddr} 0 ${kernel_addr}; bootm ${loadaddr}"
++#define CONFIG_BOOTARGS		"mem=64M "				\
++				"console=ttyS0,115200 "			\
++				"root=/dev/mtdblock8 "			\
++				"ro rootfstype=jffs2"
++
++#endif
++
++#define CONFIG_BAUDRATE		115200
++#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
++
++#define CFG_PROMPT		"U-Boot> "
++#define CFG_CBSIZE		256
++#define CFG_MAXARGS		16
++#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
++#define CFG_LONGHELP		1
++#define CONFIG_CMDLINE_EDITING	1
++
++#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN		ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
++#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
++
++#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
++
++#ifdef CONFIG_USE_IRQ
++#error CONFIG_USE_IRQ not supported
++#endif
++
++#define CONFIG_AUTO_COMPLETE	1
++
++#define CONFIG_ENV_OVERWRITE	1
++#define CONFIG_ETHADDR		00:08:00:87:00:02
++#define CONFIG_IPADDR		192.168.2.1
++#define CONFIG_NETMASK		255.255.255.0
++#define CONFIG_SERVERIP		192.168.2.2
++#define CONFIG_HOSTNAME		AT91SAM9G20
++#define CONFIG_LOADADDR		0x21400000
++
++#define CONFIG_EXTRA_ENV_SETTINGS			\
++	"kernel_addr=0x000A0000\0"			\
++	""
++
++#define CONFIG_ZERO_BOOTDELAY_CHECK		1
++
++#endif
+diff -uprN u-boot-1.3.4-vanilla/include/configs/at91sam9m10g45ek.h u-boot-1.3.4/include/configs/at91sam9m10g45ek.h
+--- u-boot-1.3.4-vanilla/include/configs/at91sam9m10g45ek.h	1969-12-31 17:00:00.000000000 -0700
++++ u-boot-1.3.4/include/configs/at91sam9m10g45ek.h	2010-03-25 16:45:59.000000000 -0500
+@@ -0,0 +1,217 @@
++/*
++ * (C) Copyright 2007-2008
++ * Stelian Pop <stelian.pop@leadtechdesign.com>
++ * Lead Tech Design <www.leadtechdesign.com>
++ *
++ * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/* ARM asynchronous clock */
++#define AT91_CPU_NAME		"AT91SAM9G45"
++#define AT91_MAIN_CLOCK		400000000	/* from 12 MHz crystal */
++#define AT91_MASTER_CLOCK	133000000	/* peripheral = main / 3 */
++#define CFG_HZ			1000000		/* 1us resolution */
++
++#define AT91_SLOW_CLOCK		32768	/* slow clock */
++
++#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
++#define CONFIG_AT91SAM9G45	1	/* It's an Atmel AT91SAM9G45 SoC*/
++
++#ifdef CFG_USE_AT91SAM9M10G45EK
++#define CONFIG_AT91SAM9M10G45EK	1	/* on an AT91SAM9M10G45EK Board	*/
++#endif
++
++#ifdef CFG_USE_AT91SAM9G45EKES
++#define CONFIG_AT91SAM9G45EKES	1	/* on an AT91SAM9G45EKES Board	*/
++#endif
++
++#ifdef CFG_USE_AT91SAM9M10EKES
++#define CONFIG_AT91SAM9M10EKES  1       /* on an AT91SAM9M10EKES Board  */
++#endif
++
++#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
++
++#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_INITRD_TAG	1
++
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SKIP_RELOCATE_UBOOT
++
++/*
++ * Hardware drivers
++ */
++#define CONFIG_ATMEL_USART	1
++#undef CONFIG_USART0
++#undef CONFIG_USART1
++#undef CONFIG_USART2
++#define CONFIG_USART3		1	/* USART 3 is DBGU */
++
++/* LCD */
++//#define CONFIG_LCD			1
++#undef CONFIG_LCD
++#define LCD_BPP				LCD_COLOR8
++#define CONFIG_LCD_LOGO			1
++#undef LCD_TEST_PATTERN
++#define CONFIG_LCD_INFO			1
++#define CONFIG_LCD_INFO_BELOW_LOGO	1
++#define CFG_WHITE_ON_BLACK		1
++#define CONFIG_ATMEL_LCD		1
++#define CONFIG_ATMEL_LCD_BGR555		1
++#define CFG_CONSOLE_IS_IN_ENV		1
++
++#define CONFIG_BOOTDELAY	3
++
++/*
++ * BOOTP options
++ */
++#define CONFIG_BOOTP_BOOTFILESIZE	1
++#define CONFIG_BOOTP_BOOTPATH		1
++#define CONFIG_BOOTP_GATEWAY		1
++#define CONFIG_BOOTP_HOSTNAME		1
++
++/*
++ * Command line configuration.
++ */
++#include <config_cmd_default.h>
++#undef CONFIG_CMD_BDI
++#undef CONFIG_CMD_IMI
++#undef CONFIG_CMD_AUTOSCRIPT
++#undef CONFIG_CMD_FPGA
++#undef CONFIG_CMD_LOADS
++#undef CONFIG_CMD_IMLS
++
++#define CONFIG_CMD_PING		1
++#define CONFIG_CMD_DHCP		1
++#define CONFIG_CMD_NAND		1
++#define CONFIG_CMD_USB		1
++
++/* SDRAM */
++#define CONFIG_NR_DRAM_BANKS		1
++#define PHYS_SDRAM			0x70000000
++#define PHYS_SDRAM_SIZE			0x08000000	/* 128 megs */
++
++/* DataFlash */
++#define CONFIG_HAS_DATAFLASH		1
++#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
++#define CFG_MAX_DATAFLASH_BANKS		1
++#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
++#define AT91_SPI_CLK			15000000
++#define DATAFLASH_TCSS			(0x1a << 16)
++#define DATAFLASH_TCHS			(0x1 << 24)
++
++/* NOR flash, if populated */
++#if 1
++#define CFG_NO_FLASH			1
++#else
++#define CFG_FLASH_CFI			1
++#define CONFIG_FLASH_CFI_DRIVER		1
++#define PHYS_FLASH_1			0x10000000
++#define CFG_FLASH_BASE			PHYS_FLASH_1
++#define CFG_MAX_FLASH_SECT		256
++#define CFG_MAX_FLASH_BANKS		1
++#endif
++
++/* NAND flash */
++#define NAND_MAX_CHIPS			1
++#define CFG_MAX_NAND_DEVICE		1
++#define CFG_NAND_BASE			0x40000000
++#define CFG_NAND_DBW_8			1
++
++/* Ethernet */
++#define CONFIG_MACB			1
++/* #define CONFIG_MII			1 */
++#define CONFIG_RMII			1
++#define CONFIG_NET_MULTI		1
++#define CONFIG_NET_RETRY_COUNT		20
++#define CONFIG_RESET_PHY_R		1
++
++/* USB */
++#define CONFIG_USB_OHCI_NEW		1
++#define LITTLEENDIAN			1
++#define CONFIG_DOS_PARTITION		1
++#define CFG_USB_OHCI_CPU_INIT		1
++#define CFG_USB_OHCI_REGS_BASE		0x00700000	/* AT91SAM9G45_UHP_OHCI_BASE */
++#define CFG_USB_OHCI_SLOT_NAME		"at91sam9g45"
++#define CFG_USB_OHCI_MAX_ROOT_PORTS	2
++#define CONFIG_USB_STORAGE		1
++
++#define CFG_LOAD_ADDR			0x22000000	/* load address */
++
++#define CFG_MEMTEST_START		PHYS_SDRAM
++#define CFG_MEMTEST_END			0x23e00000
++
++#ifdef CFG_USE_DATAFLASH
++
++/* bootstrap + u-boot + env + linux in dataflash on CS0 */
++#define CFG_ENV_IS_IN_DATAFLASH	1
++#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
++#define CFG_ENV_OFFSET		0x4200
++#define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
++#define CFG_ENV_SIZE		0x4200
++#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
++#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
++				"root=/dev/mtdblock0 " \
++				"mtdparts=at91_nand:-(root) "\
++				"rw rootfstype=jffs2"
++
++#else /* CFG_USE_NANDFLASH */
++
++/* bootstrap + u-boot + env + linux in nandflash */
++#define CFG_ENV_IS_IN_NAND	1
++#define CFG_ENV_OFFSET		0x60000
++#define CFG_ENV_OFFSET_REDUND	0x80000
++#define CFG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
++#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
++#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
++				"root=/dev/mtdblock5 " \
++				"mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
++				"rw rootfstype=jffs2"
++
++#endif
++
++#define CONFIG_BAUDRATE		115200
++#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
++
++#define CFG_PROMPT		"U-Boot> "
++#define CFG_CBSIZE		256
++#define CFG_MAXARGS		16
++#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
++#define CFG_LONGHELP		1
++#define CONFIG_CMDLINE_EDITING	1
++
++#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN		ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
++#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
++
++#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
++
++#ifdef CONFIG_USE_IRQ
++#error CONFIG_USE_IRQ not supported
++#endif
++
++#endif
+diff -uprN u-boot-1.3.4-vanilla/include/configs/at91sam9rlek.h u-boot-1.3.4/include/configs/at91sam9rlek.h
+--- u-boot-1.3.4-vanilla/include/configs/at91sam9rlek.h	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/include/configs/at91sam9rlek.h	2010-03-25 16:45:59.000000000 -0500
+@@ -117,9 +117,6 @@
+ #define CFG_MEMTEST_START		PHYS_SDRAM
+ #define CFG_MEMTEST_END			0x23e00000
+ 
+-#define CFG_USE_DATAFLASH		1
+-#undef CFG_USE_NANDFLASH
+-
+ #ifdef CFG_USE_DATAFLASH
+ 
+ /* bootstrap + u-boot + env + linux in dataflash on CS0 */
+diff -uprN u-boot-1.3.4-vanilla/Makefile u-boot-1.3.4/Makefile
+--- u-boot-1.3.4-vanilla/Makefile	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/Makefile	2010-05-13 14:00:22.000000000 -0500
+@@ -2353,15 +2353,6 @@ shannon_config	:	unconfig
+ at91rm9200dk_config	:	unconfig
+ 	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
+ 
+-at91sam9261ek_config	:	unconfig
+-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91sam9
+-
+-at91sam9263ek_config	:	unconfig
+-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9
+-
+-at91sam9rlek_config	:	unconfig
+-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91sam9
+-
+ cmc_pu2_config	:	unconfig
+ 	@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
+ 
+@@ -2384,8 +2375,175 @@ mp2usb_config	:	unconfig
+ at91cap9adk_config	:	unconfig
+ 	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91sam9
+ 
++at91sam9260ek_nandflash_config \
++at91sam9260ek_dataflash_cs0_config \
++at91sam9260ek_dataflash_cs1_config \
+ at91sam9260ek_config	:	unconfig
+-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91sam9
++	@mkdir -p $(obj)include
++	@if [ "$(findstring _nandflash,$@)" ] ; then \
++		echo "#define CFG_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in NAND FLASH" ; \
++	elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
++		echo "#define CFG_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
++	else \
++		echo "#define CFG_USE_DATAFLASH_CS1 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \
++	fi;
++	@$(MKCONFIG) -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91sam9
++
++at91sam9xeek_nandflash_config \
++at91sam9xeek_dataflash_cs0_config \
++at91sam9xeek_dataflash_cs1_config \
++at91sam9xeek_config	:	unconfig
++	@mkdir -p $(obj)include
++	@if [ "$(findstring _nandflash,$@)" ] ; then \
++		echo "#define CFG_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in NAND FLASH" ; \
++	elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
++		echo "#define CFG_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
++	else \
++		echo "#define CFG_USE_DATAFLASH_CS1 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \
++	fi;
++	@$(MKCONFIG) -n at91sam9xeek -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91sam9
++
++at91sam9g20ek_nandflash_config \
++at91sam9g20ek_dataflash_cs0_config \
++at91sam9g20ek_dataflash_cs1_config \
++at91sam9g20ek_2mmc_nandflash_config \
++at91sam9g20ek_2mmc_dataflash_cs0_config \
++at91sam9g20ek_2mmc_dataflash_cs1_config \
++at91sam9g20ek_config	:	unconfig
++	@mkdir -p $(obj)include
++	@if [ "$(findstring _nandflash,$@)" ] ; then \
++		echo "#define CFG_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in NAND FLASH" ; \
++	elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
++		echo "#define CFG_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
++	else \
++		echo "#define CFG_USE_DATAFLASH_CS1 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \
++	fi;
++	@if [ "$(findstring _2mmc_,$@)" ] ; then \
++		echo "#define CONFIG_AT91SAM9G20EK_2MMC 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... AT91SAM9G20EK board with two SD/MMC slots" ; \
++	else \
++		echo "#define CONFIG_AT91SAM9G20EK 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... AT91SAM9G20EK Board" ; \
++	fi;
++	@$(MKCONFIG) -a at91sam9g20ek arm arm926ejs at91sam9g20ek atmel at91sam9
++
++at91sam9261ek_nandflash_config \
++at91sam9261ek_dataflash_cs0_config \
++at91sam9261ek_dataflash_cs3_config \
++at91sam9261ek_config	:	unconfig
++	@mkdir -p $(obj)include
++	@if [ "$(findstring _nandflash,$@)" ] ; then \
++		echo "#define CFG_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in NAND FLASH" ; \
++	elif [ "$(findstring dataflash_cs3,$@)" ] ; then \
++		echo "#define CFG_USE_DATAFLASH_CS3 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS3" ; \
++	else \
++		echo "#define CFG_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
++	fi;
++	@$(MKCONFIG) -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91sam9
++
++at91sam9g10ek_nandflash_config \
++at91sam9g10ek_dataflash_cs0_config \
++at91sam9g10ek_dataflash_cs3_config \
++at91sam9g10ek_config   :   unconfig
++	@if [ "$(findstring _nandflash,$@)" ] ; then \
++		echo "#define CFG_USE_NANDFLASH 1"  >>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in NAND FLASH" ; \
++	elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
++		echo "#define CFG_USE_DATAFLASH_CS0 1"  >>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
++	else \
++		echo "#define CFG_USE_DATAFLASH_CS3 1"  >>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS3" ; \
++	fi;
++	@$(MKCONFIG) -a at91sam9g10ek arm arm926ejs at91sam9g10ek atmel at91sam9
++
++at91sam9263ek_nandflash_config \
++at91sam9263ek_dataflash_config \
++at91sam9263ek_dataflash_cs0_config \
++at91sam9263ek_config	:	unconfig
++	@mkdir -p $(obj)include
++	@if [ "$(findstring _nandflash,$@)" ] ; then \
++		echo "#define CFG_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in NAND FLASH" ; \
++	else \
++		echo "#define CFG_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
++	fi;
++	@$(MKCONFIG) -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91sam9
++
++at91sam9rlek_nandflash_config \
++at91sam9rlek_dataflash_config \
++at91sam9rlek_dataflash_cs0_config \
++at91sam9rlek_config	:	unconfig
++	@mkdir -p $(obj)include
++	@if [ "$(findstring _nandflash,$@)" ] ; then \
++		echo "#define CFG_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in NAND FLASH" ; \
++	else \
++		echo "#define CFG_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
++	fi;
++	@$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91sam9
++
++at91sam9m10g45ek_nandflash_config \
++at91sam9m10g45ek_dataflash_config \
++at91sam9m10g45ek_dataflash_cs0_config \
++at91sam9m10g45ek_config	:	unconfig
++	@mkdir -p $(obj)include
++	@if [ "$(findstring _nandflash,$@)" ] ; then \
++		echo "#define CFG_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in NAND FLASH" ; \
++		echo "#define CFG_USE_AT91SAM9M10G45EK 1"	>>$(obj)include/config.h ; \
++	else \
++		echo "#define CFG_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
++		echo "#define CFG_USE_AT91SAM9M10G45EK 1"	>>$(obj)include/config.h ; \
++	fi;
++	@$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91sam9
++
++at91sam9g45ekes_nandflash_config \
++at91sam9g45ekes_dataflash_config \
++at91sam9g45ekes_dataflash_cs0_config \
++at91sam9g45ekes_config	:	unconfig
++	@mkdir -p $(obj)include
++	@if [ "$(findstring _nandflash,$@)" ] ; then \
++		echo "#define CFG_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in NAND FLASH" ; \
++		echo "#define CFG_USE_AT91SAM9G45EKES 1"	>>$(obj)include/config.h ; \
++	else \
++		echo "#define CFG_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
++		echo "#define CFG_USE_AT91SAM9G45EKES 1"	>>$(obj)include/config.h ; \
++	fi;
++	@$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91sam9
++
++at91sam9m10ekes_nandflash_config \
++at91sam9m10ekes_dataflash_config \
++at91sam9m10ekes_dataflash_cs0_config \
++at91sam9m10ekes_config	:	unconfig
++	@mkdir -p $(obj)include
++	@if [ "$(findstring _nandflash,$@)" ] ; then \
++		echo "#define CFG_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in NAND FLASH" ; \
++		echo "#define CFG_USE_AT91SAM9M10EKES 1"	>>$(obj)include/config.h ; \
++	else \
++		echo "#define CFG_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
++		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
++		echo "#define CFG_USE_AT91SAM9M10EKES 1"	>>$(obj)include/config.h ; \
++	fi;
++	@$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91sam9
+ 
+ ########################################################################
+ ## ARM Integrator boards - see doc/README-integrator for more info.
+diff -uprN u-boot-1.3.4-vanilla/net/eth.c u-boot-1.3.4/net/eth.c
+--- u-boot-1.3.4-vanilla/net/eth.c	2008-08-12 09:08:38.000000000 -0500
++++ u-boot-1.3.4/net/eth.c	2010-03-25 16:45:59.000000000 -0500
+@@ -287,7 +287,7 @@ int eth_initialize(bd_t *bis)
+ 	mcdmafec_initialize(bis);
+ #endif
+ #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
+-    defined(CONFIG_AT91SAM9263)
++    defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
+ 	at91sam9_eth_initialize(bis);
+ #endif
+ 
diff --git a/multitech/recipes/u-boot/u-boot-2012.10/mtocgd3/u-boot-2012.10-mtocgd3.patch b/multitech/recipes/u-boot/u-boot-2012.10/mtocgd3/u-boot-2012.10-mtocgd3.patch
new file mode 100644
index 0000000..dbe3247
--- /dev/null
+++ b/multitech/recipes/u-boot/u-boot-2012.10/mtocgd3/u-boot-2012.10-mtocgd3.patch
@@ -0,0 +1,344 @@
+Index: git/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+===================================================================
+--- git.orig/board/atmel/at91sam9x5ek/at91sam9x5ek.c	2013-02-11 10:22:37.000000000 -0600
++++ git/board/atmel/at91sam9x5ek/at91sam9x5ek.c	2013-02-11 13:52:43.930054966 -0600
+@@ -60,8 +60,6 @@
+ 	/* Enable CS3 */
+ 	csa = readl(&matrix->ebicsa);
+ 	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+-	/* NAND flash on D16 */
+-	csa |= AT91_MATRIX_NFD0_ON_D16;
+ 
+ 	/* Configure IO drive */
+ 	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+@@ -115,8 +113,9 @@
+ 
+ #ifdef CONFIG_MACB
+ 	if (has_emac0())
++		/* MTOCGD3: use phy addr 5 for ethernet switch */
+ 		rc = macb_eth_initialize(0,
+-			(void *)ATMEL_BASE_EMAC0, 0x00);
++			(void *)ATMEL_BASE_EMAC0, 0x05);
+ 	if (has_emac1())
+ 		rc = macb_eth_initialize(1,
+ 			(void *)ATMEL_BASE_EMAC1, 0x00);
+Index: git/include/configs/at91sam9x5ek.h
+===================================================================
+--- git.orig/include/configs/at91sam9x5ek.h	2013-02-11 10:22:38.000000000 -0600
++++ git/include/configs/at91sam9x5ek.h	2013-02-11 13:56:13.890363608 -0600
+@@ -54,6 +54,7 @@
+ #define CONFIG_USART_ID		ATMEL_ID_SYS
+ 
+ /* LCD */
++/* MTOCGD3 has no LCD
+ #define CONFIG_LCD
+ #define LCD_BPP			LCD_COLOR16
+ #define LCD_OUTPUT_BPP		24
+@@ -65,6 +66,7 @@
+ #define CONFIG_ATMEL_HLCD
+ #define CONFIG_ATMEL_LCD_RGB565
+ #define CONFIG_SYS_CONSOLE_IS_IN_ENV
++*/
+ 
+ #define CONFIG_BOOTDELAY	3
+ 
+@@ -120,12 +122,14 @@
+ /* our CLE is AD22 */
+ #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+ #define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
++/* MTOCGD3: nand ready is on PC31 */
++#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC31
+ 
+ /* PMECC & PMERRLOC */
+ #define CONFIG_ATMEL_NAND_HWECC		1
+ #define CONFIG_ATMEL_NAND_HW_PMECC	1
+-#define CONFIG_PMECC_CAP		2
++/* MTOCGD3: 4-bit PMECC */
++#define CONFIG_PMECC_CAP		4
+ #define CONFIG_PMECC_SECTOR_SIZE	512
+ #define CONFIG_PMECC_INDEX_TABLE_OFFSET	0x8000
+ 
+@@ -140,9 +144,14 @@
+ 
+ /* Ethernet */
+ #define CONFIG_MACB
+-#define CONFIG_RMII
++/* MTOCGD3 is MII */
++#undef CONFIG_RMII
+ #define CONFIG_NET_RETRY_COUNT		20
+-#define CONFIG_MACB_SEARCH_PHY
++/* MTOCGD3: MAC is connected to fixed-speed PHY on ethernet switch */
++#undef CONFIG_MACB_SEARCH_PHY
++#define CONFIG_FIXED_PHY   1
++/* enable MII command */
++#define CONFIG_CMD_MII 1
+ 
+ #define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+ 
+@@ -155,9 +164,8 @@
+ #define CONFIG_ENV_OFFSET		0xc0000
+ #define CONFIG_ENV_OFFSET_REDUND	0x100000
+ #define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+-#define CONFIG_BOOTCOMMAND	"nand read " \
+-				"0x22000000 0x200000 0x300000; " \
+-				"bootm 0x22000000"
++/* MTOCGD3: read from env variables for boot */
++#define CONFIG_BOOTCOMMAND "nboot.jffs2 ${loadaddr} 0 ${kernel_addr}; bootm ${loadaddr}"
+ #else
+ #ifdef CONFIG_SYS_USE_SPIFLASH
+ /* bootstrap + u-boot + env + linux in spi flash */
+@@ -172,11 +180,8 @@
+ #endif
+ #endif
+ 
+-#define CONFIG_BOOTARGS		"mem=128M console=ttyS0,115200 " \
+-				"mtdparts=atmel_nand:" \
+-				"8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
+-				"root=/dev/mtdblock1 rw " \
+-				"rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"
++/* MTOCGD3: rootfs is jffs2 */
++#define CONFIG_BOOTARGS	"mem=128M console=ttyS0,115200 root=/dev/mtdblock8 ro rootfstype=jffs2"
+ 
+ #define CONFIG_BAUDRATE		115200
+ 
+@@ -199,4 +204,22 @@
+ #error CONFIG_USE_IRQ not supported
+ #endif
+ 
++// MTOCGD3 defaults
++#define CONFIG_ENV_OVERWRITE   1 /* Allow Overwrite of serial# & ethaddr */
++#define CONFIG_ETHADDR     00:08:00:87:00:02
++#define CONFIG_IPADDR      192.168.2.1
++#define CONFIG_NETMASK     255.255.255.0
++#define CONFIG_SERVERIP    192.168.2.2
++#define CONFIG_HOSTNAME    AT91SAM9G25
++#define CONFIG_LOADADDR    0x22000000
++
++// MTOCGD3 - enable watchdog
++#define CONFIG_AT91SAM9_WATCHDOG 1
++#define CONFIG_HW_WATCHDOG 1
++
++#define CONFIG_EXTRA_ENV_SETTINGS          \
++   "kernel_addr=0x200000\0"          \
++   ""
++
++
+ #endif
+Index: git/drivers/net/macb.c
+===================================================================
+--- git.orig/drivers/net/macb.c	2013-02-11 13:52:43.930054966 -0600
++++ git/drivers/net/macb.c	2013-02-11 13:52:43.930054966 -0600
+@@ -86,6 +86,18 @@
+ #define TXBUF_WRAP		0x40000000
+ #define TXBUF_USED		0x80000000
+ 
++#define BIT0  (1<<0)
++#define BIT1  (1<<1)
++#define BIT2  (1<<2)
++#define BIT3  (1<<3)
++#define BIT4  (1<<4)
++#define BIT5  (1<<5)
++#define BIT6  (1<<6)
++#define BIT7  (1<<7)
++#define BIT8  (1<<8)
++#define BIT9  (1<<9)
++#define BIT10 (1<<10)
++
+ struct macb_device {
+ 	void			*regs;
+ 
+@@ -105,6 +117,7 @@
+ 	const struct device	*dev;
+ 	struct eth_device	netdev;
+ 	unsigned short		phy_addr;
++	unsigned short		ext_phy_addr;
+ };
+ #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
+ 
+@@ -113,6 +126,13 @@
+ 	unsigned long netctl;
+ 	unsigned long netstat;
+ 	unsigned long frame;
++	unsigned short phya;
++
++	// use extended phy addr if set, else use fixed phy addr
++	if (macb->ext_phy_addr != 0)
++		phya = macb->ext_phy_addr;
++	else
++		phya = macb->phy_addr;
+ 
+ 	netctl = macb_readl(macb, NCR);
+ 	netctl |= MACB_BIT(MPE);
+@@ -120,7 +140,7 @@
+ 
+ 	frame = (MACB_BF(SOF, 1)
+ 		 | MACB_BF(RW, 1)
+-		 | MACB_BF(PHYA, macb->phy_addr)
++		 | MACB_BF(PHYA, phya)
+ 		 | MACB_BF(REGA, reg)
+ 		 | MACB_BF(CODE, 2)
+ 		 | MACB_BF(DATA, value));
+@@ -140,6 +160,14 @@
+ 	unsigned long netctl;
+ 	unsigned long netstat;
+ 	unsigned long frame;
++	unsigned short phya;
++
++	// use extended phy addr if set, else use fixed phy addr
++	if (macb->ext_phy_addr != 0)
++		phya = macb->ext_phy_addr;
++	else
++		phya = macb->phy_addr;
++
+ 
+ 	netctl = macb_readl(macb, NCR);
+ 	netctl |= MACB_BIT(MPE);
+@@ -147,7 +175,7 @@
+ 
+ 	frame = (MACB_BF(SOF, 1)
+ 		 | MACB_BF(RW, 2)
+-		 | MACB_BF(PHYA, macb->phy_addr)
++		 | MACB_BF(PHYA, phya)
+ 		 | MACB_BF(REGA, reg)
+ 		 | MACB_BF(CODE, 2));
+ 	macb_writel(macb, MAN, frame);
+@@ -167,15 +195,59 @@
+ 
+ #if defined(CONFIG_CMD_MII)
+ 
++// Micrel switch support -- converts SMI register address to split reg and phy address fields
++void convert_smi_reg(u8 smi_reg, u8 *reg, u8 *phy_adr)
++{
++	u8 new_phy_adr = 0;
++
++	// lower 5 bits go in reg
++	if (reg)
++		*reg = smi_reg & 0x1f;
++
++	// upper 3 bits go in phy_adr bits 4,3,0
++	if (smi_reg & BIT5)
++		new_phy_adr |= BIT0;
++	if (smi_reg & BIT6)
++		new_phy_adr |= BIT3;
++	if (smi_reg & BIT7)
++		new_phy_adr |= BIT4;
++
++	// bits 1 and 2 are always 1
++	new_phy_adr |= BIT1;
++	new_phy_adr |= BIT2;
++
++	if (phy_adr)
++		*phy_adr = new_phy_adr;
++}
++
+ int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
+ {
+ 	struct eth_device *dev = eth_get_dev_by_name(devname);
+ 	struct macb_device *macb = to_macb(dev);
++	u8 smi_reg = reg;
++	u8 phy_arg = phy_adr;
++	u8 reg_arg = reg;
++
++	if (phy_adr == 0 || phy_adr > 6)
++	    return -1;
++
++	// ---micrel switch support---
++	// use phy_adr 0x06 to designate that reg is an SMI command and we should
++	// construct phy_adr and reg values for accessing the control registers
++	if (phy_adr == 0x06) {
++		convert_smi_reg(smi_reg, &reg_arg, &phy_arg);
++		//debug("reading SMI reg %x, phy_adr %x, reg %x\n",
++		//	smi_reg, phy_arg, reg_arg);
++		debug("reading SMI reg %x\n", smi_reg);
++	}
+ 
+-	if ( macb->phy_addr != phy_adr )
+-		return -1;
++	// allow reading any phy addr value (ethernet switch)
++	macb->ext_phy_addr = phy_arg;
++
++	*value = macb_mdio_read(macb, reg_arg);
+ 
+-	*value = macb_mdio_read(macb, reg);
++	// reset to use fixed phy for later calls
++	macb->ext_phy_addr = 0;
+ 
+ 	return 0;
+ }
+@@ -184,11 +256,30 @@
+ {
+ 	struct eth_device *dev = eth_get_dev_by_name(devname);
+ 	struct macb_device *macb = to_macb(dev);
++	u8 smi_reg = reg;
++	u8 phy_arg = phy_adr;
++	u8 reg_arg = reg;
++
++	if (phy_adr == 0 || phy_adr > 6)
++	    return -1;
++
++	// ---micrel switch support---
++	// use phy_adr 0x06 to designate that reg is an SMI command and we should
++	// construct phy_adr and reg values for accessing the control registers
++	if (phy_adr == 0x06) {
++		convert_smi_reg(smi_reg, &reg_arg, &phy_arg);
++		//debug("writing value %x to SMI reg %x, phy_adr %x, reg %x\n",
++		//	value, smi_reg, phy_arg, reg_arg);
++		debug("writing value %x to SMI reg %x\n", value, smi_reg);
++	}
+ 
+-	if ( macb->phy_addr != phy_adr )
+-		return -1;
++	// allow using any phy addr value (ethernet switch)
++	macb->ext_phy_addr = phy_arg;
+ 
+-	macb_mdio_write(macb, reg, value);
++	macb_mdio_write(macb, reg_arg, value);
++
++	// reset to use fixed phy for later calls
++	macb->ext_phy_addr = 0;
+ 
+ 	return 0;
+ }
+@@ -396,6 +487,14 @@
+ 		return 0;
+ 	}
+ 
++#ifdef CONFIG_FIXED_PHY
++	ncfgr = macb_readl(macb, NCFGR);
++	// MTOCGD3: force link to 100, full duplex
++	ncfgr |= MACB_BIT(SPD);
++	ncfgr |= MACB_BIT(FD);
++	macb_writel(macb, NCFGR, ncfgr);
++	return 1;
++#else
+ 	status = macb_mdio_read(macb, MII_BMSR);
+ 	if (!(status & BMSR_LSTATUS)) {
+ 		/* Try to re-negotiate if we don't have link already. */
+@@ -428,6 +527,7 @@
+ 		macb_writel(macb, NCFGR, ncfgr);
+ 		return 1;
+ 	}
++#endif /* CONFIG_FIXED_PHY */
+ }
+ 
+ static int macb_init(struct eth_device *netdev, bd_t *bd)
+@@ -554,6 +654,7 @@
+ 
+ 	macb->regs = regs;
+ 	macb->phy_addr = phy_addr;
++	macb->ext_phy_addr = 0;
+ 
+ 	sprintf(netdev->name, "macb%d", id);
+ 	netdev->init = macb_init;
+@@ -583,6 +684,10 @@
+ #if defined(CONFIG_CMD_MII)
+ 	miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write);
+ #endif
++
++	// MTOCGD3: enable micrel switch
++	macb_miiphy_write("macb0", 6, 1, 0x41);
++
+ 	return 0;
+ }
+ 
diff --git a/multitech/recipes/u-boot/u-boot-2012.10/u-boot-2010.06-macb-autoneg-timeout.patch b/multitech/recipes/u-boot/u-boot-2012.10/u-boot-2010.06-macb-autoneg-timeout.patch
new file mode 100644
index 0000000..5294b1a
--- /dev/null
+++ b/multitech/recipes/u-boot/u-boot-2012.10/u-boot-2010.06-macb-autoneg-timeout.patch
@@ -0,0 +1,53 @@
+Index: u-boot-2010.06/drivers/net/macb.c
+===================================================================
+--- u-boot-2010.06.orig/drivers/net/macb.c	2013-01-04 16:57:21.460051123 -0600
++++ u-boot-2010.06/drivers/net/macb.c	2013-01-04 17:03:28.880052058 -0600
+@@ -57,7 +57,7 @@
+ #define CONFIG_SYS_MACB_RX_RING_SIZE		(CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
+ #define CONFIG_SYS_MACB_TX_RING_SIZE		16
+ #define CONFIG_SYS_MACB_TX_TIMEOUT		1000
+-#define CONFIG_SYS_MACB_AUTONEG_TIMEOUT	5000000
++#define CONFIG_SYS_MACB_AUTONEG_TIMEOUT	3000000
+ 
+ struct macb_dma_desc {
+ 	u32	addr;
+@@ -322,11 +322,12 @@
+ 	return 0;
+ }
+ 
+-static void macb_phy_reset(struct macb_device *macb)
++static u16 macb_phy_reset(struct macb_device *macb)
+ {
+ 	struct eth_device *netdev = &macb->netdev;
+ 	int i;
+-	u16 status, adv;
++	u16 status = 0;
++	u16 adv;
+ 
+ 	adv = ADVERTISE_CSMA | ADVERTISE_ALL;
+ 	macb_mdio_write(macb, MII_ADVERTISE, adv);
+@@ -346,6 +347,8 @@
+ 	else
+ 		printf("%s: Autonegotiation timed out (status=0x%04x)\n",
+ 		       netdev->name, status);
++
++	return status;
+ }
+ 
+ #ifdef CONFIG_MACB_SEARCH_PHY
+@@ -397,14 +400,7 @@
+ 	status = macb_mdio_read(macb, MII_BMSR);
+ 	if (!(status & BMSR_LSTATUS)) {
+ 		/* Try to re-negotiate if we don't have link already. */
+-		macb_phy_reset(macb);
+-
+-		for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) {
+-			status = macb_mdio_read(macb, MII_BMSR);
+-			if (status & BMSR_LSTATUS)
+-				break;
+-			udelay(100);
+-		}
++		status = macb_phy_reset(macb);
+ 	}
+ 
+ 	if (!(status & BMSR_LSTATUS)) {
diff --git a/multitech/recipes/u-boot/u-boot-2012.10/u-boot-2012.10-sam9x5-eth-mii-fix.patch b/multitech/recipes/u-boot/u-boot-2012.10/u-boot-2012.10-sam9x5-eth-mii-fix.patch
new file mode 100644
index 0000000..0f41ac4
--- /dev/null
+++ b/multitech/recipes/u-boot/u-boot-2012.10/u-boot-2012.10-sam9x5-eth-mii-fix.patch
@@ -0,0 +1,27 @@
+Index: git/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
+===================================================================
+--- git.orig/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c	2013-02-11 10:22:35.000000000 -0600
++++ git/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c	2013-02-11 10:32:59.652182120 -0600
+@@ -206,14 +206,14 @@
+ #ifndef CONFIG_RMII
+ 	/* Only emac0 support MII */
+ 	if (has_emac0()) {
+-		at91_set_b_periph(AT91_PIO_PORTB, 16, 0);	/* ECRS */
+-		at91_set_b_periph(AT91_PIO_PORTB, 17, 0);	/* ECOL */
+-		at91_set_b_periph(AT91_PIO_PORTB, 13, 0);	/* ERX2 */
+-		at91_set_b_periph(AT91_PIO_PORTB, 14, 0);	/* ERX3 */
+-		at91_set_b_periph(AT91_PIO_PORTB, 15, 0);	/* ERXCK */
+-		at91_set_b_periph(AT91_PIO_PORTB, 11, 0);	/* ETX2 */
+-		at91_set_b_periph(AT91_PIO_PORTB, 12, 0);	/* ETX3 */
+-		at91_set_b_periph(AT91_PIO_PORTB, 8, 0);	/* ETXER */
++		at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* ECRS */
++		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* ECOL */
++		at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ERX2 */
++		at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* ERX3 */
++		at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* ERXCK */
++		at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* ETX2 */
++		at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX3 */
++		at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ETXER */
+ 	}
+ #endif
+ }
diff --git a/multitech/recipes/u-boot/u-boot_1.3.4.bb b/multitech/recipes/u-boot/u-boot_1.3.4.bb
index 3ffcdb1..4179176 100644
--- a/multitech/recipes/u-boot/u-boot_1.3.4.bb
+++ b/multitech/recipes/u-boot/u-boot_1.3.4.bb
@@ -1,6 +1,6 @@
 require recipes/u-boot/u-boot.inc
 
-PR = "r9"
+PR = "r10"
 ALLOW_EMPTY = 1
 
 SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2 \
@@ -9,12 +9,7 @@ SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2 \
 SRC_URI[md5sum] = "ca12b805b4f2bdcf15733be3fe22e896"
 SRC_URI[sha256sum] = "096aa286d923b7cc356bbe0dda0a29a701369deeb27ada1a2f053155aa403c31"
 
-SRC_URI_append_mtcdp = "\
-            file://u-boot-${PV}-mts.patch \
-            file://fw_env.config \
-"
-
-SRC_URI_append_mt100eocg = "\
+SRC_URI_append = "\
             file://u-boot-${PV}-mts.patch \
             file://fw_env.config \
 "
@@ -28,8 +23,7 @@ FILES_${PN} = " \
     ${base_sbindir}/fw_printenv \
 "
 
-FILES_${PN}_append_mtcdp = "${sysconfdir}/fw_env.config"
-FILES_${PN}_append_mt100eocg = "${sysconfdir}/fw_env.config"
+FILES_${PN}_append = "${sysconfdir}/fw_env.config"
 
 do_configure_prepend() {
     mv -f tools/setlocalversion tools/setlocalversion.old
diff --git a/multitech/recipes/u-boot/u-boot_2012.10.bb b/multitech/recipes/u-boot/u-boot_2012.10.bb
new file mode 100644
index 0000000..cd9f151
--- /dev/null
+++ b/multitech/recipes/u-boot/u-boot_2012.10.bb
@@ -0,0 +1,34 @@
+PR = "r0"
+require recipes/u-boot/u-boot.inc
+
+DEFAULT_PREFERENCE = "-1"
+
+# U-Boot 2012.10 for AT91
+SRCREV="linux4sam_4.0"
+
+SRC_URI = "git://github.com/linux4sam/u-boot-at91.git;protocol=http;tag=${SRCREV} \
+           file://u-boot-2012.10-sam9x5-eth-mii-fix.patch \
+           "
+
+# add patch to speed up boot if ethernet autonegotiation fails
+SRC_URI += "file://u-boot-2010.06-macb-autoneg-timeout.patch"
+
+SRC_URI_append_mtocgd3 = " file://u-boot-2012.10-mtocgd3.patch"
+
+TARGET_LDFLAGS = ""
+
+S = "${WORKDIR}/git"
+
+inherit base
+
+do_configure_prepend() {
+    mv -f tools/setlocalversion tools/setlocalversion.old
+    echo -e "#!/bin/sh\necho '-${MACHINE}-${PR}'" > tools/setlocalversion
+    chmod a+rx tools/setlocalversion
+}
+
+do_compile () {
+       oe_runmake ${UBOOT_MACHINE}
+       oe_runmake all
+}
+
diff --git a/multitech/recipes/udev/udev-165/mt100eocg-pcie-dk/corecdp.rules b/multitech/recipes/udev/udev-165/mt100eocg-pcie-dk/corecdp.rules
new file mode 100644
index 0000000..633947d
--- /dev/null
+++ b/multitech/recipes/udev/udev-165/mt100eocg-pcie-dk/corecdp.rules
@@ -0,0 +1,54 @@
+ACTION=="remove", GOTO="corecdp_end"
+SUBSYSTEM!="tty", GOTO="corecdp_end"
+KERNEL!="ttyUSB[0-9]*|ttyACM[0-9]*|ttyS*", GOTO="corecdp_end"
+
+# use serial port by default, allow USB radios to overwrite link
+KERNEL=="ttyS1", SYMLINK+="modem0", OPTIONS+="link_priority=-1"
+KERNEL=="ttyS1", SYMLINK+="modem_at0", OPTIONS+="link_priority=-1"
+
+SUBSYSTEMS=="usb", ENV{ID_IFACE}="$attr{bInterfaceNumber}"
+ENV{ID_IFACE}=="", GOTO="corecdp_end"
+
+# All modem ports
+# H5
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="00", SYMLINK+="modem0"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="02", SYMLINK+="modem1"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="04", SYMLINK+="modem2"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="06", SYMLINK+="modem3"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="08", SYMLINK+="modem4"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="0a", SYMLINK+="modem5"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="0c", SYMLINK+="modem6"
+# EV3
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="00", SYMLINK+="modem0"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="01", SYMLINK+="modem1"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="02", SYMLINK+="modem2"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="03", SYMLINK+="modem3"
+# H4
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="00", SYMLINK+="modem0"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="01", SYMLINK+="modem1"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="02", SYMLINK+="modem2"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="03", SYMLINK+="modem3"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="04", SYMLINK+="modem4"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="05", SYMLINK+="modem5"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="06", SYMLINK+="modem6"
+# EV2
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="0028", SYMLINK+="modem$env{ID_PORT}"
+
+# AT Command ports
+# H5: ttyACM0, ttyACM3
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="00", SYMLINK+="modem_at0"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="06", SYMLINK+="modem_at1"
+# EV3: ttyUSB2, ttyUSB3
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="02", SYMLINK+="modem_at0"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="03", SYMLINK+="modem_at1"
+# H4: ttyUSB3, ttyUSB4, ttyUSB5
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="03", SYMLINK+="modem_at0"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="04", SYMLINK+="modem_at1"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="05", SYMLINK+="modem_at2"
+# EV2: ttyUSB0
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="0028", ENV{ID_PORT}=="0", SYMLINK+="modem_at0"
+
+# mtpcie-dk: bluetooth on exar chip (ACM1, iface 2)
+ATTRS{idVendor}=="04e2", ATTRS{idProduct}=="1414", ENV{ID_IFACE}=="02", SYMLINK+="bt"
+
+LABEL="corecdp_end"
diff --git a/multitech/recipes/udev/udev-165/mtocgd3/corecdp.rules b/multitech/recipes/udev/udev-165/mtocgd3/corecdp.rules
new file mode 100644
index 0000000..be32fa0
--- /dev/null
+++ b/multitech/recipes/udev/udev-165/mtocgd3/corecdp.rules
@@ -0,0 +1,57 @@
+ACTION=="remove", GOTO="corecdp_end"
+SUBSYSTEM!="tty", GOTO="corecdp_end"
+KERNEL!="ttyUSB[0-9]*|ttyACM[0-9]*|ttyS*", GOTO="corecdp_end"
+
+# use serial port by default, allow USB radios to overwrite link
+KERNEL=="ttyS1", SYMLINK+="modem0", OPTIONS+="link_priority=-1"
+KERNEL=="ttyS1", SYMLINK+="modem_at0", OPTIONS+="link_priority=-1"
+
+SUBSYSTEMS=="usb", ENV{ID_IFACE}="$attr{bInterfaceNumber}"
+ENV{ID_IFACE}=="", GOTO="corecdp_end"
+
+# All modem ports
+# H5
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="00", SYMLINK+="modem0"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="02", SYMLINK+="modem1"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="04", SYMLINK+="modem2"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="06", SYMLINK+="modem3"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="08", SYMLINK+="modem4"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="0a", SYMLINK+="modem5"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="0c", SYMLINK+="modem6"
+# EV3
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="00", SYMLINK+="modem0"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="01", SYMLINK+="modem1"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="02", SYMLINK+="modem2"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="03", SYMLINK+="modem3"
+# H4
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="00", SYMLINK+="modem0"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="01", SYMLINK+="modem1"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="02", SYMLINK+="modem2"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="03", SYMLINK+="modem3"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="04", SYMLINK+="modem4"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="05", SYMLINK+="modem5"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="06", SYMLINK+="modem6"
+# EV2
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="0028", SYMLINK+="modem$env{ID_PORT}"
+
+# AT Command ports
+# H5: ttyACM0, ttyACM3
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="00", SYMLINK+="modem_at0"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="0021", ENV{ID_IFACE}=="06", SYMLINK+="modem_at1"
+# EV3: ttyUSB2, ttyUSB3
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="02", SYMLINK+="modem_at0"
+ATTRS{idVendor}=="1bc7", ATTRS{idProduct}=="1010", ENV{ID_IFACE}=="03", SYMLINK+="modem_at1"
+# H4: ttyUSB3, ttyUSB4, ttyUSB5
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="03", SYMLINK+="modem_at0"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="04", SYMLINK+="modem_at1"
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="683c", ENV{ID_IFACE}=="05", SYMLINK+="modem_at2"
+# EV2: ttyUSB0
+ATTRS{idVendor}=="1199", ATTRS{idProduct}=="0028", ENV{ID_PORT}=="0", SYMLINK+="modem_at0"
+
+# mtocgd3: bluetooth on exar chip (ACM1, iface 2)
+ATTRS{idVendor}=="04e2", ATTRS{idProduct}=="1414", ENV{ID_IFACE}=="02", SYMLINK+="bt"
+
+# mtocgd3: external serial on exar chip (ACM2, iface 4)
+ATTRS{idVendor}=="04e2", ATTRS{idProduct}=="1414", ENV{ID_IFACE}=="04", SYMLINK+="ext_serial"
+
+LABEL="corecdp_end"
diff --git a/multitech/recipes/udev/udev-165/udev-164-remove-v4l1.patch b/multitech/recipes/udev/udev-165/udev-164-remove-v4l1.patch
new file mode 100644
index 0000000..288da53
--- /dev/null
+++ b/multitech/recipes/udev/udev-165/udev-164-remove-v4l1.patch
@@ -0,0 +1,47 @@
+Author: Kay Sievers <kay.sievers@vrfy.org>
+Date:   Tue Feb 15 17:24:32 2011 +0100
+
+    v4l_id: kill the v4l1 ioctl
+    
+    Recent kernels do not have v4l1 anymore.
+
+diff --git a/extras/v4l_id/v4l_id.c b/extras/v4l_id/v4l_id.c
+index d530a6d..21cb328 100644
+--- a/extras/v4l_id/v4l_id.c
++++ b/extras/v4l_id/v4l_id.c
+@@ -28,7 +28,6 @@
+ #include <sys/types.h>
+ #include <sys/time.h>
+ #include <sys/ioctl.h>
+-#include <linux/videodev.h>
+ #include <linux/videodev2.h>
+ 
+ int main (int argc, char *argv[])
+@@ -39,7 +38,6 @@ int main (int argc, char *argv[])
+ 	};
+ 	int fd;
+ 	char *device;
+-	struct video_capability v1cap;
+ 	struct v4l2_capability v2cap;
+ 
+ 	while (1) {
+@@ -82,19 +80,6 @@ int main (int argc, char *argv[])
+ 		if ((v2cap.capabilities & V4L2_CAP_RADIO) > 0)
+ 			printf("radio:");
+ 		printf("\n");
+-	} else if (ioctl (fd, VIDIOCGCAP, &v1cap) == 0) {
+-		printf("ID_V4L_VERSION=1\n");
+-		printf("ID_V4L_PRODUCT=%s\n", v1cap.name);
+-		printf("ID_V4L_CAPABILITIES=:");
+-		if ((v1cap.type & VID_TYPE_CAPTURE) > 0)
+-			printf("capture:");
+-		if ((v1cap.type & VID_TYPE_OVERLAY) > 0)
+-			printf("video_overlay:");
+-		if (v1cap.audios > 0)
+-			printf("audio:");
+-		if ((v1cap.type & VID_TYPE_TUNER) > 0)
+-			printf("tuner:");
+-		printf("\n");
+ 	}
+ 
+ 	close (fd);
diff --git a/multitech/recipes/udev/udev_165.bbappend b/multitech/recipes/udev/udev_165.bbappend
index e87ff82..e6d011c 100644
--- a/multitech/recipes/udev/udev_165.bbappend
+++ b/multitech/recipes/udev/udev_165.bbappend
@@ -1,11 +1,14 @@
 FILESEXTRA := "${THISDIR}"
 FILESPATHBASE =. "${FILESEXTRA}:"
 
-PR .= ".corecdp2"
+PR .= ".corecdp5"
 
 # add custom rules for persistent modem device names
 SRC_URI += "file://corecdp.rules"
 
+# patch for building against newer linux headers
+SRC_URI += "file://udev-164-remove-v4l1.patch"
+
 do_install_append() {
 	install -d ${D}${sysconfdir}/udev/rules.d
 	install -m 644 ${WORKDIR}/corecdp.rules ${D}${sysconfdir}/udev/rules.d/
diff --git a/multitech/recipes/uvccapture/files/uvccapture_use_videodev2.patch b/multitech/recipes/uvccapture/files/uvccapture_use_videodev2.patch
new file mode 100644
index 0000000..b6e4617
--- /dev/null
+++ b/multitech/recipes/uvccapture/files/uvccapture_use_videodev2.patch
@@ -0,0 +1,24 @@
+--- a/uvccapture.c	2008-08-03 22:02:38 +0000
++++ b/uvccapture.c	2011-06-09 16:31:30 +0000
+@@ -31,7 +31,7 @@
+ #include <unistd.h>
+ #include <jpeglib.h>
+ #include <time.h>
+-#include <linux/videodev.h>
++#include <linux/videodev2.h>
+ 
+ #include "v4l2uvc.h"
+ 
+
+--- a/v4l2uvc.c	2008-03-28 19:13:23 +0000
++++ b/v4l2uvc.c	2011-06-09 16:31:30 +0000
+@@ -28,7 +28,7 @@
+ #include <errno.h>
+ #include <unistd.h>
+ #include <fcntl.h>
+-#include <linux/videodev.h>
++#include <linux/videodev2.h>
+ #include <sys/mman.h>
+ #include <sys/ioctl.h>
+ #include "v4l2uvc.h"
+
diff --git a/multitech/recipes/uvccapture/uvccapture_0.5.bb b/multitech/recipes/uvccapture/uvccapture_0.5.bb
index 184721f..e6a9679 100644
--- a/multitech/recipes/uvccapture/uvccapture_0.5.bb
+++ b/multitech/recipes/uvccapture/uvccapture_0.5.bb
@@ -1,10 +1,11 @@
 DESCRIPTION = "Command-line tool to capture webcam images"
 DEPENDS = "jpeg virtual/kernel"
-PR = "r0"
+PR = "r1"
 
 inherit autotools
 
 SRC_URI = "http://staticwave.ca/source/uvccapture/${PN}-${PV}.tar.bz2 \
+		   file://uvccapture_use_videodev2.patch \
 		   file://makefile.patch \
 		   "
 
diff --git a/multitech/recipes/vizzini/files/vizzini.init b/multitech/recipes/vizzini/files/vizzini.init
new file mode 100644
index 0000000..b49473f
--- /dev/null
+++ b/multitech/recipes/vizzini/files/vizzini.init
@@ -0,0 +1,22 @@
+#!/bin/sh
+
+exit
+
+case $1 in
+  start)
+    echo "Loading vizzini module"
+    modprobe vizzini
+    ;;
+
+  stop)
+    echo "Unloading vizzini module"
+    modprobe -r vizzini
+    ;;
+
+  *)
+    echo "Usage: $0 {start|stop}"
+    exit 2
+    ;;
+esac
+
+
diff --git a/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-enable-cts.patch b/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-enable-cts.patch
new file mode 100644
index 0000000..d4b1211
--- /dev/null
+++ b/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-enable-cts.patch
@@ -0,0 +1,30 @@
+--- a/vizzini.c	2013-03-28 16:37:49.863760786 -0500
++++ b/vizzini.c	2013-03-28 16:38:57.353205784 -0500
+@@ -95,6 +95,9 @@
+ #define READ_URB_RUNNING    0
+ #define READ_URB_STOPPED    1
+ 
++#define UART_PIN_RTS 0x020
++#define UART_GPIO_DIR 0x01b
++
+ static int debug;
+ 
+ 
+@@ -559,6 +562,17 @@
+ 
+         vizzini_set_reg(port, block, UART_FLOW, flow);
+         vizzini_set_reg(port, block, UART_GPIO_MODE, gpio_mode);
++        /* if flow control hasn't been turned on, enable RTS for modem-like functionality */
++        if (flow == UART_FLOW_MODE_NONE) {
++                char value;
++                vizzini_get_reg(port, block, UART_GPIO_DIR, &value);
++                value |= UART_PIN_RTS;
++                vizzini_set_reg(port, block, UART_GPIO_DIR, value);
++                vizzini_get_reg(port, block, UART_GPIO_CLR, &value);
++                value |= UART_PIN_RTS;
++                vizzini_set_reg(port, block, UART_GPIO_CLR, value);
++        }
++
+ 
+         if (portdata->trans9) {
+                 /* Turn on wide mode if we're 9-bit transparent. */
diff --git a/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-flow-control.patch b/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-flow-control.patch
new file mode 100644
index 0000000..77adf53
--- /dev/null
+++ b/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-flow-control.patch
@@ -0,0 +1,157 @@
+--- a/vizzini.c	2013-03-26 11:34:39.362546946 -0500
++++ b/vizzini.c	2013-03-27 10:43:03.123460275 -0500
+@@ -92,6 +92,9 @@
+ #define N_OUT_URB   4
+ #define IN_BUFLEN   4096
+ 
++#define READ_URB_RUNNING    0
++#define READ_URB_STOPPED    1
++
+ static int debug;
+ 
+ 
+@@ -169,6 +172,7 @@
+ 
+         struct urb   *in_urbs[N_IN_URB];
+         char         *in_buffer[N_IN_URB];
++        int           in_urb_flags[N_IN_URB];
+ 
+         int           ctrlin;
+         int           ctrlout;
+@@ -995,6 +999,8 @@
+         char                            *transfer_buffer = urb->transfer_buffer;
+         int                              length, room, have_extra_byte;
+         int                              err;
++        unsigned long                    flags;
++        int j;
+ 
+         if (debug) dev_dbg(&port->dev, "%s: %p\n", __func__, urb);
+ 
+@@ -1085,9 +1091,26 @@
+                 portdata->extra_byte = transfer_buffer[urb->actual_length - 1];
+         }
+ 
+-        err = usb_submit_urb(urb, GFP_ATOMIC);
+-        if (err)
+-                dev_err(&port->dev, "resubmit read urb failed. (%d)\n", err);
++        /* throttle device if requested */
++        spin_lock_irqsave(&port->lock, flags);
++        port->throttled = port->throttle_req;
++        if (! port->throttled) {
++                spin_unlock_irqrestore(&port->lock, flags);
++                err = usb_submit_urb(urb, GFP_ATOMIC);
++                if (err)
++                        dev_err(&port->dev, "resubmit read urb failed. (%d)\n", err);
++        } else {
++                spin_unlock_irqrestore(&port->lock, flags);
++                for (j = 0; j < N_IN_URB; j++) {
++                        if (portdata->in_urbs[j] == urb) {
++                                if (debug) dev_dbg(&port->dev, "throttling urb %d\n", j);
++                                spin_lock_irqsave(&port->lock, flags);
++                                portdata->in_urb_flags[j] = READ_URB_STOPPED;
++                                spin_unlock_irqrestore(&port->lock, flags);
++                                break;
++                        }
++                }
++        }
+ }
+ 
+ 
+@@ -1172,6 +1195,7 @@
+         int                              i;
+         struct urb                      *urb;
+         int                              result;
++        unsigned long                    flags;
+ 
+         portdata = usb_get_serial_port_data(port);
+ 
+@@ -1179,10 +1203,19 @@
+ 
+         acm_set_control(port, portdata->ctrlout = ACM_CTRL_DTR | ACM_CTRL_RTS);
+ 
++        /* unthrottle device in case TTY was closed while throttled */
++        spin_lock_irqsave(&port->lock, flags);
++        port->throttled = 0;
++        port->throttle_req = 0;
++        spin_unlock_irqrestore(&port->lock, flags);
++
+         /* Reset low level data toggle and start reading from endpoints */
+         for (i = 0; i < N_IN_URB; i++) {
+                 if (debug) dev_dbg(&port->dev, "%s urb %d\n", __func__, i);
+ 
++                spin_lock_irqsave(&port->lock, flags);
++                portdata->in_urb_flags[i] = READ_URB_RUNNING;
++                spin_unlock_irqrestore(&port->lock, flags);
+                 urb = portdata->in_urbs[i];
+                 if (!urb)
+                         continue;
+@@ -1207,8 +1240,6 @@
+                 }
+         }
+ 
+-        tty->low_latency = 1;
+-
+         /* start up the interrupt endpoint if we have one */
+         if (port->interrupt_in_urb) {
+                 result = usb_submit_urb(port->interrupt_in_urb, GFP_KERNEL);
+@@ -1592,6 +1623,51 @@
+         usb_serial_disconnect(interface);
+ }
+ 
++static void vizzini_throttle(struct tty_struct *tty)
++{ 
++        unsigned long flags;
++        struct usb_serial_port *port = tty->driver_data;
++
++        if (debug) dev_dbg(&port->dev, "TTY buffer approaching limit, stopping USB reads\n");
++
++        spin_lock_irqsave(&port->lock, flags);
++        port->throttle_req = 1;
++        spin_unlock_irqrestore(&port->lock, flags);
++}
++
++static void vizzini_unthrottle(struct tty_struct *tty)
++{ 
++        unsigned long flags;
++        unsigned int was_throttled;
++        struct usb_serial_port *port = tty->driver_data;
++        struct vizzini_port_private *portdata = usb_get_serial_port_data(port);
++        int err;
++        int i;
++
++        if (debug) dev_dbg(&port->dev, "Resuming USB reads\n");
++
++        spin_lock_irqsave(&port->lock, flags);
++        was_throttled = port->throttled;
++        port->throttled = 0;
++        port->throttle_req = 0;
++        spin_unlock_irqrestore(&port->lock, flags);
++
++        if (was_throttled) {
++                for (i = 0; i < N_IN_URB; i++) {
++                        spin_lock_irqsave(&port->lock, flags);
++                        if (portdata->in_urb_flags[i] == READ_URB_STOPPED) {
++                                if (debug) dev_dbg(&port->dev, "unthrottling urb %d\n", i);
++                                portdata->in_urb_flags[i] = READ_URB_RUNNING;
++                                spin_unlock_irqrestore(&port->lock, flags);
++                                err = usb_submit_urb(portdata->in_urbs[i], GFP_ATOMIC);
++                                if (err)
++                                        dev_err(&port->dev, "resubmit read urb failed. (%d)\n", err);
++                        } else {
++                                spin_unlock_irqrestore(&port->lock, flags);
++                        }
++                }
++        }
++}
+ 
+ 
+ static struct usb_serial_driver vizzini_device = {
+@@ -1606,6 +1682,8 @@
+         .probe              = vizzini_probe,
+         .open               = vizzini_open,
+         .close              = vizzini_close,
++        .throttle           = vizzini_throttle,
++        .unthrottle         = vizzini_unthrottle,
+         .write              = vizzini_write,
+         .write_room         = vizzini_write_room,
+         .ioctl              = vizzini_ioctl,
diff --git a/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-rs485.patch b/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-rs485.patch
new file mode 100644
index 0000000..e299b81
--- /dev/null
+++ b/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-rs485.patch
@@ -0,0 +1,97 @@
+--- a/vizzini.c	2013-01-22 15:37:32.345592809 -0600
++++ b/vizzini.c	2013-01-29 14:27:04.550051817 -0600
+@@ -186,6 +186,7 @@
+ #ifdef VIZZINI_IWA
+         int           iwa;
+ #endif
++        struct serial_rs485 rs485;
+ };
+ 
+ 
+@@ -428,7 +429,41 @@
+ 	return -EINVAL;
+ }
+ 
++static int vizzini_set_rs485(struct usb_serial_port *port, struct serial_rs485 *rs485conf)
++{
++	struct vizzini_port_private *portdata = usb_get_serial_port_data(port);
++	int 		block 	= portdata->block;
++	int result = 0;
++	unsigned int gpio_mode, flow = 0;
++
++	portdata->rs485 = *rs485conf;
++
++	if (portdata->rs485.flags & SER_RS485_ENABLED) {
++		dev_info(&port->dev, "Enabling RS485");
++
++		/* enable auto tranceiver enable on transmit, TX active high */
++		gpio_mode = UART_GPIO_MODE_SEL_XCVR_EN_ACT | UART_GPIO_MODE_XCVR_EN_POL;
++
++		result = vizzini_set_reg(port, block, UART_GPIO_MODE, gpio_mode);
+ 
++		if (result < 0)
++			dev_err(&port->dev, "Error setting auto trans enable");
++
++		/* half duplex rs485 */
++		flow = UART_FLOW_HALF_DUPLEX;
++		result = vizzini_set_reg(port, block, UART_FLOW, flow);
++
++		if (result < 0)
++			dev_err(&port->dev, "Error setting half duplex");
++	}
++	else {
++		dev_info(&port->dev, "Disabling RS485 - flow control off");
++        	vizzini_set_reg(port, block, UART_GPIO_MODE, UART_GPIO_MODE_SEL_GPIO);
++        	vizzini_set_reg(port, block, UART_FLOW, UART_FLOW_MODE_NONE);
++	}
++	
++	return 0;
++}
+ 
+ static void vizzini_set_termios(struct tty_struct *tty_param,
+                                 struct usb_serial_port *port,
+@@ -604,6 +639,7 @@
+         char                    *data;
+         int                      result;
+         struct serial_struct     ss;
++        struct serial_rs485      rs485conf;
+ 
+         if (debug) dev_dbg(&port->dev, "%s %08x\n", __func__, cmd);
+ 
+@@ -636,6 +672,36 @@
+ /*      mutex_unlock(&config_mutex); */
+                 break;
+ 
++        case TIOCGRS485:
++                if (!arg) {
++                        dev_err(&port->dev, "%s - TIOCGRS485 arg invalid\n", __func__);
++                        return -EFAULT;
++		}
++                if (copy_to_user((struct serial_rs485 *) arg,
++                        &(portdata->rs485),
++                        sizeof(struct serial_rs485))) {
++                        dev_err(&port->dev, "%s - TIOCGRS485 copy_to_user fail\n", __func__);
++                        return -EFAULT;
++                }
++                break;
++
++        case TIOCSRS485:
++        	dev_dbg(&port->dev, "%s TIOCSRS485\n", __func__);
++                if (!arg) {
++                        return -EFAULT;
++                        dev_err(&port->dev, "%s - TIOCSRS485 arg invalid\n", __func__);
++		}
++                if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
++                        sizeof(rs485conf))) {
++                        dev_err(&port->dev, "%s - TIOCSRS485 copy_from_user fail\n", __func__);
++                        return -EFAULT;
++                }
++
++                vizzini_disable(port);
++                vizzini_set_rs485(port, &rs485conf);
++                vizzini_enable(port);
++                break;
++
+         case VZIOC_GET_REG:
+                 if (get_user(block, (int __user *)arg))
+                         return -EFAULT;
diff --git a/multitech/recipes/vizzini/vizzini-0.76/xr21v141x-lnx-3.0-pak.tar.gz b/multitech/recipes/vizzini/vizzini-0.76/xr21v141x-lnx-3.0-pak.tar.gz
new file mode 100644
index 0000000..3d10bac
--- /dev/null
+++ b/multitech/recipes/vizzini/vizzini-0.76/xr21v141x-lnx-3.0-pak.tar.gz
diff --git a/multitech/recipes/vizzini/vizzini.inc b/multitech/recipes/vizzini/vizzini.inc
new file mode 100644
index 0000000..6ceaeb9
--- /dev/null
+++ b/multitech/recipes/vizzini/vizzini.inc
@@ -0,0 +1,52 @@
+DESCRIPTION = "USB Driver for Exar USB UARTs"
+HOMEPAGE = "http://www.exar.com/connectivity/uart-and-bridging-solutions/usb-uarts/xr21v1414"
+SECTION = "base"
+PRIORITY = "optional"
+LICENSE = "GPL"
+DEPENDS = "virtual/kernel"
+RDEPENDS = "kernel (${KERNEL_VERSION})"
+INC_PR = "r1"
+
+SRC_URI = " \
+    file://vizzini.init \
+"
+
+inherit module-base
+inherit update-rc.d
+
+EXTRA_OEMAKE = " -C ${STAGING_KERNEL_DIR} \
+                M=${S} \
+                modules \
+                "
+
+do_configure () {
+   echo "Nothing to configure for vizzini"
+}
+
+do_compile () {
+    unset CFLAGS CPPFLAGS CXXFLAGS LDFLAGS
+    oe_runmake
+}
+
+PACKAGES = "${PN}"
+
+FILES_${PN} = "${base_libdir}/modules/${KERNEL_VERSION}/extra/vizzini.ko"
+FILES_${PN} += "${sysconfdir}/init.d/vizzini"
+
+INITSCRIPT_NAME = "vizzini"
+INITSCRIPT_PARAMS = "start 90 S ."
+
+PARALLEL_MAKE = ""
+
+fakeroot do_install () {
+    install -m 0755 -d ${D}${base_libdir}/modules/${KERNEL_VERSION}/extra
+    # use cp instead of install so the driver doesn't get stripped
+    cp ${S}/vizzini.ko ${D}${base_libdir}/modules/${KERNEL_VERSION}/extra
+    cp ${S}/vizzini.h ${STAGING_KERNEL_DIR}/include/linux/
+    cp ${S}/vizzini.h ${STAGING_INCDIR}/linux/
+    cp ${S}/vzioctl.h ${STAGING_KERNEL_DIR}/include/linux/
+    cp ${S}/vzioctl.h ${STAGING_INCDIR}/linux/
+
+    install -d ${D}${sysconfdir}/init.d
+    install -m 0755 ${WORKDIR}/vizzini.init ${D}${sysconfdir}/init.d/vizzini
+}
diff --git a/multitech/recipes/vizzini/vizzini_0.76.bb b/multitech/recipes/vizzini/vizzini_0.76.bb
new file mode 100644
index 0000000..52f168e
--- /dev/null
+++ b/multitech/recipes/vizzini/vizzini_0.76.bb
@@ -0,0 +1,12 @@
+require vizzini.inc
+
+LOCAL_PR = "${INC_PR}.2"
+MACHINE_KERNEL_PR_append = "${LOCAL_PR}"
+
+SRC_URI += "file://xr21v141x-lnx-3.0-pak.tar.gz \
+			file://vizzini-0.76-rs485.patch \
+			file://vizzini-0.76-flow-control.patch \
+			file://vizzini-0.76-enable-cts.patch \
+			"
+S = "${WORKDIR}/xr21v141x-lnx-3.0-pak"
+
diff --git a/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/115K/WL127xL_BT_Service_Pack_2.4.bts b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/115K/WL127xL_BT_Service_Pack_2.4.bts
new file mode 100644
index 0000000..15a7933
--- /dev/null
+++ b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/115K/WL127xL_BT_Service_Pack_2.4.bts
diff --git a/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/3M/WL127xL_BT_Service_Pack_2.4.bts b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/3M/WL127xL_BT_Service_Pack_2.4.bts
new file mode 100644
index 0000000..4282f32
--- /dev/null
+++ b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/3M/WL127xL_BT_Service_Pack_2.4.bts
diff --git a/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/3M/WL127xL_BT_Service_Pack_2.4.xml b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/3M/WL127xL_BT_Service_Pack_2.4.xml
new file mode 100644
index 0000000..7656fbe
--- /dev/null
+++ b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/3M/WL127xL_BT_Service_Pack_2.4.xml
@@ -0,0 +1,25708 @@
+<?xml version="1.0" encoding="ISO8859-1"?>

+<HCILib xmlns="url:http://sdw.itg.ti.com/hcilibrary">   

+    <Version>

+        <Platform>ORCA</Platform>

+        <SoftwareMajor>6</SoftwareMajor>

+        <SoftwareMinor>15</SoftwareMinor>

+        

+        <MinTesterVerMajor>2</MinTesterVerMajor>

+        <MinTesterVerMinor>2</MinTesterVerMinor>

+        <MinTesterVerSub>5</MinTesterVerSub>

+    </Version>

+    

+    <!-- Types of command                 -->

+    <!-- ================                 -->

+    <!--                                  -->

+    <!-- "gb" = Group Begin               -->

+    <!-- "sc" = Spec Command              -->

+    <!-- "se" = Spec Event                -->

+    <!-- "vc" = Vendor Specific Command   -->

+    <!-- "ve" = Vendor Specific Event     -->

+    <!-- "llc"= HCILL Command             -->

+    <!-- "lle"= HCILL Event               -->

+    <!-- "dc" = DOT Command               -->

+    <!-- "de" = DOT Event                 --> 

+    <!-- "nc" = Negotiate Command         -->

+    <!-- "ne" = Negotiate Event           -->

+    <!-- "ac" = Alive Command             -->

+    <!-- "ae" = Alive Event               -->

+    <!-- "cc" = Custom Command            -->

+    <!--                                  -->

+      

+    <!-- Properties of command -->

+    <!-- ===================== -->

+    <!--                       -->

+    <!-- "h" = Hidden command  -->

+    

+    

+    <!-- Types of parameter                                                               -->

+    <!-- ==================                                                               -->

+    <!--                                                                                  -->

+    <!-- "u" = Unsigned Number (replaces "1".."4")  E.g. 0x002F01                         -->

+    <!-- "d" = Signed Number (two's complmenet)     E.g. 0x01                             -->

+    <!-- "1" = 1 Byte Number,                       E.g. 0x01                             -->

+    <!-- "2" = 2 Byte Number,                       E.g. 0x0123                           -->

+    <!-- "3" = 3 Byte Number,                       E.g. 0x012345                         -->

+    <!-- "4" = 4 Byte Number,                       E.g. 0x01234567                       -->

+    <!-- "x" = Hex bytes array,                     E.g. "02:C1:32" means (0x02 0xC1 0x32)-->

+    <!-- "s" = String with escape codes (see below) E.g. "Hello"                          -->

+    <!-- "b" = BD Address                           E.g. "01:02:03:04:05;06"              -->

+    <!-- "h" = Connection Handle,                   E.g. 0x0001                           -->

+    <!-- "t" = Event Timeout (ms),                  E.g. 5000                             -->

+    <!-- "m" = Module Number for vendor specific opcode 0xFC00                            -->

+    <!-- "o" = Opcode for vendor specific                                                 -->

+    <!-- "R" = Related events and commands                                                -->

+    <!--                                                                                  -->

+    

+    <!-- Properties of Parameter  -->

+    <!-- =======================  -->

+    <!--                          -->

+    <!-- "h" = Hidden parameter   -->

+    <!-- "r" = Reversed parameter -->

+    <!-- "s" = Reverse the whole size of the parameter -->

+    <!--       valid only if "r" has been specified    -->

+    

+    

+    <!-- Escape Code for Strings                                       -->

+    <!-- =======================                                       -->

+    <!--                                                               -->

+    <!-- To specify a value in hex type "\xFF"                         -->

+    <!-- To specify a value in decimal type "\999"                     -->

+    <!--                                                               -->

+    <!-- E.g. "Hello\xFF" will specify ('H' 'e' 'l' 'l' 'o' 0xFF)      -->

+    <!--                                                               -->

+    

+    <!-- ******************************************************* -->

+    <!-- ******************************************************* -->

+    <!--                                                       	 -->

+    <!-- Packets Definitions                                   	 -->

+    <!--                                                       	 -->

+    <!-- ******************************************************* -->

+    <!-- ******************************************************* -->

+    <Type name="CommandComplete">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" assign="NumHCIBuffers">

+            <Name>Number HCI commands</Name>

+            <Default>any</Default>

+            <Desc>Number of additional HCI Command Packets to be sent to the Host Controller from the host</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Command Opcode</Name>

+        </Param>

+    </Type>

+    

+    <Packet name="ve" type="ve" typemask="0x00000002">

+        <Param type="u" size="1">

+            <Name>Layer</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Event Opcode</Name>

+            <Value>0xFF</Value>

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Length</Name>

+        </Param>

+        <Param type="o" size="1" label="code">

+            <Name>Opcode</Name>

+        </Param>

+		<Param cond="code==0xF0 || code==0xF3 || code==0xF8">

+			<Param type="u" size="1">

+				<Name>Ignore</Name>

+			</Param>

+			<Param type="o" size="1">

+				<Name>Opcode</Name>

+			</Param>

+			<Param type="x" size="len-3">

+				<Name>Payload</Name>

+			</Param>

+		</Param>

+		<Param cond="code==0xF4">

+			<Param type="x" size="len-1">

+				<Name>F4 Payload</Name>

+			</Param>

+        </Param>

+        <Param cond="code==0xF5">

+            <Param type="u" size="1">

+                <Name>FTD Ignore</Name>

+            </Param>

+            <Param type="o" size="1">

+                <Name>FTD Header</Name>

+            </Param>

+            <Param type="x" size="len-3">

+                <Name>Payload</Name>

+            </Param>

+        </Param>

+        <Param cond="(code.lt.0xF0 || code.gt.0xF8)">

+            <Param type="o" size="1">

+                <Name>Opcode2</Name>

+            </Param>

+            <Param type="x" size="len-2">

+                <Name>Payload</Name>

+            </Param>

+        </Param>

+    </Packet>

+    

+    <Packet name="se" type="se" typemask="0x00000002">

+        <Param type="u" size="1">

+            <Name>Layer</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="o" size="1">

+            <Name>Event Opcode</Name>

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Length</Name>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Payload</Name>

+        </Param>

+    </Packet>

+    

+    <Packet name="sc" type="sc">

+        <Param type="u" size="1">

+            <Name>Layer</Name>

+            <Value>0x01</Value>

+        </Param>

+        <Param type="o" size="2">

+            <Name>Event Opcode</Name>

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Length</Name>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Payload</Name>

+        </Param>

+    </Packet>

+    

+    <Packet name="acl_in" type="ce" typemask="0x00000008">

+        <Param type="u" size="1">

+            <Name>Layer</Name>

+            <Value>0x02</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Handle</Name>

+        </Param>

+        <Param type="u" size="2" label="len">

+            <Name>Length</Name>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Payload</Name>

+        </Param>

+    </Packet>

+    

+    <Packet name="HCILL Command" type="llc">

+        <Param type="u" size="1" label="layer">

+            <Name>Layer</Name>

+        </Param>

+        <Param failcond="layer.lt.0x30 || layer.gt.0x33" />

+    </Packet>

+    

+    <Packet name="HCILL Event" type="lle">

+        <Param type="o" size="1" label="layer">

+            <Name>Layer</Name>

+        </Param>

+        <Param failcond="layer.lt.0x30 || layer.gt.0x33" />

+    </Packet>

+    

+    <Packet name="dc" type="cc">

+        <Param type="u" size="1">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="o" size="2">

+            <Name>DOT Debug Opcode</Name>

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Length</Name>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Payload</Name>

+        </Param>

+    </Packet>

+    

+    <Packet name="DOT_Dbg_Event" type="dde">

+        <Param type="u" size="1">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="o" size="1">

+            <Name>DOT Debug Opcode</Name>

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Length</Name>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Payload</Name>

+        </Param>

+    </Packet>

+    

+    <Packet name="DOT_STT_Event" type="dse">

+        <Param type="u" size="1">

+            <Name>Layer</Name>

+            <Value>0xF1</Value>

+        </Param>

+        <Param type="o" size="1">

+            <Name>DOT Status Opcode</Name>

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Length</Name>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Payload</Name>

+        </Param>

+    </Packet>

+    

+    <Packet name="Negotiate" type="ce" typemask="0x00000080">

+        <Param type="u" size="1">

+            <Name>Layer</Name>

+            <Value>0x06</Value>

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Length</Name>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Payload</Name>

+        </Param>

+    </Packet>

+    

+    <Packet name="Alive" type="ce" typemask="0x00000020">

+        <Param type="u" size="1">

+            <Name>Layer</Name>

+            <Value>0x07</Value>

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Length</Name>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Payload</Name>

+        </Param>

+    </Packet>

+    

+    <Packet name="FM_Event" type="ce" typemask="0x00000040"> 

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x08</Value>

+        </Param>

+         <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Num_FM_HCI_Commands</Name>

+            <Default>any</Default>

+        </Param>

+        <Param type="u" size="1">

+            <Name>FM Opcode</Name>

+            <Default>0x00</Default>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>Command Type</Name>

+            <Default>0x00</Default>

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Data Length</Name>

+            <Default>0x02</Default>

+        </Param>

+        

+        <Param type="u" size="len">

+            <Name>Data Parameters</Name>

+            <Default>0x00</Default>

+        </Param>

+    </Packet>

+    

+	<Packet name="GPS_Event" type="ce" > 

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x09</Value>

+        </Param>

+		<Param type="u" size="1">

+            <Name>opcode</Name>           

+        </Param>

+        <Param type="u" size="2" label="len">

+            <Name>Length</Name>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Payload</Name>

+        </Param>

+    </Packet>

+

+	<Packet name="LE_DATA_Event" type="ce" > 

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x52</Value>

+        </Param>

+	<Param type="u" size="2">

+            <Name>opcode</Name>           

+        </Param>

+        <Param type="u" size="2" label="DataLength">

+            <Name>ConnectionId</Name>

+        </Param>

+        <Param type="x" size="DataLength">

+            <Name>Data</Name>

+        </Param>

+    </Packet>

+    

+    <!-- ******************************************************* -->

+    <!-- ******************************************************* -->

+    <!--                                                       	 -->

+    <!-- Enumerations and masks value tables	             	 -->

+    <!--                                                       	 -->

+    <!-- ******************************************************* -->

+    <!-- ******************************************************* -->

+    <Values name="Status" type="enum">

+        <Value val="0x00">Success</Value>

+        <Value val="0x01">Unknown HCI Command</Value>

+        <Value val="0x02">Unknown Connection Identifier</Value>

+        <Value val="0x03">Hardware Failure</Value>

+        <Value val="0x04">Page Timeout</Value>

+        <Value val="0x05">Authentication Failure</Value>

+        <Value val="0x06">PIN Missing</Value>

+        <Value val="0x07">Memory Capacity Exceeded</Value>

+        <Value val="0x08">Connection Timeout</Value>

+        <Value val="0x09">Connection Limit Exceeded</Value>

+        <Value val="0x0A">Synchronous Connection Limit To A Device Exceeded</Value>

+        <Value val="0x0B">ACL Connection Already Exists</Value>

+        <Value val="0x0C">Command Disallowed</Value>

+        <Value val="0x0D">Connection Rejected due to Limited Resources</Value>

+        <Value val="0x0E">Connection Rejected Due To Security Reasons</Value>

+        <Value val="0x0F">Connection Rejected due to Unacceptable BD_ADDR</Value>

+        <Value val="0x10">Connection Accept Timeout Exceeded</Value>

+        <Value val="0x11">Unsupported Feature or Parameter Value</Value>

+        <Value val="0x12">Invalid HCI Command Parameters</Value>

+        <Value val="0x13">Remote User Terminated Connection</Value>

+        <Value val="0x14">Remote Device Terminated Connection due to Low Resources</Value>

+        <Value val="0x15">Remote Device Terminated Connection due to Power Off</Value>

+        <Value val="0x16">Connection Terminated By Local Host</Value>

+        <Value val="0x17">Repeated Attempts</Value>

+        <Value val="0x18">Pairing Not Allowed</Value>

+        <Value val="0x19">Unknown LMP PDU</Value>

+        <Value val="0x1A">Unsupported Remote Feature</Value>

+        <Value val="0x1B">SCO Offset Rejected</Value>

+        <Value val="0x1C">SCO Interval Rejected</Value>

+        <Value val="0x1D">SCO Air Mode Rejected</Value>

+        <Value val="0x1E">Invalid LMP Parameters</Value>

+        <Value val="0x1F">Unspecified Error</Value>

+        <Value val="0x20">Unsupported LMP Parameter Value</Value>

+        <Value val="0x21">Role Change Not Allowed</Value>

+        <Value val="0x22">LMP Response Timeout</Value>

+        <Value val="0x23">LMP Error Transaction Collision</Value>

+        <Value val="0x24">LMP PDU Not Allowed</Value>

+        <Value val="0x25">Encryption Mode Not Acceptable</Value>

+        <Value val="0x26">Link Key Can Not be Changed</Value>

+        <Value val="0x27">Requested QoS Not Supported</Value>

+        <Value val="0x28">Instant Passed</Value>

+        <Value val="0x29">Pairing With Unit Key Not Supported</Value>

+        <Value val="0x2A">Different Transaction Collision</Value>

+        <Value val="0x2B">Reserved</Value>

+        <Value val="0x2C">QoS Unacceptable Parameter</Value>

+        <Value val="0x2D">QoS Rejected</Value>

+        <Value val="0x2E">Channel Classification Not Supported</Value>

+        <Value val="0x2F">Insufficient Security</Value>

+        <Value val="0x30">Parameter Out Of Mandatory Range</Value>

+        <Value val="0x31">Reserved</Value>

+        <Value val="0x32">Role Switch Pending</Value>

+        <Value val="0x33">Reserved</Value>

+        <Value val="0x34">Reserved Slot Violation</Value>

+        <Value val="0x35">Role Switch Failed</Value>

+        <Value val="0x3A">Controller Busy</Value>

+        <Value val="0x3B">Unacceptable Connection Interval</Value>

+        <Value val="0x3C">Directed Advertisement Timeout</Value>

+        <Value val="0x3D">Connection Terminated Due To MIC Failure</Value>

+        <Value val="0x3E">Connection Failed To Be Established</Value>

+    </Values>

+    

+    <Values name="TestMux" type="enum">

+        <Value val="0x01">Test Mux 1</Value>

+        <Value val="0x02">Test Mux 2</Value>

+        <Value val="0x03">Test Mux 3</Value>

+        <Value val="0x04">Test Mux 4</Value>

+        <Value val="0x05">Test Mux 5</Value>

+    </Values>

+    

+    <Values name="SetTestMuxPinNumber" type="enum">

+        <Value val="0x01">DBG 1</Value>

+        <Value val="0x02">DBG 2</Value>

+        <Value val="0x03">DBG 3</Value>

+        <Value val="0x04">DBG 4</Value>

+        <Value val="0x05">DBG 5</Value>

+        <Value val="0x06">DBG 6</Value>

+        <Value val="0x07">DBG 7</Value>

+        <Value val="0x08">DBG 8</Value>

+        <Value val="0x09">DBG 9</Value>

+        <Value val="0x0A">DBG 10</Value>

+    </Values>

+    

+    <Values name="SetTestMuxModuleName" type="enum">

+        <Value val="0x00">DRP - Run also DRP_MUX</Value>

+        <Value val="0x01">WIBREE - Run also Wibree_MUX</Value>

+        <Value val="0x02">Resereved</Value>

+        <Value val="0x03">DMA</Value>

+        <Value val="0x04">OCP_IC</Value>

+        <Value val="0x05">UART</Value>

+        <Value val="0x06">I2C - Not Supported</Value>

+        <Value val="0x07">BT</Value>

+        <Value val="0xFF">Don't Change</Value>

+    </Values>

+    

+    <Values name="UART_Debug_pins" type="enum">

+        <Value val="0x00">vra1_write_txd_cmd</Value>

+        <Value val="0x01">vra21_tx_fifo_rd_req</Value>

+        <Value val="0x02">vra21_rx_fifo_wr_req</Value>

+        <Value val="0x03">vra1_read_rxd_cmd</Value>

+        <Value val="0x04">vra1_irq_source(0)</Value>

+        <Value val="0x05">qra20_halt</Value>

+        <Value val="0x06">qra20_rx_flow_ctrl_state</Value>

+        <Value val="0x07">vre0_byte_en</Value>

+        <Value val="0x08">vra1_tx_rxn</Value>

+        <Value val="0x09">vra1_espi_int_pending</Value>

+        <Value val="0x0A">ca21_baud_clk --> dbg (10)</Value>

+        <Value val="0x0A">vre0_bit_count(18:10) --> dbg (9:1)</Value>

+        <Value val="0x0B">vre0_bit_count(9:0) --> dbg (10:1) </Value>

+        <Value val="0x0C">vre0_tx_state(3:0)--> dbg (4:1)</Value>

+        <Value val="0x0C">vre0_rx_state(3:0)--> dbg (8:5)</Value>

+        <Value val="0x0D">qra1_rx_data_reg(7:0) --> dbg (8:1)</Value>

+        <Value val="0x0E">qra1_tx_state(2:0) --> dbg (3:1)</Value>

+        <Value val="0x0E">qra1_rx_state(2:0) --> dbg (6:4)</Value>

+    </Values>

+    

+    

+    <Values name="OCP_IC_Debug_pins" type="enum">

+        <Value val="0x00">vra1_dfc_api_req</Value>

+        <Value val="0x01">vra1_dfc_l3_req</Value>

+        <Value val="0x02">vra1_bt_gocpu_drp_req</Value>

+        <Value val="0x03">vra1_bt_gocpu_l3_req</Value>

+        <Value val="0x04">vra1_pcmi_l3_req</Value>

+        <Value val="0x05">vra1_pcmi_api_req</Value>

+        <Value val="0x06">vra1_dma1_drp_req</Value>

+        <Value val="0x07">vra1_dma1_api_req</Value>

+        <Value val="0x08">vra1_dma1_sdio_req</Value>

+        <Value val="0x09">vra1_dma1_uart_req</Value>

+        <Value val="0x0A">vra1_dma1_l3_req</Value>

+        <Value val="0x0B">vra1_dma0_drp_req</Value>

+        <Value val="0x0C">vra1_dma0_api_req</Value>

+        <Value val="0x0D">vra1_dma0_sdio_req</Value>

+        <Value val="0x0E">vra1_dma0_uart_req</Value>

+        <Value val="0x0F">vra1_dma0_l3_req</Value>

+        <Value val="0x10">vra1_arm_drp_req</Value>

+        <Value val="0x11">vra1_arm_api_req</Value>

+        <Value val="0x12">vra1_arm_sdio_req</Value>

+        <Value val="0x13">vra1_arm_uart_req</Value>

+        <Value val="0x14">vra1_arm_l3_req</Value>

+        <Value val="0x15">vra1_wibree_api_req</Value>

+        <Value val="0x16">vra1_wibree_l3_req</Value>

+        <Value val="0x17">vra1_api_mcmd(0)</Value>

+        <Value val="0x18">vra1_drp_mcmd(0)</Value>

+        <Value val="0x19">vra1_l3_bridge_mcmd(0)</Value>

+        <Value val="0x1A">vra1_sdio_mcmd_i(0)</Value>

+        <Value val="0x1B">vra1_uart_mcmd_i(0)</Value>

+        <Value val="0x1C">vra1_wibree_mcmd_i(0)</Value>

+        <Value val="0x1D">vra1_drp_scmdaccept(0)</Value>

+        <Value val="0x1E">vra1_l3_bridge_scmdaccept</Value>

+        <Value val="0x1F">vra1_sdio_scmdaccept_i</Value>

+        <Value val="0x20">vra1_uart_scmdaccept_i</Value>

+        <Value val="0x21">vra1_wibree_scmdaccept_i</Value>

+        <Value val="0x22">vra1_arm_serror_i</Value>

+        <Value val="0x23">vra1_pcmi_serror_i</Value>

+        <Value val="0x24">vra1_bt_gocpu_serror_i</Value>

+        <Value val="0x25">bt_dfc_serror</Value>

+        <Value val="0x26">vra1_dma1_serror</Value>

+        <Value val="0x27">vra1_dma0_serror</Value>

+        <Value val="0x28">vra1_wibree_serror</Value>

+        <Value val="0x29">vra1_sinterrupts(0)</Value>

+        <Value val="0x2A">vra1_sinterrupts(1)</Value>

+        <Value val="0x2B">vra1_sinterrupts(2)</Value>

+        <Value val="0x2C">vra1_sinterrupts(3)</Value>

+        <Value val="0x2D">vra1_sinterrupts(4)</Value>

+        <Value val="0x2E">vra1_sinterrupts(5)</Value>

+        <Value val="0x2F">vra1_sinterrupts(6)</Value>

+        <Value val="0x30">vra1_sinterrupts(7)</Value>

+        <Value val="0x31">vra1_sinterrupts(8)</Value>

+        <Value val="0x32">vra1_sinterrupts(9)</Value>

+        <Value val="0x33">vra1_sinterrupts(10)</Value>

+        <Value val="0x34">vra1_sinterrupts(11)</Value>

+        <Value val="0x35">vra1_sinterrupts(12)</Value>

+        <Value val="0x36">vra1_sinterrupts(13)</Value>

+        <Value val="0x37">vra1_sinterrupts(14)</Value>

+        <Value val="0x38">vra1_sinterrupts(15)</Value>

+        <Value val="0x39">vra1_l3_cs(0)--> dbg 0</Value>

+        <Value val="0x39">vra1_l3_cs(1)--> dbg 1</Value>

+        <Value val="0x39">vra1_l3_cs(2)--> dbg 2</Value>

+        <Value val="0x39">vra1_l3_cs(3)--> dbg 3</Value>

+        <Value val="0x39">vra1_l3_cs(0)--> dbg 4</Value>

+        <Value val="0x39">vra1_l3_cs(1)--> dbg 5</Value>

+        <Value val="0x39">vra1_l3_cs(2)--> dbg 6</Value>

+        <Value val="0x39">vra1_l3_cs(3)--> dbg 7</Value>

+    </Values>

+    

+    

+    <Values name="DMA_Debug_pins" type="enum">

+        <Value val="00">SCE1 state (bit 0/1) *</Value>

+        <Value val="01">SCE2 state (bit 0/1) *</Value>

+        <Value val="02">Ch1 arbiter state (bit 0/1) *</Value>

+        <Value val="03">Ch2 arbiter state (bit 0/1) *</Value>

+        <Value val="04">SDMARequest ch1(0)</Value>

+        <Value val="05">SDMARequest ch1(1)</Value>

+        <Value val="06">SDMARequest ch2(0)</Value>

+        <Value val="07">SDMARequest ch2(1)</Value>

+        <Value val="08">SCE1 FIFO empty</Value>

+        <Value val="09">SCE2 FIFO empty</Value>

+        <Value val="10">end-of-transfer ch1</Value>

+        <Value val="11">end-of-transfer ch2</Value>

+        <Value val="12">end-of-script ch1</Value>

+        <Value val="13">end-of-script ch2</Value>

+    </Values>

+    

+    

+    <Values name="SDIO_Debug_pins" type="enum">

+        <Value val="00">bt_sdio_phy_direction--> dbg 1</Value>

+        <Value val="00">bt_sdio_block_start--> dbg 2</Value>

+        <Value val="00">bt_sdio_phy_direction--> dbg 3</Value>

+        <Value val="00">bt_sdio_phy_block_crc_err--> dbg 4</Value>

+        <Value val="00">vra1_dma_flow_rd--> dbg 5</Value>

+        <Value val="00">vra1_l2_rxfifo_rd_en--> dbg 6</Value>

+        <Value val="00">vra2_phy_rxfifo_wr_en--> dbg 7</Value>

+        <Value val="00">qra2_start_tx_sync--> dbg 8</Value>

+        <Value val="00">bt_sdio_phy_direction--> dbg 9</Value>

+        <Value val="00">bt_sdio_phy_direction--> dbg 10</Value>

+        <Value val="01">vra2_ack--> dbg 1</Value>

+        <Value val="01">vra2_nack--> dbg 2</Value>

+        <Value val="01">vra2_write_retry--> dbg 3</Value>

+        <Value val="01">bt_sdio_phy_card_reset--> dbg 4</Value>

+        <Value val="01">bt_sdio_phy_interrupt--> dbg 5</Value>

+        <Value val="01">vra2_phy_txfifo_rd_en--> dbg 6</Value>

+        <Value val="01">vra1_l2_txfifo_wr_en--> dbg 7</Value>

+        <Value val="01">vra1_dma_flow_wr--> dbg 8</Value>

+        <Value val="01">vra2_ack--> dbg 9</Value>

+        <Value val="01">vra2_ack--> dbg 10</Value>

+        <Value val="02">bt_sdio_phy_set_busy--> dbg 1</Value>

+        <Value val="02">bt_sdio_block_crc_err--> dbg 1</Value>

+        <Value val="02">qra_txfifo_busy--> dbg 1</Value>

+        <Value val="02">qra2_txfifo_busy_sync--> dbg 1</Value>

+        <Value val="02">qra2_crc_busy--> dbg 1</Value>

+        <Value val="02">bt_sdio_phy_direction--> dbg 1</Value>

+        <Value val="02">vra2_phy_txfifo_rd_en--> dbg 1</Value>

+        <Value val="02">vra1_l2_txfifo_wr_en--> dbg 1</Value>

+        <Value val="02">bt_sdio_phy_set_busy--> dbg 1</Value>

+        <Value val="02">bt_sdio_phy_set_busy--> dbg 1</Value>

+        <Value val="03">qra2_txfifo_busy--> dbg 1</Value>

+        <Value val="03">qra2_rxfifo_busy_sync--> dbg 2</Value>

+        <Value val="03">bt_sdio_phy_set_busy--> dbg 3</Value>

+        <Value val="03">vra2_ack--> dbg 4</Value>

+        <Value val="03">vra2_nack--> dbg 5</Value>

+        <Value val="03">vra2_write_retry--> dbg 6</Value>

+        <Value val="03">bt_sdio_phy_block_start--> dbg 7</Value>

+        <Value val="03">bt_sdio_phy_block_crc_err--> dbg 8</Value>

+        <Value val="03">qra2_txfifo_busy--> dbg 9</Value>

+        <Value val="03">qra2_txfifo_busy--> dbg 10</Value>

+        <Value val="04">ca1_ocp_gated_clk--> dbg 1</Value>

+        <Value val="04">vra1_dma_flow_wr--> dbg 2</Value>

+        <Value val="04">vra1_dma_flow_rd--> dbg 3</Value>

+        <Value val="04">vra1_l2_rxfifo_rd_en--> dbg 4</Value>

+        <Value val="04">vra2_phy_rxfifo_wr_en--> dbg 5</Value>

+        <Value val="04">qra2_start_tx_sync--> dbg 6</Value>

+        <Value val="04">qra2_start_tx_clr--> dbg 7</Value>

+        <Value val="04">vra2_phy_if_error--> dbg 8</Value>

+        <Value val="04">ca1_ocp_gated_clk--> dbg 9</Value>

+        <Value val="04">ca1_ocp_gated_clk--> dbg 10</Value>

+        <Value val="05">bt_sdio_phy_mcmd[0]--> dbg 1</Value>

+        <Value val="05">bt_sdio_phy_mcmd[1]--> dbg 2</Value>

+        <Value val="05">bt_sdio_phy_mcmd[0]--> dbg 3</Value>

+        <Value val="05">bt_sdio_phy_mcmd[0]--> dbg 4</Value>

+        <Value val="05">bt_sdio_phy_sresp[0]--> dbg 5</Value>

+        <Value val="05">bt_sdio_phy_sresp[1]--> dbg 6</Value>

+        <Value val="05">bt_sdio_phy_sdata[0]--> dbg 7</Value>

+        <Value val="05">bt_sdio_phy_sdata[1]--> dbg 8</Value>

+        <Value val="05">bt_sdio_phy_mcmd[0]--> dbg 9</Value>

+        <Value val="05">bt_sdio_phy_mcmd[0]--> dbg 10</Value>

+        <Value val="06">vra1_wr_ptr_bin_ocp[0]--> dbg 1</Value>

+        <Value val="06">vra1_wr_ptr_bin_ocp[1]--> dbg 2</Value>

+        <Value val="06">vra1_wr_ptr_bin_ocp[2]--> dbg 3</Value>

+        <Value val="06">vra1_wr_ptr_bin_ocp[3]--> dbg 4</Value>

+        <Value val="06">qra1_wr_ptr_wrap--> dbg 5</Value>

+        <Value val="06">qra1_rd_ptr_bin[0]--> dbg 6</Value>

+        <Value val="06">qra1_rd_ptr_bin[1]--> dbg 7</Value>

+        <Value val="06">qra1_rd_ptr_bin[2]--> dbg 8</Value>

+        <Value val="06">qra1_rd_ptr_bin[3]--> dbg 9</Value>

+        <Value val="06">qra1_rd_ptr_wrap--> dbg 10</Value>

+        <Value val="07">qra1_wr_ptr_bin_ocp[0]--> dbg 1</Value>

+        <Value val="07">qra1_wr_ptr_bin_ocp[1]--> dbg 2</Value>

+        <Value val="07">qra1_wr_ptr_bin_ocp[2]--> dbg 3</Value>

+        <Value val="07">qra1_wr_ptr_bin_ocp[3]--> dbg 4</Value>

+        <Value val="07">qra1_wr_ptr_bin_ocp[9]--> dbg 5</Value>

+        <Value val="07">vra1_rd_ptr_bin_ocp[0]--> dbg 6</Value>

+        <Value val="07">vra1_rd_ptr_bin_ocp[1]--> dbg 7</Value>

+        <Value val="07">vra1_rd_ptr_bin_ocp[2]--> dbg 8</Value>

+        <Value val="07">vra1_rd_ptr_bin_ocp[3]--> dbg 9</Value>

+        <Value val="07">vra1_rd_ptr_bin_ocp[9]--> dbg 10</Value>

+    </Values>

+    

+    

+    <Values name="GCM_Debug_pins" type="enum">

+        <Value val="0x00">pll clock signal to design</Value>

+        <Value val="0x01">pll input clock signal from GCM</Value>

+        <Value val="0x02">pll lock signal</Value>

+        <Value val="0x03">pll sync signal</Value>

+        <Value val="0x04">pll power down command (active low)</Value>

+        <Value val="0x05">fast frequency input </Value>

+        <Value val="0x06">system slow clock</Value>

+        <Value val="0x07">system root clock after retiming in DRP</Value>

+        <Value val="0x08">ocp clock</Value>

+        <Value val="0x09">arm clock</Value>

+        <Value val="0x0A">uart clock</Value>

+        <Value val="0x0B">1MHz bt clock</Value>

+        <Value val="0x0C">4MHz bt clock</Value>

+        <Value val="0x0D">8MHz bt clock</Value>

+        <Value val="0x0E">external memory interface clock</Value>

+        <Value val="0x0F">codec clock</Value>

+        <Value val="0x10">sdio clock</Value>

+        <Value val="0x11">spi clock</Value>

+        <Value val="0x12">powerup reset</Value>

+        <Value val="0x13">watchdog timer reset </Value>

+        <Value val="0x14">watch timer interrupt</Value>

+        <Value val="0x15">fast clock enable indication from fcgen to fdc</Value>

+        <Value val="0x16">slow wakeup event from wakeup unit</Value>

+        <Value val="0x17">fast wakeup event from wakeup unit</Value>

+        <Value val="0x18">usec timer event</Value>

+        <Value val="0x19">slow domain control state machine (bus only 0:3), fast domain control state machine (bus only 4:7)</Value>

+        <Value val="0x1A">slow domain scripter control bus (bus only 0:3 or 4:7)</Value>

+    </Values>

+    

+    <Values name="PCMI_Debug_pins" type="enum">

+        <Value val="0x00">codec_get [0]</Value>

+        <Value val="0x01">codec_get [1]</Value>

+        <Value val="0x02">codec_take [0]</Value>

+        <Value val="0x03">codec_take [1]</Value>

+        <Value val="0x04">codec_fsync [0]</Value>

+        <Value val="0x05">codec_fsync [1]</Value>

+        <Value val="0x06">buffer_full [0]</Value>

+        <Value val="0x07">buffer_full [1]</Value>

+        <Value val="0x08">wrap_around_cond [0]</Value>

+        <Value val="0x09">wrap_around_cond [1]</Value>

+        <Value val="0x0A">go_packet_loss [0]</Value>

+        <Value val="0x0B">go_packet_loss [1]</Value>

+        <Value val="0x0C">codec_get_toggle [0]</Value>

+        <Value val="0x0D">codec_get_toggle [1]</Value>

+        <Value val="0x0E">tx_ch_sel</Value>

+        <Value val="0x0F">motorola_mode_duplication [0]</Value>

+        <Value val="0x10">motorola_mode_duplication [1]</Value>

+        <Value val="0x11">motorola_mode_noise [0]</Value>

+        <Value val="0x12">motorola_mode_noise [1]</Value>

+        <Value val="0x13">chx_rx_api_almost_full [0]</Value>

+        <Value val="0x14">chx_rx_api_almost_full [1]</Value>

+        <Value val="0x15">chx_rx_api_full [0]</Value>

+        <Value val="0x16">chx_rx_api_full [1]</Value>

+        <Value val="0x17">codec_take_toggle [0]</Value>

+        <Value val="0x18">codec_take_toggle [1]</Value>

+        <Value val="0x19">rx_ch_sel</Value>

+        <Value val="0x1A">motorola_state_ch0 (0..1;2..3; 4..5; 6..7; 8..9)</Value>

+        <Value val="0x1B">motorola_state_ch1 (0..1;2..3; 4..5; 6..7; 8..9)</Value>

+        <Value val="0x1C">eplc_n_cnt_ch0 (0..4; 5..9)</Value>

+        <Value val="0x1D">eplc_r_cnt_ch0 (0..4; 5..9)</Value>

+        <Value val="0x1E">eplc_n_cnt_ch1 (0..4; 5..9)</Value>

+        <Value val="0x1F">eplc_r_cnt_ch1 (0..4; 5..9)</Value>

+        <Value val="0x20">tx_state (0..3; 4..7)</Value>

+        <Value val="0x21">tx_mn_state (0..3; 4..7)</Value>

+        <Value val="0x22">a_tx_state_ch0 (0..2; 3..5; 6..8)</Value>

+        <Value val="0x23">a_tx_state_ch1 (0..2; 3..5; 6..8)</Value>

+        <Value val="0x24">tx_a_fifo_len_ch0 (0..3; 4..7)</Value>

+        <Value val="0x25">tx_a_fifo_len_ch1 (0..3; 4..7)</Value>

+        <Value val="0x26">rx_state (0..3; 4..7)</Value>

+        <Value val="0x27">rx_mn_state (0..3; 4..7)</Value>

+        <Value val="0x28">a_rx_state_ch0 (0..2; 3..5; 6..8)</Value>

+        <Value val="0x29">a_rx_state_ch1 (0..2; 3..5; 6..8)</Value>

+        <Value val="0x2A">rx_a_fifo_len_ch0 (0..3; 4..7)</Value>

+        <Value val="0x2B">rx_a_fifo_len_ch1 (0..3; 4..7)</Value>

+        <Value val="0x2C">state (0..2; 3..5; 6..8)</Value>

+        <Value val="0x2D">dout_state (0..1;2..3; 4..5; 6..7; 8..9)</Value>

+        <Value val="0x2E">dout_state1_ch0 (0..1;2..3; 4..5; 6..7; 8..9)</Value>

+        <Value val="0x2F">dout_state1_ch1 (0..1;2..3; 4..5; 6..7; 8..9)</Value>

+        <Value val="0x30">din_state (0..1;2..3; 4..5; 6..7; 8..9)</Value>

+        <Value val="0x31">din_mux_sel_ch0 (0..4; 5..9)</Value>

+        <Value val="0x32">din_mux_sel_ch1 (0..4; 5..9)</Value>

+        <Value val="0x33">dout_mux_sel_ch0 (0..4; 5..9)</Value>

+        <Value val="0x34">dout_mux_sel_ch1 (0..4; 5..9)</Value>

+        <Value val="0x35">frame_timer (9..0)</Value>

+        <Value val="0x36">frame_timer(15..10)</Value>

+    </Values>

+    

+    <Values name="BT_Debug_pins" type="enum">

+        <Value val="00">Vf1_LBT[2]</Value>

+        <Value val="01">Vf1_LBT[3]</Value>

+        <Value val="02">Vf1_NBT1[2]</Value>

+        <Value val="03">Vf1_NBT1[3]</Value>

+        <Value val="04">Vf1_NBT2[2]</Value>

+        <Value val="05">Vf1_NBT2[3]</Value>

+        <Value val="06">C51_network1_clk_cts</Value>

+        <Value val="07">C52_network2_clk_cts</Value>

+        <Value val="08">C6_local_clk_cts</Value>

+        <Value val="09">Vf1_switched_BTC[2]</Value>

+        <Value val="10">Vf1_switched_BTC[3]</Value>

+        <Value val="11">Vf1_switched_scheduler_BTC[2]</Value>

+        <Value val="12">Sr1_lcl_packet_timer[10]</Value>

+        <Value val="13">Sr1_net1_packet_timer[10]</Value>

+        <Value val="14">Sr1_net2_packet_timer[10]</Value>

+        <Value val="15">Sr1_switched_packet_timer[10]</Value>

+        <Value val="16">Scheduler_switched_packet_timer[10]</Value>

+        <Value val="17">Vr1_SCO_ch1_window</Value>

+        <Value val="18">Vr1_SCO_ch2_window</Value>

+        <Value val="19">Vr1_SCO_ch1_instant</Value>

+        <Value val="20">Vr1_SCO_ch2_instant</Value>

+        <Value val="21">Vr1_SCO_ch_select</Value>

+        <Value val="22">Vr1_SCO_ch1_active</Value>

+        <Value val="23">Vr1_SCO_ch2_active</Value>

+        <Value val="24">Vr1_SCO_req</Value>

+        <Value val="25">Vr1_SCO_go</Value>

+        <Value val="26">Vr1_SCO_block</Value>

+        <Value val="27">Vr1_scheduler_req</Value>

+        <Value val="28">Vr1_scheduler_go</Value>

+        <Value val="29">Vr1_scheduler_block</Value>

+        <Value val="30">Vr1_periodic_req</Value>

+        <Value val="31">Vr1_periodic_go</Value>

+        <Value val="32">Vr1_periodic_block</Value>

+        <Value val="33">Vr1_sco_tx_enable</Value>

+        <Value val="34">Vr1_ACL_tx_enable</Value>

+        <Value val="35">NIRQ1</Value>

+        <Value val="36">NIRQ2</Value>

+        <Value val="37">NIRQ3</Value>

+        <Value val="38">NIRQ4</Value>

+        <Value val="39">Vr1_scheduler_empty</Value>

+        <Value val="40">Vr1_scheduler_stalled</Value>

+        <Value val="41">Vr1_scheduler_almost_empty</Value>

+        <Value val="42">Vr1_mode_reg_jump</Value>

+        <Value val="43">Vr10_scheduler_flush_command</Value>

+        <Value val="44">scheduler_continue_program</Value>

+        <Value val="45">scheduler_program_started</Value>

+        <Value val="46">Vr1_correlation_win</Value>

+        <Value val="47">Vr1_sync_event</Value>

+        <Value val="48">OCP clk</Value>

+        <Value val="49">ca11_bt_ctl_clk</Value>

+        <Value val="50">ca12_bt_dt_clk </Value>

+        <Value val="51">cs1_bt_slow_clk</Value>

+        <Value val="52">L_Status</Value>

+        <Value val="53">N1_Status</Value>

+        <Value val="54">N2_Status</Value>

+        <Value val="55">Main_clk_Status</Value>

+        <Value val="56">Vr1_Slave_nMaster</Value>

+        <Value val="57">Vr1_N2_Select</Value>

+        <Value val="58">L_Load_event</Value>

+        <Value val="59">N1_Load_ event</Value>

+        <Value val="60">N2_Load_ event</Value>

+        <Value val="61">AFH_selector[0]</Value>

+        <Value val="62">AFH_selector[1]</Value>

+        <Value val="63">AFH_enabled</Value>

+        <Value val="64">AFH_recovery</Value>

+        <Value val="65">Vr1_HEC_event</Value>

+        <Value val="66">Vr1_HEC_ok</Value>

+        <Value val="67">Vr1_CRC_event</Value>

+        <Value val="68">Vr1_CRC_ok</Value>

+        <Value val="69">Vr1_length_event</Value>

+        <Value val="70">Vr1_bad_length</Value>

+        <Value val="71">Vr1_rx_stop</Value>

+        <Value val="72">Vr1_tx_strech</Value>

+        <Value val="73">Vr1_rx_strech</Value>

+        <Value val="74">Vr1_rx_time_out</Value>

+        <Value val="75">BB_TX_Data @ 3M</Value>

+        <Value val="76">BB_RX_Data @ 3M</Value>

+        <Value val="77">BB_TX_RX_Data @ 3M</Value>

+        <Value val="78">RX_nTX_wire (MU1_control)</Value>

+        <Value val="79">Tx_payload_br[0]</Value>

+        <Value val="80">Tx_payload_br[1]</Value>

+        <Value val="81">Rx_payload_br[0]</Value>

+        <Value val="82">Rx_payload_br[1]</Value>

+        <Value val="83">EDR_sync</Value>

+        <Value val="84">Per Debug</Value>

+        <Value val="85">Per Debug</Value>

+        <Value val="86">Per Debug</Value>

+        <Value val="87">Per Debug</Value>

+        <Value val="88">Per Debug</Value>

+        <Value val="89">Per Debug</Value>

+        <Value val="90">Per Debug</Value>

+        <Value val="91">Per Debug</Value>

+        <Value val="92">Per Debug</Value>

+        <Value val="93">Per Debug</Value>

+        <Value val="94">Per Debug</Value>

+        <Value val="95">Per Debug</Value>

+        <Value val="96">Per Debug</Value>

+        <Value val="97">Per Debug</Value>

+        <Value val="98">Per Debug</Value>

+        <Value val="00">vra11_sco_chid(ESCO1_WINDOW) - Orca </Value>

+        <Value val="01">vra11_sco_chid(ESCO2_WINDOW) - Orca </Value>

+        <Value val="02">vra11_sco_chid(INSTANT1) - Orca </Value>

+        <Value val="03">vra11_sco_chid(INSTANT2) - Orca </Value>

+        <Value val="04">vra11_sco_chid(CH_SELECT) - Orca </Value>

+        <Value val="05">vra11_sco_chid(CH1_ACTIVE) - Orca </Value>

+        <Value val="06">vra11_sco_chid(CH2_ACTIVE) - Orca </Value>

+        <Value val="07">vra11_sco_req - Orca </Value>

+        <Value val="08">vra11_sco_go - Orca </Value>

+        <Value val="09">vra11_sco_block - Orca </Value>

+        <Value val="10">vra11_scheduler_req - Orca </Value>

+        <Value val="11">vra11_scheduler_go - Orca </Value>

+        <Value val="12">vra11_scheduler_block - Orca </Value>

+        <Value val="13">vra11_sco_tx_en - Orca </Value>

+        <Value val="14">vra11_acl_tx_en - Orca </Value>

+        <Value val="15">qra11_dc2dc_mode - Orca </Value>

+        <Value val="16">vra11_nirq1 - Orca </Value>

+        <Value val="17">vra11_nirq3 - Orca </Value>

+        <Value val="18">vra11_nirq4 - Orca </Value>

+        <Value val="19">vra11_scheduler_empty - Orca </Value>

+        <Value val="20">vra11_scheduler_stalled - Orca </Value>

+        <Value val="21">vra11_scheduler_almost_empty - Orca </Value>

+        <Value val="22">vra11_mode_register_jump_event - Orca </Value>

+        <Value val="23">vra11_scheduler_flush_cmd - Orca </Value>

+        <Value val="24">vra11_scheduler_continue_pgm - Orca </Value>

+        <Value val="25">vra11_program_started_dbg - Orca </Value>

+        <Value val="26">vra11_scheduler_fetch_done - Orca </Value>

+        <Value val="27">qra11_correlation_window - Orca </Value>

+        <Value val="28">ca1_ocp_clk - Orca </Value>

+        <Value val="29">ca11_bt_ctl_clk - Orca </Value>

+        <Value val="30">ca12_bt_dt_clk  - Orca </Value>

+        <Value val="31">vra11_static_control(SLAVE_NMASTER) - Orca </Value>

+        <Value val="32">vra11_static_control(N2_SELECT) - Orca </Value>

+        <Value val="33">vra11_decoded_afh_sel[0] - Orca </Value>

+        <Value val="34">vra11_decoded_afh_sel[1] - Orca </Value>

+        <Value val="35">vra11_decoded_afh_en - Orca </Value>

+        <Value val="36">vra11_decoded_recovery_en - Orca </Value>

+        <Value val="37">vra11_HEC_event - Orca </Value>

+        <Value val="38">vra11_HEC_ok - Orca </Value>

+        <Value val="39">vra11_CRC_event - Orca </Value>

+        <Value val="40">vra11_CRC_ok - Orca </Value>

+        <Value val="41">vra11_length_event - Orca </Value>

+        <Value val="42">vra11_bad_length - Orca </Value>

+        <Value val="43">vra11_rx_stop - Orca </Value>

+        <Value val="44">vra11_tx_strech - Orca </Value>

+        <Value val="45">vra11_rx_strech - Orca </Value>

+        <Value val="46">vra1_rx_acl_almost_empty_intr - Orca </Value>

+        <Value val="47">OR Fifo hflush - Orca </Value>

+        <Value val="48">OR Fifo sflush - Orca </Value>

+        <Value val="49">vra12_bb_txd_dbg - Orca </Value>

+        <Value val="50">qra11_rx_ntx_wire - Orca </Value>

+        <Value val="51">qra11_packet_br[0] (TX) - Orca </Value>

+        <Value val="52">qra11_packet_br[1] (TX) - Orca </Value>

+        <Value val="53">vra11_packet_br[0] (RX) - Orca </Value>

+        <Value val="54">vra11_packet_br[1] (RX) - Orca </Value>

+        <Value val="55">vra11_gfsk_sync  - Orca </Value>

+        <Value val="56">vra11_edr_sync  - Orca </Value>

+        <Value val="57">vra12_bb_rxd_dbg - Orca </Value>

+        <Value val="58">tx_rx_data_post_sync - Orca </Value>

+        <Value val="59">tx_data_toggle - Orca </Value>

+        <Value val="60">phy_data_toggle (RX data) - Orca </Value>

+    </Values>

+    

+    <Values name="PackageType" type="enum">

+        <Value val="0x0">BGA</Value>

+        <Value val="0x1">WSP</Value>

+        <Value val="0xff">All</Value>

+        

+    </Values>

+    

+    <Values name="Role" type="enum">

+        <Value val="0x00">Master</Value>

+        <Value val="0x01">Slave</Value>

+    </Values>

+    

+    <Values name="Sampling_edge_type" type="enum">

+        <Value val="0">Rising Edge</Value>

+        <Value val="1">Falling Edge</Value>

+    </Values>

+    

+    <Values name="FM_command" type="enum">

+        <Value val="0">STEREO_GET</Value>

+        <Value val="1">RSSI_LVL_GET</Value>

+        <Value val="2">IF_COUNT_GET</Value>

+        <Value val="3">FLAG_GET</Value>

+        <Value val="4">RDS_SYNC_GET</Value>

+		<Value val="5">RDS_DATA_GET</Value>

+        <Value val="6">LOCK_GET</Value>

+        <Value val="10">FREQ_SET_GET</Value>

+        <Value val="11">AF_FREQ_SET_GET</Value>

+        <Value val="12">MOST_MODE_SET_GET</Value>

+        <Value val="13">MOST_BLEND_SET_GET</Value>

+        <Value val="14">DEMPH_MODE_SET_GET</Value>

+        <Value val="15">SEARCH_LVL_SET_GET</Value>

+        <Value val="16">BAND_SET_GET</Value>

+        <Value val="17">MUTE_STATUS_SET_GET</Value>

+        <Value val="18">RDS_PAUSE_LVL_SET_GET</Value>

+        <Value val="19">RDS_PAUSE_DUR_SET_GET</Value>

+        <Value val="20">RDS_MEM_SET_GET</Value>

+        <Value val="21">RDS_BLK_B_SET_GET</Value>

+        <Value val="22">RDS_MSK_B_SET_GET</Value>

+        <Value val="23">RDS_PI_MASK_SET_GET</Value>

+        <Value val="24">RDS_PI_SET_GET</Value>

+        <Value val="25">RDS_SYSTEM_SET_GET</Value>

+        <Value val="26">INT_MASK_SET_GET</Value>

+        <Value val="27">SEARCH_DIR_SET_GET</Value>

+        <Value val="28">VOLUME_SET_GET</Value>

+        <Value val="29">AUDIO_ENABLE_SET_GET</Value>

+        <Value val="30">I2S_CLOCK_CONFIG_SET_GET</Value>

+        <Value val="31">I2S_MODE_CONFIG_SET_GET</Value>

+        <Value val="32">POWER_SET_GET</Value>

+        <Value val="33">INTX_CONFIG_SET_GET</Value>

+        <Value val="34">PULL_EN_SET_GET</Value>

+        <Value val="35">HILO_SET_GET</Value>

+		<Value val="36">SWITCH2FREF</Value> 

+        <Value val="37">FREQ_DRIFT_REPORT</Value>

+        <Value val="40">PCE_GET</Value>

+        <Value val="41">FIRM_VER_GET</Value>

+        <Value val="42">ASIC_VER_GET</Value>

+        <Value val="43">ASIC_ID_GET</Value>

+        <Value val="44">MAN_ID_GET</Value>

+        <Value val="45">TUNER_MODE_SET</Value>

+        <Value val="46">STOP_SEARCH</Value>

+        <Value val="55">CHANL_SET</Value>

+        <Value val="56">CHANL_BW_SET</Value>

+        <Value val="57">REF_SET</Value>

+        <Value val="58">POWER_ATT_SET</Value>

+        <Value val="59">POWER_LEV_SET</Value>

+        <Value val="60">AUDIO_DEV_SET</Value>

+        <Value val="61">PILOT_DEV_SET</Value>

+        <Value val="62">RDS_DEV_SET</Value>

+        <Value val="63">AUDIO_IO_SET</Value>

+        <Value val="64">PREMPH_SET</Value>

+        <Value val="65">BAND_SET</Value>

+        <Value val="66">MONO_SET</Value>

+        <Value val="67">MPX_LMT_SET</Value>

+        <Value val="68">PI_SET</Value>

+        <Value val="69">TYPE_SET</Value>

+        <Value val="70">PTY</Value>

+        <Value val="71">AF</Value>

+        <Value val="72">DISPLAY_SIZE</Value>

+        <Value val="73">RDS_MODE</Value>

+        <Value val="74">DISPLAY_MODE</Value>

+        <Value val="75">LENGTH</Value>

+        <Value val="76">TOGGLE_AB</Value>

+        <Value val="77">RDS_REP_SET</Value>

+        <Value val="78">TA_SET</Value>

+        <Value val="79">TP_SET</Value>

+        <Value val="80">DI_SET</Value>

+        <Value val="81">MS_SET</Value>

+        <Value val="82">PS_SCROLL_SPEED</Value>

+        <Value val="90">POWER_ENB_SET</Value>

+        <Value val="91">PUPD_SET</Value>

+        <Value val="92">MUTE</Value>

+        <Value val="93">REF_ERR_SET</Value>

+        <Value val="94">RDS_DATA_ENB</Value>

+        <Value val="99">RDS_DATA_SET !!! Experimental !!!</Value>

+        <Value val="100">HW_REGISTER_SET</Value>

+        <Value val="101">CODE_DOWNLOAD</Value>

+        <Value val="102">RESET</Value>

+        <Value val="254">FM_POWER_MODE (Relevant only on Channel 8)</Value>

+    </Values>

+     

+    

+    <Values name="SleepProtocolTypes" type="enum">

+        <Value val="0x00">HCILL</Value>

+        <Value val="0x01">PALAU</Value>

+        <Value val="0x02">PALAU Six Wire</Value>

+        <Value val="0x03">BORNEO Six Wite Active High</Value>

+        <Value val="0x04">BORNEO Six Wite Active Low</Value>

+        <Value val="0x05">H5 (you can either choose 0xFF for H5 deep sleep)</Value>

+        <Value val="0x06">SPI (Both eSPI and BT_SPI)</Value>

+        <Value val="0x07">Reserved</Value>

+        <Value val="0x08">Reserved</Value>

+        <Value val="0x09">UART Break Indication protocol</Value>

+        <Value val="0x0A">SBIS (SlimBus In-band Sleep protocol)</Value>

+        <Value val="0x0B">SLIMbus Out Of Band</Value>

+        <Value val="0xFF">Don't Change</Value>

+    </Values>

+    

+    <Values name="SLEEP_MODE_CONFIGURATION_OUTPUT_IO_SELECT" type="enum">

+        <Value val="0x01">BT_FUNC1</Value>

+        <Value val="0x02">BT_FUNC2</Value>

+        <Value val="0x03">BT_FUNC3</Value>

+        <Value val="0x04">BT_FUNC4</Value>

+        <Value val="0x05">BT_FUNC5</Value>		

+        <Value val="0x06">BT_FUNC6</Value>

+        <Value val="0x07">BT_FUNC7</Value>

+    </Values>

+    

+    <Values name="SLEEP_MODE_CONFIGURATION_INPUT_IO_SELECT" type="enum">

+        <Value val="0xFF">0xFF - Dont Change</Value>

+        <Value val="0x01">BT_FUNC1</Value>

+        <Value val="0x02">BT_FUNC2</Value>

+        <Value val="0x03">BT_FUNC3</Value>

+    </Values>

+    

+    <Values name="GSM_CONFIGURATION_ORCA_SELECT" type="enum">

+        <Value val="0x01">BT_FUNC1</Value>

+        <Value val="0x02">BT_FUNC2</Value>

+        <Value val="0x03">BT_FUNC3</Value>

+        <Value val="0x04">BT_FUNC4</Value>

+        <Value val="0x05">BT_FUNC5</Value>

+        <Value val="0x07">BT_FUNC7</Value>

+    </Values>

+    

+    <Values name="ClkSharingPullTypes_BT_IP" type="enum">

+        <Value val="0x00">Disable Pull</Value>

+        <Value val="0x01">Enable Pull</Value>

+    </Values>

+	

+	<Values name="ClkSharingPullConfiguration_BT_IP" type="enum">

+        <Value val="0x00">Pull Down</Value>

+        <Value val="0x01">Pull up</Value>

+    </Values>

+    

+    <Values name="ClockSharingOutputMode_BT_IP" type="enum">

+        <Value val="0x01">Output is Tri-state</Value>

+        <Value val="0x02">Output enabled</Value>

+        <Value val="0x03">Wired OR (Clk_Req=L, output is Z;Clk_Req=H, output is enabled)</Value>

+    </Values>

+    

+    <Values name="EnableDisableNoChange" type="enum">

+        <Value val="0">Disable</Value>

+        <Value val="1">Enable</Value>

+        <Value val="0xFF">No change</Value>

+    </Values>

+	

+    <Values name="EnableDisableDefaultNoChange" type="enum">

+        <Value val="0">Disable pull</Value>

+        <Value val="1">Enable pull</Value>

+		<Value val="2">Default pull</Value>

+        <Value val="0xFF">No change</Value>

+    </Values>

+	

+	<Values name="NetworkClockSelection" type="enum">

+        <Value val="1">Network 1</Value>

+        <Value val="2">Network 2</Value>        

+    </Values>

+	

+	<Values name="Auto_Recovery_States" type="enum">

+        <Value val="0">Auto Recovery Stopped because of SLOW TO expiration</Value>

+        <Value val="1">Auto Recovery Succeeded</Value>

+		<Value val="2">Auto Recovery is in the Fast Recovery State</Value>

+		<Value val="3">Auto Recovery is in the Slow Recovery State</Value>

+    </Values>

+	

+	<Values name="Auto_Recovery_Roles" type="enum">

+        <Value val="0">Recovery Page is being scheduled</Value>

+        <Value val="1">Recovery Scan is being scheduled</Value>		

+    </Values>

+	

+    <Values name="Rwin_Override" type="enum">

+        <Value val="0x00">always override rwin with acl</Value>

+        <Value val="0x01">use the poll override theshold to override rwin</Value>

+    </Values>

+    

+    <Values name="Packet_TX_RX_Power_Level_Orca_Index" type="enum">

+        <Value val="0">Power Level 0</Value>

+        <Value val="1">Power Level 1</Value>

+        <Value val="2">Power Level 2</Value>

+        <Value val="3">Power Level 3</Value>

+        <Value val="4">Power Level 4</Value>

+        <Value val="5">Power Level 5</Value>

+        <Value val="6">Power Level 6</Value>

+        <Value val="7">Power Level 7</Value>

+        <Value val="8">Power Level 8</Value>

+        <Value val="9">Power Level 9</Value>

+        <Value val="10">Power Level 10</Value>

+        <Value val="11">Power Level 11</Value>

+        <Value val="12">Power Level 12</Value>

+        <Value val="13">Power Level 13</Value>

+        <Value val="14">Power Level 14</Value>

+        <Value val="15">Power Level 15</Value>

+    </Values>

+    

+    <Values name="Packet_TX_RX_Pkt_Type" type="enum">

+        <Value val="0x0">DM1</Value>

+        <Value val="0x1">DH1</Value>

+        <Value val="0x2">DM3</Value>

+        <Value val="0x3">DH3</Value>

+        <Value val="0x4">DM5</Value>

+        <Value val="0x5">DH5</Value>

+        <Value val="0x6">2-DH1</Value>

+        <Value val="0x7">2-DH3</Value>

+        <Value val="0x8">2-DH5</Value>

+        <Value val="0x9">3-DH1</Value>

+        <Value val="0xA">3-DH3</Value>

+        <Value val="0xB">3-DH5</Value>

+    </Values>

+    

+    <Values name="Packet_TX_RX_Pkt_Pattern" type="enum">

+        <Value val="0x0">All 0</Value>

+        <Value val="0x1">All 1</Value>

+        <Value val="0x2">ZOZO</Value>

+        <Value val="0x3">F0F0</Value>

+        <Value val="0x4">Ordered</Value>

+        <Value val="0x5">PRBS9 Random</Value>

+    </Values>

+    

+    <Values name="PA_Mode" type="enum">

+        <Value val="0">Off</Value>

+        <Value val="1">DAC</Value>

+        <Value val="2">PWM</Value>

+        <Value val="3">Digital</Value>

+        <Value val="0xFF">Don't change</Value>

+    </Values>

+    

+    <Values name="Override_Temp" type="enum">

+        <Value val="0x00">Only if temp changes</Value>

+        <Value val="0x01">Override temp changes</Value>

+    </Values>

+    

+    <Values name="Modulation_Type" type="enum">

+        <Value val="0x00">GFSK</Value>

+        <Value val="0x01">EDR 2MB</Value>

+        <Value val="0x02">EDR 3MB</Value>

+    </Values>

+    

+    <Values name="Con_TX_Modulation_Scheme" type="enum">

+        <Value val="0x0">CW</Value>

+        <Value val="0x1">GFSK</Value>

+        <Value val="0x2">2-EDR</Value>

+        <Value val="0x3">3-EDR</Value>

+		<Value val="0x4">BLE</Value>

+    </Values>

+    

+    <Values name="Con_TX_Test_Pattern" type="enum">

+        <Value val="0x0">PN9</Value>

+        <Value val="0x1">PN15</Value>

+        <Value val="0x2">ZOZO</Value>

+        <Value val="0x3">All 1</Value>

+        <Value val="0x4">All 0</Value>

+        <Value val="0x5">F0F0</Value>

+        <Value val="0x6">FF00</Value>

+        <Value val="0x7">User Defined</Value>

+    </Values>

+    

+    <Values name="Frequency_Mode" type="enum">

+        <Value val="0x00">Hopping</Value>

+        <Value val="0x03">Single freq</Value>

+    </Values>

+    

+    <Values name="Packet_TX_RX_Disable_Whitening" type="enum">

+        <Value val="0x00">Enable</Value>

+        <Value val="0x01">Disable</Value>

+    </Values>

+

+    <Values name="Wibree_Disable_Enable_Whitening" type="enum">

+        <Value val="0x01">Enable</Value>

+        <Value val="0x00">Disable</Value>

+    </Values>

+

+    <Values name="Wibree_force_no_force" type="enum">

+        <Value val="0x00">Don't Force</Value>

+        <Value val="0x01">Force</Value>

+    </Values>

+		    

+    <Values name="ADPLL_LF_Set" type="enum">

+        <Value val="0">0</Value>

+        <Value val="1">1</Value>

+        <Value val="2">2</Value>

+        <Value val="3">3</Value>

+        <Value val="4">4</Value>

+        <Value val="5">5</Value>

+        <Value val="6">6</Value>	

+        <Value val="7">7</Value>

+    </Values>

+

+    <Values name="DO_IO_STRENGTH_5500_SELECT" type="enum">

+        <Value val="0x00">Dont Change</Value>

+        <Value val="0x02">2 mAmp</Value>

+        <Value val="0x04">4 mAmp</Value>

+        <Value val="0x06">6 mAmp</Value>

+        <Value val="0x08">8 mAmp</Value>

+    </Values>

+

+    <Values name="DrpBerMeterPktType" type="enum">

+        <Value val="0x0">DM1</Value>

+        <Value val="0x1">DH1</Value>

+        <Value val="0x2">DM3</Value>

+        <Value val="0x3">DH3</Value>

+        <Value val="0x4">DM5</Value>

+        <Value val="0x5">DH5</Value>

+        <Value val="0x6">2-DH1</Value>

+        <Value val="0x7">2-DH3</Value>

+        <Value val="0x8">2-DH5</Value>

+        <Value val="0x9">3-DH1</Value>

+        <Value val="0xA">3-DH3</Value>

+        <Value val="0xB">3-DH5</Value>

+    </Values>

+    

+    <Values name="PageScanRepetitionMode" type="enum">

+        <Value val="0x00">R0</Value>

+        <Value val="0x01">R1</Value>

+        <Value val="0x02">R2</Value>

+    </Values>

+    

+    <Values name="DisconnectReason" type="enum">

+        <Value val="0x05">Authentication Failure</Value>

+        <Value val="0x13">Remote User Terminated Connection</Value>

+        <Value val="0x15">Remote Device Terminated Connection due to Power Off</Value>

+        <Value val="0x1A">Unsupported Remote Feature</Value>

+        <Value val="0x29">Pairing With Unit Key Not Supported</Value>

+    </Values>

+    

+    <Values name="RejectReason" type="enum">

+        <Value val="0x0D">Connection Rejected due to Limited Resources</Value>

+        <Value val="0x0E">Connection Rejected Due To Security Reasons</Value>

+        <Value val="0x0F">Connection Rejected due to Unacceptable BD_ADDR</Value>

+    </Values>

+     

+    

+    <Values name="OffOn" type="enum">

+        <Value val="0x00">Off</Value>

+        <Value val="0x01">On</Value>

+    </Values>

+    

+    <Values name="OnOff" type="enum">

+        <Value val="0x00">On</Value>

+        <Value val="0x01">Off</Value>

+    </Values>

+    

+    <Values name="LinkKeyFlag" type="enum">

+        <Value val="0x00">Use semi-permanent Link Keys</Value>

+        <Value val="0x01">Use Temporary Link Key</Value>

+    </Values>

+    

+    <Values name="Retransmission_Effort" type="enum">

+        <Value val="0x00">No retransmissions</Value>

+        <Value val="0x01">At least one retransmission, optimize for power consumption</Value>

+        <Value val="0x02">At least one retransmission, optimize for link quality</Value>

+        <Value val="0xFF">Don't care</Value>

+    </Values>

+    

+    <Values name="Io Capability" type="enum">

+        <Value val="0x00">Display only</Value>

+        <Value val="0x01">DisplayYesNo</Value>

+        <Value val="0x02">KeyboardOnly</Value>

+        <Value val="0x03">NoInputNoOutput</Value>

+    </Values>

+    

+    <Values name="OOB Data Present" type="enum">

+        <Value val="0x00">OOB authentication data not present</Value>

+        <Value val="0x01">OOB authentication data from remote device present</Value>

+    </Values>

+    

+    <Values name="Authentication Required" type="enum">

+        <Value val="0x00">MITM Protection Not Required – Single Profile.  Numeric comparison with automatic accept allowed</Value>

+        <Value val="0x01">MITM Protection Required – Single Profile.  Use IO Capabilities to determine authentication procedure</Value>

+        <Value val="0x02">MITM Protection Not Required – All Profiles.  Numeric comparison with automatic accept allowed</Value>

+        <Value val="0x03">MITM Protection Required – All Profiles.  Use IO Capabilities to determine authentication procedure</Value>

+    </Values>

+    

+    <Values name="Notification_Type" type="enum">

+        <Value val="0x00">Passkey entry started</Value>

+        <Value val="0x01">Passkey digit entered</Value>

+        <Value val="0x02">Passkey digit erased</Value>

+        <Value val="0x03">Passkey cleared</Value>

+        <Value val="0x04">Passkey entry completed</Value>

+    </Values>

+    

+    <Values name="ServiceType" type="enum">

+        <Value val="0x00">No Traffic</Value>

+        <Value val="0x01">Best Effort</Value>

+        <Value val="0x02">Guaranteed</Value>

+    </Values>

+     

+    

+    <Values name="FlowDirection" type="enum">

+        <Value val="0x00">Outgoing Flow</Value>

+        <Value val="0x01">Incoming Flow</Value>

+    </Values>

+    

+    <Values name="EventFilter" type="enum">

+        <Value val="0x00">Clear All Filters</Value>

+        <Value val="0x01">Inquiry Result</Value>

+        <Value val="0x02">Connection Setup</Value>

+    </Values>

+    

+    <Values name="EventCondition" type="enum">

+        <Value val="0x00">All Devices</Value>

+        <Value val="0x01">Specific Class Of Device</Value>

+        <Value val="0x02">Specific BD Address</Value>

+    </Values>

+    

+    <Values name="AutoAcceptFlag" type="enum">

+        <Value val="0x01">Do NOT auto accept</Value>

+        <Value val="0x02">Accept with role switch disabled</Value>

+        <Value val="0x03">Accept with role switch enabled</Value>

+    </Values>

+    

+    <Values name="PinType" type="enum">

+        <Value val="0x00">Variable</Value>

+        <Value val="0x01">Fixed</Value>

+    </Values>

+    

+    <Values name="AllLinkKeyFlag" type="enum">

+        <Value val="0x00">Link Key specified by BD_ADDR</Value>

+        <Value val="0x01">All stored Link Keys</Value>

+    </Values>

+    

+    <Values name="ScanEnable" type="enum">

+        <Value val="0x00">No Scans</Value>

+        <Value val="0x01">Inquiry Scan</Value>

+        <Value val="0x02">Page Scan</Value>

+        <Value val="0x03">Page and Inquiry Scan</Value>

+    </Values>

+    

+    <Values name="EnableDisable" type="enum">

+        <Value val="0">Disable</Value>

+        <Value val="1">Enable</Value>

+    </Values>

+    

+    <Values name="HoldModeActivity" type="enum">

+        <Value val="0x00">Maintain current Power State</Value>

+        <Value val="0x01">Suspend Page Scan</Value>

+        <Value val="0x02">Suspend Inquiry Scan</Value>

+        <Value val="0x04">Suspend Periodic Inquiries</Value>

+    </Values>

+    

+    <Values name="TransmitLevelType" type="enum">

+        <Value val="0">Read Current Transmit Power Level</Value>

+        <Value val="1">Read Maximum Transmit Power Level</Value>

+    </Values>

+    

+    <Values name="FlowControlEnable" type="enum">

+        <Value val="0x00">Flow Control Off</Value>

+        <Value val="0x01">Flow Control On for ACL</Value>

+        <Value val="0x02">Flow Control On for SCO</Value>

+        <Value val="0x03">Flow Control On for both ACL and SCO</Value>

+    </Values>

+    

+    <Values name="PeriodMode" type="enum">

+        <Value val="0x00">P0</Value>

+        <Value val="0x01">P1</Value>

+        <Value val="0x02">P2</Value>

+    </Values>

+    

+    <Values name="PageScanMode" type="enum">

+        <Value val="0x00">Mandatory</Value>

+        <Value val="0x01">Optional 1</Value>

+        <Value val="0x02">Optional 2</Value>

+        <Value val="0x03">Optional 3</Value>

+    </Values>

+    

+    <Values name="ScanType" type="enum">

+        <Value val="0x00">Mandatory: Standard Scan</Value>

+        <Value val="0x01">Optional: Interlaced Scan</Value>

+    </Values>

+    

+    <Values name="InquiryMode" type="enum">

+        <Value val="0x00">Standard</Value>

+        <Value val="0x01">With RSSI</Value>

+        <Value val="0x02">Inquiry Result with RSSI or Extended Inquiry Result Format</Value>

+    </Values>

+    

+    <Values name="Alphanumeric_Pin_Type" type="enum">

+        <Value val="0x00">Not Aware of Alphanumeric PIN codes support</Value>

+        <Value val="0x01">Cannot support Alphanumeric PIN codes</Value>

+        <!--

+<Value val="0x02">Reserved</Value>

+-->

+        <Value val="0x03">Support Alphanumeric PIN codes</Value>

+    </Values>

+    

+    <Values name="Simple_Pairing_Mode" type="enum">

+        <Value val="0x00">Undefined</Value>

+        <Value val="0x01">Simple Pairing enabled</Value>

+    </Values>

+    

+    <Values name="Erroneous_Data_Reporting" type="enum">

+        <Value val="0x00">The Packet_Status_Flag shall be set to 0 for new (e)SCO connections (Default)</Value>

+        <Value val="0x01">For new (e)SCO connections, the Packet_Status_Flag will be set</Value>

+    </Values>

+    

+    <Values name="HCIVersion" type="enum">

+        <Value val="0x00">Bluetooth HCI Specification 1.0B</Value>

+        <Value val="0x01">Bluetooth HCI Specification 1.1</Value>

+        <Value val="0x02">Bluetooth HCI Specification 1.2</Value>

+        <Value val="0x03">Bluetooth HCI Specification 2.0</Value>

+        <Value val="0x04">Bluetooth HCI Specification 2.1</Value>

+        <Value val="0x05">Bluetooth HCI Specification 3.0</Value>

+	<Value val="0x06">Bluetooth HCI Specification 4.0</Value>

+        <!-- 

+	Taken from the following URL:

+	https://www.bluetooth.org/foundry/assignnumb/document/hci_assigned_numbers 

+-->

+    </Values>

+    

+    <Values name="LMPVersion" type="enum">

+        <Value val="0x00">Bluetooth Core Specification 1.0B</Value>

+        <Value val="0x01">Bluetooth Core Specification 1.1</Value>

+        <Value val="0x02">Bluetooth Core Specification 1.2</Value>

+        <Value val="0x03">Bluetooth Core Specification 2.0</Value>

+        <Value val="0x04">Bluetooth Core Specification 2.1</Value>

+        <Value val="0x05">Bluetooth Core Specification 3.0</Value>

+	<Value val="0x06">Bluetooth Core Specification 4.0</Value>

+        <!-- 

+	Taken from the following URL:

+	https://www.bluetooth.org/foundry/assignnumb/document/link_manager_protocol

+-->

+    </Values>

+    

+    <Values name="CompID" type="enum">

+        <Value val="0">Ericsson Technology Licensing</Value>

+        <Value val="1">Nokia Mobile Phones</Value>

+        <Value val="2">Intel Corp.</Value>

+        <Value val="3">IBM Corp.</Value>

+        <Value val="4">Toshiba Corp.</Value>

+        <Value val="5">3Com</Value>

+        <Value val="6">Microsoft</Value>

+        <Value val="7">Lucent</Value>

+        <Value val="8">Motorola</Value>

+        <Value val="9">Infineon Technologies AG</Value>

+        <Value val="10">Cambridge Silicon Radio</Value>

+        <Value val="11">Silicon Wave</Value>

+        <Value val="12">Digianswer A/S</Value>

+        <Value val="13">Texas Instruments Inc.</Value>

+        <Value val="14">Parthus Technologies Inc.</Value>

+        <Value val="15">Broadcom Corporation</Value>

+        <Value val="16">Mitel Semiconductor</Value>

+        <Value val="17">Widcomm, Inc.</Value>

+        <Value val="18">Zeevo, Inc.</Value>

+        <Value val="19">Atmel Corporation</Value>

+        <Value val="20">Mitsubishi Electric Corporation</Value>

+        <Value val="21">RTX Telecom A/S</Value>

+        <Value val="22">KC Technology Inc.</Value>

+        <Value val="23">Newlogic</Value>

+        <Value val="24">Transilica, Inc.</Value>

+        <Value val="25">Rohde &amp; Schwarz GmbH &amp; Co. KG</Value>

+        <Value val="26">TTPCom Limited</Value>

+        <Value val="27">Signia Technologies, Inc.</Value>

+        <Value val="28">Conexant Systems Inc.</Value>

+        <Value val="29">Qualcomm</Value>

+        <Value val="30">Inventel</Value>

+        <Value val="31">AVM Berlin</Value>

+        <Value val="32">BandSpeed, Inc.</Value>

+        <Value val="33">Mansella Ltd</Value>

+        <Value val="34">NEC Corporation</Value>

+        <Value val="35">WavePlus Technology Co., Ltd.</Value>

+        <Value val="36">Alcatel</Value>

+        <Value val="37">Philips Semiconductors</Value>

+        <Value val="38">C Technologies</Value>

+        <Value val="39">Open Interface</Value>

+        <Value val="40">R F Micro Devices</Value>

+        <Value val="41">Hitachi Ltd</Value>

+        <Value val="42">Symbol Technologies, Inc.</Value>

+        <Value val="43">Tenovis</Value>

+        <Value val="44">Macronix International Co. Ltd.</Value>

+        <Value val="45">GCT Semiconductor</Value>

+        <Value val="46">Norwood Systems</Value>

+        <Value val="47">MewTel Technology Inc.</Value>

+        <Value val="48">ST Microelectronics</Value>

+        <Value val="49">Synopsys</Value>

+        <Value val="50">Red-M (Communications) Ltd</Value>

+        <Value val="51">Commil Ltd</Value>

+        <Value val="52">Computer Access Technology Corporation (CATC)</Value>

+        <Value val="53">Eclipse (HQ Espana) S.L.</Value>

+        <Value val="54">Renesas Technology Corp.</Value>

+        <Value val="55">Mobilian Corporation</Value>

+        <Value val="56">Terax</Value>

+        <Value val="57">Integrated System Solution Corp.</Value>

+        <Value val="58">Matsushita Electric Industrial Co., Ltd.</Value>

+        <Value val="59">Gennum Corporation</Value>

+        <Value val="60">Research In Motion</Value>

+    </Values>

+    

+    <Values name="WhichClock" type="enum">

+        <Value val="0x00">Local Clock</Value>

+        <Value val="0x01">Piconet Clock</Value>

+    </Values>

+    

+    <Values name="BoundaryPacketTypes" type="enum">

+        <Value val="2">Start Flushable</Value>

+        <Value val="1">Continuation</Value>

+        <Value val="0">Start Non-Flushable</Value>

+    </Values>

+    

+    <Values name="LoopbackMode" type="enum">

+        <Value val="0x00">No Loopback mode enabled</Value>

+        <Value val="0x01">Enable Local Loopback</Value>

+        <Value val="0x02">Enable Remote Loopback</Value>

+    </Values>

+    

+    <Values name="BroadcastTypes" type="enum">

+        <Value val="0">None</Value>

+        <Value val="1">Active</Value>

+        <Value val="2">All</Value>

+    </Values>

+    

+    <Values name="BoundaryTypes" type="enum">

+        <Value val="2">Start</Value>

+        <Value val="1">Continuation</Value>

+    </Values>

+    

+    <Values name="ACLSendType" type="enum">

+        <Value val="0">Send File</Value>

+        <Value val="1">Send Text</Value>

+    </Values>

+    

+    <Values name="L2CAPFmt" type="enum">

+        <Value val="0">UPF</Value>

+        <Value val="1">HCI Commander</Value>

+        <Value val="2">L2CAP</Value>

+    </Values>

+    

+    <Values name="FTDSeq" type="seq" size="2">

+        <Value val="0xFF50">FTD_NUM_MASTER_CON</Value>

+        <Value val="0xFF51">FTD_NUM_SLAVE_INSTANCE</Value>

+        <Value val="0xFF52">FTD_ACTIVE_SLEEP_RATIO</Value>

+        <Value val="0xFF53">FTD_HW_VERSION_NUM</Value>

+        <Value val="0xFF54">FTD_SW_VERSION_NUM</Value>

+        <Value val="0xFF55">FTD_CLASS_OF_DEVICE</Value>

+        <Value val="0xFF56">FTD_BT_COUNTRY_CODE</Value>

+        <Value val="0xFF57">FTD_BD_ADDR</Value>

+        <Value val="0xFF58">FTD_FRIENDLY_NAME</Value>

+        <Value val="0xFF5B">FTD_PMD_RESET_REASON</Value>

+        <Value val="0xFF19">FTD_CON_0_CON_STATE</Value>

+        <Value val="0xFF20">FTD_CON_1_HANDLE</Value>

+        <Value val="0xFF21">FTD_CON_1_BD_ADDR</Value>

+        <Value val="0xFF23">FTD_CON_1_CON_STATE</Value>

+        <Value val="0xFF24">FTD_CON_1_LOC_DEV_STATE</Value>

+        <Value val="0xFF60">FTD_CON_1_QUALITY</Value>

+        <Value val="0xFF25">FTD_CON_2_HANDLE</Value>

+        <Value val="0xFF26">FTD_CON_2_BD_ADDR</Value>

+        <Value val="0xFF28">FTD_CON_2_CON_STATE</Value>

+        <Value val="0xFF29">FTD_CON_2_LOC_DEV_STATE</Value>

+        <Value val="0xFF61">FTD_CON_2_QUALITY</Value>

+        <Value val="0xFF2A">FTD_CON_3_HANDLE</Value>

+        <Value val="0xFF2B">FTD_CON_3_BD_ADDR</Value>

+        <Value val="0xFF2D">FTD_CON_3_CON_STATE</Value>

+        <Value val="0xFF2E">FTD_CON_3_LOC_DEV_STATE</Value>

+        <Value val="0xFF62">FTD_CON_3_QUALITY</Value>

+        <Value val="0xFF30">FTD_CON_4_HANDLE</Value>

+        <Value val="0xFF31">FTD_CON_4_BD_ADDR</Value>

+        <Value val="0xFF33">FTD_CON_4_CON_STATE</Value>

+        <Value val="0xFF34">FTD_CON_4_LOC_DEV_STATE</Value>

+        <Value val="0xFF63">FTD_CON_4_QUALITY</Value>

+        <Value val="0xFF35">FTD_CON_5_HANDLE</Value>

+        <Value val="0xFF36">FTD_CON_5_BD_ADDR</Value>

+        <Value val="0xFF38">FTD_CON_5_CON_STATE</Value>

+        <Value val="0xFF39">FTD_CON_5_LOC_DEV_STATE</Value>

+        <Value val="0xFF64">FTD_CON_5_QUALITY</Value>

+        <Value val="0xFF3A">FTD_CON_6_HANDLE</Value>

+        <Value val="0xFF3B">FTD_CON_6_BD_ADDR</Value>

+        <Value val="0xFF3D">FTD_CON_6_CON_STATE</Value>

+        <Value val="0xFF3E">FTD_CON_6_LOC_DEV_STATE</Value>

+        <Value val="0xFF65">FTD_CON_6_QUALITY</Value>

+        <Value val="0xFF40">FTD_CON_7_HANDLE</Value>

+        <Value val="0xFF41">FTD_CON_7_BD_ADDR</Value>

+        <Value val="0xFF43">FTD_CON_7_CON_STATE</Value>

+        <Value val="0xFF44">FTD_CON_7_LOC_DEV_STATE</Value>

+        <Value val="0xFF66">FTD_CON_7_QUALITY</Value>

+        <Value val="0xFF45">FTD_CON_8_HANDLE</Value>

+        <Value val="0xFF46">FTD_CON_8_BD_ADDR</Value>

+        <Value val="0xFF48">FTD_CON_8_CON_STATE</Value>

+        <Value val="0xFF49">FTD_CON_8_LOC_DEV_STATE</Value>

+        <Value val="0xFF67">FTD_CON_8_QUALITY</Value>

+    </Values>

+    

+    <Values name="fm_command_type" type="enum">

+        <Value val="0x00">Write</Value>

+        <Value val="0x01">Read</Value>

+    </Values>

+    

+    <Values name="FTD" type="enum">

+        <Value val="0x0000">COMM_FTD_DATA_FAIL</Value>

+        <Value val="0xFF50">FTD_NUM_MASTER_CON</Value>

+        <Value val="0xFF51">FTD_NUM_SLAVE_INSTANCE</Value>

+        <Value val="0xFF52">FTD_ACTIVE_SLEEP_RATIO</Value>

+        <Value val="0xFF53">FTD_HW_VERSION_NUM</Value>

+        <Value val="0xFF54">FTD_SW_VERSION_NUM</Value>

+        <Value val="0xFF55">FTD_CLASS_OF_DEVICE</Value>

+        <Value val="0xFF56">FTD_BT_COUNTRY_CODE</Value>

+        <Value val="0xFF57">FTD_BD_ADDR</Value>

+        <Value val="0xFF58">FTD_FRIENDLY_NAME</Value>

+        <Value val="0xFF5B">FTD_PMD_RESET_REASON</Value>

+        <Value val="0xFF19">FTD_CON_0_CON_STATE</Value>

+        <Value val="0xFF20">FTD_CON_1_HANDLE</Value>

+        <Value val="0xFF21">FTD_CON_1_BD_ADDR</Value>

+        <Value val="0xFF23">FTD_CON_1_CON_STATE</Value>

+        <Value val="0xFF24">FTD_CON_1_LOC_DEV_STATE</Value>

+        <Value val="0xFF60">FTD_CON_1_QUALITY</Value>

+        <Value val="0xFF25">FTD_CON_2_HANDLE</Value>

+        <Value val="0xFF26">FTD_CON_2_BD_ADDR</Value>

+        <Value val="0xFF28">FTD_CON_2_CON_STATE</Value>

+        <Value val="0xFF29">FTD_CON_2_LOC_DEV_STATE</Value>

+        <Value val="0xFF61">FTD_CON_2_QUALITY</Value>

+        <Value val="0xFF2A">FTD_CON_3_HANDLE</Value>

+        <Value val="0xFF2B">FTD_CON_3_BD_ADDR</Value>

+        <Value val="0xFF2D">FTD_CON_3_CON_STATE</Value>

+        <Value val="0xFF2E">FTD_CON_3_LOC_DEV_STATE</Value>

+        <Value val="0xFF62">FTD_CON_3_QUALITY</Value>

+        <Value val="0xFF30">FTD_CON_4_HANDLE</Value>

+        <Value val="0xFF31">FTD_CON_4_BD_ADDR</Value>

+        <Value val="0xFF33">FTD_CON_4_CON_STATE</Value>

+        <Value val="0xFF34">FTD_CON_4_LOC_DEV_STATE</Value>

+        <Value val="0xFF63">FTD_CON_4_QUALITY</Value>

+        <Value val="0xFF35">FTD_CON_5_HANDLE</Value>

+        <Value val="0xFF36">FTD_CON_5_BD_ADDR</Value>

+        <Value val="0xFF38">FTD_CON_5_CON_STATE</Value>

+        <Value val="0xFF39">FTD_CON_5_LOC_DEV_STATE</Value>

+        <Value val="0xFF64">FTD_CON_5_QUALITY</Value>

+        <Value val="0xFF3A">FTD_CON_6_HANDLE</Value>

+        <Value val="0xFF3B">FTD_CON_6_BD_ADDR</Value>

+        <Value val="0xFF3D">FTD_CON_6_CON_STATE</Value>

+        <Value val="0xFF3E">FTD_CON_6_LOC_DEV_STATE</Value>

+        <Value val="0xFF65">FTD_CON_6_QUALITY</Value>

+        <Value val="0xFF40">FTD_CON_7_HANDLE</Value>

+        <Value val="0xFF41">FTD_CON_7_BD_ADDR</Value>

+        <Value val="0xFF43">FTD_CON_7_CON_STATE</Value>

+        <Value val="0xFF44">FTD_CON_7_LOC_DEV_STATE</Value>

+        <Value val="0xFF66">FTD_CON_7_QUALITY</Value>

+        <Value val="0xFF45">FTD_CON_8_HANDLE</Value>

+        <Value val="0xFF46">FTD_CON_8_BD_ADDR</Value>

+        <Value val="0xFF48">FTD_CON_8_CON_STATE</Value>

+        <Value val="0xFF49">FTD_CON_8_LOC_DEV_STATE</Value>

+        <Value val="0xFF67">TD_CON_8_QUALITY</Value>

+    </Values>

+    

+    <Values name="FTDReason" type="enum">

+        <Value val="0">Not Activated</Value>

+        <Value val="1">Not Supported</Value>

+        <Value val="2">Not Available</Value>

+    </Values>

+    

+    <Values name="SCO_generation_type" type="enum">

+        <Value val="0">Off</Value>

+        <Value val="1">Loopback</Value>

+        <Value val="2">Codec</Value>

+        <Value val="3">Pattern Sine</Value>

+        <Value val="4">Pattern Byte Saw Tooth</Value>

+        <Value val="5">Pattern Packet Saw Tooth</Value>

+    </Values>

+    

+    <Values name="SDIO Dest CMD52" type="enum">

+        <Value val="0">Legacy mode</Value>

+        <Value val="1">Shared SDIO, BT</Value>

+        <Value val="2">Shared SDIO, WLAN</Value>

+    </Values>

+    

+    <Values name="SDIO Dest CMD53" type="enum">

+        <Value val="0">Legacy mode</Value>

+        <Value val="1">Shared SDIO, BT</Value>

+        <Value val="2">Shared SDIO, WLAN</Value>

+    </Values>

+    

+    <Values name="SDIO Commands" type="enum">

+        <Value val="0">CMD0</Value>

+        <Value val="1">CMD3</Value>

+        <Value val="2">CMD5</Value>

+        <Value val="3">CMD7</Value>

+        <Value val="4">CMD15</Value>

+    </Values>

+                       

+    <Values name="TrueFalse" type="enum">

+        <Value val="False"></Value>

+        <Value val="True"></Value>

+    </Values>

+

+    <Values name="Wibree_activity" type="enum">

+	<Value val="0x00">Advertise</Value>

+	<Value val="0x01">Scan</Value>

+	<Value val="0x02">Connect</Value>

+	<Value val="0x03">Connection</Value>

+    </Values>

+

+	<Values name="5500_clock_sources" type="enum">

+		<Value val="0x00">FREF</Value>

+		<Value val="0x01">TCXO (5500 Only)</Value>

+    </Values>

+	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+	<!--  DTST Muxing		                                       --> 

+	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+	<Values name="dtst_Module_sel" type="enum">

+  	<Value val="0x0">DRX_BUS[31:0]</Value> 

+  	<Value val="0x1">DTX_BUS[15:0]</Value> 

+  	<Value val="0x2">DRPb_BUS[31:0]</Value> 

+  	<Value val="0x3">SCR_BUS[15:0]</Value> 

+  	<Value val="0x4">OCP_IC_BUS[15:0]</Value> 

+  	</Values>

+ 	<Values name="test_clk_mux_sel" type="enum">

+  	<Value val="0x0">DRX_CKVD48</Value> 

+  	<Value val="0x1">DRX_CKVD96</Value> 

+  	<Value val="0x2">DRX_CKVD240</Value> 

+  	<Value val="0x3">DRX_5M_CLK</Value> 

+  	<Value val="0x4">DRX_CKVD96_TDM</Value> 

+  	<Value val="0x5">DRX_CKVD240_TDM</Value> 

+  	<Value val="0x6">DRX_5M_CLK_TDM</Value> 

+  	<Value val="0x7">DTX_CKVD96_192</Value> 

+  	<Value val="0x8">DTX_CKVD96_192_TDM</Value> 

+  	<Value val="0x9">DLO_DEBUG_CKR</Value> 

+  	<Value val="0xa">SCR_DEBUG_CLK</Value> 

+  	<Value val="0xb">OCP_CLK</Value> 

+  	<Value val="0xf">NO_CLOCK</Value> 

+  	</Values> 

+	<Values name="shift_select" type="enum">

+  	<Value val="0x0">No_shift</Value> 

+  	<Value val="0x1">shift_by_1</Value> 

+  	<Value val="0x2">shift_by_2</Value> 

+  	<Value val="0x3">shift_by_3</Value> 

+  	<Value val="0x4">shift_by_4</Value> 

+  	<Value val="0x5">shift_by_4</Value> 

+  	<Value val="0x6">shift_by_5</Value> 

+  	<Value val="0x7">shift_by_6</Value> 

+  	<Value val="0x8">shift_by_7</Value> 

+  	<Value val="0x9">shift_by_8</Value> 

+  	<Value val="0xa">shift_by_9</Value> 

+  	<Value val="0xb">shift_by_10</Value> 

+  	<Value val="0xc">shift_by_11</Value> 

+  	<Value val="0xd">shift_by_12</Value> 

+  	<Value val="0xe">shift_by_13</Value> 

+  	<Value val="0xf">shift_by_14</Value> 

+  	<Value val="0x10">shift_by_15</Value> 

+   	</Values>

+  <Values name="pins_group_select" type="enum">

+    <Value val="0x0">IO_pins</Value>

+    <Value val="0x1">External_Memory_pins</Value>

+  </Values>

+	<Values name="test_dtst_enable" type="enum">

+  	<Value val="0">Disable_DTST</Value> 

+  	<Value val="1">Enable_DTST</Value> 

+  	</Values>

+	<Values name="test_mirror_enable" type="enum">

+  	<Value val="0">mirror_Disable</Value> 

+  	<Value val="1">mirror_Enable</Value> 

+  	</Values>

+	<Values name="test_apll_clk_select" type="enum">

+  	<Value val="0">DTST_clk_Selected</Value> 

+  	<Value val="1">APLL_clk_Selected</Value> 

+  	</Values>

+    <Values name="TestBusOverrideSelect" type="enum">

+  	<Value val="0">PhyDebugBus</Value> 

+  	<Value val="1">UserOverridePattern</Value> 

+  	<Value val="2">ToggelPattern_FFFF_0000</Value> 

+  	</Values>	

+  	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+	<!--  DTST Recording 		                                       --> 

+	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+	<Values name="DTST_Mem_Mode" type="enum">

+  	<Value val="0x0">Recording</Value> 

+  	<Value val="0x1">Random_Access</Value> 

+  	<Value val="0x2">Continuous_Access</Value> 

+  	</Values>

+ 	<Values name="DTST_Mem_Enable" type="enum">

+ 	<Value val="0">Disable_Mem </Value> 

+  	<Value val="1">Enable_Mem </Value> 

+   	</Values> 

+	<Values name="DTST_Enable" type="enum">

+ 	<Value val="0">Disable_Dtst </Value> 

+  	<Value val="1">Enable_Dtst </Value> 

+   	</Values> 

+	<Values name="DTST_Mem_Max_Use" type="enum">

+  	<Value val="0x1">1_KByte</Value> 

+  	<Value val="0x2">2_KByte</Value> 

+  	<Value val="0x3">3_KByte</Value> 

+  	<Value val="0x4">4_KByte</Value> 

+  	</Values>

+	<Values name="DTST_Mem_Step_Size" type="enum">

+  	<Value val="0">2_Byte</Value> 

+  	<Value val="1">4_Byte</Value> 

+  	</Values>

+	<Values name="DTST_Mem_Word_Select" type="enum">

+  	<Value val="0">16_LSB</Value> 

+  	<Value val="1">16_MSB</Value> 

+  	</Values>

+	<Values name="DTST_Mem_Offset" type="enum">

+  	</Values>

+    <Values name="DTST_Mem_Wrap_Enable" type="enum">

+  	<Value val="0">Disable_Mem_Wrap </Value> 

+  	<Value val="1">Enable_Mem_Wrap </Value> 

+  	</Values>	

+	<Values name="DTST_sleep_time" type="enum">

+  	</Values>

+	<Values name="DTST_Mem_Reading_Enable" type="enum">

+ 	<Value val="0">Disable_Mem </Value> 

+  	<Value val="1">Enable_Mem </Value> 

+   	</Values>

+	<Values name="DTST_filename" type="enum">

+  	</Values>

+    	

+	<!--  *******************************************************--> 

+    <Values name="SleepType" type="enum">

+        <Value val="0">None</Value>

+        <Value val="1">HCILL</Value>

+        <Value val="2">PALAU</Value>

+    </Values>

+    

+    <Values name="IPType" type="enum">

+        <Value val="0">TCP Client</Value>

+        <Value val="1">TCP Server</Value>

+        <Value val="2">UDP</Value>

+    </Values>

+    

+    <Values name="WriteFileType" type="enum">

+        <Value val="0">Create</Value>

+        <Value val="1">Append</Value>

+    </Values>

+    

+     <Values name="ParallelPortOffsets" type="enum">

+        <Value val="0">Port 0x0378</Value>

+        <Value val="1">Port 0x0379</Value>

+        <Value val="2">Port 0x037a</Value>

+    </Values>

+    

+    <Values name="HCIEvents" type="enum">

+        <Value code="0x01" val="HCI_Inquiry_Complete_Event" />

+        <Value code="0x02" val="HCI_Inquiry_Result_Event" />

+        <Value code="0x03" val="HCI_Connection_Complete_Event" />

+        <Value code="0x04" val="HCI_Connection_Request_Event" />

+        <Value code="0x05" val="HCI_Disconnection_Complete_Event" />

+        <Value code="0x06" val="HCI_Authentication_Complete_Event" />

+        <Value code="0x07" val="HCI_Remote_Name_Request_Complete_Event" />

+        <Value code="0x08" val="HCI_Encryption_Change_Event" />

+        <Value code="0x09" val="HCI_Change_Connection_Link_Key_Complete_Event" />

+        <Value code="0x0A" val="HCI_Master_Link_Key_Complete_Event" />

+        <Value code="0x0B" val="HCI_Read_Remote_Supported_Features_Complete_Event" />

+        <Value code="0x0C" val="HCI_Read_Remote_Version_Information_Complete_Event" />

+        <Value code="0x0D" val="HCI_QoS_Setup_Complete_Event" />

+        <Value code="0x0E" val="HCI_Command_Complete_Event" />

+        <Value code="0x0F" val="HCI_Command_Status_Event" />

+        <Value code="0x10" val="HCI_Hardware_Error_Event" />

+        <Value code="0x11" val="HCI_Flush_Occurred_Event" />

+        <Value code="0x12" val="HCI_Role_Change_Event" />

+        <Value code="0x13" val="HCI_Number_Of_Completed_Packets_Event" />

+        <Value code="0x14" val="HCI_Mode_Change_Event" />

+        <Value code="0x15" val="HCI_Return_Link_Keys_Event" />

+        <Value code="0x16" val="HCI_PIN_Code_Request_Event" />

+        <Value code="0x17" val="HCI_Link_Key_Request_Event" />

+        <Value code="0x18" val="HCI_Link_Key_Notification_Event" />

+        <Value code="0x19" val="HCI_Loopback_Command_Event" />

+        <Value code="0x1A" val="HCI_Data_Buffer_Overflow_Event" />

+        <Value code="0x1B" val="HCI_Max_Slots_Change_Event" />

+        <Value code="0x1C" val="HCI_Read_Clock_Offset_Complete_Event" />

+        <Value code="0x1D" val="HCI_Connection_Packet_Type_Changed_Event" />

+        <Value code="0x1E" val="HCI_QoS_Violation_Event" />

+        <Value code="0x20" val="HCI_Page_Scan_Repetition_Mode_Change_Event" />

+        <Value code="0x21" val="HCI_Flow_Specification_Complete_Event" />

+        <Value code="0x22" val="HCI_Inquiry_Result_with_RSSI_Event" />

+        <Value code="0x23" val="HCI_Read_Remote_Extended_Features_Complete_Event" />

+        <Value code="0x2C" val="HCI_Synchronous_Connection_Complete_Event" />

+        <Value code="0x2D" val="HCI_Synchronous_Connection_Changed_Event" />

+        <Value code="0x2E" val="HCI_Sniff_Subrate_Changed_Event" />

+        <Value code="0x2F" val="HCI_Extended_Inquiry_Result_Event" />

+        <Value code="0x30" val="HCI_Refresh_Encryption_Key_Event" />

+        <Value code="0x31" val="HCI_IO_Capability_Request_event" />

+        <Value code="0x32" val="HCI_IO_Capability_Response_event" />

+        <Value code="0x33" val="HCI_User_Confirmation_Request_event" />

+        <Value code="0x34" val="HCI_User_Passkey_Request_event" />

+        <Value code="0x35" val="HCI_Remote_Oob_request_event" />

+        <Value code="0x36" val="HCI_Simple_Pairing_complete_event" />

+        <Value code="0x37" val="HCI_Remote_Oob_Response_event" />-->

+        <Value code="0x38" val="HCI_Link_Supervision_Timeout_Change_Event" />

+        <Value code="0x39" val="HCI_Enhanced_Flush_Occured_Event" />

+        <Value code="0x3A" val="HCI_Sniff_Request_Event" />

+		<Value code="0x42" val="Hci_LE_Advertising_Packet_Report_Event" />

+		<Value code="0x44" val="Hci_LE_Remote_LL_Connection_Request_Event" />

+		<Value code="0x45" val="Hci_LE_LL_Connection_Created_Event" />

+		<Value code="0x46" val="Hci_LE_LL_Connection_Termination_Event" />

+		<Value code="0x49" val="Hci_LE_Number_of_Completed_Packets_Event" />

+		<Value code="0x4B" val="Hci_LE_Encryption_Requested_Event" />

+		<Value code="0x4C" val="Hci_LE_Encrypted_Event" />

+        <Value code="0xF0" val="HCI_FM_Event" />

+		<Value code="0xF1" val="HCI_GPS_Channel_9_event" />

+		<Value code="0xF2" val="HCI_LE_Received_Data_event" />

+		<Value code="0xFD" val="HCI_BLE_Event" />

+    </Values>

+    

+    <Values name="MsgBoxType" type="enum">

+        <Value val="0">OK button</Value>

+        <Value val="1">OK and Cancel buttons</Value>

+        <Value val="2">Abort, Retry and Ignore buttons</Value>

+        <Value val="3">Yes, No and Cancel buttons</Value>

+        <Value val="4">Yes and No buttons</Value>

+        <Value val="5">Retry and Cancel buttons</Value>

+    </Values>

+    

+    <Values name="LinkType" type="enum">

+        <Value val="0x00">SCO</Value>

+        <Value val="0x01">ACL</Value>

+        <Value val="0x02">eSCO</Value>

+    </Values>

+    

+    <Values name="HardwareErrorCodes" type="enum">

+        <!-- General Hardware Error Codes -->

+        <Value val="0x01">No Buffers Command</Value>

+        <Value val="0x02">No Buffers ACL Data</Value>

+        <Value val="0x03">No Buffers SCO Data</Value>

+        <Value val="0x06">Bad Type</Value>

+        <Value val="0x07">Bad Len</Value>

+        <Value val="0x09">Overrun</Value>

+        <Value val="0x0A">Parity</Value>

+        <Value val="0x0B">Framing</Value>

+        <Value val="0x0C">Break</Value>

+        <Value val="0x0D">Radio Event</Value>

+        

+        <!-- Palau Hardware Error Codes -->

+        <Value val="0x05">Palau Error: Ram Area Full</Value>

+        <!--Value val="0x06">Palau Error: Radio Event</Value>  -->

+        <!--Value val="0x07">Palau Error: Interupt</Value>     -->

+        <Value val="0x23">Palau Error: H4 Corrupt Data</Value>

+        <Value val="0x55">Palau Error: About To Reset</Value>

+    </Values>

+    

+    <Values name="Mode" type="enum">

+        <Value val="0x00">Active</Value>

+        <Value val="0x01">Hold</Value>

+        <Value val="0x02">Sniff</Value>

+        <Value val="0x03">Park</Value>

+    </Values>

+    

+    <Values name="KeyType" type="enum">

+        <Value val="0x00">Combination Key</Value>

+        <Value val="0x01">Local Unit Key</Value>

+        <Value val="0x02">Remote Unit Key</Value>

+        <Value val="0x03">Debug combination key</Value>

+        <Value val="0x04">Unauthenticated key</Value>

+        <Value val="0x05">Authenticated key</Value>

+        <Value val="0x06">Changed combination key</Value>

+    </Values>

+    

+    <Values name="MaxSlots" type="enum">

+        <Value val="0x01">1</Value>

+        <Value val="0x03">3</Value>

+        <Value val="0x05">5</Value>

+    </Values>

+    

+    <Values name="AirMode" type="enum">

+        <Value val="0x00">µ-law log</Value>

+        <Value val="0x01">A-law log</Value>

+        <Value val="0x02">CVSD</Value>

+        <Value val="0x03">Transparent Data</Value>

+    </Values>

+    

+    <Values name="EDR_Mode" type="enum">

+        <Value val="0x00">De-assert</Value>

+        <Value val="0x01">Show real value</Value>

+    </Values>

+    

+    <Values name="L2cap_len_flags" type="enum">

+        <Value val="0x00">Set l2cap positive length in the payload header</Value>

+        <Value val="0x01">Set l2cap zero length in the payload header</Value>

+    </Values>

+    

+    <Values name="PLL_band" type="enum">

+        <Value val="0x00">40MHz output (Europe)</Value>

+        <Value val="0x01">48MHz output (Japan)</Value>

+        <Value val="0xFF">Don't change</Value>

+    </Values>

+    

+    <Values name="External_PA_MODE_CMD_1_Select" type="enum">

+        <Value val="0x04">BT_FUNC4</Value>

+        <Value val="0xFF">Don't change</Value>

+    </Values>

+    

+    <Values name="External_PA_MODE_CMD_2_Select" type="enum">

+        <Value val="0x01">BT_FUNC1</Value>

+        <Value val="0x07">BT_FUNC7</Value>

+    </Values>

+    

+    <Values name="External_PA_MODE_PA_EN_Select" type="enum">

+        <Value val="0x02">BT_FUNC2</Value>

+        <Value val="0x05">BT_FUNC5</Value>

+    </Values>

+    

+    <Values name="External_PA_MODE_nPA_EN_Select" type="enum">

+        <Value val="0x03">BT_FUNC3</Value>

+        <Value val="0x06">BT_FUNC6</Value>

+    </Values>

+    

+    <Values name="WLAN_TX_RX_MODE" type="enum">

+        <Value val="0x00">Disable</Value>

+        <Value val="0x01">Immediate shutdown</Value>

+        <Value val="0x02">Shutdown next packet</Value>

+        <Value val="0xFF">Do not change</Value>	

+    </Values>

+    

+    <Values name="PinName_btip" type="enum">

+        <Value val="0x01">AUD_IN</Value>

+        <Value val="0x02">AUD_OUT</Value>

+        <Value val="0x03">AUD_CLK</Value>

+        <Value val="0x04">AUD_FSYNC</Value>

+        <Value val="0x06">TX_HCI</Value>

+        <Value val="0x07">RX_HCI</Value>

+        <Value val="0x08">CTS_HCI</Value>

+        <Value val="0x09">RTS_HCI</Value>

+        <Value val="0x0a">BT_FUNC_1</Value>

+        <Value val="0x0b">BT_FUNC_2</Value>

+        <Value val="0x0c">BT_FUNC_3</Value>

+        <Value val="0x0d">BT_FUNC_4</Value>

+        <Value val="0x0e">BT_FUNC_5</Value>

+        <Value val="0x0f">BT_FUNC_6</Value>

+        <Value val="0x10">BT_FUNC_7</Value>

+        <Value val="0x11">BT_FUNC_8</Value>

+        <Value val="0x12">BT_FUNC_9</Value>

+        <Value val="0x13">BT_FUNC_10</Value>

+    </Values>

+    

+    <Values name="TX_HCI_btip" type="enum">

+        <Value val="0x00">tx_hci</Value>

+        <Value val="0x01">armio_out12</Value>

+        <Value val="0x02">tx_hci</Value>

+        <Value val="0x04">espi_do</Value>

+    </Values>

+    

+    <Values name="RX_HCI_btip" type="enum">

+        <Value val="0x00">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0x01">armio_out13</Value>

+        <Value val="0x02">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0x03">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0x04">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0x05">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0x06">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0x07">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0x08">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0x09">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0xa">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0xb">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0xc">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0xd">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0xe">rx_hci(input)/espi_di(input)</Value>

+        <Value val="0xf">rx_hci(input)/espi_di(input)</Value>

+    </Values>

+    

+    <Values name="CTS_HCI_btip" type="enum">

+        <Value val="0x00">cts_hci(unput)/espi_cs(input)</Value>

+        <Value val="0x01">armio_out14</Value>

+        <Value val="0x02">debug_2</Value>

+        <Value val="0x03">cts_hci(input)/espi_cs(input)</Value>

+        <Value val="0x04">cts_hci(input)/espi_cs(input)</Value>

+        <Value val="0x05">cts_hci(input)/espi_cs(input)</Value>

+        <Value val="0x06">cts_hci(input)/espi_cs(input)</Value>

+        <Value val="0x07">debug_8</Value>

+        <Value val="0x08">cts_hci(input)/espi_cs(input)</Value>

+        <Value val="0x09">cts_hci(input)/espi_cs(input)</Value>

+        <Value val="0xa">cts_hci(input)/espi_cs(input)</Value>

+        <Value val="0xb">cts_hci(input)/espi_cs(input)</Value>

+        <Value val="0xc">cts_hci(input)/espi_cs(input)</Value>

+        <Value val="0xd">cts_hci(input)/espi_cs(input)</Value>

+        <Value val="0xe">cts_hci(input)/espi_cs(input)</Value>

+        <Value val="0xf">cts_hci(input)/espi_cs(input)</Value>

+        

+    </Values>

+    

+    <Values name="RTS_HCI_btip" type="enum">

+        <Value val="0x00">rts_hci</Value>

+        <Value val="0x01">armio_out15</Value>

+        <Value val="0x02">debug_3</Value>

+        <Value val="0x03">rts_hci</Value>

+        <Value val="0x04">espi_irq</Value>

+        <Value val="0x07">drp_tst_clk</Value>

+    </Values>

+    

+    <Values name="AUD_IN_btip" type="enum">

+        <Value val="0x00">aud_in</Value>

+        <Value val="0x01">armio_out(0)</Value>

+        <Value val="0x07">debug_12</Value>

+    </Values>

+    

+    <Values name="AUD_OUT_btip" type="enum">

+        <Value val="0x00">aud_out</Value>

+        <Value val="0x01">armio_out(1)</Value>

+        <Value val="0x07">debug_11</Value>

+    </Values>

+    

+    <Values name="AUD_CLK_btip" type="enum">

+        <Value val="0x00">aud_clk</Value>

+        <Value val="0x01">armio_out(16)</Value>

+        <Value val="0x07">debug_10</Value>

+    </Values>

+    

+    <Values name="AUD_FSYNC_btip" type="enum">

+        <Value val="0x00">aud_fsync</Value>

+        <Value val="0x01">armio_out(17)</Value>

+        <Value val="0x07">debug_9</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_1_btip" type="enum">

+        <Value val="0x00">armio_out1 -as host wkup</Value>

+        <Value val="0x01">wlan1</Value>

+        <Value val="0x02">exp_pa_cmd2</Value>

+        <Value val="0x03">spi_clk</Value>

+        <Value val="0x05">tx_bypass</Value>

+        <Value val="0x07">debug_6</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_2_btip" type="enum">

+        <Value val="0x00">armio_out2 -as BT wkup</Value>

+        <Value val="0x01">wlan0</Value>

+        <Value val="0x02">ext_pa_en</Value>

+        <Value val="0x03">tx_dbg</Value>

+        <Value val="0x05">tx_wire_3</Value>

+        <Value val="0x07">debug_5</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_3_btip" type="enum">

+        <Value val="0x00">armio_out(3)</Value>

+        <Value val="0x02">next_pa_en</Value>

+        <Value val="0x03">wlan1</Value>

+        <Value val="0x04">tx_dbg</Value>

+        <Value val="0x05">tx_wire_2</Value>

+        <Value val="0x06">rx_bypass(input)</Value>

+        <Value val="0x07">debug_4</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_4_btip" type="enum">

+        <Value val="0x00">armio_out4</Value>

+        <Value val="0x01">wibree_gpio5</Value>

+        <Value val="0x02">tx_dbg</Value>

+        <Value val="0x03">exp_pa_cmd1</Value>

+        <Value val="0x04">tx_bypass</Value> 

+        <Value val="0x05">rx_bypass(input)</Value>

+        <Value val="0x06">wlan0</Value>

+        <Value val="0x07">debug_3</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_5_btip" type="enum">

+        <Value val="0x00">armio_out5 -as sys_sync</Value>

+        <Value val="0x01">wlan1</Value>

+        <Value val="0x02">wlan0</Value>

+        <Value val="0x03">ext_pa_en</Value>

+        <Value val="0x04">rts_bypass</Value>

+        <Value val="0x05">wlan2</Value>

+        <Value val="0x06">wibree_gpio_2</Value>

+        <Value val="0x07">debug_2</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_6_btip" type="enum">

+        <Value val="0x00">armio_out(6)</Value>

+        <Value val="0x01">tx_dbg</Value>

+        <Value val="0x02">wlan1</Value>

+        <Value val="0x03">next_pa_en</Value>

+        <Value val="0x04">cts_bypass(input)</Value>

+        <Value val="0x05">tx_wire_1</Value>

+        <Value val="0x06">sda</Value>

+        <Value val="0x07">debug_1</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_7_btip" type="enum">

+        <Value val="0x00">armio_out(7)</Value>

+        <Value val="0x01">wibree_gpio(9)(input)</Value>

+        <Value val="0x02">wlan3(input)</Value>

+        <Value val="0x03">exp_pa_cmd2</Value>

+        <Value val="0x04">rx_bypass(input)</Value>

+        <Value val="0x05">tx_wire_4</Value>

+        <Value val="0x06">scl</Value>

+        <Value val="0x07">debug_0</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_8_btip" type="enum">

+        <Value val="0x00">armio_out8</Value>

+        <Value val="0x01">wibree_gpio8</Value>

+        <Value val="0x02">wlan2</Value>

+        <Value val="0x03">wlan0</Value>

+        <Value val="0x04">scl</Value>

+        <Value val="0x06">tx_dbg</Value>

+        <Value val="0x07">debug_7</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_9_btip" type="enum">

+        <Value val="0x00">armio_out9</Value>

+        <Value val="0x01">wibree_gpio7</Value>

+        <Value val="0x02">tx_dbg</Value>

+        <Value val="0x03">wlan3(input)</Value>

+        <Value val="0x07">debug_13</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_10_btip" type="enum">

+        <Value val="0x00">armio_out10</Value>

+        <Value val="0x01">tx_dbg</Value>

+        <Value val="0x03">wlan2</Value>

+        <Value val="0x07">debug_14</Value>

+    </Values>

+    

+    <Values name="PinName_orca" type="enum">

+        <Value val="0x01">TX_HCI</Value>

+        <Value val="0x02">RX_HCI</Value>

+        <Value val="0x03">CTS_HCI</Value>

+        <Value val="0x04">RTS_HCI</Value>

+        <Value val="0x05">AUD_IN</Value>

+        <Value val="0x06">AUD_OUT</Value>

+        <Value val="0x07">AUD_CLK</Value>

+        <Value val="0x08">AUD_FSYNC</Value>

+        <Value val="0x09">BT_FUNC_1</Value>

+        <Value val="0x0a">BT_FUNC_2</Value>

+        <Value val="0x0b">TX_DBG</Value>

+        <Value val="0x0c">BT_FUNC_4</Value>

+        <Value val="0x0d">BT_FUNC_6</Value>

+        <Value val="0x0e">BT_FUNC_7</Value>

+        <Value val="0x0f">CLK_REQ_OUT</Value>

+        <Value val="0x10">FM_IRQ</Value>

+        <Value val="0x11">FM_SCL</Value>

+        <Value val="0x12">FM_SDA</Value>

+        <Value val="0x13">FM_I2S_DI</Value>

+        <Value val="0x14">FM_I2S_DO</Value>

+        <Value val="0x15">FM_I2S_CLK</Value>

+        <Value val="0x16">FM_I2S_WS</Value>

+    </Values>

+    

+    <Values name="TX_HCI_orca" type="enum">

+        <Value val="0x00">tx_hci</Value>

+        <Value val="0x04">fm_dtst_clk</Value>

+        <Value val="0x05">top_dbg7</Value>

+        <Value val="0x06">fm_dtst0</Value>

+        <Value val="0x07">bt_dbg7</Value>

+    </Values>

+    

+    <Values name="RX_HCI_orca" type="enum">

+        <Value val="0x00">rx_hci (input)</Value>

+        <Value val="0x04">fm_dtst4</Value>

+        <Value val="0x05">top_dbg8</Value>

+        <Value val="0x06">fm_dtst1</Value>

+        <Value val="0x07">bt_dbg9</Value>

+    </Values>

+    

+    <Values name="CTS_HCI_orca" type="enum">

+        <Value val="0x00">cts_hci (input)</Value>

+        <Value val="0x01">bt_func6</Value>

+        <Value val="0x02">fm_dtst9</Value>

+        <Value val="0x03">bt_func1</Value>

+        <Value val="0x04">fm_dtst_13</Value>

+        <Value val="0x05">top_dbg15</Value>

+        <Value val="0x06">fm_dtst2</Value>

+        <Value val="0x07">bt_dbg_clk</Value>

+    </Values>

+    

+    <Values name="RTS_HCI_orca" type="enum">

+        <Value val="0x00">rts_hci</Value>

+        <Value val="0x03">bt_func3</Value>

+        <Value val="0x05">top_dbg10</Value>

+        <Value val="0x06">fm_dtst4</Value>

+        <Value val="0x07">bt_dbg10</Value>

+    </Values>

+    

+    <Values name="AUD_IN_orca" type="enum">

+        <Value val="0x00">aud_in </Value>

+        <Value val="0x01">fm_i2s_di (input)</Value>

+        <Value val="0x02">arm_mclk</Value>

+        <Value val="0x03">fm_dtst4</Value>

+        <Value val="0x04">fm_dtst_clk</Value>

+        <Value val="0x05">top_dbg4</Value>

+        <Value val="0x06">fm_dtst12</Value>

+        <Value val="0x07">bt_dbg4</Value>

+    </Values>

+    

+    <Values name="AUD_OUT_orca" type="enum">

+        <Value val="0x00">aud_out			</Value>

+        <Value val="0x01">fm_i2s_do			</Value>

+        <Value val="0x02">arm_mas(1)			</Value>

+        <Value val="0x03">NU			</Value>

+        <Value val="0x04">fm_dtst_clk			</Value>

+        <Value val="0x05">top_dbg6			</Value>

+        <Value val="0x06">fm_dtst9			</Value>

+        <Value val="0x07">bt_dbg6			</Value>

+    </Values>

+    

+    <Values name="AUD_CLK_orca" type="enum">

+        <Value val="0x00">aud_clk			</Value>

+        <Value val="0x01">fm_i2s_clk			</Value>

+        <Value val="0x02">arm_mas(0)			</Value>

+        <Value val="0x03">NU			</Value>

+        <Value val="0x04">NU			</Value>

+        <Value val="0x05">top_dbg0			</Value>

+        <Value val="0x06">fm_dtst10			</Value>

+        <Value val="0x07">bt_dbg0			</Value>

+    </Values>

+    

+    <Values name="AUD_FSYNC_orca" type="enum">

+        <Value val="0x00">aud_fsync			</Value>

+        <Value val="0x01">fm_i2s_ws 			</Value>

+        <Value val="0x02">arm_nmreq			</Value>

+        <Value val="0x03">NU			</Value>

+        <Value val="0x04">fm_dtst4			</Value>

+        <Value val="0x05">top_dbg9			</Value>

+        <Value val="0x06">fm_dtst11			</Value>

+        <Value val="0x07">bt_dbg9			</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_1_orca" type="enum">

+        <Value val="0x00">hci_clk (input)			</Value>

+        <Value val="0x01">bt_func1			</Value>

+        <Value val="0x02">fm_i2s_do			</Value>

+        <Value val="0x03">NU			</Value>

+        <Value val="0x04">NU			</Value>

+        <Value val="0x05">top_dbg1			</Value>

+        <Value val="0x06">fm_dtst5			</Value>

+        <Value val="0x07">bt_dbg1			</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_2_orca" type="enum">

+        <Value val="0x00">bt_func2			</Value>

+        <Value val="0x01">arm_nwait			</Value>

+        <Value val="0x02">fm_i2s_do			</Value>

+        <Value val="0x03">NU			</Value>

+        <Value val="0x04">NU			</Value>

+        <Value val="0x05">top_dbg2			</Value>

+        <Value val="0x06">fm_dtst6			</Value>

+        <Value val="0x07">bt_dbg2			</Value>

+    </Values>

+    

+    <Values name="TX_DBG_orca" type="enum">

+        <Value val="0x00">bt_func3 tx_dbg			</Value>

+        <Value val="0x01">arm_nexec			</Value>

+        <Value val="0x02">fm_i2s_do			</Value>

+        <Value val="0x03">fm_dtst_clk			</Value>

+        <Value val="0x04">tx_dbg			</Value>

+        <Value val="0x05">top_dbg3			</Value>

+        <Value val="0x06">fm_dtst7			</Value>

+        <Value val="0x07">bt_dbg3			</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_4_orca" type="enum">

+        <Value val="0x00">bt_func4 			</Value>

+        <Value val="0x01">NU			</Value>

+        <Value val="0x02">ext_be_0			</Value>

+        <Value val="0x03">fm_i2s_do			</Value>

+        <Value val="0x04">NU (Default)			</Value>

+        <Value val="0x05">top_dbg4			</Value>

+        <Value val="0x06">fm_dtst12			</Value>

+        <Value val="0x07">bt_dbg4			</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_6_orca" type="enum">

+        <Value val="0x00">bt_func6			</Value>

+        <Value val="0x01">tx_dbg			</Value>

+        <Value val="0x02">ext_be_1			</Value>

+        <Value val="0x03">NU (Default)			</Value>

+        <Value val="0x04">NU			</Value>

+        <Value val="0x05">top_dbg6			</Value>

+        <Value val="0x06">fm_dtst14			</Value>

+        <Value val="0x07">bt_dbg6			</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_7_orca" type="enum">

+        <Value val="0x00">bt_func7			</Value>

+        <Value val="0x01">NU			</Value>

+        <Value val="0x02">fm_i2s_do			</Value>

+        <Value val="0x03">NU (Default)			</Value>

+        <Value val="0x04">NU			</Value>

+        <Value val="0x05">top_dbg7			</Value>

+        <Value val="0x06">fm_dtst15			</Value>

+        <Value val="0x07">bt_dbg7			</Value>

+    </Values>

+    

+    <Values name="CLK_REQ_OUT_orca" type="enum">

+        <Value val="0x00">clk_req_out			</Value>

+        <Value val="0x01">tx_dbg			</Value>

+        <Value val="0x02">arm_nwait			</Value>

+        <Value val="0x03">bt_func5			</Value>

+        <Value val="0x04">fm_dtst3			</Value>

+        <Value val="0x05">top_dbg5			</Value>

+        <Value val="0x06">fm_dtst8			</Value>

+        <Value val="0x07">bt_dbg5			</Value>

+    </Values>

+    

+    <Values name="FM_IRQ_orca" type="enum">

+        <Value val="0x00">fm_irq			</Value>

+        <Value val="0x01">arm_nemu1			</Value>

+        <Value val="0x02">bt_func3			</Value>

+        <Value val="0x03">bt_func10			</Value>

+        <Value val="0x04">bt_func4			</Value>

+        <Value val="0x05">top_dbg13			</Value>

+        <Value val="0x06">fm_dtst2			</Value>

+        <Value val="0x07">bt_dbg13			</Value>

+    </Values>

+    

+    <Values name="FM_SCL_orca" type="enum">

+        <Value val="0x00">fm_scl 			</Value>

+        <Value val="0x01">arm_nopc			</Value>

+        <Value val="0x02">bt_func1			</Value>

+        <Value val="0x03">bt_func8			</Value>

+        <Value val="0x04">bt_func7			</Value>

+        <Value val="0x05">top_dbg11			</Value>

+        <Value val="0x06">fm_dtst0			</Value>

+        <Value val="0x07">bt_dbg11			</Value>

+    </Values>

+    

+    <Values name="FM_SDA_orca" type="enum">

+        <Value val="0x00">fm_sda			</Value>

+        <Value val="0x01">arm_nemu0			</Value>

+        <Value val="0x02">bt_func2			</Value>

+        <Value val="0x03">bt_func9			</Value>

+        <Value val="0x04">bt_func6			</Value>

+        <Value val="0x05">top_dbg12			</Value>

+        <Value val="0x06">fm_dtst1			</Value>

+        <Value val="0x07">bt_dbg12			</Value>

+    </Values>

+    

+    <Values name="FM_I2S_DI_orca" type="enum">

+        <Value val="0x00">fm_i2s_di (input)			</Value>

+        <Value val="0x01">fm_i2s_do			</Value>

+        <Value val="0x02">bt_func4			</Value>

+        <Value val="0x03">bt_func8			</Value>

+        <Value val="0x04">tdo			</Value>

+        <Value val="0x05">top_dbg14			</Value>

+        <Value val="0x06">fm_dtst_clk			</Value>

+        <Value val="0x07">bt_dbg14			</Value>

+    </Values>

+    

+    <Values name="FM_I2S_DO_orca" type="enum">

+        <Value val="0x00">fm_i2s_do			</Value>

+        <Value val="0x01">NU 			</Value>

+        <Value val="0x02">bt_func7			</Value>

+        <Value val="0x03">fm_dtst4			</Value>

+        <Value val="0x04">tck (input)			</Value>

+        <Value val="0x05">top_dbg7			</Value>

+        <Value val="0x06">fm_dtst13			</Value>

+        <Value val="0x07">bt_dbg7			</Value>

+    </Values>

+    

+    <Values name="FM_I2S_CLK_orca" type="enum">

+        <Value val="0x00">fm_i2s_clk 			</Value>

+        <Value val="0x01">fm_dtst4			</Value>

+        <Value val="0x02">bt_func5			</Value>

+        <Value val="0x03">bt_func9			</Value>

+        <Value val="0x04">tms (input)			</Value>

+        <Value val="0x05">top_dbg15			</Value>

+        <Value val="0x06">fm_dtst15			</Value>

+        <Value val="0x07">bt_dbg15			</Value>

+    </Values>

+    

+    <Values name="FM_I2S_WS_orca" type="enum">

+        <Value val="0x00">fm_i2s_ws</Value>

+        <Value val="0x01">NU</Value>

+        <Value val="0x02">bt_func6</Value>

+        <Value val="0x03">bt_func10</Value>

+        <Value val="0x04">tdi (input)</Value>

+        <Value val="0x05">top_dbg8</Value>

+        <Value val="0x06">fm_dtst14</Value>

+        <Value val="0x07">bt_dbg8</Value>

+    </Values>

+    

+	    <Values name="PinName_Quattro" type="enum">

+        <Value val="0x01">TX_HCI</Value>

+        <Value val="0x02">RX_HCI</Value>

+        <Value val="0x03">CTS_HCI</Value>

+        <Value val="0x04">RTS_HCI</Value>

+        <Value val="0x05">AUD_IN</Value>

+        <Value val="0x06">AUD_OUT</Value>

+        <Value val="0x07">AUD_CLK</Value>

+        <Value val="0x08">AUD_FSYNC</Value>

+        <Value val="0x09">BT_FUNC_1</Value>

+        <Value val="0x0a">BT_FUNC_2</Value>

+        <Value val="0x0b">BT_FUNC_5</Value>

+        <Value val="0x0c">BT_FUNC_3</Value>

+        <Value val="0x0d">BT_FUNC_6</Value>

+        <Value val="0x0e">BT_FUNC_7</Value>

+        <Value val="0x0f">SB_DATA</Value>

+        <Value val="0x10">SB_CLK</Value>

+		<Value val="0x11">WL_TX</Value>

+        <Value val="0x12">WL_RX</Value>

+        <Value val="0x15">FREF_CLK_REQ</Value>

+        <Value val="0x19">FM_I2S_DI</Value>

+        <Value val="0x1A">FM_I2S_DO</Value>

+        <Value val="0x1b">FM_I2S_CLK</Value>

+        <Value val="0x1c">FM_I2S_WS</Value>

+		<Value val="0x1e">SPI_CSX</Value>

+        <Value val="0x23">WLAN_IRQ</Value>

+        <Value val="0x24">WL_UART_DBG</Value>

+        <Value val="0x25">WL_PAEN_A</Value>

+        <Value val="0x26">WL_PAEN_B</Value>

+        <Value val="0x27">WL_BTH_SW</Value>

+        <Value val="0x28">WL_EXT_LNA_EN</Value>

+		<Value val="0x29">WL_RS232_RX</Value>

+        <Value val="0x2a">WL_RS232_TX</Value>

+        <Value val="0x2b">JTAG_TCK</Value>

+        <Value val="0x2c">JTAG_TMS</Value>

+        <Value val="0x2d">JTAG_TDI</Value>

+		<Value val="0x2e">JTAG_TDO</Value>

+        <Value val="0x2f">GPS_UART_TX</Value>

+        <Value val="0x30">GPS_UART_RX</Value>

+        <Value val="0x31">GPS_SENS_I2C_SCL</Value>

+        <Value val="0x32">GPS_SENS_I2C_SDA</Value>

+		<Value val="0x33">TESTMODE</Value>

+        <Value val="0x34">TCXO_CLK_REQ</Value>

+        <Value val="0x35">GPS_IRQ</Value>

+        <Value val="0x36">GPS_TIMESTAMP</Value>

+        <Value val="0x37">GPS_PPS_OUT</Value>

+		<Value val="0x38">GPS_I2C_UART_SELECT</Value>

+        <Value val="0x39">GPS_EXT_LNA_EN</Value>

+        <Value val="0x3a">GPS_PA_EN</Value>

+        <Value val="0x3b">DC2DC_MODE</Value>

+        <Value val="0x3c">TCXO_SLI_OUT</Value>

+		<Value val="0x3d">WL_SPI_DIN</Value>

+        <Value val="0x3e">WL_SPI_DOUT</Value>

+        <Value val="0x3f">WL_SDIO_D1</Value>

+        <Value val="0x40">WL_SDIO_D2</Value>

+    </Values>

+	

+    <Values name="TX_HCI_Quattro" type="enum">

+        <Value val="0x00">bt_tx_hci</Value>

+        <Value val="0x06">shared[2]</Value>

+    </Values>

+    

+    <Values name="RX_HCI_Quattro" type="enum">

+        <Value val="0x00">bt_rx_hci 			</Value>

+        <Value val="0x06">shared[2]			</Value>

+    </Values>

+    

+    <Values name="CTS_HCI_Quattro" type="enum">

+        <Value val="0x00">bt_cts_hci 			</Value>

+        <Value val="0x01">gps_fm_debug_clk_o			</Value>

+        <Value val="0x03">wlan_drpw_clk			</Value>

+        <Value val="0x05">bt_debug_clk			</Value>

+        <Value val="0x06">shared[4]			</Value>

+    </Values>

+

+    <Values name="RTS_HCI_Quattro" type="enum">

+        <Value val="0x00">bt_rts_hci 			</Value>

+        <Value val="0x06">shared[14]			</Value>

+    </Values>

+

+    

+

+    <Values name="AUD_IN_Quattro" type="enum">

+        <Value val="0x00">ext_pcm_di</Value>

+        <Value val="0x01">gps_fm_debug[15]			</Value>

+        <Value val="0x03">wlan_drpw[6]			</Value>

+        <Value val="0x04">prcm_sdio[5]		</Value>

+        <Value val="0x05">fm_dtst_o[2]			</Value>

+        <Value val="0x06">sb[18]			</Value>

+    </Values>

+    

+    <Values name="AUD_OUT_Quattro" type="enum">

+        <Value val="0x00">ext_pcm_do_o 			</Value>

+        <Value val="0x01">gps_fm_debug[12]			</Value>

+        <Value val="0x02">bt_func5			</Value>

+        <Value val="0x03">wlan_drpw[14]			</Value>

+        <Value val="0x04">prcm_sdio[6]	</Value>

+        <Value val="0x05">fm_dtst_o[3]			</Value>

+        <Value val="0x06">sb[19]			</Value>

+    </Values>

+	

+    <Values name="AUD_CLK_Quattro" type="enum">

+        <Value val="0x00">ext_pcm_clk 			</Value>

+        <Value val="0x01">gps_fm_debug[13]			</Value>

+        <Value val="0x02">gps_gpio_o[7]			</Value>

+        <Value val="0x03">wlan_drpw[0]			</Value>

+        <Value val="0x04">prcm_sdio[4]	</Value>

+        <Value val="0x05">fm_dtst_o[0]			</Value>

+        <Value val="0x06">shared[13]			</Value>

+    </Values>

+    

+    <Values name="AUD_FSYNC_Quattro" type="enum">

+        <Value val="0x00">ext_pcm_fsync 			</Value>

+        <Value val="0x01">gps_fm_debug[10]			</Value>

+        <Value val="0x02">bt_ic_o[1]			</Value>

+        <Value val="0x03">wlan_drpw[1]			</Value>

+        <Value val="0x04">prcm_sdio[15]		</Value>

+        <Value val="0x05">fm_dtst_o[1]		</Value>

+        <Value val="0x06">sb[17]			</Value>

+    </Values>

+	

+    <Values name="BT_FUNC_1_Quattro" type="enum">

+        <Value val="0x00">bt_func1 			</Value>

+        <Value val="0x01">fm_dtst_o[15]			</Value>

+        <Value val="0x03">wlan_drpw[8]			</Value>

+        <Value val="0x04">sb[10]			</Value>

+        <Value val="0x05">bt_ic[2]		</Value>

+        <Value val="0x06">shared[0]			</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_2_Quattro" type="enum">

+        <Value val="0x00">bt_func2 			</Value>

+        <Value val="0x01">fm_dtst_o[8]			</Value>

+        <Value val="0x03">wlan_drpw[9]			</Value>

+        <Value val="0x06">shared[1]			</Value>

+    </Values>

+	

+    <Values name="BT_FUNC_5_Quattro" type="enum">

+        <Value val="0x00">bt_func5 			</Value>

+        <Value val="0x03">wlan_drpw[12]			</Value>

+        <Value val="0x04">prcm_sdio[8]		</Value>

+        <Value val="0x05">prcm_sdio[22]		</Value>

+        <Value val="0x06">shared[3]			</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_3_Quattro" type="enum">

+        <Value val="0x00">bt_func3 			</Value>

+        <Value val="0x03">wlan_drpw[11]			</Value>

+        <Value val="0x04">prcm_sdio[23]			</Value>

+        <Value val="0x05">fm_dtst_o[6]			</Value>

+        <Value val="0x06">shared[3]			</Value>

+    </Values>

+

+    <Values name="BT_FUNC_6_Quattro" type="enum">

+        <Value val="0x00">bt_func6 			</Value>

+        <Value val="0x01">fm_dtst_o[4]			</Value>

+        <Value val="0x02">gps_ext_addr[13]			</Value>

+        <Value val="0x03">wlan_drpw[7]			</Value>

+        <Value val="0x04">bt_debug_clk			</Value>

+        <Value val="0x05">gps_gpio_o[4]			</Value>

+        <Value val="0x06">shared[3]			</Value>

+    </Values>

+    

+    <Values name="BT_FUNC_7_Quattro" type="enum">

+        <Value val="0x00">bt_func7 			</Value>

+        <Value val="0x02">gps_ext_addr[12]			</Value>

+        <Value val="0x03">wlan_drpw[10]			</Value>

+        <Value val="0x05">bt_ic[11]			</Value>

+        <Value val="0x06">shared[3]			</Value>

+    </Values>

+	

+    <Values name="SB_DATA_Quattro" type="enum">

+        <Value val="0x00">sb_data 			</Value>

+        <Value val="0x03">wlan_drpw[17]			</Value>

+        <Value val="0x05">bt_func7_o			</Value>

+        <Value val="0x06">shared[6]			</Value>

+    </Values>

+    

+    <Values name="SB_CLK_Quattro" type="enum">

+        <Value val="0x00">sb_clk 			</Value>

+        <Value val="0x01">gps_fm_gpio[0]			</Value>

+        <Value val="0x03">wlan_drpw[18]			</Value>

+        <Value val="0x05">bt_ic[13]			</Value>

+        <Value val="0x06">shared[4]			</Value>

+    </Values>

+	

+    <Values name="WL_TX_Quattro" type="enum">

+        <Value val="0x00">wl_tx_sw_final 			</Value>

+        <Value val="0x01">gps_fm_debug[0]			</Value>

+        <Value val="0x03">gps_gpio_o[4]			</Value>

+    </Values>

+    

+    <Values name="WL_RX_Quattro" type="enum">

+        <Value val="0x00">wl_rx_sw_final 			</Value>

+        <Value val="0x01">gps_fm_debug[6]			</Value>

+        <Value val="0x03">gps_gpio_o[5]			</Value>

+    </Values>

+	

+    <Values name="FREF_CLK_REQ_Quattro" type="enum">

+        <Value val="0x00">fref_clk_req_o 			</Value>

+        <Value val="0x01">fm_dtst_o[5]			</Value>

+        <Value val="0x03">jtag_rtck			</Value>

+        <Value val="0x04">sb[10]			</Value>

+        <Value val="0x05">bt_ic[3]			</Value>

+        <Value val="0x06">shared[12]			</Value>

+    </Values>

+    

+    <Values name="FM_I2S_DI_Quattro" type="enum">

+        <Value val="0x00">ext_i2s_di 			</Value>

+        <Value val="0x01">gps_fm_gpio[6]			</Value>

+        <Value val="0x02">ext_addr_0			</Value>

+        <Value val="0x03">wlan_drpw[2]			</Value>

+        <Value val="0x04">prcm_sdio[0]			</Value>

+        <Value val="0x05">bt_func1_o			</Value>

+        <Value val="0x06">shared[8]			</Value>

+    </Values>

+

+	

+    <Values name="FM_I2S_DO_Quattro" type="enum">

+        <Value val="0x00">ext_i2s_do_o 			</Value>

+        <Value val="0x01">gps_fm_gpio[7]			</Value>

+        <Value val="0x02">ext_addr_1			</Value>

+        <Value val="0x03">wlan_drpw[3]			</Value>

+        <Value val="0x04">prcm_sdio[1]			</Value>

+        <Value val="0x05">bt_func2_o			</Value>

+        <Value val="0x06">shared[9]			</Value>

+    </Values>

+    

+    <Values name="FM_I2S_CLK_Quattro" type="enum">

+        <Value val="0x00">ext_i2s_clk 			</Value>

+        <Value val="0x02">ext_addr_2			</Value>

+        <Value val="0x03">wlan_drpw[4]			</Value>

+        <Value val="0x04">prcm_sdio[2]			</Value>

+        <Value val="0x05">bt_func3_o			</Value>

+        <Value val="0x06">shared[10]		</Value>

+    </Values>

+	

+    <Values name="FM_I2S_WS_Quattro" type="enum">

+        <Value val="0x00">ext_i2s_fsync 			</Value>

+        <Value val="0x01">jtag_rtck			</Value>

+        <Value val="0x02">ext_addr_3			</Value>

+        <Value val="0x03">wlan_drpw[5]			</Value>

+        <Value val="0x04">prcm_sdio[3]			</Value>

+        <Value val="0x05">bt_func4_o			</Value>

+        <Value val="0x06">shared[11]			</Value>

+    </Values>

+    

+    <Values name="SPI_CSX_Quattro" type="enum">

+        <Value val="0x00">spi_csx_o 			</Value>

+        <Value val="0x01">gps_fm_debug[3]			</Value>

+        <Value val="0x02">gps_ext_addr[6]			</Value>

+        <Value val="0x03">fm_dtst_o[11]			</Value>

+        <Value val="0x04">sb[2]			</Value>

+        <Value val="0x05">bt_ic[12]			</Value>

+        <Value val="0x06">shared[0]			</Value>

+    </Values>

+

+    <Values name="WLAN_IRQ_Quattro" type="enum">

+        <Value val="0x00">sdio_wl_irq 			</Value>

+        <Value val="0x01">gps_fm_debug[1]			</Value>

+        <Value val="0x02">gps_ext_be[1]			</Value>

+        <Value val="0x04">sb[5]			</Value>

+        <Value val="0x05">bt_ic[0]			</Value>

+    </Values>

+    

+    <Values name="WL_UART_DBG_Quattro" type="enum">

+        <Value val="0x00">wl_uart_dbg_o 			</Value>

+        <Value val="0x01">gps_fm_gpio[2]			</Value>

+        <Value val="0x03">gps_irq_o			</Value>

+        <Value val="0x04">sb[9]			</Value>

+        <Value val="0x05">jtag_rtck			</Value>

+        <Value val="0x06">shared[2]			</Value>

+    </Values>

+	

+    <Values name="WL_PAEN_A_Quattro" type="enum">

+        <Value val="0x00">wl_paen_a_final 			</Value>

+        <Value val="0x02">gps_ext_be[0]			</Value>

+        <Value val="0x04">sb[6]			</Value>

+        <Value val="0x05">bt_ic[12]			</Value>

+        <Value val="0x06">shared[0]			</Value>

+    </Values>

+    

+    <Values name="WL_PAEN_B_Quattro" type="enum">

+        <Value val="0x00">wl_paen_b_final 			</Value>

+        <Value val="0x01">gps_fm_debug[9]			</Value>

+        <Value val="0x03">gps_gpio_o[3]			</Value>

+        <Value val="0x05">bt_ic[1]			</Value>

+    </Values>

+	

+    <Values name="WL_BTH_SW_Quattro" type="enum">

+        <Value val="0x00">wl_bth_sw_final 			</Value>

+        <Value val="0x01">gps_fm_debug[7]			</Value>

+        <Value val="0x03">gps_gpio_o[6]			</Value>

+        <Value val="0x06">shared[7]			</Value>

+    </Values>

+    

+    <Values name="WL_EXT_LNA_EN_Quattro" type="enum">

+        <Value val="0x00">wl_gpio_o[7] 			</Value>

+        <Value val="0x01">gps_fm_debug[11]			</Value>

+        <Value val="0x02">ext_addr_5			</Value>

+    </Values>

+

+    <Values name="WL_RS232_RX_Quattro" type="enum">

+        <Value val="0x00">wl_rs232_rx_i 			</Value>

+        <Value val="0x01">gps_fm_debug[14]			</Value>

+        <Value val="0x02">gps_ext_we			</Value>

+        <Value val="0x04">sb[8]			</Value>

+        <Value val="0x05">bt_ic[10]			</Value>

+        <Value val="0x06">shared[2]			</Value>

+    </Values>

+    

+    <Values name="WL_RS232_TX_Quattro" type="enum">

+        <Value val="0x00">wl_rs232_tx_o 			</Value>

+        <Value val="0x01">gps_fm_gpio[5]			</Value>

+        <Value val="0x02">ext_addr_14			</Value>

+        <Value val="0x03">gps_gpio_o[6]			</Value>

+        <Value val="0x04">sb[7]			</Value>

+        <Value val="0x05">bt_ic[9]			</Value>

+        <Value val="0x06">shared[1]			</Value>

+    </Values>

+    <Values name="JTAG_TCK_Quattro" type="enum">

+        <Value val="0x00">JTAG_TCK 			</Value>

+    </Values>

+	

+    <Values name="JTAG_TMS_Quattro" type="enum">

+        <Value val="0x00">jtag_tms 			</Value>

+        <Value val="0x02">gps_ext_addr[4]			</Value>

+        <Value val="0x03">gps_gpio_o[5]			</Value>

+        <Value val="0x04">prcm_sdio[13]			</Value>

+        <Value val="0x05">bt_ic[13]			</Value>

+        <Value val="0x06">shared[6]			</Value>

+    </Values>

+    

+    <Values name="JTAG_TDI_Quattro" type="enum">

+        <Value val="0x00">jtag_tdi 			</Value>

+        <Value val="0x01">gps_fm_gpio[4]			</Value>

+        <Value val="0x02">gps_ext_be[1]			</Value>

+        <Value val="0x03">gps_gpio_o[3]			</Value>

+        <Value val="0x04">sb[12]			</Value>

+        <Value val="0x05">bt_ic[15]			</Value>

+        <Value val="0x06">shared[8]			</Value>

+    </Values>

+	

+    <Values name="JTAG_TDO_Quattro" type="enum">

+        <Value val="0x00">jtag_tdo_test_out 			</Value>

+        <Value val="0x01">gps_fm_gpio[3]			</Value>

+        <Value val="0x02">gps_ext_addr[8]			</Value>

+        <Value val="0x03">wlan_drpw[15]			</Value>

+        <Value val="0x04">prcm_sdio[14]			</Value>

+        <Value val="0x05">bt_ic[14]			</Value>

+        <Value val="0x06">shared[7]			</Value>

+    </Values>

+    

+    <Values name="GPS_UART_TX_Quattro" type="enum">

+       <Value val="0x00">gps_uart_tx_o 			</Value>

+        <Value val="0x01">wimax_info_1			</Value>

+        <Value val="0x02">bt_ext_addr[6]			</Value>

+        <Value val="0x03">wlan_drpw[13]			</Value>

+        <Value val="0x04">sb[0]			</Value>

+        <Value val="0x05">bt_ic[3]			</Value>

+        <Value val="0x06">fm_dtst_o[9]			</Value>

+    </Values>

+	

+    <Values name="GPS_UART_RX_Quattro" type="enum">

+       <Value val="0x00">gps_uart_rx_i 			</Value>

+        <Value val="0x01">fm_irq			</Value>

+        <Value val="0x02">bt_ext_addr[8]			</Value>

+        <Value val="0x03">wlan_drpw[19]		</Value>

+        <Value val="0x04">sb[1]			</Value>

+        <Value val="0x06">fm_dtst_o[10]		</Value>

+    </Values>

+ 

+	   

+    <Values name="GPS_SENS_I2C_SCL_Quattro" type="enum">

+       <Value val="0x00">gps_sens_i2c_scl 			</Value>

+        <Value val="0x01">ext_fm_scl			</Value>

+        <Value val="0x02">bt_ext_addr[4]			</Value>

+        <Value val="0x03">gfm_dtst_o[7]			</Value>

+        <Value val="0x04">sb[14]			</Value>

+        <Value val="0x05">bt_func5_o			</Value>

+        <Value val="0x06">shared[10]			</Value>

+    </Values>

+

+	

+    <Values name="GPS_SENS_I2C_SDA_Quattro" type="enum">

+        <Value val="0x00">gps_sens_i2c_sda 			</Value>

+        <Value val="0x01">ext_fm_sda			</Value>

+        <Value val="0x02">bt_ext_we			</Value>

+        <Value val="0x03">wlan_drpw[23]		</Value>

+        <Value val="0x04">sb[15]			</Value>

+        <Value val="0x05">bt_ic[2]			</Value>

+        <Value val="0x06">fm_dtst_o[8]			</Value>

+    </Values>

+    

+    <Values name="TESTMODE_Quattro" type="enum">

+       <Value val="0x00">/*TESTMODE_in*/ 			</Value>

+        <Value val="0x01">fm_dtst_o[6]			</Value>

+        <Value val="0x02">gps_ext_addr[6]			</Value>

+        <Value val="0x03">wlan_drpw[16]		</Value>

+        <Value val="0x04">sb[13]			</Value>

+        <Value val="0x05">jtag_rtck			</Value>

+        <Value val="0x06">shared[15]			</Value>

+    </Values>

+	

+    <Values name="TCXO_CLK_REQ_Quattro" type="enum">

+       <Value val="0x00">tcxo_clk_req_o 			</Value>

+        <Value val="0x01">bt_ic_o[15]			</Value>

+        <Value val="0x03">gps_irq_o		</Value>

+        <Value val="0x04">sb[11]			</Value>

+        <Value val="0x05">bt_func6_o			</Value>

+        <Value val="0x06">shared[5]			</Value>

+    </Values>

+    

+    <Values name="GPS_IRQ_Quattro" type="enum">

+      <Value val="0x00">gps_irq_o 			</Value>

+        <Value val="0x01">fm_dtst_o[13]			</Value>

+        <Value val="0x02">wimax_tx_0			</Value>

+        <Value val="0x03">wlan_drpw[21]			</Value>

+        <Value val="0x04">sb[16]			</Value>

+        <Value val="0x05">bt_ic[6]			</Value>

+        <Value val="0x06">shared[14]			</Value>

+    </Values>

+

+    <Values name="GPS_TIMESTAMP_Quattro" type="enum">

+       <Value val="0x00">gpsip_time_stamp_i 			</Value>

+        <Value val="0x01">gps_fm_debug_o[10]			</Value>

+        <Value val="0x02">bt_ext_addr[12]			</Value>

+        <Value val="0x03">wlan_drpw[22]			</Value>

+        <Value val="0x04">prcm_sdio[9]			</Value>

+        <Value val="0x05">bt_ic[4]			</Value>

+        <Value val="0x06">shared[13]			</Value>

+    </Values>

+

+    <Values name="GPS_PPS_OUT_Quattro" type="enum">

+       <Value val="0x00">gps_pps_out 			</Value>

+        <Value val="0x01">gps_fm_gpio[1]			</Value>

+		<Value val="0x02">wimax_tx_1			</Value>

+        <Value val="0x03">prcm_sdio[11]			</Value>

+        <Value val="0x04">sb[7]			</Value>

+        <Value val="0x05">jtag_rtck			</Value>

+        <Value val="0x06">fm_dtst_o[14]			</Value>

+    </Values>

+	

+    <Values name="GPS_I2C_UART_SELECT_Quattro" type="enum">

+      <Value val="0x00">wl_rs232_tx_o 			</Value>

+        <Value val="0x01">gps_fm_gpio[5]			</Value>

+        <Value val="0x02">ext_addr_14			</Value>

+        <Value val="0x03">gps_gpio_o[6]			</Value>

+        <Value val="0x04">sb[7]			</Value>

+        <Value val="0x05">bt_ic[9]			</Value>

+        <Value val="0x06">shared[1]			</Value>

+    </Values>

+    

+    <Values name="GPS_EXT_LNA_EN_Quattro" type="enum">

+        <Value val="0x00">gps_ext_lna_en 			</Value>

+        <Value val="0x01">fm_dtst_o[12]			</Value>

+        <Value val="0x02">bt_ext_addr[13]			</Value>

+        <Value val="0x04">prcm_sdio[12]		</Value>

+        <Value val="0x05">bt_ic[7]			</Value>

+        <Value val="0x06">shared[9]			</Value>

+    </Values>

+	

+    <Values name="GPS_PA_EN_Quattro" type="enum">

+        <Value val="0x00">gps_pa_en 			</Value>

+        <Value val="0x01">gps_fm_debug_o[15]			</Value>

+        <Value val="0x02">ext_addr_11			</Value>

+        <Value val="0x03">fm_dtst_o[11]			</Value>

+        <Value val="0x04">prcm_sdio[10]		</Value>

+        <Value val="0x05">bt_ic[5]			</Value>

+        <Value val="0x06">shared[5]			</Value>

+    </Values>

+    

+    <Values name="DC2DC_MODE_Quattro" type="enum">

+      <Value val="0x00">dc2dc_active_mode 			</Value>

+        <Value val="0x02">ext_addr_14			</Value>

+        <Value val="0x04">prcm_sdio[7]			</Value>

+        <Value val="0x05">bt_ic[8]			</Value>

+        <Value val="0x06">shared[4]			</Value>

+    </Values>

+

+    <Values name="TCXO_SLI_OUT_Quattro" type="enum">

+       <Value val="0x00">tcxo_sli_out_o 			</Value>

+        <Value val="0x01">fm_dtst_o[5]			</Value>

+        <Value val="0x02">ext_addr_7			</Value>

+        <Value val="0x03">gps_gpio_o[7]			</Value>

+        <Value val="0x04">sb[11]			</Value>

+        <Value val="0x05">bt_func7_o			</Value>

+        <Value val="0x06">shared[5]			</Value>

+    </Values>

+	

+    <Values name="WL_SPI_DIN_Quattro" type="enum">

+       <Value val="0x00">spi_din 			</Value>

+        <Value val="0x01">gps_fm_debug[5]			</Value>

+        <Value val="0x02">gps_ext_addr[4]			</Value>

+        <Value val="0x04">sb[7]      </Value>

+        <Value val="0x05">jtag_rtck	</Value>

+    </Values>

+    

+    <Values name="WL_SPI_DOUT_Quattro" type="enum">

+        <Value val="0x00">spi_dout 			</Value>

+        <Value val="0x01">gps_fm_debug[4]			</Value>

+        <Value val="0x02">gps_ext_addr[8]			</Value>

+        <Value val="0x04">sb[1]			</Value>

+        <Value val="0x05">bt_ic[1]			</Value>

+    </Values>

+	

+    <Values name="WL_SDIO_D1_Quattro" type="enum">

+        <Value val="0x00">sdio_d1 			</Value>

+        <Value val="0x01">gps_fm_debug[2]			</Value>

+        <Value val="0x02">gps_ext_addr[11]			</Value>

+        <Value val="0x03">fm_dtst_o[7]		</Value>

+        <Value val="0x04">sb[]			</Value>

+        <Value val="0x05">bt_ic[11]			</Value>

+        <Value val="0x06">bt_ic[7]			</Value>

+    </Values>

+    

+    <Values name="WL_SDIO_D2_Quattro" type="enum">

+       <Value val="0x00">sdio_d2 			</Value>

+        <Value val="0x01">gps_fm_debug[8] 			</Value>

+        <Value val="0x03">ggps_gpio_o[2]		</Value>

+        <Value val="0x04">sb[4]			</Value>

+        <Value val="0x05">bt_ic[8]			</Value>

+        <Value val="0x06">fm_dtst_o[6]			</Value>

+    </Values>

+

+

+    <Values name="DRP_Debug_pins_empty_list" type="enum">

+        <Value val="0x00">Don't Change</Value>

+    </Values>

+    

+    <Values name="WB_Debug_pins" type="enum">

+        <Value val="0x01">Don't Change</Value>

+    </Values>

+    

+    <Values name="GCMSignalList" type="enum">

+        <Value val="0x00">pll clock signal to design</Value>

+        <Value val="0x01">fref after division</Value>

+        <Value val="0x02">pll lock signal</Value>

+        <Value val="0x03">pll sync signal</Value>

+        <Value val="0x04">fast frequency input</Value>

+        <Value val="0x05">pll power down command (active low)</Value>

+        <Value val="0x06">system slow clock</Value>

+        <Value val="0x07">system root clock after retiming in DRP</Value>

+        <Value val="0x08">ocp clock</Value>

+        <Value val="0x09">arm clock</Value>

+        <Value val="0x0a">uart clock</Value>

+        <Value val="0x0b">1MHz bt clock</Value>

+        <Value val="0x0c">4MHz bt clock</Value>

+        <Value val="0x0d">usec timer0 event</Value>

+        <Value val="0x0e">usec timer1 event</Value>

+        <Value val="0x0f">codec clock</Value>

+        <Value val="0x10">sdio clock</Value>

+        <Value val="0x11">spi clock</Value>

+        <Value val="0x12">powerup reset</Value>

+        <Value val="0x13">watchdog timer reset</Value> 

+        <Value val="0x14">watch timer event</Value>

+        <Value val="0x15">fast clock enable indication from fcgen to fdc</Value>

+        <Value val="0x16">slow wakeup event from wakeup unit</Value>

+        <Value val="0x17">fast wakeup event from wakeup unit</Value>

+        <Value val="0x18">usec timer event</Value>

+        <Value val="0x19">BT_SLOW_CLK</Value>

+        <Value val="0x1a">Status of local clock load in fast domain (0–no load/load completed,1–load in progress)</Value>

+        <Value val="0x1b">Status of network1 clock load in fast domain (0–no load/load completed, 1–load in progress)</Value>

+        <Value val="0x1c">Status of network2 clock load in fast domain (0–no load/load completed,1–load in progress)</Value>

+        <Value val="0x1d">Local Bluetooth clock, bit 2</Value>

+        <Value val="0x1e">Local Bluetooth clock, bit 3</Value>

+        <Value val="0x1f">Network1 Bluetooth clock, bit 2</Value>

+        <Value val="0x20">Network1 Bluetooth clock, bit 3</Value>

+        <Value val="0x21">Network2 Bluetooth clock, bit 2</Value>

+        <Value val="0x22">Network2 Bluetooth clock, bit 3</Value>

+        <Value val="0x23">Network2 domain status</Value>

+        <Value val="0x24">Status of local clock load in fast domain (0–no load/load completed,1–load in progress)</Value>

+        <Value val="0x25">Status of network1 clock load in fast domain (0–no load/load completed,1–load in progress)</Value>

+        <Value val="0x26">Local domain 1MHz clock</Value>

+        <Value val="0x27">Network2 domain 1MHz clock</Value>

+        <Value val="0x28">Network1 domain 1MHz clock</Value>

+        <Value val="0x29">Switched Bluetooth clock, bit 2</Value>

+        <Value val="0x2a">Switched Bluetooth clock, bit 3</Value>

+        <Value val="0x2b">Scheduler Bluetooth clock, bit 2</Value>

+        <Value val="0x2c">Local Packet Timer, bit 10</Value>

+        <Value val="0x2d">Network2 Packet Timer, bit 10</Value>

+        <Value val="0x2e">Network1 Packet Timer, bit 10</Value>

+        <Value val="0x2f">Switched Packet Timer, bit 10</Value>

+        <Value val="0x30">Scheduler Packet Timer, bit 10</Value>

+        <Value val="0x31">NIRQ 2 (timer interrupts)</Value>

+        <Value val="0x32">slow domain control state machine - dbg3:0 only</Value>

+        <Value val="0x32">fast domain control state machine - dbg7:4 only</Value>

+        <Value val="0x32">DMA clock (check dynamic DMA clock gating) - dbg9:8 only</Value>

+        <Value val="0x33">slow domain scripter control bus - dbg5:0 only</Value>

+        <Value val="0x33">Wibree root clock - dbg7:6 only</Value>

+        <Value val="0x33">Wibree gated cortex clock - dbg8 only</Value>

+        <Value val="0x33">Wibree free cortex clock - dbg9 only</Value>

+        <Value val="0x34">slow domain scripter control bus - dbg5:0 only</Value>

+        <Value val="0x34">Wibree AES clock - dbg6 only</Value>

+        <Value val="0x34">Wibree OCP gated clock - dbg7 only</Value>

+        <Value val="0x34">Wibree free OCP clock - dbg8 only</Value>

+        <Value val="0x34">Wibree dma  clock - dbg9 only</Value>

+        <Value val="0x35">BT dma  clock - dbg0 only</Value>

+        <Value val="0x35">BT PCMI  clock - dbg1 only</Value>

+        <Value val="0x35">BT I2C  clock - dbg2 only</Value>

+        <Value val="0x35">BT Debug clock - dbg3 only</Value>

+        <Value val="0x35">Network1 Bluetooth clock, bit 4 - dbg6 or dbg8 only</Value>

+        <Value val="0x35">Network2 Bluetooth clock, bit 5 - dbg4 or dbg9 only</Value>

+        <Value val="0x35">Network1 Bluetooth clock, bit 5 - dbg5 or dbg7 only</Value>

+        <Value val="0x36">Fast clock status (on / off) - dbg0 or dbg4 only</Value>

+        <Value val="0x36">qra11_n1_cdc_adjust_event_i - dbg1 or dbg5 only</Value>

+        <Value val="0x36">qra11_n2_cdc_adjust_event_i - dbg2 or dbg9 only</Value>

+        <Value val="0x36">Local Bluetooth clock, bit 5 - dbg3 or dbg7 only</Value>

+        <Value val="0x36">Network2 Bluetooth clock, bit 4 - dbg6 or dbg8 only</Value>

+        <Value val="0x37">Local Bluetooth clock, bit 4 - dbg7 or dbg8 only</Value>

+        <Value val="0x37">Switched Packet Timer, bit 9 - dbg4 only</Value>

+        <Value val="0x37">Switched Bluetooth clock, bit 4 - dbg6 or dbg9 only</Value>

+        <Value val="0x37">Switche4 Bluetooth clock, bit 5 - dbg0 or dbg5 only</Value>

+        <Value val="0x37">Local Packet Timer, bit 9 - dbg1 only</Value>

+        <Value val="0x37">Network1 Packet Timer, bit 9 - dbg2 only</Value>

+        <Value val="0x37">Network2 Packet Timer, bit 9 - dbg3 only</Value>

+    </Values>

+    

+    <!-- ================================================================== -->

+    <!--                            Mask values                             -->

+    <!-- ================================================================== -->

+    

+    <Values name="Wlan_Priority_select" type="mask">

+        <Value val ="0x0000">Priority disabled</Value>

+        <Value val ="0x0001">SCO/eSCO</Value>

+        <Value val ="0x0002">Priority during eSCO window</Value>

+        <Value val ="0x0004">Priority during FHS/ID</Value>

+        <Value val ="0x0008">Sniff</Value>

+        <Value val ="0x0010">Hold</Value>

+        <Value val ="0x0020">Inq Scan</Value>

+        <Value val ="0x0040">Inquiry</Value>

+        <Value val ="0x0080">Page Scan</Value>

+        <Value val ="0x0100">Page</Value>

+        <Value val ="0x0200">Park</Value>

+        <Value val ="0x0400">TDD</Value>

+        <Value val ="0x0800">First successfull sniff attempt only</Value>

+        <Value val ="0x1000">Park beacon</Value>

+        <Value val ="0x2000">eSCO window only in master</Value>

+        <Value val ="0x4000">Tpoll</Value>

+        <Value val ="0x8000">AFH scans</Value>

+    </Values>

+    

+    <Values name="RF_Calibration_DRPb_Bitmap" type="mask">

+        <Value val="0x00000001">Pre RF init</Value>

+        <Value val="0x00000008">Clock Dependant Calc</Value>

+        <Value val="0x00000010">Temperature recognition</Value>

+	<Value val="0x00000020">DC</Value>

+        <Value val="0x00000040">LDO</Value>

+        <Value val="0x00000080">DCO Current Optimization</Value>

+        <Value val="0x00000100">DCO Coarse Open Loop</Value>

+        <Value val="0x00000200">KDCO Nominal Current</Value>

+        <Value val="0x00000400">PPA LDO Current</Value>

+        <Value val="0x00000800">TPC</Value>

+        <Value val="0x00001000">IFA Pole Location</Value>

+        <Value val="0x00002000">LPS</Value>

+        <Value val="0x00004000">Wide Band RSSI TH</Value>

+        <Value val="0x00008000">IQ MM</Value>

+        <Value val="0x80000000">Don't Change</Value>

+    </Values>

+

+    <Values name="RF_Calibrations" type="enum">

+        <Value val="00">Pre RF init</Value>

+        <Value val="01">None</Value>

+        <Value val="02">None</Value>

+        <Value val="03">Clock Dependant Calc</Value>

+        <Value val="04">Temperature recognition</Value>

+        <Value val="05">DC</Value>

+        <Value val="06">LDO</Value>

+        <Value val="07">DCO Current Optimization</Value>

+        <Value val="08">DCO Coarse Open Loop</Value>

+        <Value val="09">KDCO Nominal Current</Value>

+        <Value val="10">PPA LDO Current</Value>

+        <Value val="11">TPC</Value>

+        <Value val="12">IFA Pole Location</Value>

+        <Value val="13">LPS</Value>

+        <Value val="14">Wide Band RSSI TH</Value>

+        <Value val="15">IQ MM</Value>

+        <Value val="16">None</Value>

+        <Value val="17">None</Value>

+        <Value val="18">None</Value>

+        <Value val="19">None</Value>

+        <Value val="20">None</Value>

+        <Value val="21">None</Value>

+        <Value val="22">None</Value>

+        <Value val="23">None</Value>

+        <Value val="24">None</Value>

+        <Value val="25">None</Value>

+        <Value val="26">None</Value>

+        <Value val="27">None</Value>

+        <Value val="28">None</Value>

+        <Value val="29">None</Value>

+        <Value val="30">None</Value>

+        <Value val="31">None</Value>

+    </Values>

+

+    <Values name="External_PA_Mode" type="mask">

+        <Value val="0x0001">PowerLevel 0</Value>

+        <Value val="0x0002">PowerLevel 1</Value>

+        <Value val="0x0004">PowerLevel 2</Value>

+        <Value val="0x0008">PowerLevel 3</Value>

+        <Value val="0x0010">PowerLevel 4</Value>

+        <Value val="0x0020">PowerLevel 5</Value>

+        <Value val="0x0040">PowerLevel 6</Value>	

+        <Value val="0x0080">PowerLevel 7</Value>

+        <Value val="0x0100">PowerLevel 8</Value>

+        <Value val="0x0200">PowerLevel 9</Value>

+        <Value val="0x0400">PowerLevel 10</Value>

+        <Value val="0x0800">PowerLevel 11</Value>

+        <Value val="0x1000">PowerLevel 12</Value>

+        <Value val="0x2000">PowerLevel 13</Value>

+        <Value val="0x4000">PowerLevel 14</Value>

+        <Value val="0x8000">PowerLevel 15</Value>	

+    </Values>

+    

+    <Values name="AclType" type="mask">

+        <Value val="0x0008">DM1</Value>

+        <Value val="0x0010">DH1</Value>

+        <Value val="0x0400">DM3</Value>

+        <Value val="0x0800">DH3</Value>

+        <Value val="0x4000">DM5</Value>

+        <Value val="0x8000">DH5</Value>

+        <Value val="0x0002">No 2DH1</Value>

+        <Value val="0x0004">No 3DH1</Value>

+        <Value val="0x0100">No 2DH3</Value>

+        <Value val="0x0200">No 3DH3</Value>

+        <Value val="0x1000">No 2DH5</Value>

+        <Value val="0x2000">No 3DH5</Value>

+    </Values>

+

+     <Values name="ScoType" type="mask">

+        <Value val="0x0020">HV1</Value>

+        <Value val="0x0040">HV2</Value>

+        <Value val="0x0080">HV3</Value>

+    </Values>

+    

+    <Values name="AclScoTypes" type="mask">

+        <Value val="0x0008">DM1</Value>

+        <Value val="0x0010">DH1</Value>

+        <Value val="0x0400">DM3</Value>

+        <Value val="0x0800">DH3</Value>

+        <Value val="0x4000">DM5</Value>

+        <Value val="0x8000">DH5</Value>

+        <Value val="0x0020">HV1</Value>

+        <Value val="0x0040">HV2</Value>

+        <Value val="0x0080">HV3</Value>

+        <Value val="0x0002">No 2DH1</Value>

+        <Value val="0x0004">No 3DH1</Value>

+        <Value val="0x0100">No 2DH3</Value>

+        <Value val="0x0200">No 3DH3</Value>

+        <Value val="0x1000">No 2DH5</Value>

+        <Value val="0x2000">No 3DH5</Value>

+    </Values>

+    

+    <Values name="ScoType2" type="mask">

+        <Value val="0x0001">HV1</Value>

+        <Value val="0x0002">HV2</Value>

+        <Value val="0x0004">HV3</Value>

+        <Value val="0x0008">EV3</Value>

+        <Value val="0x0010">EV4</Value>

+        <Value val="0x0020">EV5</Value>

+        <Value val="0x0040">No2EV3</Value>	

+        <Value val="0x0080">No3EV3</Value>

+        <Value val="0x0100">No2EV5</Value>

+        <Value val="0x0200">No3EV5</Value>

+    </Values>

+    

+    <Values name="LinkPolicy" type="mask">

+        <Value val="0x0001">Role Switch</Value>

+        <Value val="0x0002">Hold Mode</Value>

+        <Value val="0x0004">Sniff Mode</Value>

+        <Value val="0x0008">Park Mode</Value>

+    </Values>

+    

+    <Values name="EventMask" type="mask">

+        <Value val="0x0000000000000001">Inquiry Complete Event</Value>

+        <Value val="0x0000000000000002">Inquiry Result Event</Value>

+        <Value val="0x0000000000000004">Connection Complete Event</Value>

+        <Value val="0x0000000000000008">Connection Request Event</Value>

+        <Value val="0x0000000000000010">Disconnection Complete Event</Value>

+        <Value val="0x0000000000000020">Authentication Complete Event</Value>

+        <Value val="0x0000000000000040">Remote Name Request Complete Event</Value>

+        <Value val="0x0000000000000080">Encryption Change Event</Value>

+        <Value val="0x0000000000000100">Change Connection Link Key Complete Event</Value>

+        <Value val="0x0000000000000200">Master Link Key Complete Event</Value>

+        <Value val="0x0000000000000400">Read Remote Supported Features Complete Event</Value>

+        <Value val="0x0000000000000800">Read Remote Version Information Complete Event</Value>

+        <Value val="0x0000000000001000">QoS Setup Complete Event</Value>

+        <Value val="0x0000000000008000">Hardware Error Event</Value>

+        <Value val="0x0000000000010000">Flush Occurred Event</Value>

+        <Value val="0x0000000000020000">Role Change Event</Value>

+        <Value val="0x0000000000080000">Mode Change Event</Value>

+        <Value val="0x0000000000100000">Return Link Keys Event</Value>

+        <Value val="0x0000000000200000">PIN Code Request Event</Value>

+        <Value val="0x0000000000400000">Link Key Request Event</Value>

+        <Value val="0x0000000000800000">Link Key Notification Event</Value>

+        <Value val="0x0000000001000000">Loopback Command Event</Value>

+        <Value val="0x0000000002000000">Data Buffer Overflow Event</Value>

+        <Value val="0x0000000004000000">Max Slots Change Event</Value>

+        <Value val="0x0000000008000000">Read Clock Offset Complete Event</Value>

+        <Value val="0x0000000010000000">Connection Packet Type Changed Event</Value>

+        <Value val="0x0000000020000000">QoS Violation Event</Value>

+        <Value val="0x0000000040000000">Page Scan Mode Change Event [deprecated]</Value>

+        <Value val="0x0000000080000000">Page Scan Repetition Mode Change Event</Value>

+        <Value val="0x0000000100000000">Flow Specification Complete Event</Value>

+        <Value val="0x0000000200000000">Inquiry Result with RSSI Event</Value>

+        <Value val="0x0000000400000000">Read Remote Extended Features Complete Event</Value>

+        <Value val="0x0000000800000000">Fixed Address Event</Value>

+        <Value val="0x0000001000000000">Alias Address Event</Value>

+        <Value val="0x0000002000000000">Generate Alias Request Event</Value>

+        <Value val="0x0000004000000000">Active Address Event</Value>

+        <Value val="0x0000008000000000">Allow Private Pairing Event</Value>

+        <Value val="0x0000010000000000">Alias Address Request Event</Value>

+        <Value val="0x0000020000000000">Alias Not Recognized Event</Value>

+        <Value val="0x0000040000000000">Fixed Address Attempt Event</Value>

+        <Value val="0x0000080000000000">Synchronous Connection Complete Event</Value>

+        <Value val="0x0000100000000000">Synchronous Connection Changed Event</Value>

+        <Value val="0x0000200000000000">Sniff Subrate Changed Event</Value>

+        <Value val="0x0000400000000000">Extended Inquiry Result Event</Value>

+        <Value val="0x0000800000000000">Encryption Key Refresh Event</Value>

+        <Value val="0x0001000000000000">Io Capabilities Request Event</Value>

+        <Value val="0x0002000000000000">Io Capabilities Response Event</Value>

+        <Value val="0x0004000000000000">Io User Conf Req Event</Value>

+        <Value val="0x0008000000000000">User Passkey Request Event</Value>

+        <Value val="0x0010000000000000">Io User Oob Data Req Event</Value>

+        <Value val="0x0020000000000000">Simple Pairing Complete Event</Value>

+        <Value val="0x0020000000000000">Reserved</Value>

+        <Value val="0x0080000000000000">Link Supervision Timeout Change Event</Value>

+        <Value val="0x0100000000000000">Enhanced Flush Complete Event</Value>

+        <Value val="0x0200000000000000">Sniff_Request Event</Value>			

+        <Value val="0x0400000000000000">User Passkey Notification Event</Value>

+        <Value val="0x0800000000000000">Keypress Notification Event</Value>

+        <Value val="0x1000000000000000">Remote Host Supported Features Notification Event</Value>

+        <Value val="0x2000000000000000">LE Meta Event</Value>

+    </Values>

+    

+    <Values name="SPDebugMode" type="mask">

+        <Value val="0x00">Disabled</Value>

+        <Value val="0x01">Enabled</Value>

+    </Values>

+    

+    <Values name="Codec_Data_Order" type="mask">

+        <Value val="0x0001">Data driven LSB-first</Value>

+        <Value val="0x0002">Swap bytes within the sample</Value>

+        <Value val="0x0004">Shift sample by (24|16-dout_size) bits</Value>

+    </Values>

+    

+    <Values name="tst_oe" type="mask">

+        <Value val="0x0000">No bits output</Value>

+        <Value val="0x0001">Bit 0</Value>

+        <Value val="0x0002">Bit 1</Value>

+        <Value val="0x0004">Bit 2</Value>

+        <Value val="0x0008">Bit 3</Value>

+        <Value val="0x0010">Bit 4</Value>	

+        <Value val="0x0020">Bit 5</Value>

+        <Value val="0x0040">Bit 6</Value>

+        <Value val="0x0080">Bit 7</Value>

+        <Value val="0x0100">Bit 8</Value>

+        <Value val="0x0200">Bit 9</Value>

+        <Value val="0x0400">Bit 10</Value>

+        <Value val="0x0800">Bit 11</Value>

+        <Value val="0x1000">Bit 12</Value>

+        <Value val="0x2000">Bit 13</Value>

+        <Value val="0x4000">Bit 14</Value>

+        <Value val="0x8000">Bit 15</Value>

+    </Values>

+    

+    <Values name="Patches_En" type="mask">

+        <Value val="0x00000001">Patch #1</Value>

+        <Value val="0x00000002">Patch #2</Value>

+        <Value val="0x00000004">Patch #3</Value>

+        <Value val="0x00000008">Patch #4</Value>

+        <Value val="0x00000010">Patch #5</Value>

+        <Value val="0x00000020">Patch #6</Value>

+        <Value val="0x00000040">Patch #7</Value>

+        <Value val="0x00000080">Patch #8</Value>

+        <Value val="0x00000100">Patch #9</Value>

+        <Value val="0x00000200">Patch #10</Value>

+        <Value val="0x00000400">Patch #11</Value>

+        <Value val="0x00000800">Patch #12</Value>

+        <Value val="0x00001000">Patch #13</Value>

+        <Value val="0x00002000">Patch #14</Value>

+        <Value val="0x00004000">Patch #15</Value>

+        <Value val="0x00008000">Patch #16</Value>

+        <Value val="0x00010000">Patch #17</Value>

+        <Value val="0x00020000">Patch #18</Value>

+        <Value val="0x00040000">Patch #19</Value>

+        <Value val="0x00080000">Patch #20</Value>

+        <Value val="0x00100000">Patch #21</Value>

+        <Value val="0x00200000">Patch #22</Value>

+        <Value val="0x00400000">Patch #23</Value>

+        <Value val="0x00800000">Patch #24</Value>

+        <Value val="0x01000000">Patch #25</Value>

+        <Value val="0x02000000">Patch #26</Value>

+        <Value val="0x04000000">Patch #27</Value>

+        <Value val="0x08000000">Patch #28</Value>

+        <Value val="0x10000000">Patch #29</Value>

+        <Value val="0x20000000">Patch #30</Value>

+        <Value val="0x40000000">Patch #31</Value>

+        <Value val="0x80000000">Patch #32</Value>

+    </Values>

+

+    <Values name="I2C_FM_Power_Mode_Enable_Types" type="enum">

+		<Value val="0x0">FM Off</Value>	

+		<Value val="0x1">FM On</Value>	

+		<Value val="0x10">FM Off with retention</Value>	

+	</Values>

+    

+<!-- ******************************************************* -->

+<!-- ******************************************************* -->

+<!-- A3DP Values		                                     -->

+<!-- ******************************************************* -->

+<!-- ******************************************************* -->

+

+ <Values name="a3dp_audio_source" type="enum">

+	<Value val="0x00">Host's PCM bus</Value>

+	<Value val="0x01">Internal Controller's FM.</Value>

+ </Values>

+

+ <Values name="a3dp_role" type="enum">

+	<Value val="0x00">Source</Value>

+	<Value val="0x01">Sink</Value>

+ </Values>

+ 

+ <Values name="a3dp_PCM_input_sample_freq" type="enum">

+	<Value val="0x01">8000 Hz</Value>

+	<Value val="0x02">11025 Hz</Value>

+	<Value val="0x03">12000 Hz</Value>

+	<Value val="0x04">16000 Hz</Value>

+	<Value val="0x05">22050 Hz</Value>

+	<Value val="0x06">24000 Hz</Value>

+	<Value val="0x07">32000 Hz</Value>

+	<Value val="0x08">44100 Hz</Value>

+	<Value val="0x09">48000 Hz</Value>

+ </Values>

+

+ <Values name="a3dp_PCM_num_channels" type="enum">

+	<Value val="0x01">1 channel</Value>

+	<Value val="0x02">2 channels</Value>

+ </Values>

+

+ <Values name="a3dp_SBC_input_freq" type="enum">

+	<Value val="0x00">16000 Hz</Value>

+	<Value val="0x01">32000 Hz</Value>

+	<Value val="0x02">44100 Hz</Value>

+	<Value val="0x03">48000 Hz</Value>

+ </Values>

+

+ <Values name="a3dp_SBC_channel_mode" type="enum">

+	<Value val="0x00">Mono</Value>

+	<Value val="0x01">Dual Stereo</Value>

+	<Value val="0x02">Stereo</Value>

+	<Value val="0x03">Joint Stereo</Value>

+ </Values>

+

+ <Values name="a3dp_SBC_allocation_method" type="enum">

+	<Value val="0x00">Loudness</Value>

+	<Value val="0x01">SNR</Value>

+ </Values>

+ 

+ <Values name="a3dp_dynamic_bit_pool_enable" type="enum">

+	<Value val="0x00">Disable</Value>

+	<Value val="0x01">Enable</Value>

+ </Values>

+

+ <Values name="a3dp_flush_flag" type="enum">

+	<Value val="0x00">Transmit internal buffers before flush (soft flush)</Value>

+	<Value val="0x01">Immediate flush of buffers (hard flush)</Value>

+ </Values>

+  <Values name="a3dp_generate_event" type="enum">

+	<Value val="0x00">No</Value>

+	<Value val="0x01">Yes</Value>

+ </Values>

+ a3dp_generate_event

+    

+    

+    <!-- ******************************************************* -->

+    <!-- ******************************************************* -->

+    <!--                                                       	 -->

+<!-- GPS Enumerations and masks value tables	          	 -->

+	<!--                                                       	 -->

+	<!-- ******************************************************* -->

+	<!-- ******************************************************* -->

+

+	<Values name="HCI_GPS_Event_Id" type="enum">

+		<Value val="0x1">HCI GPS Inbound Data Event</Value>

+		<Value val="0x2">HCI GPS Outbound Data Event</Value>

+		<Value val="0x3">HCI GPS Number of Completed Packets Event</Value>

+	</Values>

+

+	<Values name="GPS_POWER_MODES" type="enum">

+		<Value val="0x0">Power Off</Value>

+		<Value val="0x1">Power On</Value>

+	</Values>

+

+<!-- ******************************************************* -->

+<!-- ******************************************************* -->

+<!--                                                       	 -->

+<!-- Wibree Enumerations and masks value tables	          	 -->

+<!--                                                       	 -->

+<!-- ******************************************************* -->

+<!-- ******************************************************* -->

+

+	<Values name="Hci_LE_Event_Id" type="enum">

+		<Value code="0x4B" val="Hci_LE_Encryption_Requested_Event" />

+		<Value code="0x4C" val="Hci_LE_Encrypted_Event" />

+	</Values>

+

+	<Values name="Hci_LE_Address_Type" type="enum">

+		<Value val="0x00">Public Device Address</Value>

+		<Value val="0x01">Random Device Address</Value>

+	</Values>

+

+	<Values name="Hci_LE_White_List_Ussage" type="enum">

+		<Value val="0x00">White_List Not In Use</Value>

+		<Value val="0x01">White List Is Used</Value>

+	</Values>

+

+	<Values name="Hci_LE_Event_Mask" type="mask">

+		<Value val="0x0000000000000001">LE Connection Complete Event</Value>

+		<Value val="0x0000000000000002">Advertising Report Event</Value>

+		<Value val="0x0000000000000004">LE Connection Update Complete Event</Value>

+		<Value val="0x0000000000000008">LE Read Remote Used Features Complete Event</Value>

+		<Value val="0x0000000000000010">LE Long Term Key Request Event</Value>

+	</Values>

+

+	<Values name="DebugMask" type="mask">

+		<Value val="0x0001">unmask bit 0  </Value>

+        <Value val="0x0002">unmask bit 1  </Value>

+        <Value val="0x0004">unmask bit 2  </Value>

+        <Value val="0x0008">unmask bit 3  </Value>

+        <Value val="0x0010">unmask bit 4  </Value>

+        <Value val="0x0020">unmask bit 5  </Value>

+        <Value val="0x0040">unmask bit 6  </Value>

+        <Value val="0x0080">unmask bit 7  </Value>

+        <Value val="0x0100">unmask bit 8  </Value>

+        <Value val="0x0200">unmask bit 9  </Value>

+        <Value val="0x0400">unmask bit 10 </Value>

+        <Value val="0x0800">unmask bit 11 </Value>

+        <Value val="0x1000">unmask bit 12 </Value>

+        <Value val="0x2000">unmask bit 13 </Value>

+        <Value val="0x4000">unmask bit 14 </Value>

+        <Value val="0x8000">unmask bit 15 </Value>

+	</Values>

+

+	<Values name="data_transaction_debug_mask" type="mask">

+        <Value val ="0x0001">WB_CONNECTION_UPDATE	</Value>

+        <Value val ="0x0002">WB_CHANNEL_MAP_UPDATE	</Value>

+        <Value val ="0x0004">WB_TERMINATE_IND		</Value>

+        <Value val ="0x0008">WB_ENC_REQ 			</Value>

+        <Value val ="0x0010">WB_ENC_RSP				</Value>

+        <Value val ="0x0020">WB_START_ENC_REQ		</Value>

+        <Value val ="0x0040">WB_START_ENC_RSP		</Value>

+        <Value val ="0x0080">WB_UNKNOWN_RSP			</Value>

+        <Value val ="0x0100">WB_FEATURES_REQ		</Value>	

+        <Value val ="0x0200">WB_FEATURES_RES		</Value>	

+        <Value val ="0x0400">WB_PAUSE_ENC_REQ		</Value>

+        <Value val ="0x0800">WB_PAUSE_ENC_RSP		</Value>

+        <Value val ="0x1000">WB_VERSION_IND   		</Value>

+        <Value val ="0x2000">WB_REJECT_IND   		</Value>

+	</Values>

+

+	<Values name="advertise_packet_debug_mask" type="mask">

+        <Value val ="0x0001">WB_ADV_IND 					</Value>

+        <Value val ="0x0002">WB_ADV_DIRECT_IND				</Value>

+        <Value val ="0x0004">WB_NON_CONN_ADV_IND			</Value>

+        <Value val ="0x0008">WB_SCAN_REQ 					</Value>

+        <Value val ="0x0010">WB_SCAN_RSP 					</Value>

+        <Value val ="0x0020">WB_CONNECT_REQ 				</Value>

+        <Value val ="0x0040">WB_ADV_DISCOVER_IND			</Value>

+        <Value val ="0x0080">WB_ON_CONNECT_REQ_SENT			</Value>

+        <Value val ="0x0100">WB_ON_CONNECTION_ESTABLISHED	</Value>	

+        <Value val ="0x0200">WB_ON_BAD_MIC_TERMINATION		</Value>	

+        <Value val ="0x0400">WB_ON_LE_FLUSH_FINISHED		</Value>

+	</Values>	

+

+	<Values name="Hci_LE_Start_Stop" type="enum">

+		<Value val="0x01">Start</Value>

+		<Value val="0x00">Stop</Value>

+	</Values>

+

+	<Values name="Filter_Duplicates" type="enum">

+		<Value val="0x0">Duplicate filtering is disabled</Value>

+		<Value val="0x1">Duplicate filtering is enabled</Value>

+	</Values>

+	

+	<Values name="Advertising_Event_Type" type="enum">

+		<Value val="0x00">Connectable Undirect Event</Value>

+		<Value val="0x01">Connectable Direct Event</Value>

+		<Value val="0x02">Discoverable Event</Value>

+		<Value val="0x03">Non-Connectable Undirect Event</Value>

+		<Value val="0x04">Scan Response</Value>

+	</Values>

+	

+	<Values name="Advertising_Type" type="enum">

+		<Value val="0x00">Connectable Undirect Event</Value>

+		<Value val="0x01">Connectable Direct Event</Value>

+		<Value val="0x02">Discoverable Non-direct Event</Value>

+		<Value val="0x03">Non-Connectable Undirect Event</Value>

+	</Values>

+

+	<Values name="Advertising_Filter_Policy" type="enum">

+		<Value val="0x00">Allow Scan Request from Any, Allow Connect Request from Any</Value>

+		<Value val="0x01">Allow Scan Request from White List, Allow Connect Request from Any</Value>

+		<Value val="0x02">Allow Scan Request From Any, Connect from White List</Value>

+		<Value val="0x03">Allow Scan Request From White List, Connect from White List</Value>

+	</Values>

+

+	<Values name="Scanning_Filter_Policy" type="enum">

+		<Value val="0x00">Allow ADV From Any</Value>

+		<Value val="0x01">Allow ADV White List</Value>

+	</Values>

+	

+	<Values name="Hci_LE_Event_Opcode" type="enum">

+		<Value val="0x01">LE Connection Created Event</Value>

+		<Value val="0x02">LE Advertising Report Event</Value>

+		<Value val="0x03">LE Connection Update Complete Event</Value>

+		<Value val="0x04">LE Read Remote Used Features Event</Value>

+		<Value val="0x05">LE Long Term Key Requested Event</Value>

+

+	</Values>

+

+	<Values name="Hci_LE_More_Profiles" type="enum">

+		<Value val="0x00">No Other Profiles Supported</Value>

+		<Value val="0x01">Other Profiles Supported</Value>

+	</Values>

+

+	<Values name="Hci_LE_Scan_Mode" type="enum">

+		<Value val="0x00">Passive</Value>

+		<Value val="0x01">Active</Value>

+	</Values>

+

+	<Values name="Hci_LE_Key_Type" type="enum">

+		<Value val="0x00">Apply to HCI_LE_Encrypt</Value>

+		<Value val="0x01">Apply to Data Packets</Value>

+	</Values>

+

+	<Values name="Hci_LE_Advertising_Completed_Reason" type="enum">

+		<Value val="0x00">LL Connection Requested by Peer Device</Value>

+		<Value val="0x01">Advertising Stopped by the Host</Value>

+	</Values>

+

+	<Values name="Hci_LE_Connection_Termination_Reason" type="enum">

+		<Value val="0x00">Termination Requested by the Local Device</Value>

+		<Value val="0x01">Termination Requested by the Peer Device</Value>

+		<Value val="0x02">Link Supervision Timeout</Value>

+		<Value val="0x03">Termination Due To MIC failure</Value>

+		<Value val="0x04">Termination Due To Peer Device Transaction Too Late</Value>

+	</Values>

+	

+	<Values name="PLL_Sharing_Scheme_Mode" type="enum">

+		<Value val="0x00">PLL Sharing Scheme Disabled</Value>

+		<Value val="0x01">PLL Sharing Scheme Enabled</Value>

+		<Value val="0x02">Force COEX PLL</Value>

+		<Value val="0x03">Force HP PLL</Value>

+		<Value val="0x04">Force LP PLL</Value>

+		<Value val="0x05">Force LP Bypass PLL</Value>

+	</Values>

+	

+	<Values name="PLL_Sharing_Types" type="enum">

+		<Value val="0x00">SHARED_PLL_NOT_ENABLED</Value>

+		<Value val="0x01">COEX_PLL</Value>

+		<Value val="0x02">MCS HP PLL </Value>

+		<Value val="0x03">MCS LP PLL </Value>

+		<Value val="0x04">MCS LP Power Save</Value>

+		<Value val="0x05">MCS LP Bypass PLL</Value>

+	</Values>

+	

+	<Values name="External_dc2dc_Mode" type="enum">

+		<Value val="0x00">disabled</Value>

+		<Value val="0x01">enabled</Value>

+		<Value val="0x02">According to detection</Value>

+		<Value val="0xFF">don't change</Value>

+	</Values>

+	

+	<Values name="DC2DC_input_frequency" type="enum">

+		<Value val="0x01">FM OCP</Value>

+		<Value val="0x02">TCXO</Value>

+		<Value val="0x04">HP</Value>

+		<Value val="0x08">LP</Value>

+		<Value val="0xFF">Don't change</Value>

+	</Values>

+	

+	<Values name="JTAG_Enable_RTCK_Muxing" type="enum">

+		<Value val="0x00">SPI_DIN</Value>

+		<Value val="0x01">WL_UART_DBG</Value>

+		<Value val="0x02">FM_I2S_FSYNC</Value>

+		<Value val="0x03">FREF_CLK_REQ</Value>

+		<Value val="0x04">TESTMODE</Value>

+		<Value val="0x05">GPS_PPS_OUT</Value>		

+	</Values>

+

+	<Values name="HCI_LE_Testmode_Packet_Type" type="enum">

+		<Value val="0x0">PRBS 9</Value>

+		<Value val="0x1">FOFO</Value>

+		<Value val="0x2">ZOZO</Value>

+		<Value val="0x3">PRBS 15</Value>

+		<Value val="0x4">ALL 1</Value>

+		<Value val="0x5">ALL 0</Value>

+		<Value val="0x6">OFOFO</Value>

+		<Value val="0x7">OZOZO</Value>

+	</Values>

+

+	<Values name="HCI_LE_Testmode_Receive_Mode" type="enum">

+		<Value val="0x0">Normal Mode</Value>

+		<Value val="0x1">Wide Window</Value>

+		<Value val="0x2">Continious RX</Value>

+		<Value val="0x3">Wide window and power saving</Value>

+	</Values>

+	

+	<Values name="I_LOC_RSSI_Monitoring_Alert_Type" type="enum">

+		<Value val="0x0">In Range Alert</Value>

+		<Value val="0x1">Low Alert</Value>

+		<Value val="0x2">High Alert</Value>		

+	</Values>

+

+	<Values name="LE_General_CFG_0" type="mask">	

+		<Value val="0x0001">Sync valid check from phy</Value>				

+		<Value val="0x0002">Sync valid check misc</Value>				

+		<Value val="0x0004">Sync valid check in connection setup</Value>

+		<Value val="0x0008">Sync valid check in test mode</Value>

+		<Value val="0x0010">Print syncs check to logger</Value>		

+		<Value val="0x0020">Wave io pin for syncs check</Value> 			

+		<Value val="0x0040">Force sending events to host upon disconnect</Value>		

+		<Value val="0x0080">Prevent sending events to host upon disconnect</Value>		

+	</Values>

+	

+	<Values name="LE_Qualification_bitmap" type="mask">	

+		<Value val="0x00000001">Set specific window and offset</Value>

+		<Value val="0x00000002">Send reject on start enc</Value>

+		<Value val="0x00000004">Generate transaction in past</Value>

+		<Value val="0x00000008">Generate specific packet counter in transaction</Value>

+		<Value val="0x00000010">Ignore start enc req</Value>

+		<Value val="0x00000020">Slave generate incorrect crc on conn setup</Value>

+		<Value val="0x00000040">Generate clock drift</Value>

+		<Value val="0x00000080">Skip verison ind at establishement</Value>

+		<Value val="0x00000100">Stay in latency</Value>

+		<Value val="0x00000200">Enc master use forced skdm ivm</Value>

+		<Value val="0x00000400">Enc slave use forced skds ivs</Value>

+		<Value val="0x00000800">Enc generate bad mic on invalid header received</Value>

+		<Value val="0x00001000">Enc use header rfu bits in b1</Value>

+		<Value val="0x00002000">Send lmp timeout on disconnect with lmp to</Value>

+	</Values>

+

+	<Values name="FE_scheme" type="enum">

+		<Value val="0x0">Automatic Detection</Value>

+		<Value val="0x1">Manual Detection</Value>

+	</Values>

+	

+	<Values name="FE_types" type="enum">

+		<Value val="0x0">RFMD</Value>

+		<Value val="0x1">TRIQ</Value>

+		<Value val="0x2">SKW</Value>

+		<Value val="0x3">TRIQ HP</Value>

+		<Value val="0x8">Overrite</Value>

+	</Values>

+

+	<Values name="FE_mode" type="enum">

+		<Value val="0x0">Single Band</Value>

+		<Value val="0x1">Dual Band</Value>

+	</Values>

+

+    <!-- ******************************************************* -->

+    <!-- ******************************************************* -->

+    <!--                                                       	 -->

+    <!-- Groups and Commands                                   	 -->

+    <!--                                                       	 -->

+    <!-- ******************************************************* -->

+    <!-- ******************************************************* -->

+    <!-- ================================================================== -->

+    <Command name="HCI Link Control Commands" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="HCI_Inquiry" type="sc" opcode="0x0401">

+        <Cat>Spec 1.1</Cat>

+        <Param type="x" size="3" prop="r">

+            <Name>LAP</Name>

+            <Default>"9E8B33"</Default>

+            <Desc>The LAP from which the inquiry access code should be derived</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Inquiry Length</Name>

+            <Default>0x04</Default>

+            <Desc>Maximum amount of time in 1.28 sec before the Inquiry is halted</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Number of Responses</Name>

+            <Default>0x00</Default>

+            <Desc>Maximum number of responses before the Inquiry is halted.  0 - Unlimited</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Inquiry_Cancel" type="sc" opcode="0x0402">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Periodic_Inquiry_Mode" type="sc" opcode="0x0403">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="2">

+            <Name>Max Period Length</Name>

+            <Default>0x0008</Default>

+            <Desc>Maximum amount of time in 1.28s specified between consecutive inquiries</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Min Period Length</Name>

+            <Default>0x0007</Default>

+            <Desc>Minimum amount of time in 1.28s specified between consecutive inquiries</Desc>

+        </Param>

+        <Param type="x" size="3" prop="r">

+            <Name>LAP</Name>

+            <Default>"9E8B33"</Default>

+            <Desc>LAP from which the inquiry access code should be derived when the inquiry procedure is made</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Inquiry Length</Name>

+            <Default>0x04</Default>

+            <Desc>Maximum amount of time in 1.28s before the Inquiry is halted (0x00 - 0x30)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Number of Responses</Name>

+            <Default>0x00</Default>

+            <Desc>Maximum number of responses from the Inquiry before the Inquiry is halted. 0 - Unlimited</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Exit_Periodic_Inquiry_Mode" type="sc" opcode="0x0404">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Create_Connection" type="sc" opcode="0x0405">

+        <Cat>Spec 1.1</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2" valtype="AclType">

+            <Name>Packet Types Allowed</Name>

+            <Default>0x0018</Default>

+            <Desc>0x018 - DM1 and DH1</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="PageScanRepetitionMode">

+            <Name>Page Scan Repetition Mode</Name>

+            <Default>0x01</Default>

+            <Desc>R0=0, R1=1, R2=2</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0x00</Default>

+            <Desc>Must be set to 0x00 (from spec 1.2)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Clock Offset</Name>

+            <Default>0x0000</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Role Switch allowed</Name>

+            <Default>0x00</Default>

+            <Desc>M/S switch not allowed=0, Allow M/S switch=1</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Disconnect" type="sc" opcode="0x0406">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="DisconnectReason">

+            <Name>Reason</Name>

+            <Default>0x13</Default>

+            <Desc>Reason for disconnection</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+            <Default>HCI_Disconnect</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Add_SCO_Connection" type="sc" opcode="0x0407">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2" valtype = "ScoType">

+            <Name>Packet Types Allowed</Name>

+            <Default>0x0080</Default>

+            <Desc>HV3 packet only</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+            <Default>HCI_Add_SCO_Connection</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Create_Connection_Cancel" type="sc" opcode="0x0408">

+        <Cat>Spec 1.2</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Accept_Connection_Request" type="sc" opcode="0x0409">

+        <Cat>Spec 1.1</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Role">

+            <Name>Role</Name>

+            <Default>0x01</Default>

+            <Desc>0 - Become the Master for this connection; 1 - Remain the Slave for this connection</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Reject_Connection_Request" type="sc" opcode="0x040a">

+        <Cat>Spec 1.1</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="RejectReason">

+            <Name>Reason</Name>

+            <Default>0x0D</Default>

+            <Desc>Host Reject Error Code</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Link_Key_Request_Reply" type="sc" opcode="0x040b">

+        <Cat>Spec 1.1</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+        <Param type="x" size="16" prop="rs">

+            <Name>Link Key</Name>

+            <Default>"00000000000000000000000000000000"</Default>

+            <Desc>Link Key for the associated BD_ADDR</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Link_Key_Request_Negative_Reply" type="sc" opcode="0x040c">

+        <Cat>Spec 1.1</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_PIN_Code_Request_Reply" type="sc" opcode="0x040d">

+        <Cat>Spec 1.1</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Pin Code Length</Name>

+            <Default>0x01</Default>

+            <Desc>The length, in bytes, of the PIN code to be used</Desc>

+        </Param>

+        <Param type="s" size="len" prop="r">

+            <Name>Pin Code</Name>

+            <Default>"ACBDEFGHIJKLMNOP"</Default>

+            <Desc>PIN code for the device that is to be connected</Desc>

+        </Param>

+        <Param type="x" size="16-len" prop="h">

+            <Name></Name>

+            <Value>"00"</Value>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_PIN_Code_Request_Negative_Reply" type="sc" opcode="0x040e">

+        <Cat>Spec 1.1</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Change_Connection_Packet_Type" type="sc" opcode="0x040f">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2" valtype="AclScoTypes">

+            <Name>Packet Types Allowed</Name>

+            <Default>0x0C18</Default>

+            <Desc>ACL or SCO packet types</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Authentication_Requested" type="sc" opcode="0x0411">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Set_Connection_Encryption" type="sc" opcode="0x0413">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="OffOn">

+            <Name>Encryption Enable</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Turn Link Level Encryption OFF, 1 - Turn Link Level Encryption ON</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Change_Connection_Link_Key" type="sc" opcode="0x0415">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Master_Link_Key" type="sc" opcode="0x0417">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" valtype="LinkKeyFlag">

+            <Name>Key Flag</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Use Semi-permanent Link Keys, 1 - Use Temporary Link Key</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Remote_Name_Request" type="sc" opcode="0x0419">

+        <Cat>Spec 1.1</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="PageScanRepetitionMode">

+            <Name>Page Scan Repetition Mode</Name>

+            <Default>0x01</Default>

+            <Desc>0 - R0(contineus scan), 1 - R1(Tpage scan &lt;= 1.28s); 2 - R2(T page scan &lt;= 2.56s)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0x00</Default>

+            <Desc>Must be set to 0x00 (from spec 1.2)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Clock Offset</Name>

+            <Default>0x0000</Default>

+            <Desc>Bit 16.2 of CLKslave-CLKmaster.  If bit 15 is 0,  Clock Offset invalid </Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Remote_Name_Request_Cancel" type="sc" opcode="0x041A">

+        <Cat>Spec 1.2</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Remote_Supported_Features" type="sc" opcode="0x041b">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Remote_Extended_Features" type="sc" opcode="0x041c">

+        <Cat>Spec 1.2</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Page Number</Name>

+            <Default>0x00</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Remote_Version_Information" type="sc" opcode="0x041d">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Clock_Offset" type="sc" opcode="0x041f">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_LMP_Handle" type="sc" opcode="0x0420">

+        <Cat>Spec 1.2</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc>Should be a voice connection handle</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>LMP_Handle</Name>

+            <Default>"0x00"</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Reserved</Name>

+            <Default>0x00000000</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Setup_Synchronous_Connection" type="sc" opcode="0x0428">

+        <Cat>Spec 1.2</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Transmit_Bandwidth</Name>

+            <Default>0x1f40</Default>

+            <Desc>Transmit bandwidth in octets per second</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Receive_Bandwidth</Name>

+            <Default>0x1f40</Default>

+            <Desc>Receive bandwidth in octets per second</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Max_Latency</Name>

+            <Default>0xFFFF</Default>

+            <Desc>an upper limit (in ms) of the size of: (e)SCO instant + retransmission window + reserved slots, or don't care (0xFFFF).</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Voice_Setting</Name>

+            <Default>0x0060</Default>

+            <Desc>voice settings</Desc>

+            

+            <!--

+<Param type="u" size="2" bits="2" valtype="VS_InputCoding">

+		<Name>Input Coding</Name>

+		<Default>0</Default>

+</Param>

+<Param type="u" size="2" bits="2" valtype="VS_InputDataFormat">

+		<Name>Input Data Format</Name>

+		<Default>0</Default>

+</Param>

+<Param type="u" size="2" bits="1" valtype="VS_InputSampleSize">

+		<Name>Input Sample Size</Name>

+		<Default>0</Default>

+		<Desc>Only for Linear PCM</Desc>

+</Param>

+<Param type="u" size="2" bits="3">

+		<Name>Linear PCM Bit Pos</Name>

+		<Default>0</Default>

+		<Desc>Only for Linear PCM</Desc>

+</Param>

+<Param type="u" size="2" bits="2" valtype="VS_AirCodingFormat">

+		<Name>Air Coding Format</Name>

+		<Default>0</Default>

+		<Desc>Only for Linear PCM</Desc>

+</Param>

+-->

+            

+        </Param>

+        <Param type="u" size="1" valtype="Retransmission_Effort">

+            <Name>Retransmission_Effort</Name>

+            <Default>0xFF</Default>

+            <Desc>0x00 - no retr. 0x01 - optimize for power consumption, 0x02 - optimize for link quality, 0xFF - don't care</Desc>

+        </Param>

+        <Param type="u" size="2" valtype="ScoType2">

+            <Name>Packet_Type</Name>

+            <Default>0x3F</Default>

+            <Desc>0x01-HV1, 0x02-HV2, 0x04-HV3, 0x08-EV3, 0x10-EV4, 0x20-EV5, 0x004-No2EV3, 0x008-No3EV3, 0x01-No2EV5, 0x02-No3EV5, 0x3F - All</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Accept_Synchronous_Connection_Request" type="sc" opcode="0x0429">

+        <Cat>Spec 1.2</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>Get_Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Transmit_Bandwidth</Name>

+            <Default>0xFFFFFFFF</Default>

+            <Desc>Maximum possible transmit bandwidth in octets per second, or don't care (0xFFFFFFFF)</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Receive_Bandwidth</Name>

+            <Default>0xFFFFFFFF</Default>

+            <Desc>Maximum possible receive bandwidth in octets per second, or don't care (0xFFFFFFFF)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Max_Latency</Name>

+            <Default>0xFFFF</Default>

+            <Desc>an upper limit (in ms) of the size of: (e)SCO instant + retransmission window + reserved slots, or don't care (0xFFFF).</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Content_Format</Name>

+            <Default>0x60</Default>

+            <Desc>voice settings</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Retransmission_Effort">

+            <Name>Retransmission_Effort</Name>

+            <Default>0xFF</Default>

+            <Desc>0x00 - no retr. 0x01 - optimize for power consumption, 0x02 - optimize for link quality, 0xFF - don't care</Desc>

+        </Param>

+        <Param type="u" size="2" valtype="ScoType2">

+            <Name>Packet_Type</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0x01-HV1, 0x02-HV2, 0x04-HV3, 0x08-EV3, 0x10-EV4, 0x20-EV5</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Reject_Synchronous_Connection_Request" type="sc" opcode="0x042a">

+        <Cat>Spec 1.2</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="RejectReason">

+            <Name>Reason</Name>

+            <Default>0x0D</Default>

+            <Desc>Host Reject Error Code</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+            <Default>HCI_Reject_Synchronous_Connection_Request</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_IO_Capability_Response" type="sc" opcode="0x042b">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote involved in simple pairing process</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Io Capability">

+            <Name>Io Capability</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 -	DisplayOnly, 0x01 - DisplayYesNo, 0x02 - KeyboardOnly, 0x03 - NoInputNoOutput, 0x04 - 0xFF	Reserved for future use</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="OOB Data Present">

+            <Name>OOB data present</Name>

+            <Default>0x00</Default>

+            <Desc>OOB capability with remote</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Authentication Required">

+            <Name>Authentication Required</Name>

+            <Default>0x00</Default>

+            <Desc>0 - MITM Protection Not Required – Single Profile. Numeric comparison with automatic accept allowed. 1 - MITM Protection Required – Single Profile.  Use IO Capabilities to determine authentication procedure. 2 - MITM Protection Not Required – All Profiles.  Numeric comparison with automatic accept allowed. 3 - MITM Protection Required – All Profiles.  Use IO Capabilities to determine authentication procedure</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote involved in simple pairing process</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_IO_Capability_Request_Negative_Reply" type="sc" opcode="0x0434">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote involved in simple pairing process</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Reason</Name>

+            <Default>0x1F</Default>

+            <Desc>0x1F Unspecified Error , reason 0x37 (Secure Simple Pairing Not Supported By Host) is invalid</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote involved in simple pairing process</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_User_Confirmation_Request_Reply" type="sc" opcode="0x042c">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote involved in simple pairing process</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_User_Confirmation_Request_Negative_Reply" type="sc" opcode="0x042d">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote involved in simple pairing process</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_User_Passkey_request_reply_command" type="sc" opcode="0x042e">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote involved in simple pairing process</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Numeric value  Number of Responses</Name>

+            <Default>0x0000</Default>

+            <Desc>Numeric value (Passkey) entered by user. Valid values are decimal 000000-999999</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_User_Passkey_Request_Negative_Reply" type="sc" opcode="0x042f">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote involved in simple pairing process</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Remote_OOB_Data_Request_Negative_Reply" type="sc" opcode="0x0433">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote involved in simple pairing process</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Send_Keypress_Notification" type="sc" opcode="0x0C60">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Notification_Type">

+            <Name>Notification Type</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Passkey entry started ,1 - Passkey digit entered ,2 - Passkey digit erased ,3 - Passkey cleared ,4 - Passkey entry completed</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote involved in simple pairing process</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Keypress_Notification_Event" type="se" opcode="0x3C">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Notification_Type">

+            <Name>Notification_Type</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Passkey entry started ,1 - Passkey digit entered ,2 - Passkey digit erased ,3 - Passkey cleared ,4 - Passkey entry completed</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_User_Passkey_Notification_event" type="se" opcode="0x3B">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Passkey</Name>

+            <Default>0x00</Default>

+            <Desc>Passkey to be displayed. Valid values are decimal 000000 – 999999</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Remote_Host_Supported_Features_Notification_Event" type="se" opcode="0x3D">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="x" size="8">

+            <Name>Host Features</Name>

+            <Default>"0000000000000000"</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Remote_OOB_Data_Request_Reply" type="sc" opcode="0x0430">

+        <Cat>Lisbon</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="x" size="16" prop="r">

+            <Name>C</Name>

+            <Default>"00000000000000000000000000000002"</Default>

+            <Desc>Simple pairing hash C</Desc>

+        </Param>

+        <Param type="x" size="16" prop="r">

+            <Name>R</Name>

+            <Default>"00000000000000000000000000000001"</Default>

+            <Desc>Simple pairing Randomizer R</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the Remote involved in simple pairing process</Desc>

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="HCI Link Policy Commands" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="HCI_Hold_Mode" type="sc" opcode="0x0801">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Hold Mode Max Interval</Name>

+            <Default>0x1000</Default>

+            <Desc>Maximum acceptable number of Baseband slots to wait in Hold Mode</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Hold Mode Min interval</Name>

+            <Default>0x0800</Default>

+            <Desc>Minimum acceptable number of Baseband slots to wait in Hold Mode</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Sniff_Mode" type="sc" opcode="0x0803">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Sniff Max Interval</Name>

+            <Default>0x0800</Default>

+            <Desc>Maximum acceptable number of Baseband slots between each sniff period (1 - 0xFFFF)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Sniff Min interval</Name>

+            <Default>0x0700</Default>

+            <Desc>Minimum acceptable number of Baseband slots between each sniff period (1 - 0xFFFF)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Sniff Attempt</Name>

+            <Default>0x0008</Default>

+            <Desc>Number of Baseband slots for sniff attempt (0 - 0xFFFF)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Sniff Timeout</Name>

+            <Default>0x0002</Default>

+            <Desc>Number of Baseband slots for sniff timeout (0 - 0xFFFF)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Exit_Sniff_Mode" type="sc" opcode="0x0804">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Park_Mode" type="sc" opcode="0x0805">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Beacon Max Interval</Name>

+            <Default>0x0100</Default>

+            <Desc>Maximum acceptable number of Baseband slots between consecutive beacons (0 - 0xFFFF)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Beacon Min interval</Name>

+            <Default>0x0100</Default>

+            <Desc>Minimum acceptable number of Baseband slots between consecutive beacons (0 - 0xFFFF)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Exit_Park_Mode" type="sc" opcode="0x0806">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_QoS_Setup" type="sc" opcode="0x0807">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Flags</Name>

+            <Default>0x00</Default>

+            <Desc>Reserved for Future Use</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="ServiceType">

+            <Name>Service Type</Name>

+            <Default>0x01</Default>

+            <Desc>0 - No Traffic; 1 - Best Effort; 2 - Guaranteed</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Token Rate</Name>

+            <Default>0xFFFFFFFF</Default>

+            <Desc>Token Rate in bytes per second</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Peak Bandwidth</Name>

+            <Default>0x00000000</Default>

+            <Desc>Peak Bandwidth in bytes per second</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Latency</Name>

+            <Default>0xFFFFFFFF</Default>

+            <Desc>Latency in microseconds, 0xFFFFFFFF - do not care</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Delay Variation</Name>

+            <Default>0xFFFFFFFF</Default>

+            <Desc>Delay Variation in microseconds, 0xFFFFFFFF - do not care</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Role_Discovery" type="sc" opcode="0x0809">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Role">

+            <Name>Role</Name>

+            <Default>0x00</Default>

+            <Desc>Current role for this connection handle</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Switch_Role" type="sc" opcode="0x080b">

+        <Cat>Spec 1.1</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Role">

+            <Name>Role</Name>

+            <Default>0x00</Default>

+            <Desc>For this Connection Handle change own Role to 0 - Master; 1 - Slave</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Link_Policy_Settings" type="sc" opcode="0x080c">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2" valtype="LinkPolicy">

+            <Name>Link Policy Settings</Name>

+            <Default>0x0000</Default>

+            <Desc>0 - Disable all LM modes</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Link_Policy_Settings" type="sc" opcode="0x080d">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2" valtype="LinkPolicy">

+            <Name>Link Policy Settings</Name>

+            <Default>0x0003</Default>

+            <Desc>switch, hold, no sniff, no park</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Default_Link_Policy_Settings" type="sc" opcode="0x080e">

+        <Cat>Spec 1.2</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default>HCI_Read_Default_Link_Policy_Settings</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2" valtype="LinkPolicy">

+            <Name>Default Link Policy Settings</Name>

+            <Default>"0x0000"</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Default_Link_Policy_Settings" type="sc" opcode="0x080f">

+        <Cat>Spec 1.2</Cat>

+        <Param type="u" size="2" valtype="LinkPolicy">

+            <Name>Default Link Policy Settings</Name>

+            <Default>0x0003</Default>

+            <Desc>0 - Disable All LM Modes</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Flow_Specification" type="sc" opcode="0x0810">

+        <Cat>Spec 1.2</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Flags</Name>

+            <Default>0x00</Default>

+            <Desc>Reserved for Future Use</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="FlowDirection">

+            <Name>Flow Direction</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Outgoing; 1 - Incoming</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="ServiceType">

+            <Name>Service Type</Name>

+            <Default>0x01</Default>

+            <Desc>0 - No Traffic; 1 - Best Effort; 2 - Guaranteed</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Token Rate</Name>

+            <Default>0x00000000</Default>

+            <Desc>Token Rate in bytes per seconds, 0x00000000 - not specified; 0xFFFFFFFF - maximum available</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Token Bucket Size</Name>

+            <Default>0x00000000</Default>

+            <Desc>Token Bucket Size in bytes, 0x00000000 - not needed; 0xFFFFFFFF - maximum available</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Peak Bandwidth</Name>

+            <Default>0x00000000</Default>

+            <Desc>Peak Bandwidth in bytes per second, 0x00000000 - do not care</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Access Latency</Name>

+            <Default>0xFFFFFFFF</Default>

+            <Desc>Latency in microseconds, 0xFFFFFFFF - do not care</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Sniff_Subrate" type="sc" opcode="0x0811">

+        <Cat>Spec 1.2</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Maximum Latency</Name>

+            <Default>0x0000</Default>

+            <Desc>Maximum latency in slots that the remote device with a link in sniff sub-rate can use[0x0000 - 0xFFFE]</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Min Remote Timeout</Name>

+            <Default>0x0000</Default>

+            <Desc>Maximum sniff sub-rate zero timeout that the remote device should use in slots[0x0000 - 0xFFFE]</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Min Local Timeout</Name>

+            <Default>0x0000</Default>

+            <Desc>Minimum sniff sub-rate zero timeout that the local device should use in slots[0x0000 - 0xFFFE]</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default>HCI_Sniff_Subrate</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="HCI Host Controller &amp; Baseband Commands" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="HCI_Set_Event_Mask" type="sc" opcode="0x0c01">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="8" valtype="EventMask">

+            <Name>Event Mask</Name>

+            <Default>0x000000000003FFFF</Default>

+            <Desc>Mask events to be generated</Desc>

+        </Param>

+        

+        <!--

+<Param type="x" size="8">

+<Name>Event Mask</Name>

+<Default>"000000000003FFFF"</Default>

+<Desc>Mask events to be generated</Desc>

+</Param>

+-->

+        

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Reset" type="sc" opcode="0x0c03">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Set_Event_Filter" type="sc" opcode="0x0c05">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" label="filter_type" valtype="EventFilter">

+            <Name>Filter type</Name>

+            <Default>0x00</Default>

+            <Desc>0-Clear all, 1-Inq result, 2-Connection Setup</Desc>

+        </Param>

+        

+        <Param cond="filter_type.ge.1">

+            <Param type="u" size="1" label="cond_type" valtype="EventCondition">

+                <Name>Result Filter Type</Name>

+                <Default>0x00</Default>

+            </Param>

+            

+            <Param cond="cond_type==1">

+                <Param type="u" size="3">

+                    <Name>Class of Device</Name>

+                    <Default>0x000000</Default>

+                    <Desc>Class of Device for the device</Desc>

+                </Param>

+                <Param type="u" size="3">

+                    <Name>Class of Device Mask</Name>

+                    <Default>0x000000</Default>

+                    <Desc>Class of Device Mask</Desc>

+                </Param>

+            </Param>

+            

+            <Param cond="cond_type==2">

+                <Param type="b" size="6">

+                    <Name>BD Address of the device</Name>

+                    <Default>BD_ADDR</Default>

+                    <Desc />

+                </Param>

+            </Param>

+            

+            <Param type="u" size="1" cond="filter_type==2" valtype="AutoAcceptFlag">

+                <Name>Auto Accept Flag</Name>

+                <Default>0x01</Default>

+            </Param>

+        </Param>

+        

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Flush" type="sc" opcode="0x0c08">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Persistent_Sniff" type="sc" opcode="0x0c5c">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="2">

+            <Name>Persistent Sniff Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Persistent Sniff Interval</Name>

+            <Default>0</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Persistent_Sniff" type="sc" opcode="0x0c5d">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="2">

+            <Name>Sniff Interval</Name>

+            <Default>0x0800</Default>

+            <Desc>Maximum acceptable number of Baseband slots between each sniff period (2 - 0xFFFE)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Persistent Sniff Handle</Name>

+            <Default>0</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Delete_Persistent_Sniff" type="sc" opcode="0x0c5e">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="2">

+            <Name>Sniff Reservation Handle</Name>

+            <Default>0</Default>

+            <Desc>Persistent sniff reservation handle</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Refresh_Encryption_Key" type="sc" opcode="0x0c53">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_PIN_Type" type="sc" opcode="0x0c09">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="PinType">

+            <Name>Pin Type</Name>

+            <Default>0x00</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_PIN_Type" type="sc" opcode="0x0c0a">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" valtype="PinType">

+            <Name>PIN Type</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Variable PIN, 1 - Fixed PIN</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Create_New_Unit_Key" type="sc" opcode="0x0c0b"> 

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Stored_Link_Key" type="sc" opcode="0x0c0d">

+        <Cat>Spec 1.1</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+        </Param>

+        <Param type="u" size="1" valtype="AllLinkKeyFlag">

+            <Name>Read All Flag</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Return Link Key for specified BD_ADDR, 1 - Return all stored Link Keys</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Max Num Keys</Name>

+            <Default>Any</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Num Keys Read</Name>

+            <Default>Any</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Stored_Link_Key" type="sc" opcode="0x0c11">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" label="count">

+            <Name>Num Keys To Write</Name>

+            <Default>0x01</Default>

+            <Desc>Number of Link Keys to Write</Desc>

+        </Param>

+        <Param array="count">

+            <Param type="b" size="6">

+                <Name>BD Address of the Remote</Name>

+                <Default>BD_ADDR</Default>

+                <Desc />

+            </Param>

+            <Param type="x" size="16" prop="r">

+                <Name>Link Key</Name>

+                <Default>"0102030405060708090a0b0c0d0e0f00"</Default>

+                <Desc>Link Key for the associated BD_ADDR</Desc>

+            </Param>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Max Num Keys</Name>

+            <Default>Any</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Delete_Stored_Link_Key" type="sc" opcode="0x0c12">

+        <Cat>Spec 1.1</Cat>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="AllLinkKeyFlag">

+            <Name>Delete All Flag</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Delete only the Link Key for specified BD_ADDR; 1 - Delete all stored Link Keys</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Num Keys Deleted</Name>

+            <Default>Any</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Change_Local_Name" type="sc" opcode="0x0c13">

+        <Cat>Spec 1.1</Cat>

+        <Param type="s" size="248">

+            <Name>New name</Name>

+            <Default>"Bluetooth By Texas Instruments"</Default>

+            <Desc>User Friendly Descriptive Name for the device</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Local_Name" type="sc" opcode="0x0c14">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="s" size="248">

+            <Name>Local Name</Name>

+            <Default></Default>

+            <Desc>User Friendly Descriptive Name for the device</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Connection_Accept_Timeout" type="sc" opcode="0x0c15">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Conn Accept Timeout</Name>

+            <Default>Any</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Connection_Accept_Timeout" type="sc" opcode="0x0c16">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="2">

+            <Name>Conn Accept Timeout</Name>

+            <Default>0x1FA0</Default>

+            <Desc>Connection Accept Timeout measured in Number of Baseband slots (0 - 0xFFFF)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Page_Timeout" type="sc" opcode="0x0c17">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Page Timeout</Name>

+            <Default>Any</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Page_Timeout" type="sc" opcode="0x0c18">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="2">

+            <Name>Page Timeout</Name>

+            <Default>0x2000</Default>

+            <Desc>Page Timeout measured in Number of Baseband slots (0 - 0xFFFF)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Scan_Enable" type="sc" opcode="0x0c19">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="ScanEnable">

+            <Name>Scan Enable</Name>

+            <Default>0x03</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Scan_Enable" type="sc" opcode="0x0c1a">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" valtype="ScanEnable">

+            <Name>Scan Enable</Name>

+            <Default>0x00</Default>

+            <Desc>0 - No Scans enabled, 1 - Inquiry scan enabled, 2 - Page scan enabled, 3 - both enabled</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_PageScan_Activity" type="sc" opcode="0x0c1b">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Page Scan Interval</Name>

+            <Default>Any</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Page Scan Window</Name>

+            <Default>Any</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_PageScan_Activity" type="sc" opcode="0x0c1c">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="2">

+            <Name>PageScan Interval</Name>

+            <Default>0x0800</Default>

+            <Desc>Interval between 2 consecutive Page Scans, (0x0012 - 0x1000)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>PageScan Window</Name>

+            <Default>0x0012</Default>

+            <Desc>Duration of each Page Scan (0x0012 - 0x1000)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_InquiryScan_Activity" type="sc" opcode="0x0c1d">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Inquiry Scan Interval</Name>

+            <Default>0x0800</Default>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Inquiry Scan Window</Name>

+            <Default>0x0012</Default>

+            <Desc>Duration of each Page Scan (0x0012 - 0x1000)</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_InquiryScan_Activity" type="sc" opcode="0x0c1e">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="2">

+            <Name>InquiryScan Interval</Name>

+            <Default>0x1000</Default>

+            <Desc>Interval between 2 consecutive Inquiry Scans (0x0012 - 0x1000 time slots)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>InquiryScan Window</Name>

+            <Default>0x0012</Default>

+            <Desc>Duration of each Inquiry Scan Window (0x0012 - 0x1000 time slots)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Authentication_Enable" type="sc" opcode="0x0c1f">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>Authentication Enable</Name>

+            <Default>0x01</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Authentication_Enable" type="sc" opcode="0x0c20">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>Authentication Enable</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Authentication disabled, 1 - Authentication enabled for all connections</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Class_of_Device" type="sc" opcode="0x0c23">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="x" size="3">

+            <Name>Class Of Device</Name>

+            <Default>"000000"</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Class_of_Device" type="sc" opcode="0x0c24">

+        <Cat>Spec 1.1</Cat>

+        <Param type="x" size="3">

+            <Name>Class of Device</Name>

+            <Default>"000000"</Default>

+            <Desc>Class of Device for the device</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Voice_Setting" type="sc" opcode="0x0c25">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Voice Settings</Name>

+            <Default>Any</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Voice_Setting" type="sc" opcode="0x0c26">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="2">

+            <Name>Voice settings bitmap</Name>

+            <Default>0x0060</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Automatic_Flush_Timeout" type="sc" opcode="0x0c27">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Handle of connection</Name>

+            <Default>Handle</Default>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Flash timeout</Name>

+            <Default>0</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Automatic_Flush_Timeout" type="sc" opcode="0x0c28">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Flush Timeout</Name>

+            <Default>0x0000</Default>

+            <Desc>0 - No Automatic Flush, otherwise flush timeout in slots (0 - 0x07FF)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Handle of connection</Name>

+            <Default>Handle</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Num_Broadcast_Retransmissions" type="sc" opcode="0x0c29">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Num Broadcast Retran</Name>

+            <Default>0x01</Default>

+            <Desc>Number of Broadcast Retransmissions</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Num_Broadcast_Retransmissions" type="sc" opcode="0x0c2a">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1">

+            <Name>Num Broadcast Retran</Name>

+            <Default>0x01</Default>

+            <Desc>Number of Broadcast Retransmissions</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Hold_Mode_Activity" type="sc" opcode="0x0c2b">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="HoldModeActivity">

+            <Name>Hold Mode Activity</Name>

+            <Default>0x00</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Hold_Mode_Activity" type="sc" opcode="0x0c2c">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" valtype="HoldModeActivity">

+            <Name>Hold Mode Activity</Name>

+            <Default>0x00</Default>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Transmit_Power_Level" type="sc" opcode="0x0c2d">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="TransmitLevelType">

+            <Name>Type</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Read Current Transmit Power Level, 1 - Read Maximum Transmit Power Level</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="d" size="1">

+            <Name>Transmit Power Level</Name>

+            <Default>0</Default>

+            <Desc>dBm</Desc>

+        </Param>

+    </Command>

+

+     <Command name="HCI_Read_Enhanced_Transmit_Power_Level" type="sc" opcode="0x0c68">

+        <Cat>Spec 3.0</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="TransmitLevelType">

+            <Name>Type</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Read Current Transmit Power Level, 1 - Read Maximum Transmit Power Level</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="d" size="1">

+            <Name>Transmit Power Level GFSK</Name>

+            <Default>0</Default>

+            <Desc>dBm</Desc>

+        </Param>

+           <Param type="d" size="1">

+            <Name>Transmit Power Level DQPSK</Name>

+            <Default>0</Default>

+            <Desc>dBm</Desc>

+       </Param>

+ 			<Param type="d" size="1">

+            <Name>Transmit Power Level 8DPSK</Name>

+            <Default>0</Default>

+            <Desc>dBm</Desc>

+        </Param>

+    </Command>

+

+    <Command name="HCI_Read_LE_Host_Support" type="sc" opcode="0x0C6C">

+        <Cat>Tokyo</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>LE Host Support</Name>

+            <Default>0</Default>

+            <Desc>Support Of the Host of LE</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Simultaneous LE Host Support</Name>

+            <Default>0</Default>

+            <Desc>Support Of the Host of LE in Parallel to BT</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_LE_Host_Support" type="sc" opcode="0x0C6D">

+        <Cat>Tokyo</Cat>

+        <Param type="u" size="1">

+            <Name>LE Host Support</Name>

+            <Default>0x00</Default>

+            <Desc>Support of LE by Host</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Simultaneous LE Host Support</Name>

+            <Default>0x00</Default>

+            <Desc>Support of LE by Host in Parallel to BTH</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_SCO_Flow_Control_Enable" type="sc" opcode="0x0c2e">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>SCO Flow Control Enable</Name>

+            <Default>0x00</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_SCO_Flow_Control_Enable" type="sc" opcode="0x0c2f">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>SCO Flow Control Enable</Name>

+            <Default>0x00</Default>

+            <Desc>0 - no flow control, 1 - Num Packets Completed event should include SCO information</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Set_Host_Controller_To_Host_Flow_Control" type="sc" opcode="0x0c31">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" valtype="FlowControlEnable">

+            <Name>Flow Control Enable</Name>

+            <Default>0x00</Default>

+            <Desc>Flow control in direction from Host Controller to Host 0 - OFF, 1 - ON</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Host_Buffer_Size" type="sc" opcode="0x0c33">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="2">

+            <Name>Host ACl Data Packet Length</Name>

+            <Default>0x0000</Default>

+            <Desc>Maximum length of the data portion of each HCI ACL Data Packet that the Host is able to accept</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Host SCO Data Packet Length</Name>

+            <Default>0x00</Default>

+            <Desc>Maximum length of the data portion of each HCI SCO Data Packet that the Host is able to accept</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Host Total Num ACL Data Packets</Name>

+            <Default>0x0000</Default>

+            <Desc>Total number of HCI ACL Data Packets that can be stored in the data buffers of the Host</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Host Total Num SCO Data Packets</Name>

+            <Default>0x0000</Default>

+            <Desc>Total number of HCI SCO Data Packets that can be stored in the data buffers of the Host</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Host_Number_Of_Completed_Packets" type="sc" opcode="0x0c35">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" label="count">

+            <Name>Number Of Handles</Name>

+            <Default>0x01</Default>

+            <Desc>The number of Handles and parameters pairs contained in this command</Desc>

+        </Param>

+        <Param array="count">

+            <Param type="h" size="2">

+                <Name>Connection Handle</Name>

+                <Default>Handle</Default>

+                <Desc />

+            </Param>

+            <Param type="u" size="2">

+                <Name>Host Num Of Completed Packets</Name>

+                <Default>0x0001</Default>

+                <Desc>The number of HCI Data Packets completed since the previous time the event was returned</Desc>

+            </Param>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Link_Supervision_Timeout" type="sc" opcode="0x0c36">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Link Supervision Timeout</Name>

+            <Default>0x7D00</Default>

+            <Desc>0 - No Link_Supervision_Timeout, otherwise - timeout Measured in Number of Baseband slots (0 - 0xFFFF)</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Link_Supervision_Timeout" type="sc" opcode="0x0c37">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Link Supervision Timeout</Name>

+            <Default>0x7D00</Default>

+            <Desc>0 - No Link_Supervision_Timeout, otherwise - timeout Measured in Number of Baseband slots (0 - 0xFFFF)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Number_Of_Supported_IAC" type="sc" opcode="0x0c38">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Num Support IAC</Name>

+            <Default>0x05</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Current_IAC_LAP" type="sc" opcode="0x0c39">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" label="count">

+            <Name>Num Current IAC</Name>

+            <Default>0x01</Default>

+            <Desc />

+        </Param>

+        <Param type="x" size="3" prop="r" array="count">

+            <Name>IAC LAP</Name>

+            <Default>"9E8B33"</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Current_IAC_LAP" type="sc" opcode="0x0c3a">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" label="count">

+            <Name>NumCurrentIAC</Name>

+            <Default>0x01</Default>

+            <Desc>Number of IAC which are currently in use to listen for during an Inquiry Scan</Desc>

+        </Param>

+        <Param type="x" size="3" prop="r" array="count">

+            <Name>IAC LAP</Name>

+            <Default>"9E8B00"</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+   

+    <Command name="HCI_Set_AFH_Host_Channel_Classification" type="sc" opcode="0x0c3f">

+        <Cat>Spec 1.2</Cat>

+        <Param type="x" size="10">

+            <Name>Channel Map</Name>

+            <Default>"FFFFFFFFFFFFFFFFFF7F"</Default>

+            <Desc>0-79 bits</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Inquiry_Scan_Type" type="sc" opcode="0x0c42">

+        <Cat>Spec 1.2</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="ScanType">

+            <Name>Inquiry Scan Type</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Mandatory: Standard Scan (default); 1 - Optional: Interlaced Scan</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Inquiry_Scan_Type" type="sc" opcode="0x0c43">

+        <Cat>Spec 1.2</Cat>

+        <Param type="u" size="1" valtype="ScanType">

+            <Name>Inquiry Scan Type</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Mandatory: Standard Scan (default); 1 - Optional: Interlaced Scan</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Inquiry_Mode" type="sc" opcode="0x0c44">

+        <Cat>Spec 1.2</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="InquiryMode">

+            <Name>Inquiry Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Standard Inquiry Result event format; 1 - Inquiry Result format with RSSI</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Inquiry_Mode" type="sc" opcode="0x0c45">

+        <Cat>Spec 1.2</Cat>

+        <Param type="u" size="1" valtype="InquiryMode">

+            <Name>Inquiry Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Standard Inquiry Result event format; 1 - Inquiry Result format with RSSI</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Page_Scan_Type" type="sc" opcode="0x0c46">

+        <Cat>Spec 1.2</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="ScanType">

+            <Name>Page Scan Type</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Mandatory: Standard Scan (default); 1 - Optional: Interlaced Scan</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Page_Scan_Type" type="sc" opcode="0x0c47">

+        <Cat>Spec 1.2</Cat>

+        <Param type="u" size="1" valtype="ScanType">

+            <Name>Page Scan Type</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Mandatory: Standard Scan (default); 1 - Optional: Interlaced Scan</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_AFH_Channel_Assessment_Mode" type="sc" opcode="0x0c48">

+        <Cat>Spec 1.2</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>AFH Channel Assessment Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 = local channel assessment disabled, 0x01 = local channel assessment enabled</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_AFH_Channel_Assessment_Mode" type="sc" opcode="0x0c49">

+        <Cat>Spec 1.2</Cat>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>AFH Channel Assessment Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 = local channel assessment disabled 0x01 = local channel assessment enabled</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Extended_Inquiry_Response" type="sc" opcode="0x0C52">

+        <Cat>Spec 3.0</Cat>

+        <Param type="u" size="1">

+            <Name>FEC Required</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 o FEC is not required (DH packet might be sent) 0x01 - only DM packet will be sent</Desc>

+        </Param>

+        <Param type="x" size="240">

+            <Name>Inquiry Response Data</Name>

+            <Default></Default>

+            <Desc>Will be paddad with zero to 240 bytes</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Extended_Inquiry_Response" type="sc" opcode="0x0C51">

+        <Cat>Spec 3.0</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Success</Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>FEC Required</Name>

+            <Default></Default>

+        </Param>

+        <Param type="x" size="240">

+            <Name>Inquiry Response Data</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Simple_Pairing_Mode" type="sc" opcode="0x0C56">

+        <Cat>Lisbon</Cat>

+        <Param type="u" size="1" valtype="Simple_Pairing_Mode">

+            <Name>Simple_Pairing_Mode</Name>

+            <Default>0x00</Default>

+            <Desc>Simple pairing mode</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Simple_Pairing_Mode" type="sc" opcode="0x0C55">

+        <Cat>Lisbon</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Simple Pairing Mode</Name>

+            <Default>0</Default>

+            <Desc>Simple pairing mode: 0 - Uninitialized, 1- Enabled</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Enhanced_Flush" type="sc" opcode="0x0c5f">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Packet Type</Name>

+            <Default>0x0</Default>

+            <Desc/>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Status_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Accept_Sniff_Request" type="sc" opcode="0x0431">

+        <Cat>Lisbon</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Persistent Sniff Handle</Name>

+            <Default>0</Default>

+            <Desc>Persistent Sniff Handle.0 - no assosiation with persistent sniff</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Reject_Sniff_Request" type="sc" opcode="0x0432">

+        <Cat>Lisbon</Cat>

+        <Param type="h" size="2">

+            <Name>Handle</Name>

+            <Default>Handle</Default>

+            <Desc>Connection Handle</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Local_OOB_Data" type="sc" opcode="0x0C57">

+        <Cat>Lisbon</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="x" size="16" prop="r">

+            <Name>C</Name>

+            <Default>"00000000000000000000000000000000"</Default>

+            <Desc>Simple pairing hash C</Desc>

+        </Param>

+        <Param type="x" size="16" prop="r">

+            <Name>R</Name>

+            <Default>"00000000000000000000000000000000"</Default>

+            <Desc>Simple pairing Randomizer R</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Inquiry_Response_Transmit_Power_level" type="sc" opcode="0x0C58">

+        <Cat>Lisbon</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Desc>This command will read the inquiry response Transmit Power level used to transmit the FHS and EIR data packets. This can be used directly in the Tx Power Level EIR data type, -70dBm to +20dBm</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>Tx Power</Name>

+            <Desc>dBm</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Inquiry_Transmit_Power_Level" type="sc" opcode="0x0C59">

+        <Cat>Lisbon</Cat>

+        <Param type="u" size="1">

+            <Name>Tx_Power</Name>

+            <Default>10</Default>

+            <Desc>This command is used to write the transmit power level used to transmit the inquiry (ID) packets.  The Controller should use the supported TX power level closest to the Tx_Power parameter</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Default_Erroneous_Data_Reporting" type="sc" opcode="0x0C5A">

+        <Cat>Spec 3.0</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Erroneous_Data_Reporting">

+            <Name>Erroneous Data Reporting</Name>

+            <Default>0x00</Default>

+            <Desc>Erroneous data reporting methoid is currently used</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Default_Erroneous_Data_Reporting" type="sc" opcode="0x0C5B">

+        <Cat>Spec 3.0</Cat>

+        <Param type="u" size="1" valtype="Erroneous_Data_Reporting">

+            <Name>Erroneous Data Reporting</Name>

+            <Default>0x00</Default>

+            <Desc>Erroneous data reporting methoid that will be used for new connections </Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="HCI Informational Parameters" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="HCI_Read_Local_Version_Information" type="sc" opcode="0x1001">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Success</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="HCIVersion">

+            <Name>HCI Version</Name>

+            <Default>0x00</Default>

+        </Param>

+        <Param type="u" size="2">

+            <Name>HCI Revision</Name>

+            <Default>0x0000</Default>

+            <Desc>Revision of the Current HCI in the Bluetooth device</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="LMPVersion">

+            <Name>LMP Version</Name>

+            <Default>0x00</Default>

+            <Desc>Version of the Current LMP in the Bluetooth device</Desc>

+        </Param>

+        <Param type="u" size="2" valtype="CompID">

+            <Name>Manufacturer Name</Name>

+            <Default>0x0000</Default>

+            <Desc>Manufacturer name of the bluetooth device</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>LMP Subversion</Name>

+            <Default>0x0000</Default>

+            <Desc>Subversion of the Current LMP in the Bluetooth device</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Local_Supported_Commands" type="sc" opcode="0x1002">

+        <Cat>Spec 1.2</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="x" size="64">

+            <Name>Supported Commands</Name>

+            <Default>"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"</Default>

+            <Desc>Supported commands bitmask</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Local_Supported_Features" type="sc" opcode="0x1003">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="x" size="8">

+            <Name>Supported Commands</Name>

+            <Default>"0000000000000000"</Default>

+            <Desc>Supported features bitmask</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Local_Extended_Features" type="sc" opcode="0x1004">

+        <Cat>Spec 1.2</Cat>

+        <Param type="u" size="1">

+            <Name>Page Number</Name>

+            <Default>0x00</Default>

+            <Desc>0 - the only available page</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Page Number</Name>

+            <Default>0x00</Default>

+            <Desc>0 - the only available page</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Maximum Page Number</Name>

+            <Default>0x00</Default>

+            <Desc>0 - the only available maximum page</Desc>

+        </Param>

+        <Param type="x" size="8">

+            <Name>Extended LMP Features</Name>

+            <Default>"0000000000000000"</Default>

+            <Desc>Supported extended features bitmask</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Buffer_Size" type="sc" opcode="0x1005">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Success</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>ACL Data Packet Length</Name>

+            <Default>0x0000</Default>

+            <Desc>Expecting parameter value</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>SCO Data Packet Length</Name>

+            <Default>0x00</Default>

+            <Desc>Expecting parameter value</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Total Num ACL Data Packets</Name>

+            <Default>0x0000</Default>

+            <Desc>Expecting parameter value</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Total Num SCO Data Packets</Name>

+            <Default>0x0000</Default>

+            <Desc>Expecting parameter value</Desc>

+        </Param>

+    </Command>

+        

+    <Command name="HCI_Read_BD_ADDR" type="sc" opcode="0x1009">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Address of the device</Desc>

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="HCI Status Parameters" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="HCI_Read_Failed_Contact_Counter" type="sc" opcode="0x1401">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Failed contact Counter</Name>

+            <Default>Any</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Reset_Failed_Contact_Counter" type="sc" opcode="0x1402">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Link_Quality" type="sc" opcode="0x1403">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Link Quality</Name>

+            <Default>0xFF</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_RSSI" type="sc" opcode="0x1405">

+        <Cat>Spec 1.1</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+        </Param>

+        <Param type="d" size="1">

+            <Name>RSSI</Name>

+            <Default>0</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_AFH_Channel_Map" type="sc" opcode="0x1406">

+        <Cat>Spec 1.2</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>AFH Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 = AFH disable, 0x01 = AFH enable</Desc>

+        </Param>

+        <Param type="x" size="10">

+            <Name>AFH Channel Map</Name>

+            <Default>"00000000000000000000"</Default>

+            <Desc>last AFH channel map to be broadcasted</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Clock" type="sc" opcode="0x1407">

+        <Cat>Spec 1.2</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="WhichClock">

+            <Name>Which Clock</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 = Local Clock, 0x01 = Piconet Clock</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Clock</Name>

+            <Default>0x00000000</Default>

+            <Desc>BT clock</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Accuracy</Name>

+            <Default>0x0000</Default>

+            <Desc />

+        </Param>

+    </Command>

+     <Command name="HCI_Read_Encryption_Key_Size" type="sc" opcode="0x1408">

+        <Cat>Spec 3.0</Cat>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+        </Param>

+        <Param type="d" size="1">

+            <Name>KEY_SIZE</Name>

+            <Default>0</Default>

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="HCI Testing Commands" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="HCI_Read_Loopback_Mode" type="sc" opcode="0x1801">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="LoopbackMode">

+            <Name>Loopback Mode</Name>

+            <Default>0x00</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Loopback_Mode" type="sc" opcode="0x1802">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" valtype="LoopbackMode">

+            <Name>Loopback Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0 - No Loopback mode enabled, 1 - Enable Local Loopback, 2 - Enable Remote Loopback</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Enable_Device_Under_Test_Mode" type="sc" opcode="0x1803">

+        <Cat>Spec 1.1</Cat>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Write_Simple_Pairing_Debug_Mode" type="sc" opcode="0x1804">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" valtype="SPDebugMode">

+            <Name>Simple_Pairing_Debug_Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Simple Pairing debug mode disabled (default), 1 - Simple pairing debug mode enabled, 0x02 - 0xFF - Reserved for future use</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <!-- ******************************************************* -->

+    <!-- ******************************************************* -->

+    <!--                                                         -->

+    <!-- Hci Events                                             	-->

+    <!--                                                       	-->

+    <!-- ******************************************************* -->

+    <!-- ******************************************************* -->

+    <!-- ================================================================== -->

+    <Command name="HCI Events" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="HCI_Inquiry_Complete_Event" type="se" opcode="0x0001">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Inquiry command completed successfully, otherwise Inquiry command failed</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Inquiry_Result_Event" type="se" opcode="0x0002">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" label="count">

+            <Name>Number of Responses</Name>

+            <Default>0x01</Default>

+            <Desc>Number of responses from the Inquiry</Desc>

+        </Param>

+        <Param array="count">

+            <Param type="b" size="6">

+                <Name>BD_ADDR responded</Name>

+                <Default>Get_Bd_Addr</Default>

+                <Desc />

+            </Param>

+            <Param type="u" size="1" valtype="PageScanRepetitionMode">

+                <Name>Page Scan Repetition Mode</Name>

+                <Default>0x00</Default>

+                <Desc>0 - R0, 1 - R1, 2 - R2</Desc>

+            </Param>

+            <Param type="u" size="1" valtype="PeriodMode">

+                <Name>Page Scan Period Mode</Name>

+                <Default>0x00</Default>

+                <Desc>0 - P0, 1 - P1, 2 - P2</Desc>

+            </Param>

+            <Param type="u" size="1" valtype="PageScanMode">

+                <Name>Page Scan Mode</Name>

+                <Default>0x00</Default>

+                <Desc>0 - Mandatory Page Scan Mode, 1 - Optional Page Scan Mode I</Desc>

+            </Param>

+            <Param type="u" size="3">

+                <Name>Class of Device</Name>

+                <Default>"000000"</Default>

+                <Desc>Class of Device for the device</Desc>

+            </Param>

+            <Param type="u" size="2">

+                <Name>Clock Offset</Name>

+                <Default>any</Default>

+                <Desc>Bit 16-2 of CLKslave-CLKmaster</Desc>

+            </Param>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Connection_Complete_Event" type="se" opcode="0x0003">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Connection successfully completed, otherwise Connection failed to Complete</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Get_Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="LinkType">

+            <Name>Link Type</Name>

+            <Default>0x01</Default>

+            <Desc>0 - SCO connection, 1 - ACL connection</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Encryption_Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Link level encryption disabled, 1 - Link level encryption enabled</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Connection_Request_Event" type="se" opcode="0x0004">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>Get_Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="x" size="3">

+            <Name>Class of Device</Name>

+            <Default>"001F00"</Default>

+            <Desc>Class of Device for the device, which request the connection</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="LinkType">

+            <Name>Link Type</Name>

+            <Default>0x01</Default>

+            <Desc>0 - SCO connection requested, 1 - ACL connection requested</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Disconnection_Complete_Event" type="se" opcode="0x0005">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Disconnection has occurred, otherwise Disconnection failed to Complete</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Reason</Name>

+            <Default>0x08</Default>

+            <Desc>Other End Terminated Connection (0x13-0x15), Terminated by Local Host (0x16), Timeout (0x08)</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Authentication_Complete_Event" type="se" opcode="0x0006">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Authentication Request successfully completed, otherwise Request failed</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Remote_Name_Request_Complete_Event" type="se" opcode="0x0007">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Remote Name Request command succeeded</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="s" size="248">

+            <Name>Remote Name</Name>

+            <Default>Any</Default>

+            <Desc>User Friendly Descriptive Name for the remote device</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Encryption_Change_Event" type="se" opcode="0x0008">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Encryption Change has occurred, otherwise Encryption Change failed</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="OffOn">

+            <Name>Encryption Enable</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Turn Link Level Encryption OFF, 1 - Turn Link Level Encryption ON</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Change_Connection_Link_Key_Complete_Event" type="se" opcode="0x0009">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Change_Connection_Link_Key command succeeded, otherwise Request failed</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Master_Link_Key_Complete_Event" type="se" opcode="0x000a">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Master Link Key Link Key command succeeded, otherwise request failed</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="LinkKeyFlag">

+            <Name>Key Flag</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Using Semi-permanent Link Keys, 1 - Using Temporary Link Key</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Remote_Supported_Features_Complete_Event" type="se" opcode="0x000b">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Read Remote Supported Features command succeeded</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="x" size="8">

+            <Name>LMP Features</Name>

+            <Default>"0000000000000000"</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Remote_Version_Information_Complete_Event" type="se" opcode="0x000c">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Read Remote Version Information command succeeded</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="LMPVersion">

+            <Name>LMP Version</Name>

+            <Default>0x00</Default>

+            <Desc>Version of the Current LMP in the remote Bluetooth Hardware</Desc>

+        </Param>

+        <Param type="u" size="2" valtype="CompID">

+            <Name>Manufacturer Name</Name>

+            <Default>13</Default>

+            <Desc>Manufacturer Name of the Remote Bluetooth Hardware</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>LMP Subversion</Name>

+            <Default>0x0000</Default>

+            <Desc>Subversion of the Current LMP in the remote Bluetooth Hardware</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_QoS_Setup_Complete_Event" type="se" opcode="0x000d">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - QoS Setup command succeeded, otherwise Request failed</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Flags</Name>

+            <Default>0x00</Default>

+            <Desc>Reserved for Future Use</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="ServiceType">

+            <Name>Service Type</Name>

+            <Default>0x01</Default>

+            <Desc>0 - No Traffic Available; 1 - Best Effort Available; 2 - Guaranteed Available</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Token Rate</Name>

+            <Default>0x00000000</Default>

+            <Desc>Available Token Rate in bytes per second</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Peak Bandwidth</Name>

+            <Default>0x00000000</Default>

+            <Desc>Available Peak Bandwidth in bytes per second</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Latency</Name>

+            <Default>0x00000000</Default>

+            <Desc>Available Latency in microseconds</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Delay Variation</Name>

+            <Default>0x00000000</Default>

+            <Desc>Available Delay Variation in microseconds</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Command_Complete_Event" type="se" opcode="0x000e">

+        <Cat>Spec 1.1</Cat>

+        <Param type="CommandComplete">

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Success</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Command_Status_Event" type="se" opcode="0x000f">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>2000</Default>

+            <Desc>Time in msec</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Number HCI commands</Name>

+            <Default>Any</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Command Opcode</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Hardware_Error_Event" type="se" opcode="0x0010">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="HardwareErrorCodes">

+            <Name>Hardware Code</Name>

+            <Default>0x00</Default>

+            <Desc>Error code to indicate various Hardware problems</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Flush_Occurred_Event" type="se" opcode="0x0011">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Role_Change_Event" type="se" opcode="0x0012">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Role change has occurred, 1 - Role change failed</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Role">

+            <Name>New Role</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Currently the Master for specified Connection Handle, 1 - Currently the Slave</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Number_Of_Completed_Packets_Event" type="se" opcode="0x0013">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" label="count">

+            <Name>Number of Handles</Name>

+            <Default>0x01</Default>

+            <Desc>The number of Handles and Data_Packets parameters pairs contained in this event</Desc>

+        </Param>

+        <Param array="count">

+            <Param type="h" size="2">

+                <Name>Connection Handle</Name>

+                <Default>Handle</Default>

+                <Desc />

+            </Param>

+            <Param type="u" size="2">

+                <Name>Num Completed Packets</Name>

+                <Default>0x0000</Default>

+                <Desc>number of packets that have been completed (transmitted or flushed) since the previous time the event was returned</Desc>

+            </Param>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Mode_Change_Event" type="se" opcode="0x0014">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - A Mode change has occurred, otherwise request failed</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Mode">

+            <Name>Current Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Active Mode, 1 - Hold Mode, 2 - Sniff Mode, 3 - Park Mode</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Interval</Name>

+            <Default>0x0000</Default>

+            <Desc>Hold interval, or Sniff interval, or Beacon interval</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Return_Link_Keys_Event" type="se" opcode="0x0015">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" label="count">

+            <Name>Num Keys</Name>

+            <Default>0x00</Default>

+            <Desc>Number of Link Keys contained in this event</Desc>

+        </Param>

+        <Param array="count">

+            <Param type="b" size="6">

+                <Name>BD Address of the Remote</Name>

+                <Default>BD_ADDR</Default>

+                <Desc />

+            </Param>

+            <Param type="x" size="16" prop="r">

+                <Name>Link Key</Name>

+                <Default>"00000000000000000000000000000000"</Default>

+                <Desc>Link Key for the associated BD_ADDR</Desc>

+            </Param>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_PIN_Code_Request_Event" type="se" opcode="0x0016">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Link_Key_Request_Event" type="se" opcode="0x0017">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Link_Key_Notification_Event" type="se" opcode="0x0018">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+        <Param type="x" size="16">

+            <Name>Link Key</Name>

+            <Default>"00000000000000000000000000000000"</Default>

+            <Desc>Link Key for the associated BD_ADDR</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="KeyType">

+            <Name>Key Type</Name>

+            <Default>any</Default>

+            <Desc>0 - Combination, 1 - Local Unit, 2 - Remote Unit Key</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Loopback_Command_Event" type="se" opcode="0x0019">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Default>any</Default>

+            <Desc>Opcode of the HCI Command Packet</Desc>

+        </Param>

+        <Param type="u" size="1" label="payload">

+            <Name>Length</Name>

+            <Default>any</Default>

+            <Desc>Length of the HCI Command Packet</Desc>

+        </Param>

+        <Param type="x" size="payload">

+            <Name>HCI Command Packet Data</Name>

+            <Default>Any</Default>

+            <Desc>HCI command packet data segment</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Data_Buffer_Overflow_Event" type="se" opcode="0x001a">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="LinkType">

+            <Name>Link Type</Name>

+            <Default>0x01</Default>

+            <Desc>0 - SCO Buffer Overflow, 1 - ACL Buffer Overflow</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Max_Slots_Change_Event" type="se" opcode="0x001b">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="MaxSlots">

+            <Name>LMP Max Slots</Name>

+            <Default>0x01</Default>

+            <Desc>Maximum number of slots allowed to use for baseband packets</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Link_Supervision_timeout_Change_Event" type="se" opcode="0x0038">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>LMP Link Supervision Timeout</Name>

+            <Default>any</Default>

+            <Desc>Measured in number of baseband slots. For actual timeout multiply this parm by 0.625msec. Range is 0x001-0xFFFF (0.625ms-40.9s).</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Refresh_Encryption_Key_Event" type="se" opcode="0x0030">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Fm_Event" type="se" opcode="0x00F0">

+        <Cat>Spec 1.2</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Clock_Offset_Complete_Event" type="se" opcode="0x001c">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Read Clock Offset command succeeded, otherwise request failed</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Clock Offset</Name>

+            <Default>any</Default>

+            <Desc>Bit 16.2 of CLKslave-CLKmaster</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Connection_Packet_Type_Changed_Event" type="se" opcode="0x001d">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Success</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2"  valtype="AclScoTypes">

+            <Name>Packet Type</Name>

+            <Default>0x0018</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_QoS_Violation_Event" type="se" opcode="0x001e">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Page_Scan_Repetition_Mode_Change_Event" type="se" opcode="0x0020">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="PageScanRepetitionMode">

+            <Name>Page Scan Repetition Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0 - R0,1 - R1, 2 - R2</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Flow_Specification_Complete_Event" type="se" opcode="0x0021">

+        <Cat>Spec 1.2</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - QoS Flow Specification succeeded; 0x2c - QoS Unacceptable Parameters; 0x2d - QoS Rejected</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Flags</Name>

+            <Default>0x00</Default>

+            <Desc>Reserved for Future Use</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="FlowDirection">

+            <Name>Flow Direction</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Outgoing; 1 - Incoming</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="ServiceType">

+            <Name>Service Type</Name>

+            <Default>0x01</Default>

+            <Desc>0 - No Traffic Available; 1 - Best Effort Available; 2 - Guaranteed Available</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Token Rate</Name>

+            <Default>0x00000000</Default>

+            <Desc>Token Rate in bytes per seconds, 0x00000000 - not specified; 0xFFFFFFFF - maximum available</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Token Bucket Size</Name>

+            <Default>0x00000000</Default>

+            <Desc>Token Bucket Size in bytes, 0x00000000 - not needed; 0xFFFFFFFF - maximum available</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Peak Bandwidth</Name>

+            <Default>0x00000000</Default>

+            <Desc>Peak Bandwidth in bytes per second, 0x00000000 - do not care</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Access Latency</Name>

+            <Default>0xFFFFFFFF</Default>

+            <Desc>Latency in microseconds, 0xFFFFFFFF - do not care</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Inquiry_Result_with_RSSI_Event" type="se" opcode="0x0022">

+        <Cat>Spec 1.2</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" label="count">

+            <Name>Number of Responses</Name>

+            <Default>0x01</Default>

+            <Desc>Number of responses from the Inquiry</Desc>

+        </Param>

+        <Param array="count">

+            <Param type="b" size="6">

+                <Name>BD_ADDR for each device which responded</Name>

+                <Default>Get_Bd_Addr</Default>

+                <Desc />

+            </Param>

+            <Param type="u" size="1" valtype="PageScanRepetitionMode">

+                <Name>Page Scan Repetition Mode</Name>

+                <Default>0x00</Default>

+                <Desc>0 - R0, 1 - R1, 2 - R2</Desc>

+            </Param>

+            <Param type="u" size="1" valtype="PeriodMode">

+                <Name>Page Scan Period Mode</Name>

+                <Default>0x00</Default>

+                <Desc>0 - P0, 1 - P1, 2 - P2</Desc>

+            </Param>

+            <Param type="u" size="3">

+                <Name>Class of Device</Name>

+                <Default>"000000"</Default>

+                <Desc>Class of Device for the device</Desc>

+            </Param>

+            <Param type="u" size="2">

+                <Name>Clock Offset</Name>

+                <Default>any</Default>

+                <Desc>Bit 16.2 of CLKslave-CLKmaster</Desc>

+            </Param>

+            <Param type="d" size="1">

+                <Name>RSSI</Name>

+                <Default>0x00</Default>

+                <Desc>Range: -127 to +20 Units: dBm</Desc>

+            </Param>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Extended_Inquiry_Result_Event" type="se" opcode="0x002F">

+        <Cat>Spec Lisbon</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" label="count">

+            <Name>Number of Responses</Name>

+            <Default>0x01</Default>

+            <Desc>Number of responses from the Inquiry</Desc>

+        </Param>

+        <Param array="count">

+            <Param type="b" size="6">

+                <Name>BD_ADDR for each device which responded</Name>

+                <Default>Get_Bd_Addr</Default>

+                <Desc />

+            </Param>

+            <Param type="u" size="1" valtype="PageScanRepetitionMode">

+                <Name>Page Scan Repetition Mode</Name>

+                <Default>0x00</Default>

+                <Desc>0 - R0, 1 - R1, 2 - R2</Desc>

+            </Param>

+            <Param type="u" size="1" valtype="PeriodMode">

+                <Name>Page Scan Period Mode</Name>

+                <Default>0x00</Default>

+                <Desc>0 - P0, 1 - P1, 2 - P2</Desc>

+            </Param>

+            <Param type="u" size="3">

+                <Name>Class of Device</Name>

+                <Default>"000000"</Default>

+                <Desc>Class of Device for the device</Desc>

+            </Param>

+            <Param type="u" size="2">

+                <Name>Clock Offset</Name>

+                <Default>any</Default>

+                <Desc>Bit 16.2 of CLKslave-CLKmaster</Desc>

+            </Param>

+            <Param type="d" size="1">

+                <Name>RSSI</Name>

+                <Default>0x00</Default>

+                <Desc>Range: -127 to +20 Units: dBm</Desc>

+            </Param>

+        </Param>

+        <Param type="x" size="240">

+            <Name>Inquiry Response Data</Name>

+            <Default></Default>

+            <Desc>Will be paddad with zero to 240 bytes</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Read_Remote_Extended_Features_Complete_Event" type="se" opcode="0x0023">

+        <Cat>Spec 1.2</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Read Remote Supported Features command succeeded</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Page Number</Name>

+            <Default>0x00</Default>

+            <Desc>0 - the only available page</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Maximum Page Number</Name>

+            <Default>0x00</Default>

+            <Desc>0 - the only available maximum page</Desc>

+        </Param>

+        <Param type="x" size="8">

+            <Name>LMP_Features</Name>

+            <Default>"0000000000000000"</Default>

+            <Desc>Expecting parameter value</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Synchronous_Connection_Complete_Event" type="se" opcode="0x002C">

+        <Cat>Spec 1.2</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Connection successfully completed, otherwise Connection failed to Complete</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD Address of the Remote</Name>

+            <Default>Bd_Addr</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="LinkType">

+            <Name>Link Type</Name>

+            <Default>0x02</Default>

+            <Desc>0x00 - SCO, 0x02 - eSCO</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Transmission Interval</Name>

+            <Default>0x06</Default>

+            <Desc>Time (in slots) between two consecutive eSCO instants. Must be 0 for SCO</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Retransmission Window</Name>

+            <Default>0x00</Default>

+            <Desc>The size (in slots) of the retransmission window. Must be 0 for SCO</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Rx Packet Length</Name>

+            <Default>30</Default>

+            <Desc>Length in bytes of the eSCO payload in the receive direction. Must be 0 for SCO</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Tx Packet Length</Name>

+            <Default>30</Default>

+            <Desc>Length in bytes of the eSCO payload in the transmit direction. Must be 0 for SCO</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="AirMode">

+            <Name>Air Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0x00: µ-law; 0x01: A-law; 0x02: CVSD; 0x03: Transparent Data</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Synchronous_Connection_Changed_Event" type="se" opcode="0x002D">

+        <Cat>Spec 1.2</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Connection successfully completed, otherwise Connection failed to Complete</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Transmission Interval</Name>

+            <Default>0x06</Default>

+            <Desc>Time (in slots) between two consecutive SCO/eSCO instants</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Retransmission Window</Name>

+            <Default>0x00</Default>

+            <Desc>The size (in slots) of the retransmission window. Must be 0 for SCO</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Rx Packet Length</Name>

+            <Default>30</Default>

+            <Desc>Length in bytes of the SCO/eSCO payload in the receive direction</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Tx Packet Length</Name>

+            <Default>30</Default>

+            <Desc>Length in bytes of the SCO/eSCO payload in the transmit direction</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Sniff_Subrate_Changed_Event" type="se" opcode="0x002E">

+        <Cat>Spec 1.2</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Connection successfully completed, otherwise Connection failed to Complete</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Max Transmit Latency</Name>

+            <Default>0x00000</Default>

+            <Desc>Maximum latency for data being transmitted from the local device to the remote device in ms[0x0000 - 0x9FFF]</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Max Received Latency</Name>

+            <Default>0x00000</Default>

+            <Desc>Maximum latency for data being received by the local device from the remote device in ms[0x0000 - 0x9FFF]</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Min Remote Timeout</Name>

+            <Default>0x00000</Default>

+            <Desc>The sub-rate zero timeout in baseband slots that the remote device can use in slots[0x0000 - 0x8000]</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Min Local Timeout</Name>

+            <Default>0x00000</Default>

+            <Desc>The sub-rate zero timeout in baseband slots that the local device will use in slots[0x0000 - 0x8000]</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_IO_Capability_Request_event" type="se" opcode="0x0031">

+        <Cat>Lisbon</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD_ADDR</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Addr of remote device involved in simple pairing process</Desc>

+        </Param>

+        

+    </Command>

+    

+    <Command name="HCI_IO_Capability_Response_event" type="se" opcode="0x0032">

+        <Cat>Lisbon</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD_ADDR</Name>

+            <Desc>BD Addr of remote device involved in simple pairing process</Desc>

+        </Param>

+        

+        <Param type="u" size="1" valtype="Io Capability">

+            <Name>IO capability</Name>

+            <Default>0x00</Default>

+            <Desc>IO capability of peer</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="OOB Data Present">

+            <Name>OOB data present</Name>

+            <Default>0x00</Default>

+            <Desc>OOB capability with remote</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Authentication Required">

+            <Name>Authentication Required</Name>

+            <Default>0x00</Default>

+            <Desc>0 - MITM Protection Not Required – Single Profile. Numeric comparison with automatic accept allowed. 1 - MITM Protection Required – Single Profile.  Use IO Capabilities to determine authentication procedure. 2 - MITM Protection Not Required – All Profiles.  Numeric comparison with automatic accept allowed. 3 - MITM Protection Required – All Profiles.  Use IO Capabilities to determine authentication procedure</Desc>

+        </Param>

+        

+    </Command>

+    

+    <Command name="HCI_User_Confirmation_Request_event" type="se" opcode="0x0033">

+        <Cat>Lisbon</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD_ADDR</Name>

+            <Default>BD_ADDR</Default>

+            <Desc>BD Addr of remote device involved in simple pairing process</Desc>

+        </Param>

+        

+        <Param type="u" size="4">

+            <Name>Numeric Value</Name>

+            <Default>0000</Default>

+            <Desc>Numeric value to be displayed. Valid values are decimal 0000 - 9999.</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_User_Passkey_Request_event" type="se" opcode="0x0034">

+        <Cat>Lisbon</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD_ADDR</Name>

+            <Desc>BD Addr of remote device involved in simple pairing process</Desc>

+        </Param>

+        

+    </Command>

+    

+    <Command name="HCI_Remote_Oob_data_request_event" type="se" opcode="0x0035">

+        <Cat>Lisbon</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD_ADDR</Name>

+            <default>BD_ADDR</default>

+            <Desc>BD Addr of remote device involved in simple pairing process</Desc>

+        </Param>

+        

+    </Command>

+    

+    <Command name="HCI_Simple_Pairing_complete_event" type="se" opcode="0x0036">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc> </Desc>

+        </Param>

+        <Param type="b" size="6">

+            <Name>BD_ADDR</Name>

+            <default>BD_ADDR</default>

+            <Desc>BD Addr of remote device involved in simple pairing process</Desc>

+        </Param>

+        <Cat>Lisbon</Cat>

+    </Command>

+    

+    <Command name="HCI_Remote_Oob_Response_event" type="se" opcode="0x0037">

+        <Param type="b" size="6">

+            <Name>BD_ADDR</Name>

+            <Desc>BD Addr of remote device involved in simple pairing process</Desc>

+        </Param>

+        

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc> </Desc>

+        </Param>

+        <Cat>Lisbon</Cat>

+    </Command>

+    

+    <Command name="HCI_Enhanced_Flush_Occured_Event" type="se" opcode="0x0039">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Cat>Lisbon</Cat>

+    </Command>

+    

+    <Command name="HCI_Sniff_Request_Event" type="se" opcode="0x003A">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="h" size="2">

+            <Name>Sniff Interval</Name>

+            <Default>0</Default>

+            <Desc />

+        </Param>

+        <Param type="h" size="2">

+            <Name>Sniff Attempt</Name>

+            <Default>0</Default>

+            <Desc />

+        </Param>

+        <Param type="h" size="2">

+            <Name>Sniff timeout</Name>

+            <Default>0</Default>

+            <Desc />

+        </Param>

+        <Cat>Lisbon</Cat>

+    </Command>

+    

+    <Command name="HCI_Protocol_Viewer_Message_Was_Dropped_Event" type="se" opcode="0x00EE">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        

+        <Param type="u" size="1">

+            <Name>Number of Dropped Messages</Name>

+            <Default>any</Default>

+            <Desc>number of dropped messages</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_Command_Complete_Param1_Event" type="se" opcode="0x000e">

+        <Cat>Spec 1.1</Cat>

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Number HCI commands</Name>

+            <Default>any</Default>

+            <Desc>Number of additional HCI Command Packets to be sent to the Host Controller from the Host</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Command Opcode</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Success</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Parameter(1 Byte)</Name>

+            <Default>0x00</Default>

+            <Desc>Expecting parameter value</Desc>

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="HCI VS Legacy Commands (Not released to customers)" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="HCI_VS_Set_Fixed_PIN_Code" type="sc" opcode="0xFF2B">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF2B</Default>

+            <Desc>set encryption key parameters.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>PIN Length</Name>

+            <Default>16</Default>

+            <Desc>Pin Code Length.</Desc>

+        </Param>

+        <Param type="x" size="16">

+            <Name>Pin Code Bytes</Name>

+            <Default>00000000000000000000000000000000</Default>

+            <Desc>LSB to MSB in HEX</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_L2cap_Flow_and_Length" type="sc" opcode="0xFE46">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE46</Default>

+            <Desc>control l2cap payload header and length for testing l2cap flow using zero l2cap payload length in the payload header.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="OnOff">

+            <Name>L2cap flow</Name>

+            <Default>0</Default>

+            <Desc>Sets the l2cap flow.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="L2cap_len_flags">

+            <Name>L2cap length flag</Name>

+            <Default>0</Default>

+            <Desc>Sets the l2cap length in the header (Zero or positive).</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Select_Change_Pkt_Type_Event_EDR_Mode" type="sc" opcode="0xFD0D">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD0D</Default>

+            <Desc>Select the mode which defines how the packet type field of the Change Packet Type Event is set in regard to the EDR bits</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="EDR_Mode">

+            <Name>EDR Mode</Name>

+            <Default>0</Default>

+            <Desc>Show or diregard the real value of the EDR packet bit.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_UDI_Connection" type="sc" opcode="0xFD2F">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD2F</Default>

+            <Desc>HCIPP Set Udi connection</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>udi_enable</Name>

+            <Default>0</Default>

+            <Desc>0=Disabled 1=Enabled. When set to 1, indicates enabling pcm synchronization for udi.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>synch channel</Name>

+            <Default>0</Default>

+            <Desc>voice channel that the pcm should synchronize to.0 - channel one, 1- channel two</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_EPLC" type="sc" opcode="0xfd08">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD08</Default>

+            <Desc>HCIPP Write EPLC (Enhanced packet loss concealment)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>EPLC enable</Name>

+            <Default>0x00</Default>

+            <Desc>Enhanced packet loss control feature: 0 - diabled, 1 - enabled. Enable only when there is no active voice connection.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>EPLC R value</Name>

+            <Default>0x00</Default>

+            <Desc>[0-15] R parameter used in EPLC (previous packet transmissions count), recommended max of 3. Updated only when enabling.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>EPLC N value</Name>

+            <Default>0x00</Default>

+            <Desc>[0-15] N parameter used in EPLC (noise packet transmissions count). Updated only when enabling.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0x00</Default>

+            <Desc>This field is reserved for future use</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Config_Pcm_Synch_For_UDI" type="sc" opcode="0xFD1F">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD1F</Default>

+            <Desc>Config pcm synch params</Desc>

+        </Param>

+        <Param type="2" size="2">

+            <Name>T_Check</Name>

+            <Default>2400</Default>

+            <Desc>Monitoring time of pcm buffer [frames]</Desc>

+        </Param>

+        <Param type="2" size="2">

+            <Name>T_Hold</Name>

+            <Default>4000</Default>

+            <Desc>Stabilizing time of pcm clock [frames]</Desc>

+        </Param>

+        <Param type="1" size="1">

+            <Name>Interrupt Threshold</Name>

+            <Default>12</Default>

+            <Desc>Min Threshold in percentage of the sco buffer size</Desc>

+        </Param>

+        <Param type="1" size="1">

+            <Name>Complement interrupt Threshold</Name>

+            <Default>37</Default>

+            <Desc>Max Threshold in percentage of the sco buffer size</Desc>

+        </Param>

+        <Param type="1" size="1">

+            <Name>PPM fix</Name>

+            <Default>2</Default>

+            <Desc>delta of ppm fix in pcm synchronization</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_Pwr_Consumption_Configuration" type="sc" opcode="0xfd05">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD05</Default>

+            <Desc>Set Power Consumption Configuration part 1</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>ACTIVE current (multiplied by 8)</Name>

+            <Default>45</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>RF Standby current (multiplied by 8)</Name>

+            <Default>10</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>RX current (multiplied by 8)</Name>

+            <Default>295</Default>

+            <Desc>Current consumed in rx activity (i.e. scan) per frame</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Low Power Scan current (multiplied by 8)</Name>

+            <Default>334</Default>

+            <Desc>Current consumed in one LPS</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Page/Inquiry current (multiplied by 8)</Name>

+            <Default>222</Default>

+            <Desc>Current consumed in page/inquiry activity per frame (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Big Sleep current</Name>

+            <Default>25</Default>

+            <Desc>Current consumed in big sleep per frame (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Deep Sleep current</Name>

+            <Default>1</Default>

+            <Desc>Current consumed in deep sleep per frame (multiplied by 32)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>HV1 current</Name>

+            <Default>230</Default>

+            <Desc>Current consumed in HV1 connection per frame (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>HV2 current</Name>

+            <Default>115</Default>

+            <Desc>Current consumed in HV1 connection per frame (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>HV3 current</Name>

+            <Default>77</Default>

+            <Desc>Current consumed in HV1 connection per frame (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>EV3 rx current</Name>

+            <Default>108</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>EV3 tx current</Name>

+            <Default>129</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>2EV3 rx current</Name>

+            <Default>217</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>2EV3 tx current</Name>

+            <Default>186</Default>

+            <Desc>Current consumed for one packe (multiplied by 8)t</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>3EV3 rx current</Name>

+            <Default>293</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>3EV3 tx current</Name>

+            <Default>243</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>EV4 rx current</Name>

+            <Default>383</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>EV4 tx current</Name>

+            <Default>415</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>EV5 rx current</Name>

+            <Default>381</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>EV5 tx current</Name>

+            <Default>413</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>2EV5 rx current</Name>

+            <Default>976</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>2EV5 tx current</Name>

+            <Default>753</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>3EV5 rx current</Name>

+            <Default>1431</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>3EV5 tx current</Name>

+            <Default>1092</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DM1 rx current</Name>

+            <Default>104</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DM1 tx current</Name>

+            <Default>126</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DH1 rx current</Name>

+            <Default>104</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DH1 tx current</Name>

+            <Default>126</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>2DH1 rx current</Name>

+            <Default>207</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>2DH1 tx current</Name>

+            <Default>179</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>3DH1 rx current</Name>

+            <Default>280</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>3DH1 tx current</Name>

+            <Default>233</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DM3 rx current</Name>

+            <Default>391</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DM3 tx current</Name>

+            <Default>423</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DH3 rx current</Name>

+            <Default>390</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DH3 tx current</Name>

+            <Default>422</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DM5 rx current</Name>

+            <Default>675</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DM5 tx current</Name>

+            <Default>717</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DH5 rx current</Name>

+            <Default>675</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>DH5 tx current</Name>

+            <Default>717</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>2DH3 rx current</Name>

+            <Default>998</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>2DH3 tx current</Name>

+            <Default>770</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>3DH3 rx current</Name>

+            <Default>1466</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>3DH3 tx current</Name>

+            <Default>1119</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>2DH5 rx current</Name>

+            <Default>1787</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>2DH5 tx current</Name>

+            <Default>1359</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>3DH5 rx current</Name>

+            <Default>2652</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>3DH5 tx current</Name>

+            <Default>2004</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>POLL rx current</Name>

+            <Default>49</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>POLL tx current</Name>

+            <Default>69</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>NULL rx current</Name>

+            <Default>49</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>NULL tx current</Name>

+            <Default>69</Default>

+            <Desc>Current consumed for one packet (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Slave RX Window current</Name>

+            <Default>62</Default>

+            <Desc>Current consumed for slave window opened every frame (assuming no RX) (multiplied by 8)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 0 Factor Per Packet</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling TX packets acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 0 Factor for SCO</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling SCO current acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 1 Factor Per Packet</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling TX packets acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 1 Factor for SCO</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling SCO current acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 2 Factor Per Packet</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling TX packets acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 2 Factor for SCO</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling SCO current acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 3 Factor Per Packet</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling TX packets acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 3 Factor for SCO</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling SCO current acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 4 Factor Per Packet</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling TX packets acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 4 Factor for SCO</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling SCO current acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 5 Factor Per Packet</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling TX packets acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 5 Factor for SCO</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling SCO current acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 6 Factor Per Packet</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling TX packets acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 6 Factor for SCO</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling SCO current acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 7 Factor Per Packet</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling TX packets acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX Power Level 7 Factor for SCO</Name>

+            <Default>1</Default>

+            <Desc>factor for multipling SCO current acording to power level</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>FM current</Name>

+            <Default>180</Default>

+            <Desc>currrent consumed by FM radio per frame (multiplied by 8)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Change_UART_Debug_Buffer_Params" type="sc" opcode="0xFD01">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD01</Default>

+            <Desc>Change UART Debug Buffer Params. This command actually MOVES &amp; RESIZES the buffer. Be carefull when using it!</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Buffer Start Address</Name>

+            <Default>0x85400</Default>

+            <Desc>The base address in RAM of the new UART Debug Buffer (Nominal values: 0x80000-0x853FF).</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Buffer Size</Name>

+            <Default>512</Default>

+            <Desc>The size (in bytes) of the new UART Debug Buffer (Nominal values: 128-3000).</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+     <Command name="HCI_VS_Enable_Disable_UART_Debug" type="sc" opcode="0xFDC5">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDC5</Default>

+            <Desc>Enable or Disable the UART Debug HW output (does not affect debug-over-HCI) </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>action</Name>

+            <Default>1</Default>

+            <Desc>0 - Enable, 1 - Disable (as soon as the SW FIFO gets empty), 2 - Disable immediately (may casue logger corruption) </Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+   <Command name="HCI_VS_Set_RF_Link_Timer" type="sc" opcode="0xff76">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF76</Default>

+            <Desc>HCIPP Set RF Link Timer</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Interval</Name>

+            <Default>0x14</Default>

+            <Desc>20 frames - 25 mili</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Host_Report_Fref_Drift_Over_Temperature" type="sc" opcode="0xFD11">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD11</Default>

+            <Desc>HCIPP Host Report Fref Drift Over Temperature</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>1st Range drift in ppm</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0xFFFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>1st Range High Limit</Name>

+            <Default>0xFF</Default>

+            <Desc>0xFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>2nd Range drift in ppm</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0xFFFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>2nd Range High Limit</Name>

+            <Default>0xFF</Default>

+            <Desc>(do not fill this field for highest range) 0xFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>3rd Range drift in ppm</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0xFFFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>3rd Range High Limit</Name>

+            <Default>0xFF</Default>

+            <Desc>(do not fill this field for highest range) 0xFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>4th Range drift in ppm</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0xFFFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>4th Range High Limit</Name>

+            <Default>0xFF</Default>

+            <Desc>(do not fill this field for highest range) 0xFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>5th Range drift in ppm</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0xFFFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>5th Range High Limit</Name>

+            <Default>0xFF</Default>

+            <Desc>(do not fill this field for highest range) 0xFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>6th Range drift in ppm</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0xFFFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>6th Range High Limit</Name>

+            <Default>0xFF</Default>

+            <Desc>(do not fill this field for highest range) 0xFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>7th Range drift in ppm</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0xFFFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>7th Range High Limit</Name>

+            <Default>0xFF</Default>

+            <Desc>(do not fill this field for highest range) 0xFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>8th Range drift in ppm</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0xFFFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>8th Range High Limit</Name>

+            <Default>0xFF</Default>

+            <Desc>(do not fill this field for highest range) 0xFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>9th Range drift in ppm</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0xFFFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>9th Range High Limit</Name>

+            <Default>0xFF</Default>

+            <Desc>(do not fill this field for highest range) 0xFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>10th Range drift in ppm</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0xFFFF - don't change</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_Test_Mux_Pin" type="sc" opcode="0xfd14">

+        

+        <Param type="u" size="1" label="Module_Name" valtype="SetTestMuxModuleName">

+            <Name>Module Name</Name>

+            <Default>0xFF</Default>

+            <Desc></Desc>

+        </Param>

+        

+        <Param type="u" size="1" label="pin_id" valtype="SetTestMuxPinNumber">

+            <Name>PIN ID</Name>

+            <Default>1</Default>

+            <Desc>Pin nuber (from table)</Desc>

+        </Param>

+        

+        <Param cond="Module_Name==7">

+            <Param type="u" size="1" valtype="BT_Debug_pins">

+                <Name>Test Mux value - Enter Value</Name>

+                <Default>0x00</Default>

+                <Desc>Register Value </Desc>

+            </Param>

+            

+            <Param type="u" size="1" prop="h">

+                <Name>Test Mux number of bits - Don't Touch </Name>

+                <Default>0x7</Default>

+                <Desc>number of bits each pin requires</Desc>

+            </Param>

+            <Param cond="pin_id==1">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A0F00</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==2">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A0F00</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==3">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A0F02</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==4">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A0F02</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==5">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001A0F04</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==6">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001A0F04</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==7">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001A0F06</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==8">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001A0F06</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>7</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+        </Param>

+        

+        <Param cond="Module_Name==2" >

+            <Param type="u" size="1" valtype="SDIO_Debug_pins">

+                <Name>Test Mux value - Enter Value</Name>

+                <Default>0x00</Default>

+                <Desc>Register Value </Desc>

+            </Param>

+            <Param type="u" size="1" prop="h">

+                <Name>Test Mux number of bits - Don't Touch </Name>

+                <Default>0x3</Default>

+                <Desc>number of bits each pin requires</Desc>

+            </Param>

+            <Param cond="pin_id==1">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 0 Address</Name>

+                    <Default>0x001A2018</Default>

+                    <Desc>Test Mux 0 Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>2</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==2">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 0 Address</Name>

+                    <Default>0x001A2018</Default>

+                    <Desc>Test Mux 0 Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>2</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==3">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A2018</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>8</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>2</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==4">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A2018</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>2</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==5">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A201A</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>2</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==6">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A201A</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>2</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==7">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001A201A</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>8</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>2</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==8">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001A201A</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>2</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==9">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001A201C</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>2</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==10">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001A201C</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>2</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+        </Param>

+        

+        <Param cond="Module_Name==3">

+            <Param type="u" size="1" valtype="DMA_Debug_pins">

+                <Name>Test Mux value - Enter Value</Name>

+                <Default>0x00</Default>

+                <Desc>Register Value 

+                    (*) - 	bit 0 of this signal will appear on test_bus bits: 0,2,4,6,8 

+                    bit 1 of this signal will appear on test_bus bits: 1,3,5,7,9 

+                </Desc>

+            </Param>

+            <Param cond="pin_id==1">

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux number of bits - Don't Touch </Name>

+                    <Default>0x4</Default>

+                    <Desc>number of bits each pin requires</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001AF12A</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==2">

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux number of bits - Don't Touch </Name>

+                    <Default>0x4</Default>

+                    <Desc>number of bits each pin requires</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001AF12A</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==3">

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux number of bits - Don't Touch </Name>

+                    <Default>0x4</Default>

+                    <Desc>number of bits each pin requires</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001AF12A</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>8</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==4">

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux number of bits - Don't Touch </Name>

+                    <Default>0x4</Default>

+                    <Desc>number of bits each pin requires</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001AF12A</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==5">

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux number of bits - Don't Touch </Name>

+                    <Default>0x4</Default>

+                    <Desc>number of bits each pin requires</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001AF12C</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==6">

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux number of bits - Don't Touch </Name>

+                    <Default>0x4</Default>

+                    <Desc>number of bits each pin requires</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001AF12C</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==7">

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux number of bits - Don't Touch </Name>

+                    <Default>0x4</Default>

+                    <Desc>number of bits each pin requires</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001AF12C</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>8</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==8">

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux number of bits - Don't Touch </Name>

+                    <Default>0x4</Default>

+                    <Desc>number of bits each pin requires</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001AF12C</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==9">

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux number of bits - Don't Touch </Name>

+                    <Default>0x4</Default>

+                    <Desc>number of bits each pin requires</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001AF12E</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==10">

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux number of bits - Don't Touch </Name>

+                    <Default>0x4</Default>

+                    <Desc>number of bits each pin requires</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001AF12E</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+        </Param>

+        

+        

+        <Param cond="Module_Name==4">

+            <Param type="u" size="1" valtype="OCP_IC_Debug_pins">

+                <Name>Test Mux value - Enter Value</Name>

+                <Default>0x00</Default>

+                <Desc>Register Value 

+                    (*) - 	bit 0 of this signal will appear on test_bus bits: 0,2,4,6,8 

+                    bit 1 of this signal will appear on test_bus bits: 1,3,5,7,9 

+                </Desc>

+            </Param>

+            <Param type="u" size="1" prop="h">

+                <Name>Test Mux number of bits - Don't Touch </Name>

+                <Default>6</Default>

+                <Desc>number of bits each pin requires</Desc>

+            </Param>

+            <Param cond="pin_id==1">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001AF416</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==2">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001AF416</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>8</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==3">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001AF418</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==4">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001AF418</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>8</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==5">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001AF41A</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==6">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001AF41A</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>8</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==7">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001AF41C</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==8">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001AF41C</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>8</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==9">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 5 Address - Don't Touch </Name>

+                    <Default>0x001AF41E</Default>

+                    <Desc>Test Mux 5 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==10">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 5 Address - Don't Touch </Name>

+                    <Default>0x001AF41E</Default>

+                    <Desc>Test Mux 5 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>8</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+        </Param>

+        

+        <Param cond="Module_Name==5">

+            <Param type="u" size="1" valtype="UART_Debug_pins">

+                <Name>Test Mux value - Enter Value</Name>

+                <Default>0x00</Default>

+                <Desc>Register Value </Desc>

+            </Param>

+            <Param type="u" size="1" prop="h">

+                <Name>Test Mux number of bits - Don't Touch </Name>

+                <Default>4</Default>

+                <Desc>number of bits each pin requires</Desc>

+            </Param>

+            

+            <Param cond="pin_id==1">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A1020</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>5</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==2">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A1020</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>5</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==3">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A1020</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>8</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>5</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==4">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A1020</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>5</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==5">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A1022</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>5</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==6">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A1022</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>5</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==7">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A1022</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>8</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>5</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==8">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A1022</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>5</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==9">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001A1024</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>5</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==10">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001A1024</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>4</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>5</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+        </Param>

+        

+        <Param cond="Module_Name==0">

+            <Param type="u" size="1" valtype="DRP_Debug_pins_empty_list">

+                <Name>Test Mux value - don't touch</Name>

+                <Default>0x00</Default>

+                <Desc>Register Value </Desc>

+            </Param>

+            <Param type="u" size="1" prop="h">

+                <Name>Test Mux number of bits - Don't Touch </Name>

+                <Default>0x3</Default>

+                <Desc>number of bits each pin requires</Desc>

+            </Param>

+            <Param cond="pin_id==1">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==2">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==3">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==4">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==5">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==6">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==7">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==8">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==9">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==10">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+        </Param>

+        

+        <Param cond="Module_Name==1">

+            <Param type="u" size="1" valtype="WB_Debug_pins">

+                <Name>Test Mux value - Don't touch1</Name>

+                <Default>0x01</Default>

+                <Desc>Register Value </Desc>

+            </Param>

+            <Param type="u" size="1" prop="h">

+                <Name>Test Mux number of bits - Don't Touch </Name>

+                <Default>0x3</Default>

+                <Desc>number of bits each pin requires</Desc>

+            </Param>

+            <Param cond="pin_id==1">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>1</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==2">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>1</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==3">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 1 Address - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Test Mux 1 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>1</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==4">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>1</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==5">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 2 Address - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Test Mux 2 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300A</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>1</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==6">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>0</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>1</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==7">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 3 Address - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Test Mux 3 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>3</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>1</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==8">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>6</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>1</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==9">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>9</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>1</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+            <Param cond="pin_id==10">

+                <Param type="u" size="4" prop="h">

+                    <Name>Test Mux 4 Address - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Test Mux 4 Address - Don't Touch </Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Test Mux Offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>offset inside test_mux register</Desc>

+                </Param>

+                <Param type="u" size="4" prop="h">

+                    <Name>Debug Module register - Don't Touch </Name>

+                    <Default>0x001A300C</Default>

+                    <Desc>Register Address</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module offset - Don't Touch </Name>

+                    <Default>12</Default>

+                    <Desc>Offset within the register</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Debug Module value - Don't Touch </Name>

+                    <Default>1</Default>

+                    <Desc>Register Value (3 bits)</Desc>

+                </Param>

+            </Param>

+        </Param>

+        

+        

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_HW_Reset" type="sc" opcode="0xfe39">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE39</Default>

+            <Desc>HCIPP HW Reset</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Run_Long_Self_Test" type="sc" opcode="0xfe32">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE32</Default>

+            <Desc>HCIPP Run Long Seflf Test</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Get_Rf_Meters" type="sc" opcode="0xfe1e">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE1E</Default>

+            <Desc>HCIPP Get Rf Meters</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Read_Stream_from_EEPROM" type="sc" opcode="0xff84">

+        

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF84</Default>

+            <Desc>HCIPP Read Stream from EEPROM</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x00000000</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Size</Name>

+            <Default>01</Default>

+            <Desc>1-200</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Param1_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_Stream_to_EEPROM" type="sc" opcode="0xff85">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF85</Default>

+            <Desc>HCIPP Write Stream to EEPROM</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x00000000</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Size</Name>

+            <Default>04</Default>

+            <Desc>1-200</Desc>

+        </Param>

+        <Param type="x" size="200">

+            <Name>Values</Name>

+            <Default>"0000"</Default>

+            <Desc>stream in hex, from left to right</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Read_Error_Statistics" type="sc" opcode="0xFF93">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF93</Default>

+            <Desc>HCIPP_READ_ERROR_STATISTICS</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Request </Name>

+            <Default>3</Default>

+            <Desc>1 - BER, 2 - PER, 3 - Both</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Handle  </Name>

+            <Default>0</Default>

+            <Desc> </Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="x" size="10">

+            <Name>Data</Name>

+            <Default>Any</Default>

+        </Param>

+        

+    </Command>

+    

+    <Command name="HCI_VS_TestMode_Override_PowerControl" type="sc" opcode="0xfe05">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE05</Default>

+            <Desc>HCIPP TestMode Override PowerControl</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power_Control_Override</Name>

+            <Default>1</Default>

+            <Desc>If TRUE, power control commands will never be ignored in Test Mode. 1=TRUE, 0=FALSE</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_CDC_Enable" type="sc" opcode="0xff71">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF71</Default>

+            <Desc>HCIPP CDC Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Enable CDC</Name>

+            <Default>0x0</Default>

+            <Desc>1- Enable, 0- Disable</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_Classification_Req_Params" type="sc" opcode="0xff3a">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF3A</Default>

+            <Desc>HCIPP Set AFH Classification Req Parameters</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Classification Req Mode</Name>

+            <Default>1</Default>

+            <Desc>0-Disable, 1-Enable</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Classification Req Min Interval</Name>

+            <Default>0x1F40</Default>

+            <Desc>slots (0-30 sec)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Classification Req Max Interval</Name>

+            <Default>0x3E80</Default>

+            <Desc>slots (0-30 sec)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Scan_All_Stacks" type="sc" opcode="0xff63">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF63</Default>

+            <Desc>HCIPP Scan All Stacks</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Choice</Name>

+            <Default>0x01</Default>

+            <Desc>0-scan all stacks, 1-scan registered stacks, 2- get data, 3-check program memory area</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Scan_All_Buffers" type="sc" opcode="0xff64">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF64</Default>

+            <Desc>HCIPP Scan All Buffers</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_Inquiry_Scan_Mode" type="sc" opcode="0xff65">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF65</Default>

+            <Desc>HCIPP Write Inquiry Scan Mode</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Scanning Mode</Name>

+            <Default>0x10</Default>

+            <Desc>0x00 - Chain Mode, 0x01 - Distributed Mode, 0x10 - Default Mode</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Measure_CPU_Idle_Time" type="sc" opcode="0xff67">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF67</Default>

+            <Desc>HCIPP Measure CPU Idle Time</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Time</Name>

+            <Default>80</Default>

+            <Desc>0-Enter CPU test mode , 1-Exit CPU test mode, other - start and check for "param" BT Frames</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Self_Test_Result" type="sc" opcode="0xff37">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF37</Default>

+            <Desc>HCIPP Self Test Result</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Send_LMP_Frame" type="sc" opcode="0xFF16">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF16</Default>

+            <Desc>HCIPP Send LMP Frame</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>0x0001</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Length</Name>

+            <Default>1</Default>

+            <Desc>Number of bytes for the inserted parameters (excluding the opcode)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>LMP Opcode</Name>

+            <Default>31</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Trans started by slave</Name>

+            <Default>0</Default>

+            <Desc>0- Master initiate, 1- Slave initiate</Desc>

+        </Param>

+        <Param type="x" size="30">

+            <Name>Parameters</Name>

+            <Default>"00"</Default>

+            <Desc>If a parameter is longer than 1 byte, the bytes order should be reverse for that param.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Send_LMP_Frame_Extended" type="sc" opcode="0xfe00">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE00</Default>

+            <Desc>HCIPP Send LMP Frame Extended</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>0x0001</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Length</Name>

+            <Default>0x00</Default>

+            <Desc>number of bytes for the inserted parameters, including lmp ext opcode</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>lmp opcode</Name>

+            <Default>0x7F</Default>

+            <Desc>must enter a value between 124-127</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>lmp ext opcode</Name>

+            <Default>0x00</Default>

+            <Desc>lmp opcode must be between 124-127 for usage of this field</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>trans started by slave</Name>

+            <Default>0x0</Default>

+            <Desc>0- master initiate, 1- slave initiate</Desc>

+        </Param>

+        <Param type="x" size="30">

+            <Name>params</Name>

+            <Default>"0000"</Default>

+            <Desc>if parameter is longer than 1 byte, the bytes order should be revrse for that param.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_LM_Bypass" type="sc" opcode="0xff18">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF18</Default>

+            <Desc>HCIPP Set LM Bypass</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>new value</Name>

+            <Default>01</Default>

+            <Desc>0- normal, 1-bypass LM when receiving LMPs</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_LBT" type="sc" opcode="0xff0f">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF0F</Default>

+            <Desc>HCIPP Set LBT</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Clock Value</Name>

+            <Default>0x3FF447F</Default>

+            <Desc>0-min, 0x3FFFFFF -max</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_Whitening_Mode" type="sc" opcode="0xff0a">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF0A</Default>

+            <Desc>HCIPP Set Whitening Mode</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Whitening Mode</Name>

+            <Default>01</Default>

+            <Desc>0-enable, 1-disable</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== --> 

+    <Command name="HCI VS Legacy Commands (Released to customers)" type="gb" />

+    <!-- ================================================================== -->

+   

+    <Command name="HCI_VS_Configure_Error_Statistics" type="sc" opcode="0xFF92">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF92</Default>

+            <Desc>HCIPP_CONFIGURE_ERROR_STATISTICS</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Error_Statistics_Mode </Name>

+            <Default>0</Default>

+            <Desc>0 - Disable, 1 - Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>BER_Min_Resolution </Name>

+            <Default>1</Default>

+            <Desc>0 - 5   possible resolution</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>PER_Min_Resolution </Name>

+            <Default>1</Default>

+            <Desc>0 - 5   possible resolution</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Auto_Reset </Name>

+            <Default>20</Default>

+            <Desc>0 - 20  possible auto reset</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Read_Hardware_Register" type="sc" opcode="0xFF00">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF00</Default>

+            <Desc>HCIPP Read Hardware Register</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x001A0000</Default>

+            <Desc>HW register address (32 bit)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Value</Name>

+            <Default>Any</Default>

+            <Desc>The value to be read</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_Hardware_Register" type="sc" opcode="0xFF01">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF01</Default>

+            <Desc>HCIPP Write Hardware Register</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x001A0000</Default>

+            <Desc>HW register address (32 bit)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Value</Name>

+            <Default>0x0000</Default>

+            <Desc>The value to be written</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Read_Modify_Write_Hardware_Register" type="vc" opcode="0xFD09">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD09</Default>

+            <Desc>HCIPP Read Modify Write Hardware Register</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x001A0000</Default>

+            <Desc>HW register address (32 bit)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Value</Name>

+            <Default>0x0000</Default>

+            <Desc>The value to be written. Bits that equal 0 in the mask will be ignored.</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Mask</Name>

+            <Default>0x0000</Default>

+            <Desc>The bit mask of the bits that will be over-written. In every bit: 0=No change 1=Change.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Read_Modify_Write_Hardware_Register_32bit" type="sc" opcode="0xFF0D">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF0D</Default>

+            <Desc>HCIPP Read Modify Write Hardware Register</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x001A0000</Default>

+            <Desc>HW register address (32 bit)</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Value</Name>

+            <Default>0x00000000</Default>

+            <Desc>The value to be written. Bits that equal 0 in the mask will be ignored.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Mask</Name>

+            <Default>0x00000000</Default>

+            <Desc>The bit mask of the bits that will be over-written. In every bit: 0=No change 1=Change.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Read_Memory" type="sc" opcode="0xff02">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF02</Default>

+            <Desc>HCIPP Read Memory</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x00000000</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Type</Name>

+            <Default>01</Default>

+            <Desc>1 - UINT8, 2 - UINT16, 4 - UINT32</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Data</Name>

+            <Default>Any</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_Memory" type="sc" opcode="0xff03">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF03</Default>

+            <Desc>HCIPP Write Memory</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x00000000</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Type</Name>

+            <Default>01</Default>

+            <Desc>1 - UINT8, 2 - UINT16, 4 - UINT32</Desc>

+        </Param>

+        <Param type="u" size="len">

+            <Name>Value</Name>

+            <Default>0x00000000</Default>

+            <Desc>Types 1,2 - MSBytes don't care</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Read_Memory_Block" type="sc" opcode="0xFF04">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF04</Default>

+            <Desc>HCIPP Read Memory Block</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x00000000</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Size</Name>

+            <Default>01</Default>

+            <Desc>1-200</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+		<Param type="u" size="(packet_remain==2)*2" prop="r">

+            <Name>Data</Name>

+            <Default></Default>

+            <Desc>any</Desc>

+        </Param>

+        <Param type="x" size="(packet_remain>2)*packet_remain">

+            <Name>Data</Name>

+            <Default></Default>

+            <Desc>any</Desc>

+        </Param>	       

+    </Command>

+    

+    <Command name="HCI_VS_Write_Memory_Block" type="sc" opcode="0xFF05">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF05</Default>

+            <Desc>HCIPP Write Memory Block</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x00000000</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Size</Name>

+            <Default>04</Default>

+            <Desc>1-200</Desc>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Values</Name>

+            <Default>"00000000"</Default>

+            <Desc>Addresses increase from left to right</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_Memory_Block_To_DTST_Mem" type="sc" opcode="0xFD97">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD97</Default>

+            <Desc>HCIPP Write Memory Block To DTST Mem</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x00190200</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Size</Name>

+            <Default>04</Default>

+            <Desc>1-200</Desc>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Values</Name>

+            <Default>"00000000"</Default>

+            <Desc>Data starts from left to right</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+	<Command name="HCI_VS_Read_Memory_Block_From_DTST" type="sc" opcode="0xFD7F">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD7F</Default>

+            <Desc>HCIPP Read Memory Block From DTST Mem</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x00190200</Default>

+            <Desc />

+        </Param>

+		<Param type="u" size="1" label="len">

+            <Name>Size</Name>

+            <Default>04</Default>

+            <Desc>1-200</Desc>

+        </Param>

+		<Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="x" size="packet_remain">

+            <Name>Data</Name>

+            <Desc>any</Desc>

+        </Param>

+    </Command>

+

+    <Command name="HCI_VS_Write_BD_ADDR" type="sc" opcode="0xfc06">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFC06</Default>

+            <Desc>HCIPP Write BD Address</Desc>

+        </Param>

+        <Param type="b" size="6" prop="r">

+            <Name>New BD Addr</Name>

+            <Default>BD_ADDR</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_Frequency_Mode" type="sc" opcode="0xff06">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF06</Default>

+            <Desc>HCIPP Set Frequency Mode</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Frequency Mode</Name>

+            <Default>00</Default>

+            <Desc>0-79 Freqs, 1-23 (Spain), 2-23 (France), 3-Single Freq. Mode</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Single Frequency Index</Name>

+            <Default>00</Default>

+            <Desc>(0-22) / (0-78) in 23 / 79 Freq. Modes</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Get_Frequency_Mode" type="sc" opcode="0xff07">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF07</Default>

+            <Desc>HCIPP Get Frequency Mode</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Frequency</Name>

+            <Default>Any</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Configure_ARMIO" type="sc" opcode="0xff1a">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF1A</Default>

+            <Desc>HCIPP_CONFIGURE_ARM_IO</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Port number</Name>

+            <Default>0x0</Default>

+            <Desc>0-min, 0x12 -max</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>port direction</Name>

+            <Default>0x0</Default>

+            <Desc>1-Input, 0 -output</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_ARMIO_Port" type="sc" opcode="0xff1b">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF1B</Default>

+            <Desc>HCIPP Write ARMIO Port</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>ARMIO Port Number</Name>

+            <Default>00</Default>

+            <Desc>Range 0-18, except 0 &amp; 9</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>ARMIO Port Level</Name>

+            <Default>0</Default>

+            <Desc>0=False,  1=True</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Read_ARMIO_Port" type="sc" opcode="0xff1c">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF1C</Default>

+            <Desc>HCIPP Read ARMIO Port</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>ARMIO Port Number</Name>

+            <Default>0</Default>

+            <Desc>Range 0-18, except 0 &amp; 9</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+	    <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Value</Name>

+            <Default>0x00</Default>

+            <Desc>The value to be read</Desc>

+        </Param>

+	

+    </Command>

+    

+    <Command name="HCI_VS_Set_Supported_Features" type="sc" opcode="0xff26">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF26</Default>

+            <Desc>HCIPP Set Supported Features</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Byte</Name>

+            <Default>0xFF</Default>

+            <Desc>0 - Byte #0 , 1 - Byte #1 , 2 - Byte #2</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Bit</Name>

+            <Default>0xFF</Default>

+            <Desc>0..7 - single bit , 0xXX - WHOLE Byte value</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Support</Name>

+            <Default>0xFF</Default>

+            <Desc>0 - not supported , 1 - supported , FF - change WHOLE Byte</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Read_Patch_Version" type="sc" opcode="0xFF22">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF22</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="6" valtype="Patches_En">

+            <Name>Enabled Mask</Name>

+            <Default>0x00</Default>

+            <Desc>Bit mask of active patch traps</Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>ReleaseMajor</Name>

+            <Default>0x00</Default>

+            <Desc>Main Release Major Number – The upper byte of the base SW version that the patch package is referred to.</Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>ReleaseMinor</Name>

+            <Default>0x00</Default>

+            <Desc>Main Release Minor Number – The lower byte of the base SW version that the patch package is referred to.</Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>PackageID</Name>

+            <Default>0x00</Default>

+            <Desc>Patch Trap Package ID – A unique number for patch package. A patch package contains up to 32 different patch traps.</Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>Build Number</Name>

+            <Default>0x00</Default>

+            <Desc>Patch Trap Package Build Number – A unique number for the patch package build number. This is a serial number within the patch package.</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Get_Encryption_Key_Params" type="sc" opcode="0xff24">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF24</Default>

+            <Desc>HCIPP Get Encryption Key Params</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - success, 1 - illegal command</Desc>

+        </Param>

+        

+        <Param type="u" size="1">

+            <Name>Prefered Key Size</Name>

+            <Default>0x00</Default>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Max Key Size</Name>

+            <Default>0x00</Default>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Min Key Size</Name>

+            <Default>0x00</Default>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_Encryption_Key_Params" type="sc" opcode="0xff25">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF25</Default>

+            <Desc>HCIPP Set Encryption Key Params</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Preferred Key</Name>

+            <Default>0x10</Default>

+            <Desc>Default 16</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Max Key</Name>

+            <Default>0x10</Default>

+            <Desc>Default 16</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Min Key</Name>

+            <Default>0x05</Default>

+            <Desc>Default 5</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_DBG_Pins" type="sc" opcode="0xff32">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF32</Default>

+            <Desc>HCIPP Set DBG Pins</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="BT_Debug_pins">

+            <Name>DBG1 Value</Name>

+            <Default>0xFF</Default>

+            <Desc>The value to set to the DBG1 pin (0xFF=Don't change)</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="BT_Debug_pins">

+            <Name>DBG2 Value</Name>

+            <Default>0xFF</Default>

+            <Desc>The value to set to the DBG2 pin (0xFF=Don't change)</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="BT_Debug_pins">

+            <Name>DBG3 Value</Name>

+            <Default>0xFF</Default>

+            <Desc>The value to set to the DBG3 pin (0xFF=Don't change)</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="BT_Debug_pins">

+            <Name>DBG4 Value</Name>

+            <Default>0xFF</Default>

+            <Desc>The value to set to the DBG4 pin (0xFF=Don't change)</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="BT_Debug_pins">

+            <Name>DBG5 Value</Name>

+            <Default>0xFF</Default>

+            <Desc>The value to set to the DBG5 pin (0xFF=Don't change)</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="BT_Debug_pins">

+            <Name>DBG6 Value</Name>

+            <Default>0xFF</Default>

+            <Desc>The value to set to the DBG6 pin (0xFF=Don't change)</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="BT_Debug_pins">

+            <Name>DBG7 Value</Name>

+            <Default>0xFF</Default>

+            <Desc>The value to set to the DBG7 pin (0xFF=Don't change)</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="BT_Debug_pins">

+            <Name>DBG8 Value</Name>

+            <Default>0xFF</Default>

+            <Desc>The value to set to the DBG8 pin (0xFF=Don't change)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_QoS_Interval" type="sc" opcode="0xFF33">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF33</Default>

+            <Desc>HCIPP Set QOS Interval</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>0x0001</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>QOS Interval</Name>

+            <Default>19</Default>

+            <Desc>Poll period (a poll will be sent every poll period frames) Range: 1 - 255.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_AFH_Mode" type="sc" opcode="0xff39">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF39</Default>

+            <Desc>HCIPP Set AFH Mode</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>0x0001</Default>

+            <Desc>0x00FF - Set AFH mode for all connections, otherwise - choose connection Handle</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>AFH Mode</Name>

+            <Default>1</Default>

+            <Desc>0-Disable, 1-Enable</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Enable_Protocol_Viewer" type="sc" opcode="0xff68">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF68</Default>

+            <Desc>HCIPP Enable Protocol Viewer</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Enable</Name>

+            <Default>1</Default>

+            <Desc>0-Disable, 1-Enable</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Goto_Address" type="sc" opcode="0xff83">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF83</Default>

+            <Desc>HCIPP Goto Address</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x00028151</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Param 1</Name>

+            <Default>0x00000000</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Param 2</Name>

+            <Default>0x00000000</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Param 3</Name>

+            <Default>0x00000000</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Param 4</Name>

+            <Default>0x00000000</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_I2C_Register" type="sc" opcode="0xFE0E">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE0E</Default>

+            <Desc>HCIPP Write I2C Register</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Slave ID</Name>

+            <Default>0x71</Default>

+            <Desc>Codec 1: 0x71, Codec 2: 0x1A, E2PROM: 0x50</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>PVT CLK</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Working Frequency</Name>

+            <Default>0x190</Default>

+            <Desc>Codec = 0x190 (400 KHz), E2PROM = 0x64 (100 KHz)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Sub Address</Name>

+            <Default>0x00</Default>

+            <Desc>0-255. I2C Slave device internal register address.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Data Length</Name>

+            <Default>0x01</Default>

+            <Desc>1-16. Data Length (in bytes).</Desc>

+        </Param>

+        <Param type="x" size="16">

+            <Name>Data</Name>

+            <Default>"00"</Default>

+            <Desc>Data stream in hex, from left to right</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_I2C_Register_Enhanced" type="sc" opcode="0xFD36">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD36</Default>

+            <Desc>HCIPP Write I2C Register</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Slave ID</Name>

+            <Default>0x71</Default>

+            <Desc>Codec 1: 0x71, Codec 2: 0x1A, E2PROM: 0x50</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>PVT CLK</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Working Frequency</Name>

+            <Default>0x190</Default>

+            <Desc>Codec = 0x190 (400 KHz), E2PROM = 0x64 (100 KHz)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Address Access Size</Name>

+            <Default>0x01</Default>

+            <Desc>1-2 bytes of address (Max of 64Kbyte address space).</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Sub Address</Name>

+            <Default>0x0000</Default>

+            <Desc>I2C Slave device internal register address. 1-2 bytes, according to address access size field.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Data Length</Name>

+            <Default>0x01</Default>

+            <Desc>1-16. Data Length (in bytes).</Desc>

+        </Param>

+        <Param type="x" size="16">

+            <Name>Data</Name>

+            <Default>"00"</Default>

+            <Desc>Data stream in hex, from left to right</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+  

+    <Command name="HCI_VS_Read_I2C_Register" type="sc" opcode="0xFE0F">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE0F</Default>

+            <Desc>HCIPP Write I2C Register</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Slave ID</Name>

+            <Default>0x71</Default>

+            <Desc>Codec 1: 0x71, Codec 2: 0x1A, E2PROM: 0x50</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>PVT CLK</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Working Frequency</Name>

+            <Default>0x190</Default>

+            <Desc>Codec = 0x190 (400 KHz), E2PROM = 0x64 (100 KHz)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Sub Address</Name>

+            <Default>0x00</Default>

+            <Desc>0-255. I2C Slave device internal register address.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Param1_Event</Name>

+            <Default>HCIPP_READ_I2C_REGISTER</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_SCO_Configuration" type="sc" opcode="0xfe10">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE10</Default>

+            <Desc>HCIPP Write SCO Configuration</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Connection Type</Name>

+            <Default>0x01</Default>

+            <Desc>0 - Codec , 1 - HCI , 0xFF - don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>TX buffer size (for host)</Name>

+            <Default>120</Default>

+            <Desc>30-255 bytes, 0x0 - don't change</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>TX buffer max latency</Name>

+            <Default>511</Default>

+            <Desc>1-720 bytes, 0 - don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Accept packet with bad CRC</Name>

+            <Default>0xFF</Default>

+            <Desc>0x0/0x1 - Reject/Accept packet with bad CRC, 0xFF - Don't change</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>TX Buffer size</Name>

+            <Default>100</Default>

+            <Desc>0x1-0xFF TX buffer size for next channel to be activated</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Num of buffers</Name>

+            <Default>0x0</Default>

+            <Desc>0x0-0xFF - number of SCO TX buffers for next channel to be activated</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Read_SCO_Configuration" type="sc" opcode="0xfe11">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE11</Default>

+            <Desc>HCIPP Read SCO Configuration</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH#1 Connection type</Name>

+            <Default>0x1</Default>

+            <Desc>0 - Codec , 1 - HCI</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH#1 TX buffer size (for host)</Name>

+            <Default>100</Default>

+            <Desc>[0x1-0xFF] bytes</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH#1 Num of buffers</Name>

+            <Default>3</Default>

+            <Desc>[0x0-0xFF] - number of SCO TX buffers</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>CH#1 TX buffer max latency</Name>

+            <Default>511</Default>

+            <Desc>[1-511] bytes</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH#1 Accept packet with bad CRC</Name>

+            <Default>0xFF</Default>

+            <Desc>0x0/0x1 - Reject/Accept packet with bad CRC, 0xFF - Don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH#2 Connection type</Name>

+            <Default>0x1</Default>

+            <Desc>0 - Codec , 1 - HCI</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH#2 TX buffer size (for host)</Name>

+            <Default>100</Default>

+            <Desc>[0x1-0xFF] bytes</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH#2 Num of buffers</Name>

+            <Default>3</Default>

+            <Desc>[0x0-0xFF] - number of SCO TX buffers</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>CH#2 TX buffer max latency</Name>

+            <Default>511</Default>

+            <Desc>[1-511] bytes</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH#2 Accept packet with bad CRC</Name>

+            <Default>0xFF</Default>

+            <Desc>0x0/0x1 - Reject/Accept packet with bad CRC, 0xFF - Don't change</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Get_System_Status" type="sc" opcode="0xFE1F">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE1F</Default>

+            <Desc>HCIPP Get System Status</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0</Default>

+            <Desc>0 - Success, 1 - Illegal command</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>SW Version ("Major") </Name>

+            <Default>0</Default>

+            <Desc>X</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>SW Version ("Internal") </Name>

+            <Default>0</Default>

+            <Desc>Z</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Chip Revision</Name>

+            <Default>0</Default>

+            <Desc>HW Revision</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Chip mode</Name>

+            <Default>0</Default>

+            <Desc>0 - Palau, 1 - TI, 2-3 - Reserved, 4 - Borneo, 5 - Cayman</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>ROOT Clock</Name>

+            <Default>0</Default>

+            <Desc>in KHz</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Slow Clock used</Name>

+            <Default>0</Default>

+            <Desc>0 - Internal, 1 - External</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Process Type</Name>

+            <Default>1</Default>

+            <Desc>0 - Nominal, 1 - Weak, 2 - Strong</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Deep Sleep Mode</Name>

+            <Default>0</Default>

+            <Desc>0 - Disabled, 1 - Palau, 2 - HCILL</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Whitening Mode</Name>

+            <Default>0</Default>

+            <Desc>0 - Enabled, 1 - Disabled</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CDC Mode</Name>

+            <Default>0</Default>

+            <Desc>0 - Disabled, 1 - Enabled</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Self Test Result</Name>

+            <Default>0</Default>

+            <Desc>0 - Failed, 1 - Passed</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Hopping Mode</Name>

+            <Default>0</Default>

+            <Desc>0 - Freq Hopping, 1 - Single Freq Tx &amp; Rx, 2 - Only Tx Single Freq, 3 - Only Rx Single Freq</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>HCI UART Baud Rate</Name>

+            <Default>0</Default>

+            <Desc>in bps</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Temperature Index</Name>

+            <Default>1</Default>

+            <Desc>0 - Hot. 1 - Room. 2 - Cold. 3 - Warm. 4 - Cool</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Detected Temperature</Name>

+            <Default>0</Default>

+            <Desc>in Degrees (C), 0x00-0x7F Positive Value, 0xFF-0x80 Negative Value</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>I2C Status</Name>

+            <Default>0x00</Default>

+            <Desc>bit 0 - is I2C enabled, bit 1 - is E2PROM connected, bit 2 - is Codec connected</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>FREF/TCXO Clock</Name>

+            <Default>0</Default>

+            <Desc>in KHz</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="PLL_Sharing_Types">

+            <Name>PLL Sharing Running Mode</Name>

+            <Default>0x00</Default>

+            <Desc>Relevant for Wilink 7 Only.</Desc>

+        </Param>

+    </Command>

+       

+    <Command name="HCI_VS_Set_Pcm_Loopback_Enable" type="sc" opcode="0xFE28">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE28</Default>

+            <Desc>HCI_VS_Set_Pcm_Loopback_Configuration</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>PCM loopback enable</Name>

+            <Default>0x01</Default>

+            <Desc>0 - Stop PCM loopback operation, 1 - Start PCM loopback operation</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_Min_Sleep_Time" type="sc" opcode="0xfe2C">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE2C</Default>

+            <Desc>HCIPP Set Minimum Deep Sleep Time</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Minimum Deep Sleep Time [ms]</Name>

+            <Default>4</Default>

+            <Desc>Minimum Deep Sleep Time [in frames], will not go to deep sleep for less than that time.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_Max_Voice_Connections" type="sc" opcode="0xfe2f">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE2F</Default>

+            <Desc>HCIPP Set Max Voice Connections. Affects also Local Loopback</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Max Voice Connections</Name>

+            <Default>2</Default>

+            <Desc>0-2 Number of Voice Connections</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_Max_ACL_Connections" type="sc" opcode="0xfe34">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE34</Default>

+            <Desc>HCIPP Set Max ACL Connections. Affects also Local Loopback</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Max ACL Connections</Name>

+            <Default>7</Default>

+            <Desc>0-7 Number of ACL Connections</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Start_VS_Lock" type="sc" opcode="0xfe37">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE37</Default>

+            <Desc>Start VS Commands Lock (start of protected part of script)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Major Version Number</Name>

+            <Default>0</Default>

+            <Desc>The Major number of the SW Version (X)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Minor Version Number</Name>

+            <Default>0</Default>

+            <Desc>The Minor number of the SW Version (Z)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Stop_VS_Lock" type="sc" opcode="0xfe38">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE38</Default>

+            <Desc>Stop VS Commands Lock (end of protected part of the script)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Calculate_ROM_Checksum" type="sc" opcode="0xfe3a">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE3A</Default>

+            <Desc>HCIPP Calculate ROM Checksum</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Checksum</Name>

+            <Default>0x00000000</Default>

+            <Desc>The ROM Checksum</Desc>

+        </Param>

+        

+    </Command>

+    

+    <Command name="HCI_VS_Command_Complete_Calculate_ROM_Checksum_Event" type="ve" opcode="0xfe3a">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Timeout in msec</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Checksum</Name>

+            <Default>0x00000000</Default>

+            <Desc>The ROM Checksum</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Start_VS_Lock_Package" type="sc" opcode="0xfe3b">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE3b</Default>

+            <Desc>Start VS Commands Lock according package (start of protected part of script)</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="PackageType">

+            <Name>Package type</Name>

+            <Default>0</Default>

+            <Desc>chips with this package type should accept VS commands</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_PLL_Enable" type="sc" opcode="0xFD0F">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD0F</Default>

+            <Desc>HCIPP enables/disables the BRF6300 BB PLL</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>PLL Enable</Name>

+            <Default>0</Default>

+            <Desc>0 - Disable, 1 - Enable</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Host_Report_Fref_Drift" type="sc" opcode="0xFD10">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD10</Default>

+            <Desc>HCIPP Host Report Fref Drift</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Initial FREF drift</Name>

+            <Default>20</Default>

+            <Desc>Initial FREF drift in ppm</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Number of temperature ranges</Name>

+            <Default>0</Default>

+            <Desc>Number of temperature ranges that infuance the FREF clock</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Long_Buffers_Mode" type="sc" opcode="0xfd02">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD02</Default>

+            <Desc>HCIPP Long Buffers Mode</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Mode</Name>

+            <Default>0</Default>

+            <Desc>0-Disable (default), 1-Enable (1021 bytes)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="Set_Num_Of_HCI_Commands" type="sc" opcode="0xfd03">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD03</Default>

+            <Desc>ontrol the number of command buffers reported to the host</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Cmd control</Name>

+            <Default>1</Default>

+            <Desc>Number of maximum command buffers to report to the host. (1-4)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_Pcm_Loopback_Configuration" type="sc" opcode="0xFD04">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD04</Default>

+            <Desc>HCI_VS_Set_Pcm_Loopback_Configuration</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>PCM loopback delay</Name>

+            <Default>64</Default>

+            <Desc>delay in sample units [0-1348] </Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_CODEC_Config" type="sc" opcode="0xfd06">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD06</Default>

+            <Desc>HCIPP Write CODEC Configuration</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>PCM clock rate</Name>

+            <Default>2048</Default>

+            <Desc>[64-16000] The PCM clock rate is between 64k to 4096k (Master mode) or 64K to 16M (Slave mode), it influence other params like: wait cycles, freq rate calcs and therefore shall be configured even if external clock is used</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Role">

+            <Name>PCM direction/role</Name>

+            <Default>0x00</Default>

+            <Desc>PCM clock and fsync direction: 0x00 - output (Master on PCM bus) sampled on rising edge. 0x01 - input (Slave on PCM bus).</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Frame sync frequency</Name>

+            <Default>8000</Default>

+            <Desc>[100Hz-173KHz] Actual frame sync frequency in Hz.</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Frame sync duty cycle</Name>

+            <Default>0x0001</Default>

+            <Desc>0x0000 - 50 % of Fsync period, [0x0001-0xFFFF] - Number of PCM clock cycles</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Sampling_edge_type">

+            <Name>Frame sync edge</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 - Driven/sampled at rising edge, 0x01 - Driven/sampled at falling edge</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Frame sync polarity</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 - Active-high, 0x01 - Active-low</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0x00</Default>

+            <Desc>This field is reserved for future use - Must be set to 0.</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>CH1 data out size</Name>

+            <Default>0x0010</Default>

+            <Desc>[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>CH1 data out offset</Name>

+            <Default>0x0001</Default>

+            <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Sampling_edge_type">

+            <Name>CH1 out_edge</Name>

+            <Default>0x00</Default>

+            <Desc>Data driven: 0x00 - rising edge, 0x01 - falling edge</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>CH1 data in size</Name>

+            <Default>0x0010</Default>

+            <Desc>[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>CH1 data in offset</Name>

+            <Default>0x0001</Default>

+            <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Sampling_edge_type">

+            <Name>CH1 in_edge</Name>

+            <Default>0x01</Default>

+            <Desc>Data sampled: 0x00- rising edge, 0x01 - falling edge</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0x00</Default>

+            <Desc>This field is reserved for future use - Must be set to 0.</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>CH2 data out size</Name>

+            <Default>0x0010</Default>

+            <Desc>[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>CH2 data out offset</Name>

+            <Default>0x0011</Default>

+            <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Sampling_edge_type">

+            <Name>CH2 out_edge</Name>

+            <Default>0x00</Default>

+            <Desc>Data driven: 0x00 - rising edge, 0x01 - falling edge</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>CH2 data in size</Name>

+            <Default>0x0010</Default>

+            <Desc>[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>CH2 data in offset</Name>

+            <Default>0x0011</Default>

+            <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Sampling_edge_type">

+            <Name>CH2 in_edge</Name>

+            <Default>0x01</Default>

+            <Desc>Data sampled: 0x00- rising edge, 0x01 - falling edge</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0x00</Default>

+            <Desc>This field is reserved for future use - Must be set to 0.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_CODEC_Config_Enhanced" type="sc" opcode="0xfd07">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD07</Default>

+            <Desc>HCIPP Write CODEC Configuration </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>PCM clock shutdown</Name>

+            <Default>0x00</Default>

+            <Desc>PCM clock shutdown feature: 0x00 - disabled. 0x01 - enabled. Time of start stop is defined in the following 2 fields.</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>PCM clock start</Name>

+            <Default>0x0000</Default>

+            <Desc>[0x0000-0xFFFF] Number of PCM clock cycles relative to the PCM frame sync to start PCM clock (for example - start 2 clocks before frame sync).</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>PCM clock stop</Name>

+            <Default>0x0000</Default>

+            <Desc>[0x0000-0xFFFF] Number of PCM clock cycles relative to the PCM frame sync to stop PCM clock (for example - stop 20 clocks after frame sync).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0x00</Default>

+            <Desc>This field is reserved for future use - Must be set to 0.</Desc>

+        </Param>

+        <Param type="u" valtype="Codec_Data_Order" size="1">

+            <Name>CH1 data in order</Name>

+            <Default>0x04</Default>

+            <Desc>bit 0: 0-Data driven MSB-first; bit 1: 1-swap bytes within the sample in bit-wise mode; bit 2: 1-Shift sample by (24|16-dout_size) bits</Desc>

+        </Param>

+        <Param type="u"  valtype="Codec_Data_Order" size="1" >

+            <Name>CH1 data out order</Name>

+            <Default>0x04</Default>

+            <Desc>bit 0: 0-Data driven MSB-first; bit 1: 1-swap bytes within the sample in bit-wise mode; bit 2: 1-Shift sample by (24|16-dout_size) bits</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH1 data out mode</Name>

+            <Default>0x02</Default>

+            <Desc>0 - Always 3-state (input), 1 - Always output, 2 - Switch to 3-state (input) when idle</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH1 data out dup</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Retransmit last sample when no data available, 1 - Transmit DUP_VALUE when no data available</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>CH1 tx_dup_value</Name>

+            <Default>0x000000</Default>

+            <Desc>Replacement value to transmit when no data is available. ONLY 24-bits</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH1 data quant</Name>

+            <Default>0x00</Default>

+            <Desc>1 - Byte-wise mode, 0 - Bit-wise mode</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0x00</Default>

+            <Desc>This field is reserved for future use - Must be set to 0.</Desc>

+        </Param>

+        <Param type="u" valtype="Codec_Data_Order" size="1">

+            <Name>CH2 data in order</Name>

+            <Default>0x04</Default>

+            <Desc>bit 0: 0-Data driven MSB-first; bit 1: 1-swap bytes within the sample in bit-wise mode; bit 2: 1-Shift sample by (24|16-dout_size) bits</Desc>

+        </Param>

+        <Param type="u" valtype="Codec_Data_Order" size="1">

+            <Name>CH2 data out order</Name>

+            <Default>0x04</Default>

+            <Desc>bit 0: 0-Data driven MSB-first; bit 1: 1-swap bytes within the sample in bit-wise mode; bit 2: 1-Shift sample by (24|16-dout_size) bits</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH2 data out mode</Name>

+            <Default>0x02</Default>

+            <Desc>0 - Always 3-state (input), 1 - Always output, 2 - Switch to 3-state (input) when idle</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH2 data out dup</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Retransmit last sample when no data available, 1 - Transmit DUP_VALUE when no data available</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>CH2 tx_dup_value</Name>

+            <Default>0x000000</Default>

+            <Desc>Replacement value to transmit when no data is available. ONLY 24-bits</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CH2 data quant</Name>

+            <Default>0x00</Default>

+            <Desc>1 - Byte-wise mode, 0 - Bit-wise mode</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0x00</Default>

+            <Desc>This field is reserved for future use - Must be set to 0.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_hcill_parameters" type="sc" opcode="0xfd2b">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD2B</Default>

+            <Desc>hcill_parameters</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>inactivity_timeout</Name>

+            <Default>80</Default>

+            <Desc>Time from UART inactivity to sending SLEEP_IND. 0=BT never sends sleep_ind. Unit=Frames, 80 =100msec</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>RESERVED (retransmit_timeout)</Name>

+            <Default>0xFFFF</Default>

+            <Desc>0xFFFF=ignore this field. Timeout for resending WAKEUP_IND. 0=no retransmission. Unit=Frames</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>RESERVED (rts_minimum_pulse_width)</Name>

+            <Default>0xFF</Default>

+            <Desc>0xFF=ignore this field. RTS pulse may accompany WAKEUP_IND packet. 0=disable pulse. Unit=Micro seconds</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Update_Uart_HCI_Baudrate" type="sc" opcode="0xff36">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF36</Default>

+            <Desc>HCIPP Update Uart HCI Baudrate</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Uart Baudrate</Name>

+            <Default>115200</Default>

+            <Desc>Baud Rate - in bit/sec units.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Set_Uart_HCI_Baudrate" type="sc" opcode="0xff35">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFF35</Default>

+            <Desc>HCIPP Set Uart HCI Baudrate</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Divider</Name>

+            <Default>0</Default>

+            <Desc>Baudrate Uart Divider</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Oversampling</Name>

+            <Default>0</Default>

+            <Desc>Baudrate Uart Oversampling</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Swallow Period</Name>

+            <Default>0</Default>

+            <Desc>Baudrate Uart Swallow Period</Desc>

+        </Param>

+        

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_UART_Loopback_enable" type="sc" opcode="0xFD4B">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD4B</Default>

+            <Desc>HCIPP enable loopback at UART</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_TI_SPI_Configuration" type="sc" opcode="0xFD41">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD41</Default>

+            <Desc>configures TI SPI Interface</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Bits Direction</Name>

+            <Default>0</Default>

+            <Desc>0 - MSb First, LSb First</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Clock Polarity</Name>

+            <Default>1</Default>

+            <Desc>0 - Output changed on falling edge, Sampling on rising edge, 1 - Output changed on rising edge, Sampling on falling edge</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>clock_frequency</Name>

+            <Default>0</Default>

+            <Desc>Clock Frequency</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>miso_tri_state_enable</Name>

+            <Default>0</Default>

+            <Desc>0 - BTSPI MISO is output always , 1 - BTSPI MISO is in tri-state mode when the CS is de-asserted</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>fast_wakeup_enable</Name>

+            <Default>0</Default>

+            <Desc>0 - Disable, 1 - Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>BT SPI Mode</Name>

+            <Default>0</Default>

+            <Desc>0 - eSPI (H4), 1 - TI SPI (H4 Packet wise)</Desc>

+        </Param>

+        

+        <Param type="u" size="1">

+            <Name>BTSPI MISO Pull Enable</Name>

+            <Default>0</Default>

+            <Desc>0 - Disable, 1 - Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>BTSPI MOSI Pull Enable</Name>

+            <Default>0</Default>

+            <Desc>0 - Disable, 1 - Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>BTSPI Clock Pull Enable</Name>

+            <Default>0</Default>

+            <Desc>0 - Disable, 1 - Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>BTSPI IRQ Pull Enable</Name>

+            <Default>0</Default>

+            <Desc>0 - Disable, 1 - Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>BTSPI CS Pull Enable</Name>

+            <Default>0</Default>

+            <Desc>0 - Disable, 1 - Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>BTSPI Swap mode</Name>

+            <Default>0</Default>

+            <Desc>0 disable swap mode; 1 enable swap mode</Desc> 

+        </Param>

+        <Param type="u"  size="1">

+            <Name>BTSPI Block SPI IRQ</Name>

+            <Default>0</Default>

+            <Desc>0 - Disable (SW Control); 1 - Enable (HW Control); 2 - Dynamic Control</Desc> 

+        </Param>

+        <Param type="u" valtype="DO_IO_STRENGTH_5500_SELECT" size="1">

+            <Name>DO IO Strength</Name>

+            <Default>0</Default>

+            <Desc>5500 Only: 0x00 - Don't change; 0x2 - 2mAmp; 0x4 - 4mAmp; 0x6 - 6mAmp; 0x8 - 8mAmp</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved for future use</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved for future use</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_I2C_Write_to_FM" type="sc" opcode="0xFD35">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD35</Default>

+            <Desc>HCI_VS_I2C_Write_to_FM</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="FM_command" label="fm_opcode">

+            <Name>Fm_Opcode</Name>

+            <Default>0</Default>

+            <Desc>opcode of FM module [8 bits]</Desc>

+        </Param>

+        <Param cond="fm_opcode.lt.0x63 || fm_opcode.gt.0x65">

+            <Param type="u" size="2" prop="h">

+                <Name>Length</Name>

+                <Value>0x02</Value>

+            </Param>

+            <Param type="u" size="2" prop="r">

+                <Name>Data</Name>

+                <Default>0x0000</Default>

+                <Desc>Data to write</Desc>

+            </Param>

+        </Param>

+		  <Param cond="fm_opcode==0x64">

+			<Param type="u" size="2" prop="h">

+			 <Name>Length</Name>

+			 <Value>0x06</Value>

+			 </Param>

+			<Param type="u" size="4" prop="r">

+			 <Name>Address</Name>

+			 <Default>0x00000000</Default>

+			 <Desc>Address to write</Desc>

+			</Param>

+			<Param type="u" size="2" prop="r">

+			 <Name>Data</Name>

+			 <Default>0x0000</Default>

+			 <Desc>Data to write</Desc>

+			</Param>

+		  </Param>

+        <Param cond="fm_opcode==0x65">

+            <Param type="u" size="2" label="length">

+                <Name>Length</Name>

+                <Default>2</Default>

+                <Desc>Data Length 0-1024 [16 bits]</Desc>

+            </Param>

+            <Param type="x" size="length">

+                <Name>Data</Name>

+                <Default>"0000"</Default>

+                <Desc>start Address in hex (16 bit), and new code</Desc>

+            </Param>

+        </Param>

+        <Param cond="fm_opcode==0x63">

+            <Param type="u" size="2" label="length">

+                <Name>Length</Name>

+                <Default>04</Default>

+                <Desc>0-200 ???</Desc>

+            </Param>

+            <Param type="x" size="length">

+                <Name>Data</Name>

+                <Default>"00:00:00:00"</Default>

+                <Desc>Bytes are sent from left to right</Desc>

+            </Param>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_I2C_Read_FM" type="sc" opcode="0xFD33">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD33</Default>

+            <Desc>HCI_VS_I2C_Read_FM</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="FM_command" label="fm_opcode">

+            <Name>FM_Opcode</Name>

+            <Default>0</Default>

+            <Desc>opcode of FM module [8 bits]</Desc>

+        </Param>

+        <Param cond="fm_opcode!=0x05">

+            <Param type="u" size="2" prop="h" label="length">

+                <Name>Length</Name>

+                <Value>0x02</Value>

+            </Param>

+        </Param>

+        <Param cond="fm_opcode==0x05">

+            <Param type="u" size="2" label="length">

+                <Name>Length</Name>

+                <Default>0x0003</Default>

+                <Desc>Data Length [16 bits], should be multiple of 3, Max Length 250</Desc>

+            </Param>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="(packet_remain==2)*2" prop="r">

+            <Name>Value</Name>

+            <Default>0x0000</Default>

+            <Desc>Fm Read Value</Desc>

+        </Param>

+        <Param type="x" size="(packet_remain>2)*packet_remain">

+            <Name>RDS data</Name>

+            <Default></Default>

+            <Desc>RDS data</Desc>

+        </Param>

+    </Command>

+  <Command name="HCI_VS_I2C_Read_FM_HW_Register_32_bit_address" type="sc" opcode="0xFD45">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD45</Default>

+   <Desc>HCI_VS_I2C_Read_FM_HW_Register_32_bit_address</Desc>

+  </Param>

+  <Param type="u" size="4" label="address">

+   <Name>Address</Name>

+   <Default>0x00000000</Default>

+   <Desc>Fm register address [32 bits]</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+  <Param type="u" size="1" valtype="Status">

+   <Name>Status</Name>

+   <Default>0x00</Default>

+   <Desc>Status</Desc>

+  </Param>

+  <Param type="u" size="2" prop="r">

+   <Name>Value</Name>

+   <Default>"0x0000"</Default>

+   <Desc>Fm HW Register Value</Desc>

+  </Param>

+ </Command>

+    

+    <Command name="HCI_VS_I2C_FM_POWER_MODE" type="sc" opcode="0xFD37">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD37</Default>

+            <Desc>HCI_VS_I2C_FM_POWER_MODE</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="I2C_FM_Power_Mode_Enable_Types">

+            <Name>Enable Type</Name>

+            <Default>0</Default>

+            <Desc>Enable type for FM via I2C</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_I2C_FM_CHANGE_I2C_ADDRESS" type="sc" opcode="0xFD3A">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD3A</Default>

+            <Desc>HCI_VS_I2C_FM_CHANGE_I2C_ADDRESS</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Dev_Addr</Name>

+            <Default>0</Default>

+            <Desc>7 bits I2C Device Address </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Change_FM_I2C</Name>

+            <Default>0</Default>

+            <Desc>0 - change only awake device address.1 - change device address on both awake and FM I2C modules</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+    

+       <Command name="HCI_VS_SLIMBUS_CONFIGURATION" type="sc" opcode="0xFDB1">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDB1</Default>

+            <Desc>HCI_VS_SLIMBUS_CONFIGURATION</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>slimbus_on</Name>

+            <Default>0</Default>

+            <Desc>1: turn SLIMbus on, 0: turn slimbus off, 0xFF: don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>audio_enabled</Name>

+            <Default>1</Default>

+            <Desc>SLIMbus Audio: 1: enable, otherwise: don't change. Valid only if slimbus_on = 1</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>hci_enabled</Name>

+            <Default>1</Default>

+            <Desc>SLIMbus HCI: 1: enable, otherwise: don't change. Valid only if slimbus_on = 1</Desc>

+        </Param>

+         <Param type="u" size="1">

+            <Name>SLIMbus_core_off_during_pause</Name>

+            <Default>0</Default>

+            <Desc>Should SLIMbus core be turned off while the SLIMbus clock is paused: 1: enable, 0: disable, 0xFF: don't change.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>SLIMbus_core_off_during_OutOfBand_sleep</Name>

+            <Default>0</Default>

+            <Desc>Should SLIMbus core be turned off while in Deep-Sleep using OutOfBand protocol, regardless of clock pause: 1: enable, 0: disable, 0xFF: don't change.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Use_KALDO_when_BT_is_in_deep_sleep</Name>

+            <Default>0</Default>

+            <Desc>Should KALDO be used for driving the SLIMbus when the BT is in Deep-Sleep (rather than staying with DIGLDO): 1: enable, 0: disable, 0xFF: don't change.</Desc>

+        </Param>

+         <Param type="u" size="1">

+            <Name>debug_traces_level1_enabled</Name>

+            <Default>1</Default>

+            <Desc>SLIMbus Debug Level1 Traces (to Logger): 1: enable, 0: disable, 0xFF: don't change.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>debug_traces_level2_enabled</Name>

+            <Default>1</Default>

+            <Desc>SLIMbus Debug Level2 Traces (to Logger): 1: enable, 0: disable, 0xFF: don't change.</Desc>

+        </Param>

+       <Param type="u" size="1">

+            <Name>Reserved_1</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+       <Param type="u" size="1">

+            <Name>Reserved_2</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved_3</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved_4</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+       <Param type="u" size="1">

+            <Name>Reserved_5</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+       <Param type="u" size="1">

+            <Name>Reserved_6</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved_7</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved_8</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+       <Param type="u" size="1">

+            <Name>Reserved_9</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+       <Param type="u" size="1">

+            <Name>Reserved_10</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved_11</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved_12</Name>

+            <Default>0</Default>

+            <Desc>For future use</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+

+     <Command name="HCI_VS_sbis_parameters" type="sc" opcode="0xFDB2">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDB2</Default>

+            <Desc>sbis_parameters</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>inactivity_timeout</Name>

+            <Default>80</Default>

+            <Desc>Time from SLIMbus HCI inactivity to sending TX_SUSPENDED. 0=BT never sends TX_SUSPENDED. Unit=Frames, 80=100msec</Desc>

+        </Param>

+         <Param type="u" size="1">

+            <Name>rx_should_reset_inactivity_timer</Name>

+            <Default>0</Default>

+            <Desc>Values: 0xFF=Don't change, 0=RX activity does not influence TX suspending mechanism, 1=RX activity resets inactivity timer and sends TX_ENABLE request if TX is suspended</Desc>

+        </Param>

+         <Param type="u" size="1">

+            <Name>auto_tx_enable_upon_rx_enable</Name>

+            <Default>1</Default>

+            <Desc>Values: 0xFF=Don't change, 0=RX_ENABLE does not influence TX suspending mechanism, 1=Receiving RX_ENABLE from host will force sending TX_ENABLE request if TX is suspended, and will also reset the inactivity timer</Desc>

+        </Param>

+       <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+

+   <Command name="HCI_VS_Sleep_Mode_Configurations" type="sc" opcode="0xFD0C">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD0C</Default>

+            <Desc>HCIPP Sleep Mode Configurations. Use output io BT_FUNC 5 for TRIO alone!</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Big Sleep Enable</Name>

+            <Default>1</Default>

+            <Desc>0-disable, 1-enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Deep Sleep Enable</Name>

+            <Default>0</Default>

+            <Desc>0-disable, 1-enable</Desc>

+        </Param>

+        <Param type="u" valtype="SleepProtocolTypes" size="1">

+            <Name>Deep Sleep Mode</Name>

+            <Default>0xFF</Default>

+            <Desc>Deep Sleep Protocol Mode</Desc>

+        </Param>

+        <Param type="u" valtype="SLEEP_MODE_CONFIGURATION_OUTPUT_IO_SELECT" size="1">

+            <Name>Output IO Select</Name>

+            <Default>0xFF</Default>

+            <Desc>Output IO Select</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Output Pull Enable</Name>

+            <Default>0xFF</Default>

+            <Desc>0-disable, 1-enable, 0xFF Don't Change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Input Pull Enable</Name>

+            <Default>0xFF</Default>

+            <Desc>0-disable, 1-enable, 0xFF Don't Change</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="SLEEP_MODE_CONFIGURATION_INPUT_IO_SELECT">

+            <Name>Input io Select</Name>

+            <Default>0xFF</Default>

+            <Desc>IO on which BT_wakeup will be assereted by host</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>BORNEO Deassertion Timout</Name>

+            <Default>100</Default>

+            <Desc>Deassertion timout in milisecond (BORNEO mode only)</Desc>

+        </Param>

+        

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="HCI VS Commands in BTIP PG 1.0" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="HCI_VS_Set_PLL_mode" type="sc" opcode="0xFD23">

+        <Param type="o" size="2">

+            <Name>Opcode</Name> 

+            <Default>0xFD23</Default> 

+            <Desc>sets which band the baseband PLL should work with and enables forcing the dividers.</Desc> 

+        </Param>

+        <Param type="u" size="1" valtype="PLL_band">

+            <Name>PLL_band</Name> 

+            <Default>0</Default> 

+            <Desc>40MHz output (Europe) / 48MHz output (Japan) / 0xFF don't change</Desc> 

+        </Param>

+        <Param type="u" size="2">

+            <Name>M Value</Name> 

+            <Default>0</Default> 

+            <Desc>Value For M divider. 0xFFFF for don't change</Desc> 

+        </Param>

+        <Param type="u" size="2">

+            <Name>N Value</Name> 

+            <Default>0</Default> 

+            <Desc>Value For N divider. 0xFFFF for don't change</Desc> 

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name> 

+            <Default />

+            

+            <Desc />

+            

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Config_Acl_Data_Statistics" type="sc" opcode="0xFD5A">

+        <Param type="o" size="2">

+            <Name>Opcode</Name> 

+            <Default>0xFD59</Default> 

+            <Desc>Configure the ACL data statistics parameters. Once called, data throughput statistics will be printed to the logger</Desc> 

+        </Param>

+        <Param type="u" size="1">

+            <Name>ACL Statistics Enable</Name> 

+            <Default>0x1</Default> 

+            <Desc>Enable/Disable Statistics printings to the logger</Desc> 

+        </Param>

+        <Param type="u" size="2">

+            <Name>Printings Interval</Name> 

+            <Default>5000</Default> 

+            <Desc>Time in milisec between one logger printing to another not including sleep time</Desc> 

+        </Param>

+        <Param type="u" size="1">

+            <Name>Get Static from Handle</Name> 

+            <Default>0xFF</Default> 

+            <Desc>0xFF- Don't print,0x00-0x06 print static from the current handle.</Desc> 

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name> 

+            <Default />            

+            <Desc />

+        </Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Default>0</Default>

+			<Desc>0 - Success</Desc>

+		</Param>

+		<Param type="u" size="4">

+			<Name>RX Result</Name>

+			<Default>0</Default>

+			<Desc />

+		</Param>

+		<Param type="u" size="4">

+			<Name>TX Result</Name>

+			<Default>0</Default>

+			<Desc />

+		</Param>

+			<Param type="u" size="4">

+			<Name>NACK Ratio</Name>

+			<Default>0</Default>

+			<Desc />

+		</Param>  

+	</Command>

+    

+    <Command name="HCI_VS_Set_LPS_Params_BTIP" type="sc" opcode="0xFD2E">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD2E</Default>

+            <Desc>HCIPP Set Low Power Scan Params</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Enable</Name>

+            <Default>0x1</Default>

+            <Desc>0 - Disable, 1 - Enable</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Disable sweeps length</Name>

+            <Default>600</Default>

+            <Desc>Number of scans after LPS exit to return back to LPS </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Positive sweeps Threshold</Name>

+            <Default>5</Default>

+            <Desc>Number of consequent positive scans to exit LPS</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Enable LPS in active connection</Name>

+            <Default>0</Default>

+            <Desc>1 - run LPS scan in active connection. 0 - run LPS only in Idle mode</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>minimum time between scan</Name>

+            <Default>30</Default>

+            <Desc>The minimum time betweet to LPS scan in frame (1.25 msec)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>scans history max length</Name>

+            <Default>7</Default>

+            <Desc>The number of lps scan results to remember for positive scans counting (max: 32)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name> 

+            <Default />

+            

+            <Desc />

+            

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Write_Wlan_Configuration_BTIP" type="sc" opcode="0xFD66">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD66</Default>

+            <Desc>HCIPP Setup Gemini interface in BTIP</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Enable Mode</Name>

+            <Default>0xFF</Default>

+            <Desc>0x4-Soft Gemini Palau; 0x5-Soft Gemini Borneo; All others - Reserved; </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>PA Configuration</Name>

+            <Default>0xFF</Default>

+            <Desc>0xFF - Don't change; bit0 - PA off polarity (0 = Active Low)</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="WLAN_TX_RX_MODE">

+            <Name>TX_mode</Name>

+            <Default>0xFF</Default>

+            <Desc>Configures the TX mode</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="WLAN_TX_RX_MODE">

+            <Name>RX_mode</Name>

+            <Default>0xFF</Default>

+            <Desc>Configures the RX mode</Desc>

+        </Param>

+        <Param type="u" size="2" valtype = "Wlan_Priority_select">

+            <Name>Priority select</Name>

+            <Default>0xFFFF</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Connection handle select</Name>

+            <Default>0xFF</Default>

+            <Desc>0x0-0xEFF - select the connection handle; 0xF000 - Disable priority on all handles; 0xFFFF - Don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Connection handle enable</Name>

+            <Default>0xFF</Default>

+            <Desc>0 - Disable; 1- Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Freq_mask_enable</Name>

+            <Default>0xFF</Default>

+            <Desc>0xFF - Do not change; 0x0 - No Freq mask; 0x1 - Enable freq mask on WLAN 0; 0x2 - Enable freq mask on WLAN 1; 0x3 - Enable freq mask on WLAN0 and WLAN1</Desc>

+        </Param>

+        <Param type="x" size="10">

+            <Name>Freq mask</Name>

+            <Default>"FFFFFFFFFFFFFFFFFFFF"</Default>

+            <Desc>Frequency mask</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>WLAN013_BT_IP_selected_pin</Name>

+            <Default>0xFF</Default>

+            <Desc>ORCA Only

+            0: Mux WLAN0, WLAN1 and WLAN3 on the FM_I2S i/f ports, WLAN0 on FM_I2S_DI, WLAN1 on FM_I2S_WS, WLAN3 on FM_I2S_DO

+            1: Mux WLAN0, WLAN1 and WLAN3 on the FM I2C i/f ports,	WLAN0 on FM_IRQ, WLAN1 on FM_SDA, WLAN3 on FM_SCL

+            2: Mux WLAN0, WLAN1 and WLAN3 as seen below, WLAN0 on BT_FUNC2, WLAN1 on BT_FUNC1, WLAN3 on FM_I2S_DO

+ NL5500+1270 

+            3: Mux WLAN0, WLAN1 and WLAN3 as seen below, WLAN0 on FM_SDA/BT_FUNC4, WLAN1 on FM_IRQ/BT_FUNC5, WLAN3 on BT_GPIO5/BT_FUNC7

+ NL5500 

+            4: Mux WLAN0, WLAN1 and WLAN3 as seen below, WLAN0 on BT_GPIO2/BT_FUNC4, WLAN1 on BT_GPIO4/BT_FUNC6, WLAN3 on BT_GPIO5/BT_FUNC7

+            5: Mux WLAN0, WLAN1 and WLAN3 as seen below, WLAN0 on FM_SDA/BT_FUNC4, WLAN1 on FM_I2S_CLK/BT_FUNC6, WLAN3 on FM_I2S_FSYNC/BT_FUNC7

+Quattro

+			6: Mux WLAN0, WLAN1 and WLAN3 as seen below, WLAN0 on BT_FUNC5, WLAN1 on BT_FUNC6, WLAN3 on BT_FUNC7

+            </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>WLAN2_BT_IP_selected_pin</Name>

+            <Default>0xFF</Default>

+            <Desc>0: Mux WLAN2 on the FM_I2S_CLK port, 1: Mux WLAN2 on the CLK_REQ_OUT 

+            	  Not Used For NL5500 and Quattro				  

+            </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Wlan0 pull enable</Name>

+            <Default>0xFF</Default>

+            <Desc>0xFF - Don't change; 0 - Pull set by IP, 1 - Input pull (on selected input IO) is disabled; 2 - Input pull (on selected input IO) is enabled.

+For Quattro:

+00 => IP pull control (default).

+01 => Pull Up.

+10 => Pull down.

+11 => Pull disabled.

+			</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Wlan1 pull enable</Name>

+            <Default>0xFF</Default>

+            <Desc>0xFF - Don't change; 0 - Pull set by IP, 1 - Input pull (on selected input IO) is disabled; 2 - Input pull (on selected input IO) is enabled.

+For Quattro:

+00 => IP pull control (default).

+01 => Pull Up.

+10 => Pull down.

+11 => Pull disabled.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Wlan2 pull enable</Name>

+            <Default>0xFF</Default>

+            <Desc>0xFF - Don't change; 0 - Pull set by IP, 1 - Input pull (on selected input IO) is disabled; 2 - Input pull (on selected input IO) is enabled. Not supported for QUATTRO </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Wlan3 pull enable</Name>

+            <Default>0xFF</Default>

+            <Desc>0xFF - Don't change; 0 - Pull set by IP, 1 - Input pull (on selected input IO) is disabled; 2 - Input pull (on selected input IO) is enabled

+For Quattro:

+00 => IP pull control (default).

+01 => Pull Up.

+10 => Pull down.

+11 => Pull disabled.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Disable WLAN</Name>

+            <Default>0x0</Default>

+            <Desc>0x0 - Don't do anything; 0x1 - Disable WLAN;; 0x2 - Enable BT mechanism for NL5500 +1270 </Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+   

+    <Command name="HCI_VS_Write_GSM_Configuration" type="sc" opcode="0xFD68">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD68</Default>

+            <Desc>HCIPP Setup sync scans to GSM wakeup</Desc>

+        </Param>

+        <Param type="1" size="1" valtype="GSM_CONFIGURATION_ORCA_SELECT">

+            <Name>Enable Mode</Name>

+            <Default>0xFF</Default>

+            <Desc>0x0 - Enable; 0x1-Enable on BT_FUNC1; 0x2-Enable on BT_FUNC2; 0x3-Enable on BT_FUNC3; 0x4-Enable on BT_FUNC4;0x5-Enable on BT_FUNC5; 0x7-Enable on BT_FUNC7; 0xFF-Disable</Desc>

+        </Param>

+        <Param type="1" size="1">

+            <Name>Clock active pull enable</Name>

+            <Default>0xFF</Default>

+            <Desc>0xFF - Don't change; 0x0 - Input pull disabled; 0x1 Input pull enabled</Desc>

+        </Param>

+        <Param type="2" size="2">

+            <Name>min page scan interval</Name>

+            <Default>0x0800</Default>

+            <Desc>Minimal interval in baseband slots between page scans. Range 0x0012 - 0x1000</Desc>

+        </Param>

+        <Param type="2" size="2">

+            <Name>min inquiry scan interval</Name>

+            <Default>0x0800</Default>

+            <Desc>Minimal interval in baseband slots between inquiry scans. Range 0x0012 - 0x1000</Desc>

+        </Param>

+        <Param type="1" size="1">

+            <Name>IRQ wakeup type</Name>

+            <Default>0xFF</Default>

+            <Desc>The type of the wakeup: 0x0 - Slow, 0x1 - Fast; 0xFF do not change</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Config_Power_Mng_Params" type="sc" opcode="0xFD58">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD58</Default>

+            <Desc>HCIPP Config Power Mng Params</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Enable flag</Name>

+            <Default>1</Default>

+            <Desc>When set to 1, indicates enabling of power management algorithm</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>rssi_thl_acl (dBm) </Name>

+            <Default>-60</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>rssi_thl_sco (dBm) </Name>

+            <Default>-60</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>rssi_thl_edr3 (dBm) </Name>

+            <Default>-60</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>rssi_thh_acl (dBm) </Name>

+            <Default>-40</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>rssi_thh_sco (dBm) </Name>

+            <Default>-40</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>rssi_thh_edr3 (dBm) </Name>

+            <Default>-40</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>rssi_vhth (dBm) </Name>

+            <Default>-20</Default>

+            <Desc />

+        </Param>

+        

+        <Param type="u" size="1">

+            <Name>rssi_vhth_edr3 (dBm) </Name>

+            <Default>-15</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>rssi_th_sensitivity</Name>

+            <Default>-80</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>snr_thl</Name>

+            <Default>0</Default>

+            <Desc>0 - disable SNR condition.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>snr_edr3_thl</Name>

+            <Default>0</Default>

+            <Desc>0 - disable SNR condition.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>snr_thh</Name>

+            <Default>0</Default>

+            <Desc>0 - disable SNR condition.</Desc>

+        </Param>

+        

+        <Param type="u" size="1">

+            <Name>snr_edr3_thh</Name>

+            <Default>0</Default>

+            <Desc>0 - disable SNR condition.</Desc>

+        </Param>

+        

+        <Param type="u" size="1">

+            <Name>bad_sync_count_th_sco</Name>

+            <Default>3</Default>

+            <Desc />

+        </Param>

+        

+        <Param type="u" size="1">

+            <Name>fec_ration_thl_sco</Name>

+            <Default>20</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>fec_ration_thh_sco</Name>

+            <Default>10</Default>

+            <Desc />

+        </Param>

+        

+        <Param type="u" size="2">

+            <Name>fec_min_bits_acl</Name>

+            <Default>144</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>fec_min_bits_sco</Name>

+            <Default>144</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>crc_ratio_thl_acl</Name>

+            <Default>60</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>crc_ratio_thh_acl</Name>

+            <Default>2</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>min_pkts_acl</Name>

+            <Default>50</Default>

+            <Desc>Minimum number of packets to calculate CRC statistics</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>power_decision_time</Name>

+            <Default>2</Default>

+            <Desc>The interval, in which a decision is made whether to increase/decrease or not to change peer tx power (decision interval = power_decision_time x100ms)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>power_acl_response_time</Name>

+            <Default>1</Default>

+            <Desc>On ACL channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>power_sco_response_time</Name>

+            <Default>1</Default>

+            <Desc>On E/SCO channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>power_edr3_response_time</Name>

+            <Default>1</Default>

+            <Desc>On EDR3 channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)</Desc>

+        </Param>

+        

+        <Param type="u" size="1">

+            <Name>power_delay_time</Name>

+            <Default>3</Default>

+            <Desc>The minimal delay between the last command requested to increase power or decrease to the command request to decrease power (delay interval = power_delay_time x power_decision_time x 100ms)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>deep_fade_rssi_delta1 (dBm)</Name>

+            <Default>-10</Default>

+            <Desc>rssi threshold between current measure and the previews measure	to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-1]) </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>deep_fade_rssi_delta2 (dBm)</Name>

+            <Default>-20</Default>

+            <Desc>rssi threshold between current measure and the one before the preview measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-2])</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>deep_fade_edr3_rssi_delta1 (dBm)</Name>

+            <Default>-10</Default>

+            <Desc>rssi threshold between current measure and the previews measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-1] </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>deep_fade_edr3_rssi_delta2 (dBm)</Name>

+            <Default>-20</Default>

+            <Desc>rssi threshold between current measure and the one before the preview measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-2])</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+  <Command name="HCI_VS_Config_CQDDR_Params" type="sc" opcode="0xFD64">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD64</Default>

+   <Desc>HCIPP Config CQDDR Params</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Enable flag</Name>

+   <Default>1</Default>

+   <Desc>0=Disabled 1=Enabled. When set to 1, indicates enabling of the CQDDR algorithm.</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>reserved</Name>

+   <Default>0</Default>

+   <Desc />

+  </Param>

+ <Param type="u" size="4">

+   <Name>rssi_on_max_slot_1_thr</Name>

+   <Default>-69</Default>

+   <Desc>-100..100. The RSSI threshold for changing the CQDDR state to EDR2 when max slot is 1.</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>rssi_off_max_slot_1_thr</Name>

+   <Default>-69</Default>

+   <Desc>-100..100. The RSSI threshold for changing the CQDDR state to EDR3 when max slot is 1.</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>rssi_on_max_slot_3_thr</Name>

+   <Default>-67</Default>

+   <Desc>-100..100. The RSSI threshold for changing the CQDDR state to EDR2 when max slot is 3.</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>rssi_off_max_slot_3_thr</Name>

+   <Default>-67</Default>

+   <Desc>-100..100. The RSSI threshold for changing the CQDDR state to EDR3 when max slot is 3.</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>rssi_on_max_slot_5_thr</Name>

+   <Default>-67</Default>

+   <Desc>-100..100. The RSSI threshold for changing the CQDDR state to EDR2 when max slot is 5.</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>rssi_off_max_slot_5_thr</Name>

+   <Default>-67</Default>

+   <Desc>-100..100. The RSSI threshold for changing the CQDDR state to EDR3 when max slot is 5.</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>rssi_thr_offset</Name>

+   <Default>0</Default>

+   <Desc>-100..100. The RSSI threshold offset.</Desc>

+  </Param>

+   <Param type="u" size="2">

+   <Name>ber_fec_on_thr</Name>

+   <Default>1</Default>

+   <Desc>0..65535. The BER threshold for changing the CQDDR state to FEC_ON.</Desc>

+  </Param>

+  <Param type="u" size="2">

+   <Name>ber_fec_off_thr</Name>

+   <Default>6000</Default>

+   <Desc>0..65535. The BER threshold for changing the CQDDR state to FEC_OFF.</Desc>

+  </Param>

+  <Param type="u" size="2">

+   <Name>ber_fec_off_esco_thr</Name>

+   <Default>0</Default>

+   <Desc>0..65535. The BER threshold for changing the CQDDR state to FEC_OFF at eSCO connection. ***RESERVED***</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>per_fec_on_max_slot_1_thr</Name>

+   <Default>10</Default>

+   <Desc>0..255. The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR2 when max slot is 1. ***RESERVED***</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>per_fec_off_max_slot_1_thr</Name>

+   <Default>0</Default>

+   <Desc>0..100. The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR3 when max slot is 1. ***RESERVED***</Desc>

+  </Param>

+ <Param type="u" size="1">

+   <Name>per_fec_on_max_slot_3_thr</Name>

+   <Default>30</Default>

+   <Desc>0..100. The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR2 when max slot is 3.</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>per_fec_off_max_slot_3_thr</Name>

+   <Default>0</Default>

+   <Desc>0..100. The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR3 when max slot is 3. ***RESERVED***</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>per_fec_on_max_slot_5_thr</Name>

+   <Default>30</Default>

+   <Desc>0..100 The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR2 when max slot is 5.</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>per_fec_off_max_slot_5_thr</Name>

+   <Default>0</Default>

+   <Desc>0..100. The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR3 when max slot is 5. ***RESERVED***</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>enable in basic rate</Name>

+   <Default>0</Default>

+   <Desc>0 - Disable, 1-Enable Cqddr in basic rate</Desc>

+  </Param>  

+  <Param type="u" size="1">

+   <Name>timer_thr</Name>

+   <Default>3</Default>

+   <Desc>0..100. The minimum time (1 unit = 400ms) before returning to EDR3 due to good hec &amp; crc. ***RESERVED***</Desc>

+  </Param>  

+  <Param type="u" size="2">

+   <Name>Debug handle</Name>

+   <Default>0xFFFF</Default>

+   <Desc>Connection handle.0xFFFF - debug not valid</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Enable/Disable Cqddr in Tx/Rx</Name>

+   <Default>0x11</Default>

+   <Desc>0x00:tx disable,rx disable;0x10:tx enable,rx disable;0x01:tx disable,rx enable;0x11;tx enable,rx enable</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+ </Command>

+

+    <Command name="HCI_VS_Fast_Clock_Configuration_btip" type="sc" opcode="0xFD1C">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD1C</Default>

+            <Desc>HCIPP configures the BTIP fast clock configuration</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>XTAL Enable</Name>

+            <Default>0xFF</Default>

+            <Desc>0 - Disable, 1 - Enable, 0xFF - Don't Change</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Normal Wakeup Settling Time</Name>

+            <Default>5000</Default>

+            <Desc>Normal WakeUp settling time (in uS)</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Fast Wakeup Settling Time</Name>

+            <Default>2000</Default>

+            <Desc>Fast WakeUp settling time (in uS)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Fast wakeup enable</Name>

+            <Default>0xFF</Default>

+            <Desc>0x00 - disabled For BT and FM. 0x01 - enabled For BT, disabled for FM. 0x10 - enabled For FM, disabled for BT. 0x11 - enabled For BT and FM. 0xFF - Dont Change.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>XTAL Boost Gain</Name>

+            <Default>0xFF</Default>

+            <Desc>This parameter determines the initial gain of the OSC cell</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>XTAL Normal Gain</Name>

+            <Default>0xFF</Default>

+            <Desc>This parameter determines the steady state gain of the OSC cell</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>BT TX Slicer Trim</Name>

+            <Default>0xFF</Default>

+            <Desc>This parameter determines the Slicer gain when BT is during TX/RX</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>BT idle Slicer Trim</Name>

+            <Default>0xFF</Default>

+            <Desc>This parameter determines the Slicer gain when BT is during TX/RX</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Fast Clock AC/DC Coupling</Name>

+            <Default>0xFF</Default>

+            <Desc>0 - DC Coupling, 1 - AC Coupling</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Slow Clock Accuracy</Name>

+            <Default>250</Default>

+            <Desc>Slow clock drift (PPM)</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="5500_clock_sources">

+            <Name>Clock Source</Name>

+            <Default>0</Default>

+            <Desc>0 for FREF, 1 for TCXO (5500 only)</Desc>

+        </Param>

+		<Param type="u" size="1">

+            <Name>GCM extra settling time</Name>

+            <Default>0</Default>

+            <Desc>Extra settling time to add to default settling time</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Success, Else - Error</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Configure_Clock_Sharing_bt_ip" type="sc" opcode="0xFD6A">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD6A</Default>

+            <Desc>HCIPP Configure Clock Sharing</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Polarity</Name>

+            <Default>1</Default>

+            <Desc>0- Active Low Polarity, 1- Active High Polarity</Desc>

+        </Param>

+        <Param type="u" valtype="ClockSharingOutputMode_BT_IP" size="1">

+            <Name>Clock Sharing Output Mode</Name>

+            <Default>0</Default>

+            <Desc>Clock Sharing Outout Mode</Desc>

+        </Param>

+        <Param type="u" valtype="EnableDisableDefaultNoChange" size="1">

+            <Name>Output pull Enable</Name>

+            <Default>0</Default>

+            <Desc>0-disable; 1-enable;</Desc>

+        </Param>

+		<Param type="u" valtype="ClkSharingPullConfiguration_BT_IP" size="1">

+            <Name>Pull configuration</Name>

+            <Default>0</Default>

+            <Desc>Only relevant for 5500: 0-disable pull; 1-enable pull;</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Configure_channel_classification_params" type="sc" opcode="0xfd63">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xfd63</Default>

+            <Desc>HCI_VS_Configure_channel_classification_params</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Pattern length in ACTIVE</Name>

+            <Default>15</Default>

+            <Desc>number of scans in an AFH pattern, value must be less than 16</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Pattern length in SHORT_SNIFF (only)</Name>

+            <Default>7</Default>

+            <Desc>number of scans in an AFH pattern, value must be less than 16</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Pattern length in LONG_SNIFF (only)</Name>

+            <Default>4</Default>

+            <Desc>number of scans in an AFH pattern, value must be less than 16</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>SHORT to LONG SNIFF transition threshold</Name>

+            <Default>100</Default>

+            <Desc>Threshold Tsniff period which will be considered as short / longsniff [in slots ] comparison is minimal_T_sniff to threshold , minimal_T_sniff includes subrating </Desc>

+        </Param>

+        <Param type="u" size="8">

+            <Name>Active pattern timing array</Name>

+            <Default>0x89abcdef89abcdef</Default>

+            <Desc>array holding the number of idle frames between scans (in a pattern)

+                each nibble (value 1 to 15) represents the time between two scans

+                nibble 0,(byte[0] bits[3:0] is the number of frames between the first and second scan

+                nibble 1,(byte[0] bits[7:4] is the number of frames between the second and third scan

+            </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Const interferer sequence count</Name>

+            <Default>3</Default>

+            <Desc>the number of scans where a narrow band interferer must be seen in order to be classified as bad (and removed)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Clear channel sequence count</Name>

+            <Default>6</Default>

+            <Desc>the number of patterns where a channel must be clean in order to be classified as good (and returned)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Increase priority rejection threshold</Name>

+            <Default>10</Default>

+            <Desc>the number of times an AFH scan can be "bumped" by other activities before raising its priority</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Number of slots between scan patterns</Name>

+            <Default>800</Default>

+            <Desc>the number of slots from the end of a pattern to the activation of another</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>C_to_I threshold 0 2</Name>

+            <Default>75</Default>

+            <Desc>threshold between grade 0 to 2, 17dB = 7.07 >> times 10 is 71</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>C_to_I  threshold 2 3</Name>

+            <Default>56</Default>

+            <Desc>threshold between grade 2 to 3, 15dB = 5.6 >> times 10 is 56</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>C_to_I  threshold 3 4</Name>

+            <Default>31</Default>

+            <Desc>threshold between grade 3 to 4,  10dB = 3.1 >> times 10 is 31</Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>RSSI level 1 for threshold shift</Name>

+            <Default>-65</Default>

+            <Desc>RSSI level 1 in which the C/I to GRADE thresholds are updated</Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>RSSI level 2 for threshold shift</Name>

+            <Default>-75</Default>

+            <Desc>RSSI level 2 in which the C/I to GRADE thresholds are updated</Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>Min RSSI level for grading</Name>

+            <Default>-80</Default>

+            <Desc>min RSSI level for which channels are graded based on GEORTZEL result </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Wideband detection enabled</Name>

+            <Default>1</Default>

+            <Desc>1 - enable checking for wideband interferer on a single scan result, 0- disable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Wideband detection half window size</Name>

+            <Default>5</Default>

+            <Desc>How many channels to look forward / backward from current channel for wideband interferer detection</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Wideband detection half window threshold</Name>

+            <Default>4</Default>

+            <Desc>How many channels in side window need to be bad inorder for channel to be classified as having a wideband interferer</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Wideband detection full window threshold</Name>

+            <Default>8</Default>

+            <Desc>How many channels in entire window need to be bad inorder for channel to be classified as having a wideband interferer</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Config_AFH_IN_HV1" type="sc" opcode="0xFE47">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE47</Default>

+            <Desc>HCI_VS_Config_AFH_IN_HV1</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Pattern Detection Enable</Name>

+            <Default>1</Default>

+            <Desc>0 - disable, 1 - enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Pattern Detection Window size</Name>

+            <Default>11</Default>

+            <Desc>length of the pattern window</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Pattern Detection Errors within window</Name>

+            <Default>2</Default>

+            <Desc>number of error that will be fixed</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Pattern Detection Margin</Name>

+            <Default>1</Default>

+            <Desc>Good channels that will be removed from each margin</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>CCM sample period</Name>

+            <Default>1</Default>

+            <Desc>How many times CCM is update before reading CCM results (unit of 25mS)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Accumulate threshold</Name>

+            <Default>40</Default>

+            <Desc>How many times CCM results are read before processing data (units of "CCM sample period")</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Min hits th 1</Name>

+            <Default>2</Default>

+            <Desc>When minimal RSSI is above "TH switch RSSI": Minimal number of HEC events for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Good HEC percent TH 1</Name>

+            <Default>70</Default>

+            <Desc>When minimal RSSI is above "TH switch RSSI":Percentage of good HEC for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests) </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Min SNR th 1</Name>

+            <Default>0</Default>

+            <Desc>When minimal RSSI is above "TH switch RSSI":Minimal PHY SNR for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests), in dB</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Min hits th 2</Name>

+            <Default>2</Default>

+            <Desc>When minimal RSSI is below "TH switch RSSI": Minimal number of HEC events for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Good HEC percent TH 2</Name>

+            <Default>70</Default>

+            <Desc>When minimal RSSI is below "TH switch RSSI":Percentage of good HEC for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests), in percent </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Min SNR th 2</Name>

+            <Default>0</Default>

+            <Desc>When minimal RSSI is below "TH switch RSSI":Minimal PHY SNR for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests), in dB</Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>TH switch RSSI</Name>

+            <Default>-72</Default>

+            <Desc>RSSI level at which other thresholds are switched, in dBm</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>HV1 return channel threshold</Name>

+            <Default>50</Default>

+            <Desc>minimal munber of good channels allowed in HV1, when reaching this number all channels are returned</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>HV1 return timer</Name>

+            <Default>60</Default>

+            <Desc>time in seconds for channel return in HV1 (stand alone timer, not restared at channel drop)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_switch_from_tcxo_to_fref" type="sc" opcode="0xFE48">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE48</Default>

+            <Desc>HCI_VS_switch_from_tcxo_to_fref</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+	

+    <Command name="HCI_VS_Set_Clk_Req_Mode_For_TCXO" type="sc" opcode="0xFE4A">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE4A</Default>

+            <Desc>HCI_VS_Set_Clk_Req_Mode_For_TCXO</Desc>

+        </Param>

+		<Param type="u" valtype="ClockSharingOutputMode_BT_IP" size="1">

+            <Name>Clock Sharing Output Mode</Name>

+            <Default>1</Default>

+            <Desc>0 - disable, 1 - enable</Desc>

+        </Param>

+		<Param type="u" valtype="EnableDisableDefaultNoChange" size="1">

+            <Name>Output pull enable</Name>

+            <Default>1</Default>

+            <Desc>0 - disable, 1 - enable, 2 - default pull, 0xFF - No change</Desc>

+        </Param>		

+		<Param type="u" valtype="ClkSharingPullConfiguration_BT_IP" size="1">

+            <Name>Pull configuration</Name>

+            <Default>0</Default>

+            <Desc>0-pull down; 1-pull up;</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+	<Command name="HCI_VS_WRITE_TCXO_LDO_ENABLE" type="sc" opcode="0xFE4B">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFE4B</Default>

+            <Desc>HCI_VS_Write_TCXO_LDO_Enable</Desc>

+        </Param>

+		<Param type="u" valtype="EnableDisable" size="1">

+            <Name>TCXO LDO state</Name>

+            <Default>0</Default>

+            <Desc>0-disable; 1-enable;</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+	<Command name="HCI_VS_Configure_AFH_debug" type="sc" opcode="0xfd62">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD62</Default>

+            <Desc>HCI_VS_Configure_AFH_debug</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>bit mask</Name>

+            <Default>0</Default>

+            <Desc>	

+            </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Table select</Name>

+            <Default>0xFF</Default>

+            <Desc>	

+                0 - print debug map 0

+                1 - print debug map 1

+                2 - print debug map 2

+                3 - print debug map 3

+            </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Channel to print</Name>

+            <Default>0xFF</Default>

+            <Desc> Channel for which grade and C2I will be printed (if bit in mask is high) </Desc>

+        </Param>

+        

+        <Param type="d" size="1">

+            <Name>Power 1</Name>

+            <Default>0</Default>

+            <Desc>	power 1 != 0 for loop to work [if(power1) {....}]

+                make sure bit 11 of debug mask is high (0x00000400) - to print logs of dBm_to_geortzel calc */

+            </Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>Power 2</Name>

+            <Default>0</Default>

+            <Desc>	power 1 must be larger than power 2, loop while (p1>=p2){... p1-=power step}

+            </Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>Power step</Name>

+            <Default>0</Default>

+            <Desc>	power step must be possitive , (step >0) uints in [db]

+            </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>PHY store enable</Name>

+            <Default>1</Default>

+            <Desc>When low, PHY does not store its results, they can be written through HCI script</Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>ref Power</Name>

+            <Default>-80</Default>

+            <Desc>	ref power for geortzel conversion (on Island 3 only)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>ref Goertzel</Name>

+            <Default>100</Default>

+            <Desc>ref geortzel for geortzel conversion (on Island 3 only)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_FM_BT_coex_configuration" type="sc" opcode="0xFD5D">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD5D</Default>

+            <Desc>HCI_VS_FM_BT_coex_configuration</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Coex enable bitmap</Name>

+            <Default>0x0000</Default>

+            <Desc>

+                Bit 0: report spur channels as bad in FM_RX

+                Bit 1: report spur channels as bad in FM_TX

+                Bit 2: AFH will be activated only in EDR

+                Bit 3: switch PLL mode (band)

+                Bit 4: switch OCP dividers

+                Bit 5: disable FM synt offset (ignore offset)

+                Bit 6: when in long sniff only, force basic data rate packets

+                Bit 8: enable/disable top/drp clock divison mechanism due to fm interference - disabled by default

+                Bit 15: enable debug messages for logger

+            </Desc>

+         </Param>

+        <Param type="u" size="1">

+            <Name>OCP - FREF frequency gaurdband</Name>

+            <Default>60</Default>

+            <Desc>frequency gaurdband from FM station to OCP spur (in KHz)</Desc>

+       </Param>

+        <Param type="u" size="1">

+            <Name>BT CKVD frequency gaurdband</Name>

+            <Default>200</Default>

+            <Desc>frequency gaurdband from FM station to CKVD spur (in KHz)</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Lock to AFH wait timer</Name>

+            <Default>1600</Default>

+            <Desc>time in slots to wait from FM station lock to removing channels by AFH</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCIPP_Set_Sniff_Scheduling_Params" type="sc" opcode="0xfd59">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD59</Default>

+            <Desc>Changes Sniff FBF Scheduling Parameters</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Sniff Instance Limit</Name>

+            <Default>10</Default>

+            <Desc>Number of frames to limit a sniff instance</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Sniff Voice Override Threshold</Name>

+            <Default>80</Default>

+            <Desc>Number of frames sniff could not schedule before overriding voice</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Sniff Timeout Limit</Name>

+            <Default>2</Default>

+            <Desc>Number of frames to limit a sniff timeout</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_BT_IP_Set_FM_Audio_Path" type="vc" opcode="0xFD65">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD65</Default>

+            <Desc>Controls the audio output pin mux and override pull registers</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>PCMI override</Name>

+            <Default>0</Default>

+            <Desc>The value of the PCMI_TOP_CTRL_REG. Zero indicated no change.</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>I2S override</Name>

+            <Default>0</Default>

+            <Desc>The value of the I2S_TOP_CTRL_REG. Zero indicated no change.</Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>Operation Mode</Name>

+            <Default>0</Default>

+            <Desc>FM audio path operation mode</Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>PCMI mux</Name>

+            <Default>0</Default>

+            <Desc>PCMI mux</Desc>

+        </Param>

+        

+        <Param type="u" size="1" valtype="EnableDisableNoChange">

+            <Name>PCMI Enable</Name>

+            <Default>0</Default>

+            <Desc>Enable disable the external PCM interface.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="EnableDisableNoChange">

+            <Name>I2S Enable</Name>

+            <Default>0</Default>

+            <Desc>Enable disable the external I2S interface.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Configure_Bad_Voice_Scenario_Params" type="sc" opcode="0xFD54">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD54</Default>

+            <Desc>HCI VS Configure Bad Voice Scenario Params</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>No voice override (by slave)period in bad voice scenario</Name>

+            <Default>400</Default>

+            <Desc>Number of Frames that there will be no override of voice in bad voice scenario</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Disable Voice Override Period</Name>

+            <Default>0x05</Default>

+            <Desc>The number of frames the slave will override voice for sending ACL data</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Multislot configuration in Bad Voice Scenario</Name>

+            <Default>0x02</Default>

+            <Desc>The length of slave data packets used to override voice: 0x0 - single slot, 0x1 - 3-slot packets, 0x2 - 5 slot packets</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0xFF</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0xFF</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0xFF</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_Configure_DDIP" type="sc" opcode="0xFD55">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD55</Default>

+            <Desc>Set Data During Inquiry Page Parameters</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>BE access percentage</Name>

+            <Default>20</Default>

+            <Desc>0-100: Percentage of Page or Inq to sucrifice for BE ACL</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Guaranteed access percentage</Name>

+            <Default>70</Default>

+            <Desc>0-100: Percentage of Page or Inq to sucrifice for guaranteed ACL</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Poll period</Name>

+            <Default>2</Default>

+            <Desc>Poll period to be requested by slave ACL during DDIP (0x02 - 0xFF)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Slave Wait After Tx Boundry</Name>

+            <Default>0x7</Default>

+            <Desc>A number of frames for ACK reception after the slave transmitted packet (0x02 - 0xFF) </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Slave Master Search Boundry </Name>

+            <Default>0x2</Default>

+            <Desc>The maximal number of frames in which the slave is searching for the master during DDIP (0x02 - 0xFF) </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Master Burst After Rx Enable</Name>

+            <Default>1</Default>

+            <Desc>Allows a following the Rx frame to be allocated to the same connection</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Master Burst After Rx Limit</Name>

+            <Default>1</Default>

+            <Desc>Limits a number of frames after Rx</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0xFF</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0xFF</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_QoS_Scheduler_Configuration" type="sc" opcode="0xfd56">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD56</Default>

+            <Desc>Configure conection frame by frame scheduling</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Poll Override Threshold</Name>

+            <Default>5</Default>

+            <Desc>The Minimum number of poll intervals needed before overriding voice</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Nulls Allocated for RX Data</Name>

+            <Default>1</Default>

+            <Desc>The number of NULL packets sent to peer after a data packet is received: 0-255.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Slave Search Timeout</Name>

+            <Default>40</Default>

+            <Desc>The maximum number of frames slave will wait for Poll/Null from master before giving up</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Slave Ack Timeout</Name>

+            <Default>7</Default>

+            <Desc>The maximum number of frames slave will wait for ACK after data transmission</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Master Burst After Rx Enable</Name>

+            <Default>1</Default>

+            <Desc>Master Burst After Rx Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Master Burst After Rx Limit</Name>

+            <Default>1</Default>

+            <Desc>Master Burst After Rx Limit</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Best Effort Percantage</Name>

+            <Default>15</Default>

+            <Desc>Best Effort Percantage that shall be provided to Connection</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Rwin_Override">

+            <Name>RWIN Override</Name>

+            <Default>1</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCIPP_SET_INQUIRY_VOICE_OVERRIDE" type="vc" opcode="0xFD70">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD70</Default>

+            <Desc>Configure voice override for inquiry incase of HV connections</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Frames</Name>

+            <Default>10</Default>

+            <Desc>Frames till override start</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Duration</Name>

+            <Default>5</Default>

+            <Desc>Duration (in frames) of override</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+	

+    <Command name="HCI_VS_DRP_Set_External_PA_Mode" type="sc" opcode="0xFD67">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD67</Default>

+            <Desc>Controls MUX and activation for Analog / Digital PA</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="PA_Mode">

+            <Name>PA Mode</Name>

+            <Default>0xFF</Default>

+            <Desc>0: Off, 1: DAC, 2: PWM, 3: Digital, 0xFF: Don't change.</Desc>

+        </Param>

+        

+        <Param type="u" size="1" valtype="External_PA_MODE_CMD_1_Select">

+            <Name>CMD 1 Select</Name>

+            <Default>0xFF</Default>

+            <Desc></Desc>

+        </Param>

+        

+        <Param type="u" size="1" valtype="External_PA_MODE_CMD_2_Select">

+            <Name>CMD 2 Select</Name>

+            <Default>0x01</Default>

+            <Desc></Desc>

+        </Param>

+        

+        <Param type="u" size="1" valtype="External_PA_MODE_PA_EN_Select">

+            <Name>PA_EN Select</Name>

+            <Default>0x02</Default>

+            <Desc></Desc>

+        </Param>

+        

+        <Param type="u" size="1" valtype="External_PA_MODE_nPA_EN_Select">

+            <Name>nPA_EN Select</Name>

+            <Default>3</Default>

+            <Desc></Desc>

+        </Param>

+        

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRPb_Enable_RF_Calibration" type="sc" opcode="0xFD80">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD80</Default>

+            <Desc>HCI VS DRPb Enable RF Calibration</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0x00: Calibrate once, 0x01-0xFD: Period length (x10 Secs), 0xFE: Keep periodic calibration, 0xFF: Stop periodic calibration.</Desc>

+        </Param>

+        <Param type="u" size="4" valtype="RF_Calibration_DRPb_Bitmap">

+            <Name>Calibration Procedures Selection</Name>

+            <Default>0xFFFFFFFF</Default>

+            <Desc>0x0000-0xFFFF: Procedures bitmap, 0xFFFFFFFF: Keep last bitmap.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Override_Temp">

+            <Name>Override Temp Condition</Name>

+            <Default>0x00</Default>

+            <Desc>0x00: Run selected calibrations only if temp range changed, 0x01: Run selected calibrations regardless of temp range changes</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRPb_Read_Calib_Results" type="sc" opcode="0xFD81">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD81</Default>

+            <Desc>HCI_VS_DRPb_Read_Calib_Results</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRPb_Set_Power_Vector" type="sc" opcode="0xFD82">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD82</Default>

+            <Desc>HCI VS DRPb Set Power Vector</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Modulation_Type">

+            <Name>Power Table Type</Name>

+            <Default>0x00</Default>

+            <Desc>0: GFSK, 1: EDR 2MB, 2: EDR 3MB, 3 - All modulation types, 4 - DIG_EXT_PA_CMD</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 0 Value</Name>

+            <Default>-50 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 1 Value</Name>

+            <Default>-18 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 2 Value</Name>

+            <Default>-18 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 3 Value</Name>

+            <Default>-18 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 4 Value</Name>

+            <Default>-18 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 5 Value</Name>

+            <Default>-18 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 6 Value</Name>

+            <Default>-18 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 7 Value</Name>

+            <Default>-18 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 8 Value</Name>

+            <Default>-18 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 9 Value</Name>

+            <Default>-14 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 10 Value</Name>

+            <Default>-10 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 11 Value</Name>

+            <Default>-6 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 12 Value</Name>

+            <Default>-2 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 13 Value</Name>

+            <Default>2 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 14 Value</Name>

+            <Default>6 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level 15 Value</Name>

+            <Default>10 *2</Default>

+            <Desc>-50 to 10 (dBm).</Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>tx_power_edr_epc_idx</Name>

+            <Default>0xFF</Default>

+            <Desc> epc max level Threshold 0 to 15 edr2(bits 0-3)edr3(bits 4-7) </Desc>

+        </Param>

+        <Param type="u" size="2" valtype="External_PA_Mode">

+            <Name>Externa PA Mode</Name>

+            <Default>0x00</Default>

+            <Desc></Desc>

+        </Param>

+        

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+  <Command name="HCI_VS_DRPb_Set_max_acw_power" type="sc" opcode="0xFD83">

+	  <Param type="o" size="2">

+	   <Name>Opcode</Name>

+	   <Default>0xFD83</Default>

+	   <Desc>This command allows us to define the max power </Desc>

+	  </Param>

+	  <Param type="u" size="2">

+	   <Name>MAX ACW Power 0</Name>

+	   <Default>12.5 *256</Default>

+	   <Desc>the max ACW power in dbm. for Temperature regions 0/1 

+       !!!! User must perform POWER_DEPENDENT_CALIBRATION at end of Init script if this command was used !!! </Desc>

+	  </Param>

+	  <Param type="u" size="2">

+	   <Name>MAX ACW Power 1</Name>

+	   <Default>12.5 *256</Default>

+	   <Desc>the max ACW power in dbm. for Temperature regions 2/3 </Desc>

+	  </Param>

+	  <Param type="u" size="2">

+	   <Name>MAX ACW Power 2</Name>

+	   <Default>12.5 *256</Default>

+	   <Desc>the max ACW power in dbm. for Temperature regions 4/5 </Desc>

+	  </Param>

+	  <Param type="u" size="2">

+	   <Name>MAX ACW Power 3</Name>

+	   <Default>12.5 *256</Default>

+	   <Desc>the max ACW power in dbm. for Temperature regions 6/7 </Desc>

+	  </Param>

+	  <Param type="u" size="2">

+	   <Name>MAX ACW Power 4</Name>

+	   <Default>12.5 *256</Default>

+	   <Desc>the max ACW power in dbm. for Temperature regions 8/9 </Desc>

+	  </Param>

+	  <Param type="u" size="2">

+	   <Name>MAX ACW Power 5</Name>

+	   <Default>12.5 *256</Default>

+	   <Desc>the max ACW power in dbm. for Temperature regions 10/11 </Desc>

+	  </Param>

+	  <Param type="R">

+		<Name>HCI_Command_Complete_Event</Name>

+		<Default />

+		<Desc />

+	  </Param>

+  </Command>

+ 

+     <Command name="HCI_VS_DRPb_Tester_Con_TX" type="sc" opcode="0xFD84">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD84</Default>

+            <Desc>Continuous Transmit Mode</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Con_TX_Modulation_Scheme">

+            <Name>Modulation Scheme</Name>

+            <Default>0</Default>

+            <Desc>Modulation Scheme</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Con_TX_Test_Pattern">

+            <Name>Test Pattern</Name>

+            <Default>0</Default>

+            <Desc>Test Pattern</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Frequency Index</Name>

+            <Default>0</Default>

+            <Desc>0..78: Freq</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Packet_TX_RX_Power_Level_Orca_Index">

+            <Name>Power level index</Name>

+            <Default>15</Default>

+            <Desc>Valid in BT, Range 0-15: 15=Max Output Power, 0=Min Output Power.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Generator Init Value</Name>

+            <Default>0x00000000</Default>

+            <Desc>0x00000000..0x00FFFFFF: Generator Init Value used in User Defined Pattern Only (for GFSK and EDR)</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>EDR Generator Mask Value</Name>

+            <Default>0x00000000</Default>

+            <Desc>0x00000000..0x00FFFFFF: EDR Generator Mask Value used in User Defined Pattern Only (for EDR only)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+	<Command name="HCI_VS_DRPb_Tester_Con_RX_Modulation" type="sc" opcode="0xFDB7">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDB7</Default>

+            <Desc>For BLE use this command with HCI_VS_DRPb_Tester_Con_RX, if this command is not used the default modulation is BT</Desc>

+          </Param>

+        <Param type="u" size="1">

+            <Name>Modulation type</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 - BT RX START, 0x01 - BLE RX START</Desc>

+        </Param>	

+         <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+	

+   <Command name="HCI_VS_DRPb_Tester_Con_RX" type="sc" opcode="0xFD17">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD17</Default>

+            <Desc>Continuous reception Mode</Desc>

+          </Param>

+        <Param type="u" size="1">

+            <Name>Frequency Index</Name>

+            <Default>0</Default>

+            <Desc>0..78: Freq</Desc>

+        </Param>

+          <Param type="u" size="1">

+            <Name>ADPLL loop mode</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 - Open loop, 0x01 - Closed loop</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRPb_Tester_Packet_TX_RX" type="sc" opcode="0xFD85">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD85</Default>

+            <Desc>Packet TX RX Mode</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Frequency_Mode">

+            <Name>Frequency Mode</Name>

+            <Default>3</Default>

+            <Desc>0 - Hopping, 3 - Single freq.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>TX Single Frequency Index</Name>

+            <Default>0</Default>

+            <Desc>0..78: Freq</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>RX Single Frequency Index</Name>

+            <Default>0xFF</Default>

+            <Desc>0..78: Freq, 0xFF: Disable RX</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Packet_TX_RX_Pkt_Type">

+            <Name>ACL TX Packet Type</Name>

+            <Default>0</Default>

+            <Desc>ACL TX Packet Type</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Packet_TX_RX_Pkt_Pattern">

+            <Name>ACL TX Packet Data Pattern</Name>

+            <Default>2</Default>

+            <Desc>ACL TX Packet Data Pattern</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="EnableDisable" label="extended_features">

+            <Name>Use Extended features</Name>

+            <Default>0</Default>

+            <Desc>Enable or disable the extended features of the command</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>ACL Packet Data Length</Name>

+            <Default>27</Default>

+            <Desc>0-17-&gt;DM1, 0-27-&gt;DH1, 0-121-&gt;DM3, 0-183-&gt;DH3, 0-224-&gt;DM5, 0-339-&gt;DH5</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="Packet_TX_RX_Power_Level_Orca_Index">

+            <Name>Power level index</Name>

+            <Default>15</Default>

+            <Desc>Range 0-15 : 15=Max Output Power, 0=Min Output Power.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Packet_TX_RX_Disable_Whitening">

+            <Name>Disable whitening</Name>

+            <Default>1</Default>

+            <Desc>0=Enable whitening, 1=Disable whitening</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>PRBS9 Init Value</Name>

+            <Default>0x01FF</Default>

+            <Desc>0x0000-0x01FF: PRBS9 Init Value</Desc>

+        </Param>

+		<Param cond="extended_features==1">

+			<Param type="u" size="2">

+				<Name>RX Win Length</Name>

+				<Default>200</Default>

+				<Desc>1-400-&gt;DH1, 1280-1600-&gt;DH3, 2500-2900-&gt;DH5</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>RX Packet Type</Name>

+				<Default>0</Default>

+				<Desc>0-1 slot, 1 - 3 slots, 2 - 5 slots</Desc>

+			</Param>        		

+			<Param type="u" size="1">

+				<Name>Burst Length</Name>

+				<Default>1</Default>

+				<Desc>1-0xFE Number of TX RX sequences, 0xFF - continuous</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>Burst Interval</Name>

+				<Default>2</Default>

+				<Desc>Burst length plus no action period - in frames </Desc>

+			</Param>

+				<Param type="u" size="1">

+				<Name>TX_RX Order</Name>

+				<Default>0</Default>

+				<Desc>0 : TX first(Master), 1: RX first(Slave) </Desc>

+			</Param>

+		</Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRPb_Debug_Mem_Setting" type="sc" opcode="0xFD86">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD86</Default>

+            <Desc>HCI_VS_DRPb_Debug_Mem_Setting</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRPb_Set_Class2_Single_Power" type="sc" opcode="0xFD87">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD87</Default>

+            <Desc>HCI_VS_DRPb_Set_Class2_Single_Power</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Packet_TX_RX_Power_Level_Orca_Index">

+            <Name>GFSK Power level index</Name>

+            <Default>10</Default>

+            <Desc>Table entry to use as class 2 if peer does not support power control.Range 0-15 : 15=Max Output Power, 0=Min Output Power.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Packet_TX_RX_Power_Level_Orca_Index">

+            <Name>EDR2 Power level index</Name>

+            <Default>10</Default>

+            <Desc>Table entry to use as class 2 if peer does not support power control.Range 0-15 : 15=Max Output Power, 0=Min Output Power.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Packet_TX_RX_Power_Level_Orca_Index">

+            <Name>EDR3 Power level index</Name>

+            <Default>10</Default>

+            <Desc>Table entry to use as class 2 if peer does not support power control.Range 0-15 : 15=Max Output Power, 0=Min Output Power.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRPb_Reset" type="sc" opcode="0xFD88">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD88</Default>

+            <Desc>HCI_VS_DRPb_Reset</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRPb_ADPLL_LF_Params" type="sc" opcode="0xFD89">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD89</Default>

+            <Desc>update ADPLL LF Params</Desc>

+        </Param>

+        <Param type="u" size="4" >

+            <Name>Frequency</Name>

+            <Default>19200000</Default>

+            <Desc>FREF clock being updated in Hz</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="ADPLL_LF_Set">

+            <Name>ADPLL LF Set</Name>

+            <Default>0</Default>

+            <Desc>The relevant set of LF parameters to be overridden. </Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Reserved</Name>

+            <Value>0</Value>

+        </Param>

+        <Param type="u" size="0" label="Alpha_Exp">

+            <Name>Alpha_Exp</Name>

+            <Default>0</Default>

+            <Desc>Alpha Exp value</Desc>

+        </Param>

+        <Param type="u" size="0" label="Alpha_Sig">

+            <Name>Alpha_Sig</Name>

+            <Default>0</Default>

+            <Desc>Alpha Sig value</Desc>

+        </Param>

+        <Param type="u" size="0" label="Rho_Exp">

+            <Name>Rho_Exp</Name>

+            <Default>0</Default>

+            <Desc>Rho Exp value</Desc>

+        </Param>

+        <Param type="u" size="0" label="Rho_Sig">

+            <Name>Rho_Sig</Name>

+            <Default>0</Default>

+            <Desc>Rho Sig value</Desc>

+        </Param>

+        <Param type="u" size="0" label="Gain_Exp">

+            <Name>Gain_Exp</Name>

+            <Default>0</Default>

+            <Desc>Gain Exp value</Desc>

+        </Param>

+        <Param type="u" size="0" label="Gain_Sig">

+            <Name>Gain_Sig</Name>

+            <Default>0</Default>

+            <Desc>Gain Sig value</Desc>

+        </Param>

+        <Param type="u" size="0" label="IIR_Lambda1">

+            <Name>IIR_Lambda1</Name>

+            <Default>0</Default>

+            <Desc>IIR_Lambda1 value</Desc>

+        </Param>

+        <Param type="u" size="0" label="IIR_Lambda2">

+            <Name>IIR_Lambda2</Name>

+            <Default>0</Default>

+            <Desc>IIR_Lambda2 value</Desc>

+        </Param>

+        

+        <Param type="u" size="2" prop="h">

+            <Name>pi_gain_low</Name>

+            <Value>Alpha_Exp+(Alpha_Sig*16)+(Rho_Exp*256)</Value>

+        </Param>

+        <Param type="u" size="2" prop="h">

+            <Name>pi_gain_high</Name>

+            <Value>Rho_Sig+(Gain_Exp*16)+(Gain_Sig*256)</Value>

+        </Param>

+        <Param type="u" size="2" prop="h">

+            <Name>iir</Name>

+            <Value>IIR_Lambda2+(IIR_Lambda1*256)</Value>

+        </Param>

+        

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRPb_Run_Mnem" type="sc" opcode="0xFD8A">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD8A</Default>

+            <Desc>Drp Run Mnem (2,1V)</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Test Period</Name>

+            <Default>0</Default>

+            <Desc>Test Period</Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="u" size="3">

+            <Name>Count Threshold</Name>

+            <Default>0</Default>

+            <Desc>Count Threshold</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Exception Counter</Name>

+            <Default>0</Default>

+            <Desc>Exception Counter Fail-Pass limit</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Decimation Mode</Name>

+            <Default>0</Default>

+            <Desc>Decimation Mode</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Wait Time</Name>

+            <Default>200</Default>

+            <Desc>0-255 ms</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Test Cont Flag</Name>

+            <Default>0</Default>

+            <Desc>0-dont run VS_DRP_Tester_Continous_TX , 1- run VS_DRP_Tester_Continous_TX</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - success, Other - Error</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Status Register Value</Name>

+            <Default>0x0000</Default>

+            <Desc>Status Register Value</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRPb_BER_Meter_Start" type="sc" opcode="0xFD8B">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD8B</Default>

+            <Desc>HCIPP Start DRP BER Meter</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Frequency Channel</Name>

+            <Default>59</Default>

+            <Desc>Frequency Channel</Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="u" size="6">

+            <Name>BD Address</Name>

+            <Default>0x000000000000</Default>

+            <Desc>BD Address</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>LT Address</Name>

+            <Default>1</Default>

+            <Desc>LT Address</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="DrpBerMeterPktType">

+            <Name>ACL Packet Type</Name>

+            <Default>0x1</Default>

+            <Desc>ACL Packet Type</Desc>

+        </Param>

+        <Param type="u" size="2" >

+            <Name>packet length</Name>

+            <Default>27</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="2" >

+            <Name>Number of packets</Name>

+            <Default>500</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="2" >

+            <Name>PRBS Initilaize</Name>

+            <Default>0x1FF</Default>

+            <Desc>PRBS Init state</Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>POLL Period</Name>

+            <Default>0x1</Default>

+            <Desc>In BT frames</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRP_Read_BER_Meter_Result" type="sc" opcode="0xFD13">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD13</Default>

+            <Desc>HCIPP Read DRP BER Meter Result</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>0 - success, 1 - illegal command</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Finished at least 1 test</Name>

+            <Default>0x00</Default>

+            <Desc>0 - First test has not been finished, 1 - Values are valid for current measurment</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Number of packet received in current measurment</Name>

+            <Default>0x00</Default>

+            <Desc>Number of packet received in current measurment</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Total bits counted </Name>

+            <Default>0x00</Default>

+            <Desc>Total bits counted </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of bits error found</Name>

+            <Default>0x00</Default>

+            <Desc></Desc>

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="HCI VS Commands in BTIP PG 2.1" type="gb" />

+    <!-- ================================================================== -->

+

+

+<Command name="HCI_VS_DRPB_Force_Environment_Settings" type="sc" opcode="0xFD98">

+	  <Param type="o" size="2">

+	   <Name>Opcode</Name>

+	   <Default>0xFD98</Default>

+	   <Desc>HCI VS DRPB Force Environment Settings</Desc>

+	  </Param>

+	  <Param type="u" size="1" >

+	   <Name>Set Process Type</Name>

+	   <Default>0xFF</Default>

+	   <Desc>0x00: Nominal, 0x01: Weak, 0x02: Strong, 0xFF: Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1" >

+	   <Name>Set Temperature Value</Name>

+	   <Default>0x7F</Default>

+	   <Desc>-40 to 85: Temperature Value in Celsius (C) , 0x7E: Default, 0x7F: Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 00 Threshold</Name>

+	   <Default>-70</Default>

+	   <Desc>-127 - +127:Temperature Region 00 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 01 Threshold</Name>

+	   <Default>-30</Default>

+	   <Desc>-127 - +127:Temperature Region 01 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 02 Threshold</Name>

+	   <Default>-20</Default>

+	   <Desc>-127 - +127:Temperature Region 02 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 03 Threshold</Name>

+	   <Default>-10</Default>

+	   <Desc>-127 - +127:Temperature Region 03 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 04 Threshold</Name>

+	   <Default>0</Default>

+	   <Desc>-127 - +127:Temperature Region 04 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 05 Threshold</Name>

+	   <Default>10</Default>

+	   <Desc>-127 - +127:Temperature Region 05 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 06 Threshold</Name>

+	   <Default>20</Default>

+	   <Desc>-127 - +127:Temperature Region 06 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 07 Threshold</Name>

+	   <Default>30</Default>

+	   <Desc>-127 - +127:Temperature Region 07 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 08 Threshold</Name>

+	   <Default>40</Default>

+	   <Desc>-127 - +127:Temperature Region 08 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 09 Threshold</Name>

+	   <Default>50</Default>

+	   <Desc>-127 - +127:Temperature Region 09 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 10 Threshold</Name>

+	   <Default>60</Default>

+	   <Desc>-127 - +127:Temperature Region 10 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 11 Threshold</Name>

+	   <Default>70</Default>

+	   <Desc>-127 - +127:Temperature Region 11 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="u" size="1">

+	   <Name>Temperature Region 12 Threshold</Name>

+	   <Default>125</Default>

+	   <Desc>-127 - +127:Temperature Region 12 Threshold, 0x80(-128):Don't change.</Desc>

+	  </Param>

+	  <Param type="R">

+	   <Name>HCI_Command_Complete_Event</Name>

+	   <Default />

+	   <Desc />

+	  </Param>

+	</Command>

+

+<Command name="HCI_VS_A3DP_Open_Stream" type="sc" opcode="0xFD8C">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD8C</Default>

+   <Desc>HCI_VS_A3DP_OPEN_STREAM</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Connection Handle</Name>

+   <Default>0x01</Default>

+   <Desc>The ACL connection handle</Desc>

+  </Param>

+  <Param type="u" size="2">

+   <Name>L2CAP CID</Name>

+   <Default>0x40</Default>

+   <Desc>L2CAP channel ID of the AVDTP data stream</Desc>

+  </Param>

+  <Param type="u" size="2">

+   <Name>L2CAP MTU</Name>

+   <Default>0x300</Default>

+   <Desc>L2CAP max packet length</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>AVDTP Version Parameter</Name>

+   <Default>0x02</Default>

+   <Desc>AVDTP protocol header Version parameter</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>AVDTP Payload Parameter</Name>

+   <Default>0x65</Default>

+   <Desc>AVDTP protocol header Payload parameter</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+   <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+ </Command>

+

+<Command name="HCI_VS_A3DP_Close_Stream" type="sc" opcode="0xFD8D">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD8D</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Connection Handle </Name>

+   <Default>0x01</Default>

+   <Desc>The ACL connection handle. The value 0x0 means close all streams </Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_A3DP_Codec_Configuration" type="sc" opcode="0xFD8E">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD8E</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_audio_source">

+   <Name>Audio Source</Name>

+   <Default>0x00</Default>

+   <Desc>Determines the audio source of the A2DP stream. </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_PCM_input_sample_freq">

+   <Name>PCM Input Sample Frequency</Name>

+   <Default>0x9</Default>

+   <Desc> The PCM sample frequency rate of the input PCM bus.

+When this parameter is different from the SBC Input Sample Frequency  the SRC will be used for sample rate conversion. </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_PCM_num_channels">

+   <Name>PCM Number of Channels</Name>

+   <Default>0x2</Default>

+   <Desc> The number of channels of the PCM input. </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_SBC_input_freq">

+   <Name>SBC Input Sample Frequency</Name>

+   <Default>0x4</Default>

+   <Desc> The sample frequency rate of the PCM input to SBC encoder </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_SBC_channel_mode">

+   <Name>SBC channel Mode</Name>

+   <Default>0x2</Default>

+   <Desc> Describes the channel mode used to encode a stream. </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>SBC Number of Blocks</Name>

+   <Default>16</Default>

+   <Desc> Number of SBC Encoder Blocks (4,8,12,16) </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>SBC Number of Subbands</Name>

+   <Default>8</Default>

+   <Desc>Number of SBC Encoder subbands (4,8) Currently only 8 is supported</Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_SBC_allocation_method">

+   <Name>SBC Allocation Method</Name>

+   <Default>0</Default>

+   <Desc>SBC Allocation Method </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>SBC Bit Pool Low Boundary </Name>

+   <Default>35</Default>

+   <Desc>The lower boundary of the negotiated bit pool range</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>SBC Recommended Bit pull</Name>

+   <Default>53</Default>

+   <Desc>The Host can recommend for a specific bit pool value from the bit pool rate. </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_dynamic_bit_pool_enable">

+   <Name>SBC dynamic Bit Pull Enable</Name>

+   <Default>0</Default>

+   <Desc>Determines whether a dynamic bit pool mechanism should be used to performance/quality adjustment</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+   <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_A3DP_Multiple_SNK_Configuration" type="sc" opcode="0xFD96">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD96</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>SBC Bit Pool Low Boundary </Name>

+   <Default>15</Default>

+   <Desc>The lower boundary of negotiated bit pool range (max of both SNK low boundary) </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>SBC Recommended Bit pull</Name>

+   <Default>53</Default>

+   <Desc>The recommended bit pool of both SNK </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_dynamic_bit_pool_enable">

+   <Name>SBC multiple SNK dynamic Bit Pull Enable</Name>

+   <Default>1</Default>

+   <Desc>Determines whether a dynamic bit pool mechanism should be used during multiple SNK scenario</Desc>

+   </Param>

+  <Param type="u" size="5">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_A3DP_Start_Stream" type="sc" opcode="0xFD8F">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD8F</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Connection Handle </Name>

+   <Default>0x01</Default>

+   <Desc>The ACL connection handle</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_A3DP_Stop_Stream" type="sc" opcode="0xFD90">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD90</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Connection Handle </Name>

+   <Default>0x01</Default>

+   <Desc>The ACL connection handle. The value 0x0 means stop all streams </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_flush_flag">

+   <Name>Flush  Flag</Name>

+   <Default>0x01</Default>

+   <Desc>Determines whether the current internal buffers should be transmitted to the remotes device(s), or should be flushed immediately. </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_generate_event">

+   <Name>Generate Stop Event</Name>

+   <Default>0x00</Default>

+   <Desc>Determines whether a stop stream event will be generated as soon as stream is stopped. To be used in Soft Flush </Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_A3DP_Stop_Stream_Event" type="ve" opcode="0x0300">

+  <Param type="t">

+   <Name>Timeout</Name>

+   <Default>10000</Default>

+   <Desc>Timeout in msec</Desc>

+  </Param>

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0x0300</Default>

+   <Desc>GAP</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Handle</Name>

+   <Default>0x01</Default>

+   <Desc>Opcode</Desc>

+  </Param>

+ </Command>

+

+<Command name="HCI_VS_AVPR_Debug" type="sc" opcode="0xFD91">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD91</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Debug IPC Logger </Name>

+   <Default>0x01</Default>

+   <Desc>Enable/Disable IPC logger messages. 1 - Enable. 0 - Disable </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Reserved</Name>

+   <Default>0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>A3DP IO</Name>

+   <Default>0x01</Default>

+   <Desc>Enable/Disable A3DP IOs. 1 - Enable. 0 - Disable </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Reserved</Name>

+   <Default>0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Reservede</Name>

+   <Default>0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+

+

+  <Param type="R">

+	<Name>HCI_Command_Complete_Event</Name>

+	<Default />

+	<Desc />

+   </Param>

+</Command>

+

+<Command name="HCI_VS_A3DP_Dynamic_Bit_Pool_Config" type="sc" opcode="0xFD99">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD99</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="2">

+   <Name>Decrease Start Threshold</Name>

+   <Default>850</Default>

+   <Desc>Used to calculate the IPC buffer occupation amount, above which bit pool decrease starts</Desc>

+  </Param>

+  <Param type="u" size="2" >

+   <Name>Decrease Start Threshold Multi</Name>

+   <Default>1000</Default>

+   <Desc>Used to calculate the IPC buffer occupation amount, above which bit pool decrease starts in multiple SNK scenario </Desc>

+  </Param>

+  <Param type="u" size="2">

+   <Name>Increase Start Threshold</Name>

+   <Default>600</Default>

+   <Desc>Used to calculate the IPC buffer occupation amount, above which bit pool increase starts</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Increase Rate</Name>

+   <Default>50</Default>

+   <Desc>Defines how many encoding cycles passes between one bit pool increase to another</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Increase Interations Boundary </Name>

+   <Default>2</Default>

+   <Desc>Defines the number of iterations above which the factor for slowing the decrease rate is NOT increased for every decrease/ increase loop</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Decrease Clear Interations Boundary</Name>

+   <Default>4</Default>

+   <Desc>Defines the number of iterations above which the decrease rate becomes very fast</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>First Decrease</Name>

+   <Default>6</Default>

+   <Desc>Defines the amount of bit pool unites which are decreased in the first decreasing cycle</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Rate Factor</Name>

+   <Default>50</Default>

+   <Desc>The rate of the dynamic bit pool determise how frequent (in terms of packet calc cycles)

+will bit pool decrease be. If the rate is 1 - every calc cycle a decrease will occur

+This variable is a factor in the rate calculation</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Decrease Factor</Name>

+   <Default>2</Default>

+   <Desc>Each time bit pool is lowered the decrease amount is calculated. The number of times the bit pool

+was swinging up and down slows that decrease amount, in order to stabilize the bit pool on the 

+channel's current bandwidth. The following variable is a factor in the decrease amount calculation

+</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Halt Value</Name>

+   <Default>37</Default>

+   <Desc>Determines the value of the bit pool during halt</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Bad RF Value</Name>

+   <Default>37</Default>

+   <Desc>Determines the value of the bit pool during bad RF</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Nack Threshold</Name>

+   <Default>20</Default>

+   <Desc>Determines the threshold above which the channel is considered 'bad rf' channel for

+the dynamic bit pool mechanism</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Nack Threshold Multi</Name>

+   <Default>10</Default>

+   <Desc>Determines the threshold above which the channel is considered 'bad rf' channel for

+the dynamic bit pool mechanism in multiple SNK </Desc>

+  </Param>

+  <Param type="u" size="2">

+   <Name>RF statistics period</Name>

+   <Default>400</Default>

+   <Desc>Determines the RF statistics period</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+    

+<Command name="HCI_VS_Configure_page_scan_response" type="sc" opcode="0xFD6C">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD6C</Default>

+            <Desc>Configure page scan response that will be used when a connection attempt with the same Bluetooth address of an existing connection is made</Desc>

+        </Param>

+        <Param type="u" size="2" >

+            <Name>page scan behavior</Name>

+            <Default>0</Default>

+            <Desc>0 - allow new connection attempt and disconnect existing connection, 1 - reject new connection whilst existing connection remains present</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+<Command name="HCI_VS_Set_esco_retransmission_windows_policy" type="sc" opcode="0xFD6D">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD6D</Default>

+            <Desc>configure the retransmission windows in diffrent Retransmission Effort mode</Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>power consumption</Name>

+            <Default>1</Default>

+            <Desc>Number of retransmission windows in power consumption mode.(Retransmission_Effort = 1)</Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>link quality</Name>

+            <Default>2</Default>

+            <Desc>Number of retransmission windows in link quality mode.(Retransmission_Effort = 2)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+<Command name="HCI_VS_Configure_ACL_Data_Buffers" type="sc" opcode="0xFD7C">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD7C</Default>

+            <Desc>configure the number and length of ACL data buffers</Desc>

+        </Param>

+        <Param type="u" size="2" >

+            <Name>Buffer length</Name>

+            <Default>1021</Default>

+            <Desc></Desc>

+        </Param>

+         <Param type="u" size="4" >

+            <Name>reserved</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0</Default>

+            <Desc>0 - Success, 1 - Illegal command</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Number of ACL buffers</Name>

+            <Default>0</Default>

+            <Desc>X</Desc>

+        </Param>

+    </Command>

+

+<Command name="HCI_VS_Configure_Extended_ACL_Data_Buffers" type="sc" opcode="0xFD7D">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD7D</Default>

+            <Desc>configure the number and length of Extended ACL data buffers</Desc>

+        </Param>

+        <Param type="u" size="2" >

+            <Name>Buffer length</Name>

+            <Default>1021</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>acl data threshold</Name>

+            <Default>1</Default>

+            <Desc>Threshold for acl flow control</Desc>

+        </Param>

+        <Param type="u" size="2" >

+            <Name>acl data timeout</Name>

+            <Default>800</Default>

+            <Desc>HCID timer period</Desc>

+        </Param>

+        <Param type="u" size="4" >

+            <Name>cortex_owner</Name>

+            <Default>0</Default>

+            <Desc>0 - Wibree [Default]; 1 - None; 2 - AVPR</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0</Default>

+            <Desc>0 - Success, 1 - Illegal command</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Number of ACL buffers</Name>

+            <Default>0</Default>

+            <Desc>X</Desc>

+        </Param>

+    </Command>

+

+<Command name="HCI_VS_Class_1p5_LDO_mode" type="sc" opcode="0xFD6E">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD6E</Default>

+            <Desc>This command configures the Class 1p5 mode </Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>Mode</Name>

+            <Default>0xFF</Default>

+            <Desc>0 - Direct Battery Input, 1 - SMPS High power Mode, , 2 - SMPS Low power Mode, 0xFF - Don't change </Desc>

+        </Param>

+        <Param type="u" size="1" >

+            <Name>Class 1.5 LDO trim</Name>

+            <Default>0xFF</Default>

+            <Desc>Control word for Class 1.5 Vout 0x0 - low 0xf = high (4 bit), 0xFF - Don't change</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+<Command name="HCI_VS_Configure_Debug_Message_Over_HCI" type="sc" opcode="0xFD7E">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD7E</Default>

+            <Desc>Configure debug messages over HCI

+            Not supported under Palau mode

+            Execute after setting Uart HCI Baudrate and not before it</Desc>

+        </Param>

+        <Param type="u" size="2" >

+            <Name>Mode</Name>

+            <Default>1</Default>

+            <Desc>0 - Disable mode, 1 - Enable mode

+            Not supported under Palau mode

+            Execute after setting Uart HCI Baudrate and not before it.</Desc>

+        </Param>

+        <Param type="u" size="2" >

+            <Name>Timeout</Name>

+            <Default>80</Default>

+            <Desc>time in BT Frames - 

+                dispatch messages in case this time elapsed from last sent</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+   <Command name="HCI_VS_Set_eSCO_Retransmission_Priority_Policy" type="sc" opcode="0xFFD0">

+        <Param type="u" size="1" >

+            <Name>Mode</Name>

+            <Default>1</Default>

+            <Desc>0 - Disabled, 1 - Signal Priority on possible eSCO RWIN, 2 - Signal Priority only on Master when slave bad HEC</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+   <Command name="HCI_VS_Get_Random_Seed" type="sc" opcode="0xFFD1">

+        <Param type="u" size="2" >

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+	<Command name="HCI_VS_GPS_POWER_MODE" type="vc" opcode="0xFFC0">

+		<Cat>GPS</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFFC0</Default>

+			<Desc>Power GPS On / Off</Desc>

+		</Param>

+		<Param type="u" size="1" valtype="GPS_POWER_MODES">

+			<Name>Power mode</Name>

+			<Default>0</Default>

+		</Param>

+		<Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+	</Command>

+

+<!-- =========================================================================================== -->

+	<Command name="HCI VS Commands in Wilink 7" type="gb" />

+<!-- =========================================================================================== -->

+	<Command name="HCI_VS_PLL_Sharing_Enable" type="vc" opcode="0xFD71">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD71</Default>

+            <Desc>Configure pll sharing parameters</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="PLL_Sharing_Scheme_Mode">

+            <Name>PLL Sharing Scheme Mode</Name>

+            <Default>1</Default>

+            <Desc>Determine the PLL sharing scheme mode.</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>GPS requires HP</Name>

+            <Default>0</Default>

+            <Desc>Configure whether GPS requires hp or not</Desc>

+        </Param>

+		<Param type="u" size="8" >

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+	

+	<Command name="HCI_VS_QUATTRO_DC2DC_Configuration" type="vc" opcode="0xFD72">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD72</Default>

+            <Desc>Configure DC2DC parameters</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="External_dc2dc_Mode">

+            <Name>External dc2dc</Name>

+            <Default>0xFF</Default>

+            <Desc>Determine External DC2DC mode</Desc>

+        </Param>

+		<Param type="u" size="1">

+            <Name>Internal dc2dc</Name>

+            <Default>0</Default>

+            <Desc>Determine Internal DC2DC mode</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>DC2DC clock priority</Name>

+            <Default>0</Default>

+            <Desc>Determine DC2DC clock priority. Values: 0-0xFFF</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="DC2DC_input_frequency">

+            <Name>Source input frequency</Name>

+            <Default>0xFF</Default>

+            <Desc>Determine DC2DC clock priority.</Desc>

+        </Param>		

+		<Param type="u" size="2">

+            <Name>Required Output Frequency</Name>

+            <Default>0xffff</Default>

+            <Desc>0x0000-0xfffd :Required frequency in KHz\n

+			0xfffe: Use value from DC2DC_BANK_X_GENERAL , DC2DC_BANK_X_TOGGLE_1, DC2DC_BANK_X_TOGGLE_2\n

+			0xffff: Don't change</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>DC2DC bank X general</Name>

+            <Default>0xffff</Default>

+            <Desc>Override to the relevant register</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>DC2DC bank X toggle 1</Name>

+            <Default>0xffff</Default>

+            <Desc>Override to the relevant register</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>DC2DC bank X toggle 2</Name>

+            <Default>0xffff</Default>

+            <Desc>Override to the relevant register</Desc>

+        </Param>

+		<Param type="u" size="1">

+            <Name>Standalone DC2DC output voltage trim</Name>

+            <Default>0xff</Default>

+            <Desc>Override to the relevant register. 0xFFFF for don't change</Desc>

+        </Param>

+		<Param type="u" size="8">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>		

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+	<Command name="HCI_VS_Quattro_Power_Save_Features" type="vc" opcode="0xFD73">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD73</Default>

+            <Desc>Enable/Disable Quattro power save features</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="EnableDisableNoChange">

+            <Name>Dig LDO 1v at room temp</Name>

+            <Default>0xFF</Default>

+            <Desc>Enable/disable Dig LDO 1v at room temp</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="EnableDisableNoChange">

+            <Name>Standalone features</Name>

+            <Default>0xFF</Default>

+            <Desc>Enable/disable Global standalone</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="EnableDisableNoChange">

+            <Name>LP Bypass PLL Standalone</Name>

+            <Default>0xFF</Default>

+            <Desc>Enable/disable LP Standalone sequence</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="EnableDisableNoChange">

+            <Name>dc2dc pwm frequncy standalone</Name>

+            <Default>0xFF</Default>

+            <Desc>Enable/disable dc2dc pwm frequncy standalone</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="EnableDisableNoChange">

+            <Name>dc2dc vtrim standalone</Name>

+            <Default>0xFF</Default>

+            <Desc>Enable/disable dc2dc vtrim standalone</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="EnableDisableNoChange">

+            <Name>BT ref clock blocking standalone</Name>

+            <Default>0xFF</Default>

+            <Desc>Enable/disable BT ref clock blocking</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="EnableDisableNoChange">

+            <Name>Coex Pll Clock Blocking Standalone</Name>

+            <Default>0xFF</Default>

+            <Desc>Enable/disable Coex Pll Clock Blocking Standalone</Desc>

+        </Param>

+	<Param type="u" size="1" valtype="EnableDisableNoChange">

+            <Name>Slicer Itrim Override</Name>

+            <Default>0xFF</Default>

+            <Desc>Enable/Disable Slicer Itrim Override</Desc>

+        </Param>		

+		<Param type="u" size="8">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+	

+	<Command name="HCI_VS_JTAG_Enable" type="vc" opcode="0xFD74">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD74</Default>

+            <Desc>Enable/Disable JTAG for Quattro</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>WU source enable</Name>

+            <Default>0</Default>

+            <Desc>Enable or disable JTAG as a wakeup source</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="JTAG_Enable_RTCK_Muxing">

+            <Name>RTCK muxing</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+		<Param type="u" size="4" >

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+	

+	<Command name="HCI_VS_GPS_Standalone_Config" type="vc" opcode="0xFD75">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD75</Default>

+            <Desc>Enable/disable GPS standalone mode</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>Standalone mode</Name>

+            <Default>0</Default>

+            <Desc>Enable/disable GPS standalone mode</Desc>

+        </Param>        

+		<Param type="u" size="4" >

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_DRPb_Set_RF_Calibration_Info" type="sc" opcode="0xFD76">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFD76</Default>

+            <Desc>HCI VS DRPb set RF calibration info</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Split Mode</Name>

+            <Default>0x01</Default>

+            <Desc>0x00: Disable, 0x01: Enable</Desc>

+        </Param>

+        <Param type="u" size="4" valtype="RF_Calibration_DRPb_Bitmap">

+            <Name>Calibrations with PA/LNA</Name>

+            <Default>0x00005421</Default>

+            <Desc>Checked box = use PA/LNA, Unchecked box = don't use PA/LNA; 0x0000-0xFFFF: PA/LNA bitmap, 0xFFFFFFFF: Keep last bitmap.</Desc>

+        </Param>

+        <Param type="u" size="4" valtype="RF_Calibration_DRPb_Bitmap">

+            <Name>Calibrations with protection</Name>

+            <Default>0x00005761</Default>

+            <Desc>Checked box = protected, Unchecked box = unprotected; 0x0000-0xFFFF: Protection bitmap, 0xFFFFFFFF: Keep last bitmap.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>PA_SD delay_ms</Name>

+            <Default>20</Default>

+            <Desc>Trigger same calibration in [x] ms in case of non successive attempt due to PA_SD</Desc>

+		</Param>

+		<Param type="u" size="1">

+            <Name>Num of calib PA_SD attempts</Name>

+            <Default>5</Default>

+            <Desc>Maximum number of additional non successive attempts due to WLAN PA_SD during calibration process</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Interference delay_ms</Name>

+            <Default>10</Default>

+            <Desc>Trigger same calibration in [x] ms in case of non successive attempt due to general interference</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Num of calib interf attempts</Name>

+            <Default>5</Default>

+            <Desc>Maximum number of additional non successive attempts due to general interference during calibration process</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #1</Name>

+            <Default>00</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #2</Name>

+            <Default>07</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #3</Name>

+            <Default>06</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #4</Name>

+            <Default>10</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #5</Name>

+            <Default>04</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #6</Name>

+            <Default>05</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #7</Name>

+            <Default>08</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #8</Name>

+            <Default>09</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #9</Name>

+            <Default>11</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #10</Name>

+            <Default>12</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #11</Name>

+            <Default>13</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #12</Name>

+            <Default>14</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #13</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #14</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #15</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #16</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #17</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #18</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #19</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #20</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #21</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #22</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #23</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #24</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #25</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #26</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #27</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #28</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #29</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #30</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #31</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="RF_Calibrations">

+            <Name>Calibration #32</Name>

+            <Default>16</Default>

+            <Desc>Calibrations order</Desc>

+        </Param>

+		<Param type="u" size="4" >

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+	<Command name="HCI_VS_Auto_Recovery_State_Change" type="ve" opcode="0x1700">

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0x1700</Default>

+			<Desc>Auto recovery status change event</Desc>

+		</Param>

+        <Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default></Default>

+            <Desc>BD address for which the recovery is being processed</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="Auto_Recovery_States">

+            <Name>State</Name>

+            <Default>0</Default>

+            <Desc>Auto recovery state</Desc>

+        </Param>

+		<Param type="u" size="1" valtype="Auto_Recovery_Roles">

+            <Name>Role</Name>

+            <Default>0</Default>

+            <Desc>Auto recovery Role: Pager or scanner</Desc>

+        </Param>

+    </Command>

+	

+	<Command name="HCI_VS_Auto_Recovery_Parameter_Request" type="vc" opcode="0xFDAA">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDAA</Default>

+            <Desc>Request Parameters for an Auto recovery session</Desc>

+        </Param>

+	<Param type="u" size="2">

+            <Name>connection handle</Name>

+            <Default>1</Default>

+            <Desc>Connection handle to request parameters for</Desc>

+        </Param>

+		<Param type="u" size="8">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+		 <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0</Default>

+            <Desc>0 - Success, 1 - Illegal command</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>connection handle</Name>

+            <Default>1</Default>

+            <Desc>Connection handle to enable auto recovery on</Desc>

+        </Param>

+		<Param type="u" size="4">

+            <Name>Start Value</Name>

+            <Default>0x0</Default>

+            <Desc>BT CLK to act as a reference point for anchor points</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>Anchor Interval</Name>

+            <Default>0x400</Default>

+            <Desc>Interval between two recovery anchor points</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>Fast Timeout</Name>

+            <Default>1800</Default>

+            <Desc>Fast recovery timeout (In seconds)</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>Slow Timeout</Name>

+            <Default>48000</Default>

+            <Desc>Fast recovery timeout (In seconds)</Desc>

+        </Param>		

+    </Command>

+

+	

+	<Command name="HCI_VS_Auto_Recovery_Enable" type="vc" opcode="0xFDAC">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDAC</Default>

+            <Desc>Enable auto recovery on link</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>connection handle</Name>

+            <Default>1</Default>

+            <Desc>Connection handle to enable auto recovery on</Desc>

+        </Param>

+		<Param type="u" size="4">

+            <Name>Start Value</Name>

+            <Default>0x0</Default>

+            <Desc>BT CLK to act as a reference point for anchor points</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>Anchor Interval</Name>

+            <Default>0x400</Default>

+            <Desc>Interval between two recovery anchor points</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>Fast Timeout</Name>

+            <Default>1800</Default>

+            <Desc>Fast recovery timeout (In seconds)</Desc>

+        </Param>

+		<Param type="u" size="2">

+            <Name>Slow Timeout</Name>

+            <Default>48000</Default>

+            <Desc>Fast recovery timeout (In seconds)</Desc>

+        </Param>

+		<Param type="u" size="8">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+	

+	<Command name="HCI_VS_Auto_Recovery_Disable" type="vc" opcode="0xFDAD">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDAD</Default>

+            <Desc>Disable auto recovery on link</Desc>

+        </Param>

+		<Param type="b" size="6">

+            <Name>BD Address</Name>

+            <Default>bd_addr</Default>

+            <Desc>BD Address to disable auto recovery on</Desc>

+        </Param>

+		<Param type="u" size="8">

+            <Name>Reserved</Name>

+            <Default>0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+  

+  

+  

+  

+  <!-- =========================================================================================== -->

+    <Command name="HCI VS Commands in BTIP PG 3.0" type="gb" />

+  <!-- =========================================================================================== -->

+  

+<Command name="HCI_VS_A3DP_Sink_Open_Stream" type="sc" opcode="0xFD9A">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD9A</Default>

+   <Desc>HCI_VS_A3DP_SNK_OPEN_STREAM</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Connection Handle</Name>

+   <Default>0x01</Default>

+   <Desc>The ACL connection handle</Desc>

+  </Param>

+  <Param type="u" size="2">

+   <Name>L2CAP CID</Name>

+   <Default>0x40</Default>

+   <Desc>L2CAP channel ID of the AVDTP data stream</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+   <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+ </Command>

+

+<Command name="HCI_VS_A3DP_Sink_Close_Stream" type="sc" opcode="0xFD9B">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD9B</Default>

+   <Desc>HCI_VS_A3DP_SNK_CLOSE_STREAM </Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_A3DP_Sink_Codec_Configuration" type="sc" opcode="0xFD9C">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD9C</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_PCM_num_channels">

+   <Name>PCM Number of Channels</Name>

+   <Default>0x2</Default>

+   <Desc> The number of channels of the PCM input. </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_SBC_input_freq">

+   <Name>SBC Input Sample Frequency</Name>

+   <Default>0x3</Default>

+   <Desc> The sample frequency rate of the PCM input to SBC encoder </Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_SBC_channel_mode">

+   <Name>SBC channel Mode</Name>

+   <Default>0x2</Default>

+   <Desc> Describes the channel mode used to encode a stream. </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>SBC Number of Blocks</Name>

+   <Default>16</Default>

+   <Desc> Number of SBC Encoder Blocks (4,8,12,16) </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>SBC Number of Subbands</Name>

+   <Default>8</Default>

+   <Desc>Number of SBC Encoder subbands (4,8) Currently only 8 is supported</Desc>

+  </Param>

+  <Param type="u" size="1" valtype="a3dp_SBC_allocation_method">

+   <Name>SBC Allocation Method</Name>

+   <Default>0</Default>

+   <Desc>SBC Allocation Method </Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+   <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_A3DP_Sink_Start_Stream" type="sc" opcode="0xFD9D">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD9D</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_A3DP_Sink_Stop_Stream" type="sc" opcode="0xFD9E">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD9E</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_AVPR_Enable" type="sc" opcode="0xFD92">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD92</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Enable/Disable AVPR </Name>

+   <Default>0x01</Default>

+   <Desc>Enable/Disable The AVPR clock. Enable also reloads the AVPR code.

+1 - Enable. 0 - Disable </Desc>

+   </Param>

+  <Param type="u" size="1" valtype="a3dp_role">

+   <Name>A3DP role</Name>

+   <Default>0x00</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Code upload</Name>

+   <Default>0x01</Default>

+   <Desc>0x00 - Don't load A3DP code,0x01- Load A3DP code </Desc>

+  </Param>  

+  <Param type="u" size="2">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_A3DP_Sink_Configure_IPC_Threshold" type="sc" opcode="0xFD9F">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD9F</Default>

+   <Desc> </Desc>

+  </Param>

+  <Param type="u" size="2" >

+   <Name>Buffering Threshold</Name>

+   <Default>1800</Default>

+   <Desc> The threshold to move from BUFFERING state to STREAMING State in ARM7 state machine </Desc>

+  </Param>

+  <Param type="u" size="2" >

+   <Name>Streaming Threshold</Name>

+   <Default>300</Default>

+   <Desc> The threshold to move from STREAMING state to OVER-LOAD State in ARM7 state machine </Desc>

+  </Param>

+  <Param type="u" size="2" >

+   <Name>Buffering after Underrun Threshold</Name>

+   <Default>1800</Default>

+   <Desc> The threshold to move from BUFFERING state to STREAMING State after Underrun in ARM7 state machine </Desc>

+  </Param>

+  <Param type="u" size="2" >

+   <Name>Underrun Threshold</Name>

+   <Default>5100</Default>

+   <Desc> The threshold to move from STREAMING state to BUFFERING State in ARM7 state machine </Desc>

+  </Param>

+  <Param type="u" size="8">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+

+    <Command name="HCI_VS_Load_Pre_Dist_Table" type="sc" opcode="0xFD24">

+        <Param type="o" size="2">

+            <Name>Opcode</Name> 

+            <Default>0xFD24</Default> 

+            <Desc>Loas AM2AM and AM2PM tables</Desc> 

+        </Param>

+        <Param type="u" size="1">

+            <Name>Process</Name> 

+            <Default>0</Default> 

+            <Desc>0 - Nominal, 1 - Weak, 2 - Strong</Desc> 

+        </Param>

+        <Param type="u" size="1">

+            <Name>Temperature Region</Name> 

+            <Default>1</Default> 

+            <Desc>0 - Cold, 1 - Room, 2 - Hot</Desc> 

+        </Param>

+        <Param type="u" size="1">

+            <Name>PM Config</Name> 

+            <Default>1</Default> 

+            <Desc>0 - Battrery, 1 - DC2DC, 2 - Not Used</Desc> 

+        </Param>

+        <Param type="u" size="4" label="len">

+            <Name>Size</Name>

+            <Default>04</Default>

+            <Desc>1-200</Desc>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Values</Name>

+            <Default>"00000000"</Default>

+            <Desc>Data starts from left to right</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name> 

+            <Default />

+            <Desc />

+        </Param>

+    </Command>	  

+  

+    <Command name="HCI_VS_Masked_Traces_Debug" type="vc" opcode="0xFD7A">

+	<Cat>Wibree</Cat>

+	<Param type="o" size="2">

+		<Name>Opcode</Name>

+		<Default>0xFD7A</Default>

+		<Desc>Set the masked traces debug configuration</Desc>

+	</Param>

+	<Param type="u" size="2" valtype="DebugMask">

+            <Name>Group 0: LE Data path Upper MAC</Name>

+            <Default>0x000</Default>

+            <Desc>The bit mask enabling Data path Upper MAC traces</Desc>

+    </Param>

+    <Param type="u" size="2" valtype="DebugMask">

+            <Name>Group 1: LE Scheduling GENERAL/SCAN/CONNECT Upper MAC</Name>

+            <Default>0x000</Default>

+            <Desc>The bit mask enabling Scheduling GENERAL/SCAN/CONNECT Upper MAC traces</Desc>

+    </Param>

+    <Param type="u" size="2" valtype="DebugMask">

+            <Name>Group 2: LE Scheduling CONNECTION Upper MAC</Name>

+            <Default>0x000</Default>

+            <Desc>The bit mask Scheduling ADV/CONNECTION Upper MAC traces</Desc>

+    </Param>

+     <Param type="u" size="2" valtype="DebugMask">

+            <Name>Group 3: LE General Upper MAC</Name>

+            <Default>0x000</Default>

+            <Desc>The bit mask enabling General Upper MAC traces</Desc>

+    </Param>

+    <Param type="u" size="2" valtype="DebugMask">

+            <Name>Group 4: LE Scheduling ADV Upper MAC</Name>

+            <Default>0x000</Default>

+            <Desc>The bit mask enabling Scheduling ADV Upper MAC</Desc>

+    </Param>

+    <Param type="u" size="2" valtype="DebugMask">

+            <Name>Group 5: BT Group 1 </Name>

+            <Default>0x000</Default>

+            <Desc>The bit mask enabling BT Group 1 </Desc>

+    </Param>

+     <Param type="u" size="2" valtype="DebugMask">

+            <Name>Group 6: BT Group 2 </Name>

+            <Default>0x000</Default>

+            <Desc>The bit mask enabling BT Group 2 </Desc>

+    </Param>

+    <Param type="u" size="2" valtype="DebugMask">

+            <Name>Group 26: LE CONNECT/SCAN Lower MAC</Name>

+            <Default>0x000</Default>

+            <Desc>The bit mask enabling ADV/SCAN Lower MAC traces</Desc>

+    </Param>

+    <Param type="u" size="2" valtype="DebugMask">

+            <Name>Group 27: LE Connection Lower MAC</Name>

+            <Default>0x000</Default>

+            <Desc>The bit mask enabling Connect/Connection Lower MAC traces</Desc>

+    </Param>

+    <Param type="u" size="2" valtype="DebugMask">

+            <Name>Group 28: LE Mini Sync/General Lower MAC</Name>

+            <Default>0x000</Default>

+            <Desc>The bit mask enabling Mini Sync/General Lower MAC traces</Desc>

+    </Param>

+    <Param type="u" size="2" valtype="DebugMask">

+            <Name>Group 29: LE ADV Lower MAC</Name>

+            <Default>0x000</Default>

+            <Desc>The bit mask enabling Encryption Lower MAC traces</Desc>

+    </Param>

+	<Param type="R">

+	   <Name>HCI_Command_Complete_Event</Name>

+	   <Default />

+	   <Desc />

+	</Param>

+	</Command>	

+

+	<Command name="HCI_VS_LOAD_Cortex" type="vc" opcode="0xFDA8">

+        <Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDA8</Default>

+			<Desc>Load Cortex</Desc>

+		</Param>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0x01 = Disable Cortex Sleep</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+

+	<Command name="HCI_VS_DRPB_Run_Self_Test" type="vc" opcode="0xFDC4">

+        <Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDC4</Default>

+			<Desc>Run DRPB self test</Desc>

+		</Param>

+        <Param type="u" size="1">

+            <Name>Test Bitmask</Name>

+            <Default>0x00</Default>

+            <Desc>bit_0 test TX_STOP to RX_START timing </Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>test status</Name>

+            <Default>0</Default>

+            <Desc>a 1 indicates failure in corresponding bit test</Desc>

+        </Param>

+    </Command>

+

+	<Command name="HCI_VS_FE_Configuration" type="sc" opcode="0xFDDC">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDDC</Default>

+            <Desc> </Desc>

+        </Param>

+        <Param type="u" size="1" valtype="FE_scheme">

+            <Name>FE Detection Scheme</Name>

+            <Default>0x00</Default>

+            <Desc>Detection scheme. 0 - Automatic; 1 - Manual</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="FE_types">

+            <Name>FE Type Manual</Name>

+            <Default>0x1</Default>

+            <Desc>FE Type: The value ignored in case of Automatic Detection</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="FE_mode">

+            <Name>FE Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0 - Single Band; 1 - Dual Band</Desc>

+        </Param>

+		<Param type="u" size="1" label="mode" valtype="EnableDisable">

+			<Name>Extended MAX Allowed Power</Name>

+			<Default>1</Default>

+			<Desc>0-Set single value for MAX Allowed Power 1-Set multiple values for MAX Allowed Power</Desc>

+		</Param>

+		<Param cond="mode==1">

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power GFSK - RFMD SB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for GFSK RFMD Single band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power EDR - RFMD SB</Name>

+				<Default>2*9</Default>

+				<Desc>Maximal allowed power for EDR RFMD Single band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power GFSK - TRIQ SB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for GFSK TRIQ Single band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power EDR - TRIQ SB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for EDR TRIQ Single band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power GFSK - SKW SB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for GFSK SKW Single band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power EDR - SKW SB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for EDR SKW Single band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power GFSK - Override SB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for GFSK Override Single band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power EDR - Override SB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for EDR Override Single band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power GFSK - RFMD DB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for GFSK RFMD Dual band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power EDR - RFMD DB</Name>

+				<Default>2*9</Default>

+				<Desc>Maximal allowed power for EDR RFMD Dual band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power GFSK - TRIQ DB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for GFSK TRIQ Dual band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power EDR - TRIQ DB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for EDR TRIQ Dual band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power GFSK - SKW DB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for GFSK SKW Dual band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power EDR - SKW DB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for EDR SKW Dual band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power GFSK - TRIQ HP DB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for GFSK TRIQ HP Dual band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power EDR - TRIQ HP DB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for EDR TRIQ HP Dual band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power GFSK - Override DB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for GFSK Override Dual band</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>MAX Allowed Power EDR - Override DB</Name>

+				<Default>0xFF</Default>

+				<Desc>Maximal allowed power for EDR Override Dual band</Desc>

+			</Param>

+		</Param>

+		<Param cond="mode == 0">

+        <Param type="u" size="1">

+            <Name>MAX Allowed Power</Name>

+				<Default>2*9</Default>

+            <Desc>Maximal allowed power for EDR 2/3</Desc>

+        </Param>

+		</Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+		

+	<Command name="HCI_VS_Read_RSSI" type="vc" opcode="0xFDFC">

+		<Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDFC</Default>

+            <Desc> </Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc>Read RSSI value without threshold for current handle</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+        </Param>

+        <Param type="d" size="1">

+            <Name>RSSI</Name>

+            <Default>0</Default>

+        </Param>

+    </Command>

+

+	<Command name="HCI_VS_Set_Sniff_Override_Intervals" type="vc" opcode="0xFDB4">

+		<Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDB4</Default>

+            <Desc> </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Slave BR</Name>

+            <Default>0x24</Default>

+            <Desc>Configure min T sniff in frames for HID connection when there is a slave connected with basic rate throughput</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Master BR</Name>

+            <Default>0x18</Default>

+            <Desc>Configure min T sniff in frames for HID connection when there is a master connected with basic rate throughput</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Slave EDR</Name>

+            <Default>0x20</Default>

+            <Desc>Configure min T sniff in frames for HID connection when there is a slave connected with EDR throughput</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Master EDR</Name>

+            <Default>0x10</Default>

+            <Desc>Configure min T sniff in frames for HID connection when there is a master connected with EDR throughput</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+	

+    <Command name="HCI_VS_Block_Events" type="sc" opcode="0xFDDB">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDDB</Default>

+            <Desc> </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Block/Unblock Events </Name>

+            <Default>0x01</Default>

+            <Desc>Block/Unblock Events to the host. 1 - Enable; 0 - Disable </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Reserved</Name>

+            <Default>0x0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+	 

+  <!-- =========================================================================================== -->   

+	<Command name="HCI VS LE Commands" type="gb" />

+  <!-- =========================================================================================== -->

+

+<Command name="HCI_VS_WIBREE_SET_WHITENING_MODE" type="vc" opcode="0xFD4C">

+	<Cat>Wibree</Cat>

+	<Param type="o" size="2">

+		<Name>Opcode</Name>

+		<Default>0xFD4C</Default>

+		<Desc>set Wibree whitening mode</Desc>

+	</Param>

+	<Param type="u" size="1" valtype="Wibree_force_no_force">

+		<Name>force connection access address</Name>

+		<Default>1</Default>

+		<Desc>0=Don't Force,1=Force</Desc>

+	</Param>	

+    <Param type="u" size="1" valtype="Wibree_Disable_Enable_Whitening">

+        <Name>whitening mode</Name>

+        <Default>1</Default>

+        <Desc>1=Enable whitening, 0=Disable whitening</Desc>

+	</Param>

+	<Param type="R">

+	   <Name>HCI_Command_Complete_Event</Name>

+	   <Default />

+	   <Desc />

+	 </Param> 

+</Command>

+

+<Command name="HCI_VS_BLE_Enable" type="vc" opcode="0xFD5B">

+		<Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFD5B</Default>

+			<Desc>Enable BLE sub-system</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>Enable , Disable</Name>

+			<Default>1</Default>

+			<Desc>0=Disable,1=Enable</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>Load LE code</Name>

+			<Default>1</Default>

+			<Desc>0=Dop not load code,1=Load code</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+			<Default />

+			<Desc />

+		</Param> 

+</Command>

+

+<Command name="HCI_VS_WIBREE_SET_SCAN_CERTAIN_FREQS" type="vc" opcode="0xFD21">

+	<Cat>Wibree</Cat>

+	<Param type="o" size="2">

+		<Name>Opcode</Name>

+		<Default>0xFD21</Default>

+		<Desc>set Wibree scan and connect to single period, hence together with setting (window = interval) will achive continues scan</Desc>

+	</Param>

+	<Param type="u" size="1" valtype="Wibree_force_no_force">

+		<Name>force certain freq mask</Name>

+		<Default>1</Default>

+		<Desc>0=Don't Force,1=Force</Desc>

+	</Param>

+	<Param type="u" size="1">

+		<Name>freq mask to be scanned</Name>

+		<Default>0x0</Default>

+		<Desc>any number 0 - 7</Desc>

+	</Param>

+	<Param type="R">

+	   <Name>HCI_Command_Complete_Event</Name>

+	   <Default />

+	   <Desc />

+	 </Param> 

+</Command>

+ 

+<Command name="HCI_VS_WIBREE_SET_LL_CHANNEL_ACCESS_ADDRESS" type="vc" opcode="0xFD6F">

+	<Cat>Wibree</Cat>

+	<Param type="o" size="2">

+		<Name>Opcode</Name>

+		<Default>0xFD6F</Default>

+		<Desc>set Wibree access address manualy</Desc>

+	</Param>

+	<Param type="u" size="1" valtype="Wibree_force_no_force">

+		<Name>force connection access address</Name>

+		<Default>1</Default>

+		<Desc>0=Don't Force,1=Force</Desc>

+	</Param>

+	<Param type="u" size="4">

+		<Name>access_address</Name>

+		<Default>0x0</Default>

+		<Desc>wb connection access address</Desc>

+	</Param>

+	<Param type="R">

+	   <Name>HCI_Command_Complete_Event</Name>

+	   <Default />

+	   <Desc />

+	 </Param> 

+</Command>

+

+

+	<Values name="Hci_LE_Encryption_Mode" type="enum">

+		<Value val="0x00">Open</Value>

+		<Value val="0x01">Encrypted</Value>

+	</Values>

+

+	<Values name="Hci_LE_Device_Roll" type="enum">

+		<Value val="0x01">Slave</Value>

+		<Value val="0x02">Master</Value>

+	</Values>

+

+<Command name="HCIPP_CORTEX_SET_SLEEP_MODE_CONFIGURATIONS" type="vc" opcode="0xFDA5">

+		<Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDA5</Default>

+			<Desc>set sleep mode configurations</Desc>

+		</Param>

+			<Param type="u" size="1">

+			<Name>enable cortex deep sleep</Name>

+			<Default>1</Default>

+			<Desc>1- enable cortex deep sleep while arm in big sleep, 0- disable.</Desc>

+		</Param>	

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+			<Default />

+			<Desc />

+		</Param> 

+</Command>

+

+<Command name="HCIPP_LE_TRANSACTION_DEBUG_CONFIGURATIONS" type="vc" opcode="0xFDA6">

+		<Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDA6</Default>

+			<Desc>set sleep mode configurations</Desc>

+		</Param>

+		<Param type="u" size="2" valtype="data_transaction_debug_mask">

+				<Name>reply Transaction</Name>

+				<Default>0x000</Default>

+				<Desc>Select the transaction that you want to reply with UNKNOWN_RSP to the peer </Desc>

+		</Param>

+		<Param type="u" size="2" valtype="data_transaction_debug_mask">

+				<Name>Ignore Transaction</Name>

+				<Default>0x000</Default>

+				<Desc>Select the transaction that you want to Ignore</Desc>

+		</Param>

+		<Param type="u" size="2" >

+				<Name>NACK Transaction</Name>

+				<Default>0x000</Default>

+				<Desc>0- Default , 1- Send NACK</Desc>

+		</Param>

+		<Param type="u" size="2" valtype="advertise_packet_debug_mask">

+				<Name>Ignore Advertise/Scanner Packet</Name>

+				<Default>0x000</Default>

+				<Desc>Select the Advertise Packet that you want to Ignore </Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+			<Default />

+			<Desc />

+		</Param> 

+</Command>

+

+<Command name="hcipp_le_general_configuration_enable_mask" type="vc" opcode="0xFDA7">

+		<Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDA7</Default>

+			<Desc>LE_GENERAL_CONFIGURATION_ENABLE</Desc>

+		</Param>

+		<Param type="u" size="2" valtype="LE_General_CFG_0">

+			<Name>cfg_0</Name>

+			<Default>0x5</Default>

+			<Desc>mask for false SYNC (AA) filtering and more. See bitmap</Desc>

+		</Param>

+		<Param type="u" size="2">

+				<Name>cfg_1</Name>

+				<Default>0x000</Default>

+				<Desc>mask for TBD ... </Desc>

+		</Param>

+		<Param type="u" size="2">

+				<Name>cfg_2</Name>

+				<Default>0x000</Default>

+				<Desc>mask for TBD ... </Desc>

+		</Param>

+		<Param type="u" size="2">

+				<Name>cfg_3</Name>

+				<Default>0x000</Default>

+				<Desc>mask for TBD ... </Desc>

+		</Param>

+		<Param type="u" size="2">

+				<Name>cfg_1</Name>

+				<Default>0x000</Default>

+				<Desc>mask for TBD ... </Desc>

+		</Param>

+		<Param type="u" size="2">

+				<Name>cfg_1</Name>

+				<Default>0x000</Default>

+				<Desc>mask for TBD ... </Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+			<Default />

+			<Desc />

+		</Param> 

+</Command>

+

+

+<Command name="HCI_VS_LE_Configure_Connection_Parameters" type="vc" opcode="0xFDAB">

+		<Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDAB</Default>

+			<Desc>configure connection parameters</Desc>

+		</Param>

+			<Param type="u" size="1">

+			<Name>MAX Event Duration</Name>

+			<Default>0xFF</Default>

+			<Desc>set the max event duraration</Desc>

+		</Param>

+			<Param type="u" size="1">

+			<Name>Create connection override voice TH</Name>

+			<Default>0xFF</Default>

+			<Desc>0-5</Desc>

+		</Param>

+			<Param type="u" size="1">

+			<Name>Voice override threshold (Non HID)</Name>

+			<Default>0xFF</Default>

+			<Desc>number of connection intervals before LSTO in which BLE connection starts overriding voice</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>HID Voice override threshold - denominator</Name>

+			<Default>0xFF</Default>

+			<Desc>The fraction (denominator) of LSTO in which BLE HID overrides voice</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>HID Voice override threshold - nominator</Name>

+			<Default>0xFF</Default>

+			<Desc>The fraction (nominator) of LSTO in which BLE HID overrides voice</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>HID interval threshold</Name>

+			<Default>0xFF</Default>

+			<Desc>Definitions the type of the BLE connections: Regular or HID. in frames</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>min trans distance in events</Name>

+			<Default>0xFF</Default>

+			<Desc>Define the min indicate of the connEventCount when the channelMapNEW shall be applied,a minimum of 6 connection.in frames</Desc>

+		</Param>

+		

+		<Param type="u" size="4">

+			<Name>Reserved</Name>

+			<Default>0xFFFF</Default>

+			<Desc>Reserved</Desc>

+		</Param>

+		<Param type="u" size="4">

+			<Name>Reserved</Name>

+			<Default>0xFFFF</Default>

+			<Desc>Reserved</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+			<Default />

+			<Desc />

+		</Param> 

+</Command>

+

+<Command name="HCIPP_LE_VS_Configure_Channel_Classification_Params" type="vc" opcode="0xFDAF">

+		<Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDAF</Default>

+			<Desc>configure channel classification params</Desc>

+		</Param>

+			<Param type="u" size="1">

+			<Name>Short Long threshold</Name>

+			<Default>50</Default>

+			<Desc>define the threshold between long and short sniff in mSec</Desc>

+		</Param>

+			<Param type="u" size="1">

+			<Name>Periodic Short Timer</Name>

+			<Default>200</Default>

+			<Desc>periodic trigger for Short sniff, integer multiply of *Tsniff. 0x1 - always running , 0x0 - the timer never trigger the AFH </Desc>

+		</Param>

+			<Param type="u" size="1">

+			<Name>Periodic Long Timer</Name>

+			<Default>160</Default>

+			<Desc>periodic trigger for Long sniff, integer multiply of *Tsniff. 0x1 - always running , 0x0 - the timer never trigger the AFH </Desc>

+		</Param>

+		<Param type="d" size="1">

+            <Name>No Sync RSSI threshold</Name>

+            <Default>-82</Default>

+            <Desc>When RSSI level is above the threshold and we notice no Sync requiers to active afh_scan, in dBm</Desc>

+		</Param>

+			<Param type="d" size="1">

+            <Name>SNR RSSI threshold</Name>

+            <Default>-72</Default>

+            <Desc>When RSSI level is above the threshold and SNR under the threshold requiers to active afh_scan, in dBm</Desc>

+		</Param>

+			<Param type="u" size="1">

+            <Name>Min SNR threshold </Name>

+            <Default>1</Default>

+            <Desc>When RSSI level is above the threshold and SNR under the threshold requiers to active afh_scan</Desc>

+		</Param>		

+			<Param type="u" size="1">

+			<Name>Short X 1sec timer</Name>

+			<Default>3</Default>

+			<Desc>Indicate number of time to repeat the afh_scan 1 sec timer loop (0 is NA)</Desc>

+		</Param>

+			<Param type="u" size="1">

+			<Name>Long X 1sec timer</Name>

+			<Default>2</Default>

+			<Desc>Indicate number of time to repeat the afh_scan 1 sec timer loop (0 is NA)</Desc>

+		</Param>		

+			<Param type="u" size="1">

+			<Name>ULP Nscan Short Sniff</Name>

+			<Default>4</Default>

+			<Desc>Number of afh_scan to perform every time the 1 sec timer is expierd</Desc>

+		</Param>

+			<Param type="u" size="1">

+			<Name>ULP Nscan Long Sniff</Name>

+			<Default>3</Default>

+			<Desc>Number of afh_scan to perform every time the 1 sec timer is expierd</Desc>

+		</Param>

+			<Param type="u" size="1">

+			<Name>consecutive no sync</Name>

+			<Default>2</Default>

+			<Desc>Trig AFH scan if (frame_from_last_sync > interval*(latency +1+ consecutive_no_sync)) 0-0xFD,0xFE - consecutive equal to latancy </Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>channel map change threshold</Name>

+			<Default>5</Default>

+			<Desc></Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>min events between updates</Name>

+			<Default>1</Default>

+			<Desc>min events (interval * latenct...) between two update channel map transactions</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>max events to block updates</Name>

+			<Default>20</Default>

+			<Desc>max events (interval * latenct...) from last that update channel map transactions in which a new  new map will be sent only if lots of channels have changed</Desc>

+		</Param>

+			<Param type="u" size="1">

+			<Name>AFH Tigger on no SYNC statistic threshold</Name>

+			<Default>0xA3</Default>

+			<Desc>bits [7:4] events to count untils decision, bits [3:0] number of no syncs in events, if higher than threshold trigger AFH</Desc>

+		</Param>		

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+			<Default />

+			<Desc />

+		</Param> 

+</Command>

+

+<Command name="HCI_VS_Write_LE_Channel_Assessment_Mode" type="vc" opcode="0xFDA9">

+        <Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDA9</Default>

+			<Desc>LE Channel Assessment Mode</Desc>

+		</Param>

+        <Param type="u" size="1" valtype="EnableDisable">

+            <Name>AFH Channel Assessment Mode</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 = BLE channel assessment disabled 0x01 = BLE channel assessment enabled</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+

+	<Command name="HCIPP_LE_VS_Configure_Scan_Parameters" type="vc" opcode="0xFDC0">

+		<Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDC0</Default>

+			<Desc>Configure Scan Parameters</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>Refresh Rate Threshhold</Name>

+			<Default>100</Default>

+			<Desc>Set the Filter duplicate refresh rate threshhold</Desc>

+		</Param>

+		<Param type="u" size="1" valtype="EnableDisableNoChange">

+			<Name>check data</Name>

+			<Default>0xFF</Default>

+			<Desc>Send event to host if ADV data was change</Desc>

+		</Param>

+		<Param type="u" size="1" valtype="EnableDisableNoChange">

+			<Name>wait for scan res</Name>

+			<Default>0xFF</Default>

+			<Desc>Continue to send ADV ind event to host if Scan res did not received.</Desc>

+		</Param>

+		<Param type="u" size="4">

+			<Name>Reserved</Name>

+			<Default>0xFFFF</Default>

+			<Desc>Reserved</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+			<Default />

+			<Desc />

+		</Param> 

+	</Command>

+	

+	<Command name="HCI_VS_LE_Configure_RSSI_Metering_Params" type="vc" opcode="0xFDC1">		

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDC1</Default>

+			<Desc>Configure RSSI metering params for performing RSSI average.

+			</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Interval Thresshold</Name>

+			<Default>400</Default>

+			<Desc>The inteval thresshold used to determine which Alpha to use: Short interval Alpha or long interval Alpha</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>Short interval Alpha</Name>

+			<Default>153</Default>

+			<Desc>The Alpha to use, as a fraction of 256. For instance, for a value of 0.75, use 0.75*256 = 192</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>Long interval Alpha</Name>

+			<Default>204</Default>

+			<Desc>The Alpha to use, as a fraction of 256. For instance, for a value of 0.25, use 0.25*256 = 64</Desc>

+		</Param>

+		<Param type="u" size="4">

+			<Name>Reserved</Name>

+			<Default>0</Default>

+			<Desc>Reserved</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+			<Default />

+			<Desc />

+		</Param> 

+	</Command>

+

+	<Command name="HCI_VS_Load_Compressed_Data" type="vc" opcode="0xFDC2">		

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDC2</Default>

+			<Desc>Load Compressed data in order to decompress an image.

+					Please note that this command can be used in a dual syntax:

+					The second parameter may be the target address.

+					The third parameter may be the compressed image size.

+					The fourth parameter may be the compressed buffer.

+			</Desc>

+		</Param>

+		<Param type="u" size="1" label="len">

+			<Name>Data Size</Name>

+			<Default>253</Default>

+			<Desc>Number of compressed bytes in this packet</Desc>

+		</Param>				

+        <Param type="x" size="len">

+            <Name>Values</Name>

+            <Default>"00000000"</Default>

+            <Desc>Compressed data to load.</Desc>

+        </Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+			<Default />

+			<Desc />

+		</Param> 

+	</Command>

+	<Command name="HCI_Write_LE_Qualification_Configuration" type="vc" opcode="0xFDB3">

+        <Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDB3</Default>

+			<Desc>LE Qualification Configuration - Act as tester</Desc>

+		</Param>

+        <Param type="u" size="4" valtype="LE_Qualification_bitmap">

+            <Name>Configuration Bit Map</Name>

+            <Default>0x00</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="d" size="1">

+            <Name>Param1</Name>

+            <Default>0x00</Default>

+            <Desc>Depending on the bitmap is the interpritaion of the field</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Param2</Name>

+            <Default>0x00</Default>

+            <Desc>Depending on the bitmap is the interpritaion of the field</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Param3</Name>

+            <Default>0x00</Default>

+            <Desc>Depending on the bitmap is the interpritaion of the field</Desc>

+        </Param>

+		<Param type="u" size="4">

+            <Name>Reserved</Name>

+            <Default>0x00</Default>

+            <Desc>Reserved for future use</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+    </Command>

+

+ <Command name="Hci_VS_LE_Read_Ber_Test_Results" type="vc" opcode="0xFDAE">

+		<Cat>Wibree</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFDAE</Default>

+			<Desc>Read BER Test results</Desc>

+		</Param>

+		<Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of BER in Type received </Name>

+            <Default>0</Default>

+            <Desc>Number of BER in Type received</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of BER in Length received </Name>

+            <Default>0</Default>

+            <Desc>Number of BER in Length received</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of BER in Payload Received Part 1 </Name>

+            <Default>0</Default>

+            <Desc>Number of BER in Payload received</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of BER in Payload Received Part 2 </Name>

+            <Default>0</Default>

+            <Desc>Number of BER in Payload received</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of BER in Payload Received Part 3 </Name>

+            <Default>0</Default>

+            <Desc>Number of BER in Payload received</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of BER in Payload Received Part 4 </Name>

+            <Default>0</Default>

+            <Desc>Number of BER in Payload received</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of BER in CRC received </Name>

+            <Default>0</Default>

+            <Desc>Number of BER in CRC received</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of SYNC Events received </Name>

+            <Default>0</Default>

+            <Desc>Number of SYNC Events received</Desc>

+        </Param>

+	<Param type="u" size="2">

+		<Name>Number of Packet with Bad Type </Name>

+			<Default>0</Default>

+		<Desc>Number of Packet with Bad Type received</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of Packet with Bad Length </Name>

+			<Default>0</Default>

+		<Desc>Number of Packet with Bad Length received</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of Packet with Bad CRC </Name>

+			<Default>0</Default>

+		<Desc>Number of Packet with Bad CRC received</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of FA Events </Name>

+			<Default>0</Default>

+		<Desc>Number of FA Events</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of iac_1_indication </Name>

+			<Default>0</Default>

+		<Desc>Number of iac_1_indication</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of iac_2_indication </Name>

+			<Default>0</Default>

+		<Desc>Number of iac_2_indication</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of iac_3_indication </Name>

+			<Default>0</Default>

+		<Desc>Number of iac_3_indication</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of 32 bit corrlation </Name>

+			<Default>0</Default>

+		<Desc>Number of 32 bit corrlation</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of 31 bit corrlation </Name>

+			<Default>0</Default>

+		<Desc>Number of 31 bit corrlation</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of 30 bit corrlation </Name>

+			<Default>0</Default>

+		<Desc>Number of 30 bit corrlation</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of 28_29 bit corrlation </Name>

+			<Default>0</Default>

+		<Desc>Number of 28_29 bit corrlation</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of 26_27 bit corrlation </Name>

+			<Default>0</Default>

+		<Desc>Number of 26_27 bit corrlation</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of 25 or less bit corrlation </Name>

+			<Default>0</Default>

+		<Desc>Number of 25 or less bit corrlation</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of good crc band sync packets</Name>

+			<Default>0</Default>

+		<Desc>Number of good crc band sync packets</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of good sync band crc packets</Name>

+			<Default>0</Default>

+		<Desc>Number of good sync band crc packets</Desc>

+	</Param>

+	<Param type="u" size="2">

+		<Name>Number of Packets with Good CRC</Name>

+			<Default>0</Default>

+		<Desc>Number of Packets with Good CRC Received</Desc>

+	</Param>

+	</Command>

+

+

+<Command name="HCI_VS_SET_BLE_WLAN_COEX_PARAMS" type="vc" opcode="0xFDC6">

+	<Cat>Wibree</Cat>

+	<Param type="o" size="2">

+		<Name>Opcode</Name>

+		<Default>0xFDC6</Default>

+		<Desc>set BLE WLAN coex priority</Desc>

+	</Param>

+	<Param type="u" size="1" >

+		<Name>priority_bitmask</Name>

+		<Default>0</Default>

+		<Desc>

+			bit 0 ADV

+			bit 1 scan

+			bit 2 connect

+			bit 3 reserved

+			bit 4 connection

+		</Desc>

+	</Param>	

+	<Param type="R">

+	   <Name>HCI_Command_Complete_Event</Name>

+	   <Default />

+	   <Desc />

+	 </Param> 

+</Command>

+

+

+

+    <Command name="HCI_VS_ANT_Enable" type="sc" opcode="0xFDD0">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDD0</Default>

+            <Desc> </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Enable/Disable ANT </Name>

+            <Default>0x01</Default>

+            <Desc>Enable/Disable The ANT Sub System.

+            1 - Enable. 0 - Disable </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Code Upload</Name>

+            <Default>0x01</Default>

+            <Desc>0x0 - Do not initialize ANT with code upload; 0x1 - initialize with code upload</Desc>

+        </Param>

+        <Param type="u" size="8">

+            <Name>Reserved</Name>

+            <Default>0x0</Default>

+            <Desc>Reserved</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+    <Command name="HCI_VS_ANT_Send_Msg" type="sc" opcode="0xFDD1">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDD1</Default>

+            <Desc> </Desc>

+        </Param>

+        <Param type="u" size="2" prop="h">

+            <Name>Length</Name>

+            <Value>size(data)</Value>

+        </Param>

+        <Param type="x" size="input" label="data">

+            <Name>Data</Name>

+            <Default>"00:11:22"</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+    <Command name="HCI_VS_LE_BLE_Output_Power" type="sc" opcode="0xFDDD">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDDD</Default>

+            <Desc> </Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Power Level Index</Name>

+            <Default>15</Default>

+            <Desc>Value indicating hte Power Level to be used for transmit output power of BLE</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_VS_ANT_Receive_Msg_Event" type="ve" opcode="0x0500">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>10000</Default>

+            <Desc>Timeout in msec</Desc>

+        </Param>

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0x0500</Default>

+            <Desc>Opcode</Desc>

+        </Param>

+        <Param type="u" size="2" prop="h" label="len">

+            <Name>Length</Name>

+            <Value></Value>

+        </Param>

+        <Param type="x" size="len" >

+            <Name>Data</Name>

+            <Default>"00:11:22"</Default>

+            <Desc />

+        </Param>

+     </Command>

+    

+

+    <!-- ================================================================== -->

+	<Command name="HCI Vendor Specific WBS Commands" type="gb" />

+    <!-- ================================================================== -->

+

+

+	<Command name="HCI_Vs_Wbs_Associate" type="vc" opcode="0xFD78">

+		<Cat>WBS</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFD9A</Default>

+			<Desc>TBD</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>ACL handle</Name>

+			<Default>0x1</Default>

+			<Desc>TBD</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+	</Command>

+

+	<Command name="HCI_Vs_Wbs_Disassociate" type="vc" opcode="0xFD79">

+		<Cat>WBS</Cat>

+		<Param type="o" size="2">

+			<Name>Opcode</Name>

+			<Default>0xFD9B</Default>

+			<Desc>TBD</Desc>

+	</Param>

+	<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+	</Param>

+

+	

+	</Command>

+

+    <!-- ================================================================== -->

+    <Command name="ACL" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="HCI_ACL_Data" type="cc">

+        <Cat>Spec 1.1</Cat>

+        

+        <Macro><![CDATA[

+		_handle_  = %1

+		_text_    = %2

+		_bdry_    = %3

+		_brdcst_   = %4

+

+		_size_ = size(_text_)

+

+		_handle_ |= (((_bdry_ & 3)<<12) | ((_brdcst_ & 3) << 14))

+

+		_data_ = todata(2, 1)

+		_data_ += todata(_handle_, 2)

+

+		if (g_bACL_L2CAP) then 

+			_data_ += todata(_size_, 2)

+			_data_ += _text_

+		else

+			_data_ += todata(_size_+4, 2)

+			_data_ += todata(_size_, 2)

+			_data_ += todata(0xDAD1, 2)

+			_data_ += _text_

+		end if

+

+		WritePort _data_

+

+]]></Macro>

+        

+        <Param type="h" size="2" bits="12" label="handle">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="s" label="data">

+            <Name>Text</Name>

+            <Default>"Hello World"</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2" bits="2" valtype="BoundaryPacketTypes">

+            <Name>Boundary</Name>

+            <Default>0x02</Default>

+            <Desc>0-Start Non-Flushable 1-Continuation 2-Start Flushable</Desc>

+        </Param>

+        <Param type="u" size="2" bits="2" valtype="BroadcastTypes">

+            <Name>Broadcast flag</Name>

+            <Default>0x00</Default>

+            <Desc>0-No broadcast 1-active 2-all</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_ACL_Data_Event" type="ce">

+        <Cat>Spec 1.1</Cat>

+        

+        <Macro><![CDATA[

+		_timeout_ = %1

+		_handle_  = %2

+		_bdry_    = %3

+		_text_    = %4

+		_brdcst_  = %5

+

+		_size_ = size(_text_)

+

+		Wait_HCI_ACL_Packet_Event _timeout_, _handle_, _bdry_, _brdcst_, &_data_

+

+		if (!g_bACL_L2CAP) then

+			# discard the L2CAP part

+			_data_ = mid(_data_, 4)

+		end if

+

+		if 0 != strcomp(_text_, _data_) then

+			Fail "Text mismatch. Expected: \"%s\", Got: \"%s\"", _text_, str(_data_)

+		end if

+

+]]></Macro>

+        

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec</Desc>

+        </Param>

+        <Param type="u">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" valtype="BoundaryTypes">

+            <Name>Boundary</Name>

+            <Default>0x02</Default>

+            <Desc>0-Start Non-Flushable 1-Continuation 2-Start Flushable</Desc>

+        </Param>

+        <Param type="s">

+            <Name>Data</Name>

+            <Default>"Hello World"</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="BroadcastTypes">

+            <Name>Broadcast flag</Name>

+            <Default>0x00</Default>

+            <Desc>0-No broadcast 1-active 2-all</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_ACL_Packet" type="cc">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x02</Value>

+        </Param>

+        <Param type="h" size="2" bits="12">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2" bits="2" valtype="BoundaryTypes">

+            <Name>Boundary</Name>

+            <Default>0x02</Default>

+            <Desc>0-Start Non-Flushable 1-Continuation 2-Start Flushable</Desc>

+        </Param>

+        <Param type="u" size="2" bits="2" valtype="BroadcastTypes">

+            <Name>Broadcast flag</Name>

+            <Default>0x00</Default>

+            <Desc>0-No broadcast 1-active 2-all</Desc>

+        </Param>

+        <Param type="u" size="2" prop="h">

+            <Name>Payload Length</Name>

+            <Value>size(data)</Value>

+        </Param>

+        <Param type="x" size="input" label="data">

+            <Name>Data</Name>

+            <Default>"00:11:22"</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_ACL_Packet_Event" type="acl_in">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x02</Value>

+        </Param>

+        <Param type="h" size="2" bits="12">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2" bits="2" valtype="BoundaryTypes">

+            <Name>Boundary</Name>

+            <Default>0x02</Default>

+            <Desc>0-Start Non-Flushable 1-Continuation 2-Start Flushable</Desc>

+        </Param>

+        <Param type="u" size="2" bits="2" valtype="BroadcastTypes">

+            <Name>Broadcast flag</Name>

+            <Default>0x00</Default>

+            <Desc>0-No broadcast 1-active 2-all</Desc>

+        </Param>

+        <Param type="u" size="2" label="len" prop="h">

+            <Name>Length</Name>

+            <Default>0</Default>

+        </Param>

+        <Param type="x" size="len">

+            <Name>Data</Name>

+            <Default>&amp;ACLData</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_L2CAP_Packet_Data" type="sc" prop="h">

+        <Cat>Spec 1.1</Cat>

+        

+        <Macro><![CDATA[

+		_handle_ = %1

+		_cid_    = %2

+		_data_   = %3

+		_brdcst_ = %4

+

+		# Only on init

+		if _acl_size_ > 0 && _acl_count_ > 0 then

+			# Already set, Do nothing

+		else

+			_acl_size_ = 0

+			_acl_count_ = 0

+			_acl_available_ = 0

+		end if

+

+		# Make sure we have the size of ACL packets and the buffers count

+		if _acl_size_ == 0 || _acl_count_ == 0 then

+			Send_HCI_Read_Buffer_Size

+			Wait_HCI_Command_Complete_Read_Buffer_Size_Event 5000, any, HCI_Read_Buffer_Size, 0, &_acl_size_, any, &_acl_count_, any

+		end if

+

+		# If still no information the error

+		if _acl_size_ == 0 || _acl_count_ == 0 then

+			Fail "ACL Buffer Size Error"

+		end if

+

+		_acl_available_ = _acl_count_

+

+		# Create the whole payload (to be splited later for each ACL

+		_data_ = todata(size(_data_), 2) + todata(_cid_,2) + todata(_data_)

+		_size_ = size(_data_)

+

+		_pos_ = 0

+		_segment_ = _acl_size_

+

+		if _segment_ > 0 then

+			while _pos_ < _size_

+				

+				# Loop on all free buffers available

+				while _pos_ < _size_ && _acl_available_ > 0

+					abPayload = mid(_data_, _pos_, _segment_)

+					Send_HCI_ACL_Packet _handle_, _pos_==0 ? 2 : 1, _brdcst_, todata(abPayload)

+					_pos_ += _segment_

+					_acl_available_--

+				wend

+			

+				Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_

+				_acl_available_ += _freed_

+			wend

+				

+				# Wait for all completed events that still need to come up   

+				while _acl_available_ < _acl_count_

+						Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_

+						_acl_available_ += _freed_

+				wend

+		end if

+]]></Macro>

+        

+        <Param type="u">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u">

+            <Name>CID</Name>

+            <Default>0xDAD1</Default>

+            <Desc />

+        </Param>

+        <Param type="x">

+            <Name>Data</Name>

+            <Default>"Hello World"</Default>

+            <Desc />

+        </Param>

+        <Param type="u" valtype="BroadcastTypes">

+            <Name>Broadcast flag</Name>

+            <Default>0x00</Default>

+            <Desc>0-No broadcast 1-active 2-all</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_L2CAP_Packet" type="sc">

+        <Cat>Spec 1.1</Cat>

+        

+        <Macro><![CDATA[

+		_handle_ = %1

+		_cid_    = %2

+		_data_   = %3

+		_brdcst_ = %4

+

+		# Only on init

+		if _acl_size_ > 0 && _acl_count_ > 0 then

+			# Already set, Do nothing

+		else

+			_acl_size_ = 0

+			_acl_count_ = 0

+			_acl_available_ = 0

+		end if

+

+		# Make sure we have the size of ACL packets and the buffers count

+		if _acl_size_ == 0 || _acl_count_ == 0 then

+			Send_HCI_Read_Buffer_Size

+			Wait_HCI_Command_Complete_Read_Buffer_Size_Event 5000, any, HCI_Read_Buffer_Size, 0, &_acl_size_, any, &_acl_count_, any

+		end if

+

+		# If still no information the error

+		if _acl_size_ == 0 || _acl_count_ == 0 then

+			Fail "ACL Buffer Size Error"

+		end if

+

+		_acl_available_ = _acl_count_

+

+		# Create the whole payload (to be splited later for each ACL

+		_data_ = todata(size(_data_)+1, 2) + todata(_cid_,2) + todata(_data_) + todata(0, 1)

+		_size_ = size(_data_)

+

+		_pos_ = 0

+		_segment_ = _acl_size_

+

+		if _segment_ > 0 then

+			while _pos_ < _size_

+				

+				# Loop on all free buffers available

+				while _pos_ < _size_ && _acl_available_ > 0

+					abPayload = mid(_data_, _pos_, _segment_)

+					Send_HCI_ACL_Packet _handle_, _pos_==0 ? 2 : 1, _brdcst_, todata(abPayload)

+					_pos_ += _segment_

+					_acl_available_--

+				wend

+			

+				Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_

+				_acl_available_ += _freed_

+			wend

+				

+				# Wait for all completed events that still need to come up   

+				while _acl_available_ < _acl_count_

+						Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_

+						_acl_available_ += _freed_

+				wend

+		end if

+]]></Macro>

+        

+        <Param type="u">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u">

+            <Name>CID</Name>

+            <Default>0xDAD1</Default>

+            <Desc />

+        </Param>

+        <Param type="s">

+            <Name>Text</Name>

+            <Default>"Hello World"</Default>

+            <Desc />

+        </Param>

+        <Param type="u" valtype="BroadcastTypes">

+            <Name>Broadcast flag</Name>

+            <Default>0x00</Default>

+            <Desc>0-No broadcast 1-active 2-all</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_L2CAP_Packet_Event" type="se">

+        <Cat>Spec 1.1</Cat>

+        

+        <Macro><![CDATA[

+		_timeout_ = %1

+		_handle_  = %2

+		_cid_     = %3

+		_text_    = %4

+

+		_size_ = size(_text_)

+		_got_ = 0

+

+		while _got_ < _size_

+			Wait_HCI_ACL_Packet_Event _timeout_, _handle_, _got_==0 ? 2 : 1, any, &_data_

+

+			if (_got_==0) then

+				

+				# Match CID

+				_cidin_ = val(mid(_data_, 2, 2))

+				if _cid_ != _cidin_ then

+					Fail "CID mismatch. Expected: 0x%04x, Got: 0x%04x", _cid_, _cidin_

+				end if

+

+				_whole_ = mid(_data_, 4)

+				_got_ += size(_data_) - 4

+		

+			else

+		

+				_whole_ += _data_

+				_got_ += size(_data_)

+		

+			end if

+

+		wend

+

+		# Match text

+		if 0 != strcomp(_text_, _whole_) then

+			Fail "Text mismatch. Expected: \"%s\", Got: \"%s\"", _text_, str(_whole_)

+		end if

+

+]]></Macro>

+        

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u">

+            <Name>CID</Name>

+            <Default>0xDAD1</Default>

+            <Desc />

+        </Param>

+        <Param type="s">

+            <Name>Text</Name>

+            <Default>"Hello World"</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_ACL_L2CAP_Text" type="cc">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x02</Value>

+        </Param>

+        <Param type="h" size="2" bits="12">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2" bits="2" valtype="BoundaryTypes">

+            <Name>Boundary</Name>

+            <Default>0x02</Default>

+            <Desc>1-Continuation 2-Start</Desc>

+        </Param>

+        <Param type="u" size="2" bits="2" valtype="BroadcastTypes">

+            <Name>Broadcast flag</Name>

+            <Default>0x00</Default>

+            <Desc>0-No broadcast 1-active 2-all</Desc>

+        </Param>

+        <Param type="u" label="cid">

+            <Name>CID</Name>

+            <Default>0xDad1</Default>

+        </Param>

+        <Param type="s" label="text">

+            <Name>Text</Name>

+            <Default>"Hello World"</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2" prop="h">

+            <Name>Payload Length</Name>

+            <Value>size(text)+5</Value>

+        </Param>

+        <Param type="u" size="2" prop="h">

+            <Name>L2CAP Payload Length</Name>

+            <Value>size(text)+1</Value>

+        </Param>

+        <Param type="u" size="2" prop="h">

+            <Name>CID</Name>

+            <Value>cid</Value>

+        </Param>

+        <Param type="s" size="size(text)+1" prop="h">

+            <Name>Text</Name>

+            <Value>text</Value>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_ACL_L2CAP_Data" type="cc">

+        <Cat>Spec 1.1</Cat>

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x02</Value>

+        </Param>

+        <Param type="h" size="2" bits="12">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2" bits="2" valtype="BoundaryTypes">

+            <Name>Boundary</Name>

+            <Default>0x02</Default>

+            <Desc>1-Continuation 2-Start</Desc>

+        </Param>

+        <Param type="u" size="2" bits="2" valtype="BroadcastTypes">

+            <Name>Broadcast flag</Name>

+            <Default>0x00</Default>

+            <Desc>0-No broadcast 1-active 2-all</Desc>

+        </Param>

+        <Param type="u" size="2" prop="h">

+            <Name>Payload Length</Name>

+            <Value>size(data)+4</Value>

+        </Param>

+        <Param type="u" size="2" prop="h">

+            <Name>L2CAP Payload Length</Name>

+            <Value>size(data)</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>CID</Name>

+            <Default>0xDad1</Default>

+        </Param>

+        <Param type="x" size="input" label="data">

+            <Name>Data</Name>

+            <Default>"00:11:22"</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCI_ACL_Data_Types" type="sc">

+        <Cat>Spec 1.1</Cat>

+        

+        <Macro><![CDATA[

+		_handle_ = %1

+		_type_   = %2

+		_path_   = %3

+		_bdry_   = %4

+		_brdcst_ = %5

+		_fmt_    = %6

+

+		If _type_==1 Then

+			Send_HCI_ACL_L2CAP_Text _handle_, _bdry_, _brdcst_, 0xDad1, _path_

+		Else

+			# Extract the file name without the path

+			_pos_ = InStrRev(_path_, "\\")

+	

+			if (_pos_ >= 0) then

+				_name_ = mid(_path_, _pos_+1)

+			else

+				_name_ = _path_

+			end if

+	

+			if _fmt_==2 then

+				LoadFile _FileData_, _path_

+				_size_ = size(_FileData_)

+				Send_HCI_L2CAP_Packet_Data _handle_, 0xDA00, todata(_name_) + todata(0, 1) + _FileData_, _brdcst_

+			else

+				# Only on init

+				if _acl_size_ > 0 && _acl_count_ > 0 then

+					# Already set, Do nothing

+				else

+					_acl_size_ = 0

+					_acl_count_ = 0

+					_acl_available_ = 0

+				end if

+		

+				# Make sure we have the size of ACL packets and the buffers count

+				if _acl_size_ == 0 || _acl_count_ == 0 then

+					Send_HCI_Read_Buffer_Size

+					Wait_HCI_Command_Complete_Read_Buffer_Size_Event 5000, any, HCI_Read_Buffer_Size, 0, &_acl_size_, any, &_acl_count_, any

+				end if

+		

+				# If still no information the error

+				if _acl_size_ == 0 || _acl_count_ == 0 then

+					Fail "ACL Buffer Size Error"

+				end if

+		

+				_acl_available_ = _acl_count_

+		

+				##############################

+				# Write Header

+				##############################

+		

+				LoadFile _FileData_, _path_

+		

+				_size_ = size(_FileData_)

+				abHeaderData = todata(_size_, 4) + todata(_name_) + todata(0, 1)

+		

+				Send_HCI_ACL_L2CAP_Data _handle_, _bdry_, _brdcst_, 0xDada, abHeaderData

+		

+				_acl_available_--

+				_pos_ = 0

+				_segment_ = _acl_size_ - 4

+		

+				if _segment_ > 0 then

+					while _pos_ < _size_

+						

+						# Loop on all free buffers available

+						while _pos_ < _size_ && _acl_available_ > 0

+							abPayload = mid(_FileData_, _pos_, _segment_)

+							Send_HCI_ACL_L2CAP_Data _handle_, _bdry_, _brdcst_, 0xDada, abPayload

+							_pos_ += _segment_

+							_acl_available_--

+						wend

+					

+						Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_

+						_acl_available_ += _freed_

+					WEnd

+				

+				# Wait for all completed events that still need to come up   

+				while _acl_available_ < _acl_count_

+						Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_

+						_acl_available_ += _freed_

+					WEnd

+				End If

+			End If

+		End If

+]]></Macro>

+        

+        <Param type="u">

+            <Name>Connection Handle</Name>

+            <Default>Handle</Default>

+            <Desc />

+        </Param>

+        <Param type="u" valtype="ACLSendType" label="type">

+            <Name>Type</Name>

+            <Default>0</Default>

+            <Desc />

+        </Param>

+        <Param type="s" cond="type==0">

+            <Name>File Path</Name>

+            <Default>""</Default>

+            <Desc />

+        </Param>

+        <Param type="s" cond="type!=0">

+            <Name>Text</Name>

+            <Default>"Hello World"</Default>

+            <Desc />

+        </Param>

+        <Param type="u" valtype="BoundaryTypes">

+            <Name>Boundary</Name>

+            <Default>0x02</Default>

+            <Desc>1-Continuation 2-Start</Desc>

+        </Param>

+        <Param type="u" valtype="BroadcastTypes">

+            <Name>Broadcast flag</Name>

+            <Default>0x00</Default>

+            <Desc>0-No broadcast 1-active 2-all</Desc>

+        </Param>

+        <Param type="u" valtype="L2CAPFmt">

+            <Name>Format</Name>

+            <Default>0x00</Default>

+            <Desc>0-UPF 1-HCICommander 2-L2CAP</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="FM_Command_On_Channel_8" type="cc">

+        

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x08</Value>

+        </Param>

+        

+        <Param type="u" size="0" valtype="FM_command" label="fm_opcode_">

+            <Name>Fm_Opcode</Name>

+            <Default>0</Default>

+            <Desc>opcode of FM module [8 bits]</Desc>

+        </Param>

+        

+        <Param type="u" size="0" valtype="fm_command_type" label="command_type">

+            <Name>Command Type</Name>

+            <Default>0</Default>

+            <Desc>0 - Write, 1 - Read</Desc>

+        </Param>

+        

+        <Param cond="command_type==0">

+            <Param cond="fm_opcode_.lt.0x63 || fm_opcode_.gt.0x65">

+                <Param type="u" size="1" prop="h">

+                    <Name>Length</Name>

+                    <Value>0x05</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Fm_Opcode</Name>

+                    <Value>fm_opcode_</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Command Type</Name>

+                    <Value>command_type</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Length</Name>

+                    <Value>0x02</Value>

+                </Param>

+                <Param type="u" size="2" prop="r">

+                    <Name>Data</Name>

+                    <Default>0x0000</Default>

+                    <Desc>Data to write</Desc>

+                </Param>

+                

+            </Param>

+            <Param cond="fm_opcode_==0x64">

+                <Param type="u" size="1" prop="h">

+                    <Name>Length</Name>

+                    <Value>0x09</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Fm_Opcode</Name>

+                    <Value>fm_opcode_</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Command Type</Name>

+                    <Value>command_type</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Length</Name>

+                    <Value>0x06</Value>

+                </Param>

+                <Param type="u" size="0" label="address">

+                    <Name>Addr</Name>

+                    <Default>0x00000000</Default>

+                    <Desc>Fm register address [16 bits]</Desc>

+                </Param>

+                <Param type="u" size="4" prop="hr">

+                    <Name>Address</Name>

+                    <Value>address</Value>

+                </Param>

+                <Param type="u" size="2" prop="r">

+                    <Name>Data</Name>

+                    <Default>0x0000</Default>

+                    <Desc>Data to write</Desc>

+                </Param>

+            </Param>

+            

+            <Param cond="fm_opcode_==0x65">

+                <Param type="u" size="0" label="length">

+                    <Name>Data Length</Name>

+                    <Default>4</Default>

+                    <Desc>Data Length 0-1024 [16 bits]</Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Length</Name>

+                    <Value>length+3</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Fm_Opcode</Name>

+                    <Value>fm_opcode_</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Command Type</Name>

+                    <Value>command_type</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Data Length</Name>

+                    <Value>length</Value>

+                    <Desc></Desc>

+                </Param>

+                <Param type="x" size="length">

+                    <Name>Data</Name>

+                    <Default>"0000"</Default>

+                    <Desc>start Address in hex (16 bit), and new code</Desc>

+                </Param>

+            </Param>

+        </Param>

+        

+        <Param cond="command_type==1">

+            <Param cond="fm_opcode_!=0x64 &amp;&amp; fm_opcode_!=5">

+                <Param type="u" size="1" prop="h">

+                    <Name>Length</Name>

+                    <Value>0x03</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Fm_Opcode</Name>

+                    <Value>fm_opcode_</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Command Type</Name>

+                    <Value>command_type</Value>

+                </Param>

+                <Param type="u" size="1" prop="h" label="length">

+                    <Name>Length</Name>

+                    <Value>0x02</Value>

+                </Param>

+            </Param>

+            <Param cond="fm_opcode_==5">

+                <Param type="u" size="1" prop="h">

+                    <Name>Length</Name>

+                    <Value>0x03</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Fm_Opcode</Name>

+                    <Value>fm_opcode_</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Command Type</Name>

+                    <Value>command_type</Value>

+                </Param>

+                <Param type="u" size="1">

+                    <Name>Length</Name>

+                    <Default>0x03</Default>

+                    <Desc>Data Length [16 bits], should be multiple of 3, Max Length 250</Desc>

+                </Param>

+            </Param>

+            <Param cond="fm_opcode_==0x64">

+                <Param type="u" size="1" prop="h">

+                    <Name>Length</Name>

+                    <Default>0x05</Default>

+                    <Desc></Desc>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Fm_Opcode</Name>

+                    <Value>fm_opcode_</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Command Type</Name>

+                    <Value>command_type</Value>

+                </Param>

+                <Param type="u" size="1" prop="h">

+                    <Name>Length</Name>

+                    <Value>0x02</Value>

+                </Param>

+                <Param type="u" size="0" label="address_">

+                    <Name>Addr</Name>

+                    <Default>0x0000</Default>

+                    <Desc>Fm register address [16 bits]</Desc>

+                </Param>

+                <Param type="u" size="2" prop="hr">

+                    <Name>Address_div_2_</Name>

+                    <Value>address_/2</Value>

+                </Param>

+            </Param>

+            

+        </Param>

+        

+        <Param type="R">

+            <Name>FM_Channel_8_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        

+    </Command>

+

+

+   <Command name="FM_Channel_8_Event" type="FM_Event">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x08</Value>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Num_FM_HCI_Commands</Name>

+            <Default>any</Default>

+        </Param>

+        <Param type="u" size="1" valtype="FM_command" label="fm_Opcode">

+            <Name>FM Opcode</Name>

+            <Default>0x00</Default>

+        </Param>

+        <Param type="u" size="1" valtype="fm_command_type" label="command_type">

+            <Name>Command Type</Name>

+            <Default>0x00</Default>

+        </Param>

+        <Param type="u" size="1" label="len">

+            <Name>Data Length</Name>

+            <Default>0x02</Default>

+        </Param>

+        

+        <Param cond="fm_Opcode==5">

+            <Param type="x" size="len"> 

+                <Name>Data Parameters</Name> 

+                <Default>0x00</Default>

+            </Param>

+        </Param>

+        <Param cond="fm_Opcode!=5">

+            <Param cond="command_type==1">

+                <Param type="u" size="2" prop="r"> 

+                    <Name>Data Parameters</Name> 

+                    <Default>0x00</Default>

+                </Param>

+            </Param>

+            <Param cond="command_type!=1">

+                <Param type="u" size="len"> 

+                    <Name>Data Parameters</Name> 

+                    <Default>0x00</Default>

+                </Param>

+            </Param>

+        </Param>

+        

+    </Command>    

+	

+    <!-- ================================================================== -->

+    <Command name="Deep Sleep" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="HCILL_GO_TO_Sleep_Ind" type="HCILL Command" opcode="0x0030">

+        <Param type="R">

+            <Name>HCILL_GO_TO_Sleep_Ack_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCILL_GO_TO_Sleep_Ack" type="HCILL Command" opcode="0x0031" />

+    

+    <Command name="HCILL_Wake_Up_Ind" type="HCILL Command" opcode="0x0032">

+        <Param type="R">

+            <Name>HCILL_Wake_Up_Ack_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HCILL_Wake_Up_Ack" type="HCILL Command" opcode="0x0033" />

+    

+    <Command name="HCILL_GO_TO_Sleep_Ind_Event" type="HCILL Event" opcode="0x0030">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="o" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x30</Value>

+        </Param>

+    </Command>

+    

+    <Command name="HCILL_GO_TO_Sleep_Ack_Event" type="HCILL Event" opcode="0x0031">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="o" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x31</Value>

+        </Param>

+    </Command>

+    

+    <Command name="HCILL_Wake_Up_Ind_Event" type="HCILL Event" opcode="0x0032">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="o" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x32</Value>

+        </Param>

+    </Command>

+    

+    <Command name="HCILL_Wake_Up_Ack_Event" type="HCILL Event" opcode="0x0033">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="o" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x33</Value>

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="DOT Commands" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="DOT_General" type="dc" opcode="0x0001">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0001</Value>

+            <Desc>General</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Baud rate</Name>

+            <Default>0     </Default>

+            <Desc>0=low=115.2kbps, 1=high= either 921.6kbps or 1000kbps, or type the baudrate directly.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Reset_&amp;_Negotiation" type="dc" opcode="0x0002">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0002</Value>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x24</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Reset BT now, Init baudrate</Name>

+            <Default>0</Default>

+            <Desc>0 = Don't Reset, baudtare = FREF/320,

+                1 = Reset BT, baudtare = FREF/320, 

+                2 = Don't Reset, baudtare = 115200,

+                3 = Reset BT, baudtare = 115200 

+            </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Start Negotiation now</Name>

+            <Default>1</Default>

+            <Desc>0= No              1= Yes        </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Flow control         </Name>

+            <Default>0</Default>

+            <Desc>0= Byte wise,    1= Packet wise,   0x0002-0xFFFE = segmentation (segment size in bytes)</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Clock of BT device   </Name>

+            <Default>13000000</Default>

+            <Desc>Hz</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Baud rate            </Name>

+            <Default>0</Default>

+            <Desc>0=low=115.2kbps, 1=high= either 921.6kbps or 1000kbps, or type the baudrate directly.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Palau spec 3.0</Name>

+            <Default>1</Default>

+            <Desc>0=old spec,   1=new (16-bit align, new negotiation, Etc.)</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>RTS pulse width</Name>

+            <Default>0</Default>

+            <Desc>Minumum width of RTS pulse in packet wise (T5)</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Enable Deep sleep after negotiation</Name>

+            <Default>1</Default>

+            <Desc>0=Keep previous (Enb/Dis), 1=Enable, 2=Disable deep sleep after negotiation</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Padding needed        </Name>

+            <Default>0</Default>

+            <Desc>0= No              1= Yes        </Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Data_Generation_Configuration" type="dc" opcode="0x0003">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0003</Value>

+            <Desc>Data Generation Configuration</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x18</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Period of statistic message</Name>

+            <Default>20    </Default>

+            <Desc>Sec.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Send ACL Data packets to host</Name>

+            <Default>0     </Default>

+            <Desc>0=No   1=Yes</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Order of packets</Name>

+            <Default>0     </Default>

+            <Desc>(Not supported) 0=Cyclic 1=Random. For 2 or more connections</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Read Buffer size</Name>

+            <Default>0     </Default>

+            <Desc>0=DOT sends the command, Else=Buffer size of BT</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Context of packets</Name>

+            <Default>0     </Default>

+            <Desc>0=Incremental data,  1=All bytes are zero</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>ThreshHold for statistics</Name>

+            <Default>0     </Default>

+            <Desc>0=STT_Event only,  1 and above= DBG_Event</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Host_Flow_Control" type="dc" opcode="0x0004">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0004</Value>

+            <Desc>TBD, Host flow Control</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x20</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Enable</Name>

+            <Default>1     </Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of host ACL buffers</Name>

+            <Default>5     </Default>

+            <Desc>0..20</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Host packet size          </Name>

+            <Default>100   </Default>

+            <Desc>0..65535</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Threshold, for host_num.. </Name>

+            <Default>4     </Default>

+            <Desc>1..20, minimum number of ACL packets</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Timeout to send host_num..</Name>

+            <Default>2000  </Default>

+            <Desc>ms, 10..10000, if threhold didn't happen</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Algorithm to choose handle</Name>

+            <Default>0     </Default>

+            <Desc>0=Recived handle, 1=Round Robin</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Time between commands     </Name>

+            <Default>0     </Default>

+            <Desc>Not supported</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Burst of commands         </Name>

+            <Default>0     </Default>

+            <Desc>0=Normal, 1=Dot trys to send burst of commands</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event    </Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Deep_Sleep" type="dc" opcode="0x0006">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0006</Value>

+            <Desc>Deep Sleep (Nokia Only)</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x10</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Enable deep sleep </Name>

+            <Default>1     </Default>

+            <Desc>0=Disable   1=Enable</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Minimum sleep time</Name>

+            <Default>0     </Default>

+            <Desc>ms, Minimum low time for BT_WAKEUP signal.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Minimum awake time</Name>

+            <Default>0     </Default>

+            <Desc>ms, Minimum high time for BT_WAKEUP signal.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Wait for cts before rising bt wakeup</Name>

+            <Default>0</Default>

+            <Desc>0=Drop and Immediate raise of BT wakeup is Alowed. 1=After Droping the bt_wakeup, Wait for RTS.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Deep_Sleep_Motorola" type="dc" opcode="0x001B">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x001B</Value>

+            <Desc>Deep Sleep (Motorola Only)</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x14</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Enable deep sleep </Name>

+            <Default>1     </Default>

+            <Desc>0=Disable   1=Enable</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Minimum sleep time</Name>

+            <Default>0     </Default>

+            <Desc>ms, Minimum deassert time for BT_WAKE signal.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Minimum awake time</Name>

+            <Default>0     </Default>

+            <Desc>ms, Minimum assert time for BT_WAKE signal.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Polarity of BT_WAKE signal</Name>

+            <Default>0</Default>

+            <Desc>0=active low, 1=active high.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Polarity of HOST_WAKE signal</Name>

+            <Default>0</Default>

+            <Desc>0=active low, 1=active high.</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Deep_Sleep_HCILL" type="dc" opcode="0x0010">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0010</Value>

+            <Desc>Deep Sleep</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x1C</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Enable and Protocol</Name>

+            <Default>2     </Default>

+            <Desc>0=Disable, 2=HCILL</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Sleep Time range1</Name>

+            <Default>0     </Default>

+            <Desc>ms, Minimum low time for BT_WAKEUP signal. Random LOWER range</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Sleep Time range2</Name>

+            <Default>100   </Default>

+            <Desc>ms, Minimum low time for BT_WAKEUP signal. Random UPPER range</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Wake Time range1</Name>

+            <Default>0     </Default>

+            <Desc>ms, Minimum high time for BT_WAKEUP signal. Random LOWER range</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Wake Time range2</Name>

+            <Default>100   </Default>

+            <Desc>ms, Minimum high time for BT_WAKEUP signal. Random UPPER range</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Delay before Wakeup Ack</Name>

+            <Default>0     </Default>

+            <Desc>ms</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Delay before Sleep Ack</Name>

+            <Default>0   </Default>

+            <Desc>ms</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+    <Command name="DOT_Deep_Sleep_EMP" type="dc" opcode="0x0039">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0039</Value>

+            <Desc>Deep Sleep</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x14</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Enable and Protocol</Name>

+            <Default>4     </Default>

+            <Desc>0=Disable, 4=EMP</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Sleep Time lower range</Name>

+            <Default>0     </Default>

+            <Desc>ms, Minimum time that the device will be sleeping </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Sleep Time upper range</Name>

+            <Default>100   </Default>

+            <Desc>ms, Minimum time that the device will be sleeping </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Wake Time lower range</Name>

+            <Default>0     </Default>

+            <Desc>ms, Minimum time that the device will be awake (before setting the break indication) </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Wake Time upper range</Name>

+            <Default>100   </Default>

+            <Desc>ms, Minimum time that the device will be awake (before setting the break indication)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Write_Hardware_Register" type="dc" opcode="0x0011">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0011</Value>

+            <Desc>Write Hardware Register</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x06</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address            </Name>

+            <Default>0x03007ffc</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Value              </Name>

+            <Default>0x0000</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Read_Hardware_Register" type="dc" opcode="0x0012">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0012</Value>

+            <Desc>Read Hardware Register</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Address</Name>

+            <Default>0x03007ffc</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Configure_ARMIO" type="dc" opcode="0x0032">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0032</Value>

+            <Desc>Configure ARMIO Port</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x02</Value>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Port number</Name>

+            <Default>2</Default>

+            <Desc>Available IO's - 2,3,5,14</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>port direction</Name>

+            <Default>0x0</Default>

+            <Desc>1-Input, 0 -output</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+    <Command name="DOT_Write_ARMIO_Port" type="dc" opcode="0x0036">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0036</Value>

+            <Desc>Write ARMIO Port</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x02</Value>

+        </Param>

+        <Param type="u" size="1">

+            <Name>ARMIO Port Number</Name>

+            <Default>2</Default>

+            <Desc>Available IO's - 2,3,5,14</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>ARMIO Port Level</Name>

+            <Default>0</Default>

+            <Desc>0=False,  1=True</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+    <Command name="DOT_Read_ARMIO_Port" type="dc" opcode="0x0033">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0033</Value>

+            <Desc>Read ARMIO Port</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x01</Value>

+        </Param>

+        <Param type="u" size="1">

+            <Name>ARMIO Port Number</Name>

+            <Default>0</Default>

+            <Desc>Available IO's - 2,3,5,14</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+    <Command name="DOT_force_bt_wakeup" type="dc" opcode="0x0015">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0015</Value>

+            <Desc>Force BT wakeup signal</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Value</Name>

+            <Default>0</Default>

+            <Desc>0=low=, 1=high. Dot Deep sleep protocol must be 'Disable'</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Alive" type="dc" opcode="0x0016">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0016</Value>

+            <Desc>Dot will send a palau alive message to BT devive</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Period (sec)</Name>

+            <Default>70</Default>

+            <Desc>0=disable, other=period</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Generate_SCO_Data" type="dc" opcode="0x0017">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0017</Value>

+            <Desc>Generate_SCO_Data</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x0c</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Channel</Name>

+            <Default>0     </Default>

+            <Desc>0/1 - SCO Channel</Desc>

+        </Param>

+        <Param type="u" size="4" valtype="SCO_generation_type">

+            <Name>Data Genration Type</Name>

+            <Default>0     </Default>

+            <Desc>0=Off, 1=Loopback, 2=Codec, 3=Pattern Sine, 4=Pattern Byte Saw Tooth, 5=Pattern Packet Saw Tooth</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Data Genration Rate</Name>

+            <Default>8000</Default>

+            <Desc>Rate [Bytes/sec]. Valid Params for Codec: 8000 (8KHz 8bit),

+                16000 (8KHz 16bit), 24000 (8KHz 24bit), 32000 (32KHz 8bit)

+            </Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Configure_SCO_Data" type="dc" opcode="0x0018">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0018</Value>

+            <Desc>Configure_SCO_Data - The DOT executes read buffer size</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x14</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Channel</Name>

+            <Default>0     </Default>

+            <Desc>0/1 - SCO Channel</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Min SCO Buffer Threshold</Name>

+            <Default>30</Default>

+            <Desc>Min SCO Buffer threshold [bytes]</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Max SCO Buffer Threshold</Name>

+            <Default>30</Default>

+            <Desc>Max SCO Buffer threshold [bytes]</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Min SCO Packet Size</Name>

+            <Default>30</Default>

+            <Desc>Min SCO Packet Size [bytes]</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Max SCO Packet Size</Name>

+            <Default>30</Default>

+            <Desc>Max SCO Packet Size [bytes]</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Host_SCO_Flow_Control" type="dc" opcode="0x001A">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x001A</Value>

+            <Desc>Host SCO flow Control</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>24</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>BT Flow Control Enable</Name>

+            <Default>0</Default>

+            <Desc>1/0 - Enable/Disable Flow control from the Host to the BT</Desc>

+        </Param>

+        <Param type="u" size="4" label="host_flow">

+            <Name>Host Flow Control Enable</Name>

+            <Default>0</Default>

+            <Desc>1/0 - Enable/Disable Flow control from the BT to the host</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of host SCO buffers</Name>

+            <Default>10</Default>

+            <Desc>0..40, DOT3: 0..6</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Host SCO buffer size</Name>

+            <Default>120</Default>

+            <Desc>0..255</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Threshold, for host_num.. </Name>

+            <Default>4</Default>

+            <Desc>1..20, minimum number of SCO buffers</Desc>

+        </Param>

+        <Param type="u" size="4" prop="h">

+            <Name>Algorithm to choose handle</Name>

+            <Default>0</Default>

+            <Desc>0=Received handle, 1=Round Robin</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event    </Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_H5" type="dc" opcode="0x0019">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0019</Value>

+            <Desc>Activate H5 protocol</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x14</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Enable</Name>

+            <Default>5</Default>

+            <Desc>5=Use H5 protocol,   4=Use H4 protocol</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Baudrate</Name>

+            <Default>115200</Default>

+            <Desc>bps</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Window size</Name>

+            <Default>4</Default>

+            <Desc>1-7</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Flow control</Name>

+            <Default>1</Default>

+            <Desc>0=None,  1=HW(cts/rts),  2=SW (xon/xoff)</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>CRC allowed</Name>

+            <Default>0</Default>

+            <Desc>0=crc is not allowed, 1=crc is allowed</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="DOT3 Commands" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="DOT_SDIO" type="dc" opcode="0x001E">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x001E</Value>

+            <Desc>Activate SDIO</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x08</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>SDIO Mode</Name>

+            <Default>0</Default>

+            <Desc>SDIO Data bus width 

+            0 = 1 bit , 1 = 4 bits </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Receive over Transmit priority</Name>

+            <Default>1</Default>

+            <Desc>Value more then 0, determines during interleaving how many packets are to be received before resume of current tranmission. Zero means NO interleaving</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_SDIO_Deep_Sleep" type="dc" opcode="0x0029">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0029</Value>

+            <Desc>SDIO deep sleep</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x14</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Deep Sleep Enable</Name>

+            <Default>0</Default>

+            <Desc>0 - Disable, 1 - Enable</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Sleep Time range1</Name>

+            <Default>0     </Default>

+            <Desc>ms, </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Sleep Time range2</Name>

+            <Default>100   </Default>

+            <Desc>ms, Make sure that max value range for deassertion timer in DOT must be smaller than deassertion timer in sleep protocol configurations VS.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>SDIO Sleep Mode</Name>

+            <Default>0</Default>

+            <Desc>0 - Commands will wake up the device, 1 - SDIO Clocks will wakeup the device </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>SDIO min wake time before sending commands</Name>

+            <Default>0</Default>

+            <Desc>Time (in us) between waking up the device and sending the first packet (relevant when clocks will wakeup the device)</Desc>

+        </Param>

+        

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_SDIO_Change_Retry" type="dc" opcode="0x001F">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x001F</Value>

+            <Desc>Change read acknowledgement behavior</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Set Read Acknowledgement </Name>

+            <Default>0</Default>

+            <Desc>0 = Disable , 1 = Enable</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_SDIO_Change_Max_Clock_Rate" type="dc" opcode="0x0020">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0020</Value>

+            <Desc>Change SDIO max clock</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Clock</Name>

+            <Default>25000000</Default>

+            <Desc>Clock im Hz</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_SDIO_Send_Command_52" type="dc" opcode="0x0021">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0021</Value>

+            <Desc>Issue command 52</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>20</Value>

+        </Param>

+        <Param type="u" size="2"  valtype="SDIO Dest CMD52">

+            <Name>SDIO destination</Name>

+            <Default>0</Default>

+            <Desc>0 - Legacy mode,

+                1 - Shared SDIO, BT 

+                2 - Shared SDIO, WLAN

+            </Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Read / write</Name>

+            <Default>0</Default>

+            <Desc>0 - Read, 1 - Write</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Function Number</Name>

+            <Default>0</Default>

+            <Desc>0 - 7</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Read After Write flag</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Register Address</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Write Data</Name>

+            <Default>0</Default>

+            <Desc>Must be 0 in read commands</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_SDIO_Send_Command_53" type="dc" opcode="0x0022">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0022</Value>

+            <Desc>Issue command 52</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>84</Value>

+        </Param>

+        <Param type="u" size="2"  valtype="SDIO Dest CMD53">

+            <Name>SDIO destination</Name>

+            <Default>0</Default>

+            <Desc>0 - Legacy mode,

+                1 - Shared SDIO, BT 

+                2 - Shared SDIO, WLAN

+            </Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Read / write</Name>

+            <Default>0</Default>

+            <Desc>0 - Read, 1 - Write</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Function Number</Name>

+            <Default>0</Default>

+            <Desc>0 - 7</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Block Mode and Opcode</Name>

+            <Default>0</Default>

+            <Desc>0 - R/W from fixed address, 1 - R/W from incrementing address</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Register Address</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Byte / Block count</Name>

+            <Default>0</Default>

+            <Desc>Must be 0 in read commands</Desc>

+        </Param>

+        <Param type="x" size="64">

+            <Name>Data to be sent</Name>

+            <Default></Default>

+            <Desc>Relevant only in write commands</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_SDIO_Send_Command" type="dc" opcode="0x0023">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0023</Value>

+            <Desc>Issue SDIO General command</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>8</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>SDIO destination </Name>

+            <Default>0</Default>

+            <Desc>0 = Legacy mode,

+                1 = Shared SDIO, BT

+                2 = Shared SDIO, WLAN

+            </Desc>

+        </Param>

+        <Param type="u" size="2" valtype="SDIO Commands">

+            <Name>SDIO Command value</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Argument</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Configure_Codec_Emulator" type="dc" opcode="0x0024">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0024</Value>

+            <Desc>Configure codec emulator. This command stops the sco generation.</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>60</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Enable/Disable</Name>

+            <Default>0</Default>

+            <Desc>1 - Enable, 0 - Disable</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Emulator clock rate</Name>

+            <Default>2048</Default>

+            <Desc>[64-16000] The PCM clock rate is between 64k to 4096k (Master mode) or 64K to 16M (Slave mode), it influence other params like: wait cycles, freq rate calcs and therefore shall be configured even if external clock is used</Desc>

+        </Param>

+        <Param type="u" size="4" valtype="Role">

+            <Name>Emulator role</Name>

+            <Default>0x00</Default>

+            <Desc>PCM clock and fsync direction: 0x00 - output (Master on PCM bus) sampled on rising edge. 0x01 - input (Slave on PCM bus).</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Frame sync frequency</Name>

+            <Default>8000</Default>

+            <Desc>[100Hz-173KHz] Actual frame sync frequency in Hz.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Frame sync duty cycle</Name>

+            <Default>0x0001</Default>

+            <Desc>0x0000 - 50 % of Fsync period, [0x0001-0xFFFF] - Number of PCM clock cycles</Desc>

+        </Param>

+        <Param type="u" size="4" valtype="Sampling_edge_type">

+            <Name>Frame sync edge</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 - Driven/sampled at rising edge, 0x01 - Driven/sampled at falling edge</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Frame sync polarity</Name>

+            <Default>0x00</Default>

+            <Desc>0x00 - Active-high, 0x01 - Active-low</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Data out size</Name>

+            <Default>0x0010</Default>

+            <Desc>[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Data out offset ch1</Name>

+            <Default>1</Default>

+            <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Data out offset ch2</Name>

+            <Default>17</Default>

+            <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>

+        </Param>

+        <Param type="u" size="4" valtype="Sampling_edge_type">

+            <Name>Data out edge</Name>

+            <Default>0x00</Default>

+            <Desc>Data driven: 0x00 - rising edge, 0x01 - falling edge</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Data in size</Name>

+            <Default>0x10</Default>

+            <Desc>[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Data in offset ch1</Name>

+            <Default>1</Default>

+            <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Data in offset ch2</Name>

+            <Default>17</Default>

+            <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>

+        </Param>

+        <Param type="u" size="4" valtype="Sampling_edge_type">

+            <Name>Data in edge</Name>

+            <Default>0x01</Default>

+            <Desc>Data sampled: 0x00- rising edge, 0x01 - falling edge</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_eSPI" type="dc" opcode="0x0025">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0025</Value>

+            <Desc>eSPI configuration</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>48</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>eSPI Mode </Name>

+            <Default>1</Default>

+            <Desc>0 = Init,

+                1 = Change timing parameters

+            </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>RX Delay Interrupt -> CS</Name>

+            <Default>0</Default>

+            <Desc>Delay between Interrupt line assertion until CS assertion [u sec]</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>TX Delay Interrupt -> Header</Name>

+            <Default>0</Default>

+            <Desc>Delay between Interrupt line assertion until header (type1) is sent [u sec]</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>RX Delay CS -> Header</Name>

+            <Default>0</Default>

+            <Desc>Delay between CS line assertion until header (type3) is sent [u sec]</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Delay Header -> Data</Name>

+            <Default>0</Default>

+            <Desc>Delay between header to data [u sec]</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Delay Data -> CS</Name>

+            <Default>0</Default>

+            <Desc>Delay between last data byte until CS deassertion [u sec]</Desc>

+        </Param>

+        <Param type="u" size="4">

+			<Name>Reserved</Name>

+            <Default>0</Default>

+			<Desc></Desc>

+        </Param>

+        <Param type="u" size="4">

+			<Name>Reserved</Name>

+            <Default>0</Default>

+			<Desc></Desc>

+        </Param>

+        <Param type="u" size="4">

+			<Name>Reserved</Name>

+            <Default>0</Default>

+			<Desc></Desc>

+        </Param>

+        <Param type="u" size="4">

+			<Name>Reserved</Name>

+            <Default>0</Default>

+			<Desc></Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Time between two consequtive HCI packets</Name>

+            <Default>0</Default>

+            <Desc>Time between two consequtive HCI packets [u sec]</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Reset BT Device</Name>

+            <Default>0</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+	<Command name="DOT_RX_Data_Validity" type="dc" opcode="0x0026">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0026</Value>

+			<Desc>configure RX validity checking</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>4</Value>

+        </Param>

+        <Param type="u" size="4">

+			<Name>Mode</Name>

+			<Default>1</Default>

+			<Desc>0 = Disable checking validity,

+				1 = Enable checking validity</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="DOT_TI_SPI_Mode" type="dc" opcode="0x002B">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x002B</Value>

+            <Desc>SPI mode</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>2</Value>

+        </Param>

+        <Param type="u" size="1">

+            <Name>SPI Mode </Name>

+            <Default>1</Default>

+            <Desc>0 = eSPI mode, 1 = TI SPI Mode</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>SPI SWAP Mode (Reserved) </Name>

+            <Default>0</Default>

+            <Desc>(Reserved)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_SDIO_Rx_Error_Generation" type="dc" opcode="0x0027">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0027</Value>

+            <Desc>Configure SDIO error generation for Rx flow

+                (NACK generation instead of ACK)

+            </Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x10</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Random Mode</Name>

+            <Default>0</Default>

+            <Desc>0 = Non random, 1 = Random mode 

+                (errors are generated at random times on random blocks)

+            </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Packet number</Name>

+            <Default>0</Default>

+            <Desc>Upon reception of which packet error will be generated.

+                0 - No error will be generated

+            </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Block number</Name>

+            <Default>0</Default>

+            <Desc>Upon reception of which SD block error generated.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>One shot</Name>

+            <Default>1</Default>

+            <Desc>1 - one shot. 0 - forever</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_SDIO_Tx_Error_Generation" type="dc" opcode="0x0028">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0028</Value>

+            <Desc>Configure SDIO error generation for Tx flow.

+                Noise generation on DAT line while SDIO transmits

+            </Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x10</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Random Mode</Name>

+            <Default>0</Default>

+            <Desc>0 = Non random, 1 = Random mode 

+                (errors are generated at random times on random blocks)

+            </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Packet number</Name>

+            <Default>0</Default>

+            <Desc>Upon transmission of which packet error will be generated.

+                0 - No error will be generated

+            </Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Block number</Name>

+            <Default>0</Default>

+            <Desc>Upon transmission of which SD block error generated.</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>One shot</Name>

+            <Default>1</Default>

+            <Desc>1 - one shot. 0 - forever</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Set_Uart_HCI_Baudrate" type="dc" opcode="0x002A">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Default>0x002A</Default>

+            <Desc>Set Uart HCI Baudrate parameters</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x10</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Divider</Name>

+            <Default>0</Default>

+            <Desc>Baudrate Uart Divider</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Oversampling</Name>

+            <Default>0</Default>

+            <Desc>Baudrate Uart Oversampling</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Swallow Period</Name>

+            <Default>0</Default>

+            <Desc>Baudrate Uart Swallow Period</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Middle of Bit</Name>

+            <Default>0</Default>

+            <Desc>Middle of Bit value</Desc>

+        </Param>

+        

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Cpu_Idle_Time" type="dc" opcode="0x0034">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Default>0x0034</Default>

+            <Desc>DOT_Cpu_Idle_Time</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x2</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Time</Name>

+            <Default>80</Default>

+            <Desc>0-Enter CPU test mode , 1-Exit CPU test mode, other - start and check for "param" * 8ms (Dot Timer ticks) </Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    <Command name="DOT_Set_Uart_Debug_Baud_Rate" type="dc" opcode="0x002E">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x002E</Value>

+            <Desc>Set DOT uart debug baud rate</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Baud Rate</Name>

+            <Default>921600</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    <Command name="DOT_Test" type="dc" opcode="0x0035">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0035</Value>

+            <Desc>DOT test debug</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Param</Name>

+            <Default>0</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+

+    <Command name="DOT_SLIMbus" type="dc" opcode="0x0040">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0040</Value>

+            <Desc>DOT SLIMbus initialization and Configuration</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x0A</Value>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Mode</Name>

+            <Default>1</Default>

+            <Desc>1: Initialize and Configure, 0: Configure (already initialize). This parameter should be set to 1 at the first time this command being called, and only then.</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Dot is Active Framer</Name>

+            <Default>1</Default>

+            <Desc>1: Active Framer role is done by the DOT, 0: Active Framer role is done by another framer on the bus. If the setup includes only DOT and WL7, this parameter must be set to 1. This parameter is "Don't care" if Mode == 0</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Initial Root Frequency</Name>

+            <Default>1</Default>

+            <Desc>All frequencies are in MHz: 1: 24.576, 2: 22.5792, 3: 15.36, 4: 16.8, 5: 19.2 6: 24, 7: 25, 8: 26, 9: 27. Note: At the moment, Initial Root Frequency must be 24.576, Initial Clock Gear must be 9, and Clock Divider must be 4. This parameter is "Don't care" if Mode == 0</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Initial Clock Gear</Name>

+            <Default>9</Default>

+            <Desc>0 to 10, in respect to the definitions in the SLIMbus Specification. 10: clock is not divided, 9: clock is divided by 2, 8: divided by 4, and so on. Note: At the moment, Initial Root Frequency must be 24.576, Initial Clock Gear must be 9, and Clock Divider must be 4. This parameter is "Don't care" if Mode == 0</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Initial Subframe Mode</Name>

+            <Default>0xB</Default>

+            <Desc>Subframe Mode according to the SLIMbus Specification, to be used initially until reconfigured otherwise using normal SLIMbus sequence (NEXT_SUBFRAME_MODE). This parameter is "Don't care" if Mode == 0</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Clock Source Select</Name>

+            <Default>0</Default>

+            <Desc>0 - CODEC (12.288 MHz or 12 MHz), 1 - External (FPGA external clock), 2 - FREF (19.2 MHz). This parameter is "Don't care" if Mode == 0</Desc>

+        </Param>

+      <Param type="u" size="1">

+            <Name>Clock Divider</Name>

+            <Default>4</Default>

+            <Desc>0 - ratio 1:32 (gears 6 to 10 forbidden), 1 - ratio 1:16 (gears 7 to 10 forbidden), 2 - ratio 1:8 (gears 8 to 10 forbidden), 3 - ratio 1:4 (gears 9 to 10 forbidden), 4 - ratio 1:2 (gear 10 forbidden), 5 - ratio 1:1 (root frequency = input frequency), 6 - 1:2, 7 - 1:4, 8 - 1:8, 9 - 1:16, 10 - 1:32. Note: At the moment, Initial Root Frequency must be 24.576, Initial Clock Gear must be 9, and Clock Divider must be 4. This parameter is "Don't care" if Mode == 0</Desc>

+        </Param>

+       <Param type="u" size="1">

+            <Name>Enable HCI</Name>

+            <Default>1</Default>

+            <Desc>1 - Enable, 0 - Disable, 0xFF - Don't change</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Enable Debug Level 1 Trace Messages</Name>

+            <Default>1</Default>

+            <Desc>1 - Enable, 0 - Disable, 0xFF - Don't change</Desc>

+        </Param>        

+        <Param type="u" size="1">

+            <Name>Enable Debug Level 2 Trace Messages</Name>

+            <Default>0</Default>

+            <Desc>1 - Enable, 0 - Disable, 0xFF - Don't change</Desc>

+        </Param>        

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_SLIMbus_Manual_Clock_Resume" type="dc" opcode="0x0042">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0042</Value>

+            <Desc>DOT SLIMbus manual clock resume</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x00</Value>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_SLIMbus_Audio_CODEC_Configuration" type="dc" opcode="0x0044">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0044</Value>

+            <Desc>DOT SLIMbus Audio CODEC Configuration</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="u" size="1">

+            <Name>audio format</Name>

+            <Default>0x53</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>sample rate</Name>

+            <Default>0x0C</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>left volume</Name>

+            <Default>0x17</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>right volume</Name>

+            <Default>0x17</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_SLIMbus_Audio" type="dc" opcode="0x0041">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0041</Value>

+            <Desc>DOT SLIMbus initialize Audio</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x26</Value>

+        </Param>

+        <Param type="u" size="1">

+            <Name>audio format</Name>

+            <Default>0x53</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>sample rate</Name>

+            <Default>0x0C</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>left volume</Name>

+            <Default>0x17</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>right volume</Name>

+            <Default>0x17</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" label="ch0_mode">

+			<Name>Channel 0</Name>

+			<Default>1</Default>

+			<Desc>0-disable 1-TX 2-RX</Desc>

+		</Param>

+		<Param cond="ch0_mode!=0">

+			<Param type="u" size="1">

+				<Name>Source Device ID</Name>

+				<Default>2</Default>

+				<Desc>TX Device logical number</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>Sink Device ID</Name>

+				<Default>5</Default>

+				<Desc>Rx Device logical number</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>TX Port index</Name>

+				<Default>4</Default>

+				<Desc>1-HCI_TX;

+        4-BT_AUDIO_TX_0;5-BT_AUDIO_TX_1

+        8-FM_AUDIO_TX_0;9-FM_AUDIO_TX_1</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>RX Port index</Name>

+				<Default>2</Default>

+				<Desc>0-HCI_RX;

+        2-BT_AUDIO_RX_0;3-BT_AUDIO_RX_1

+        6-FM_AUDIO_RX_0;7FM_AUDIO_RX_1</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>Channel number</Name>

+				<Default>0</Default>

+				<Desc>channel number from 0 to 7</Desc>

+			</Param>

+

+			<Param type="u" size="1">

+				<Name>Transport protocol</Name>

+				<Default>0</Default>

+				<Desc></Desc>

+			</Param>

+			<Param type="u" size="2">

+				<Name>segment distribution</Name>

+				<Default>0x24</Default>

+				<Desc></Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>segment length</Name>

+				<Default>4</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>frequency locked</Name>

+				<Default>0</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>presence rate</Name>

+				<Default>0x11</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>auxiliary bit format</Name>

+				<Default>0</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>data type</Name>

+				<Default>0</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>channel link</Name>

+				<Default>0</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>data length</Name>

+				<Default>4</Default>

+				<Desc></Desc>

+			</Param>

+	  </Param>

+	  <Param cond="ch0_mode == 0">

+			<Param type="s" size="15" prop="h">

+				<Name></Name>

+			</Param>

+	  </Param>

+        <Param type="u" size="1" label="ch1_mode">

+			<Name>Channel 1</Name>

+			<Default>2</Default>

+			<Desc>0-disable 1-TX 2-RX</Desc>

+		</Param>

+		<Param cond="ch1_mode!=0">

+			<Param type="u" size="1">

+				<Name>Source Device ID</Name>

+				<Default>5</Default>

+				<Desc>TX Device logical number</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>Sink Device ID</Name>

+				<Default>2</Default>

+				<Desc>RX Device logical number</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>TX Port index</Name>

+				<Default>4</Default>

+				<Desc>1-HCI_TX

+        4-BT_AUDIO_TX_0;5-BT_AUDIO_TX_1

+        8-FM_AUDIO_TX_0;9-FM_AUDIO_TX_1</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>RX Port index</Name>

+				<Default>2</Default>

+				<Desc>0-HCI_RX

+        2-BT_AUDIO_RX_0;3-BT_AUDIO_RX_1

+        6-FM_AUDIO_RX_0;7FM_AUDIO_RX_1</Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>Channel number</Name>

+				<Default>1</Default>

+				<Desc>channel number from 0 to 7</Desc>

+			</Param>

+

+			<Param type="u" size="1">

+				<Name>Transport protocol</Name>

+				<Default>0</Default>

+				<Desc></Desc>

+			</Param>

+			<Param type="u" size="2">

+				<Name>segment distribution</Name>

+				<Default>0x28</Default>

+				<Desc></Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>segment length</Name>

+				<Default>4</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>frequency locked</Name>

+				<Default>0</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>presence rate</Name>

+				<Default>0x11</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>auxiliary bit format</Name>

+				<Default>0</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>data type</Name>

+				<Default>0</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>channel link</Name>

+				<Default>0</Default>

+				<Desc> </Desc>

+			</Param>

+			<Param type="u" size="1">

+				<Name>data length</Name>

+				<Default>4</Default>

+				<Desc></Desc>

+			</Param>

+	    </Param>

+	    <Param cond="ch1_mode == 0">

+			<Param type="s" size="15" prop="h">

+				<Name></Name>

+			</Param>

+	    </Param>

+	    <Param type="u" size="1">

+		    <Name>Subframe mode</Name>

+		    <Default>0xA</Default>

+		    <Desc></Desc>

+	    </Param>

+	    <Param type="u" size="1">

+		    <Name>Clock gear</Name>

+		    <Default>8</Default>

+		    <Desc></Desc>

+	    </Param>

+

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    <Command name="DOT_SLIMbus_Send_Message" type="dc" opcode="0x0048">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0048</Value>

+            <Desc>DOT SLIMbus send message for Debug purpose</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>3 + size(dest) + size(data)</Value>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Message ID</Name>

+            <Default>0x0C</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Destination Length</Name>

+            <Value>size(dest)</Value>

+        </Param>

+        <Param type="x" size="input" label="dest">

+            <Name>Destination</Name>

+            <Default>"11:22:33:44:55:66"</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Payload Length</Name>

+            <Value>size(data)</Value>

+        </Param>

+        <Param type="x" size="input" label="data">

+            <Name>Data</Name>

+            <Default>"00:11:22"</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+     

+    <Command name="DOT_SlimBus_Deep_Sleep" type="dc" opcode="0x0043">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0043</Value>

+            <Desc>Slimbus Deep Sleep in band and out of band</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x18</Value>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Enable and Protocol</Name>

+            <Default>5     </Default>

+            <Desc>0=Disable, 5=SBIS 6=SB Out of Band</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Sleep Time range1</Name>

+            <Default>0     </Default>

+            <Desc>ms, Minimum low time for BT_WAKEUP signal. Random LOWER range</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Sleep Time range2</Name>

+            <Default>100   </Default>

+            <Desc>ms, Minimum low time for BT_WAKEUP signal. Random UPPER range</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Wake Time range1</Name>

+            <Default>0     </Default>

+            <Desc>ms, Minimum high time for BT_WAKEUP signal. Random LOWER range</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Just Wake Time range2</Name>

+            <Default>100   </Default>

+            <Desc>ms, Minimum high time for BT_WAKEUP signal. Random UPPER range</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Automatic Clock Pause on HCI SUSPENDED</Name>

+            <Default>0   </Default>

+            <Desc>Contols whether when both TX and RX are suspended, the DOT automatically sends a clock pause sequence (begin/pause/now). 0: Disable, 1: Enable, 0xFF: Don't change</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+        <!-- ================================================================== -->

+    <Command name="DOT Data Generation (per Handle)" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="DOT_Start" type="dc" opcode="0x000b">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x000B</Value>

+            <Desc>Start Data Generation</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>0x0001</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+            <Name>Test Type</Name>

+            <Default>3</Default>

+            <Desc>1=RX   2=TX   3=RX+TX </Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Stop" type="dc" opcode="0x000c">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x000C</Value>

+            <Desc>Stop Data Generation</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x02</Value>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>0x0001</Default>

+            <Desc />

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Packet_size" type="dc" opcode="0x000d">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x000D</Value>

+            <Desc>Packet size</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x12</Value>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>0x0001</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Unit of packet size</Name>

+            <Default>0     </Default>

+            <Desc>0=Packet has a Fix size   ,   1=Random</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Fix packet size</Name>

+            <Default>339   </Default>

+            <Desc>5-339, Affective only with Fix size</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Random lower range</Name>

+            <Default>5     </Default>

+            <Desc>5-339, Affective only with Random</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Random upper range</Name>

+            <Default>339   </Default>

+            <Desc>5-339, Affective only with Random</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Rate" type="dc" opcode="0x000e">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x000E</Value>

+            <Desc>Rate</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+			<Value>14</Value>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>0x0001</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Maximum rate</Name>

+            <Default>0     </Default>

+            <Desc>Bit per second.  0= Maximum rate</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Resolution</Name>

+            <Default>2     </Default>

+            <Desc>1=Delay every 1 second,  2=Delay every 8ms</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Number of Packets</Name>

+            <Default>0     </Default>

+            <Desc>limit the number of bt buffers to use in TX. 0=Max buffers,  1 - Max buffers (lowest - highest)</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_L2CAP_Header" type="dc" opcode="0x000f">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x000F</Value>

+            <Desc>L2CAP Header</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>0x12</Value>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>0x0001</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+			<Name>Number of TX channel ID's</Name>

+            <Default>1     </Default>

+            <Desc>How many headers are in this list</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Algoritm to choose an ID</Name>

+            <Default>1     </Default>

+            <Desc>0=Cyclyc,   1=Random</Desc>

+        </Param>

+        <Param type="u" size="2">

+			<Name>TX Channel ID #1</Name>

+            <Default>0x0041</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+			<Name>TX Channel ID #2</Name>

+            <Default>0xDADA</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+			<Name>TX Channel ID #3</Name>

+            <Default>0x0042</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+			<Name>TX Channel ID #4</Name>

+            <Default>0x0043</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+			<Name>TX Channel ID #5</Name>

+            <Default>0x0044</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="2">

+			<Name>A3DP RX channel ID</Name>

+			<Default>0x0000</Default>

+			<Desc>0 - No ID</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_Host_Flow_Control_Rate" type="dc" opcode="0x0014">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0xF0</Value>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Opcode</Name>

+            <Value>0x0014</Value>

+            <Desc>Host flow control Rate</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>6</Value>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Connection Handle</Name>

+            <Default>0x0001</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Maximum rate</Name>

+            <Default>0     </Default>

+            <Desc>Bit per second.  0= Maximum rate</Desc>

+        </Param>

+        <Param type="R">

+            <Name>DOT_DBG_Response_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+	<Command name="DOT_Configure_ACL" type="dc" opcode="0x002C">

+		<Param type="u" size="1" prop="h">

+			<Name>Layer</Name>

+			<Value>0xF0</Value>

+			</Param>

+		<Param type="u" size="2">

+			<Name>Opcode</Name>

+			<Value>0x2C</Value>

+			<Desc>ACL Header</Desc>

+		</Param>

+		<Param type="u" size="1" prop="h">

+			<Name>Length</Name>

+			<Value>0x10</Value>

+			</Param>

+		<Param type="h" size="2">

+			<Name>Connection Handle</Name>

+			<Default>0x0001</Default>

+			<Desc />

+		</Param>

+		<Param type="u" size="2" label="mode">

+			<Name>Configure ACL Header</Name>

+			<Default>1</Default>

+			<Desc>0-Set header with fixed params 1-Set header according to the following params</Desc>

+		</Param>

+		<Param cond="mode==1">

+			<Param type="u" size="2">

+				<Name>ACL Boundary</Name>

+				<Default>2</Default>

+				<Desc>0-Force Start 1-Force Continuation 2-Auto according to the L2CAP packet size</Desc>

+			</Param>

+			<Param type="u" size="2">

+				<Name>ACL Automatically Flushable</Name>

+				<Default>1</Default>

+				<Desc>0=No, 1=Yes.</Desc>

+			</Param>

+			<Param type="u" size="4" valtype="BroadcastTypes">

+				<Name>ACL Broadcast flag</Name>

+				<Default>0</Default>

+				<Desc>0-No broadcast 1-active 2-all</Desc>

+			</Param>

+			<Param type="u" size="4">

+				<Name>L2CAP Payload Size</Name>

+				<Default>1021</Default>

+				<Desc>Packet size in bytes.</Desc>

+			</Param>

+	  </Param>

+	  <Param cond="mode == 0">

+			<Param type="s" size="12" prop="h">

+				<Name></Name>

+			</Param>

+	  </Param>

+		<Param type="R">

+			<Name>DOT_DBG_Response_Event</Name>

+			<Default />

+			<Desc />

+		</Param>

+	</Command>

+

+	<Command name="DOT_Generate_GPS_Data" type="dc" opcode="0x002D">

+		<Param type="u" size="1" prop="h">

+			<Name>Layer</Name>

+			<Value>0xF0</Value>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Opcode</Name>

+			<Value>0x2D</Value>

+			<Desc>GPS data</Desc>

+		</Param>

+		<Param type="u" size="1" prop="h">

+			<Name>Length</Name>

+			<Value>0x0A</Value>

+			</Param>

+		<Param type="u" size="2" label="start">

+			<Name>Start Test</Name>

+			<Default>1</Default>

+			<Desc>0-Stop test,  1-Start test</Desc>

+		</Param>

+		<Param cond="start==1">

+			<Param type="u" size="2">

+				<Name>Min Packet length</Name>

+				<Default>800</Default>

+				<Desc>1-Max packet length in bytes</Desc>

+			</Param>

+			<Param type="u" size="2">

+				<Name>Max Packet length</Name>

+				<Default>2000</Default>

+				<Desc>(bytes)</Desc>

+			</Param>

+			<Param type="u" size="4">

+				<Name>Interval</Name>

+				<Default>1000</Default>

+				<Desc>time in between packets (millisec)</Desc>

+			</Param>

+		</Param>

+		<Param cond="start == 0">

+			<Param type="s" size="8" prop="h">

+				<Name></Name>

+			</Param>

+		</Param>

+		<Param type="R">

+			<Name>DOT_DBG_Response_Event</Name>

+			<Default />

+			<Desc />

+		</Param>

+	</Command>

+

+	<Command name="DOT_Configure_ACL_Buffers" type="dc" opcode="0x002F">

+		<Param type="u" size="1" prop="h">

+			<Name>Layer</Name>

+			<Value>0xF0</Value>

+			</Param>

+		<Param type="u" size="2">

+			<Name>Opcode</Name>

+			<Value>0x2F</Value>

+			<Desc>Configure ACL buffers</Desc>

+		</Param>

+		<Param type="u" size="1" prop="h">

+			<Name>Length</Name>

+			<Value>0x4</Value>

+			</Param>

+        <Param type="u" size="2">

+            <Name>TX Buffer Length</Name>

+            <Default>1021</Default>

+            <Desc>10 to 1021 (default 1021 = 5 buffers)</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>RX Buffer Length</Name>

+            <Default>1021</Default>

+            <Desc>10 to 1021 (default 1021 = 6 buffers)</Desc>

+        </Param>

+		<Param type="R">

+			<Name>DOT_DBG_Response_Event</Name>

+			<Default />

+			<Desc />

+		</Param>

+	</Command>

+

+    <!-- ================================================================== -->

+    <Command name="DOT events" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="DOT_STT_Data_Event" type="DOT_STT_Event" opcode="0x0001">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0x01</Default>

+            <Desc>get statistics string</Desc>

+        </Param>

+        <Param type="s" size="30">

+            <Name>handle</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="30">

+            <Name>TX rate (bit/sec)</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="30">

+            <Name>RX rate (bit/sec)</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="30">

+            <Name>TX packets (Since prv msg)</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="30">

+            <Name>RX packets (Since prv msg)</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="30">

+            <Name>RX ERR packets (Since prv msg)</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="75">

+            <Name>notes</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_STT_Assert_Event" type="DOT_STT_Event" opcode="0x0002">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0x02</Default>

+            <Desc>assert</Desc>

+        </Param>

+        <Param type="s" size="80">

+            <Name>ASSERT</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="80">

+            <Name>File</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Line</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Var</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="87">

+            <Name>File</Name>

+            <Default />

+            <Desc>Fill</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="DOT_DBG_String_Event" type="DOT_Dbg_Event" opcode="0x0001">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0x01</Default>

+            <Desc>get debug string</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>data</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="251">

+            <Name>string</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_DBG_String2_Event" type="DOT_Dbg_Event" opcode="0x0004">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0x04</Default>

+            <Desc>get debug string</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>data</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="11">

+            <Name>string</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_DBG_Assert_Event" type="DOT_Dbg_Event" opcode="0x0002">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0x02</Default>

+            <Desc>assert</Desc>

+        </Param>

+        <Param type="s" size="80">

+            <Name>ASSERT</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="80">

+            <Name>File</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Line</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="4">

+            <Name>Var</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="DOT_DBG_Response_Event" type="DOT_Dbg_Event" opcode="0x0003">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0x03</Default>

+            <Desc>response</Desc>

+        </Param>

+        <Param type="u" size="4" valtype="Status">

+            <Name>Status</Name>

+            <Default>0</Default>

+            <Desc />

+        </Param>

+        <Param type="s" size="80">

+            <Name>      </Name>

+            <Default>any</Default>

+            <Desc />

+        </Param>

+        <Param type="s" size="171">

+            <Name></Name>

+            <Default>any</Default>

+            <Desc>Fill</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="DOT_DBG_Data_Event" type="DOT_Dbg_Event" opcode="0x0005">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0x05</Default>

+            <Desc>get statistics string</Desc>

+        </Param>

+        <Param type="s" size="30">

+            <Name>handle</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="30">

+            <Name>TX rate (bit/sec)</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="30">

+            <Name>RX rate (bit/sec)</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="30">

+            <Name>TX packets (Since prv msg)</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="30">

+            <Name>RX packets (Since prv msg)</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="30">

+            <Name>RX ERR packets (Since prv msg)</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="s" size="75">

+            <Name>notes</Name>

+            <Default />

+            <Desc />

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="Custom Commands" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="Bulk" type="cc">

+        <Param type="x" size="input">

+            <Name>Data</Name>

+            <Default>"00:11:22"</Default>

+            <Desc></Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_SCO_Data" type="cc">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x03</Value>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Handle</Name>

+            <Default>SCO_Handle</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>size(data)</Value>

+            <Desc></Desc>

+        </Param>

+        <Param type="x" size="input" label="data">

+            <Name>SCO Data</Name>

+            <Default>"00:11:22"</Default>

+            <Desc></Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_SCO_Text" type="cc">

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x03</Value>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Handle</Name>

+            <Default>SCO_Handle</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>size(data)</Value>

+            <Desc></Desc>

+        </Param>

+        <Param type="s" size="input" label="data">

+            <Name>SCO Text</Name>

+            <Default>"Hello Bluetooth"</Default>

+            <Desc></Desc>

+        </Param>

+    </Command>

+    

+    <Command name="Bulk_Event" type="ce">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="x" size="input">

+            <Name>Data</Name>

+            <Default>"00:11:22"</Default>

+            <Desc></Desc>

+        </Param>

+    </Command>

+    

+    <Command name="Any_HCI_Event" type="ce">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x04</Value>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Event Type</Name>

+            <Default>Any</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Param Length</Name>

+            <Value>size(data)</Value>

+            <Desc></Desc>

+        </Param>

+        <Param type="x" size="input" label="data">

+            <Name>Parameters</Name>

+            <Default>"00:11:22"</Default>

+            <Desc></Desc>

+        </Param>

+    </Command>

+    

+    <Command name="HCI_SCO_Data_Event" type="ce">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec to wait for the event</Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Layer</Name>

+            <Value>0x03</Value>

+        </Param>

+        <Param type="h" size="2">

+            <Name>Handle</Name>

+            <Default>SCO_Handle</Default>

+            <Desc></Desc>

+        </Param>

+        <Param type="u" size="1" prop="h">

+            <Name>Length</Name>

+            <Value>size(data)</Value>

+            <Desc></Desc>

+        </Param>

+        <Param type="x" size="input" label="data">

+            <Name>SCO Data</Name>

+            <Default>"00:11:22"</Default>

+            <Desc></Desc>

+        </Param>

+    </Command>

+    <!-- ================================================================== -->

+    <Command name="Tester Commands" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="Reconnect">

+    </Command>

+    

+    <Command name="COM_SetParams" type="">

+        <Param type="u" size="4">

+            <Name>Baud Rate</Name>

+            <Default>115200</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Flow Control</Name>

+            <Default>1</Default>

+            <Desc>0=None, 1=HW, 2=Packet Wise, 5=Three Wire</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Alignment Type</Name>

+            <Default>0</Default>

+            <Desc>0=Don't Change, 1=No Alignment, 2=Word, 3=Segment Padding</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="COM_SetSleepType" type="">

+        <Param type="u" valtype="SleepType">

+            <Name>Sleep Type</Name>

+            <Default>1</Default>

+            <Desc>Enable or Disable L2CAP data in HCI_ACL_DATA</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="TCPIP_Connect">

+        <Param type="s">

+            <Name>Address</Name>

+            <Default>"127.0.0.1"</Default>

+            <Desc>Address to connect</Desc>

+        </Param>

+        <Param type="u">

+            <Name>IP Port</Name>

+            <Default>80</Default>

+            <Desc />

+        </Param>

+        <Param type="u" valtype="IPType">

+            <Name>IP Type</Name>

+            <Default>0</Default>

+            <Desc />

+        </Param>

+        <Param type="u" valtype="TrueFalse">

+            <Name>KeepAlive</Name>

+            <Default>True</Default>

+            <Desc>Auto reconnect on disconnect</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="Suspend" type="" />

+    

+    <Command name="Resume" type="" />

+    

+    <Command name="SetSuspendTimeout" type="">

+        <Param type="u" size="4">

+            <Name>Timeout Minimum</Name>

+            <Default>2000</Default>

+            <Desc>Minimum idle time before host requests to sleep</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Timeout Maximum</Name>

+            <Default>0</Default>

+            <Desc>Maximum time for a random timeout. 0 = Uses the Minimum as a fixed value</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="SetAutoSuspend" type="">

+        <Param type="u" size="1">

+            <Name>Enable/Disable</Name>

+            <Default>2000</Default>

+            <Desc>Enable (1) or Disable (0) for automatic suspend and resume</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="SetSuspendState" type="">

+        <Param type="u" size="1">

+            <Name>Sleep or Wakeup</Name>

+            <Default>1</Default>

+            <Desc>Set current state as Sleep (1) or Wakeup (0)</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="EnableHostFlowControl" type="">

+        <Param type="u" size="1">

+            <Name>Enable or Disable</Name>

+            <Default>1</Default>

+            <Desc>0 = Disable, 1 = Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>ACL or SCO</Name>

+            <Default>1</Default>

+            <Desc>1 = ACL, 2 = SCO</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Minimum Packets</Name>

+            <Default>20</Default>

+            <Desc>Minimum count of packets in buffer to send a complete command</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Timeout</Name>

+            <Default>500</Default>

+            <Desc>Time (msec) to wait for minimum packets count to send a complete event</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="SetThreeWireParams" type="">

+        <Param type="u" size="1">

+            <Name>Flow Control</Name>

+            <Default>1</Default>

+            <Desc>0 = None, 1 = Hardware, 2 = Software</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>ACL or SCO</Name>

+            <Default>1</Default>

+            <Desc>1 = ACL, 2 = SCO</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Sliding Window Size</Name>

+            <Default>5</Default>

+            <Desc />

+        </Param>

+        <Param type="u" size="1">

+            <Name>Data Integrity</Name>

+            <Default>1</Default>

+            <Desc>0 = None, 1 = Use</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="ETLM_Select">

+        <Param type="u">

+            <Name>IR Length</Name>

+            <Default>6</Default>

+            <Desc />

+        </Param>

+        <Param type="u">

+            <Name>IR Data</Name>

+            <Default>0x3e</Default>

+            <Desc />

+        </Param>

+        <Param type="u">

+            <Name>DR Length</Name>

+            <Default>5</Default>

+            <Desc />

+        </Param>

+        <Param type="u">

+            <Name>DR Data</Name>

+            <Default>0x10</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="OCP_Read">

+        <Param type="u">

+            <Name>Address</Name>

+            <Default>0x3800</Default>

+            <Desc>JTAG Address</Desc>

+        </Param>

+        <Param type="u">

+            <Name>Bytes Size</Name>

+            <Default>2</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="OCP_Write">

+        <Param type="u">

+            <Name>Address</Name>

+            <Default>0x3800</Default>

+            <Desc>JTAG Address</Desc>

+        </Param>

+        <Param type="u">

+            <Name>Bytes Size</Name>

+            <Default>2</Default>

+            <Desc />

+        </Param>

+        <Param type="u">

+            <Name>Value</Name>

+            <Default>0x0000</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="HardReset">

+        <Param type="u" size="4">

+            <Name>Time</Name>

+            <Default>4000</Default>

+            <Desc>Time in msec to wait until the device is up</Desc>

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="HCITester - Script" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="Sleep" type="">

+        <Param type="u" size="4">

+            <Name>Duration</Name>

+            <Default>1000</Default>

+            <Desc>in milliseconds</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="SetVerbose" type="">

+        <Param type="u" size="1">

+            <Name>Level</Name>

+            <Default>1</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="Logger">

+        <Param type="u">

+            <Name>Level</Name>

+            <Default>7</Default>

+            <Desc>Level of log.</Desc>

+        </Param>

+        <Param type="s">

+            <Name>Text</Name>

+            <Default>"Log this"</Default>

+            <Desc>Formatted text to be logged</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="SetTraceFilter">

+        <Param type="s">

+            <Name>Label</Name>

+            <Default>""</Default>

+            <Desc>Packet type or command name</Desc>

+        </Param>

+        <Param type="u" valtype="TrueFalse">

+            <Name>Enable</Name>

+            <Default>True</Default>

+            <Desc>Sets or removes a trace filter</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="ClearTrace">

+        <Param type="u" valtype="TrueFalse">

+            <Name>NetworkScope</Name>

+            <Default>False</Default>

+            <Desc>Clear trace of all hosts in current network</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="WriteFile">

+        <Param type="s">

+            <Name>File Path</Name>

+            <Default>""</Default>

+            <Desc>Path of the file to be used</Desc>

+        </Param>

+        <Param type="u" valtype="WriteFileType">

+            <Name>Type</Name>

+            <Default>0</Default>

+            <Desc>Create or Append</Desc>

+        </Param>

+        <Param type="s">

+            <Name>Text</Name>

+            <Default>""</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="WaitOtherPort">

+        <Param type="s">

+            <Name>Name</Name>

+            <Default></Default>

+            <Desc>Name of sync point</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Count</Name>

+            <Default>2</Default>

+            <Desc>Total sync points to wait for</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Timeout</Name>

+            <Default>0</Default>

+            <Desc>Time in msec to wait. 0 = infinite</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="WritePort">

+        <Param type="s">

+            <Name>Variable</Name>

+            <Default>VarName</Default>

+            <Desc>Variable name whose contents should be outputted to the port</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="SetParallelPort">

+        <Param type="u" size="2" valtype="ParallelPortOffsets">

+            <Name>Offset</Name>

+            <Default>0</Default>

+            <Desc>Port offset: 0=0x378, 1=0x0379, 2=0x37A</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Data</Name>

+            <Default>0x00</Default>

+            <Desc>Data value to write to the port</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="ReadParallelPort">

+        <Param type="u" valtype="ParallelPortOffsets">

+            <Name>Offset</Name>

+            <Default>0</Default>

+            <Desc>Offset value related to 0x378. LastResult is set with the returned value</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="IgnoreEvent" type="">

+        <Param type="u" size="1" valtype="HCIEvents">

+            <Name>Event Opcode</Name>

+            <Default>0x00</Default>

+        </Param>

+        <Param type="u" size="1" valtype="TrueFalse">

+            <Name>Ignore</Name>

+            <Default>0</Default>

+        </Param>

+    </Command>

+    

+    <Command name="Log" type="">

+        <Param type="s">

+            <Name>Message</Name>

+            <Default>"My Log Message"</Default>

+            <Desc />

+        </Param>

+        <Param type="u">

+            <Name>Param 1</Name>

+        </Param>

+        <Param type="u">

+            <Name>Param 2</Name>

+        </Param>

+        <Param type="u">

+            <Name>Param 3</Name>

+        </Param>

+        <Param type="u">

+            <Name>Param 4</Name>

+        </Param>

+        <Param type="u">

+            <Name>Param 5</Name>

+        </Param>

+    </Command>

+    

+    <Command name="Execute" type="">

+        <Param type="u" valtype="TrueFalse">

+            <Name>Wait</Name>

+            <Default>True</Default>

+            <Desc>Wait until the execution is finished</Desc>

+        </Param>

+        <Param type="s">

+            <Name>Command</Name>

+            <Default>""</Default>

+            <Desc>Path to the file to be executed</Desc>

+        </Param>

+        <Param type="s">

+            <Name>Arguments</Name>

+            <Default>""</Default>

+            <Desc>Command line arguments</Desc>

+        </Param>

+        <Param type="s">

+            <Name>Folder</Name>

+            <Default>""</Default>

+            <Desc>Folder in which the execution will start</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="MsgBox">

+        <Param type="s">

+            <Name>Prompt</Name>

+            <Default>"Hello"</Default>

+            <Desc>Text to be displayed</Desc>

+        </Param>

+        <Param type="u" valtype="MsgBoxType">

+            <Name>Style</Name>

+            <Default>0</Default>

+            <Desc />

+        </Param>

+        <Param type="s">

+            <Name>Title</Name>

+            <Default>"Script"</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="Pause" type="">

+        <Param type="s">

+            <Name>Prompt Message</Name>

+            <Default>"Click OK to continue, Cancel to abort."</Default>

+            <Desc />

+        </Param>

+    </Command>

+    

+    <Command name="Exit" type="" />

+    

+    <Command name="StopScript">

+        <Param type="s">

+            <Name>Text</Name>

+            <Default>"Script failed"</Default>

+            <Desc>Reason</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="Fail">

+        <Param type="s">

+            <Name>Reason</Name>

+            <Default>""</Default>

+            <Desc>Reason of failure</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="WaitForEvent">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Event's Opcode</Name>

+            <Default></Default>

+            <Desc>Value of event's opcode</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="CallFile">

+        <Param type="s">

+            <Name>File Name</Name>

+            <Default></Default>

+            <Desc>Absolute or relative path of the filename</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Parameter</Name>

+            <Default></Default>

+            <Desc>Parameter value to be passed to the filename</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Parameter</Name>

+            <Default></Default>

+            <Desc>Parameter value to be passed to the filename</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Parameter</Name>

+            <Default></Default>

+            <Desc>Parameter value to be passed to the filename</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Parameter</Name>

+            <Default></Default>

+            <Desc>Parameter value to be passed to the filename</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Parameter</Name>

+            <Default></Default>

+            <Desc>Parameter value to be passed to the filename</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Parameter</Name>

+            <Default></Default>

+            <Desc>Parameter value to be passed to the filename</Desc>

+        </Param>

+        <Param type="u" size="4">

+            <Name>Parameter</Name>

+            <Default></Default>

+            <Desc>Parameter value to be passed to the filename</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="LoadFile">

+        <Param type="s">

+            <Name>Variable</Name>

+            <Default>FileData</Default>

+            <Desc>Variable name to get the file contents</Desc>

+        </Param>

+        <Param type="s">

+            <Name>File Path</Name>

+            <Default>"&lt;path&gt;"</Default>

+            <Desc>Absolute or relative path of the filename</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="ClearVariables">

+    </Command>

+    

+    <Command name="CloseAllDocuments">

+    </Command>

+    

+    <Command name="EnableHexDump">

+        <Param type="u" size="1">

+            <Name>Enable Incoming</Name>

+            <Default>0</Default>

+            <Desc>0 = Disable, 1 = Enable</Desc>

+        </Param>

+        <Param type="u" size="1">

+            <Name>Enable Outgoing</Name>

+            <Default>0</Default>

+            <Desc>0 = Disable, 1 = Enable</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="LoadLib">

+        <Param type="s">

+            <Name>Path</Name>

+            <Default>""</Default>

+            <Desc>Path to the XML library</Desc>

+        </Param>

+        <Param type="u" valtype="TrueFalse">

+            <Name>Append</Name>

+            <Default>False</Default>

+            <Desc>True to append new XML to the current one. False to replace it.</Desc>

+        </Param>

+    </Command>

+    

+    <!-- ================================================================== -->

+    <Command name="HCITester - Async Events" type="gb" />

+    <!-- ================================================================== -->

+    

+    <Command name="EnableAsyncEvents">

+        <Param type="u" valtype="TrueFalse">

+            <Name>Enable</Name>

+            <Default>False</Default>

+            <Desc>Enable or disable default state of asynchronous events</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="WaitForAllEvents">

+        <Param type="t">

+            <Name>Timeout</Name>

+            <Default>5000</Default>

+            <Desc>Time in msec</Desc>

+        </Param>

+        <Param type="u" valtype="TrueFalse">

+            <Name>Include Infinite</Name>

+            <Default>True</Default>

+            <Desc>Wait also for pending infinite events to finish</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="ClearAllEvents">

+        <Param type="u" valtype="TrueFalse">

+            <Name>Include Infinite</Name>

+            <Default>True</Default>

+            <Desc>Clear also pending infinite events</Desc>

+        </Param>

+    </Command>

+    

+    <Command name="OnMismatch">

+    </Command>

+    

+    <Command name="OnTimeout">

+    </Command>

+    

+    <Command name="ClearMismatch">

+    </Command>

+    

+    <Command name="ClearTimeout">

+    </Command>

+    

+    <Command name="RestartEvent">

+    </Command>

+    

+    <Command name="Return">

+    </Command>

+    

+

+	<!-- ******************************************************* -->

+	<!-- ******************************************************* -->

+	<!--                                                       	 -->

+	<!-- HCI_LE Event Definition                               	 -->

+	<!--                                                       	 -->

+	<!-- ******************************************************* -->

+	<!-- ******************************************************* -->

+

+	<Command name="Hci_LE_Generic_Report_Event" type="se" opcode="0x003E">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="1" valtype="Hci_LE_Event_Opcode" label="Event_Type">

+			<Name>Event Opcode</Name>

+		</Param>

+

+	<!-- Handle each kind of event -->

+	<!-- LE Connection Created Event -->

+		<Param cond="Event_Type==0x01">

+			<Param type="u" size="1" valtype="Status">

+				<Name>Status</Name>

+				<Default>0x00</Default>

+			</Param>

+			<Param type="u" size="2">

+				<Name>Connection Id</Name>

+			</Param>

+			<Param type="u" size="1" valtype="Role">

+				<Name>Role</Name>

+			</Param>

+			<Param type="u" size="1" valtype="Hci_LE_Address_Type">

+				<Name>Address Type</Name>

+			</Param>

+			<Param type="b" size="6">

+				<Name>Peer Device Address</Name>

+			</Param>

+			<Param type="u" size="2">

+				<Name>Interval</Name>

+			</Param>

+			<Param type="u" size="2">

+				<Name>Latency</Name>

+			</Param>

+			<Param type="u" size="2">

+				<Name>Timeout</Name>

+			</Param>

+			<Param type="u" size="1">

+				<Name>Clock Accuracy</Name>

+			</Param>

+		</Param>

+		

+		<!-- Handle Adv Event  -->

+        <Param cond="Event_Type==0x02">

+			<Param type="u" size="1" label="Count">

+				<Name>Number of Devices</Name>

+				<Default>0x01</Default>

+			</Param>

+			<Param array="Count">

+				<Param type="u" size="1" valtype="Advertising_Event_Type">

+					<Name>Advertising Event Type</Name>

+				</Param>

+				<Param type="u" size="1" valtype="Hci_LE_Address_Type">

+					<Name>Device Address Type</Name>

+				</Param>

+				<Param type="b" size="6">

+					<Name>Device Address</Name>

+				</Param>

+				<Param type="u" size="1" label="DataLength">

+					<Name>Data Length</Name>

+				</Param>

+				<Param type="x" size="DataLength">

+					<Name>Data</Name>

+				</Param>

+				<Param type="d" size="1">

+					<Name>RSSI</Name>

+				</Param>

+			</Param>

+        </Param>

+        

+		<!-- LE LL Connection Parameters Update Complete Event -->

+		<Param cond="Event_Type==0x03">

+			<Param type="u" size="1" valtype="Status">

+				<Name>Status</Name>

+				<Default>0x00</Default>

+			</Param>

+			<Param type="u" size="2">

+				<Name>Connection Id</Name>

+			</Param>

+			<Param type="u" size="2">

+				<Name>Connection Interval</Name>

+			</Param>

+			<Param type="u" size="2">

+				<Name>Connection Latency</Name>

+			</Param>

+			<Param type="u" size="2">

+				<Name>Connection Timeout</Name>

+			</Param>

+		</Param>

+		

+		<!-- LE Read Remote Feature Support Complete Event -->

+		<Param cond="Event_Type==0x04">

+			<Param type="u" size="1" valtype="Status">

+				<Name>Status</Name>

+				<Default>0x00</Default>

+			</Param>

+			<Param type="u" size="2">

+				<Name>Connection Id</Name>

+			</Param>

+			<Param type="x" size="8" prop="r">

+				<Name>Features Set</Name>

+			</Param>

+		</Param>

+		

+		<!-- LE Encryption Request Event -->

+		<Param cond="Event_Type==0x05">

+			<Param type="u" size="2">

+				<Name>Connection Handle</Name>

+			</Param>

+			<Param type="x" size="8" prop="r">

+				<Name>Random Number</Name>

+			</Param>

+			<Param type="u" size="2">

+				<Name>Encrypted Diversifier</Name>

+			</Param>

+		</Param>

+		

+	</Command>

+

+	<!-- ******************************************************* -->

+	<!-- ******************************************************* -->

+	<!--                                                      	 -->

+	<!-- Wibree Groups and Commands                            	 -->

+	<!--                                                      	 -->

+	<!-- ******************************************************* -->

+	<!-- ******************************************************* -->

+

+	<!-- ================================================================== -->

+	<Command name="HCI_LE Radio Setup and Configuration" type="gb" />

+	<!-- ================================================================== -->

+

+	<Command name="HCI_LE_Set_Event_Mask" type="sc" opcode="0x2001">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="8" valtype="Hci_LE_Event_Mask">

+			<Name>Hci_LE Event Mask</Name>

+			<Default>0x1F00000000000000</Default>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+            <Default>0x00</Default>

+			<Desc>0x00 = Command succeeded. 0x01 – 0xFF = Command failed.</Desc>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Read_Buffer_Size" type="vc" opcode="0x2002">

+		<Cat>Wibree</Cat>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+            <Default>0x00</Default>

+			<Desc>Command status</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Data Packet Length</Name>

+			<Desc>Max length of data packets</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>Number of Data Packets</Name>

+			<Desc>Number of Data Packets</Desc>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Read_Local_Feature_Support" type="sc" opcode="0x2003">

+		<Cat>Wibree</Cat>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+           	<Default>0x00</Default>

+			<Desc>0x00 = Command succeeded. 0x01 – 0xFF = Command failed.</Desc>

+		</Param>

+		<Param type="x" size="8" prop="r">

+			<Name>Feature Set</Name>

+			<Desc>LE Controller feature support bit map. This is treated as a parameter in which the LSO is transmitted first.</Desc>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Write_Random_Device_Address" type="sc" opcode="0x2005">

+		<Cat>Wibree</Cat>

+		<Param type="b" size="6">

+			<Name>Local Device Private Address</Name>

+			<Default>"010203040506"</Default>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Default>0x00</Default>

+			<Desc>Command status</Desc>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Read_White_List_Size" type="sc" opcode="0x200F">

+		<Cat>Wibree</Cat>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+            <Default>0x00</Default>

+			<Desc>0x00 = Command succeeded. 0x01 – 0xFF = Command failed.</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>Number of empty entries</Name>

+            <Desc>Number of empty entries in the device address White List in the LE Controller. Range: 0x01 to 0xFF</Desc>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Clear_White_List" type="sc" opcode="0x2010">

+		<Cat>Wibree</Cat>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+                        <Default>0x00</Default>

+			<Desc>0x00 = Command succeeded. 0x01 – 0xFF = Command failed.</Desc>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Add_Device_To_White_List" type="sc" opcode="0x2011">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="1" valtype="Hci_LE_Address_Type">

+			<Name>Device Address Type</Name>

+			<Default>0x00</Default>

+            <Desc>Indicates device address type of the address added to the list. 0x00 = Public address, 0x01 = Random address, 0x02-0xFF = Reserved</Desc>

+		</Param>

+		<Param type="b" size="6">

+			<Name>Device Address</Name>

+			<Default>"010203040506"</Default>

+           	<Desc>Device address that is to be added to the White List.</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+            <Default>0x00</Default>

+			<Desc>0x00 = Command succeeded. 0x01 – 0xFF = Command failed.</Desc>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Remove_Device_From_White_List" type="sc" opcode="0x2012">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="1" valtype="Hci_LE_Address_Type">

+			<Name>Device Address Type</Name>

+			<Default>0x00</Default>

+            <Desc>Indicates device address type of the address added to the list. 0x00 = Public address, 0x01 = Random address, 0x02-0xFF = Reserved</Desc>

+		</Param>

+		<Param type="b" size="6">

+			<Name>Device Address</Name>

+			<Default>"010203040506"</Default>

+            <Desc>Device address that is to be added to the White List.</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+            <Default>0x00</Default>

+			<Desc>0x00 = Command succeeded. 0x01 – 0xFF = Command failed.</Desc>

+		</Param>

+	</Command>

+	

+	<!-- ================================================================== -->

+	<Command name="HCI_LE Device Discovery" type="gb" />

+	<!-- ================================================================== -->

+	<Command name="HCI_LE_Write_Advertising_Parameters" type="sc" opcode="0x2006">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="2">

+			<Name>Advertise Min Interval</Name>

+			<Default>0x0000</Default>

+            <Desc>advIntervalmin = Adv_Interval_Min * 0.625 ms, advIntervalmin range: 20 ms to 10.24 s, Does not apply to connectable directed events.</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Advertise Max Interval</Name>

+			<Default>0x0000</Default>

+            <Desc>advIntervalmax = Adv_Interval * 0.625 ms, advIntervalmax range: 20 ms to 10.24 s, advIntervalmax shall be set to a value equal to or greater than the advIntervalmin Values outside the range are reserved. Does not apply to connectable directed events.</Desc>

+		</Param>

+		<Param type="u" size="1" valtype="Advertising_Type">

+			<Name>Advertising Type</Name>

+			<Default>0x00</Default>

+			<Desc>advIntervalmax = Adv_Interval * 0.625 ms, advIntervalmax range: 20 ms to 10.24 s, advIntervalmax shall be set to a value equal to or greater than the advIntervalmin Values outside the range are reserved. Does not apply to connectable directed events.</Desc>

+		</Param>

+		<Param type="u" size="1" valtype="Hci_LE_Address_Type">

+			<Name>Own_Address_Type</Name>

+			<Default>0x00</Default>

+			<Desc>Public or random device address to use. The default is to use public</Desc>

+		</Param>

+		<Param type="u" size="1" valtype="Hci_LE_Address_Type">

+			<Name>Direct Address Type</Name>

+			<Default>0x00</Default>

+			<Desc>Public or random device address to use.The default is to use public</Desc>

+		</Param>

+		<Param type="b" size="6">

+			<Name>Direct Address</Name>

+			<Default>"010203040506"</Default>

+		</Param>

+		<Param type="u" size="1">

+			<Name>Advertising Channel Map</Name>

+			<Default>7</Default>

+			<Desc>Whcih channels out of 3 Adv channels to be used</Desc>

+		</Param>

+		<Param type="u" size="1" valtype="Advertising_Filter_Policy">

+			<Name>Advertising Filter Policy</Name>

+			<Default>0</Default>

+			<Desc>Advertiser filtering policy to be applied</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Desc>Command status</Desc>

+			<Default>0x00</Default>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Read_Advertising_Channel_TX_Power" type="sc" opcode="0x2007">

+		<Cat>Wibree</Cat>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Desc>Command status</Desc>

+			<Default>0</Default>

+		</Param>

+		<Param type="u" size="1">

+			<Name>Advertising Channel TX Power</Name>

+			<Desc>Transmit power of advertising channel</Desc>

+			<Default>0x00</Default>

+		</Param>

+	</Command>

+

+

+	<Command name="HCI_LE_Write_Advertising_Data" type="sc" opcode="0x2008">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="1">

+			<Name>Data Length</Name>

+			<Default>0x00</Default>

+		</Param>

+		<Param type="x" size="input">

+			<Name>Advertising data</Name>

+			<Default>"000102030405060708090A0B0C0D0E0F"</Default>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Desc>Command status</Desc>

+			<Default>0x00</Default>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Write_Scan_Response_Data" type="sc" opcode="0x2009">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="1" label="Scan_response_Data_Length">

+			<Name>Data Length</Name>

+			<Default>0x0000</Default>

+		</Param>

+		<Param type="x" size="Scan_response_Data_Length">

+			<Name>Data</Name>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Desc>Command status</Desc>

+			<Default>0x00</Default>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Write_Advertise_Enable" type="sc" opcode="0x200A">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="1" valtype="Hci_LE_Start_Stop">

+			<Name>Advertise Mode</Name>

+			<Default>0x00</Default>

+            <Desc>0x01 = On (start advertising), 0x00 = Off (stop advertising), 0x02-0xFF = Reserved</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Desc>Command status</Desc>

+			<Default>0x00</Default>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Write_Scan_Parameters" type="sc" opcode="0x200B">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="1" valtype="Hci_LE_Scan_Mode">

+			<Name>Scan Mode</Name>

+			<Default>0x01</Default>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Scan Interval</Name>

+			<Default>0x0004</Default>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Scan Window</Name>

+			<Default>0x0004</Default>

+		</Param>

+		<Param type="u" size="1" valtype="Hci_LE_Address_Type">

+			<Name>Local Device Address Type</Name>

+			<Default>0x00</Default>

+		</Param>

+		<Param type="u" size="1" valtype="Scanning_Filter_Policy">

+			<Name>Scanning Filter Policy</Name>

+			<Default>0x00</Default>

+			<Desc>0 - Accept all advertisement packets,1 Ignore advertisement packets from devices not in the White List Only</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Desc>Command status</Desc>

+			<Default>0x00</Default>

+		</Param>

+	</Command>

+	

+	<Command name="HCI_LE_Write_Scan_Enable" type="sc" opcode="0x200C">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="1" valtype="Hci_LE_Start_Stop">

+			<Name>Scan Enable</Name>

+			<Default>0x00</Default>

+            <Desc>0x01 = On (start scanning), 0x00 = Off (stop scanning), 0x02-0xFF = Reserved</Desc>

+		</Param>

+		<Param type="u" size="1" valtype="Filter_Duplicates">

+			<Name>Filter Duplicates</Name>

+			<Default>0x01</Default>

+            <Desc>0x0 = Duplicate filtering is disabled, 0x01 = Duplicate filtering is enabled</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+            <Default>0x00</Default>

+			<Desc>0x00 = LE Controller started or stopped scan service successfully. 0x01 – 0xFF = Command failed.</Desc>

+		</Param>

+	</Command>

+

+	

+

+	<!-- ================================================================== -->

+	<Command name="HCI_LE Link Layer Connection Management" type="gb" />

+	<!-- ================================================================== -->

+

+	<Command name="HCI_LE_Create_Connection" type="sc" opcode="0x200D">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="2">

+			<Name>Scan Interval</Name>

+			<Default>0x0004</Default>

+            <Desc>Time between consecutive scans. scanInterval = Scan_Interval * 0.625 ms, scanInterval range: 2.5 ms to 10.24 s, Scan_Interval range: 0x0004 to 0x4000.</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Scan Window</Name>

+			<Default>0x0004</Default>

+            <Desc>Duration of the scan. scanWindow = Scan_Window * 0.625 ms, scanWindow range: 2.5 ms to 10.24 s, Scan_Window range: 0x0004 to 0x4000.</Desc>

+		</Param>

+		<Param type="u" size="1" valtype="Hci_LE_White_List_Ussage">

+			<Name>Initiator_Filter_Policy</Name>

+			<Default>0x0</Default>

+            <Desc> 0x00 = White List not used but the advertiser’s address in this command is used, 0x01 = White List is used and the advertiser’s address in this command is not used, 0x02 – 0xFF = Reserved</Desc>

+		</Param>

+		<Param type="u" size="1" valtype="Hci_LE_Address_Type">

+			<Name>Peer Device Address Type</Name>

+			<Default>0x00</Default>

+            <Desc>Valid only if White_List = 0x00. Indicates address type of the advertiser’s address. 0x00 = Public address, 0x01 = Random address, 0x02 – 0xFF = Reserved.</Desc>

+		</Param>

+		<Param type="b" size="6">

+			<Name>Peer Device Address</Name>

+			<Default>"010203040506"</Default>

+            <Desc>Valid only if White_List = 0x00. Device address of the advertiser to which the connection is to be created. </Desc>

+		</Param>

+		<Param type="u" size="1" valtype="Hci_LE_Address_Type">

+			<Name>Local Device Address Type</Name>

+			<Default>0x00</Default>

+            <Desc>Indicates whether to use own public or private device address. 0x00 = Public address, 0x01 = Random address, 0x02 – 0xFF = Reserved</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Min Connection Interval</Name>

+			<Default>0x0008</Default>

+            <Desc>connIntervalmin = Conn_Interval * 1.25 ms, Conn_Interval_Min range: 0x0006 to 0x0C80.</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Max Connection Interval</Name>

+			<Default>0x0008</Default>

+            <Desc>connIntervalmax = Conn_Interval * 1.25 ms, Conn_Interval_Max range: 0x0006 to 0x0C80, Shall be equal to or greater than the Conn_Interval_Min.</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Connection Latency</Name>

+			<Default>"0x0002"</Default>

+            <Desc>connSlaveLatency = Conn_Latency (as number of LL connection events). Conn_Latency range: 0x0000 to 0x03E8.</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Connection Timeout</Name>

+			<Default>"0x0001"</Default>

+            <Desc>connTimeout = Conn_Timeout * 10 ms Conn_Timeout range: 0x000A to 0x0C80.</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Minimum Length</Name>

+			<Default>0x0000</Default>

+            <Desc>minimum length = Minimum_Length * 0.625 ms, Minimum_Length range: 0x01 to 2*Conn_Interval</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Maximum Length</Name>

+			<Default>0x0000</Default>

+            <Desc>maximum length = Maximum_Length * 0.625 ms, Maximum_Length range: 0x01 to 2*Conn_Interval</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Status_Event</Name>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Create_Connection_Cancel" type="sc" opcode="0x200E">

+		<Cat>Wibree</Cat>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Desc>0x00 = Connection creation stopped. 0x01 – 0xFF = Command failed.</Desc>

+			<Default>0x00</Default>

+		</Param>

+	</Command>

+

+

+	<Command name="HCI_LE_Connection_Update" type="sc" opcode="0x2013">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="2">

+			<Name>Connection Handle</Name>

+			<Default>0x0000</Default>

+            <Desc>Local identifier of the LL connection</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Min Connection Interval</Name>

+			<Default>0x0003</Default>

+            <Desc>connInterval = Conn_Interval * 1.25 ms, Conn_Interval range: 0x0006 to 0x0C80</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Max Connection Interval</Name>

+			<Default>0x0003</Default>

+            <Desc>connIntervalmax = Conn_Interval * 1.25 ms, Conn_Interval_Max range: 0x0006 to 0x0C80, Shall be equal to or greater than the Conn_Interval_Min.</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Connection Latency</Name>

+			<Default>0x0000</Default>

+            <Desc>connSlaveLatency = Conn_Latency (as number of LL connection events). Conn_Latency range: 0x0000 to 0x01F4</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Connection Timeout</Name>

+			<Default>0x0001</Default>

+            <Desc>connTimeout = Conn_Timeout * 10 ms, Conn_Timeout range: 0x000A to 0x0C80</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Minimum Length</Name>

+			<Default>0x0000</Default>

+            <Desc>minimum length = Minimum_Length * 0.625 ms, Minimum_Length range: 0x01 to 2*Conn_Interval</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Maximum Length</Name>

+			<Default>0x0000</Default>

+            <Desc>maximum length = Maximum_Length * 0.625 ms, Maximum_Length range: 0x01 to 2*Conn_Interval</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Status_Event</Name>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Set_Host_Channel_Classification" type="sc" opcode="0x2014">

+		<Cat>Wibree</Cat>

+		<Param type="x" size="5">

+			<Name>BLE Channel Map</Name>

+			<Default>"FFFFFFFF1F"</Default>

+		</Param>

+		<Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+	</Command>

+

+	<Command name="HCI_LE_Read_Channel_Map" type="sc" opcode="0x2015">

+		<Param type="u" size="2">

+			<Name>Handle</Name>

+			<Default>0x0000</Default>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Default>0x00</Default>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Handle</Name>

+			<Default>0x0000</Default>

+		</Param>

+		<Param type="x" size="5">

+			<Name>BLE Channel Map</Name>

+			<Default>"FFFFFFFF1F"</Default>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Read_Remote_Used_Features" type="sc" opcode="0x2016">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="2">

+			<Name>Connection Handle</Name>

+			<Default>0x401</Default>

+			<Desc>Local identifier of the LL connection</Desc>			

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Status_Event</Name>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Default>0x00</Default>

+			<Desc>Command status</Desc>

+		</Param>

+		<Param type="x" size="8" prop="r">

+			<Name>Feature Set</Name>

+			<Desc>Indicates the size of the Feature_Set parameter in octets</Desc>

+		</Param>

+	</Command>

+	

+	<!-- ================================================================== -->

+	<Command name="HCI_LE Security Management" type="gb" />

+	<!-- ================================================================== -->

+	<Command name="HCI_LE_Encrypt" type="sc" opcode="0x2017">

+		<Cat>Wibree</Cat>

+		<Param type="x" size="16" prop="r">

+			<Name>Key</Name>

+			<Default>"05AF519CF0E41E8A0C3C76C0D550A6A9"</Default>

+		</Param>

+		<Param type="x" size="16" prop="r">

+			<Name>Data</Name>

+			<Default>"85B2261C8E840E389868E9EFEA18A27F"</Default>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Default>0x00</Default>

+			<Desc>Command status</Desc>

+		</Param>

+		<Param type="x" size="16" prop="r">

+			<Name>Encrypted Data</Name>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Rand" type="sc" opcode="0x2018">

+		<Cat>Wibree</Cat>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+			<Default>0x00</Default>

+			<Desc>Command status</Desc>

+		</Param>

+		<Param type="x" size="8">

+			<Name>Random Data</Name>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Start_Encryption" type="sc" opcode="0x2019">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="2">

+			<Name>Connection Handle</Name>

+                        <Desc>Local identifier of the LL connection to which the command applies</Desc>

+		</Param>

+		<Param type="u" size="8">

+			<Name>Random</Name> 

+                        <Desc>Random vector used in device identification</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Encrypted Diversifier</Name>

+                        <Desc>Encrypted diversifier</Desc>

+		</Param>

+		<Param type="x" size="16" prop="r">

+			<Name>Long Term Key</Name>

+                        <Desc>Long term key</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Status_Event</Name>

+		</Param>

+	</Command>

+

+	<Command name="HCI_LE_Long_Term_Key_Requested_Reply" type="sc" opcode="0x201A">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="2">

+			<Name>Connection Handle</Name>

+            <Desc>Local identifier of the LL connection to which the command applies</Desc>

+		</Param>

+		<Param type="x" size="16" prop="r">

+			<Name>Key</Name>

+			<Default>"0102030405060708090A0B0C0D0E0F10"</Default>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Connection Handle</Name>

+		</Param>     

+	</Command>

+

+	<Command name="HCI_LE_Long_Term_Key_Requested_Negative_Reply" type="sc" opcode="0x201B">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="2">

+			<Name>Connection Handle</Name>

+            <Desc>Local identifier of the LL connection to which the command applies</Desc>

+		</Param>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+		</Param>

+		<Param type="u" size="2">

+			<Name>Connection Handle</Name>

+		</Param>      

+	</Command>

+

+	<Command name="HCI_LE_Read_Supported_States" type="sc" opcode="0x201C">

+		<Cat>Wibree</Cat>

+		<Param type="R">

+			<Name>HCI_Command_Complete_Event</Name>

+		</Param>

+		<Param type="u" size="1" valtype="Status">

+			<Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+		</Param>

+     	<Param type="u" size="4">

+            <Name>Supported States</Name>

+            <Default>0</Default>

+            <Desc>LE States as defined in spec</Desc>

+        </Param>

+	</Command>

+

+	<!-- ================================================================== -->

+	<Command name="HCI_LE RF Test Mode" type="gb" />

+	<!-- ================================================================== -->

+	

+	<Command name="HCI_BLE_Receiver_Test" type="sc" opcode="0x201D">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="1">

+			<Name>RX Frequency</Name>

+			<Default>0x00</Default>

+			<Desc>Frequency on which the tester sends data</Desc>

+		</Param>

+		<Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+	</Command>

+

+	

+	<Command name="HCI_BLE_Transmitter_Test" type="sc" opcode="0x201E">

+		<Cat>Wibree</Cat>

+		<Param type="u" size="1">

+			<Name>TX Frequency</Name>

+			<Default>0x00</Default>

+			<Desc>Frequency on which the DUT sends data</Desc>

+		</Param>

+		<Param type="u" size="1">

+			<Name>Data Length</Name>

+			<Default>0x00</Default>

+			<Desc>Data Length</Desc>

+		</Param>

+		<Param type="u" size="1" valtype="HCI_LE_Testmode_Packet_Type">

+			<Name>Packet Payload Type</Name>

+			<Default>0</Default>

+			<Desc>Payload type: 0 - PRBS 9, 1 - Pattern 11110000, 2 - Pattern 10101010, 3 - PRBS 15, 4 - All 1, 5 - All 0, 6 - 00001111, 7 - 0101</Desc>

+		</Param>

+		<Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+	</Command>

+

+	<Command name="HCI_BLE_Test_End" type="sc" opcode="0x201F">

+		<Cat>Wibree</Cat>

+		<Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0x00</Default>

+            <Desc>Status</Desc>

+        </Param>

+        <Param type="u" size="2">

+            <Name>Number of packets received</Name>

+            <Default>0</Default>

+            <Desc>Number of packets received.Zero in TX test</Desc>

+        </Param>

+	</Command>

+

+    <!-- ================================================================== -->

+    <Command name="Macroes" type="gb" />

+    <!-- ================================================================== -->

+	<Command name="Reset_Logger" type="vc">

+	<Macro><![CDATA[

+		Execute True, "C:\Program Files\ResetLooger\ResetLooger.exe", "", ""

+  ]]></Macro>

+	</Command>

+	

+    <Command name="Set_IO_Pin_Mux_BTIP" type="sc">

+        

+        <Cat>Spec 1.1</Cat>

+        

+        <Macro><![CDATA[

+		_IO_Pin_Number = %1

+		_Mux_Select = %2

+		_BitShift = _IO_Pin_Number % 4

+		If _BitShift == 0 Then

+			_BitShift = 4

+		End If

+		_BitsToSend = _Mux_Select << 4*(_BitShift-1)

+		_BitsMask   = 15 << 4*(_BitShift-1) 

+		_Pin_Group = (_IO_Pin_Number-1) / 4

+		_Register_Address = 0x1af610 + (_Pin_Group << 1) 

+		log "Pin Number 0x%x", _IO_Pin_Number

+		log "Mux_Select 0x%x", _Mux_Select

+		log "_BitShift 0x%x", _BitShift

+		log "_BitsToSend 0x%x", _BitsToSend

+		log "_BitsMask 0x%x", _BitsMask

+		log "_Pin_Group 0x%x", _Pin_Group

+		log "_Register_Address 0x%x", _Register_Address

+		

+

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, _Register_Address, _BitsToSend, _BitsMask

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+  ]]></Macro>

+        

+        <Param type="u" size="1" label="Pin_Name" valtype="PinName_btip">

+            <Name>Pin Name</Name>

+            <Default>1</Default>

+            <Desc>Select pin to Mux</Desc>

+        </Param>

+        <Param cond="Pin_Name==1">

+            <Param type="u" size="1" valtype="AUD_IN_btip">

+                <Name>AUD_IN Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_IN Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==2">

+            <Param type="u" size="1" valtype="AUD_OUT_btip">

+                <Name>AUD_OUT Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_OUT Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==3">

+            <Param type="u" size="1" valtype="AUD_CLK_btip">

+                <Name>AUD_CLK Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_CLK Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==4">

+            <Param type="u" size="1" valtype="AUD_FSYNC_btip">

+                <Name>AUD_FSYNC Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_FSYNC Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==6">

+            <Param type="u" size="1" valtype="TX_HCI_btip">

+                <Name>TX_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>TX_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==7">

+            <Param type="u" size="1" valtype="RX_HCI_btip">

+                <Name>RX_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>TX_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==8">

+            <Param type="u" size="1" valtype="CTS_HCI_btip">

+                <Name>CTS_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>CTS_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==9">

+            <Param type="u" size="1" valtype="RTS_HCI_btip">

+                <Name>RTS_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>RTS_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==10">

+            <Param type="u" size="1" valtype="BT_FUNC_1_btip">

+                <Name>BT_FUNC_1 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC1 Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==11">

+            <Param type="u" size="1" valtype="BT_FUNC_2_btip">

+                <Name>BT_FUNC_2 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC2 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==12">

+            <Param type="u" size="1" valtype="BT_FUNC_3_btip">

+                <Name>BT_FUNC_3 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC3 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==13">

+            <Param type="u" size="1" valtype="BT_FUNC_4_btip">

+                <Name>BT_FUNC_4 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC4 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==14">

+            <Param type="u" size="1" valtype="BT_FUNC_5_btip">

+                <Name>BT_FUNC_5 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC5 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==15">

+            <Param type="u" size="1" valtype="BT_FUNC_6_btip">

+                <Name>BT_FUNC_1 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC6 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==16">

+            <Param type="u" size="1" valtype="BT_FUNC_7_btip">

+                <Name>BT_FUNC_7 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC1 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==17">

+            <Param type="u" size="1" valtype="BT_FUNC_8_btip">

+                <Name>BT_FUNC_8 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC8 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==18">

+            <Param type="u" size="1" valtype="BT_FUNC_9_btip">

+                <Name>BT_FUNC_1 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC1 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==19">

+            <Param type="u" size="1" valtype="BT_FUNC_10_btip">

+                <Name>BT_FUNC_10 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC10 Pin mux</Desc>

+            </Param>

+        </Param>

+    </Command>

+    

+    <Command name="Set_IO_Pin_Mux_Orca_top" type="sc">

+        

+        <Cat>Spec 1.1</Cat>

+        

+        <Macro><![CDATA[

+		_IO_Pin_Number = %1

+		_Mux_Select = %2

+		_BitShift = ((_IO_Pin_Number-1) % 2) * 8

+		_BitsToSend = _Mux_Select << _BitShift

+		_BitsMask   = 15 << _BitShift

+		_Pin_Group = (_IO_Pin_Number-1) / 2

+		_Register_Address = 0x1a7c80 + (_Pin_Group << 1) 

+		If _Register_Address == 0x1a7c94 Then

+			_Register_Address = 0x1a7c9A

+		End If

+		If _Register_Address == 0x1a7c8e Then

+			_Register_Address = 0x1a7c94

+		End If

+		If _Register_Address == 0x1a7c90 Then

+			_Register_Address = 0x1a7c96

+		End If

+		If _Register_Address == 0x1a7c92 Then

+			_Register_Address = 0x1a7c98

+		End If

+

+		log "Pin Number 0x%x", _IO_Pin_Number

+		log "Mux_Select 0x%x", _Mux_Select

+		log "_BitShift 0x%x", _BitShift

+		log "_BitsToSend 0x%x", _BitsToSend

+		log "_BitsMask 0x%x", _BitsMask

+		log "_Pin_Group 0x%x", _Pin_Group

+		log "_Register_Address 0x%x", _Register_Address

+		

+

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, _Register_Address, _BitsToSend, _BitsMask

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+  ]]></Macro>

+        

+        <Param type="u" size="1" label="Pin_Name" valtype="PinName_orca">

+            <Name>Pin Name</Name>

+            <Default>1</Default>

+            <Desc>Select pin to Mux</Desc>

+        </Param>

+        <Param cond="Pin_Name==1">

+            <Param type="u" size="1" valtype="TX_HCI_orca">

+                <Name>TX_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>TX_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==2">

+            <Param type="u" size="1" valtype="RX_HCI_orca">

+                <Name>RX_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>RX_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==3">

+            <Param type="u" size="1" valtype="CTS_HCI_orca">

+                <Name>CTS_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>CTS_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==4">

+            <Param type="u" size="1" valtype="RTS_HCI_orca">

+                <Name>RTS_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>RTS_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==5">

+            <Param type="u" size="1" valtype="AUD_IN_orca">

+                <Name>AUD_IN Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_IN Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==6">

+            <Param type="u" size="1" valtype="AUD_OUT_orca">

+                <Name>AUD_OUT Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_OUT Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==7">

+            <Param type="u" size="1" valtype="AUD_CLK_orca">

+                <Name>AUD_CLK Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_CLK Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==8">

+            <Param type="u" size="1" valtype="AUD_FSYNC_orca">

+                <Name>AUD_FSYNC Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_FSYNC Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==9">

+            <Param type="u" size="1" valtype="BT_FUNC_1_orca">

+                <Name>BT_FUNC_1 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC1 Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==10">

+            <Param type="u" size="1" valtype="BT_FUNC_2_orca">

+                <Name>BT_FUNC_2 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC2 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==11">

+            <Param type="u" size="1" valtype="TX_DBG_orca">

+                <Name>TX_DBG Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>TX_DBG Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==12">

+            <Param type="u" size="1" valtype="BT_FUNC_4_orca">

+                <Name>BT_FUNC_4 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC4 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==13">

+            <Param type="u" size="1" valtype="BT_FUNC_6_orca">

+                <Name>BT_FUNC_6 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC6 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==14">

+            <Param type="u" size="1" valtype="BT_FUNC_7_orca">

+                <Name>BT_FUNC_7 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC_7 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==15">

+            <Param type="u" size="1" valtype="CLK_REQ_OUT_orca">

+                <Name>CLK_REQ_OUT Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>CLK_REQ_OUT Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==16">

+            <Param type="u" size="1" valtype="FM_IRQ_orca">

+                <Name>FM_IRQ Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FM_IRQ Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==17">

+            <Param type="u" size="1" valtype="FM_SCL_orca">

+                <Name>FM_SCL Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FM_SCL Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==18">

+            <Param type="u" size="1" valtype="FM_SDA_orca">

+                <Name>FM_SDA Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FM_SDA Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==19">

+            <Param type="u" size="1" valtype="FM_I2S_DI_orca">

+                <Name>FM_I2S_DI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FM_I2S_DI Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==20">

+            <Param type="u" size="1" valtype="FM_I2S_DO_orca">

+                <Name>FM_I2S_DO Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FM_I2S_DO Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==21">

+            <Param type="u" size="1" valtype="FM_I2S_CLK_orca">

+                <Name>FM_I2S_CLK Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FM_I2S_CLK Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==22">

+            <Param type="u" size="1" valtype="FM_I2S_WS_orca">

+                <Name>FM_I2S_WS Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FM_I2S_WS Pin mux</Desc>

+            </Param>

+        </Param>

+    </Command>

+       <Command name="Set_IO_Pin_Mux_Quattro_top" type="sc">

+        

+        <Cat>Spec 1.1</Cat>

+        

+        <Macro><![CDATA[

+		_IO_Pin_Number = %1

+		_Mux_Select = %2

+		_BitShift = ((_IO_Pin_Number-1) % 2) * 8

+		_BitsToSend = _Mux_Select << _BitShift

+		_BitsMask   = 15 << _BitShift

+		_Pin_Group = (_IO_Pin_Number-1) / 2

+		_Register_Address = 0x1a7c80 + (_Pin_Group << 1) 

+		If _Register_Address == 0x1a7c92 Then

+			_Register_Address = 0x1a7c94

+		End If

+		If _Register_Address == 0x1a7c9E Then

+			_Register_Address = 0x1a7cA2

+		End If

+		If _Register_Address == 0x1a7cA0 Then

+			_Register_Address = 0x1a7cA2

+		End If

+		log "Pin Number 0x%x", _IO_Pin_Number

+		log "Mux_Select 0x%x", _Mux_Select

+		log "_BitShift 0x%x", _BitShift

+		log "_BitsToSend 0x%x", _BitsToSend

+		log "_BitsMask 0x%x", _BitsMask

+		log "_Pin_Group 0x%x", _Pin_Group

+		log "_Register_Address 0x%x", _Register_Address

+		

+

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, _Register_Address, _BitsToSend, _BitsMask

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+  ]]></Macro>

+        

+        <Param type="u" size="1" label="Pin_Name" valtype="PinName_Quattro">

+            <Name>Pin Name</Name>

+            <Default>1</Default>

+            <Desc>Select pin to Mux</Desc>

+        </Param>

+        <Param cond="Pin_Name==1">

+            <Param type="u" size="1" valtype="TX_HCI_Quattro">

+                <Name>TX_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>TX_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==2">

+            <Param type="u" size="1" valtype="RX_HCI_Quattro">

+                <Name>RX_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>RX_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+        <Param cond="Pin_Name==3">

+            <Param type="u" size="1" valtype="CTS_HCI_Quattro">

+                <Name>CTS_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>CTS_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+		

+        <Param cond="Pin_Name==4">

+            <Param type="u" size="1" valtype="RTS_HCI_Quattro">

+                <Name>RTS_HCI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>RTS_HCI Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==5">

+            <Param type="u" size="1" valtype="AUD_IN_Quattro">

+                <Name>AUD_IN Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_IN Pin mux</Desc>

+            </Param>

+        </Param>

+		

+        <Param cond="Pin_Name==6">

+            <Param type="u" size="1" valtype="AUD_OUT_Quattro">

+                <Name>AUD_OUT Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_OUT Pin mux</Desc>

+            </Param>

+        </Param>

+		

+        <Param cond="Pin_Name==7">

+            <Param type="u" size="1" valtype="AUD_CLK_Quattro">

+                <Name>AUD_CLK Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_CLK Pin mux</Desc>

+            </Param>

+        </Param>

+		

+        <Param cond="Pin_Name==8">

+            <Param type="u" size="1" valtype="AUD_FSYNC_Quattro">

+                <Name>AUD_FSYNC Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>AUD_FSYNC Pin mux</Desc>

+            </Param>

+        </Param>

+		

+        <Param cond="Pin_Name==9">

+            <Param type="u" size="1" valtype="BT_FUNC_1_Quattro">

+                <Name>BT_FUNC_1 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC_1 Pin mux</Desc>

+            </Param>

+        </Param>

+		

+        <Param cond="Pin_Name==10">

+            <Param type="u" size="1" valtype="BT_FUNC_2_Quattro">

+                <Name>BT_FUNC_2 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC_2 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==11">

+            <Param type="u" size="1" valtype="BT_FUNC_5_Quattro">

+                <Name>BT_FUNC_5 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC_5 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==12">

+            <Param type="u" size="1" valtype="BT_FUNC_3_Quattro">

+                <Name>BT_FUNC_3 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC_3 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==13">

+            <Param type="u" size="1" valtype="BT_FUNC_6_Quattro">

+                <Name>BT_FUNC_6 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC_6 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==14">

+            <Param type="u" size="1" valtype="BT_FUNC_7_Quattro">

+                <Name>BT_FUNC_7 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>BT_FUNC_7 Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==15">

+            <Param type="u" size="1" valtype="SB_DATA_Quattro">

+                <Name>SB_DATA Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>SB_DATA Pin mux</Desc>

+            </Param>

+        </Param>

+		

+        <Param cond="Pin_Name==16">

+            <Param type="u" size="1" valtype="SB_CLK_Quattro">

+                <Name>CSB_CLK Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>SB_CLK Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==17">

+            <Param type="u" size="1" valtype="WL_TX_Quattro">

+                <Name>WL_TX Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_TX Pin mux</Desc>

+            </Param>

+        </Param>

+        

+        <Param cond="Pin_Name==18">

+            <Param type="u" size="1" valtype="WL_RX_Quattro">

+                <Name>WL_RX Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_RX Pin mux</Desc>

+            </Param>

+        </Param>

+		

+		<Param cond="Pin_Name==21">

+            <Param type="u" size="1" valtype="FREF_CLK_REQ_Quattro">

+                <Name>FREF_CLK_REQ Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FREF_CLK_REQ Pin mux</Desc>

+            </Param>

+        </Param>

+		

+        <Param cond="Pin_Name==25">

+            <Param type="u" size="1" valtype="FM_I2S_DI_Quattro">

+                <Name>FM_I2S_DI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FM_I2S_DI Pin mux</Desc>

+            </Param>

+        </Param>

+		

+        <Param cond="Pin_Name==26">

+            <Param type="u" size="1" valtype="FM_I2S_DO_Quattro">

+                <Name>FM_I2S_DO Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FM_I2S_DO Pin mux</Desc>

+            </Param>

+        </Param>

+		

+        <Param cond="Pin_Name==27">

+            <Param type="u" size="1" valtype="FM_I2S_CLK_Quattro">

+                <Name>FM_I2S_CLK Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FM_I2S_CLK Pin mux</Desc>

+            </Param>

+        </Param>

+		

+        <Param cond="Pin_Name==28">

+            <Param type="u" size="1" valtype="FM_I2S_WS_Quattro">

+                <Name>FM_I2S_WS Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>FM_I2S_WS Pin mux</Desc>

+            </Param>

+        </Param>

+		

+		<Param cond="Pin_Name==30">

+            <Param type="u" size="1" valtype="SPI_CSX_Quattro">

+                <Name>SPI_CSX Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>SPI_CSX Pin mux</Desc>

+            </Param>

+        </Param>

+		

+		<Param cond="Pin_Name==35">

+            <Param type="u" size="1" valtype="WLAN_IRQ_Quattro">

+                <Name>WLAN_IRQ Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WLAN_IRQ Pin mux</Desc>

+            </Param>

+        </Param>

+		

+		<Param cond="Pin_Name==36">

+            <Param type="u" size="1" valtype="WL_UART_DBG_Quattro">

+                <Name>WL_UART_DBG Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_UART_DBG Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==37">

+            <Param type="u" size="1" valtype="WL_PAEN_A_Quattro">

+                <Name>WL_PAEN_A Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_PAEN_A Pin mux</Desc>

+            </Param>

+        </Param>

+	

+		<Param cond="Pin_Name==38">

+            <Param type="u" size="1" valtype="WL_PAEN_B_Quattro">

+                <Name>WL_PAEN_B Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_PAEN_B Pin mux</Desc>

+            </Param>

+        </Param>

+		

+		<Param cond="Pin_Name==39">

+            <Param type="u" size="1" valtype="WL_BTH_SW_Quattro">

+                <Name>WL_BTH_SW Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_BTH_SW Pin mux</Desc>

+            </Param>

+        </Param>

+		     

+		 <Param cond="Pin_Name==40">

+            <Param type="u" size="1" valtype="WL_EXT_LNA_EN_Quattro">

+                <Name>WL_EXT_LNA_EN Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_EXT_LNA_EN Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==41">

+            <Param type="u" size="1" valtype="WL_RS232_RX_Quattro">

+                <Name>WL_RS232_RX Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_RS232_RX Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==42">

+            <Param type="u" size="1" valtype="WL_RS232_TX_Quattro">

+                <Name>WL_RS232_TX Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_RS232_TX Pin mux</Desc>

+            </Param>

+        </Param>

+	

+		<Param cond="Pin_Name==43">

+            <Param type="u" size="1" valtype="JTAG_TCK_Quattro">

+                <Name>JTAG_TCK Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>JTAG_TCK Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==44">

+            <Param type="u" size="1" valtype="JTAG_TMS_Quattro">

+                <Name>JTAG_TMS Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>JTAG_TMS Pin mux</Desc>

+            </Param>

+        </Param>

+	

+		<Param cond="Pin_Name==45">

+            <Param type="u" size="1" valtype="JTAG_TDI_Quattro">

+                <Name>JTAG_TDI Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>JTAG_TDI Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==46">

+            <Param type="u" size="1" valtype="JTAG_TDO_Quattro">

+                <Name>JTAG_TDO Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>JTAG_TDO Pin mux</Desc>

+            </Param>

+        </Param>

+		

+		<Param cond="Pin_Name==47">

+            <Param type="u" size="1" valtype="GPS_UART_TX_Quattro">

+                <Name>GPS_UART_TX Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>GPS_UART_TX Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==48">

+            <Param type="u" size="1" valtype="GPS_UART_RX_Quattro">

+                <Name>GPS_UART_RX Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>GPS_UART_RX Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==49">

+            <Param type="u" size="1" valtype="GPS_SENS_I2C_SCL_Quattro">

+                <Name>GPS_SENS_I2C_SCL Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>GPS_SENS_I2C_SCL Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==50">

+            <Param type="u" size="1" valtype="GPS_SENS_I2C_SDA_Quattro">

+                <Name>GPS_SENS_I2C_SDA Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>GPS_SENS_I2C_SDA Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==51">

+            <Param type="u" size="1" valtype="TESTMODE_Quattro">

+                <Name>TESTMODE Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>TESTMODE Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==52">

+            <Param type="u" size="1" valtype="TCXO_CLK_REQ_Quattro">

+                <Name>TCXO_CLK_REQ Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>TCXO_CLK_REQ Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==53">

+            <Param type="u" size="1" valtype="GPS_IRQ_Quattro">

+                <Name>GPS_IRQ Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>GPS_IRQ Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==54">

+            <Param type="u" size="1" valtype="GPS_TIMESTAMP_Quattro">

+                <Name>GPS_TIMESTAMP Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>GPS_TIMESTAMP Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==55">

+            <Param type="u" size="1" valtype="GPS_PPS_OUT_Quattro">

+                <Name>GPS_PPS_OUT Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>GPS_PPS_OUT Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==56">

+            <Param type="u" size="1" valtype="GPS_I2C_UART_SELECT_Quattro">

+                <Name>GPS_I2C_UART_SELECT Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>GPS_I2C_UART_SELECT Pin mux</Desc>

+            </Param>

+        </Param>			

+

+		<Param cond="Pin_Name==57">

+            <Param type="u" size="1" valtype="GPS_EXT_LNA_EN_Quattro">

+                <Name>GPS_EXT_LNA_EN Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>GPS_EXT_LNA_EN Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==58">

+            <Param type="u" size="1" valtype="GPS_PA_EN_Quattro">

+                <Name>GPS_PA_EN Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>GPS_PA_EN Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==59">

+            <Param type="u" size="1" valtype="DC2DC_MODE_Quattro">

+                <Name>DC2DC_MODE Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>DC2DC_MODE Pin mux</Desc>

+        </Param>

+        </Param>

+

+		<Param cond="Pin_Name==60">

+            <Param type="u" size="1" valtype="TCXO_SLI_OUT_Quattro">

+                <Name>TCXO_SLI_OUT Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>TCXO_SLI_OUT Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==61">

+            <Param type="u" size="1" valtype="WL_SPI_DIN_Quattro">

+                <Name>WL_SPI_DIN Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_SPI_DIN Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==62">

+            <Param type="u" size="1" valtype="WL_SPI_DOUT_Quattro">

+                <Name>WL_SPI_DOUT Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_SPI_DOUT Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==63">

+            <Param type="u" size="1" valtype="WL_SDIO_D1_Quattro">

+                <Name>WL_SDIO_D1 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_SDIO_D1 Pin mux</Desc>

+            </Param>

+        </Param>

+

+		<Param cond="Pin_Name==64">

+            <Param type="u" size="1" valtype="WL_SDIO_D2_Quattro">

+                <Name>WL_SDIO_D2 Pin mux</Name>

+                <Default>0x00</Default>

+                <Desc>WL_SDIO_D2 Pin mux</Desc>

+            </Param>

+		</Param>

+    </Command>

+	

+    <Command name="GCM_MUX_SIGNAL" type="cc">

+        <Cat>Spec 1.1</Cat>

+        

+        <Macro><![CDATA[

+		_gcm_signal_number = %1

+		_pin_id = %2

+

+		log "_gcm_signal_number %d", _gcm_signal_number

+		log "_pin_id %d", _pin_id

+		

+		# Select GCM signals

+		############################ 

+

+	

+		

+		# Write to TEST SELECT REGISTER: 

+		# DRX is muxed out 

+		

+		# Generate TEST_SELECT_Register

+		#value = _test_clk_mux_sel & 0xf

+		#value = ((_dtst_mux_sel & 0xf) << 4) ^ value

+		#value = ((_test_clock_invert & 0x1) << 8) ^ value

+		#value = ((_inter_sel & 0xf) << 9) ^ value

+		#value = ((_lsb_sel & 0x1) << 13) ^ value

+		#value = ((_shl_sel & 0x1f) << 14) ^ value

+		

+		#Send_HCI_VS_DRP_Write_Register 0xFD2A, 0x804, value

+		#Wait_HCI_Command_Complete_VS_DRP_Write_Register_Event 5000, any, HCI_VS_DRP_Write_Register, 0x00

+	

+		#debug bus enable

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A3002, 0x0004, 0x0004

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		#enable test bus clock in gcm

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A6010, 0x0020, 0x0020

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+	

+		If (_pin_id == 1) Then

+		#put selected signal on selected dbg pin

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A604c, _gcm_signal_number, 0x003f

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#select dbg pin from gcm and not from soc

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A605e, 0x0001, 0x0001

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		End If

+

+		If (_pin_id == 2) Then

+		_gcm_signal_number_=_gcm_signal_number<<8

+		#put selected signal on selected dbg pin

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A604c,  _gcm_signal_number_,0x3f00

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#select dbg pin from gcm and not from soc

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A605e, 0x0002, 0x0002

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		End If

+		

+		If (_pin_id == 3) Then

+		#put selected signal on selected dbg pin

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A604e, _gcm_signal_number,0x003f

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#select dbg pin from gcm and not from soc

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A605e, 0x0004, 0x0004

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		End If

+

+		If (_pin_id == 4) Then

+		_gcm_signal_number_=_gcm_signal_number<<8

+		#put selected signal on selected dbg pin

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A604e, _gcm_signal_number_,0x3f00

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#select dbg pin from gcm and not from soc

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A605e, 0x0008, 0x0008

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		End If

+

+		If (_pin_id == 5) Then

+		#put selected signal on selected dbg pin

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A6050, _gcm_signal_number,0x003f

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#select dbg pin from gcm and not from soc

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A605e, 0x0010, 0x0010

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		End If

+

+		If (_pin_id == 6) Then

+		_gcm_signal_number_=_gcm_signal_number<<8

+		#put selected signal on selected dbg pin

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A6050, _gcm_signal_number_,0x3f00

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#select dbg pin from gcm and not from soc

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A605e, 0x0020, 0x0020

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		End If

+

+		If (_pin_id == 7) Then

+		#put selected signal on selected dbg pin

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A6052, _gcm_signal_number,0x003f

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#select dbg pin from gcm and not from soc

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A605e, 0x0040, 0x0040

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		End If

+

+		If (_pin_id == 8) Then

+		_gcm_signal_number_=_gcm_signal_number<<8

+		#put selected signal on selected dbg pin

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A6052, _gcm_signal_number_,0x3f00

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#select dbg pin from gcm and not from soc

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A605e, 0x0080, 0x0080

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		End If

+

+		If (_pin_id == 9) Then

+		#put selected signal on selected dbg pin

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A6054, _gcm_signal_number,0x003f

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#select dbg pin from gcm and not from soc

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A605e, 0x0100, 0x0100

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		End If

+

+		If (_pin_id == 10) Then

+		_gcm_signal_number_=_gcm_signal_number<<8

+		#put selected signal on selected dbg pin

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A6054, _gcm_signal_number_,0x3f00

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#select dbg pin from gcm and not from soc

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A605e, 0x0200, 0x0200

+	    Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		End If

+

+	

+

+  	]]></Macro>

+        

+        <Param type="u" size="1" valtype="GCMSignalList">

+            <Name>GCM signal select</Name>

+            <Default>0x00</Default>

+            <Desc>1-Selects the output clock on test_clk output</Desc>

+        </Param>

+        <Param type="u" size="1" valtype="SetTestMuxPinNumber">

+            <Name>DBG pin number</Name>

+            <Default>0x01</Default>

+            <Desc>Selects the outputs to be muxed on the test output</Desc>

+        </Param>

+    </Command>

+   <!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+	<!--  DTST Muxing		                                       --> 

+	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+ <Command name="DRP_Mux_DTST" type="cc">

+  <Cat>Spec 1.1</Cat> 

+<Macro>

+<![CDATA[ 

+		_test_mux_Signal_sel= %1

+		_dtst_Module_sel = %2

+		_shift_select= %3

+		_test_clk_mux_sel = %4

+		_test_dtst_enable = %5

+		_test_mirror_enable = %6

+		_test_apll_clk_select = %7

+		_TestBusOverrideSelect = %8

+		_TestBusOverrideValue = %9

+        _test_pins_group_select = %10

+

+		

+		# Dont Set config module settings

+		############################ 

+

+		#BTIP Configu module configuraton

+		#Send_HCIPP_Set_IO_Pin_Mux_BTIP 0x01, 0x07

+

+		

+		# Set debug module settings 

+		########################### 

+	

+		# Write to TEST SELECT REGISTER: 

+		# DRX is muxed out 

+

+		# DBG(9:5)

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A300C, 0x0000

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+

+		# DBG(4:0)

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A300A, 0x0000

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+

+		# DBG(15:0) enable

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A3002, 0x0004

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+

+		#**************************************************************************#

+		sleep 100

+		#**************************************************************************#

+		#BTIP AOD module (GCM level) configuration(10 lsb's the other 7 by pass this module )

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A605c, 0x0000

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		#**************************************************************************#

+		sleep 100

+		#**************************************************************************#

+		

+		

+		#-- Reading DMEM indication for PLATFORM type

+		Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x0019315A

+		Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &Platform

+		

+		if(Platform == 0 ) then  

+			

+		#ORCA Top level configuration (Output Connector Pins ) 

+		

+

+		# ORCA TOP_CONFIG

+		# MUX DBG(15:0) & DBG_CLK on ORCA primary pins

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C82, 0x0707

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C84, 0x0707

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C86, 0x0707

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C88, 0x0707

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C8A, 0x0007

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C94, 0x0707

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C96, 0x0707

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C98, 0x0707

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C9A, 0x0707

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C9C, 0x1600

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		

+		# configure CLK_REQ_OUT to be output & without pu/pd

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C7E, 0x002F

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		

+		# configure FM_SCL and FM_SDA NMODE

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7CAA, 0x000F

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+		endif

+		if(Platform == 1 ) then  

+			

+				#Trio Top level configuration (Output Connector Pins ) 

+				Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d06, 0x0001, 0x0001

+				Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+				

+				# Trio TOP_CONFIG

+				# MUX DBG(15:0) & DBG_CLK on ORCA primary pins

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C82, 0x0003

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+				

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C84, 0x0303

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+				

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C86, 0x0300

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+				

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C88, 0x0303

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+				

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C94, 0x0303

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+				

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C96, 0x0303

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+				

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C98, 0x0303

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+				

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C9A, 0x0303

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+				

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7C9C, 0x0300

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+				

+				

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7CbE, 0x0303

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+				

+				

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7d08, 0x0000

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+				

+				

+				Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7d0a, 0x0100

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+					

+		endif

+		if(Platform == 2) then	

+

+				#NL5500 Top level configuration (Output Connector Pins ) 

+				

+		

+				if _test_pins_group_select == 0 then

+      		# Use the following commands when you want to debug on I\O pins

+		

+      		# change mode of top pins to mode 3

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d30, 0x0303, 0x0707

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d38, 0x0003, 0x0007

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d3e, 0x0300, 0x0700

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d44, 0x0303, 0x0707

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d46, 0x0303, 0x0707

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d48, 0x0303, 0x0707

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d4c, 0x0303, 0x0707

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d32, 0x0303, 0x0707

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d50, 0x0303, 0x0707

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d4e, 0x0300, 0x0700

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d52, 0x0003, 0x0007

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x1A7d82, 0x0F00, 0x0F00

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		

+    		else

+      		# Use the following commands when you want to debug on external mem pins

+      		#change mode of ext.mem top pins to 6 - to enable BT debug bus on mem_data bus + mem_clk

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d54, 0x0600, 0x0700

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d56, 0x0006, 0x0007

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+      		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7d58, 0x0006, 0x0007

+      		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+    		end if

+		endif	

+		if(Platform == 3) then	

+			# Napoleon-Pinmux Top Configuration:

+

+			#EMIF_CLK DEBUG0

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D22, 0x0007

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			#EMIF_D0_D1 DEBUG1 DEBUG2

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D24, 0x0707

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			#EMIF_D2 DEBUG3

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D26, 0x0700

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			#SPI_CLK DEBUG4

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D28, 0x0700

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			#SPI_DAT1 DEBUG5

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D2A, 0x0700

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			#GPIO0_1 DEBUG6 DEBUG7

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D30, 0x0707

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			#GPIO2_3 DEBUG8 DEBUG9

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D32, 0x0707

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			#GPIO_5 DEBUG10

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D34, 0x0700

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			#GPIO_6 DEBUG11

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D36, 0x0007

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			#AUDIO0_CLK_SYNC DEBUG12 DEBUG13

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D2C, 0x0707

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			#AUDIO1_DI_D0 DEBUG 14 DEBUG15

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D2E, 0x0707

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			#GPIO4_5  DEVUG_CLK

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1A7D34, 0x0007

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		endif

+		if(platform == 4) then

+		# Quattro-Pinmux Configuration:

+

+			# Enable using SPI_CSX for debug.      Quattro-Shared Register: PINMUX_CONFIG

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7D06, 0x0001, 0x0001

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Enable input broadcast for debug.    Quattro-Shared Register: PINMUX_CONFIG

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7D06, 0x0020, 0x0020

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring SPI_CSX Pad.             Quattro-Shared Register: SPI_CSX_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7C9C, 0x0500, 0x0700

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring SDIO_D1 Pad.             Quattro-Shared Register: SDIO_D1_D2_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CBE, 0x0005, 0x0007

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring SDIO_D2 Pad.             Quattro-Shared Register: SDIO_D1_D2_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CBE, 0x0500, 0x0700

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring WLAN_IRQ Pad.            Quattro-Shared Register: WL_IRQ_UARTDBG_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CA2, 0x0005, 0x0007

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring WL_PAEN_B Pad.           Quattro-Shared Register: WL_PAEN_A_B_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CA4, 0x0500, 0x0700

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring WL_RS232_Tx Pad.         Quattro-Shared Register: WL_RS232_RX_TX_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CA8, 0x0500, 0x0700

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring WL_RS232_Rx Pad.         Quattro-Shared Register: WL_RS232_RX_TX_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CA8, 0x0005, 0x0007

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring HCI_CTS Pad.             Quattro-Shared Register: HCI_CTS_RTS_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7C82, 0x0005, 0x0007

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring JTAG_TDO Pad.            Quattro-Shared Register: JTAG_TDI_TDO_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CAC, 0x0500, 0x0700

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring JTAG_TDI Pad.            Quattro-Shared Register: JTAG_TDI_TDO_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CAC, 0x0005, 0x0007

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring SB_CLK Pad.              Quattro-Shared Register: SB_DATA_CLK_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7C8E, 0x0500, 0x0700

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring GPS_SENS_I2C_SDA Pad.    Quattro-Shared Register: GPS_SENS_I2C_SCL_SDA_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CB0, 0x0500, 0x0700

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring GPS_UART_TX Pad.         Quattro-Shared Register: GPS_UART_TX_RX_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CAE, 0x0005, 0x0007

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring GPS_TIMESTAMP Pad.       Quattro-Shared Register: GPS_IRQ_TIMESTAMP_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CB4, 0x0500, 0x0700

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring GPS_PA_EN Pad.           Quattro-Shared Register: GPS_EXT_LNA_EN_PA_EN_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CB8, 0x0500, 0x0700

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring GPS_EXT_LNA_EN Pad.      Quattro-Shared Register: GPS_EXT_LNA_EN_PA_EN_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CB8, 0x0005, 0x0007

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+			# Configuring GPS_IRQ Pad.             Quattro-Shared Register: GPS_IRQ_TIMESTAMP_SEL

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7CB4, 0x0005, 0x0007

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+

+

+			# =========================================================================

+			# Top-Level Second Level Multiplexors Configuration:

+

+			# Configure Bits [15: 0].              Quattro-Shared Register: TOP_DEBUG_PORT_SEL_1

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7D08, 0x0000

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+

+			# Configure Bits [23:16] + Clock.      Quattro-Shared Register: TOP_DEBUG_PORT_SEL_2

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7D0A, 0x0000

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+

+

+			# =========================================================================

+	endif

+		

+

+		#******************* DRP DTST REG CONFIG  *******************************************************#

+		

+		#Clear dtst En 

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, 0<<4, 0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		# WRITE test_mux_Signal_sel to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204, _test_mux_Signal_sel, 0x00ff

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _dtst_Module_sel to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204, _dtst_Module_sel<<8, 0x0700

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _shift_select to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204, _shift_select<<12, 0xf000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _test_clk_mux_sel to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_clk_mux_sel, 0x000f

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _test_mirror_enable to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_mirror_enable<<8, 0x0100

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _test_apll_clk_select to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_apll_clk_select<<12, 0x1000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+	

+

+	

+		log "test_dtst_enable %d", _test_dtst_enable

+		if _test_dtst_enable > 0 then

+

+		# WRITE _test_dtst_enable to	DTST_CTRL Register

+		#		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, 0x1B, 0x001f

+		#		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE DTST Enable to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_dtst_enable<<4, 0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _test_apll_clk_select to	DTST_CTRL Register

+		end if

+		

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,0, 0x0001

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+	

+		if _test_clk_mux_sel > 3 & _test_clk_mux_sel < 7 then 

+		# WRITE _test_mirror_enable to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,1, 0x0001

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+	    else

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,0, 0x0001

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		end if 

+		log "test_dtst_enable %d", _test_dtst_enable

+		

+		#******************* DRP DTST REG CONFIG END  *******************************************************#

+			

+		#******************* DRP DTST Bus Override   *******************************************************#

+		# WRITE TestBusOverrideSelect to Register

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021e, _TestBusOverrideSelect

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+

+		# WRITE TestBusOverrideValue to	 Register

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021c, _TestBusOverrideValue

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+

+		if _TestBusOverrideSelect > 0 then

+		# WRITE _test_mirror_enable to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190102, 1<<12, 0x1000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _test_apll_clk_select to	DTST_CTRL Register

+		end if

+	#******************* DRP DTST Bus Override End  *******************************************************#

+  	]]> 

+  	</Macro>

+ 	<Param type="u" size="1">

+  	<Name>Signal_sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>1-Selects the signals to Mux </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="4" valtype="dtst_Module_sel">

+  	<Name>Module_sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects the DRP Module </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="4" valtype="shift_select">

+  	<Name>shift_select</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>0 - Select Number of bits to mux </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="4" valtype="test_clk_mux_sel">

+  	<Name>test_clk_mux_sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects the output clock on test_clk output</Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="test_dtst_enable">

+  	<Name>test_dtst_enable</Name> 

+  	<Default>1</Default> 

+  	<Desc>0 - Enable\Disable DTST</Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="test_mirror_enable">

+  	<Name>test_mirror_enable</Name> 

+  	<Default>0</Default> 

+  	<Desc>0 - Enable Mirrore </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="test_apll_clk_select">

+  	<Name>test_apll_clk_select</Name> 

+  	<Default>0</Default> 

+  	</Param>

+ 	<Param type="u" size="1" bits="2" valtype="TestBusOverrideSelect">

+  	<Name>TestBusOverrideSelect</Name> 

+  	<Default>0</Default> 

+  	</Param>

+  	<Values name="TestBusOverrideValue" type="enum">

+  	</Values>	

+	<Param type="u" size="1">

+  	<Name>TestBusOverrideValue</Name> 

+  	<Default>0x0000</Default> 

+  	<Desc>1-Enter TestBusOverrideValue </Desc> 

+  	</Param>

+   <Param type="u" size="1" bits="1" valtype="pins_group_select">

+     <Name>pins_group_select</Name>

+     <Default>0x00</Default>

+     <Desc>0 - Select between IO pins and External Memory pins works only for NL5500 </Desc>

+   </Param>

+  	</Command>  

+  	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+	<!--  Read DTST Memory		                                       --> 

+	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+<Command name="DRP_DTST_Memory_Read" type="cc">

+  <Cat>Spec 1.1</Cat> 

+<Macro>

+<![CDATA[ 

+

+		_DTST_Mem_Max_Use 				= %1

+		_DTST_filename					= %2

+		

+		

+		Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x00190218

+		Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &DtstParamL

+		Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x0019021a

+		Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &DtstParamM

+		Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x00190210

+		Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &DtstMemCtrl

+		Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x00190206

+		Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &DtstCtrl	

+		Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x00190214

+		Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &saveddtst

+	

+   

+		# Configure memory for dump

+#************************************************************************************************************#		

+

+		clk_select=0x0b

+FileName1	= _DTST_filename

+		   

+		    # WRITE _test_clk_mux_sel to	DTST_CTRL Register

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, clk_select, 0x000f

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+Sleep 1

+		    # config  _DTST_Mem_Mode=2 

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, 2<<2, 0x000c

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+			#Read Stop_Address

+			Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x00190224

+			Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &stp_addr

+			#pause "stop adr = %d",stp_addr

+			

+			#DTST_MEM_OCP_PARAMS - write start_address

+			Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190216, stp_addr+1

+			Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+			# config  _DTST_Mem_Enable=1

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, 1, 0x0001

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+			# WRITE DTST Enable to	DTST_CTRL Register

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, 1<<4, 0x0010

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+			# config  _DTST_Mem_Addr_Load =1 

+			Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, 0x0001<<4, 0x0010

+			Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+			sleep 10 

+			

+			

+

+		#save results to file

+		WriteFile FileName1, 0, ""

+

+# read 1st block - from stp_addr+1 to buffer_end

+block_size = (DTST_Mem_Max_Use-stp_addr-1)*4

+While (block_size>0)

+	chunk_size = Min(block_size,200)

+	Send_HCI_VS_Read_Memory_Block_From_DTST 0xFD7F, 0x00190200, chunk_size

+	Wait_HCI_Command_Complete_VS_Read_Memory_Block_From_DTST_Event 5000, any, HCI_VS_Read_Memory_Block_From_DTST, 0x00, &mydata

+	WriteFile FileName1, 1, StrData(mydata)	

+	WriteFile FileName1, 1, "\n"

+	block_size-=chunk_size

+Wend

+		

+# Reset start address

+				#DTST_MEM_OCP_PARAMS - write start_address

+Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190216, 0

+				Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+				# config  _DTST_Mem_Addr_Load =1 

+				Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, 0x0001<<4, 0x0010

+				Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+				

+# read 2st block - from buffer_start to stp_addr

+block_size = (stp_addr+1)*4

+While (block_size>0)

+	chunk_size = Min(block_size,200)

+	Send_HCI_VS_Read_Memory_Block_From_DTST 0xFD7F, 0x00190200, chunk_size

+	Wait_HCI_Command_Complete_VS_Read_Memory_Block_From_DTST_Event 5000, any, HCI_VS_Read_Memory_Block_From_DTST, 0x00, &mydata

+	WriteFile FileName1, 1, StrData(mydata)	

+	WriteFile FileName1, 1, "\n"

+	block_size-=chunk_size

+Wend

+

+	

+		

+		

+		

+		

+		

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190218, DtstParamL

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021a, DtstParamL

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190210, DtstMemCtrl

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190206, DtstCtrl

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190214, saveddtst

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+

+		

+#************************************************************************************************************#		

+		

+  	]]> 

+  	</Macro>

+

+	<Param type="u" size="1" bits="2" valtype="DTST_Mem_Max_Use">

+  	<Name>DTST_Mem_Max_Use</Name> 

+	  	<Default>0x04</Default> 

+  	<Desc>Selects Memory Size </Desc> 

+  	</Param>

+	<Param type="u" size="1">

+	<Name>DTST_filename</Name> 

+  	<Default>"C:\Temp\DTST_results"</Default> 

+  	<Desc> Chose the Path and filename </Desc> 

+  	</Param>

+	</Command>  	

+	

+  	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+	<!--  DTST Fast Recording		                                       --> 

+	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+ <Command name="DRP_DTST_Memory_Conf_Fast" type="cc">

+  <Cat>Spec 1.1</Cat> 

+<Macro>

+<![CDATA[ 

+

+		_DTST_Mem_Mode				= %1

+		_DTST_Mem_Enable 			= %2

+		_DTST_Enable 				= %3

+		_DTST_Signal_sel			= %4

+		_DTST_Module_sel			= %5

+		_DTST_Clk_Sel				= %6

+		_DTST_Mem_Max_Use 			= %7

+		_DTST_Mem_Step_Size			= %8

+		_DTST_Mem_Word_Select 		= %9

+		_DTST_Mem_Offset			= %10

+		_DTST_Mem_Wrap_Enable		= %11

+		_DTST_Sleep_Time			= %12

+		

+		

+		Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x00190218

+		Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &DtstParamL

+		Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x0019021a

+		Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &DtstParamM

+		Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x00190210

+		Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &DtstMemCtrl

+		Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x00190206

+		Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &DtstCtrl	

+		Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x00190214

+		Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &saveddtst

+	

+   

+

+    

+		#******************* DRP DTST REG CONFIG  *******************************************************#

+		

+		#Dmem Flag Register=0

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019326E, 0x0

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+	

+		#config DTST_MEM_SIG_REC_PARAMS

+		# config  DTST_Mem_Max_Use

+		DTST_Mem_Max_Use=(_DTST_Mem_Max_Use*1024)-1

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190218, DTST_Mem_Max_Use, 0x0fff

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config  DTST_Mem_Step_Size

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190218, _DTST_Mem_Step_Size<<12, 0x1000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config DTST_Mem_Word_Select

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190218, _DTST_Mem_Word_Select<<13, 0x2000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config DTST_Mem_Mem_Offset

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x0019021a, _DTST_Mem_Offset, 0x0fff

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config  DTST_Mem_Wrap_Enable

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x0019021a, _DTST_Mem_Wrap_Enable<<12, 0x1000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		#DTST_MEM_STOP_ADDR

+		#Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190226, 1

+		#Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		

+		#config DTST_MEM_CTRL

+		# config  _DTST_Mem_Mode 

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, _DTST_Mem_Mode<<2, 0x000c

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config  _DTST_Mem_Addr_Load 

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, 0x0001<<4, 0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		Sleep 10

+		# config  _DTST_Mem_Enable 

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, _DTST_Mem_Enable, 0x0001

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#Config DTST_CTRL register 

+		

+		#Disable DTST

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206,0x00000 ,  0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		#config signal_select 

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204,_DTST_Signal_sel ,  0x00ff

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config module_select

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204,_DTST_Module_sel<<8 ,  0x0700

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config Clk_select

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206,_DTST_Clk_Sel ,  0x000f

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		sleep 1

+		

+		# config _DTST_Enable DTST CTRL (enable/disable the DTST)

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206,_DTST_Enable<<4 ,  0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#Enable the rx_start cortex 0x001932D6 This register set in the DMEM 

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019326E, 0x1

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+	

+		# wait DTST_Sleep_Time micro-sec 

+		sleep _DTST_Sleep_Time+5

+

+#************************************************end recording ************************************************************#

+		# config  DTST_Mem_Wrap_Enable =0

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x0019021a, 0<<12, 0x1000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		Sleep 1000

+		# config  _DTST_Mem_Enable=0

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, 0, 0x0001

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE DTST Disable to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, 0<<4, 0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+			

+#************************************************************************************************************#		

+

+	

+	

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190218, DtstParamL

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021a, DtstParamL

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190210, DtstMemCtrl

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190206, DtstCtrl

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190214, saveddtst

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+

+#************************************************************************************************************#		

+		

+  	]]> 

+  	</Macro>

+ 	<Param type="u" size="1" bits="2" valtype="DTST_Mem_Mode">

+  	<Name>DTST_Mem_Mode</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects the Memory Mode </Desc> 

+  	</Param>

+  	<Param type="u" size="1" bits="1" valtype="DTST_Mem_Enable">

+  	<Name>DTST_Mem_Enable</Name> 

+  	<Default>1</Default> 

+  	<Desc>0 - Enable\Disable Mem</Desc> 

+  	</Param>	

+	<Param type="u" size="1" bits="1" valtype="DTST_Enable">

+  	<Name>DTST_Enable</Name> 

+  	<Default>1</Default> 

+  	<Desc>0 - Enable\Disable Mem</Desc> 

+  	</Param>

+	<Param type="u" size="1">

+  	<Name>DTST_Signal_sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>1-Selects the signals to Mux </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="4" valtype="dtst_Module_sel">

+  	<Name>DTST_Module_sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects the DRP Module </Desc> 

+  	</Param>	

+  	<Param type="u" size="1" bits="4" valtype="test_clk_mux_sel">

+  	<Name>DTST_Clk_Sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects the output clock on test_clk output</Desc> 

+  	</Param>

+	<Param type="u" size="1" bits="2" valtype="DTST_Mem_Max_Use">

+  	<Name>DTST_Mem_Max_Use</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects Memory Size </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="DTST_Mem_Step_Size">

+  	<Name>DTST_Mem_Step_Size</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>0 - Select Step Size in bytes </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="DTST_Mem_Word_Select">

+  	<Name>DTST_Mem_Word_Select</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects DTST Mem Word MSB LSB</Desc> 

+  	</Param>

+  	<Param type="u" size="1">

+  	<Name>DTST_Mem_Offset</Name> 

+  	<Default>0x000</Default> 

+  	<Desc>1-Selects the DTST Mem Offset up to 4KByte  </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="DTST_Mem_Wrap_Enable">

+  	<Name>DTST_Mem_Wrap_Enable</Name> 

+  	<Default>1</Default> 

+  	<Desc>0 - Enable\Disable Wrap</Desc> 

+  	</Param>

+ 	<Param type="u" size="1">

+  	<Name>DTST_sleep_time</Name> 

+  	<Default>0x0000</Default> 

+  	<Desc>Selects how length of the recording procudure in us  (sleep between redord enable/disable </Desc> 

+  	</Param>

+	

+	</Command>  

+	

+  	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+	<!--  DTST Fast Recording Without internal 'stop'                                    --> 

+	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+ <Command name="DRP_DTST_Memory_Conf_Fast_NoStop" type="cc">

+  <Cat>Spec 1.1</Cat> 

+<Macro>

+<![CDATA[ 

+

+		_DTST_Mem_Mode				= %1

+		_DTST_Mem_Enable 			= %2

+		_DTST_Enable 				= %3

+		_DTST_Signal_sel			= %4

+		_DTST_Module_sel			= %5

+		_DTST_Clk_Sel				= %6

+		_DTST_Mem_Max_Use 			= %7

+		_DTST_Mem_Step_Size			= %8

+		_DTST_Mem_Word_Select 		= %9

+		_DTST_Mem_Offset			= %10

+		_DTST_Mem_Wrap_Enable		= %11		

+			

+   

+

+    

+		#******************* DRP DTST REG CONFIG  *******************************************************#

+		

+		#Dmem Flag Register=0

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019326E, 0x0

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+	

+		#config DTST_MEM_SIG_REC_PARAMS

+		# config  DTST_Mem_Max_Use

+		DTST_Mem_Max_Use=(_DTST_Mem_Max_Use*1024)-1

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190218, DTST_Mem_Max_Use, 0x0fff

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config  DTST_Mem_Step_Size

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190218, _DTST_Mem_Step_Size<<12, 0x1000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config DTST_Mem_Word_Select

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190218, _DTST_Mem_Word_Select<<13, 0x2000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config DTST_Mem_Mem_Offset

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x0019021a, _DTST_Mem_Offset, 0x0fff

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config  DTST_Mem_Wrap_Enable

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x0019021a, _DTST_Mem_Wrap_Enable<<12, 0x1000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		#DTST_MEM_STOP_ADDR

+		#Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190226, 1

+		#Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		

+		#config DTST_MEM_CTRL

+		# config  _DTST_Mem_Mode 

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, _DTST_Mem_Mode<<2, 0x000c

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config  _DTST_Mem_Addr_Load 

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, 0x0001<<4, 0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		Sleep 10

+		# config  _DTST_Mem_Enable 

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, _DTST_Mem_Enable, 0x0001

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#Config DTST_CTRL register 

+		

+		#Disable DTST

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206,0x00000 ,  0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		#config signal_select 

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204,_DTST_Signal_sel ,  0x00ff

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config module_select

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204,_DTST_Module_sel<<8 ,  0x0700

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# config Clk_select

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206,_DTST_Clk_Sel ,  0x000f

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		sleep 1

+		

+		# config _DTST_Enable DTST CTRL (enable/disable the DTST)

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206,_DTST_Enable<<4 ,  0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		#Enable the rx_start cortex 0x001932D6 This register set in the DMEM 

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019326E, 0x1

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+	

+

+#************************************************************************************************************#		

+		

+  	]]> 

+  	</Macro>

+ 	<Param type="u" size="1" bits="2" valtype="DTST_Mem_Mode">

+  	<Name>DTST_Mem_Mode</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects the Memory Mode </Desc> 

+  	</Param>

+  	<Param type="u" size="1" bits="1" valtype="DTST_Mem_Enable">

+  	<Name>DTST_Mem_Enable</Name> 

+  	<Default>1</Default> 

+  	<Desc>0 - Enable\Disable Mem</Desc> 

+  	</Param>	

+	<Param type="u" size="1" bits="1" valtype="DTST_Enable">

+  	<Name>DTST_Enable</Name> 

+  	<Default>1</Default> 

+  	<Desc>0 - Enable\Disable Mem</Desc> 

+  	</Param>	

+	<Param type="u" size="1">

+  	<Name>DTST_Signal_sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>1-Selects the signals to Mux </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="4" valtype="dtst_Module_sel">

+  	<Name>DTST_Module_sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects the DRP Module </Desc> 

+  	</Param>	

+  	<Param type="u" size="1" bits="4" valtype="test_clk_mux_sel">

+  	<Name>DTST_Clk_Sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects the output clock on test_clk output</Desc> 

+  	</Param>

+	<Param type="u" size="1" bits="2" valtype="DTST_Mem_Max_Use">

+  	<Name>DTST_Mem_Max_Use</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects Memory Size </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="DTST_Mem_Step_Size">

+  	<Name>DTST_Mem_Step_Size</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>0 - Select Step Size in bytes </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="DTST_Mem_Word_Select">

+  	<Name>DTST_Mem_Word_Select</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects DTST Mem Word MSB LSB</Desc> 

+  	</Param>

+  	<Param type="u" size="1">

+  	<Name>DTST_Mem_Offset</Name> 

+  	<Default>0x000</Default> 

+  	<Desc>1-Selects the DTST Mem Offset up to 4KByte  </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="DTST_Mem_Wrap_Enable">

+  	<Name>DTST_Mem_Wrap_Enable</Name> 

+  	<Default>1</Default> 

+  	<Desc>0 - Enable\Disable Wrap</Desc> 

+  	</Param>

+

+	

+	</Command>  	

+

+	

+	

+  	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+	<!--  Stop DTST Fast Recording Without internal 'stop'                           --> 

+	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+ <Command name="DRP_Stop_DTST_Memory_Conf" type="cc">

+  <Cat>Spec 1.1</Cat> 

+<Macro>

+<![CDATA[ 

+

+#************************************************end recording ************************************************************#

+		# config  DTST_Mem_Wrap_Enable =0

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x0019021a, 0<<12, 0x1000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		Sleep 1000

+		# config  _DTST_Mem_Enable=0

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, 0, 0x0001

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE DTST Disable to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, 0<<4, 0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00			

+

+

+#************************************************************************************************************#		

+		

+  	]]> 

+  	</Macro>

+	

+	</Command>  

+  	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+	<!--  DRP Power Levels Setting  		                                       --> 

+	<!--  *******************************************************  --> 

+	<!--  *******************************************************  --> 

+ <Command name="DRP_Power_Levels_Setting" type="cc">

+  <Cat>Spec 1.1</Cat> 

+<Macro>

+<![CDATA[ 

+

+		_GFSKPowerValue= %1

+		_GFSKDeltaPowerValue = %2

+		_EDR2PowerValue = %3

+		_EDR2DeltaPowerValue= %4

+		_EDR3PowerValue = %5

+		_EDR3DeltaPowerValue = %6

+		 	

+ 	

+ 	

+ 	#enter power levels here 

+GFSKPowerValueT=_GFSKPowerValue

+GFSKDeltaPowerValueT=_GFSKDeltaPowerValue

+EDR2PowerValueT=_EDR2PowerValue

+EDR2DeltaPowerValueT=_EDR2DeltaPowerValue

+EDR3PowerValueT=_EDR3PowerValue

+EDR3DeltaPowerValueT=_EDR3DeltaPowerValue

+

+

+FileNameGFSK="C:\Temp\GFSKPowerSet.txt"

+FileNameEDR2="C:\Temp\EDR2PowerSet.txt"

+FileNameEDR3="C:\Temp\EDR3PowerSet.txt"

+

+LoopNom=15

+

+

+#GFSK LOOP

+WriteFile FileNameGFSK, 0,"GFSKPowerValue=\""

+for loop=0 to ( LoopNom )

+GFSKPowerValueT=GFSKPowerValueT-GFSKDeltaPowerValueT

+valLT = GFSKPowerValueT&0x00ff

+valHT = GFSKPowerValueT&0xff00

+valH = valHT >> 8 

+valL = valLT << 8 

+GFSKPowerValue=valL+valH

+WriteFile FileNameGFSK,1, "%x",GFSKPowerValue

+next

+WriteFile FileNameGFSK, 1, "\""

+

+#GFSK LOOP

+WriteFile FileNameEDR2, 0,"EDR2PowerValue=\""

+for loop=0 to ( LoopNom )

+EDR2PowerValueT=EDR2PowerValueT-EDR2DeltaPowerValueT

+valLT = EDR2PowerValueT&0x00ff

+valHT = EDR2PowerValueT&0xff00

+valH = valHT >> 8 

+valL = valLT << 8 

+EDR2PowerValue=valL+valH

+WriteFile FileNameEDR2,1, "%x",EDR2PowerValue

+next

+WriteFile FileNameEDR2, 1, "\""

+

+#EDR3 LOOP

+WriteFile FileNameEDR3, 0,"EDR3PowerValue=\""

+for loop=0 to ( LoopNom )

+EDR3PowerValueT=EDR3PowerValueT-EDR3DeltaPowerValueT

+valLT = EDR3PowerValueT&0x00ff

+valHT = EDR3PowerValueT&0xff00

+valH = valHT >> 8 

+valL = valLT << 8 

+EDR3PowerValue=valL+valH

+WriteFile FileNameEDR3,1, "%x",EDR3PowerValue

+next

+WriteFile FileNameEDR3, 1, "\""

+

+ callfile "C:\Temp\GFSKPowerSet.txt"

+ callfile "C:\Temp\EDR2PowerSet.txt"

+ callfile "C:\Temp\EDR3PowerSet.txt"

+ 

+

+

+#write GFSK POWER values

+Send_HCI_VS_Write_Memory_Block 0xFF05, 0x193356, 32,GFSKPowerValue

+Wait_HCI_Command_Complete_VS_Write_Memory_Block_Event 5000, any, HCI_VS_Write_Memory_Block, 0x00

+

+#write EDR2 POWER values

+Send_HCI_VS_Write_Memory_Block 0xFF05, 0x193376, 32,EDR2PowerValue

+Wait_HCI_Command_Complete_VS_Write_Memory_Block_Event 5000, any, HCI_VS_Write_Memory_Block, 0x00

+

+#write EDR3 POWER values

+Send_HCI_VS_Write_Memory_Block 0xFF05, 0x193396, 32,EDR3PowerValue

+Wait_HCI_Command_Complete_VS_Write_Memory_Block_Event 5000, any, HCI_VS_Write_Memory_Block, 0x00

+ 

+]]> 

+  	</Macro>

+   	<Param type="u" size="1">

+  	<Name>GFSKMaxPowerValue</Name> 

+  	<Default>0x0000</Default> 

+  	<Desc>1-Selects GFSK Max Power   </Desc> 

+  	</Param>

+  	<Param type="u" size="1">

+  	<Name>GFSKDeltaPowerValue</Name> 

+  	<Default>0x0000</Default> 

+  	<Desc>1-Selects GFSK Delta Power </Desc> 

+  	</Param>

+  	<Param type="u" size="1">

+  	<Name>EDR2MaxPowerValue</Name> 

+  	<Default>0x0000</Default> 

+  	<Desc>1-Selects EDR2 Max Power  </Desc> 

+  	</Param>

+  	<Param type="u" size="1">

+  	<Name>EDR2DeltaPowerValue</Name> 

+  	<Default>0x0000</Default> 

+  	<Desc>1-Selects EDR2 Delta Power  </Desc> 

+  	</Param>

+  	<Param type="u" size="1">

+  	<Name>EDR3MaxPowerValue</Name> 

+  	<Default>0x0000</Default> 

+  	<Desc>1-Selects EDR3 Max Power </Desc> 

+  	</Param>

+  	<Param type="u" size="1">

+  	<Name>EDR3DeltaPowerValue</Name> 

+  	<Default>0x0000</Default> 

+  	<Desc>1-Selects EDR3 Delta Power </Desc> 

+  	</Param>

+  	</Command>  

+    

+

+

+

+<Command name="HCI_VS_PCM_48_Rate_Conversion_Enable" type="sc" opcode="0xFD93">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD93</Default>

+   <Desc> Enabel Conversion from 48KHz rate to 8/16KHz</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Enable Rate</Name>

+   <Default>0x0</Default>

+   <Desc>Bit0=convert to 8KHz enable, Bits 1-7=Reserved</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Reserved</Name>

+   <Default>0x0</Default>

+   <Desc>Reserved</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_Set_Narrow_Band_Voice_Path" type="sc" opcode="0xFD94">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD94</Default>

+   <Desc> Set Source for Voice Links </Desc>

+  </Param>

+  <Param type="u" size="2">

+   <Name>Voice Handle</Name>

+   <Default>0x0000</Default>

+   <Desc>0x0000 - Clear Association, 0x0101..0x702 - Associate Existing Handle, 0xFFFF - Associate Next Handle</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Source</Name>

+   <Default>0</Default>

+   <Desc>0 - Host(Default), 1 - FM</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>Path</Name>

+   <Default>0</Default>

+   <Desc>0 - Regular voice connection, 1 - WBS conneciton </Desc>

+  </Param>

+

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+

+<Command name="HCI_VS_BT_IP1_1_Set_FM_Audio_Path" type="vc" opcode="0xFD95">

+    <Param type="o" size="2">

+        <Name>Opcode</Name>

+        <Default>0xFD95</Default>

+        <Desc>Controls the audio output pin mux and override pull registers</Desc>

+    </Param>

+    <Param type="u" size="4">

+        <Name>PCMI override</Name>

+        <Default>0xFFFFFFFF</Default>

+        <Desc>The value of the PCMI_TOP_CTRL_REG. 0xFFFFFFFF indicates no change. For Quattro pull upddate done through Quatt pcmi pull config only when override filed is not 0xFFFFFFFF. The value in Quattro sets PCM CTRL reg. Value of 0xFFFFFFFE updates only PCM pull reg for Quattro  </Desc>

+    </Param>

+    <Param type="u" size="4">

+        <Name>I2S override</Name>

+        <Default>0xFFFFFFFF</Default>

+        <Desc>The value of the I2S_TOP_CTRL_REG. 0xFFFFFFFF indicates no change. For Quattro pull upddate done through Quatt i2s pull config only when override filed is not 0xFFFFFFFF. The value in Quattro sets I2S CTRL reg. Value of 0xFFFFFFFE updates only I2S pull reg for Quattro  </Desc>

+    </Param>

+    <Param type="u" size="1" >

+        <Name>BT Audio Path</Name>

+        <Default>0xFF</Default>

+        <Desc>0 - None, 1 - PCM, 2 - I2S, 0xFF - Don't Change</Desc>

+    </Param>

+    <Param type="u" size="1" >

+        <Name>FM Audio Path</Name>

+        <Default>0xFF</Default>

+        <Desc>0 - None, 1 - PCM, 2 - I2S, 0xFF - Don't Change</Desc>

+    </Param>

+    <Param type="u" size="1" >

+        <Name>TDM Enable</Name>

+        <Default>0xFF</Default>

+        <Desc>0 - Enable TDM with BT M, 1 - Enable TDM with FM M, 2 - Enable TDM with Host M, 3 - Disable TDM, 0xFF - Don't Change</Desc>

+    </Param>

+    <Param type="u" size="1">

+        <Name>Quattro PCMI pull config</Name>

+        <Default>0</Default>

+        <Desc>Quattro pcmi pull config (fieled is applied when PCMI override is 0xFFFFFFFE or different than 0xFFFFFFFF) 0:1- Audio in, 2:3- audio out, 4:5- audio clock, 6:7- audio fsync</Desc>

+    </Param>

+    <Param type="u" size="1">

+        <Name>Quattro I2S pull config</Name>

+        <Default>0</Default>

+        <Desc>Quattro i2s pull config (fieled is applied when I2S override is 0xFFFFFFFE or different than 0xFFFFFFFF)  0:1- Din, 2:3- Dout, 4:5- clock, 6:7- fsync</Desc>

+    </Param>

+    <Param type="u" size="1">

+        <Name>Reserved</Name>

+        <Default>0</Default>

+        <Desc></Desc>

+    </Param>

+    <Param type="u" size="1">

+        <Name>Reserved</Name>

+        <Default>0</Default>

+        <Desc></Desc>

+    </Param>

+    

+    <Param type="R">

+        <Name>HCI_Command_Complete_Event</Name>

+        <Default />

+        <Desc />

+    </Param>

+</Command>

+

+

+ 

+<Command name="HCI_VS_Set_LE_Test_Mode_Parameters" type="sc" opcode="0xFD77">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFD77</Default>

+   <Desc> Sets parameters for the BLE Test Mode </Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>TX Power Level</Name>

+   <Default>0xF</Default>

+   <Desc>Transmit power level</Desc>

+  </Param>

+  <Param type="u" size="1" valtype="HCI_LE_Testmode_Receive_Mode">

+   <Name>RX Mode</Name>

+   <Default>1</Default>

+   <Desc>0 - Normal mode, 1 - Wide Window, 2 - Continious RX, 3 - Wide window and power saving</Desc>

+  </Param>

+  <Param type="u" size="2">

+   <Name>Packets to transmit</Name>

+   <Default>0</Default>

+   <Desc>A number of packets to transmit.0 means continious TX</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Access Code</Name>

+   <Default>0x71764129</Default>

+   <Desc>An access code to sync/transmit.Default value is 0x71764129</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>BLE BER Test Enable</Name>

+   <Default>0</Default>

+   <Desc>Enable of the BER test</Desc>

+  </Param>

+  <Param type="u" size="1" valtype="HCI_LE_Testmode_Packet_Type">

+   <Name>BLE Ber Test pattern</Name>

+   <Default>0</Default>

+   <Desc>A data pattern of the payload that is expected to be received</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>BER Test packet length</Name>

+   <Default>10</Default>

+   <Desc>A number of payload bytes that are expected to be received in the BER test</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>BER FA Threshold</Name>

+   <Default>20</Default>

+   <Desc>A threshold for the FA detection</Desc>

+  </Param>

+    <Param type="u" size="1">

+   <Name>Trace Enable</Name>

+   <Default>0</Default>

+   <Desc>Enables or Disables traces during the BER test</Desc>

+  </Param>

+  <Param type="u" size="4">

+   <Name>Referance CRC</Name>

+   <Default>0</Default>

+   <Desc>Referance CRC value for the packet</Desc>

+  </Param>

+  <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="HCI_VS_Set_LE_GPIO_BB_signals" type="vc" opcode="0xFDA4">

+  <Param type="o" size="2">

+   <Name>Opcode</Name>

+   <Default>0xFDA4</Default>

+   <Desc> Sets GPIO waving of BLE BB signals, if value is 0xFF do not wave IO for this signal</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>TX strech select</Name>

+   <Default>0xFF</Default>

+   <Desc>IO pin for TX strech</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>RX strech select</Name>

+   <Default>0xFF</Default>

+   <Desc>IO pin for RX strech</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>CRC OK select</Name>

+   <Default>0xFF</Default>

+   <Desc>IO pin for CRC OK</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>CONNECT_REQ TX select</Name>

+   <Default>0xFF</Default>

+   <Desc>IO pin for CONNECT_REQ TX</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>SCAN_REQ TX select</Name>

+   <Default>0xFF</Default>

+   <Desc>IO pin for CAN_REQ TX</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>CTRL PACKET RECEIVED select</Name>

+   <Default>0xFF</Default>

+   <Desc>IO pin for signals ctrl packet received</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>CTRL PACKET SENT select</Name>

+   <Default>0xFF</Default>

+   <Desc>IO pin for ctrl packet sent</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>RETRANSMIT DATA select</Name>

+   <Default>0xFF</Default>

+   <Desc>IO pin for retransmit data packet sent</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>NO_SYNC_TIME</Name>

+   <Default>0xFF</Default>

+   <Desc>IO pin indicating NO SYNC, set high every time RX was expected but there was no SYNC</Desc>

+  </Param>

+  <Param type="u" size="1">

+   <Name>reserved5</Name>

+   <Default>0xFF</Default>

+   <Desc>IO pin for reserved</Desc>

+  </Param>

+   <Param type="R">

+   <Name>HCI_Command_Complete_Event</Name>

+   <Default />

+   <Desc />

+  </Param>

+</Command>

+

+<Command name="DRP_Mux_DTST_BT_IP" type="cc">

+  <Cat>Spec 1.1</Cat> 

+<Macro>

+<![CDATA[ 

+		_test_mux_Signal_sel= %1

+		_dtst_Module_sel = %2

+		_shift_select= %3

+		_test_clk_mux_sel = %4

+		_test_dtst_enable = %5

+		_test_mirror_enable = %6

+		_test_apll_clk_select = %7

+		_TestBusOverrideSelect = %8

+		_TestBusOverrideValue = %9

+

+		

+		# Dont Set config module settings

+		############################ 

+

+		#BTIP Configu module configuraton

+		#Send_HCIPP_Set_IO_Pin_Mux_BTIP 0x01, 0x07

+

+		

+		# Set debug module settings 

+		########################### 

+	

+		# Write to TEST SELECT REGISTER: 

+		# DRX is muxed out 

+

+		# DBG(9:5)

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A300C, 0x0000

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+

+		# DBG(4:0)

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A300A, 0x0000

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+

+		# DBG(15:0) enable

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A3002, 0x0004

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00

+

+		#**************************************************************************#

+		sleep 100

+		#**************************************************************************#

+		#BTIP AOD module (GCM level) configuration(10 lsb's the other 7 by pass this module )

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A605c, 0x0000

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+		#**************************************************************************#

+		sleep 100

+		#**************************************************************************#

+		

+		#quattro TOP related mux is done by 

+		

+

+		

+

+		#******************* DRP DTST REG CONFIG  *******************************************************#

+		

+		#Clear dtst En 

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, 0<<4, 0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		

+		# WRITE test_mux_Signal_sel to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204, _test_mux_Signal_sel, 0x00ff

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _dtst_Module_sel to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204, _dtst_Module_sel<<8, 0x0700

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _shift_select to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204, _shift_select<<12, 0xf000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _test_clk_mux_sel to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_clk_mux_sel, 0x000f

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _test_mirror_enable to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_mirror_enable<<8, 0x0100

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _test_apll_clk_select to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_apll_clk_select<<12, 0x1000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+	

+

+	

+		log "test_dtst_enable %d", _test_dtst_enable

+		if _test_dtst_enable > 0 then

+

+		# WRITE _test_dtst_enable to	DTST_CTRL Register

+		#		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, 0x1B, 0x001f

+		#		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE DTST Enable to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_dtst_enable<<4, 0x0010

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _test_apll_clk_select to	DTST_CTRL Register

+		end if

+		

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,0, 0x0001

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+	

+		if _test_clk_mux_sel > 3 & _test_clk_mux_sel < 7 then 

+		# WRITE _test_mirror_enable to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,1, 0x0001

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+	    else

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,0, 0x0001

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		end if 

+		log "test_dtst_enable %d", _test_dtst_enable

+		

+		#******************* DRP DTST REG CONFIG END  *******************************************************#

+			

+		#******************* DRP DTST Bus Override   *******************************************************#

+		# WRITE TestBusOverrideSelect to Register

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021e, _TestBusOverrideSelect

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+

+		# WRITE TestBusOverrideValue to	 Register

+		Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021c, _TestBusOverrideValue

+		Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00

+

+		if _TestBusOverrideSelect > 0 then

+		# WRITE _test_mirror_enable to	DTST_CTRL Register

+		Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190102, 1<<12, 0x1000

+		Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00

+		# WRITE _test_apll_clk_select to	DTST_CTRL Register

+		end if

+	#******************* DRP DTST Bus Override End  *******************************************************#

+  	]]> 

+  	</Macro>

+ 	<Param type="u" size="1">

+  	<Name>Signal_sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>1-Selects the signals to Mux </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="4" valtype="dtst_Module_sel">

+  	<Name>Module_sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects the DRP Module </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="4" valtype="shift_select">

+  	<Name>shift_select</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>0 - Select Number of bits to mux </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="4" valtype="test_clk_mux_sel">

+  	<Name>test_clk_mux_sel</Name> 

+  	<Default>0x00</Default> 

+  	<Desc>Selects the output clock on test_clk output</Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="test_dtst_enable">

+  	<Name>test_dtst_enable</Name> 

+  	<Default>1</Default> 

+  	<Desc>0 - Enable\Disable DTST</Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="test_mirror_enable">

+  	<Name>test_mirror_enable</Name> 

+  	<Default>0</Default> 

+  	<Desc>0 - Enable Mirrore </Desc> 

+  	</Param>

+ 	<Param type="u" size="1" bits="1" valtype="test_apll_clk_select">

+  	<Name>test_apll_clk_select</Name> 

+  	<Default>0</Default> 

+  	</Param>

+ 	<Param type="u" size="1" bits="2" valtype="TestBusOverrideSelect">

+  	<Name>TestBusOverrideSelect</Name> 

+  	<Default>0</Default> 

+  	</Param>

+  	<Values name="TestBusOverrideValue" type="enum">

+  	</Values>	

+	<Param type="u" size="1">

+  	<Name>TestBusOverrideValue</Name> 

+  	<Default>0x0000</Default> 

+  	<Desc>1-Enter TestBusOverrideValue </Desc> 

+  	</Param>

+  	</Command>  

+  	<!--  *******************************************************  --> 

+

+

+    <Command name="HCI_VS_Read_LE_Statistics" type="sc" opcode="0xFDA1">

+        <Param type="o" size="2">

+            <Name>Opcode</Name>

+            <Default>0xFDA1</Default>

+            <Desc>HCIPP Read LE Statistics</Desc>

+        </Param>

+        <Param type="R">

+            <Name>HCI_Command_Complete_Event</Name>

+            <Default />

+            <Desc />

+        </Param>

+        <Param type="u" size="1" valtype="Status">

+            <Name>Status</Name>

+            <Default>0</Default>

+            <Desc>0 - Success, 1 - Illegal command</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_ADV_sent_ch0 </Name>

+            <Default>Any</Default>

+            <Desc>Num of ADV packets sent by advertiser on ch 0</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_ADV_sent_ch1 </Name>

+            <Default>Any</Default>

+            <Desc>Num of ADV packets sent by advertiser on ch 1</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_ADV_sent_ch2 </Name>

+            <Default>Any</Default>

+            <Desc>Num of ADV packets sent by advertiser on ch 2</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_RSP_sent_ch0 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_RSP packets sent by advertiser on ch 0</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_RSP_sent_ch1 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_RSP packets sent by advertiser on ch 1</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_RSP_sent_ch2 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_RSP packets sent by advertiser on ch 2</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_REQ_received_ch0 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_REQ packets received by advertiser on ch 0</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_REQ_received_ch1 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_REQ packets received by advertiser on ch 1</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_REQ_received_ch2 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_REQ packets received by advertiser on ch 2</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_ADV_received_ch0 </Name>

+            <Default>Any</Default>

+            <Desc>Num of ADV packets received by scanner on ch 0</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_ADV_received_ch1 </Name>

+            <Default>Any</Default>

+            <Desc>Num of ADV packets received by scanner on ch 1</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_ADV_received_ch2 </Name>

+            <Default>Any</Default>

+            <Desc>Num of ADV packets received by scanner on ch 2</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_RSP_received_ch0 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_RSP packets received by scanner on ch 0</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_RSP_received_ch1 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_RSP packets received by scanner on ch 1</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_RSP_received_ch2 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_RSP packets received by scanner on ch 2</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_REQ_sent_ch0 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_REQ packets sent by scanner on ch 0</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_REQ_sent_ch1 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_REQ packets sent by scanner on ch 1</Desc>

+        </Param>

+        <Param type="d" size="2">

+            <Name>Num_SCAN_REQ_sent_ch2 </Name>

+            <Default>Any</Default>

+            <Desc>Num of SCAN_REQ packets sent by scanner on ch 2</Desc>

+        </Param>

+    </Command>

+

+

+    

+</HCILib>

+

diff --git a/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/LICENCE b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/LICENCE
new file mode 100644
index 0000000..2a1539f
--- /dev/null
+++ b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/bluetooth/LICENCE
@@ -0,0 +1,46 @@
+   1 TECHNOLOGY AND SOFTWARE PUBLICLY AVAILABLE

+   2 SOFTWARE LICENSE

+   3 

+   4 Copyright (c) 2011, Texas Instruments Incorporated.

+   5 

+   6 All rights reserved.

+   7 

+   8 Redistribution.  

+   9 

+  10 Redistribution and use in binary form, without modification, are

+  11 permitted provided that the following conditions are met:

+  12 

+  13  * Redistributions must preserve existing copyright notices and reproduce 

+  14	this license (including the above copyright notice and the disclaimer below)

+  15	in the documentation and/or other materials provided with the distribution.

+  16 

+  17  * Neither the name of Texas Instruments Incorporated nor the names of 

+  18    its suppliers may be used to endorse or promote products derived 

+  19    from this software without specific prior written permission.

+  20 

+  21  * No reverse engineering, decompilation, or disassembly of this

+  22    software is permitted.

+  23 

+  24 Limited patent license.

+  25 

+  26 Texas Instruments Incorporated grants a world-wide, royalty-free, 

+  27 non-exclusive license under patents it now or hereafter owns or controls 

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+  33 

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diff --git a/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/LICENCE b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/LICENCE
new file mode 100644
index 0000000..085f6c7
--- /dev/null
+++ b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/LICENCE
@@ -0,0 +1,151 @@
+Texas Instruments Incorporated
+Technology and Software Publicly Available
+Software (Object Code) License Agreement
+
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+1
+TILAW-#236402v3
+
diff --git a/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-2.bin b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-2.bin
new file mode 100644
index 0000000..a01324e
--- /dev/null
+++ b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-2.bin
diff --git a/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-ap.bin b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-ap.bin
new file mode 100644
index 0000000..c145a71
--- /dev/null
+++ b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-ap.bin
diff --git a/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-multirole-plt.bin b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-multirole-plt.bin
new file mode 100755
index 0000000..784b275
--- /dev/null
+++ b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-multirole-plt.bin
diff --git a/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-multirole-roc.bin b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-multirole-roc.bin
new file mode 100755
index 0000000..3655919
--- /dev/null
+++ b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-fw-multirole-roc.bin
diff --git a/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-nvs.bin b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-nvs.bin
new file mode 100644
index 0000000..91978f9
--- /dev/null
+++ b/multitech/recipes/wl12xx-firmware/wl12xx-firmware/wifi/wl1271-nvs.bin
diff --git a/multitech/recipes/wl12xx-firmware/wl12xx-firmware_1.0.bb b/multitech/recipes/wl12xx-firmware/wl12xx-firmware_1.0.bb
new file mode 100644
index 0000000..9b8c59f
--- /dev/null
+++ b/multitech/recipes/wl12xx-firmware/wl12xx-firmware_1.0.bb
@@ -0,0 +1,28 @@
+DESCRIPTION = "TI wl1271 firmware"
+HOMEPAGE = "http://processors.wiki.ti.com/index.php/ARM_Processor_Open_Source_Wireless_Connectivity"
+PR="r3"
+
+# bluetooth firmware from TI wiki:
+#   http://processors.wiki.ti.com/index.php/OMAP_Wireless_Connectivity_BTS_files_overview
+#   http://processors.wiki.ti.com/images/a/a2/BTS_files_v1.zip
+
+SRC_URI = "file://bluetooth/3M/WL127xL_BT_Service_Pack_2.4.bts \
+			file://wifi/wl1271-fw-2.bin \
+			file://wifi/wl1271-fw-ap.bin \
+			file://wifi/wl1271-fw-multirole-plt.bin \
+			file://wifi/wl1271-fw-multirole-roc.bin \
+			file://wifi/wl1271-nvs.bin \
+			"
+
+do_install() {
+	install -d ${D}/lib/firmware
+	install -d ${D}/lib/firmware/ti-connectivity
+	# wifi firmware
+	install ${WORKDIR}/wifi/wl1271-fw*.bin ${D}/lib/firmware/ti-connectivity
+	# factory nvs file
+	install ${WORKDIR}/wifi/wl1271-nvs.bin ${D}/lib/firmware/ti-connectivity/wl1271-nvs.bin
+	# bluetooth firmware
+	install ${WORKDIR}/bluetooth/3M/WL127xL_BT_Service_Pack_2.4.bts ${D}/lib/firmware/TIInit_7.6.15.bts
+}
+
+FILES_${PN} = "/lib/firmware"
diff --git a/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0.inc b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0.inc
new file mode 100644
index 0000000..7ca4cc3
--- /dev/null
+++ b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0.inc
@@ -0,0 +1,94 @@
+DESCRIPTION = "A Client for Wi-Fi Protected Access (WPA)."
+HOMEPAGE = "http://hostap.epitest.fi/wpa_supplicant/"
+BUGTRACKER = "http://hostap.epitest.fi/bugz/"
+SECTION = "network"
+LICENSE = "GPLv2 | BSD"
+LIC_FILES_CHKSUM = "file://../COPYING;md5=c54ce9345727175ff66d17b67ff51f58 \
+                    file://../README;md5=54cfc88015d3ce83f7156e63c6bb1738 \
+                    file://wpa_supplicant.c;beginline=1;endline=17;md5=acdc5a4b0d6345f21f136eace747260e"
+DEPENDS = "gnutls dbus libnl openssl ${@base_contains("COMBINED_FEATURES", "madwifi", "madwifi-ng", "",d)}"
+RRECOMMENDS_${PN} = "wpa-supplicant-passphrase wpa-supplicant-cli"
+INC_PR = "r0"
+
+SRC_URI = "http://hostap.epitest.fi/releases/wpa_supplicant-${PV}.tar.gz \
+           file://defconfig \
+           file://defaults-sane \
+           file://wpa-supplicant.sh \
+           file://wpa_supplicant.conf \
+           file://wpa_supplicant.conf-sane \
+           file://99_wpa_supplicant"
+
+S = "${WORKDIR}/wpa_supplicant-${PV}/wpa_supplicant"
+
+PACKAGES_prepend = "wpa-supplicant-passphrase wpa-supplicant-cli "
+FILES_wpa-supplicant-passphrase = "/usr/sbin/wpa_passphrase"
+FILES_wpa-supplicant-cli = "/usr/sbin/wpa_cli"
+FILES_${PN} += " /usr/share/dbus-1/system-services/*"
+
+do_configure () {
+	install -m 0755 ${WORKDIR}/defconfig .config
+	if [ "${@base_contains('COMBINED_FEATURES', 'madwifi', 1, 0, d)}" = "1" ]; then
+		echo "CONFIG_DRIVER_MADWIFI=y" >> .config
+		echo "CFLAGS += -I${STAGING_INCDIR}/madwifi-ng" >> .config
+	fi
+}
+
+do_compile () {
+	make
+}
+
+do_install () {
+	install -d ${D}${sbindir}
+	install -m 755 wpa_supplicant ${D}${sbindir}
+	install -m 755 wpa_passphrase ${D}${sbindir}
+	install -m 755 wpa_cli        ${D}${sbindir}
+
+	install -d ${D}${docdir}/wpa_supplicant
+	install -m 644 README ${WORKDIR}/wpa_supplicant.conf ${D}${docdir}/wpa_supplicant
+
+	install -d ${D}${sysconfdir}/default
+	install -m 600 ${WORKDIR}/defaults-sane ${D}${sysconfdir}/default/wpa
+	install -m 600 ${WORKDIR}/wpa_supplicant.conf-sane ${D}${sysconfdir}/wpa_supplicant.conf
+
+	if grep -q ^CONFIG_CTRL_IFACE_DBUS=y .config || grep -q ^CONFIG_CTRL_IFACE_DBUS_NEW=y .config; then
+		install -d ${D}/${sysconfdir}/dbus-1/system.d
+		install -m 644 ${S}/dbus/dbus-wpa_supplicant.conf ${D}/${sysconfdir}/dbus-1/system.d
+		install -d ${D}/${datadir}/dbus-1/system-services
+		if grep -q ^CONFIG_CTRL_IFACE_DBUS=y .config; then
+			sed -i -e s:/sbin:${sbindir}:g ${S}/dbus/fi.epitest.hostap.WPASupplicant.service
+			install -m 644 ${S}/dbus/fi.epitest.hostap.WPASupplicant.service ${D}/${datadir}/dbus-1/system-services
+		fi
+		if grep -q ^CONFIG_CTRL_IFACE_DBUS_NEW=y .config; then
+			sed -i -e s:/sbin:${sbindir}:g ${S}/dbus/fi.w1.wpa_supplicant1.service
+			install -m 644 ${S}/dbus/fi.w1.wpa_supplicant1.service ${D}/${datadir}/dbus-1/system-services
+		fi
+	fi
+
+	install -d ${D}${sysconfdir}/network/if-pre-up.d/
+	install -d ${D}${sysconfdir}/network/if-post-down.d/
+	install -d ${D}${sysconfdir}/network/if-down.d/
+	install -m 644 ${WORKDIR}/wpa_supplicant.conf ${D}${sysconfdir}
+	install -m 755 ${WORKDIR}/wpa-supplicant.sh ${D}${sysconfdir}/network/if-pre-up.d/wpa-supplicant
+	cd ${D}${sysconfdir}/network/ && \
+	ln -sf ../if-pre-up.d/wpa-supplicant if-post-down.d/wpa-supplicant
+
+	install -d ${D}/etc/default/volatiles
+	install -m 0644 ${WORKDIR}/99_wpa_supplicant ${D}/etc/default/volatiles
+}
+
+#we introduce MY_ARCH to get 'armv5te' as arch instead of the misleading 'arm' on armv5te builds
+MY_ARCH := "${PACKAGE_ARCH}"
+PACKAGE_ARCH = "${@base_contains('COMBINED_FEATURES', 'madwifi', '${MACHINE_ARCH}', '${MY_ARCH}', d)}"
+
+pkg_postinst_wpa-supplicant () {
+	# can't do this offline
+	if [ "x$D" != "x" ]; then
+		exit 1
+	fi
+
+	DBUSPID=`pidof dbus-daemon`
+
+	if [ "x$DBUSPID" != "x" ]; then
+		/etc/init.d/dbus-1 reload
+	fi
+}
diff --git a/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/99_wpa_supplicant b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/99_wpa_supplicant
new file mode 100644
index 0000000..6ff4dd8
--- /dev/null
+++ b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/99_wpa_supplicant
@@ -0,0 +1 @@
+d root root 0700 /var/run/wpa_supplicant none
diff --git a/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/defaults-sane b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/defaults-sane
new file mode 100644
index 0000000..67c4cbd
--- /dev/null
+++ b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/defaults-sane
@@ -0,0 +1,8 @@
+# Useful flags:
+#  -i <ifname>          Interface (required, unless specified in config)
+#  -D <driver>          Wireless Driver
+#  -d                   Debugging (-dd for more)
+#  -q                   Quiet (-qq for more)
+
+CONFIG="/etc/wpa_supplicant.conf"
+OPTIONS="-i eth1 -D wext"
diff --git a/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/defconfig b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/defconfig
new file mode 100644
index 0000000..4136225
--- /dev/null
+++ b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/defconfig
@@ -0,0 +1,409 @@
+# Example wpa_supplicant build time configuration
+#
+# This file lists the configuration options that are used when building the
+# hostapd binary. All lines starting with # are ignored. Configuration option
+# lines must be commented out complete, if they are not to be included, i.e.,
+# just setting VARIABLE=n is not disabling that variable.
+#
+# This file is included in Makefile, so variables like CFLAGS and LIBS can also
+# be modified from here. In most cases, these lines should use += in order not
+# to override previous values of the variables.
+
+
+# Uncomment following two lines and fix the paths if you have installed OpenSSL
+# or GnuTLS in non-default location
+#CFLAGS += -I/usr/local/openssl/include
+#LIBS += -L/usr/local/openssl/lib
+
+# Some Red Hat versions seem to include kerberos header files from OpenSSL, but
+# the kerberos files are not in the default include path. Following line can be
+# used to fix build issues on such systems (krb5.h not found).
+#CFLAGS += -I/usr/include/kerberos
+
+# Example configuration for various cross-compilation platforms
+
+#### sveasoft (e.g., for Linksys WRT54G) ######################################
+#CC=mipsel-uclibc-gcc
+#CC=/opt/brcm/hndtools-mipsel-uclibc/bin/mipsel-uclibc-gcc
+#CFLAGS += -Os
+#CPPFLAGS += -I../src/include -I../../src/router/openssl/include
+#LIBS += -L/opt/brcm/hndtools-mipsel-uclibc-0.9.19/lib -lssl
+###############################################################################
+
+#### openwrt (e.g., for Linksys WRT54G) #######################################
+#CC=mipsel-uclibc-gcc
+#CC=/opt/brcm/hndtools-mipsel-uclibc/bin/mipsel-uclibc-gcc
+#CFLAGS += -Os
+#CPPFLAGS=-I../src/include -I../openssl-0.9.7d/include \
+#	-I../WRT54GS/release/src/include
+#LIBS = -lssl
+###############################################################################
+
+
+# Driver interface for Host AP driver
+CONFIG_DRIVER_HOSTAP=y
+
+# Driver interface for Agere driver
+#CONFIG_DRIVER_HERMES=y
+# Change include directories to match with the local setup
+#CFLAGS += -I../../hcf -I../../include -I../../include/hcf
+#CFLAGS += -I../../include/wireless
+
+# Driver interface for madwifi driver
+# Deprecated; use CONFIG_DRIVER_WEXT=y instead.
+#CONFIG_DRIVER_MADWIFI=y
+# Set include directory to the madwifi source tree
+#CFLAGS += -I../../madwifi
+
+# Driver interface for ndiswrapper
+# Deprecated; use CONFIG_DRIVER_WEXT=y instead.
+#CONFIG_DRIVER_NDISWRAPPER=y
+
+# Driver interface for Atmel driver
+# CONFIG_DRIVER_ATMEL=y
+
+# Driver interface for old Broadcom driver
+# Please note that the newer Broadcom driver ("hybrid Linux driver") supports
+# Linux wireless extensions and does not need (or even work) with the old
+# driver wrapper. Use CONFIG_DRIVER_WEXT=y with that driver.
+#CONFIG_DRIVER_BROADCOM=y
+# Example path for wlioctl.h; change to match your configuration
+#CFLAGS += -I/opt/WRT54GS/release/src/include
+
+# Driver interface for Intel ipw2100/2200 driver
+# Deprecated; use CONFIG_DRIVER_WEXT=y instead.
+#CONFIG_DRIVER_IPW=y
+
+# Driver interface for Ralink driver
+#CONFIG_DRIVER_RALINK=y
+
+# Driver interface for generic Linux wireless extensions
+CONFIG_DRIVER_WEXT=y
+
+# Driver interface for Linux drivers using the nl80211 kernel interface
+CONFIG_DRIVER_NL80211=y
+CONFIG_LIBNL20=y
+
+# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver)
+#CONFIG_DRIVER_BSD=y
+#CFLAGS += -I/usr/local/include
+#LIBS += -L/usr/local/lib
+#LIBS_p += -L/usr/local/lib
+#LIBS_c += -L/usr/local/lib
+
+# Driver interface for Windows NDIS
+#CONFIG_DRIVER_NDIS=y
+#CFLAGS += -I/usr/include/w32api/ddk
+#LIBS += -L/usr/local/lib
+# For native build using mingw
+#CONFIG_NATIVE_WINDOWS=y
+# Additional directories for cross-compilation on Linux host for mingw target
+#CFLAGS += -I/opt/mingw/mingw32/include/ddk
+#LIBS += -L/opt/mingw/mingw32/lib
+#CC=mingw32-gcc
+# By default, driver_ndis uses WinPcap for low-level operations. This can be
+# replaced with the following option which replaces WinPcap calls with NDISUIO.
+# However, this requires that WZC is disabled (net stop wzcsvc) before starting
+# wpa_supplicant.
+# CONFIG_USE_NDISUIO=y
+
+# Driver interface for development testing
+#CONFIG_DRIVER_TEST=y
+
+# Include client MLME (management frame processing) for test driver
+# This can be used to test MLME operations in hostapd with the test interface.
+# space.
+#CONFIG_CLIENT_MLME=y
+
+# Driver interface for wired Ethernet drivers
+CONFIG_DRIVER_WIRED=y
+
+# Driver interface for the Broadcom RoboSwitch family
+#CONFIG_DRIVER_ROBOSWITCH=y
+
+# Driver interface for no driver (e.g., WPS ER only)
+#CONFIG_DRIVER_NONE=y
+
+# Enable IEEE 802.1X Supplicant (automatically included if any EAP method is
+# included)
+CONFIG_IEEE8021X_EAPOL=y
+
+# EAP-MD5
+CONFIG_EAP_MD5=y
+
+# EAP-MSCHAPv2
+CONFIG_EAP_MSCHAPV2=y
+
+# EAP-TLS
+CONFIG_EAP_TLS=y
+
+# EAL-PEAP
+CONFIG_EAP_PEAP=y
+
+# EAP-TTLS
+CONFIG_EAP_TTLS=y
+
+# EAP-FAST
+# Note: Default OpenSSL package does not include support for all the
+# functionality needed for EAP-FAST. If EAP-FAST is enabled with OpenSSL,
+# the OpenSSL library must be patched (openssl-0.9.8d-tls-extensions.patch)
+# to add the needed functions.
+#CONFIG_EAP_FAST=y
+
+# EAP-GTC
+CONFIG_EAP_GTC=y
+
+# EAP-OTP
+CONFIG_EAP_OTP=y
+
+# EAP-SIM (enable CONFIG_PCSC, if EAP-SIM is used)
+#CONFIG_EAP_SIM=y
+
+# EAP-PSK (experimental; this is _not_ needed for WPA-PSK)
+#CONFIG_EAP_PSK=y
+
+# EAP-PAX
+#CONFIG_EAP_PAX=y
+
+# LEAP
+CONFIG_EAP_LEAP=y
+
+# EAP-AKA (enable CONFIG_PCSC, if EAP-AKA is used)
+#CONFIG_EAP_AKA=y
+
+# EAP-AKA' (enable CONFIG_PCSC, if EAP-AKA' is used).
+# This requires CONFIG_EAP_AKA to be enabled, too.
+#CONFIG_EAP_AKA_PRIME=y
+
+# Enable USIM simulator (Milenage) for EAP-AKA
+#CONFIG_USIM_SIMULATOR=y
+
+# EAP-SAKE
+#CONFIG_EAP_SAKE=y
+
+# EAP-GPSK
+#CONFIG_EAP_GPSK=y
+# Include support for optional SHA256 cipher suite in EAP-GPSK
+#CONFIG_EAP_GPSK_SHA256=y
+
+# EAP-TNC and related Trusted Network Connect support (experimental)
+#CONFIG_EAP_TNC=y
+
+# Wi-Fi Protected Setup (WPS)
+#CONFIG_WPS=y
+
+# EAP-IKEv2
+#CONFIG_EAP_IKEV2=y
+
+# PKCS#12 (PFX) support (used to read private key and certificate file from
+# a file that usually has extension .p12 or .pfx)
+CONFIG_PKCS12=y
+
+# Smartcard support (i.e., private key on a smartcard), e.g., with openssl
+# engine.
+CONFIG_SMARTCARD=y
+
+# PC/SC interface for smartcards (USIM, GSM SIM)
+# Enable this if EAP-SIM or EAP-AKA is included
+#CONFIG_PCSC=y
+
+# Development testing
+#CONFIG_EAPOL_TEST=y
+
+# Select control interface backend for external programs, e.g, wpa_cli:
+# unix = UNIX domain sockets (default for Linux/*BSD)
+# udp = UDP sockets using localhost (127.0.0.1)
+# named_pipe = Windows Named Pipe (default for Windows)
+# y = use default (backwards compatibility)
+# If this option is commented out, control interface is not included in the
+# build.
+CONFIG_CTRL_IFACE=y
+
+# Include support for GNU Readline and History Libraries in wpa_cli.
+# When building a wpa_cli binary for distribution, please note that these
+# libraries are licensed under GPL and as such, BSD license may not apply for
+# the resulting binary.
+#CONFIG_READLINE=y
+
+# Remove debugging code that is printing out debug message to stdout.
+# This can be used to reduce the size of the wpa_supplicant considerably
+# if debugging code is not needed. The size reduction can be around 35%
+# (e.g., 90 kB).
+#CONFIG_NO_STDOUT_DEBUG=y
+
+# Remove WPA support, e.g., for wired-only IEEE 802.1X supplicant, to save
+# 35-50 kB in code size.
+#CONFIG_NO_WPA=y
+
+# Remove WPA2 support. This allows WPA to be used, but removes WPA2 code to
+# save about 1 kB in code size when building only WPA-Personal (no EAP support)
+# or 6 kB if building for WPA-Enterprise.
+#CONFIG_NO_WPA2=y
+
+# Remove IEEE 802.11i/WPA-Personal ASCII passphrase support
+# This option can be used to reduce code size by removing support for
+# converting ASCII passphrases into PSK. If this functionality is removed, the
+# PSK can only be configured as the 64-octet hexstring (e.g., from
+# wpa_passphrase). This saves about 0.5 kB in code size.
+#CONFIG_NO_WPA_PASSPHRASE=y
+
+# Disable scan result processing (ap_mode=1) to save code size by about 1 kB.
+# This can be used if ap_scan=1 mode is never enabled.
+#CONFIG_NO_SCAN_PROCESSING=y
+
+# Select configuration backend:
+# file = text file (e.g., wpa_supplicant.conf; note: the configuration file
+#	path is given on command line, not here; this option is just used to
+#	select the backend that allows configuration files to be used)
+# winreg = Windows registry (see win_example.reg for an example)
+CONFIG_BACKEND=file
+
+# Remove configuration write functionality (i.e., to allow the configuration
+# file to be updated based on runtime configuration changes). The runtime
+# configuration can still be changed, the changes are just not going to be
+# persistent over restarts. This option can be used to reduce code size by
+# about 3.5 kB.
+#CONFIG_NO_CONFIG_WRITE=y
+
+# Remove support for configuration blobs to reduce code size by about 1.5 kB.
+#CONFIG_NO_CONFIG_BLOBS=y
+
+# Select program entry point implementation:
+# main = UNIX/POSIX like main() function (default)
+# main_winsvc = Windows service (read parameters from registry)
+# main_none = Very basic example (development use only)
+#CONFIG_MAIN=main
+
+# Select wrapper for operatins system and C library specific functions
+# unix = UNIX/POSIX like systems (default)
+# win32 = Windows systems
+# none = Empty template
+#CONFIG_OS=unix
+
+# Select event loop implementation
+# eloop = select() loop (default)
+# eloop_win = Windows events and WaitForMultipleObject() loop
+# eloop_none = Empty template
+#CONFIG_ELOOP=eloop
+
+# Select layer 2 packet implementation
+# linux = Linux packet socket (default)
+# pcap = libpcap/libdnet/WinPcap
+# freebsd = FreeBSD libpcap
+# winpcap = WinPcap with receive thread
+# ndis = Windows NDISUIO (note: requires CONFIG_USE_NDISUIO=y)
+# none = Empty template
+#CONFIG_L2_PACKET=linux
+
+# PeerKey handshake for Station to Station Link (IEEE 802.11e DLS)
+CONFIG_PEERKEY=y
+
+# IEEE 802.11w (management frame protection)
+# This version is an experimental implementation based on IEEE 802.11w/D1.0
+# draft and is subject to change since the standard has not yet been finalized.
+# Driver support is also needed for IEEE 802.11w.
+#CONFIG_IEEE80211W=y
+
+# Select TLS implementation
+# openssl = OpenSSL (default)
+# gnutls = GnuTLS (needed for TLS/IA, see also CONFIG_GNUTLS_EXTRA)
+# internal = Internal TLSv1 implementation (experimental)
+# none = Empty template
+#CONFIG_TLS=openssl
+
+# Whether to enable TLS/IA support, which is required for EAP-TTLSv1.
+# You need CONFIG_TLS=gnutls for this to have any effect. Please note that
+# even though the core GnuTLS library is released under LGPL, this extra
+# library uses GPL and as such, the terms of GPL apply to the combination
+# of wpa_supplicant and GnuTLS if this option is enabled. BSD license may not
+# apply for distribution of the resulting binary.
+#CONFIG_GNUTLS_EXTRA=y
+
+# If CONFIG_TLS=internal is used, additional library and include paths are
+# needed for LibTomMath. Alternatively, an integrated, minimal version of
+# LibTomMath can be used. See beginning of libtommath.c for details on benefits
+# and drawbacks of this option.
+#CONFIG_INTERNAL_LIBTOMMATH=y
+#ifndef CONFIG_INTERNAL_LIBTOMMATH
+#LTM_PATH=/usr/src/libtommath-0.39
+#CFLAGS += -I$(LTM_PATH)
+#LIBS += -L$(LTM_PATH)
+#LIBS_p += -L$(LTM_PATH)
+#endif
+# At the cost of about 4 kB of additional binary size, the internal LibTomMath
+# can be configured to include faster routines for exptmod, sqr, and div to
+# speed up DH and RSA calculation considerably
+#CONFIG_INTERNAL_LIBTOMMATH_FAST=y
+
+# Include NDIS event processing through WMI into wpa_supplicant/wpasvc.
+# This is only for Windows builds and requires WMI-related header files and
+# WbemUuid.Lib from Platform SDK even when building with MinGW.
+#CONFIG_NDIS_EVENTS_INTEGRATED=y
+#PLATFORMSDKLIB="/opt/Program Files/Microsoft Platform SDK/Lib"
+
+# Add support for old DBus control interface
+# (fi.epitest.hostap.WPASupplicant)
+CONFIG_CTRL_IFACE_DBUS=y
+
+# Add support for new DBus control interface
+# (fi.w1.hostap.wpa_supplicant1)
+CONFIG_CTRL_IFACE_DBUS_NEW=y
+
+# Add introspection support for new DBus control interface
+#CONFIG_CTRL_IFACE_DBUS_INTRO=y
+
+# Add support for loading EAP methods dynamically as shared libraries.
+# When this option is enabled, each EAP method can be either included
+# statically (CONFIG_EAP_<method>=y) or dynamically (CONFIG_EAP_<method>=dyn).
+# Dynamic EAP methods are build as shared objects (eap_*.so) and they need to
+# be loaded in the beginning of the wpa_supplicant configuration file
+# (see load_dynamic_eap parameter in the example file) before being used in
+# the network blocks.
+#
+# Note that some shared parts of EAP methods are included in the main program
+# and in order to be able to use dynamic EAP methods using these parts, the
+# main program must have been build with the EAP method enabled (=y or =dyn).
+# This means that EAP-TLS/PEAP/TTLS/FAST cannot be added as dynamic libraries
+# unless at least one of them was included in the main build to force inclusion
+# of the shared code. Similarly, at least one of EAP-SIM/AKA must be included
+# in the main build to be able to load these methods dynamically.
+#
+# Please also note that using dynamic libraries will increase the total binary
+# size. Thus, it may not be the best option for targets that have limited
+# amount of memory/flash.
+#CONFIG_DYNAMIC_EAP_METHODS=y
+
+# IEEE Std 802.11r-2008 (Fast BSS Transition)
+#CONFIG_IEEE80211R=y
+
+# Add support for writing debug log to a file (/tmp/wpa_supplicant-log-#.txt)
+#CONFIG_DEBUG_FILE=y
+
+# Enable privilege separation (see README 'Privilege separation' for details)
+#CONFIG_PRIVSEP=y
+
+# Enable mitigation against certain attacks against TKIP by delaying Michael
+# MIC error reports by a random amount of time between 0 and 60 seconds
+#CONFIG_DELAYED_MIC_ERROR_REPORT=y
+
+# Enable tracing code for developer debugging
+# This tracks use of memory allocations and other registrations and reports
+# incorrect use with a backtrace of call (or allocation) location.
+#CONFIG_WPA_TRACE=y
+# For BSD, comment out these.
+#LIBS += -lexecinfo
+#LIBS_p += -lexecinfo
+#LIBS_c += -lexecinfo
+
+# Use libbfd to get more details for developer debugging
+# This enables use of libbfd to get more detailed symbols for the backtraces
+# generated by CONFIG_WPA_TRACE=y.
+#CONFIG_WPA_TRACE_BFD=y
+# For BSD, comment out these.
+#LIBS += -lbfd -liberty -lz
+#LIBS_p += -lbfd -liberty -lz
+#LIBS_c += -lbfd -liberty -lz
+CONFIG_TLS = gnutls
+CONFIG_GNUTLS_EXTRA=y
+CONFIG_CTRL_IFACE_DBUS=y
+CONFIG_CTRL_IFACE_DBUS_NEW=y
diff --git a/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/wpa-supplicant.sh b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/wpa-supplicant.sh
new file mode 100644
index 0000000..5c9e5d3
--- /dev/null
+++ b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/wpa-supplicant.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+
+WPA_SUP_BIN="/usr/sbin/wpa_supplicant"
+WPA_SUP_PNAME="wpa_supplicant"
+WPA_SUP_PIDFILE="/var/run/wpa_supplicant.$IFACE.pid"
+WPA_SUP_OPTIONS="-B -P $WPA_SUP_PIDFILE -i $IFACE"
+
+VERBOSITY=0
+
+
+if [ -s "$IF_WPA_CONF" ]; then
+	WPA_SUP_CONF="-c $IF_WPA_CONF"
+else
+	exit 0
+fi
+
+if [ ! -x "$WPA_SUP_BIN" ]; then
+	
+	if [ "$VERBOSITY" = "1" ]; then
+		echo "$WPA_SUP_PNAME: binaries not executable or missing from $WPA_SUP_BIN"
+	fi
+	
+	exit 1
+fi
+
+if [ "$MODE" = "start" ] ; then
+	# driver type of interface, defaults to wext when undefined
+	if [ -s "/etc/wpa_supplicant/driver.$IFACE" ]; then
+		IF_WPA_DRIVER=$(cat "/etc/wpa_supplicant/driver.$IFACE")
+	elif [ -z "$IF_WPA_DRIVER" ]; then
+		
+		if [ "$VERBOSITY" = "1" ]; then
+			echo "$WPA_SUP_PNAME: wpa-driver not provided, using \"wext\""
+		fi
+		
+		IF_WPA_DRIVER="wext"
+	fi
+	
+	# if we have passed the criteria, start wpa_supplicant
+	if [ -n "$WPA_SUP_CONF" ]; then
+		
+		if [ "$VERBOSITY" = "1" ]; then
+			echo "$WPA_SUP_PNAME: $WPA_SUP_BIN $WPA_SUP_OPTIONS $WPA_SUP_CONF -D $IF_WPA_DRIVER"
+		fi
+		
+		start-stop-daemon --start --quiet \
+			--name $WPA_SUP_PNAME --startas $WPA_SUP_BIN --pidfile $WPA_SUP_PIDFILE \
+			--  $WPA_SUP_OPTIONS $WPA_SUP_CONF -D $IF_WPA_DRIVER
+	fi
+
+	# if the interface socket exists, then wpa_supplicant was invoked successfully
+	if [ -S "$WPA_COMMON_CTRL_IFACE/$IFACE" ]; then
+	
+		if [ "$VERBOSITY" = "1" ]; then
+			echo "$WPA_SUP_PNAME: ctrl_interface socket located at $WPA_COMMON_CTRL_IFACE/$IFACE"
+		fi
+
+		exit 0
+		
+	fi
+	
+elif [ "$MODE" = "stop" ]; then
+
+	if [ -f "$WPA_SUP_PIDFILE" ]; then
+		
+		if [ "$VERBOSITY" = "1" ]; then
+			echo "$WPA_SUP_PNAME: terminating $WPA_SUP_PNAME daemon"
+		fi
+		
+		start-stop-daemon --stop --quiet \
+			--name $WPA_SUP_PNAME --pidfile	$WPA_SUP_PIDFILE
+			
+		if [ -S "$WPA_COMMON_CTRL_IFACE/$IFACE" ]; then
+			rm -f $WPA_COMMON_CTRL_IFACE/$IFACE
+		fi
+			
+		if [ -f "$WPA_SUP_PIDFILE" ]; then
+			rm -f $WPA_SUP_PIDFILE
+		fi
+	fi
+
+fi
+
+exit 0
diff --git a/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/wpa_supplicant.conf b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/wpa_supplicant.conf
new file mode 100644
index 0000000..f0c993d
--- /dev/null
+++ b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/wpa_supplicant.conf
@@ -0,0 +1,690 @@
+##### Example wpa_supplicant configuration file ###############################
+#
+# This file describes configuration file format and lists all available option.
+# Please also take a look at simpler configuration examples in 'examples'
+# subdirectory.
+#
+# Empty lines and lines starting with # are ignored
+
+# NOTE! This file may contain password information and should probably be made
+# readable only by root user on multiuser systems.
+
+# Note: All file paths in this configuration file should use full (absolute,
+# not relative to working directory) path in order to allow working directory
+# to be changed. This can happen if wpa_supplicant is run in the background.
+
+# Whether to allow wpa_supplicant to update (overwrite) configuration
+#
+# This option can be used to allow wpa_supplicant to overwrite configuration
+# file whenever configuration is changed (e.g., new network block is added with
+# wpa_cli or wpa_gui, or a password is changed). This is required for
+# wpa_cli/wpa_gui to be able to store the configuration changes permanently.
+# Please note that overwriting configuration file will remove the comments from
+# it.
+#update_config=1
+
+# global configuration (shared by all network blocks)
+#
+# Parameters for the control interface. If this is specified, wpa_supplicant
+# will open a control interface that is available for external programs to
+# manage wpa_supplicant. The meaning of this string depends on which control
+# interface mechanism is used. For all cases, the existance of this parameter
+# in configuration is used to determine whether the control interface is
+# enabled.
+#
+# For UNIX domain sockets (default on Linux and BSD): This is a directory that
+# will be created for UNIX domain sockets for listening to requests from
+# external programs (CLI/GUI, etc.) for status information and configuration.
+# The socket file will be named based on the interface name, so multiple
+# wpa_supplicant processes can be run at the same time if more than one
+# interface is used.
+# /var/run/wpa_supplicant is the recommended directory for sockets and by
+# default, wpa_cli will use it when trying to connect with wpa_supplicant.
+#
+# Access control for the control interface can be configured by setting the
+# directory to allow only members of a group to use sockets. This way, it is
+# possible to run wpa_supplicant as root (since it needs to change network
+# configuration and open raw sockets) and still allow GUI/CLI components to be
+# run as non-root users. However, since the control interface can be used to
+# change the network configuration, this access needs to be protected in many
+# cases. By default, wpa_supplicant is configured to use gid 0 (root). If you
+# want to allow non-root users to use the control interface, add a new group
+# and change this value to match with that group. Add users that should have
+# control interface access to this group. If this variable is commented out or
+# not included in the configuration file, group will not be changed from the
+# value it got by default when the directory or socket was created.
+#
+# When configuring both the directory and group, use following format:
+# DIR=/var/run/wpa_supplicant GROUP=wheel
+# DIR=/var/run/wpa_supplicant GROUP=0
+# (group can be either group name or gid)
+#
+# For UDP connections (default on Windows): The value will be ignored. This
+# variable is just used to select that the control interface is to be created.
+# The value can be set to, e.g., udp (ctrl_interface=udp)
+#
+# For Windows Named Pipe: This value can be used to set the security descriptor
+# for controlling access to the control interface. Security descriptor can be
+# set using Security Descriptor String Format (see http://msdn.microsoft.com/
+# library/default.asp?url=/library/en-us/secauthz/security/
+# security_descriptor_string_format.asp). The descriptor string needs to be
+# prefixed with SDDL=. For example, ctrl_interface=SDDL=D: would set an empty
+# DACL (which will reject all connections). See README-Windows.txt for more
+# information about SDDL string format.
+#
+ctrl_interface=/var/run/wpa_supplicant
+
+# IEEE 802.1X/EAPOL version
+# wpa_supplicant is implemented based on IEEE Std 802.1X-2004 which defines
+# EAPOL version 2. However, there are many APs that do not handle the new
+# version number correctly (they seem to drop the frames completely). In order
+# to make wpa_supplicant interoperate with these APs, the version number is set
+# to 1 by default. This configuration value can be used to set it to the new
+# version (2).
+eapol_version=1
+
+# AP scanning/selection
+# By default, wpa_supplicant requests driver to perform AP scanning and then
+# uses the scan results to select a suitable AP. Another alternative is to
+# allow the driver to take care of AP scanning and selection and use
+# wpa_supplicant just to process EAPOL frames based on IEEE 802.11 association
+# information from the driver.
+# 1: wpa_supplicant initiates scanning and AP selection
+# 0: driver takes care of scanning, AP selection, and IEEE 802.11 association
+#    parameters (e.g., WPA IE generation); this mode can also be used with
+#    non-WPA drivers when using IEEE 802.1X mode; do not try to associate with
+#    APs (i.e., external program needs to control association). This mode must
+#    also be used when using wired Ethernet drivers.
+# 2: like 0, but associate with APs using security policy and SSID (but not
+#    BSSID); this can be used, e.g., with ndiswrapper and NDIS drivers to
+#    enable operation with hidden SSIDs and optimized roaming; in this mode,
+#    the network blocks in the configuration file are tried one by one until
+#    the driver reports successful association; each network block should have
+#    explicit security policy (i.e., only one option in the lists) for
+#    key_mgmt, pairwise, group, proto variables
+ap_scan=1
+
+# EAP fast re-authentication
+# By default, fast re-authentication is enabled for all EAP methods that
+# support it. This variable can be used to disable fast re-authentication.
+# Normally, there is no need to disable this.
+fast_reauth=1
+
+# OpenSSL Engine support
+# These options can be used to load OpenSSL engines.
+# The two engines that are supported currently are shown below:
+# They are both from the opensc project (http://www.opensc.org/)
+# By default no engines are loaded.
+# make the opensc engine available
+#opensc_engine_path=/usr/lib/opensc/engine_opensc.so
+# make the pkcs11 engine available
+#pkcs11_engine_path=/usr/lib/opensc/engine_pkcs11.so
+# configure the path to the pkcs11 module required by the pkcs11 engine
+#pkcs11_module_path=/usr/lib/pkcs11/opensc-pkcs11.so
+
+# Dynamic EAP methods
+# If EAP methods were built dynamically as shared object files, they need to be
+# loaded here before being used in the network blocks. By default, EAP methods
+# are included statically in the build, so these lines are not needed
+#load_dynamic_eap=/usr/lib/wpa_supplicant/eap_tls.so
+#load_dynamic_eap=/usr/lib/wpa_supplicant/eap_md5.so
+
+# Driver interface parameters
+# This field can be used to configure arbitrary driver interace parameters. The
+# format is specific to the selected driver interface. This field is not used
+# in most cases.
+#driver_param="field=value"
+
+# Maximum lifetime for PMKSA in seconds; default 43200
+#dot11RSNAConfigPMKLifetime=43200
+# Threshold for reauthentication (percentage of PMK lifetime); default 70
+#dot11RSNAConfigPMKReauthThreshold=70
+# Timeout for security association negotiation in seconds; default 60
+#dot11RSNAConfigSATimeout=60
+
+# network block
+#
+# Each network (usually AP's sharing the same SSID) is configured as a separate
+# block in this configuration file. The network blocks are in preference order
+# (the first match is used).
+#
+# network block fields:
+#
+# disabled:
+#	0 = this network can be used (default)
+#	1 = this network block is disabled (can be enabled through ctrl_iface,
+#	    e.g., with wpa_cli or wpa_gui)
+#
+# id_str: Network identifier string for external scripts. This value is passed
+#	to external action script through wpa_cli as WPA_ID_STR environment
+#	variable to make it easier to do network specific configuration.
+#
+# ssid: SSID (mandatory); either as an ASCII string with double quotation or
+#	as hex string; network name
+#
+# scan_ssid:
+#	0 = do not scan this SSID with specific Probe Request frames (default)
+#	1 = scan with SSID-specific Probe Request frames (this can be used to
+#	    find APs that do not accept broadcast SSID or use multiple SSIDs;
+#	    this will add latency to scanning, so enable this only when needed)
+#
+# bssid: BSSID (optional); if set, this network block is used only when
+#	associating with the AP using the configured BSSID
+#
+# priority: priority group (integer)
+# By default, all networks will get same priority group (0). If some of the
+# networks are more desirable, this field can be used to change the order in
+# which wpa_supplicant goes through the networks when selecting a BSS. The
+# priority groups will be iterated in decreasing priority (i.e., the larger the
+# priority value, the sooner the network is matched against the scan results).
+# Within each priority group, networks will be selected based on security
+# policy, signal strength, etc.
+# Please note that AP scanning with scan_ssid=1 and ap_scan=2 mode are not
+# using this priority to select the order for scanning. Instead, they try the
+# networks in the order that used in the configuration file.
+#
+# mode: IEEE 802.11 operation mode
+# 0 = infrastructure (Managed) mode, i.e., associate with an AP (default)
+# 1 = IBSS (ad-hoc, peer-to-peer)
+# Note: IBSS can only be used with key_mgmt NONE (plaintext and static WEP)
+# and key_mgmt=WPA-NONE (fixed group key TKIP/CCMP). In addition, ap_scan has
+# to be set to 2 for IBSS. WPA-None requires following network block options:
+# proto=WPA, key_mgmt=WPA-NONE, pairwise=NONE, group=TKIP (or CCMP, but not
+# both), and psk must also be set.
+#
+# proto: list of accepted protocols
+# WPA = WPA/IEEE 802.11i/D3.0
+# RSN = WPA2/IEEE 802.11i (also WPA2 can be used as an alias for RSN)
+# If not set, this defaults to: WPA RSN
+#
+# key_mgmt: list of accepted authenticated key management protocols
+# WPA-PSK = WPA pre-shared key (this requires 'psk' field)
+# WPA-EAP = WPA using EAP authentication (this can use an external
+#	program, e.g., Xsupplicant, for IEEE 802.1X EAP Authentication
+# IEEE8021X = IEEE 802.1X using EAP authentication and (optionally) dynamically
+#	generated WEP keys
+# NONE = WPA is not used; plaintext or static WEP could be used
+# If not set, this defaults to: WPA-PSK WPA-EAP
+#
+# auth_alg: list of allowed IEEE 802.11 authentication algorithms
+# OPEN = Open System authentication (required for WPA/WPA2)
+# SHARED = Shared Key authentication (requires static WEP keys)
+# LEAP = LEAP/Network EAP (only used with LEAP)
+# If not set, automatic selection is used (Open System with LEAP enabled if
+# LEAP is allowed as one of the EAP methods).
+#
+# pairwise: list of accepted pairwise (unicast) ciphers for WPA
+# CCMP = AES in Counter mode with CBC-MAC [RFC 3610, IEEE 802.11i/D7.0]
+# TKIP = Temporal Key Integrity Protocol [IEEE 802.11i/D7.0]
+# NONE = Use only Group Keys (deprecated, should not be included if APs support
+#	pairwise keys)
+# If not set, this defaults to: CCMP TKIP
+#
+# group: list of accepted group (broadcast/multicast) ciphers for WPA
+# CCMP = AES in Counter mode with CBC-MAC [RFC 3610, IEEE 802.11i/D7.0]
+# TKIP = Temporal Key Integrity Protocol [IEEE 802.11i/D7.0]
+# WEP104 = WEP (Wired Equivalent Privacy) with 104-bit key
+# WEP40 = WEP (Wired Equivalent Privacy) with 40-bit key [IEEE 802.11]
+# If not set, this defaults to: CCMP TKIP WEP104 WEP40
+#
+# psk: WPA preshared key; 256-bit pre-shared key
+# The key used in WPA-PSK mode can be entered either as 64 hex-digits, i.e.,
+# 32 bytes or as an ASCII passphrase (in which case, the real PSK will be
+# generated using the passphrase and SSID). ASCII passphrase must be between
+# 8 and 63 characters (inclusive).
+# This field is not needed, if WPA-EAP is used.
+# Note: Separate tool, wpa_passphrase, can be used to generate 256-bit keys
+# from ASCII passphrase. This process uses lot of CPU and wpa_supplicant
+# startup and reconfiguration time can be optimized by generating the PSK only
+# only when the passphrase or SSID has actually changed.
+#
+# eapol_flags: IEEE 802.1X/EAPOL options (bit field)
+# Dynamic WEP key required for non-WPA mode
+# bit0 (1): require dynamically generated unicast WEP key
+# bit1 (2): require dynamically generated broadcast WEP key
+# 	(3 = require both keys; default)
+# Note: When using wired authentication, eapol_flags must be set to 0 for the
+# authentication to be completed successfully.
+#
+# proactive_key_caching:
+# Enable/disable opportunistic PMKSA caching for WPA2.
+# 0 = disabled (default)
+# 1 = enabled
+#
+# wep_key0..3: Static WEP key (ASCII in double quotation, e.g. "abcde" or
+# hex without quotation, e.g., 0102030405)
+# wep_tx_keyidx: Default WEP key index (TX) (0..3)
+#
+# peerkey: Whether PeerKey negotiation for direct links (IEEE 802.11e DLS) is
+# allowed. This is only used with RSN/WPA2.
+# 0 = disabled (default)
+# 1 = enabled
+#peerkey=1
+#
+# Following fields are only used with internal EAP implementation.
+# eap: space-separated list of accepted EAP methods
+#	MD5 = EAP-MD5 (unsecure and does not generate keying material ->
+#			cannot be used with WPA; to be used as a Phase 2 method
+#			with EAP-PEAP or EAP-TTLS)
+#       MSCHAPV2 = EAP-MSCHAPv2 (cannot be used separately with WPA; to be used
+#		as a Phase 2 method with EAP-PEAP or EAP-TTLS)
+#       OTP = EAP-OTP (cannot be used separately with WPA; to be used
+#		as a Phase 2 method with EAP-PEAP or EAP-TTLS)
+#       GTC = EAP-GTC (cannot be used separately with WPA; to be used
+#		as a Phase 2 method with EAP-PEAP or EAP-TTLS)
+#	TLS = EAP-TLS (client and server certificate)
+#	PEAP = EAP-PEAP (with tunnelled EAP authentication)
+#	TTLS = EAP-TTLS (with tunnelled EAP or PAP/CHAP/MSCHAP/MSCHAPV2
+#			 authentication)
+#	If not set, all compiled in methods are allowed.
+#
+# identity: Identity string for EAP
+# anonymous_identity: Anonymous identity string for EAP (to be used as the
+#	unencrypted identity with EAP types that support different tunnelled
+#	identity, e.g., EAP-TTLS)
+# password: Password string for EAP
+# ca_cert: File path to CA certificate file (PEM/DER). This file can have one
+#	or more trusted CA certificates. If ca_cert and ca_path are not
+#	included, server certificate will not be verified. This is insecure and
+#	a trusted CA certificate should always be configured when using
+#	EAP-TLS/TTLS/PEAP. Full path should be used since working directory may
+#	change when wpa_supplicant is run in the background.
+#	On Windows, trusted CA certificates can be loaded from the system
+#	certificate store by setting this to cert_store://<name>, e.g.,
+#	ca_cert="cert_store://CA" or ca_cert="cert_store://ROOT".
+#	Note that when running wpa_supplicant as an application, the user
+#	certificate store (My user account) is used, whereas computer store
+#	(Computer account) is used when running wpasvc as a service.
+# ca_path: Directory path for CA certificate files (PEM). This path may
+#	contain multiple CA certificates in OpenSSL format. Common use for this
+#	is to point to system trusted CA list which is often installed into
+#	directory like /etc/ssl/certs. If configured, these certificates are
+#	added to the list of trusted CAs. ca_cert may also be included in that
+#	case, but it is not required.
+# client_cert: File path to client certificate file (PEM/DER)
+#	Full path should be used since working directory may change when
+#	wpa_supplicant is run in the background.
+#	Alternatively, a named configuration blob can be used by setting this
+#	to blob://<blob name>.
+# private_key: File path to client private key file (PEM/DER/PFX)
+#	When PKCS#12/PFX file (.p12/.pfx) is used, client_cert should be
+#	commented out. Both the private key and certificate will be read from
+#	the PKCS#12 file in this case. Full path should be used since working
+#	directory may change when wpa_supplicant is run in the background.
+#	Windows certificate store can be used by leaving client_cert out and
+#	configuring private_key in one of the following formats:
+#	cert://substring_to_match
+#	hash://certificate_thumbprint_in_hex
+#	for example: private_key="hash://63093aa9c47f56ae88334c7b65a4"
+#	Note that when running wpa_supplicant as an application, the user
+#	certificate store (My user account) is used, whereas computer store
+#	(Computer account) is used when running wpasvc as a service.
+#	Alternatively, a named configuration blob can be used by setting this
+#	to blob://<blob name>.
+# private_key_passwd: Password for private key file (if left out, this will be
+#	asked through control interface)
+# dh_file: File path to DH/DSA parameters file (in PEM format)
+#	This is an optional configuration file for setting parameters for an
+#	ephemeral DH key exchange. In most cases, the default RSA
+#	authentication does not use this configuration. However, it is possible
+#	setup RSA to use ephemeral DH key exchange. In addition, ciphers with
+#	DSA keys always use ephemeral DH keys. This can be used to achieve
+#	forward secrecy. If the file is in DSA parameters format, it will be
+#	automatically converted into DH params.
+# subject_match: Substring to be matched against the subject of the
+#	authentication server certificate. If this string is set, the server
+#	sertificate is only accepted if it contains this string in the subject.
+#	The subject string is in following format:
+#	/C=US/ST=CA/L=San Francisco/CN=Test AS/emailAddress=as@example.com
+# altsubject_match: Semicolon separated string of entries to be matched against
+#	the alternative subject name of the authentication server certificate.
+#	If this string is set, the server sertificate is only accepted if it
+#	contains one of the entries in an alternative subject name extension.
+#	altSubjectName string is in following format: TYPE:VALUE
+#	Example: EMAIL:server@example.com
+#	Example: DNS:server.example.com;DNS:server2.example.com
+#	Following types are supported: EMAIL, DNS, URI
+# phase1: Phase1 (outer authentication, i.e., TLS tunnel) parameters
+#	(string with field-value pairs, e.g., "peapver=0" or
+#	"peapver=1 peaplabel=1")
+#	'peapver' can be used to force which PEAP version (0 or 1) is used.
+#	'peaplabel=1' can be used to force new label, "client PEAP encryption",
+#	to be used during key derivation when PEAPv1 or newer. Most existing
+#	PEAPv1 implementation seem to be using the old label, "client EAP
+#	encryption", and wpa_supplicant is now using that as the default value.
+#	Some servers, e.g., Radiator, may require peaplabel=1 configuration to
+#	interoperate with PEAPv1; see eap_testing.txt for more details.
+#	'peap_outer_success=0' can be used to terminate PEAP authentication on
+#	tunneled EAP-Success. This is required with some RADIUS servers that
+#	implement draft-josefsson-pppext-eap-tls-eap-05.txt (e.g.,
+#	Lucent NavisRadius v4.4.0 with PEAP in "IETF Draft 5" mode)
+#	include_tls_length=1 can be used to force wpa_supplicant to include
+#	TLS Message Length field in all TLS messages even if they are not
+#	fragmented.
+#	sim_min_num_chal=3 can be used to configure EAP-SIM to require three
+#	challenges (by default, it accepts 2 or 3)
+# phase2: Phase2 (inner authentication with TLS tunnel) parameters
+#	(string with field-value pairs, e.g., "auth=MSCHAPV2" for EAP-PEAP or
+#	"autheap=MSCHAPV2 autheap=MD5" for EAP-TTLS)
+# Following certificate/private key fields are used in inner Phase2
+# authentication when using EAP-TTLS or EAP-PEAP.
+# ca_cert2: File path to CA certificate file. This file can have one or more
+#	trusted CA certificates. If ca_cert2 and ca_path2 are not included,
+#	server certificate will not be verified. This is insecure and a trusted
+#	CA certificate should always be configured.
+# ca_path2: Directory path for CA certificate files (PEM)
+# client_cert2: File path to client certificate file
+# private_key2: File path to client private key file
+# private_key2_passwd: Password for private key file
+# dh_file2: File path to DH/DSA parameters file (in PEM format)
+# subject_match2: Substring to be matched against the subject of the
+#	authentication server certificate.
+# altsubject_match2: Substring to be matched against the alternative subject
+#	name of the authentication server certificate.
+#
+# fragment_size: Maximum EAP fragment size in bytes (default 1398).
+#	This value limits the fragment size for EAP methods that support
+#	fragmentation (e.g., EAP-TLS and EAP-PEAP). This value should be set
+#	small enough to make the EAP messages fit in MTU of the network
+#	interface used for EAPOL. The default value is suitable for most
+#	cases.
+#
+# EAP-PSK variables:
+# eappsk: 16-byte (128-bit, 32 hex digits) pre-shared key in hex format
+# nai: user NAI
+#
+# EAP-PAX variables:
+# eappsk: 16-byte (128-bit, 32 hex digits) pre-shared key in hex format
+#
+# EAP-SAKE variables:
+# eappsk: 32-byte (256-bit, 64 hex digits) pre-shared key in hex format
+#	(this is concatenation of Root-Secret-A and Root-Secret-B)
+# nai: user NAI (PEERID)
+#
+# EAP-GPSK variables:
+# eappsk: Pre-shared key in hex format (at least 128 bits, i.e., 32 hex digits)
+# nai: user NAI (ID_Client)
+#
+# EAP-FAST variables:
+# pac_file: File path for the PAC entries. wpa_supplicant will need to be able
+#	to create this file and write updates to it when PAC is being
+#	provisioned or refreshed. Full path to the file should be used since
+#	working directory may change when wpa_supplicant is run in the
+#	background. Alternatively, a named configuration blob can be used by
+#	setting this to blob://<blob name>
+# phase1: fast_provisioning=1 option enables in-line provisioning of EAP-FAST
+#	credentials (PAC)
+#
+# wpa_supplicant supports number of "EAP workarounds" to work around
+# interoperability issues with incorrectly behaving authentication servers.
+# These are enabled by default because some of the issues are present in large
+# number of authentication servers. Strict EAP conformance mode can be
+# configured by disabling workarounds with eap_workaround=0.
+
+# Example blocks:
+
+# Simple case: WPA-PSK, PSK as an ASCII passphrase, allow all valid ciphers
+network={
+	ssid="simple"
+	psk="very secret passphrase"
+	priority=5
+}
+
+# Same as previous, but request SSID-specific scanning (for APs that reject
+# broadcast SSID)
+network={
+	ssid="second ssid"
+	scan_ssid=1
+	psk="very secret passphrase"
+	priority=2
+}
+
+# Only WPA-PSK is used. Any valid cipher combination is accepted.
+network={
+	ssid="example"
+	proto=WPA
+	key_mgmt=WPA-PSK
+	pairwise=CCMP TKIP
+	group=CCMP TKIP WEP104 WEP40
+	psk=06b4be19da289f475aa46a33cb793029d4ab3db7a23ee92382eb0106c72ac7bb
+	priority=2
+}
+
+# Only WPA-EAP is used. Both CCMP and TKIP is accepted. An AP that used WEP104
+# or WEP40 as the group cipher will not be accepted.
+network={
+	ssid="example"
+	proto=RSN
+	key_mgmt=WPA-EAP
+	pairwise=CCMP TKIP
+	group=CCMP TKIP
+	eap=TLS
+	identity="user@example.com"
+	ca_cert="/etc/cert/ca.pem"
+	client_cert="/etc/cert/user.pem"
+	private_key="/etc/cert/user.prv"
+	private_key_passwd="password"
+	priority=1
+}
+
+# EAP-PEAP/MSCHAPv2 configuration for RADIUS servers that use the new peaplabel
+# (e.g., Radiator)
+network={
+	ssid="example"
+	key_mgmt=WPA-EAP
+	eap=PEAP
+	identity="user@example.com"
+	password="foobar"
+	ca_cert="/etc/cert/ca.pem"
+	phase1="peaplabel=1"
+	phase2="auth=MSCHAPV2"
+	priority=10
+}
+
+# EAP-TTLS/EAP-MD5-Challenge configuration with anonymous identity for the
+# unencrypted use. Real identity is sent only within an encrypted TLS tunnel.
+network={
+	ssid="example"
+	key_mgmt=WPA-EAP
+	eap=TTLS
+	identity="user@example.com"
+	anonymous_identity="anonymous@example.com"
+	password="foobar"
+	ca_cert="/etc/cert/ca.pem"
+	priority=2
+}
+
+# EAP-TTLS/MSCHAPv2 configuration with anonymous identity for the unencrypted
+# use. Real identity is sent only within an encrypted TLS tunnel.
+network={
+	ssid="example"
+	key_mgmt=WPA-EAP
+	eap=TTLS
+	identity="user@example.com"
+	anonymous_identity="anonymous@example.com"
+	password="foobar"
+	ca_cert="/etc/cert/ca.pem"
+	phase2="auth=MSCHAPV2"
+}
+
+# WPA-EAP, EAP-TTLS with different CA certificate used for outer and inner
+# authentication.
+network={
+	ssid="example"
+	key_mgmt=WPA-EAP
+	eap=TTLS
+	# Phase1 / outer authentication
+	anonymous_identity="anonymous@example.com"
+	ca_cert="/etc/cert/ca.pem"
+	# Phase 2 / inner authentication
+	phase2="autheap=TLS"
+	ca_cert2="/etc/cert/ca2.pem"
+	client_cert2="/etc/cer/user.pem"
+	private_key2="/etc/cer/user.prv"
+	private_key2_passwd="password"
+	priority=2
+}
+
+# Both WPA-PSK and WPA-EAP is accepted. Only CCMP is accepted as pairwise and
+# group cipher.
+network={
+	ssid="example"
+	bssid=00:11:22:33:44:55
+	proto=WPA RSN
+	key_mgmt=WPA-PSK WPA-EAP
+	pairwise=CCMP
+	group=CCMP
+	psk=06b4be19da289f475aa46a33cb793029d4ab3db7a23ee92382eb0106c72ac7bb
+}
+
+# Special characters in SSID, so use hex string. Default to WPA-PSK, WPA-EAP
+# and all valid ciphers.
+network={
+	ssid=00010203
+	psk=000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f
+}
+
+
+# IEEE 802.1X/EAPOL with dynamically generated WEP keys (i.e., no WPA) using
+# EAP-TLS for authentication and key generation; require both unicast and
+# broadcast WEP keys.
+network={
+	ssid="1x-test"
+	key_mgmt=IEEE8021X
+	eap=TLS
+	identity="user@example.com"
+	ca_cert="/etc/cert/ca.pem"
+	client_cert="/etc/cert/user.pem"
+	private_key="/etc/cert/user.prv"
+	private_key_passwd="password"
+	eapol_flags=3
+}
+
+
+# LEAP with dynamic WEP keys
+network={
+	ssid="leap-example"
+	key_mgmt=IEEE8021X
+	eap=LEAP
+	identity="user"
+	password="foobar"
+}
+
+# Plaintext connection (no WPA, no IEEE 802.1X)
+network={
+	ssid="plaintext-test"
+	key_mgmt=NONE
+}
+
+
+# Shared WEP key connection (no WPA, no IEEE 802.1X)
+network={
+	ssid="static-wep-test"
+	key_mgmt=NONE
+	wep_key0="abcde"
+	wep_key1=0102030405
+	wep_key2="1234567890123"
+	wep_tx_keyidx=0
+	priority=5
+}
+
+
+# Shared WEP key connection (no WPA, no IEEE 802.1X) using Shared Key
+# IEEE 802.11 authentication
+network={
+	ssid="static-wep-test2"
+	key_mgmt=NONE
+	wep_key0="abcde"
+	wep_key1=0102030405
+	wep_key2="1234567890123"
+	wep_tx_keyidx=0
+	priority=5
+	auth_alg=SHARED
+}
+
+
+# IBSS/ad-hoc network with WPA-None/TKIP.
+network={
+	ssid="test adhoc"
+	mode=1
+	proto=WPA
+	key_mgmt=WPA-NONE
+	pairwise=NONE
+	group=TKIP
+	psk="secret passphrase"
+}
+
+
+# Catch all example that allows more or less all configuration modes
+network={
+	ssid="example"
+	scan_ssid=1
+	key_mgmt=WPA-EAP WPA-PSK IEEE8021X NONE
+	pairwise=CCMP TKIP
+	group=CCMP TKIP WEP104 WEP40
+	psk="very secret passphrase"
+	eap=TTLS PEAP TLS
+	identity="user@example.com"
+	password="foobar"
+	ca_cert="/etc/cert/ca.pem"
+	client_cert="/etc/cert/user.pem"
+	private_key="/etc/cert/user.prv"
+	private_key_passwd="password"
+	phase1="peaplabel=0"
+}
+
+# Example of EAP-TLS with smartcard (openssl engine)
+network={
+	ssid="example"
+	key_mgmt=WPA-EAP
+	eap=TLS
+	proto=RSN
+	pairwise=CCMP TKIP
+	group=CCMP TKIP
+	identity="user@example.com"
+	ca_cert="/etc/cert/ca.pem"
+	client_cert="/etc/cert/user.pem"
+
+	engine=1
+
+	# The engine configured here must be available. Look at
+	# OpenSSL engine support in the global section.
+	# The key available through the engine must be the private key
+	# matching the client certificate configured above.
+
+	# use the opensc engine
+	#engine_id="opensc"
+	#key_id="45"
+
+	# use the pkcs11 engine
+	engine_id="pkcs11"
+	key_id="id_45"
+
+	# Optional PIN configuration; this can be left out and PIN will be
+	# asked through the control interface
+	pin="1234"
+}
+
+# Example configuration showing how to use an inlined blob as a CA certificate
+# data instead of using external file
+network={
+	ssid="example"
+	key_mgmt=WPA-EAP
+	eap=TTLS
+	identity="user@example.com"
+	anonymous_identity="anonymous@example.com"
+	password="foobar"
+	ca_cert="blob://exampleblob"
+	priority=20
+}
+
+blob-base64-exampleblob={
+SGVsbG8gV29ybGQhCg==
+}
+
+
+# Wildcard match for SSID (plaintext APs only). This example select any
+# open AP regardless of its SSID.
+network={
+	key_mgmt=NONE
+}
diff --git a/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/wpa_supplicant.conf-sane b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/wpa_supplicant.conf-sane
new file mode 100644
index 0000000..c91ffe0
--- /dev/null
+++ b/multitech/recipes/wpa-supplicant/wpa-supplicant-1.0/wpa_supplicant.conf-sane
@@ -0,0 +1,7 @@
+ctrl_interface=/var/run/wpa_supplicant
+ctrl_interface_group=0
+update_config=1
+
+network={
+        key_mgmt=NONE
+}
diff --git a/multitech/recipes/wpa-supplicant/wpa-supplicant_1.0.bb b/multitech/recipes/wpa-supplicant/wpa-supplicant_1.0.bb
new file mode 100644
index 0000000..32fc4dd
--- /dev/null
+++ b/multitech/recipes/wpa-supplicant/wpa-supplicant_1.0.bb
@@ -0,0 +1,6 @@
+require wpa-supplicant-1.0.inc
+
+PR = "${INC_PR}.0"
+
+SRC_URI[md5sum] = "8650f6aa23646ef634402552d0669640"
+SRC_URI[sha256sum] = "91d41d473a5aafa2e25dd6577ebda975c4d4a3188850a53e31feaf7c04482b9c"